Studies & Researches

I want to know God's thoughts...the rest are details.
Albert Einstein

Life is good for only two things, discovering mathematics and teaching mathematics.
Siméon Denis Poisson

Er tut das Notwendige, das Not wendet.
Lao Tze

Why Science?

Why do I plan to return to Universities or institutes for scientific researches?

The main reason of this fundamental change of my life and career is my firm belief that only the acquaintance with science and studies of the Nature can give me some sort of satisfaction and happiness. In my childhood, I have always been thinking about becoming a top scientist and this is still my unrealized dream. I am thirsty to learn everything about the Nature and her principles. All branches of sciences are attracting me – mathematics, physics, chemistry…. When dived into the realm of science, I forget the rest of the world.

Secondly, I’ve found the industry, commerce and politics all full of crimes, evils, lies, corruption and injustice (in fact they are synonyms) , and I hate all these, therefore, after so many years there, I want to keep myself distant away from them and concentrate myself on pure scientific researches.

Thirdly, my personality is very fit for scientific researches. Although working in the industry and business over the last two decades, I am still maintaining my habit to learn new sciences every day without interruption. My reading and study capability is unique. Each day I might read more than 100 pages of books of various kinds. I am able to read papers in English, German and French and I am still improving my Russian.

And lastly, I should have been among the top scientists if I have accepted the Ph.D studies I won from several European and N. American universities such as University of Glasgow (gas turbine combustion), University of Paris (surface chemistry), Laval University, and universities of Germany and other countries during 1991-1992 shortly after graduation as a master of science. I was unable to attend these universities because of private reasons Further in 1996, I was nearly admitted by Harvard to pursue a MPA when my former boss told me that the job at Alstom was worth more than a Harvard MPA, a wrong judgment of course.

For short, only a scientific career can fulfill my dream of lifetime endeavors.

Childhood Dreams

As a child, I dreamed to become Einstein No 2. And still this is my lifetime goal. In any case I shall keep myself competitive technically and scientifically in one way or another. Unfortunately I didn’t continue with my Ph.D. studies at one o2017-12-20. My then girlfriend was a Taiwanese and her English or German or French was NULL, therefore I gave up my doctoral study plan and instead got a job in Taiwan (Bechtel’s joint venture with the Ministry of Science in Taiwan). I also didn’t go to work in Taiwan due to dramatical change later on.

Nevertheless, I have been able to pursue a master study of thermophysics at one of the best universities in China, have learned four or five foreign languages, paving the way for to acquire information of the outside world without any difficulty and obstacle from any organizations. I have also learned almost all software and Internet technologies, enabling me design websites and related functions, so that I may promote my business without a third hand. Of course I’ve also learned a lot of other stuff, some are still useful, the majority is sleeping forever.

Current Studies (2017--)

After a decade of researches and studies on other topics, I am now resctricting my scope of academic activities to the following three areas. That will never be changed, unless there is good reason to do so.

IC Technologies

VLSI is the most important technology of the world today and tomorrow, and this is the reason I have chosen it as my research focus in relation with math, particularly graph theory.

Next Generations of Integrated Circuits

Nowadays CMOS based VLSI technology has reached its limits, therefore I will no more follow the silicon based IC technology, but the upcoming new promising computation circuits with radically new physics and chemistry and even biological fundamentals. But at the moment there is no sight of breakthrough. Just follow me to find out where this great leap will come true.

I am currently focusing on quantum circuits as I did two or three years ago.

Earlier I was involved in a lot of the upcoming techniques, such as the ones below:

  • Quantum circuits
  • Spin based circuits
  • Graphene FETs
  • Nano IC technologies
  • DNA chips
  • Cellular chips
  • Gallium
  • Germanium
  • Indium
  • Molecular chips
  • Membrane chips
  • Molybdenium chips
  • Neural computer
  • Photonic chips
  • Resonant tunneling IC
  • Reversible computing
  • Single electron devices
  • Strained silicon chips
  • Superconducting chips
  • 3D IC

Unfortunately there is no sign that any of them can replace silicon in the nearest future, therefore we have to live now a time when IC development will be stagnated or at least slowing down. No major speed up of CPU is seen over the last years.

You may also find some of the latest development on my another website here: Super IC Technologies.

Specific, Silicon Based Integrated Circuits

Once upon a time I was also interested in different kinds of chip architectures such as the following:

  • AMS - analog/mixed-signal
  • ASAP - asynchronous array of simple processors
  • ASIC
  • ASIP Application Specific Instruction-Set Processors
  • CMP - chip multi processors
  • DSP - digital signal processor
  • FPGA ASIC
  • GPU - graphics processing unit
  • MCM - multichip module
  • MCP - multi-core processors
  • MPSOC - multiprocessor system-on-chip
  • NOC- Network-on-chip (noc)
  • OCN - on-chip networks
  • Pipelining
  • Reconfigurable
  • POC - Process on-chip
  • PSOC - programmable system-on-chip
  • SOC - system-on-chip
  • SOI - silicon-on-insulator
  • SOP - system-on-package
  • SOPC - system-on-a-programmable chip

I really am confused by soo many variations of the silicon integrated circuits and have now not enough time to follow up all these technologies, but from time to time I may still come back to some of them, particularly FPGA architecture, and SOC as well.

My Hardware Monitoring IC Design Project

But before a new generation of IC technology can be brought to life, I still have to deal with traditional, silicon-based IC technologies. For this reason I am now also doing some design work - for example, I am designing a PC harware monitoring IC based on some of the popular hardware monitoring models from companies like ITE, Nuvoton and Winbond. But it will take me long time to finish the project, as this design is just my hobby and part time work, without any supports from the industry and commerce. If some one can finance my design, the pace will be accelerated and quality will be improved, though.

Old, Soon-to-be-absolete IC Technologies

Apart from the above design project, I am of course also studying basic IC technologies as a followup of my research mission set a couple of years ago. I have read quite a bunch of entry level IC books downloaded from the Web, like the one titled

"CMOS DIGITAL INTEGRATED CIRCUITS - Analysis and Design"

co-authored by SUNG-MO (STEVE) KANG and YUSUF LEBLEBIGI. But sometimes I am missing the technical details of the CMOS structure and I-V characteristics. Never mind, though, because I don't mean to make a CMOS circuits myself, but to make me sufficiently familiar with the design process, therefore understanding CMOS details is not essential and critical.

?

Graph theory and related mathematics

Initially graph theory was studied for the sake of IC design and technologies, for at that time I was thinking that

1) I shall choose only mathematics as my research orientation because for physical sciences I have to means to carry out their studies and

2) and secondly those maths that are related to the most important technologies of our time - which is IC technology undoubtedly.

Therefore by 2014 I have decided to concentrate my future research of graph theory for the IC technology.

But in between I have no chance with the IC industry and academia, and what's more important is that, after the death of my mother, I don't need to keep my previous ambitious plan and therefore I need to cut short my research scale, thus, after more than 600 days of considerations and reluctance, I have decided to stop IC related graph research and focus on pure graph theory and related sciences such as

  • Algebra
  • Combinatorial optimization
  • Discrete math
  • Operations researches

and some of my other interests in math such as

  • cryptography,
  • differential equations,
  • probability,
  • functional,
  • number theory, and
  • numerical analysis.

In 2014 I have submitted a research program to the US National Science Foundation called Graph Theoretical Applications to VLSI Design, but it was not approved.

In the same year I have written a paper called Hypergraph modeling for FPGAs – a Preliminary Investigation, but not published.

My current studies and writting are

1) about TSP and its variants VRP - Vehicle Routing Problem and

2) graph embedding - starting with my indepth studies of graph representation i.e. graph data structure in computer.

But operations research will also be on my agenda, at least for the time being.

My aim of the studies is threefold:

  • 1) to investigate in full scale which graph data structures are there
  • 2) to find out which software, programs and codes are there to handle the computation of graph representation and finally
  • 3) to improve the existing algorithms and codes to speed up the graph data processing in computer

More information about my Graph Theory and Related Math Studies please read this file: math.htm

Web and IT Technologies

My latest IT technological activities is the development of web scraping scripts written in Python and Java for my own use - searching emails, web links and many other stuff from the web. I have also explored with other programming languages such as C/C++/C#, VB/.Net, rugby, go language, PHP, node.js, perl, R, swift, delphi, erlang, scala etc, but finally I've decided only to use Java and Python, for these two are the most popular web scraping language, particularly python. But I am not satisfied with python and Java for their speed. I use some of the 3rd party packages for the development of codes, such as scrapy in python and crawler4j in Java.

My other efforts in software cracking or better named reverse engineering are proven to be a more hard task.

Another activities related to IT and web is about privacy and secrecy in Internet life, where there are needs to overcome of censorship imposed by some regimes and to keep yourself safe while surfing the web. I started to investigate into this area as early as 2009 and I have spent hundreds or even thousands of hours trying to circumvent the filtering and protections measures. It is very difficult. My conclusion is that if the regime wants to block you, you have no way to come out of it.

More pls refer to this file.

Languages

I was able to use 5 languages at 20 and since then I have never stopped a single day learning these languages. And sometime around 2006 I've decided to expand my language skills to include the most important ones such as Greek, Latin, and Hebrew to my language skill pools. I have managed to revive my Russian which was forgotten long ago and now I am again able to read some simple books. I've nearly completed the basics of Greek, Hebrew and Latin likewise. Again I have recovered my Esperanto to almost at the same level of my 1980's. More information about my language studies consult this document.

But something happend and which forced me to stop all of them except English.

First, most importantly, is the unexpected death of my mother last year (2016). After 600 days of thinking I have decided that it is not necessaory nor useful to keep the original study plan, incl. those of languages, therefore I decided to give up all languages except English which is anyway useful in all of my life aspects.

And just a couple of days ago, I have again tried to contact the German and French agencies, governments and organizations to make some kinds of connections with regards of my literature studies activities as well as my biography writting plan of my mother in their languages - for I am able to write in German and French quitely fluently, albeit not as good as in English. But all of my hundreds of emails or site submittals were ignored. They simply did not respond to my queries, just like what they have done to me 10 years ago, when I have contacted their governments and organizations to help me get out of China, because I am under strict supervision as a person with democratic views.

Therefore, I've determined from now on, I will never touch German, French and all other languages except English. I won'd make detailed reasoning here but it's really disappointing what the socalled democratic West has done to me. In my mind there is no true democracy in this world at all. I will explain my view in another place.

More about my English language and literature studies please read this document.

A Trial Period (2006-2016)

Since 2006, after the death of my father, people have persuaded me to do something to contribute to the society and not to waste my talents. Over this time period, I have tried many areas of researches and studies, which can be divided into: math, thermodynamics, fluiddynamics, solar physics, cryptography and Internet security. Over that period of time (2006-2013), I have read tens of thousands of pages of all kinds of papers and books, and drafted a number of books and papers as well (the total number is never calculated but is easily over 200). On this website I have just shown those survived, because whe I decided to focus only on math for chip technology - which is now and will be forever my research direction - I have removed all those I have read before and as a result, only a few were able to be kep alive since they were backed up in my computer at earlier time.

And in the future, I will more or less concentrate on mathematics, particularly those related to information technology - and now mathematics for chip technology.

(The above statement and plan was given up since the death of my mother in March 2016. And now only graph theory and a little math studies remain to be among my study menu, all others are given up. No books and papers will be written, nor will be any published or otherwise publicized. Another reasons is the refusal of the academic communities of my willingness ot do my researches there.)

Previous Studies and Researches

Over the last years I’ve completed my master degree at one of the best universities in China, acquired 7 or 8 foreign languages, acquired wide spectrum of knowledge in power, energy, IT and Internet, aviation and other industries. My knowledge base is now mainly on three pillars – math, IT and languages.

However, over the past years I've been intensively engaged in studies and researches in different fields, centered around thermal science, solar technology and Internet technologies.

Here below are a little more details of areas of my past studies:

  1. Mathematics – Combinatorics, numer theory, numerical computation, functional analysis ...
  2. Fluiddynamics - Micro/Nano Flows, CFD?- computational fluid dynamics
  3. Thermal Physics & Thermodynamics - Nanothermodynamics, Thermodynamics Of Cancers, Mesoscopic Thermodynamics (Thermodynamics Of Small Structures), Thermodynamics & Thermophysics Of Life, Cosmic Thermodynamics Or Thermodynamics Of The Universe, Solar Thermodynamics & Thermophysics, Thermodynamics And Thermophysics In Solar Radiation And Measurement, Thermodynamics Of Solar Energy Systems, Solar Technology, Industry And Applications
  4. Solar Physics, Solar Radiation, Solar Aviation And Aerospace, Solar Photovoltaics

And in the future, I will more or less concentrate on graph theory andperhaps some interesting IT technologies for my own use and fun only.

Below is some documentation about my studies over the last years:

  • VLSI
  • Web and IT
  • math
  • graph theory
  • languages
  • thermodynamics
  • others

My Writing

My writing is of gigantic nature. Thousands of study notes were prepared during the last 10 years alone, and more than 200 notes were written which are publishable if I will. Here is a list of my writing as well as a descrption of how I am writing my books and papers.

The pdf file - WhatsWrittenSince2003.pdf looks better.

And here is the document lists (document_list.pdf) based on which I have drafted the above study notes.

Research Methods

There are people who have worked on how to make scientific discoveries and have written tons of books and papers and invented millions of methods to improve to scientific finding capacity.

However, scientific finding is basically a luxurious job: when you have enough time and money, you can make new things to become reality, and if you're poor and too busy, you have no chance at all, regardless if you have learned all these methods or not. I know combinatorial techniques are the most effective ones.

Problems
Occasionally I would write down what I have in my mind about new ideas of a certain scientific topic. But I have no time to tackle them yet. See Problems.doc and Problems1.doc

Scientists

As a result of my previous researches and studies, I have compiled a number of lists of worldwide scientists, in China and elsewhere, ancient and contemporary, in the fields of my interests. I have read some books and papers from some of them, I have also contacted some of them for research position by them. None was willing to accept me though.

The Greatest Works

These are the greatest scientific and humanity works ever written in the history of humans. I have planned to read some of the most important but somehow I could not realize my plan because of my daily burden.

Funding my Researches

There was days when I fancied that someone would provide some capital for my scientific activities either researches or writing. But none have showed enough willingness.

Then suddenly, on Sept 13, 2014, a certain Mr Kenneth Whang, Program Director, Division of Information and Intelligent Systems, National Science Foundation sent me an email for the call of proposals for the Collaborative Research in Computational Neuroscience program. I was wondering how did he know that I am working on this subject and how did he get my email address. I can remember that I ever have left my email address to NSF site. And how did he get my email address is still a secret. Nevertheless, I did have some kind of studies of computation, but in fluiddynamics and thermodynamics but not neuroscience. I did have some population with the US government, when I was quoted as a solar expert by US National Renewable Energy Labs under the Ministry of Energy during 2005-2007.

But his email aroused my extinguished interest in NSF, and I decided to seek a funding from there. Therefore I have registered at NSF and prepared and submitted my application for funding package today (2014-09-17) . It took me 3 days to do so. My version of Chinese PDF reader has some defect so that the first submittals were failed and I have to switch to English version and change a bit of the contents, and finally the submission was done OK. Now I have to wait for the review results.

Education

I hold a master of engineering degree in thermal science from one of the top Chinese University in Shanghai. My major studies were turbines (steam and aeroderivative), boilers, combustion engines, and advanced thermal physics.

I was once one of the hardest learning students of the university. I was possibly the first student entering the door of the University Library in the morning and the last who left the library in the evening.

I was in one of the four best classes of the University when accepted by the university – the four were the mathematics, physics, chemical and applied mechanics where I was.

But I didn’t stay there for long – only one semester, then the university asked me and several other classmates to transfer to the socalled “German Class” of two hundreds. The German Classes were formed to learn a year of German and then these students chosen from around all departments of the university will be sent to Germany to continue their studies in Germany, as part of the bilateral culture exchange. Of course, I didn’t know the background and paid little attention to the class. I also didn’t like foreign languages at all, as I considered them as the courses for women only, and men shall learn physics and other complicated science and technology. Women are more talkative than men, they deserve the language studies, but men not, especially I am very quiet. Therefore during the early years I didn’t learn hard enough so that I’ve missed a chance to go to Germany to continue my career.

However, my interest in foreign languages was aroused only two or three years after.

During my stay there I have studied not only the areas of my major, but all other sciences and technologies, arts, culture, religion, politics, economy, finance, in one word, every I can find on the library shelves. I was very thirsty of knowledge and studied deep into the night every day, so that my health was quite damaged.

During my studies, I have also developed my own thinking, my own way of working and living as well as my independence of anyone else. My working ability was also developed.

After the postgraduate studies I was also admitted to PhD research programs of several well-known universities in the US, UK, Germany, France and Canada (such as Université de Pierre et Marie Curie in Paris (University of Paris VII), Université de Provence, University of Glasgow, Université Laval , Universität Gesamthochschule Essen and lastly quasi admitted into MPA program at Harvard etc). but these plans were given up due to an engagement with my then girlfriend.

And during the 2008-2011 period I have again tried to reenter the universities for either a PhD study or direct researches on various topics at Nanyang University of Technology and Zhejiang University, however, these efforts yielded no results, and hence I have now completely shunned away from the academic communities except with my own studies of computational number theory.

This file:Education.htm gives you a global picture of my career related records.

Complete Documentation

This file Studies.htm gives you a global picture of my studies and researches or consult the complete currently valid directory listing (updated a couple of days ago as of the date when this essay was written) for an overall view.
For some additional information about my academic activities you may also consult this document.


Untitled Document

Languages

since 1976-9-1

I have spent billions of hours on language studies, from Greek to Hebrew, eight in all. See languages.htm and lang.chm for some details.

English Literature & Scientists

I've read lots of English novels, essays, poems etc. Earlier I have read some of Shakespere's drama, and currently I am reading the following:

English Literature

Ellison: Invisible Man p451

406

The relations between whites and blacks were so tense at that time that one can hardly imagine how America is evolved into a civilized and "democratic" society now.

000Lawrence Sons and Lovers p641.pdf

601

p375
A son’s my son till he takes him a wife,But my daughter’s my daughter the whole of her life.

Here below some of the romans I've finished reading and some quotes from them:

Aesop Aesop’s Fables

Sorrow not over what is lost forever
‘Never trust the advice of a man in difficulties.’

Alcott Little Women

... he practiced what he preached, having waited patiently thirty years for fruit of his own to ripen, and being in no haste to gather it even now when it was sweet and mellow.

... the brave, tenderhearted little lads, who still love their mothers better than themselves and are not ashamed to own it. Laurie

... for marriage, they say, halves one’s rights and doubles one’s duties.

Andersen Andersen’s Fairy Tales

Caroll Alice’s Adventures in Wonderland

Defoe Robinson Crusoe

okokok

Dickens: Great Expectations

It seems that owing some properties was a great expectation at that time.

Finished reading in Jan 18, 2018

Hugo Les Miserables

Kafka The Trial

Lawrence Sons and Lovers
A son’s my son till he takes him a wife,But my daughter’s my daughter the whole of her life.

More Utopia

Plato thinks that nations will be happy when either philosophers become kings or kings become philosophers.

Those are romans I have started to read but interrupted somehow:

XXXXXXXXXXXXXXXXX
Dostoevsky Crime and Punishment p767
20

XXXXXXXXXXXXXXXXX
Dostoevsky The Brothers Karamazov p1313
11

XXXXXXXXXXXXXXXXX
Dostoyevsky The Idiot p913
11

XXXXXXXXXXXXXXXXX
Dumas The Three Musketeers p945
151

Eliot Middlemarch p1193
154

XXXXXXXXXXXXXXXXX
Fitzgerald The Great Gatsby p193.pdf
95

XXXXXXXXXXXXXXXXX
Flaubert Madame Bovary p457
26

Grimm Grimms’ Fairy Tales p373
10

James The Portrait of a Lady p837
148

XXXXXXXXXXXXXXXXX
Journey to the West
5

Joyce Ulysses p1047
8

XXXXXXXXXXXXXXXXX
Kafka The Castle p318
82

okokok
Kafka The Trial p271

Lawrence Lady Chatterly’s Lover p447
24

A relatively exhaustive listing of some of the English literature I am planning to read over the next years:

English studies

English studies (pdf)

English literature sites

The simple text navigation file.

The html navigation file.

Some of the English literature sites I will visit from time to time:

http://www.americanliterature.com/

The Scarlet Letter by Nathaniel Hawthorne

https://americanliterature.com/author/nathaniel-hawthorne/book/the-scarlet-letter/the-custom-house

http://www.biographyonline.net/

https://www.englishforum.ch/

https://www.gutenberg.org/

http://www.languageforexchange.com/

http://literarylondon.org/

http://www.literature.at/

Literature.org - The Online Literature Library

www.literature.org/

http://www.literaturecircles.com/

http://www.literaturecollection.com/

http://www.literaturejunction.com/

with forums

http://www.literatureproject.com/

http://www.literature-study-online.com/

Winners of the Nobel Prize in Literature

www.nobelprizes.com/nobel/literature/literature.html

http://www.online-literature.com/

with forums

http://www.postcolonialweb.org/

http://shakespeare-online.com/

Today in Literature

www.todayinliterature.com

http://www.world-english.org/

http://www.worldliteratureforum.com/

forums

https://www.worldliteraturetoday.org

https://www.writersandartists.co.uk

English Scientists

Apart from literature I also read many greatest scientific works of the English nation, for example:

Aristotle METAPHYSICS p135

Newton Mathematical Principles of Natural Philosophy

Poincare Papers on Topology p281
42

Here below is a complete list of the works of some of the greatest scientists to be read:

This file was created on December 01, 2017, 08:23

scientists
├Aristotle METAPHYSICS p135.pdf
├Cauchy Cours de analyse p432.pdf
├Dalton New system of chemical philosophy p600.pdf
├Einstein Brownian Movement.pdf
├Einstein Relativity The Special and General Theory p56.pdf
├Einstein Relativity The Special and the General Theory A Popular Exposition, 3rd ed. P154.pdf
├Einstein The Meaning of Relativity p134.pdf
├Hayek The Road to Serfdom p266.pdf
├Malthus An Essay on the Principle of population p134.pdf
├MAXWELL A treatise on electricity p518.pdf
├Newton Mathematical Principles of Natural Philosophy p594.pdf
├Plato Republic p484.pdf
├Plato Republic p509.pdf
├Poincare Papers on Topology p281.pdf
├Poincare The Value of science p124.pdf
├Popper The Logic of Scientific Discovery p545.pdf
├Rawls A Theory of Justice Revised Edition p561.pdf
└Smith Wealth of nations p754.pdf

See also english_scientists_snapshot.txt

诺贝尔评出100本最伟大文学作品！中国入选1部(图)
文章来源: 蚂蜂窝旅行网 于 2017-12-06 15:47:56 - 新闻取自各大新闻媒体，新闻内容并不代表本网立场！
打印本新闻 (被阅读 46173 次)
早在 2002 年 5 月，挪威诺贝尔学院和挪威读书会就曾共同策划，发起了一个“所有时代最佳百部书籍”的评选活动。

来自 54 个国家的 100 位名作家参与投票，包括法国作家米兰·昆德拉，英国作家鲁西迪、多丽丝·莱辛、约翰·勒·卡雷，中国诗人北岛等。

卑鄙是卑鄙者的通行证，高尚是高尚者的墓志铭。——北岛

100 位作家纷纷给出了各自心目中 10 部“世界文学中最优秀、最核心的作品”，最后由挪威读书会统计出调查结果。

其中，《堂吉诃德》获票超过半数，被选为“举世最佳的文学作品。”而陀思妥耶夫斯基包揽书单中 4 本。

下面是挪威读书会公布的「所有时代最佳百部书籍」

书目，（根据国家和作者的出生年代先后大致排序）：

【希腊】4 部

来自蚂蜂窝用户@行行摄摄－Hunter

荷马：《奥德赛》

索福克里斯：《俄狄浦斯王》

欧里庇得斯：《美狄亚》

卡赞扎基斯《希腊佐巴的故事》

【意大利】7 部

来自蚂蜂窝用户@小小苏子木花花菜

维吉尔：《埃涅阿斯纪》

奥维德：《变形记》

但丁：《神曲》

薄伽丘：《十日谈》

莱奥帕尔迪：《诗集》

斯维沃：《泽诺的意识》

莫兰黛：《历史》

【英国】16 部

来自蚂蜂窝用户@肥/pig+

乔叟：《坎特伯雷故事集》

乔纳森·斯威夫特：《格列佛游记》

莎士比亚：《哈姆雷特》《李尔王》《奥赛罗》

简·奥斯丁：《傲慢与偏见》

艾米莉·勃朗特《呼啸山庄》

乔治·艾略特：《米德尔马契》

狄更斯：《远大前程》

康拉德：《诺斯特罗莫》

劳伦斯：《儿子与情人》

奥威尔：《一九八四》

伍尔夫：《达洛维夫人》《到灯塔去》

多丽丝·莱辛：《金色笔记》

萨尔曼·鲁西迪（印度 / 英国）：《午夜之子》

【爱尔兰】5 部

来自蚂蜂窝用户@胖猪猪胖猪猪

劳伦斯·斯特恩：《项狄传》

乔伊斯：《尤利西斯》

贝克特：戏剧三部曲

《马洛伊》《马洛伊之死》《无名的人》

【法国】12 部

来自蚂蜂窝用户@金辰不是天才

拉伯雷：《巨人传》

蒙田：《随笔集》

狄德罗：《宿命论者雅克和他的主人》

司汤达：《红与黑》

巴尔扎克：《高老头》

福楼拜：《包法利夫人》、《情感教育》

普鲁斯特：《追忆逝水年华》

塞利纳：《茫茫黑夜漫游》

加缪：《局外人》

策兰（罗马尼亚 / 法国）：《诗集》

玛格丽特·尤瑟纳尔：《哈德良回忆录》

【德国】5 部

来自蚂蜂窝用户@无拘无束游四方

歌德：《浮士德》

德布林：《柏林，亚历山大广场》

托马斯·曼：《布登勃洛克一家》《魔山》

格拉斯：《铁皮鼓》

【奥地利】4 部

来自蚂蜂窝用户@逸如

穆齐尔：《没有个性的人》

卡夫卡：《故事全集》《审判》《城堡》

【丹麦】1 部

来自蚂蜂窝用户@似水流年

安徒生：《安徒生童话故事集》

【挪威】2 部

来自蚂蜂窝用户@临窗听雨眠

哈姆生：《饥饿》

易卜生：《玩偶之家》

【瑞典】1 部

来自蚂蜂窝用户@陈力⑦

林格伦：《长袜子皮皮》

【冰岛】2 部

来自蚂蜂窝用户@小晨

《尼雅尔萨迦》

拉克斯内斯：《独立的人们》

【西班牙】2 部

来自蚂蜂窝用户@南山Nathan

塞万提斯：《堂吉诃德》

罗卡：《吉普赛故事诗》

【葡萄牙】2 部

来自蚂蜂窝用户@流苏如画

佩索阿：《惶然录》

萨拉马戈：《失明症漫记》

【俄罗斯】9 部

来自蚂蜂窝用户@问号

果戈里：《死魂灵》

陀思妥耶夫斯基：

《罪与罚》《白痴》《群魔》《卡拉马佐夫兄弟》

托尔斯泰：《战争与和平》

《安娜·卡列尼娜》《伊凡·伊里奇之死及其他》

契诃夫：《小说集》

【美国】10 部

来自蚂蜂窝用户@胖猪猪胖猪猪

爱伦·坡：《故事全集》

惠特曼：《草叶集》

麦尔维尔：《白鲸》

马克·吐温：《哈克贝利·费恩历险记》

福克纳：《押沙龙，押沙龙》《喧哗与骚动》

海明威：《老人与海》

纳博科夫（俄罗斯 / 美国）：《洛丽塔》

艾里森：《看不见的人》

莫里森：《宠儿》

【拉丁美洲地区】5 部

来自蚂蜂窝用户@frank

罗萨（巴西）：《广阔的腹地：条条小路》

胡安·鲁尔福（墨西哥）：《佩德罗·巴拉莫》

博尔赫斯（阿根廷）：《小说集》

马尔克斯（哥伦比亚）：

《百年孤独》《霍乱时期的爱情》

【非洲地区】3 部

来自蚂蜂窝用户@行影相随

纳吉布·马哈富兹（埃及）：《街魂》

塔伊布·萨利赫（苏丹）：《移居北方的时期》

阿契贝（尼日利亚）：《瓦解》

【亚洲地区】11 部

来自蚂蜂窝用户@雪梨酱

《吉尔伽美什史诗》（美索不达米亚）

《约伯记》（以色列）

萨迪（伊朗）：《果园》

鲁米（伊朗）：《玛斯纳维》

《摩诃婆罗多》（印度）

蚁垤（印度）：《罗摩衍那》

迦梨陀娑（印度）：《沙恭达罗》

《一千零一夜》（印度 / 伊朗 / 伊拉克 / 埃及）

鲁迅（中国）：《狂人日记及其他》

紫氏部（日本）：《源氏物语》

川端康成（日本）：《山音》

你旅行时读过哪些书？

-end-

读万卷书行万里路

Other Languages

After the document named lang.chm was written (it was shown as of February 2017), I have again hesitated repeatedly whether or not to recover all my other languages, therefore there was time when I have again and again resumed my other 7 lanagues, and as a result, there were some progresses and records of these studies, such as the ones here below: But I will never resume them again after about November 1, 2017.

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esperanto

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esperanto.html

Esperanto.pdf

Kellerman A COMPLETE GRAMMAR OF ESPERANTO 1910 p352.pdf
148

Kellerman A complete grammar of esperanto1 1910 p352

KARDEC LA LIBRO DE LA SPIRITOJ p475.pdf
68

KARDEC LA GENEZO p436.pdf
52

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french

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french.html

French.pdf

french_litterature_francaise.htm

000Dumas LES TROIS MOUSQUETAIRES p914
17

?????????????????????????

Hugo Notre Dame de Paris p374
17

okokok
Molière Le Bourgeois gentilhomme p121

okokok
Stendhal Le Rouge et le Noir p1086

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scientists

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Cauchy Analyse algébrique p602
72

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german

@@@@@@@@@@@@@@@@@@@@@@@@@@@
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000German.pdf

00german.html

>>>romans

okokok
Musil Die Verwirrungen des Z?glings T?rle? p317

Mann Der Untertan p466
46

>>>scientists

Helmholtz Vorlesung über Theoretische Physik p394
79

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greek

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greek.html

Greek.pdf

greek_literature.htm

okokok
Rutherford First Greek Grammar Accidence p199

okokok
Smith A First Greek Course p214

White First Greek Book p362.pdf
84

White First Greek Book1 p362

http://www.bbc.co.uk/languages/greek/

okokok
https://www.loecsen.com/en/learn-greek

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http://www.surfacelanguages.com/language/Greek
Days. General,

okokok
https://www.ted.com/talks?language=el

okokok
https://en.wikibooks.org/wiki/Modern_Greek

okokok
https://en.wikipedia.org/wiki/Greek_language
okokok
https://en.wikipedia.org/wiki/Modern_Greek_grammar
okokok
https://en.wikivoyage.org/wiki/Greek_phrasebook
?????????????????????????????????????
http://www.xanthi.ilsp.gr/filog/
?????????????????????????????????????
https://www.youtube.com/playlist?list=PLA5UIoabheFOFpdSn-QNUDltHseSulwxs
?????????????????????????????????????
https://www.youtube.com/results?search_query=learn+greek

http://www.xanthi.ilsp.gr/filog/

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hebrew

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hebrew.html

Hebrew.pdf

Cook Biblical Hebrew A Student Grammar p244 2011.pdf
62

Davidson An introductory Hebrew grammar p162
36

Kittel Biblical Herbrew a Text and work book p451
65

??????????????????
Putnam Toward Reading & Understanding Biblical Hebrew p403
58

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latin

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latin.html

Latin.pdf

DOOGE Latin For Beginners 1911 p365
135

Reed Julia p114
47

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russian

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russian.html

Russian.pdf

russian_literature.htm

???????????????????????????
Гоголь Вечера на хуторе близ Диканьки p126
15

Гоголь Миргород Tom 2

okokok
Гоголь Повесть о том, как поссорился Иван Иванович с Иваном Никифоровичем p89

http://www.russianlessons.net/
New: Lesson 18 - Russian Homes and Apartments - Learn all the words needed around the house. Many examples!
http://www.russianlessons.net/lessons/lesson18_main.php
http://www.russianlessons.net/lessons/lesson16_main.php
Летать / Лететь - To Fly


Languages

English

I have learned English completely by my own without attending a single class. I began to learn English in 1982 just a year before graduation. It was the fourth foreign language after Russian, German and French. Only half year later I was able to take English entry exam for postgraduate studies, and was able to read and understand English without much difficulty. I have learned it by many ways – reading a lot, listening a lot (at that time mainly the VOA and BBC radios now rarely able to be received via radios), and practiced a lot.

After school English was very much my second language at works, as my first job was dealing with import of US power generation equipment technologies at the Ministry of Machinery Industry in Beijing. And later I was able to show my excellent English levels to many people in the multinational companies where I used to work.
I have passed an IELS test with a score of 7.0 and my oral score was 9.0, a near native level. Thus around the 1990’s my oral English was fairly good.

English is now almost my working language, as I mostly read English everyday, much more than my native language of Chinese. I have about 30,000 words in mind and can write English with prior preparation of Chinese. That is to say, I think in English too. Many dreams are made in English as well – I often talk in English with people in my dreams. Many times it’s more comfortable to communicate and write English than my native language.

English.docx
English20060802.doc
English20080111.doc
English20111225.doc
English20131111.docx

Literature

Google literature page 5

Contemporary English literature ??

Aesop Aesop’s Fables p89?

Alcott Little Women p684

?

Andersen Andersen’s Fairy Tales p200?

?

Austen Emma p594

Austen Northanger Abbey p288

Austen Persuasion p304

Austen Pride and Prejudice p479

Austen Sense and Sensibility p459

?

?

Bronte Agnes Grey p253

Bronte Jane Eyre p691

Bronte Wuthering Heights p428

?

Buchan The Thirty-Nine Steps p146

?

Burroughs Tarzan of the Apes p342

?

Butler Erewhon p308

?

Caroll Alice’s Adventures in Wonderland p111

?

?

Cervantes Don_Quixote_1 p755.pdf

?

?

?

Clarke For the Term of His Natural Life p723

?

Conrad Heart-of-Darkness p131.pdf??????????????????? 6

Conrad Heart of Darkness p131

Conrad Nostromo: A Tale of the Seaboard p627

?

?

Cooper The Last of the Mohicans p559

?

Defoe Robinson Crusoe p393

?

?

Dickens

Dickens A Christmas Carol p106

Dickens A Tale of Two Cities p537

Dickens Bleak House p1307

Dickens David Copperfield p1307

Dickens Great Expectations p685

Dickens Oliver Twist p641

?

?

Dostoevsky Crime and Punishment p767

Dostoevsky Notes from the Underground p167

Dostoevsky The Brothers Karamazov p1313

Dostoyevsky The Idiot p913

Dostoevsky The Possessed

?

Doyle The Hound of the Baskervilles p223

?

Dumas The Three Musketeers p945

?

Eliot Middlemarch p1193

?

Fitzgerald Tender is the Night p459

Fitzgerald The Great Gatsby p193

Fitzgerald The-Great-Gatsby p193.pdf???????????? 31

?

?

Flaubert Madame Bovary p457

?

Goethe Faust

?

Gogol Dead Souls

?

Grimm Grimms’ Fairy Tales p373

?

Hardy Tess of the d’Urbervilles p584

?

Homer The Iliad p509

Homer The Odyssey p443

?

?

Hugo Les Miserables p2453.pdf

119

?

?

Irving The Legend of Sleepy Hollow p43

?

James The Portrait of a Lady p837.pdf

?

Joyce Dubliners p257

Joyce Ulysses p1047

?

?

Joycew A Portrait of the Artist as a Young Man p317

?

?

Kafka The Castle

Kafka The Metamorphosis p77

Kafka The Trial p271

?

?

Kipling The Jungle Book p189

?

?

Lawrence Lady Chatterly’s Lover p447

Lawrence Sons and Lovers p641

Lawrence Women in Love p717

?

Machiavelli The Prince p194

?

Maugham Of Human Bondage p1009

?

Melville Moby Dick p861

?

Milton Paradise Lost p375

?

?

Mitchell Gone With the Wind

?

?

Montgomery Anne of Green Gables p391

?

More Utopia p148

?

Nietzsche Beyond Good and Evil p250

?

Orczy The Scarlet Pimpernel p343

?

?

Orwell 1984 p393

Orwell Down and Out in Paris and London p254

?

?

Perrault The Tales of Mother Goose p67

?

Porter Pollyanna p243

?

Proust Swann’s Way p658

Proust Within A Budding Grove p783

?

Pyle The Merry Adventures of Robin Hood p395

?

?

Shakespere

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.folgerdigitaltexts.org/download/

http://www.gutenberg.org/ebooks/authors/search/?query=Shakespeare,+William

https://librivox.org/

https://librivox.org/

http://doyle.lib.miamioh.edu/shakespeare/

http://shakespeare.mit.edu/

http://www.opensourceshakespeare.org/

http://www.shakespeare-literature.com/

http://www.shakespeare-literature.com/King_Lear/index.html

http://www.shakespeare-literature.com/King_Lear/1.html

https://en.wikipedia.org/wiki/William_Shakespeare

?

Shakespeare Cymbeline.pdf

Shakespeare Hamlet.pdf

Shakespeare Sonnets.pdf

juliuscaesar_1002_librivox.zip

king_lear_librivox.zip

shakespeare.tar.gz

?

juliuscaesar_1002_librivox/

?

king_lear_librivox/

?

?

shakespeare/

?

?

??? comedies/

?

??????? allswellthatendswell

??????? asyoulikeit

??????? comedyoferrors

??????? cymbeline

??????? loveslabourslost

??????? measureforemeasure

??????? merchantofvenice

??????? merrywivesofwindsor

??????? midsummersnightsdream

??????? muchadoaboutnothing

??????? periclesprinceoftyre

??????? tamingoftheshrew

??????? tempest

??????? troilusandcressida

??????? twelfthnight

??????? twogentlemenofverona

??????? winterstale

?

?

??? histories/

?

??????? 1kinghenryiv

??????? 1kinghenryvi

??????? 2kinghenryiv

??????? 2kinghenryvi

??????? 3kinghenryvi

??????? kinghenryv

??????? kinghenryviii

??????? kingjohn

??????? kingrichardii

??? ????kingrichardiii

?

?

??? poetry/

?

??????? loverscomplaint

??????? rapeoflucrece

??????? sonnets

??????? various

??????? venusandadonis

?

?

??? tragedies/

?

??????? antonyandcleopatra

??????? coriolanus

??????? hamlet

??????? juliuscaesar

??????? kinglear

??????? macbeth

??????? othello

??????? romeoandjuliet

??????? timonofathens

??????? titusandronicus

?

?

Shelley Frankenstein p277

?

?

Stevenson Kidnapped p299

Stevenson The Strange Case of Dr. Jekyll and Mr. Hyde p96

Stevenson Treasure Island p266

?

?

Stoker Dracula p542

?

Swift Gulliver’s Travels p383

?

Thackeray Vanity Fair p1100

?

?

Tolstoy Anna Karenina p1423

Tolstoy War and Peace p2299

?

?

Twain The Adventures of Huckleberry Finn p397

Twain The Adventures of Tom Sawyer p285

?

?

Verne Around the World in 80 Days p279

?

?

?

Voltaire Candide

?

Wells The Island of Doctor Moreau p171

Wells The Time Machine p120

?

Wilde The Picture of Dorian Gray p198

?

The best English novels

?

http://www.bbc.com/culture/story/20150119-the-21st-centurys-12-best-novels

?

http://www.englishnovels.net/

?

http://flavorwire.com/442262/the-50-greatest-british-novels-of-the-19th-century

?

http://www.infoplease.com/ipea/A0776722.html

?

http://www.modernlibrary.com/top-100/100-best-novels/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.planetebook.com/free-ebooks.asp

?

http://www.scaruffi.com/fiction/bestuk.html

?

http://www.telegraph.co.uk/books/what-to-read/100-novels-everyone-should-read/

http://www.telegraph.co.uk/books/what-to-read/20-best-British-novels-of-all-time/

?

http://thegreatestbooks.org/

?

http://www.theguardian.com/books/2015/aug/17/the-100-best-novels-written-in-english-the-full-list

http://entertainment.time.com/2005/10/16/all-time-100-novels/slide/all/

http://entertainment.time.com/2005/10/16/all-time-100-novels/??

?

Literature Sites

?

Google literature page 5?

?

http://www2.hn.psu.edu/faculty/jmanis/jimspdf.htm?????????

?

http://www.4literature.net/

?

http://www.africanlit.org/

?

http://www.americanliterature.com/

?

http://www.anglistikguide.de/

?

http://www.blackliterature.com/

?

http://www.childrensliteratureassembly.org/?

?

http://www.childrenslit.com/

?

http://www.civilwarliterature.com/

?

http://www.danishliterature.info/

?

http://www.dickens-literature.com/

?

http://www.english-literature.org/

?

http://www.fantasticliterature.com/

?

http://www.ferrariliterature.com/

?

http://www.indigenouspeople.net/

?

http://www.irelandliterature.com/

?

http://www.irelandliteratureguide.com/

?

http://www.literature.at/

?

Literature.org - The Online Literature Library

www.literature.org/

?

http://www.literature2000.org/

?

http://www.literaturecircles.com/

?

http://www.literaturecollection.com/

?

http://www.literaturepost.com/

?

http://www.literatureproject.com/

?

http://www.literaturnetz.com/

?

http://www.literaturetraining.com/

?

http://www.multiculturalchildrenslit.com/

?

Winners of the Nobel Prize in Literature

www.nobelprizes.com/nobel/literature/literature.html

?

http://www.oxford-americanliterature.com

?

http://www.postcolonialweb.org/

?

Today in Literature

www.todayinliterature.com

?

American Literature Sites

http://www.wsu.edu/~campbelld/amlit/sites.htm?

?

?

Scientists

?

Aristotle METAPHYSICS p135

?

BACON THE NEW ATLANTIS p41.pdf??????????????? 10

Dalton New system of chemical philosophy p600.pdf???????????? 24

@@@@@@@@@@@@@@@@@@@@@@@@@@

darwin-on-the-origin-of-species p298.pdf??????????????? 12

DarwinYYY originspecies p448.pdf

dewey democracy and education p368.pdf??????????? 28

?

Einstein Brownian Movement

Einstein Sidelights on Relativity.zip

Einstein The Meaning of Relativity p134

Einstein The Meaning of Relativity1 p134

Einstein Relativity The Special and General Theory.zip

Einstein Relativity: The Special and General Theory p56

Einstein Relativity: The Special and the General Theory A Popular Exposition, 3rd ed. P154?

?

grotius De jure belli ac pacis libri tres p224.pdf????????? 4? 54

Hayek The road to serfdom p266.pdf? .................ok

IshaUpanishad p607.pdf ...................... 8

Malthus An Essay on the Principle of population p134.pdf?????????????? 17

MAXWELL a treatise on electricity p533.pdf? ..................? 33

MAXWELL A treatise on electricity p518.pdf

mcluhan Understanding Media p396.pdf????????????????????? 18

Mill The Collected Works Vol1 p489.pdf? .............................? 84

Needham Science and civilization in China p280.pdf????????? 28

?

牛顿《自然哲学之数学原理》

Principia.pdf??????????????????? 139?? / 594

Newton Principia.pdf .......................? 17

Newton Mathematical Principles of Natural Philosophy

?

>>>Newton Mathematical-principles-of-natural-philosophy

Definitions.

Axioms, or Laws of Motion.

Corollary iii.

?

http://www.archive.org/stream/newtonspmathema00newtrich#page/n9/mode/2up

https://ebooks.adelaide.edu.au?

?

Plato Republic p484.pdf

Plato Republic p509.pdf

?

poincare Analysis Situs and Its Five Supplements p281.pdf?????????????? 19

Poincare Papers on Topology p281.pdf

Popper The Logic of Scientific Discovery p545.pdf ,,,,,,,,,,,,,,,,,,,,,,,,,,, 6

prigogine_from_being_to_becoming p293.pdf????????????? 46

RawlsYYY A Theory of Justice Revised Edition p561.pdf

Rawls A theory of justice p562.pdf???????????????? ?547 / 33 of 562

Smith The wealth of nations p508.pdf???????? ?????????????14

SmithYYY wealth-nations p786.pdf

Smith Wealth of nations p754.pdf?

?

News Websites

?

www.abc.net.au

?

http://www.ajc.com

?

http://www.american-reporter.com/

?

www.arabianbusiness.com

?

http://www.asian-affairs.com

?

http://www.asianfortunenews.com

?

www.bbc.co.uk

http://www.bbc.co.uk/education/asguru/english/tvtimecodes.shtml

?

http://broadband-television.com/tv/english.html

?

http://www.bizjournals.com

?

http://www.bloomberg.com

?

http://www.boston.com

?

http://www.bostonherald.com/

?

http://www.businessinsider.com/

?

http://www.businessweek.com/

?

www.cbsnews.com

?

http://news.cnet.com

?

www.cnn.com

?

http://www.chicagotribune.com/

?

http://www.chinaeconomicreview.com/

?

http://www.computerweekly.com/

?

http://www.csmonitor.com/

?

http://www.dailymail.co.uk/

?

http://www.earthtimes.org/

?

http://www.ecogeek.org/

Blogs?

?

http://www.eetimes.com/

?

http://www.forbes.com/

?

http://www.foxbusiness.com

?

www.foxnews.com

?

www.ft.com

?

http://www.geek.com/

?

http://www.gfmag.com/

?

http://www.i-micronews.com/

?

http://www.industryweek.com? ?

?

http://www.inhabitat.com/?

?

http://www.latimes.com/

http://www.marketwire.com/?

?

www.msn.com

?

www.news.com.au

?

http://www.newscientist.com/

?

http://www.newser.com/

?

http://www.northcountrygazette.org/

?

http://www.nydailynews.com/

?

http://www.nytimes.com/

?

http://physicsworld.com/

?

http://planetark.org/

?

http://www.prnewswire.com/

?

http://www.putclub.com/?

?

http://www.reuters.com/

?

http://www.sciencecentric.com

?

http://www.scidev.net/en/

?

http://www.sfgate.com/

?

http://www.signonsandiego.com/

?

http://www.smh.com.au/

?

http://www.sptimes.com/

?

http://www.sunspot.net/

?

http://www.suntimes.com/

?

http://www.swissinfo.org/

?

http://www.thebreakthrough.org/

?

http://www.thedailygreen.com/

?

www.theengineer.co.uk

?

http://www.themalaysianinsider.com/

?

www.thesun.co.uk

?

http://www.topnews.in/

?

http://www.toytownmunich.com/wiki/English_language_television

?

http://www.tv.com/diane-english/person/21566/summary.html

?

http://uanews.org/

?

http://www.usatoday.com/

?

http://www.washingtonpost.com/

?

http://www.washtimes.com/

?

http://www.worldchanging.com/

?

http://www.wsj.com

?

http://wwitv.com/

?

www.yahoo.com

?

http://www.yeworld.net/

?

http://www.yourindustrynews.com/?

?

?

Bible

?

bible_en.chm

?

Revelation 啟示錄 Revelation?? 20


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英语文学
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Google

english literature

english literature portals

english literature friends

english literature penpals

english literature forums

contemporary english writers

page 5

http://www.americanliterature.com/

The Scarlet Letter by Nathaniel Hawthorne

https://americanliterature.com/author/nathaniel-hawthorne/book/the-scarlet-letter/the-custom-house

http://www.biographyonline.net/

https://www.englishforum.ch/

https://www.gutenberg.org/

http://www.languageforexchange.com/

http://literarylondon.org/

http://www.literature.at/

Literature.org - The Online Literature Library

www.literature.org/

http://www.literaturecircles.com/

http://www.literaturecollection.com/

http://www.literaturejunction.com/

with forums

http://www.literatureproject.com/

http://www.literature-study-online.com/

Winners of the Nobel Prize in Literature

www.nobelprizes.com/nobel/literature/literature.html

XXXXXXXXXXXXXXXXXXX

http://www.online-literature.com/

with forums

http://www.postcolonialweb.org/

http://shakespeare-online.com/

Today in Literature

www.todayinliterature.com

XXXXXXXXXXXXXXXXXXXXX

http://www.world-english.org/

XXXXXXXXXXXXXXXXXXXXX

http://www.worldliteratureforum.com/

forums

meinleben

alllinguistist@vfemail.net

vnr3trghfhbfghf

2017-05-24

Hello everyone,

I am first time here. I come here to learn how to write biography in English, because I want to write one for my mother. My native tongue is Chinese, therefore it's not an easy job for me to start a literary project, although English is my working language over 20 years now and my proficiency is close to native already more than 25 years ago when I was enrolled at a British university for PhD studies, and albeit the fact that I used to be multilingual as well, with differing degrees of proficiency in French, German, Russian, Esperanto, Greek, Hebrew and Latin. Now I've decided to focus only on English because I cannot afford maintaining so many languages while all the remaining languages are of no use whatsoever, except English and Chinese. I cannot reach to a level compatible with those of Dickens and Shakespeare, but I do wish to improve my English writing to a level necessary for my writing project called "Mother", which, when finished, shall become a historical memoir of one of the greatest mothers of human history. Please help me if you can. Thank you in advance!

XXXXXXXXXXXXXXXXXXXXX

https://www.worldliteraturetoday.org

XXXXXXXXXXXXXXXXXXXXX

https://www.writersandartists.co.uk


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literature
├<Aesop>
│	└Aesop Aesop’s Fables p89.pdf
├<Alcott>
│	└Alcott Little Women p684.pdf
├<Andersen>
│	└Andersen Andersen’s Fairy Tales p200.pdf
├<Austen>
│	├Austen Emma p594.pdf
│	├Austen Northanger Abbey p288.pdf
│	├Austen Persuasion p304.pdf
│	├Austen Pride and Prejudice p479.pdf
│	└Austen Sense and Sensibility p459.pdf
├<Bronte>
│	├Bronte Agnes Grey p253.pdf
│	├Bronte Jane Eyre p691.pdf
│	└Bronte Wuthering Heights p428.pdf
├<Buchan>
│	└Buchan The Thirty-Nine Steps p146.pdf
├<Burroughs>
│	└Burroughs Tarzan of the Apes p342.pdf
├<Butler>
│	└Butler Erewhon p308.pdf
├<Caroll>
│	└Caroll Alice’s Adventures in Wonderland p111.pdf
├<Clarke>
│	└Clarke For the Term of His Natural Life p723.pdf
├<Conrad>
│	├Conrad Heart of Darkness p131.pdf
│	└Conrad Nostromo A Tale of the Seaboard p627.pdf
├<Cooper>
│	└Cooper The Last of the Mohicans p559.pdf
├<Defoe>
│	└Defoe Robinson Crusoe p393.pdf
├<Dickens>
│	├Dickens A Christmas Carol p106.pdf
│	├Dickens A Tale of Two Cities p537.pdf
│	├Dickens Bleak House p1307.pdf
│	├Dickens David Copperfield p1307.pdf
│	├Dickens Great Expectations p685.pdf
│	└Dickens Oliver Twist p641.pdf
├<Dostoevsky>
│	├Dostoevsky Crime and Punishment p767.pdf
│	├Dostoevsky Notes from the Underground p167.pdf
│	├Dostoevsky The Brothers Karamazov p1313.pdf
│	└Dostoyevsky The Idiot p913.pdf
├<Doyle>
│	└Doyle The Hound of the Baskervilles p223.pdf
├<Dumas>
│	└Dumas The Three Musketeers p945.pdf
├<Eliot>
│	└Eliot Middlemarch p1193.pdf
├<Ellison>
│	└Ellison Invisible Man p451.pdf
├<Fitzgerald>
│	├Fitzgerald Tender is the Night p459.pdf
│	└Fitzgerald The Great Gatsby p193.pdf
├<Flaubert>
│	└Flaubert Madame Bovary p457.pdf
├<Grimm>
│	└Grimm Grimms’ Fairy Tales p373.pdf
├<Hardy>
│	└Hardy Tess of the d’Urbervilles p584.pdf
├<Homer>
│	├Homer The Iliad p509.pdf
│	├Homer The Odyssey p443.pdf
│	├Homer.doc
│	└Homer5.doc
├<Hugo>
│	└000Hugo Les Miserables p2453.pdf
├<Irving>
│	└Irving The Legend of Sleepy Hollow p43.pdf
├<James>
│	├James The Portrait of a Lady p837.pdf
│	└James The Portrait of a Lady1 p837.pdf
├<Johnson>
│	└Johnson The Rise of English p39.pdf
├<jourwest>
│	└jourwest.pdf
├<Joyce>
│	├Joyce Dubliners p257.pdf
│	├Joyce Ulysses p1047.pdf
│	└Joyce Ulysses p1305.pdf
├<Joycew>
│	└Joycew A Portrait of the Artist as a Young Man p317.pdf
├<Kafka>
│	├Kafka The Castle p318.pdf
│	├Kafka The Metamorphosis p77.pdf
│	└Kafka The Trial p271.pdf
├<Kingsley>
│	└Kingsley Alexandria and her Schools p98.pdf
├<Kipling>
│	└Kipling The Jungle Book p189.pdf
├<Lawrence>
│	├000Lawrence Sons and Lovers p641.pdf
│	├Lawrence Lady Chatterly’s Lover p447.pdf
│	└Lawrence Women in Love p717.pdf
├<Longus>
│	└Longus Daphnis Chloe p457.pdf
├<Lowry>
│	└Lowry Under the volcano p692.pdf
├<Machiavelli>
│	└Machiavelli The Prince p194.pdf
├<Maugham>
│	└Maugham Of Human Bondage p1009.pdf
├<Melville>
│	└Melville Moby Dick p861.pdf
├<Milton>
│	└Milton Paradise Lost p375.pdf
├<Montgomery>
│	└Montgomery Anne of Green Gables p391.pdf
├<More>
│	└More Utopia p148.pdf
├<Nabokov>
│	└Nabokov Lolita p224.pdf
├<Nietzsche>
│	└Nietzsche Beyond Good and Evil p250.pdf
├<Orczy>
│	└Orczy The Scarlet Pimpernel p343.pdf
├<Orwell>
│	├Orwell 1984 p192.pdf
│	├Orwell 1984 p393.pdf
│	└Orwell Down and Out in Paris and London p254.pdf
├<Perrault>
│	└Perrault The Tales of Mother Goose p67.pdf
├<Porter>
│	└Porter Pollyanna p243.pdf
├<Proust>
│	├Proust Swann’s Way p658.pdf
│	└Proust Within A Budding Grove p783.pdf
├<Pyle>
│	└Pyle The Merry Adventures of Robin Hood p395.pdf
├<Shakespere>
│	├<comedies>
│	│	├allswellthatendswell
│	│	├asyoulikeit
│	│	├comedyoferrors
│	│	├cymbeline
│	│	├loveslabourslost
│	│	├measureforemeasure
│	│	├merchantofvenice
│	│	├merrywivesofwindsor
│	│	├midsummersnightsdream
│	│	├muchadoaboutnothing
│	│	├periclesprinceoftyre
│	│	├tamingoftheshrew
│	│	├tempest
│	│	├troilusandcressida
│	│	├twelfthnight
│	│	├twogentlemenofverona
│	│	└winterstale
│	├glossary
│	├<histories>
│	│	├1kinghenryiv
│	│	├1kinghenryvi
│	│	├2kinghenryiv
│	│	├2kinghenryvi
│	│	├3kinghenryvi
│	│	├kinghenryv
│	│	├kinghenryviii
│	│	├kingjohn
│	│	├kingrichardii
│	│	└kingrichardiii
│	├<poetry>
│	│	├loverscomplaint
│	│	├rapeoflucrece
│	│	├sonnets
│	│	├various
│	│	└venusandadonis
│	├README
│	├Shakespeare Cymbeline.pdf
│	├Shakespeare Hamlet.pdf
│	├Shakespeare Sonnets.pdf
│	└<tragedies>
│	  	├antonyandcleopatra
│	  	├coriolanus
│	  	├hamlet
│	  	├juliuscaesar
│	  	├kinglear
│	  	├macbeth
│	  	├othello
│	  	├romeoandjuliet
│	  	├timonofathens
│	  	└titusandronicus
├<Shelley>
│	└Shelley Frankenstein p277.pdf
├<Stevenson>
│	├Stevenson Kidnapped p299.pdf
│	├Stevenson The Strange Case of Dr. Jekyll and Mr. Hyde p96.pdf
│	└Stevenson Treasure Island p266.pdf
├<Stoker>
│	└Stoker Dracula p542.pdf
├<Swift>
│	└Swift Gulliver’s Travels p383.pdf
├<Thackeray>
│	└Thackeray Vanity Fair p1100.pdf
├<Tolstoy>
│	├Tolstoy Anna Karenina p1423.pdf
│	└Tolstoy War and Peace p2299.pdf
├<Twain>
│	├Twain The Adventures of Huckleberry Finn p397.pdf
│	└Twain The Adventures of Tom Sawyer p285.pdf
├<Verne>
│	└Verne Around the World in 80 Days p279.pdf
├<Wells>
│	├Wells The Island of Doctor Moreau p171.pdf
│	└Wells The Time Machine p120.pdf
└<Wilde>
      └Wilde The Picture of Dorian Gray p198.pdf


German

Why German ???

?
Germany was in the forefront of science, technology and culture in the period of the mid 16th to early 20th century and now it is unfortunately lagging behind the US mainly in the computer, software, space, and biotechnology. German products are declared to be good quality - not so nowadays - and German people are reliable - the same deterioration as their products now.

Nevertheless, with her well-educated population, good natural resources and climate, her cultural, technological and scientific treasures, Germany is still and will be continue to lead the world in somewhere or other.

German is much more difficult to learn, partly because of her complicated grammar. I have still difficulties with her prepositions and the "Nebensatz" in speaking. Very difficult to compose a complicated word when speaking ...

Regardless of the above, German is my most favored foreign language. I began to study foreign language in 1976, at that time it was Russian. My German studies were started in 1979 when Tongji University has assembled the 200 elite students from all the faculties and fortunately I was one of them (I was considered among the top 50 of the University at that time). These 200 students have been organized into special classes with the only courses of German language and cultures for a year. Many teachers came from Germany such as the Universit?t Ruhr-Bochum, and even after the one-year intensive German lectures, many courses were still taught in German, for example my Physics, Mathematics (Algebra), German history were taught in German, partly at least, or as a supplementary. After the school, I’ve never stopped learning German wherever I went.

There was one time I wanted to exclusively devote to German literature studies, ca around 2007, when my solar, business aviation and all other businesses failed. But I also failed to get some assistance or jobs from German institutions such as Goethe Institut, therefore I abandoned the idea shortly after.
Sept. 09, 2003
Heute bei web.de:
Leni Riefenstahl ist tot: München (WEB.DE) - Die umstrittene Filmemacherin und Fotografin Leni Riefenstahl ist tot. Sie starb im Alter von 101 Jahren in P?cking am Starnberger See...
Dresdner Sinfoniker hüllen <Rammstein> in ein klassisches Gewand: Dresden (dpa) - Normalerweise liegen Welten zwischen den Rockern der Band Rammstein und Musikern wie den Philharmonikern aus Wien oder Berlin. Doch der Dresdner Jazz-Schlagzeuger Sven Helbig hat als eine Art Mittler zwischen den musikalischen Welten die einen für die anderen interessieren k?nnen. Das Ergebnis kommt am 20. Oktober in ganz Europa als Pressung der Deutschen Grammophon auf den Markt, tr?gt den Titel ?Mein Herz brennt? und sorgt in der Musikwelt schon vorab für Schlagzeilen...

In Brüssel ist "Mohamed" der beliebteste Jungenname: Brüssel (dpa) - In der europäischen "Hauptstadt" Brüssel ist "Mohamed" der beliebteste Name für neugeborene Jungen. Mädchen wurden dort im vergangenen Jahr am häufigsten "Sarah" genannt, wie das belgische Statistikamt INS berichtete. Landesweit lagen "Laura" und "Thomas" an der Spitze, erklärten die Statistiker nach Auswertung von gut 110 000 Geburtsanzeigen bei den Standesämtern....
Medienpreis für Sprachkultur an Sandra Maischberger
Gerhard Mayer-Vorfelder ist <<Sprachpanscher des Jahres>>
Taiwan schreibt Chinesisch künftig von links nach rechts: Taipeh (dpa) - Taiwan will seine Sprache internationalen Standards anpassen und künftig - wie in China längst üblich - Chinesisch von links nach rechts und oben nach unten schreiben. Bislang wurden die Schriftzeichen dort von rechts nach links und von unten nach oben geschrieben. Die Umstellung soll Taiwanern das Schreiben auf Papier und am Computer erleichtern, und Ausländern soll es beim Erlernen der Schriftsprache helfen, teilte die Regierung mit...
Hobsbawm erinnert sich an sein Leben als Marxist: München (dpa) - Auch als bis heute bekennender Marxist und mit seinen inzwischen 86 Jahren hat Eric Hobsbawm keine Mühe, õffentlich Gehõr zu finden. So, als der britische Historiker im Sommer die Politik von US-Präsident George W. Bush "großenwahnsinnig" nannte. Seine eigenen Lebenserinnerungen unter dem Titel "Gefährliche Zeiten" sind eher von einer bescheidenen, vor allem aber selbstironischen Sicht geprägt...
Heute bei spiegel.de:
IT-Arbeitsplätze: Indische Unternehmen ziehen deutsche Budgets ab:
Wer in deutschen Gro?unternehmen mit Informationstechnologie (IT) zu tun hat, muss harte Konkurrenz fürchten. Einer Studie zufolge werden schon 2008 bis 20 Prozent der IT-Aufwendungen nach Indien fließen...
Modewoche in Barcelona: Hurra, wir leben noch:
Nomen est Omen. Die Gaudí-Schauen, die derzeit in Barcelona stattfinden, halten, was der Name verspricht: Die Mode, die dort präsentiert wird, steht für die pure Lebenslust. Die spanischen Designer haben offenbar den Spaß an der Arbeit wieder entdeckt...
Websiten:
Bernhard Werner Goldschmidt
Gedichte in alemannischer Mundart. Lyrik aus Ebringen bei Freiburg im Herz des Schwarzwaldes.
Neue Herrlichkeit
Auf dieser Seite finden sie skurrile Geschichten und Illustrationen.
Sept. 11, Midmoon Festival, Hardworking Night
voila.fr
  • Canicule: Mattei admet qu'il n'y a pas eu d'anticipation à la crise sanitaire ...
  • Les films de la semaine: un peu d'histoires de famille, un peu d'Histoire ...
  • Un an avec sursis requis contre Guillaume Depardieu ...
Web.de
  • Erster Astrid-Lindgren-Preis an Autorin Nästlinger überreicht...
  • Genveränderte Bakterien sollen Aidsviren in der Scheide stoppen...

German Class (1979-1980)

Only after a semester of studies at Tongji University, Shanghai, then I was transferred to a German Language Study Class (GLSC), or German Class for short, together with other four classmates of our Department of Mechanics.

Among the five of us, three of us kept in contact until 2001 when I moved from Beijing to Hangzhou, a long friendship of about 23 years. I was very sad to have stopped that relations. I wish someday we will resume the friendship.

One of the five transferees was a lady much elder than us, therefore I didn't know her anything. I can't remember her now.

Mr. Wu Tianyi departed me in 1986 or so when I came back to Shanghai from Beijing. He was teaching at Shanghai Electric Power College. Soon after he left for the U.S. and we lost contacts forever.

Dr. Liu is residing in Guangdong and is a CEO of a publicly traded enterprises, and finally, Mrs. Wu is a editor-in-chief of a german car magazine published in China.

**********************************

There were two classes, one from students enrolled in the 1978 spring season and the other in the 1978 fall semester. I belonged to the later.

As I learned later, the GLSC was a program of the Uni to train german language for students who shall be sent to Germany later. The elder lady was one of them, but the rest 4 didn't get that chance.

Of course, the GLSC was not the only tunnel to pass through to other countries. In fact, most other colleagues went overseas in one way or other, most to North America, not Germany.

Nevertheless, the GLSC gave people a chance to learn a foreign language intensively. During the one-year course period, no other courses were studied, even politics was removed from the program. Starting from pronunciation and ending at speaking, I was happy to know a 2nd language apart from my Russian learned in high school. Although frankly speaking, I knew nothing about the use of these languages. In fact, the whole mission of study at university was very ambiguous - except I knew that one day I may become a scientist, an engineer or even a politician (the last objective was the only purpose why chinese students went to school). But I had no ideas that skills learned at university shall first be used to get a job to earn money to survive and later to prosper in the world.

I still can remember vividly the classes, teachers and colleagues in the classrooms, located in the backyard of the campus, close to the laboratory of thermal science.

I went up very early, at about 6:30 every morning, to speak German in a fresh air. I have been to every grass field, every corner of the campus to find a proper place to speak out. I don't want to people to watch my reading. Sometime we came together with others.

Our books were plumb printed, looked plain but they introduced me to a new world - a world that influenced my life and career forever.

The University invited several teachers from west Germany's Ruhr Bochum University. They taught mathematics, physics, german geology, german history and other courses in German.

We had two chinese teachers too. Of them was a lady, a very nice lady, patient, tender and excellent in speaking. The male teacher looked very pleasant too.

A year passed very quickly. I was redistributed to other department (the Department of Mechanical Engineering) with our remaining three classmates from the Dept of Mechanics whence I came from.

But I never stopped learning German ever since, even today.

DEHMitglied.doc
deutschecke.htm

dlk.doc

German.doc

German Literature

deutschecke.htm

german_literature.htm

0deutsche_literatur.htm

Deutsch-Chinesische Literaturaustausche.htm

autoren.pdf

china_alt.pdf

china_neu.pdf

einblick.pdf

German_Resources.pdf

germanists.pdf

hochschulen.pdf

ngos.pdf

romane.pdf

古典中国文学德译 Alte chinesische Literatur auf deutsch.htm

德语学习资料 Zusammenfassung deutsches Sprachlernens.htm

德语文学专家 Chinesische Germanisten.htm

德语文学介绍 Zusammenfassung deutscher Literaten.htm

德语文学简介 Einfürung.htm

德语文学网站 Deutsche Literature.htm

德语文学译作 übersetze Werke.htm

Liste der Weltliteratur (in alphabetischer Reihenfolge)

?

die altgriechische Literatur

http://www.digbib.org/

?

Die Erz?hlungen aus den tausendundein N?chten

Das Nibelungenlied

?

?

Okonkwo oder das Alte stürzt.????? Chinua Achebe

?

Dante Alighieri, Die G?ttliche Kom?die

?

Hans Christian Andersen, M?rchen

?

Augustinus, Bekenntnisse

?

Stolz und Vorurteil Jane Austen

?

Vater Goriot??? Honoré de Balzac

Honoré de Balzac, Verlorene Illusionen

?

Drei Romane. Molloy. Malone stirbt. Der Namenlose. Samuel Beckett

Samuel Beckett, Das letzte Band

?

Ernst Bloch, Spuren

?

Das Dekameron????? Giovanni Boccaccio

Giovanni Boccaccio, Das Decameron

?

Heinrich B?ll, Erz?hlungen

?

Fiktionen: Erz?hlungen 1939 – 1944??? Jorge Luis Borges

?

Ulrich Br?ker, Der arme Mann im Tockenburg

?

Bertolt Brecht, Geschichten vom Herrn Keuner

?

Sturmh?he: Roman Emily Bront?

?

Georg Büchner, Lenz

?

Der Fremde??? Albert Camus

Albert Camus, Der Fremde

?

Lewis Carroll, Alice im Wunderland

?

Giacomo Casanova, Geschichte meines Lebens

?

Die Gedichte?? Paul Celan

?

Reise ans Ende der Nacht????? Louis-Ferdinand Céline

?

Miguel de Cervantes Saavedra, Don Quijote

?

Die Canterbury-Erz?hlungen Geoffrey Chaucer

?

Nostromo?????? Joseph Conrad

?

Daniel Defoe, Robinson Crusoe

?

Gro?e Erwartungen?????? Charles Dickens

Charles Dickens, Oliver Twist

?

Denis Diderot, Jacques der Fatalist und sein Herr

?

Alfred D?blin, Berlin Alexanderplatz

?

Verbrechen und Strafe??? Fyodor M. Dostoyevsky

Der Idiot Fyodor M. Dostoyevsky

Die Brüder Karamasow? Fyodor M. Dostoyevsky

Fjodor Dostojewski, Die D?monen

?

Eichendorff, Aus dem Leben eines Taugenichts

?

Middlemarch: Roman: Eine Studie des Provinzlebens? George Eliot

?

Der unsichtbare Mann.?? Ralph Ellison

?

Wolfram v. Eschenbach, Parzival

?

Medea???? Euripides

?

Absalom, Absalom!.????? William Faulkner

William Faulkner, Licht im August

?

Henry Fielding, Tom Jones

?

Sigmund Freud, Das Unbehagen in der Kultur

?

Madame Bovary: Sitten der Provinz???? Gustave Flaubert

?

Theodor Fontane, Der Stechlin

?

Max Frisch, Stiller

?

Jean Genet, Querelle

?

André Gide, Tagebücher

Mesopotamia? Gilgamesh

?

歌德Goethe

?

http://www.digbib.org/Johann_Wolfgang_von_Goethe_1749/Faust_I

??????????????

http://www.goethe-bytes.de/?

!!!!!!!!!!!!!!

http://de.goethe-faust.org/?

http://de.goethe-faust.org/der-tragoedie-erster-teil/strasse-2

!!!!!!!!!!!!!!

http://www.hs-augsburg.de/~harsch/germanica/Chronologie/18Jh/Goethe/goe_uf00.html

http://www.hs-augsburg.de/~harsch/germanica/Chronologie/18Jh/Goethe/goe_uf01.html

!!!!!!!!!!!!!!

http://www.kerber-net.de/literatur/deutsch/drama/goethe/faust.htm

http://gutenberg.spiegel.de/index.php?id=18&autor=A

http://gutenberg.spiegel.de/?id=5&xid=3448&kapitel=1#gb_found

!!!!!!!!!!!!!! !!!!!!!!!!!!!!

http://www.wissen-im-netz.info/literatur/goethe/faust/index.htm

!!!!!!!!!!!!!!

http://www.zum.de/Faecher/D/BW/gym/faust/index.htm?

?

浮士德? Faust

Faust Eine Trag?die: Erster und zweiter Teil Johann Wolfgang von Goethe

Johann Wolfgang v. Goethe, Die Leiden des jungen Werthers

Johann Wolfgang v. Goethe, Die Wahlverwandtschaften

?

?

?

Goethe Das Maerchen p19.pdf

11

?

?

Goethe Der neue Paris p7.pdf

Goethe Der Prokurator p9.pdf

Goethe Die Geschichte von Mignons Eltern p8.pdf

Goethe Egmont p43.pdf

?

?

Goethe Faust Der Trag?die erster Teil p99

18

?

Goethe Faust Der Trag?die zweiter Teil p175

?

Goethe G?tz von Berlichingen p55.pdf

Goethe Prometheus p13.pdf

Goethe Wilhelm Meisters Lehrjahre p246.pdf???????????????? 8? /? 246

?

?

Nikolai Gogol, Die toten Seelen

?

Iwan Gontscharow, Oblomow

?

Günter Grass, Die Blechtrommel

?

http://www.guenter-grass.de/

http://www.guenter-grass-haus.de/

?

GrassGuenther Die Blechtrommel p281.pdf????????????

53

?

?

?

Die Brüder Grimm, Kinder- und Hausm?rchen

?

Grimmelshausen, Der abenteuerliche Simplicissimus

?

Knut Hamsun, Hunger

?

Jaroslav Ha?ek, Abenteuer des braven Soldaten Schwejk

?

Johann Peter Hebel, Das Schatzk?stlein des Rheinischen Hausfreunds

?

Heinrich Heine, Deutschland. Ein Winterm?rchen

Heine Ideen Das Buch Le Grand

7

?

?

?

Ernest Hemingway, Der alte Mann und das Meer

?

Hermann Hesse, Der Steppenwolf

?

E.T.A. Hoffmann, Kater Murr und Kreisler

?

Friedrich H?lderlin, Hyperion

?

Ilias Homer

Odyssee?? Homer

?

Victor Hugo, Die Elenden

?

Nora oder Ein Puppenheim / Hedda Gabler? Henrik Ibsen

?

Das Buch Hiob?????? Ijob

?

Uwe Johnson, Jahrestage

?

James Joyce, Ulysses

?

Die Verwandlung und andere Erz?hlungen?? Franz Kafka

Der Prozess??? Franz Kafka

Franz Kafka, Erz?hlungen

Franz Kafka, Das Schlo?

?

Kafka Das Schloss

30

?

?

Sakuntala: Drama in sieben Akten Kalidasa

?

Immanuel Kant, Zum ewigen Frieden

?

Ein Kirschbaum im Winter: Roman????? Yasunari Kawabata

?

Alexis Sorbas? Nikos Kazantzakis

?

Gottfried Keller, Der grüne Heinrich

?

Soeren Kierkegaard, Entweder – Oder

?

Heinrich von Kleist

Heinrich v. Kleist, Erz?hlungen

http://www.kleist.org/

http://www.authorama.com/der-zerbrochene-krug-1.html

Der zerbrochene Krug

Der_zerbrochne_Krug.pdf??????????? 8

?

?

S?hne und Liebhaber???? D.H. Lawrence

?

Sein eigener Herr?? Halldór K. Laxness

?

Giacomo Leopardi. Gedichte. Giacomo Leopardi

?

Das goldene Notizbuch. Doris Lessing

G. E. Lessing, Anti-Goeze

?

Claude Lévi-Strauss, Traurige Tropen

?

G. C. Lichtenberg, Sudelbücher

?

Pippi Langstrumpf? Astrid Lindgren

?

Longos, Daphnis und Chloe

?

Zigeunerromanzen? Federico García Lorca

?

Das trunkene Land: Erz?hlungen???? Lu Xun

?

Mahabharata??

?

UT, Nr.50, Die Kinder unseres Viertels Naguib Mahfouz

?

Heinrich Mann, Der Untertan

?

Thomas Mann, Die Buddenbrooks

Der Zauberberg. Roman.?????? Thomas Mann

?

MannThomas Tonio Kr?ger p167.pdf ???????????????????

47

?

?

Hundert Jahre Einsamkeit???? Gabriel García Márquez

Die Liebe in den Zeiten der Cholera???? Gabriel García Márquez

?

Karl Marx, Der 18. Brumaire des Louis Bonaparte

?

Moby Dick???? Herman Melville

?

Michel de Montaigne, Essais

?

La Storia: Roman?? Elsa Morante

?

Menschenkind Toni Morrison

?

Karl P. Moritz, Anton Reiser

?

Thomas Morus, Utopia

?

Die Geschichte vom Prinzen Genji. 2 Bde.?? Shikibu Murasaki

?

Der Mann ohne Eigenschaften 1: Erstes und zweites Buch? Robert Musil

Robert Musil, Die Verwirrungen des Z?glings T?rle?

?

Lolita????? Vladimir Nabokov

?

Nietzsche Also sprach Zarathustra p489.pdf

?

Brennu-Njáls saga? Njals saga

?

Friedrich Nietzsche, Menschliches, Allzumenschliches

?

1984?????? George Orwell

?

Metamorphosen????? Ovid

?

John Dos Passos, Manhattan Transfer

?

Blaise Pascal, Pensées

?

Jean Paul, Siebenk?s

?

Das Buch der Unruhe???? Fernando Pessoa

?

Platon, Apologie

?

S?mtliche Erz?hlungen? Edgar Allan Poe

Edgar Allan Poe, Phantastische Erz?hlungen

?

Auf der Suche nach der verlorenen Zeit?????? Marcel Proust

?

Wilhelm Raabe, Abu Telfan oder Die Heimkehr vom Mondgebirge

?

Fran?ois Rabelais, Gargantua und Pantagruel

?

Rainer Maria Rilke, Aufzeichnungen des Malte Laurids Brigge

?

Grande Sert?o Jo?o Guimar?es Rosa

?

Jean-Jacques Rousseau, Bekenntnisse

?

Pedro Páramo Juan Rulfo

?

Mathnawi?????? Jalal ad-din Rumi

?

Mitternachtskinder? Salman Rushdie

?

Anna Seghers, Das siebte Kreuz

?

The Orchard?? Sheikh Musharrif ud-din Sadi

?

Season of Migration to the North? Tayeb Salih

?

Die Stadt der Blinden??? José Saramago

?

Jean-Paul Sartre, Die W?rter

?

Friedrich Schiller, ?sthetische Schriften

?

Stendhal, Rot und Schwarz

?

Arthur Schopenhauer, Parerga und Paralipomena

?

Hamlet??? William Shakespeare

K?nig Lear???? William Shakespeare

Wiliam Shakespeare: Othello

?

K?nig ?dipus Sofokles

?

Laurence Sterne, Leben und Ansichten von Tristram Shandy

?

Adalbert Stifter, Erz?hlungen

?

Gottfried v. Stra?burg, Tristan

?

August Strindberg, Sohn einer Magd

?

Zeno Cosini??? Italo Svevo

?

Jonathan Swift, Gullivers Reisen

?

Tacitus, Germania

?

Anton Tschechow, Erz?hlungen

?

Leo Tolstoi, Krieg und Frieden

Anna Karenina?????? Lev Tolstoj

Der Tod des Iwan Illjitsch???? Lev Tolstoj

?

Leo Trotzki, Mein Leben

?

Erz?hlungen.? Anton P. Tsjekhov

?

Tausend und eine Nacht? Kitab Alf layla wa layla

?

Iwan Turgenew, V?ter und S?hne

?

Die Abenteuer des Huckleberry Finn??? Mark Twain

?

Ramayana?????? Valmiki

?

Vergil, Aeneis

?

Grashalme????? Walt Whitman

?

Oscar Wilde, Das Bildnis des Dorian Gray

?

Mrs Dalloway Virginia Woolf

?

Die Erinnerungen des Kaisers Hadrian Roman???? Marguerite Yourcenar

?

émile Zola, Germinal

?

Deutsche Autoren

http://www.authorama.com/

http://www.archive.org

www.ds-shanghai.org.cn

http://www.klassiker-der-weltliteratur.de

http://www.literaturcafe.de

http://www.literaturkritik.de

http://www.literaturhaus.at/

www.livinglakes.org

http://www.lyrikwelt.de

www.natur.de

www.sinogermanschool.com

http://gutenberg.spiegel.de/

www.VDS-ev.de

http://www.sino-german.com/

http://www.tour-literatur.de

http://www.virtuelleallgemeinbibliothek.de

Scientists

?Albert Einstein

http://www.alberteinstein.info/

http://alberteinstein.info/

http://einstein.biz/

http://www.aeinstein.org/

http://www.albert-einstein.org/

http://www.einsteinandreligion.com/

http://einsteinpapers.press.princeton.edu/

http://press.princeton.edu/einstein/

http://www.pupress.princeton.edu/catalogs/series/cpe.html

?

http://www.einstein.caltech.edu/

http://www.einstein.caltech.edu/what/index.html

https://www.dmoz.org/Science/Physics/History/People/Einstein%2C_Albert/

http://www.gutenberg.org/ebooks/author/1630

https://www.ias.edu/people/einstein

http://www.shapell.org/manuscript/einstein-jewish-refugees-from-germany-hitler-1935

http://www.westegg.com/einstein/

https://en.wikipedia.org/wiki/Albert_Einstein

?

?

okokok

Einstein Molekürdimension

?

okokok

Einstein Tr?gheit

?

?

okokok

Einstein über die Bewegung

?

okokok

Einstein über einen Gesichtspunkt

?

okokok

Einstein Zur Elektrodynamik

?

?

Leonhard Euler

?

okokok

Joseph Fraunhofer

Fraunhofer Bestimmung

?

okokok

FreudSigmund Traumdeutung p79.pdf?????????????

FreudSigmund Traumdeutung p78.pdf?????????????

?

Carl Friedrich Gauss (1777-1855)

?

?

okokok

Gauss Disquisitiones UNTERSUCHUNGEN üBER H?HERE ARITHMETIK p356.pdf??????????????

?

okokok

Gauss Untersuchungen über Gegenst?nde der H?hren Geod?sie p112.pdf

?

?

?

okokok

Gauss_Carl_Friedrich_Werke_8 p472.pdf????????????????

?

?

Otto Hahn

?

?

okokok

Hasse Mathematischen Tagebücher p566.pdf????????????

Hasse Mathematischen Tagebücher1 p566.pdf

?

?

Werner Heisenberg

?

Hermann von Helmholtz

?

Richard Hesse

okokok

Humboldt Cosmos p518

?

okokok

Humboldt Gesammelte Werke p380

?

?

Immanuel Kant

Kant Kritik der reinen Vernunft p1014.pdf???????

Kant - Kritik der reinen Vernunft p1015.pdf???????

59

?

?

Rolf Landauer

?

Gottfried Leibniz

Leibniz Dissertatio Arte Combinatoria p85

LeibnizYYY S?MTLICHE SCHRIFTEN UND BRIEFE p68.pdf????????

?

?

okokok

Max Planck

Planck Entropie und Temperatur strahlender Waerme.pdf

?

?

Schopenhauer Die Welt als Wille und Vorstellung p2372.pdf?????

40

?

?

Weber Religionssoziologie p238.pdf??????????????

6

German literature Studies (2007)

Like IT, I never considered languages as part of my research subjects, with one exception - German, although I was multilingual - English, German, French, Russian and a little Greek, Latin and Hebrew. There was time when I wanted to devote to German language and literature studies and researches, but I gave the plan up after failure to find a research institute to support my plan, such as Goethe Institute. Nevertheless I have spent quite some efforts to study the German literature and to prepare for that studies.

alleandere.doc
austausch.doc
autoren.doc
autoren.docx
autoren1.doc
china_alt.doc
china_alt1.doc
china_alt1xxx.doc
china_neu1.doc
china_neu2.doc
de_lernen.doc
einblick.doc
germanists.doc

German_Resources.doc
German_Resources1.doc
German_Resources2.doc

hochschulen.doc
hochschulen1.doc
magazin.doc
ngos.doc
ngos1.doc
prufung.doc

romane.doc
romane.docx
romane1.doc

TOC_German_Literature.doc
TOC_German_Literature1.doc

ubersetzungsfirmen.doc
websites.doc

Zeitungen

?

www.aachener-zeitung.de

?

www.aargauerzeitung.ch/

?

www.abendblatt.de

?

www.aerzte-zeitung.de/

?

www.aha-zeitschrift.de/

?

www.ahgz.de/

?

www.aichacher-zeitung.de/

?

www.alfelder-zeitung.de/

?

www.aller-zeitung.de/

?

www.all-in.de

?

www.allgemeine-zeitung.de/

?

www.andelfinger.ch/

?

www.apc.de/veto

?

www.arbeit-wirtschaft.at/

?

www.arbeitnehmer-online.de/

?

www.archaeologisch.de/

?

www.athener-zeitung.com

?

www.atz-blinde.de/

?

www.augsburger-allgemeine.de/

?

www.autozeitung.de/

?

www.az-namibia.de

?

www.az-online.de

?

www.azag.ch

?

www.az-badkreuznach.de/

?

www.azonline.ch/

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www.azonline.de/

?

www.baden-online.de/

?

www.badenerzeitung.at

?

www.badische-zeitung.de

?

www.balaton-zeitung.de/

?

www.barmstedter-zeitung.de/

?

www.baz.ch

?

www.berlin-nachrichten.de/

?

www.berlinonline.de

?

www.bietigheimerzeitung.de/

?

www.berliner.de/

?

www.blackwell.de

?

www.bleckederzeitung.de/

?

www.bnet.co.at/oz/

?

www.boersen-zeitung.com

?

www.boehme-zeitung.de

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www.boennigheimerzeitung.de/

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www.borkumer-zeitung.de/

?

www.brandschutz-zeitschrift.de/

?

www.braunschweiger-zeitung.de/

?

www.bunte.de

?

www.bvd.de

?

www.bz-net.de/

?

www.bz-online.ch

?

www.cellesche-zeitung.de

?

www.computer-zeitung.de

?

http://www2.computer-zeitung.de/cz/

?

www.contextxxi.at/

?

www.coopzeitung.ch/

?

www.d-b-z.de/

?

www.d-o-z.de/

?

www.degruyter.de/journals/zgl/

?

www.deisternz.de/

?

www.derpatriot.com/

?

www.detail.de/

?

www.deutscher-apotheker-verlag.de/DAZ/

?

www.dewezet.de/Schaumburger_Zeitung/

?

www.die-bonn.de/zeitschrift/

?

www.diezeitschrift.de

?

www.diezeitung.com/

?

www.dill.de/

?

www.diz-muenchen.de/

?

www.doebelner-allgemeine.de/

?

www.donau.de

?

www.dpg-online.de/

?

www.dsz-verlag.de/

?

www.dud.de/

?

www.dulzinea.de

?

www.dumag.ch

?

www.dvz.de/

?

www.dw-world.de ?????????

?

www.eberbacher-zeitung.de/

?

www.eckernfoerder-zeitung.de

?

www.efriz.ch/

?

www.eifelzeitung.de/

?

www.einblick.dgb.de/

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www.ejz.de/

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www.eltern.de/

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www.emderzeitung.de/

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www.energie-und-management.de/

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www.eppendorfer.de/

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www.espace.ch

?

www.eulenspiegel-zeitschrift.de/

?

www.evlka.de

?

www.ez-online.de

?

www.fafiz.muehlbauer-verlag.de/

?

www.famrz.de/

?

www.faz.de??? www.faz.com

?

www.focus.de

?

www.forschung-und-lehre.de/

?

www.frankenpost.de/

?

www.free.de/antifa/nrw/

?

www.freiepresse.de/

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www.fuldaerzeitung.de/

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www.gebrauchtwagen-zeitung.de/

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www.gestalt.de

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www.getraenke-zeitung.de/

?

www.gigi-online.de/

?

www.giessener-allgemeine.de/

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www.goslar-zeitung.de

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www.goslarsche-zeitung.de/

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www.gz-journal.de/

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www.hannover-zeitung.de/

?

www.hanser.de/zeitschriften/mk/

?

www.haz.de

?

www.heinsberger-zeitung.de/

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www.hersbrucker-zeitung.de/

?

www.hersfelder-zeitung.de/

?

www.herald-zeitung.com/

?

www.heute.de

?

www.haz.hildesheim.com

?

www.hilpoltsteiner-zeitung.de/

?

www.hockey-zeitung.de/

?

www.hohenzollerische-zeitung.de/

?

www.homoeopathie-zeitschrift.de

?

www.hunsrueck-zeitung.com/

?

www.hz-online.de

?

www.idowa.de/

?

www.ifa.de/zfk/

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www.info3.de/

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www.immobilien-zeitung.de/

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www.inst.at/trans/

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www.islamische-zeitung.de

?

www.jazzzeitung.de/

?

www.jurass.de/

?

www.jurpc.de

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www.k-zeitung.de/

?

www.kemet.de/

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www.kes.info/

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www.kindercircus-zeitung.de/

?

www.kleine.co.at

?

www.kleinezeitung.at

?

www.kritische-sozialwissenschaft.de/

?

www.krone.at

?

www.kuenstliche-intelligenz.de/

?

www.kurier.at/

?

www.kwz.de/

?

www.labournet.de/express/

?

www.lahn-dill.de/

?

www.lelac.ch/

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www.lichtungen.at/

?

www.literatur-live.de

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www.lust-zeitschrift.de/

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www.lohn-und-gehalt-zeitschrift.de/

?

www.lose-blaetter.de/

?

www.lz-net.de/

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www.lz-online.de/

?

www.maerkischeallgemeine.de/?

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www.main-rheiner.de

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www.mainpost.de

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www.mare.de/

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www.matices.de/

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www.mdz-moskau.de/

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www.medienpaed.com/

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www.medienpraktisch.de

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www.mendener-zeitung.de/

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www.memmingen-online.de/

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www.merz-zeitschrift.de/

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www.mittelbayerische.de/

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www.mittelhessen.de/

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www.mittendrin-magazin.de/

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www.morgengrauen.org/

?

www.moz.de/

?

www.mz-web.de/

?

www.rnz.de

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www.n-tv.de

?

www.nachrichten.ch ???????????????????????

?

www.nachrichten.com

?

www.nachrichten.at

?

www.naps-online.de/

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www.natur.de/

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www.netzeitung.de/

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www.neue-lz.ch

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www.neue-oz.de

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www.newsclick.de

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www.ngz-online.de

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www.nmz.de/

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www.nnz-online.de/

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www.nordsee-zeitung.de

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www.nordschleswiger.dk/zeitung/

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www.nordwest-zeitung.de/

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www.nordzeit.de/

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www.nrz.de/

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www.ntz.de

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www.nuernberger-zeitung.de/

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www.nur-zeitschriften.de

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www.nuz.de/

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www.nwz-online.de

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www.nz-online.de

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www.nzz.ch/

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www.oberhasler.ch/

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www.oberpfalznetz.de/

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www.oeghd.or.at/zeitschrift/

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www.oekotest.de

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www.oezp.at

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www.online-merkur.de/

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www.onlinepc.ch/

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www.osteuropa.rwth-aachen.de/

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www.ostfriesen-zeitung.de

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www.ostpreussenblatt.de/

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www.ostsee-zeitung.de

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www.ostseezeitung.de/

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www.otz.de

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www.owl-online.de/

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www.oz-net.at/

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www.panorama.ch/

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www.paz-online.de/

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www.pegnitz-zeitung.de/

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www.pharmazeutische-zeitung.de

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www.pommersche-zeitung.com

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www.post.ch

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www.prokla.de/

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www.protoculture.org/

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www.psyche.de/

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www.psychotherapie.de/

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www.publik-forum.de/

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www.pulsar.at/

?

www.pz-net.de

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www.pz-news.de

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www.pz.pirmasens.de

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www.regionalzeitung.ch/

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www.rems-zeitung.de

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www.revolver-film.de/

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www.rheiderland.de/

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www.riehener-zeitung.ch/

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www.rote-hilfe.de/rhz/

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www.saale-zeitung.de/

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www.saar-zeitung.de/

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www.saarland-online.de/

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www.salzburg.com

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www.schnapp.de/

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www.schreibheft.de/

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www.schwaebische-zeitung.de

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www.segeberger-zeitung.de/

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www.segler-zeitung.de/

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www.sh-nordsee.de/

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www.shz.de/

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www.siebenbuerger.de/

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www.single-zeitschrift.de/

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www.sol.de/szimnetz/

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www.solothurner-zeitung.ch

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www.sonntagszeitung.ch

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www.sowieso.de/

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www.sozialismus-jetzt.de/

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www.sozialoekonomie.de

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www.spanien-zeitung.com/

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www.spiegel.de?

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www.spielgruppe.ch/

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www.sport-zeitung.de/

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http://www.springeronline.com

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www.spw.de/

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www.stamp.ch

?

www.steglitz.de/StadtteilZeitung/?

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www.stern.de

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www.stimme.de/

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www.stuttgarter-zeitung.de

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www.stuttgarterzeitung.de/

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www.styria.com

?

www.stz-online.de/

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www.suderburg-online.de/suz

?

www.sued-zeitung.de/

www.sueddeutsche.de?? www.sueddeutschezeitung.de?? www.sueddeutsche.com

?

www.suedostasien-zeitung.com/

?

www.sz-online.de

?

www.sz-newsline.de

?

www.szbz.de/

?

www.t-online.de

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?

德语角

??

Meine Eigene Deutsche Ecke Hangzhou

Late April (in 2002 perhaps), when I was talking with a girl in the Zhejiang library for a translation and teaching opportunity, an idea suddenly come up: to organize a German corner in Hangzhou.

I learned later, there were once two german corners in the city, one in the Zhejiang university and the other in the Shuren university, all disbanded because of lack of participants. I asked why. People learning german feared difficult to find jobs and the previous corners didn't provide chances for information exchange for jobs and other concerns.

Now I will organize one to cater those needs. My german corner will be well prepared, well organized.

First, german people will be invited to the corner in each session (about once a week). These german people come mostly from the industry, some also as teachers or students. They will provide german lessons, history, art, music, science, geography, living and study in Germany etc, everything about Germany and german language. They will improve our speaking; they will probably provide job opportunities;

And further we hope the german industries will sponsor our activities, in turn we will try to promote their companies, and their products.

During each session, various topics will be talked, personal life, culture, art, traditions, cuisines, travel etc.

The group will also move around the city. Up at mountain tips, down on the Westlake, here at cafe shops, there in a teehouse. Or in an open garden. I have already made a candidate meeting places, some costing money, some free.

In my plan, we will held a German Week os something to promote the german presence in the province. Germany's Schleswig Holstein state is the partner state with Zhejiang. But development of economic ties is mostly stagnating. Few companies from Germany enter into the soil of the province. They like Shanghai more.

I sent out invitations to german companies I found from AHS Shanghai. Mr Thomas Gut of SurTec responded. He was enthusiastic and we met the next day, together with their four, at the StarBucks, an expensive but nice coffee shop. That was the first and only meeting of my planed german corner. It was not well organized, people seemed a bit nervous and Mr Gut was the suspect in front of the police officers. We kept asking him questions while others remained silent, esp. the young girls.

After that meeting I have planning another event, trying to get feedback from my friends. Like my emails to Chinese solar suppliers, they got no replies. I was despaired once again, for I was spending my time preparing for the meeting which is good to others. What they want ?

I was soon discouraged and told another, senior level german teacher to take over the task and then retreated.

At the moment, a certain Mr Zhou from SAR is managing the case. He told me he also has got no replies from his participants.

Hallo,

Ich m?chte eine deutsche Ecke (DE) bei der Zhejiang Bibliothek organisieren. Die DE soll der Verweiterung, Verbesserung und Ausbildung der deutschen Sprache in Hangzhou bedienen. Ich hoffe auch darauf, dass am m?glichsten viele deustchen Expatriaten hier in Hangzhou und der Provinz Zhejiang unsere Ecke teilnehmen k?nnten.

Ich werde die Ecke so organisieren, dass es m?glichst gleiche M?dchen und M?nner gibt, um die geschlechtliche Unbalance zu vermeiden.

Wenn Sie Interesse haben sollten, dann melden Sie sich bei mir via email oder rufen Sie mich an unter 0571-********, 0571-********,.

über mich bitte gucken Sie mal nach http://www.solaires.com/company/bio.htm ?an.

Viel Spa? !

Chen Minghua

Meine Damen und Herren,

vielen Dank für ihre Teilnahmen an das erste (ungeplannte) Zusammentreffen unserer Deutsche Ecke Hangzhou (DEH) heute am StarBucks Bar. Spezifische Danke für Herr Gut's Kaffe und Ms Cinderella's Dienst.

Ich werde Ihnen das Datum, den Zeitpunkt, die Fahrrichtung, die Aktivit?ten vorher (zirka drei Tage zuvor) anmelden. Es muss nicht unbedingt am n?chsten Wochenende sein, zumindenst am Angfang der DEH. Ich hoffe, dass Sie Ihre Vorschl?ge und Informationseintritte bei mir am frühesten anlegen k?nnen.

Wir werden auch mal sehen, ob wir einen festen Platz für Treffen kriegen k?nnen. Dieser Platz muss uns gebührenfrei jede Zeit verfügbar, oder mindenstens am Wochenende.

Ich sende Ihnen unsere Liste und auch die Aktivit?tsrekords. Beide sollten von dem n?chsten Organisierer behalten und weiterbearbeiten.

Ich hoffe darauf, dass unsere DEH allen hilfreich sein sollte und jeder von Ihnen wird ein aktiver Teil der Gruppe sein.

Ich wünsche auch dass wir auch eine privatliche Beziehung zwischen einigen von uns entwickeln kann.

Ziel DEH: deutsche Sprachekenntnisse zu verbessern, miteinnander zu helfen (Arbeitnehmern gute Arbeitgeber zu finden und umgekehrt, Information und Erfahrungen auszutauschen, deutsche Kultur und Industrien zu promovieren um die Stadt Hangzhou).

Wünsche Ihnen alle ein gutes Wochenende !

Chen Minghua

Sehr geehrter Herr Pauen,

herzlich willkommen zu unserer Deutsche Ecke Hanzhou, einem Platz wo man über verschiedenste Thema diskutieren kann.

Beiliegend sind zwei Unterlagen zu finden: 1) unsere Mitgliederliste mit Updating von neuen Teilnehmern und 2) unser Gruppebericht. Ich werde Ihnen über alle DEH Entwicklung informiert machen und zur weiteren k?nnten Sie all diese Information auch bei meiner Website hier: http://www.solaires.com/deutsch/index_de.htm ?finden. Dieser Teil der Web ist noch unter Plan, dennoch sieht es noch nicht gut aus aber ich werde es innerhalb eines Monates alles ?ndern.

Information und Vorschl?ge sind sehr willkommen.

Die zweite Aff?re wird sich mitgeteilt nachdem wir alle mit der Termine, dem Platz und Allgemeinen Thema verbunden sind. Vielleicht k?nnte es einbisschen l?nger dauern wegen SARS.

Beste Grü?e !

Chen Minghua

Betreff: Versp?tung DEH Wegen SARS

Meine Damen und Herren,

Es tut mir leid, da? ich Ihnen informieren mu?, das n?chste Treffen unserer Deutschen Ecke einbisschen zu verschieben. Wann wir uns wiedertreffen k?nnten, h?ngt v?llig von der SARS-Situation ab.

Inzwischen k?nnen wir per Email oder Telefonieren in Kontakt nehmen oder machen wir individuellen Kontak in kleinerem Umfang.

Ich hoffe darauf, da? sich unsere DEH zum Verstehen zwischen Deutschland und China beitragen kann.

Mit freundlichen Grü?en !

Chen Minghua

Tel.: 0571-85113764 (Büro), 88912373 (private), 13023615275 (handy)

Sehr geehrte Herr/Frau Paulus,

ich bin sehr erfreut, Sie beide gestern kennenzulernen und bin ich Ihnen auch sehr dankbar für Ihr Angebot.

Gestern habe ich vergessen zu bemerken, dass ich ganz in dem Norden der Statdt lebe und deswegen muss ich eine lange Strecke gehe um Ihr Wohnhous zu erreichen - etwa eine Stunde entweder mit Bus oder bei Radfahren. Ich habe kein eingenes Auto.

So muss ich Ihnen darum bitten, entweder lassen Sie Ihren Fahrer hier mich abzuholen oder bezahlen Sie die Taxigebühren (ungef?hr RMB 2x(25-30) oder RMB 50-60 einen Tag). Ich werde Ihnen natürlich die Papiere vorlegen.

Dann noch die Zeit. Vielleicht w?re es besser, einbisschen sp?ter bei Ihrem Wohnhous anzukommen, z.B. 15-30 Minuten sp?ter, d.h. um 8:15 oder 8:30 morgens.

über die Quittung habe ich noch keine andere L?sung. Sobald meine Firma noch existiert, kann ich es beschaffen. Aber ich habe schon vor, n?chte Woche mein Büro zu schliessen. Es gibt keine Chance für mich in Hangzhou. Wir werden bei Ihrern Buchhaltungsberatern noch einbisschen diskutieren. Ich glaube, die Leute haben irgendwelche L?sung.

Ich wünsche Ihnen ein sch?nes Wochenende !

Chen Minghua

Tel.: 0571-88912373, 13023615275

Sehr geehrter Herr Paulus,

entschudigen Sie bitte - ich kann morgen nicht kommen. Habe eine Pech - soeben haben die Fischgr?te meine Zunge gekratzt - ich muss zu Hause ruhig bleiben. Ich werde auch versuchen, einen anderen einzuführen.

Grü? !

Chen Minghua

Hallo Frau/Herr Yvonne und Peter Paulus,

besten Dank für Ihre Kummer um meine Gesundheit. Schon besser, aber noch bisschen Probleme mit meiner Kehleschmerz (throatsore).

Ich habe die Mitgliederliste beigelegen, so dass Sie genaus wissen, wer in der DEH anwesend sind. Hoffentlich gibt's da Leute mit denen Sie sprachlich Austauschen machen k?nnen.

Ich habe schon mit Herrn Liu von der Shuren Universit?t gesagt, dass ich in Hangzhou nicht lang bleiben kann. Er ist mit mir einverstanden, die DEH weiterzuleiten. So schlage ich Ihnen vor, mit ihm in direkten Kontakt zu nehmen. Ich bin sleber nicht sicher, ob ich noch bei n?chstem Mal nich dasein sei.

Ich bin auch einbisschen von der Mentalit?t der Hangzhouer entt?tuscht.Ich habe vor zwei Wochen an alle Teilnehmer geschrieben, mir Feedbackinformation über die Veranstaltung unserer DEH so schnell wie m?glich zu etwas Vorschl?ge zu senden (sehen Sie auch an meiner Website). Aber alle verschweigen sich. Und ich habe keine Leidenschaft mehr.

Ich habe generell negative Eindrücke von nativen Menschen in dieser Stadt. In Shanghai habe ich andere Historie.

Ein DES oder DEB wird vielleicht besser.

Wenn ich Ihnen hilfsreich sein konnte, bitte teilen Sie mir mit.

Meine beste Grü?e !

Chen Minghua

Hallo Herr Liu,

beiliegend finden Sie bitte die Information über die Deutsche Ecke Hangzhou. Ich hoffe, dass Sie DEH weiterorganisieren k?nnen. Ich bin auch nicht sicher, ob ich diese Woche noch Zeit habe.

Wenn Sie Problems haben, rufen Sie mich an oder scheiben Sie ein Email.

Grü? !

Chen Minghua

Neue Treffenpunkt

Hallo meine Damen und Herren,

heute nachmittag bin ich zur Franz?sischen Ecke (FE) gegangen, und fand es einen guten Treffenpunkt für unsere Deuteche Ecke (DE) auch. So habe ich mit dem Organisierer der FE diskutiert, er sagte, es w?re kein Problem, dass sich die DE auch am derselben Platz stattfindet. So haben wir abgestimmt, dass unsere deutsche Ecke nun auch einen festgestellten Platz hat:

Der Chunnuan Huaikai (春暖花开书店) Buchladen gegenüber dem Xixi Digital Port (西溪数码港) an der Wensan Strasse (文三路) nahe der Mugansan Str. (莫干山路).

Der Laden ist ge?ffnet vom Morgen bis in die Nacht, so beeilen Sie sich nicht, um um eine bestimmete Zeit da zu sein. Dieser Platz is frei zur Verfügng zu stehen, so brauchen Sie auch keine Angst. Aber Sie k?nne auch Bier, Tee oder Kaffe trinken wie Sie wollen, aber mit Ihrem eigenen Geld.

Der Klub ist am ersten Gescho? und die DE wird sich am Sonntag, nicht Samstag stattfinden.

Ich hoffe Sie alle dort so bald zu treffen.

Sch?nes Wochenend !

Chen Minghua

杭州德语角欢迎加入！

杭州德语角在文三路西溪数码港对面的春暖花开书店举行，每周日下午2：30开始，没有固定结束时间，欢迎在杭州的德语爱好者加入！有关信息也可在下列网址找到：http://www.solaires.com/deutsch/ubersetzen/dec.htm。

电子邮件: solaires@hotmail.com??

Deutsche Ecke Hangzhou 杭州德语角

西城图书馆
还真是个好地方儿，有专门的旅游阅览室和德文图书德语角
www.xiashabbs.com/bbs

Stammtisch in Hangzhou

MAX CLUB in hangzhou
米·CLUB咖啡馆

杭州德语角

?

杭州德语角欢迎加入！

?

http://www.beiming.net/t9730-1-1.html

http://solartoday.myartsonline.com/contact/bio.htm

http://neolife.mipropia.com/intro/cv/ResumeCN20100807Consult.pdf?ckattempt=1

?

solaires

发表于 2003-7-14 15:41:53 | 只看该作者 回帖奖励

您需要 登录 才可以下载或查看，没有帐号？加入北冥 用百度帐号登录

x 杭州德语角欢迎加入！

杭州德语角在文三路西溪数码港对面的春暖花开书店举行，每周日下午2：30开始，没

有固定结束时间，欢迎在杭州的德语爱好者加入！有关信息也可在下列网址找到：http://www.solaires.com/deutsch/ubersetzen/dec.htm。

电子邮件:

sts_china@hotmail.com

?

?

浙江科技学院·外国语学院/中德学院

德语角/ 浙江科技学院小和山校区精艺园

http://wyx.zust.edu.cn/shownews.asp?id=1939

?

杭州下沙德语角

时间:?

2013年05月26日 周日 18:00-20:30

地点: 杭州 江干区 艾咖啡：下沙东海未名园东面白杨路13号

费用:? 免费

Bible

?

bible_de_Die Geschichte der Bibel.pdf

bible_de_FrauenderBibel.pdf

bible_de_islam_bibel.pdf??? 6

bible_de_Warum_Muslime_die_Bibel_f_r_verf_lscht_halten.pdf

?

bible_de_luther_1.pdf

bible_de_luther_1.pdf???????????? xiv

?

bible_de_Tafelbibel.pdf????

25
Some Internet Resources

German - Chinese Information Resources & Translation Services
in China
  • 中国德语界
  • 中德论坛
  • 北京德讯之窗
  • 德语园地
  • 德语学习
  • 德语德国
  • 北冥信息港
  • 星天空德国留学社区
  • 德国中文
  • 北京周报德语版
  • 德国世纪网播
  • goethe.com.cn
  • Guide Translation Service
  • Deutsche Schule Shanghai
  • Radio China International
  • China im Bild
in Germany
  • Agnes Fatrai
  • Brucca.de
  • Changdamm übersetzungen
  • China Print + Screen Media
  • China Translation Bonn
  • Deutsche China-Gesellschaft e.V.
  • Dr. Yubo Wang
  • Globalization Partners International
  • Hongqin Flicker
  • Lektorat.de Infosysteme
  • Macfarlane Internationaler Sprachendienst
  • Offenberg übersetzungsdienst
  • Ostasienservice
  • Petra Müller China Consult
  • Sino-Bridge
  • Zappmedia
  • China Platform
  • China tech+culture trans Prof. Wolfgang Arlt
  • IMTS - Beratung und Management auf Zeit in China
  • Christine Berg China-Dienste, Hamburg
  • INSIDE A
  • EURO-CHINA Vermittlungsbüro für wirtschaftliche und technische Zusammenarbeit (ECV)
  • INTERKULTURELLE KOMMUNIKATIONSBERATUNG XUGUANG PAN
  • CHINA SCOUT
  • Asia-Pacific Management Consulting GmbH
  • China Contact
  • China-Consult Rath
  • Planet Text
  • Sprachendienst Bangard
  • Abitz
  • Übersetzer online
  • A P O S T R O P H ü B E R S E T Z U N G E N
  • Dr Schmidt Übersetzungsservice SPKG Battenstein GmbH
  • Language Services, Ltd., Victoria, B.C., Canada
  • Übersetzungsfuchs Röhling
  • Übersetzungsdienst MOP
  • Escadra s.r.o.
  • Orbis Sprachendienst
  • Deutsch-Chinesische Wirtschaftsvereinigung (DCW)
Portals
  • Chinalink
  • schanghai.com
  • China Club
  • Asia-Bridge
Industries & Diplomacy
  • Deutschen Botschaft Peking http://www.deutschebotschaft-china.org
  • Botschaft der Volksrepublik China in der Bundesrepublik Deutschland http://www.china-botschaft.de
  • the German speaking Community Shenzhen http://www.inshenzhen.de/
  • Generalkonsulat der Bundesrepublik Deutschland Shanghai
  • Generalkonsulat der Bundesrepublik Deutschland Hongkong
  • Generalkonsulat der Bundesrepublik Deutschland Kanton
  • www.guangzhou.diplo.de
  • Chinesisch-Deutsche Zentrum für Wissenschaftsfõrderunghttp://www.sinogermanscience.org.cn/
  • Delegiertenbüro der Deutschen Wirtschaft Hongkong und Südchina
  • Delegiertenbüro der Deutschen Wirtschaft Shanghai
  • Deutsche Entwicklungsgesellschaft, Peking
  • Deutsche Industrie- und Handelskammer Peking
  • Deutsche Informationsbibliothek Shanghai
  • Deutsche Schule Peking
  • Deutsche Schule Shanghai
  • German Centre Peking
  • German Centre Shanghai
  • China Campus Berlin 2002


5 Deutsche Literatur und China

Deutsch-Chinesische Literaturaustäusche
中德文学交流
1 中德文化交流 2
1.1 “2007北京国际图书博览会”传来信息：中德文学交流存在翻译障碍2007-09-03 2
1.2 《中国德语文学研究史———一九四九》课题结项2007-09-11 4
1.3 张威廉与中国德语文学的译介：04-02-25：吴晓樵 5
1.4 关注德国，关注德意志文化2007-09-03 7
1.5 中国名作家苏童将与德国文学家互访推广城市交流2007-7-26 9
1.6 德国学者来校讲述德国文化2007-3-29 10
1.7 “德国文化周”明年来华2006年12月19日 12
1.8 北京理工大学第一届德国文化周 12
1.9 主题：德国当代文学新生代作家朗诵会 14
1.10 德国文化周，生活更具魅力—上海德国文化周?安亭新镇分会场(2005.12.29) 18
1.11 中国杭州大剧院由德国人来管？ 2005年4月5日 19
1.12 “2007杭州法国文化周”10月28日在天都城开幕 21
2 德国文学在中国的影响 22
2.1 德国文学在中国的解读和误读2007-08-31 22
2.2 二十世纪上半期中国的“德国文学学科”历程2005年4月7日 23
2.3 主题：在历史课本中起伏－采访新获德国文学奖的北岛05-05-12 27
3 中国对德国文学的影响 32
3.1 中国文化里所具有的“世界精神”——德国文学里的中国图景及其思想史意义 2007-5-13 32


Deutsche Ecke

Hallo,

Ich möchte eine deutsche Ecke (DE) bei der Zhejiang Bibliothek organisieren. Die DE soll der Verweiterung, Verbesserung und Ausbildung der deutschen Sprache in Hangzhou bedienen. Ich hoffe auch darauf, dass am möglichsten viele deustchen Expatriaten hier in Hangzhou und der Provinz Zhejiang unsere Ecke teilnehmen könnten.

Ich werde die Ecke so organisieren, dass es möglichst gleiche Mädchen und Männer gibt, um die geschlechtliche Unbalance zu vermeiden.

Wenn Sie Interesse haben sollten, dann melden Sie sich bei mir via email oder rufen Sie mich an unter 0571-88912373, 0571-85113764.

Über mich bitte gucken Sie mal nach http://www.solaires.com/company/bio.htm an.

Viel Spaß !

Chen Minghua

Meine Damen und Herren,

vielen Dank für ihre Teilnahmen an das erste (ungeplannte) Zusammentreffen unserer Deutsche Ecke Hangzhou (DEH) heute am StarBucks Bar. Spezifische Danke für Herr Gut's Kaffe und Ms Cinderella's Dienst.

Ich werde Ihnen das Datum, den Zeitpunkt, die Fahrrichtung, die Aktivitäten vorher (zirka drei Tage zuvor) anmelden. Es muss nicht unbedingt am nächsten Wochenende sein, zumindenst am Angfang der DEH. Ich hoffe, dass Sie Ihre Vorschläge und Informationseintritte bei mir am frühesten anlegen können.

Wir werden auch mal sehen, ob wir einen festen Platz für Treffen kriegen können. Dieser Platz muss uns gebührenfrei jede Zeit verfügbar, oder mindenstens am Wochenende.

Ich sende Ihnen unsere Liste und auch die Aktivitätsrekords. Beide sollten von dem nächsten Organisierer behalten und weiterbearbeiten.

Ich hoffe darauf, dass unsere DEH allen hilfreich sein sollte und jeder von Ihnen wird ein aktiver Teil der Gruppe sein.

Ich wünsche auch dass wir auch eine privatliche Beziehung zwischen einigen von uns entwickeln kann.

Ziel DEH: deutsche Sprachekenntnisse zu verbessern, miteinnander zu helfen (Arbeitnehmern gute Arbeitgeber zu finden und umgekehrt, Information und Erfahrungen auszutauschen, deutsche Kultur und Industrien zu promovieren um die Stadt Hangzhou).

Wünsche Ihnen alle ein gutes Wochenende !

Chen Minghua

Sehr geehrter Herr Pauen,

herzlich willkommen zu unserer Deutsche Ecke Hanzhou, einem Platz wo man über verschiedenste Thema diskutieren kann.

Beiliegend sind zwei Unterlagen zu finden: 1) unsere Mitgliederliste mit Updating von neuen Teilnehmern und 2) unser Gruppebericht. Ich werde Ihnen über alle DEH Entwicklung informiert machen und zur weiteren könnten Sie all diese Information auch bei meiner Website hier: http://www.solaires.com/deutsch/index_de.htm finden. Dieser Teil der Web ist noch unter Plan, dennoch sieht es noch nicht gut aus aber ich werde es innerhalb eines Monates alles ändern.

Information und Vorschläge sind sehr willkommen.

Die zweite Affäre wird sich mitgeteilt nachdem wir alle mit der Termine, dem Platz und Allgemeinen Thema verbunden sind. Vielleicht könnte es einbisschen länger dauern wegen SARS.

Beste Grüße !

Chen Minghua

Betreff: Verspätung DEH Wegen SARS

Meine Damen und Herren,

Es tut mir leid, daß ich Ihnen informieren muß, das nächste Treffen unserer Deutschen Ecke einbisschen zu verschieben. Wann wir uns wiedertreffen könnten, hängt völlig von der SARS-Situation ab.

Inzwischen können wir per Email oder Telefonieren in Kontakt nehmen oder machen wir individuellen Kontak in kleinerem Umfang.

Ich hoffe darauf, daß sich unsere DEH zum Verstehen zwischen Deutschland und China beitragen kann.

Mit freundlichen Grüßen !

Chen Minghua

Tel.: 0571-85113764 (Büro), 88912373 (private), 13023615275 (handy)

Sehr geehrte Herr/Frau Paulus,

ich bin sehr erfreut, Sie beide gestern kennenzulernen und bin ich Ihnen auch sehr dankbar für Ihr Angebot.

Gestern habe ich vergessen zu bemerken, dass ich ganz in dem Norden der Statdt lebe und deswegen muss ich eine lange Strecke gehe um Ihr Wohnhous zu erreichen - etwa eine Stunde entweder mit Bus oder bei Radfahren. Ich habe kein eingenes Auto.

So muss ich Ihnen darum bitten, entweder lassen Sie Ihren Fahrer hier mich abzuholen oder bezahlen Sie die Taxigebühren (ungefähr RMB 2x(25-30) oder RMB 50-60 einen Tag). Ich werde Ihnen natürlich die Papiere vorlegen.

Dann noch die Zeit. Vielleicht wäre es besser, einbisschen später bei Ihrem Wohnhous anzukommen, z.B. 15-30 Minuten später, d.h. um 8:15 oder 8:30 morgens.

Über die Quittung habe ich noch keine andere Lösung. Sobald meine Firma noch existiert, kann ich es beschaffen. Aber ich habe schon vor, nächte Woche mein Büro zu schliessen. Es gibt keine Chance für mich in Hangzhou. Wir werden bei Ihrern Buchhaltungsberatern noch einbisschen diskutieren. Ich glaube, die Leute haben irgendwelche Lösung.

Ich wünsche Ihnen ein schönes Wochenende !

Chen Minghua

Tel.: 0571-88912373, 13023615275

Sehr geehrter Herr Paulus,

entschudigen Sie bitte - ich kann morgen nicht kommen. Habe eine Pech - soeben haben die Fischgräte meine Zunge gekratzt - ich muss zu Hause ruhig bleiben. Ich werde auch versuchen, einen anderen einzuführen.

Grüß !

Chen Minghua

Hallo Frau/Herr Yvonne und Peter Paulus,

besten Dank für Ihre Kummer um meine Gesundheit. Schon besser, aber noch bisschen Probleme mit meiner Kehleschmerz (throatsore).

Ich habe die Mitgliederliste beigelegen, so dass Sie genaus wissen, wer in der DEH anwesend sind. Hoffentlich gibt's da Leute mit denen Sie sprachlich Austauschen machen können.

Ich habe schon mit Herrn Liu von der Shuren Universität gesagt, dass ich in Hangzhou nicht lang bleiben kann. Er ist mit mir einverstanden, die DEH weiterzuleiten. So schlage ich Ihnen vor, mit ihm in direkten Kontakt zu nehmen. Ich bin sleber nicht sicher, ob ich noch bei nächstem Mal nich dasein sei.

Ich bin auch einbisschen von der Mentalität der Hangzhouer enttätuscht.Ich habe vor zwei Wochen an alle Teilnehmer geschrieben, mir Feedbackinformation über die Veranstaltung unserer DEH so schnell wie möglich zu etwas Vorschläge zu senden (sehen Sie auch an meiner Website). Aber alle verschweigen sich. Und ich habe keine Leidenschaft mehr.

Ich habe generell negative Eindrücke von nativen Menschen in dieser Stadt. In Shanghai habe ich andere Historie.

Ein DES oder DEB wird vielleicht besser.

Wenn ich Ihnen hilfsreich sein konnte, bitte teilen Sie mir mit.

Meine beste Grüße !

Chen Minghua

Hallo Herr Liu,

beiliegend finden Sie bitte die Information über die Deutsche Ecke Hangzhou. Ich hoffe, dass Sie DEH weiterorganisieren können. Ich bin auch nicht sicher, ob ich diese Woche noch Zeit habe.

Wenn Sie Problems haben, rufen Sie mich an oder scheiben Sie ein Email.

Grüß !

Chen Minghua

Neue Treffenpunkt

Hallo meine Damen und Herren,

heute nachmittag bin ich zur Französischen Ecke (FE) gegangen, und fand es einen guten Treffenpunkt für unsere Deuteche Ecke (DE) auch. So habe ich mit dem Organisierer der FE diskutiert, er sagte, es wäre kein Problem, dass sich die DE auch am derselben Platz stattfindet. So haben wir abgestimmt, dass unsere deutsche Ecke nun auch einen festgestellten Platz hat:

Der Chunnuan Huaikai (春暖花开书店) Buchladen gegenüber dem Xixi Digital Port (西溪数码港) an der Wensan Strasse (文三路) nahe der Mugansan Str. (莫干山路).

Der Laden ist geöffnet vom Morgen bis in die Nacht, so beeilen Sie sich nicht, um um eine bestimmete Zeit da zu sein. Dieser Platz is frei zur Verfügng zu stehen, so brauchen Sie auch keine Angst. Aber Sie könne auch Bier, Tee oder Kaffe trinken wie Sie wollen, aber mit Ihrem eigenen Geld.

Der Klub ist am ersten Geschoß und die DE wird sich am Sonntag, nicht Samstag stattfinden.

Ich hoffe Sie alle dort so bald zu treffen.

Schönes Wochenend !

Chen Minghua

杭州德语角欢迎加入！

杭州德语角在文三路西溪数码港对面的春暖花开书店举行，每周日下午2：30开始，没有固定结束时间，欢迎在杭州的德语爱好者加入！有关信息也可在下列网址找到：http://www.solaires.com/deutsch/ubersetzen/dec.htm。

电子邮件:solaires@hotmail.com.


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德语文学
deutsche literatur
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http://www.dw.com/

Lei Li
Programmvertrieb: China, Taiwan, Hongkong, Singapur, Vietnam, Myanmar
T.+49.228.429-2603
lei.li@dw.com

dw-akademie@dw.com
info@dw.com

=============================

http://deutsche-literaturgesellschaft.de/

Empfang@Deutsche-Literaturgesellschaft.de

Date: | Mon, 16 Oct 2017 10:16:36 +0200
To: | Mark Chen <markchen@xmail.net>
From: | Deutsche Literaturgesellschaft, S. Finnern <empfang@deutsche-literaturgesellschaft.de>
Subject: | [No Subject]

Sehr geehrter Herr Chen,

vielen Dank für Ihre freundliche Mail.

Wir sind einer der bedeutendsten Anbieter für Self-Publishing-L?sungen,
d.h., wir unterstützen Autoren, die sich entscheiden, ihr Buch selbst
heraus zu bringen – und dabei unser Verlags-Know-How nutzen wollen. Wir
helfen, indem wir für sie Lektorat, Buchsatz, Coverlayout, Druck,
Vertrieb und Werbung/PR übernehmen. Heute erscheinen ja mehr als 80%
aller Bücher eigenfinanziert und feiern gro?e Erfolge, auch kehren immer
mehr etablierte Autoren ihren Verlagen den Rücken, um selbstbestimmt und
mit mehr Anteil am Gewinn zu ver?ffentlichen.
Wenn dies der Weg ist, den Sie gehen m?chten, schauen wir gerne mit
Ihnen gemeinsam, was die beste L?sung ist. Dafür ben?tigen wir das
Manuskript und etwa 14 Tage Zeit.

Ich freue mich, von Ihnen zu h?ren!

Mit freundlichen Grü?en

Sabine Finnern
Autorenbetreuung
--
Deutsche Literaturgesellschaft
Repr?sentanzbüro Berlin
Fasanenstra?e 61 - 10719 Berlin
Tel. 030/76 75 99 22
Ein Imprint der Europ?ische Verlagsgesellschaften GmbH

Sehr geehrte Frau Sabine Finnern,

vielen Dank für Ihr Rückschreiben.

Sie haben ganz recht, daß jetzt viele Autoren versuchen, selbst zu veröffentlichen. Ich bin keine Ausnahme.

Aber ich bin noch nicht bereit, weil ich noch kein Manuskript geschrieben habe. Ich habe nur eine Einführung und ein Kapitel auf englisch und drei Kapiteln auf chinesisch geschrieben, kein deutsch. Die Biographie meiner Mutter will nicht offiziell gestartet werden, bevor ich genug Einkommen gewonnen habe, und der Schreibensprojekt wird sehr lange dauern, vielleicht einige Jahre or mehr. Das ist ein Projekt von meinem ganzen Lebenslauf, nicht aber eine kurze Sache. So ich brauche mehr Zeit und Geduld. Und viel Geld auch, weil es sich auch mit mehreren anderen Erinnerungsaktivitäten angeknüpft ist.

Wenn ich wirklich bereit bin, werde ich mir sicher an Sie wenden, und dann werden Sie hoffentlich sehen würden, das mein Projekt ganz anders als alle anderen sein sollten, die Sie bisher gesehen and gehört haben. Weil ich etwas außerordentliches tun wollte, in meinem Lebenslauf.

Vielen dank nocheinmal für Ihre Antwort und wünsche ich Ihnen

Alles Gut!

Mark Chen

=============================

http://china.ahk.de/about-us/contact-us-in/east-china/#c113002

Simone Pohl

Delegate and Chief Representative of Delegation of German Industry and Commerce Shanghai Executive Director and Board Member of German Chamber of Commerce in China – Shanghai

+86-21-5081-2266

office@sh.china.ahk.de

=============================

https://www.goethe.de/ins/cn/de/sta/sha.html

Generalkonsulat der Bundesrepublik Deutschland Shanghai
101 Cross Tower
318 Fu Zhou Lu
Shanghai 200001, VR China

Tel.: +86 21 63912068
Fax.:?+86 21 63840269
info@shanghai.goethe.org

=============================

http://www.literaturcafe.de/infos-und-impressum/

Chefredakteur, Herausgeber und inhaltlich Verantwortlicher gem?? § 55 Rundfunkstaatsvertrag (RfStV) und Absatz 5 Telemediengesetz (TMG): Wolfgang Tischer

tischer@literaturcafe.de

=============================

http://www.spiegel.de/

=============================

https://www.stern.de

=============================

http://www.literaturkonferenz.de/

info@literaturkonferenz.de

Ansprechpartnerin: Iris Mai (Email: mai@literaturkonferenz.de)

=============================

https://www.xlibris.de/Kontakt

=============================

http://literaturhaus-frankfurt.de/service/kontakt/

info@literaturhaus-frankfurt.de

=============================

https://www.autorenwelt.de/kontakt

=============================

www.germancentreshanghai.com

=============================

http://www.china.diplo.de/Vertretung/china/de/Startseite.html

=============================

https://www.volkswagenstiftung.de/

info@volkswagenstiftung.de

=============================

http://www.china-stiftung.de/

Vorstand: Johanna P?llath

johanna.poellath@pplaw.com

Fangfang Gao

fangfang.gao@pplaw.com

=============================

https://www.humboldt-foundation.de/

info@avh.de

=============================

https://www.boell.de/

info@cn.boell.org

=============================

http://www.daad.de

http://www.daad.org.cn/

http://www.daad.org.cn/germanistik-und-deutsche-sprache-in-china

shanghai@daad.org.cn

Ansprechpartner: Dr. Sven H?nke，Leitung Lektorenprogramm China

lektoren@daad.org.cn

http://www.daad.org.cn/germanistik-und-deutsche-sprache-in-china/daad-lektorenliste

http://www.daad.org.cn/germanistik-und-deutsche-sprache-in-china/germanistikforderung-des-daad-in-china?vhocvqgtkufkufum

http://www.daad.org.cn/stipendienangebote-fur-chinesen/sonderprogrammesonstiges

=============================

http://www.schanghai.com/

team@schanghai.com

=============================

https://www.deutscheakademie.de/

sekretariat@deutscheakademie.de

=============================

https://www.deutscher-literaturfonds.de

info@deutscher-literaturfonds.de

=============================

http://www.lcb.de/uebersetzer/

mail@lcb.de

=============================

http://www.kas.de

Hans-Joerg.Clement@kas.de

=============================

https://www.kulturrat.de/ueber-uns/deutsche-literaturkonferenz/

post@kulturrat.de

=============================

http://www.re-cit.eu/contact/

Europ?isches übersetzer-Kollegium Nordrhein-Westfalen in Straelen (Deutschland)
euk.straelen@t-online.de

=============================

http://www.uebersetzerfonds.de/kontakt.html

mail@uebersetzerfonds.de

=============================

http://www.ds.uzh.ch/gfdsl/kontakt.php

gfdsl@ds.uzh.ch

=============================

http://hans-feger.de/koop-china.html

  • Telefon:
    +49 (0)30 838-544 21
    +49 (0)30 838-552 87
  • Fax:
    +49 (0)30 838-567 49
    +49 (0)30 838-596 74
  • E-Mail:
    hdfeger@zedat.fu-berlin.de

Dr Hans Feger

=============================

http://www.bosch-stiftung.de/content/language1/html/57867.asp

=============================

https://www.freiheit.org/

=============================

http://www.fes.de/

info@fes-shanghai.org

=============================

http://www.europaeische-kultur-stiftung.org/

=============================

http://www.bundesstiftung-friedensforschung.de/

info@bundesstiftung-friedensforschung.de

=============================

http://www.bertelsmann-stiftung.de/

=============================

https://www.welthaus.de/

info@welthaus.de

=============================

https://www.aasf.de/

aasf@aasf.de

=============================

http://www.chinavdma.org/

holger.paul@vdma.org

=============================

http://www.aai-wien.at/

office@aai-wien.at

=============================

Hanns-Seidel-Stiftung China

Hanns-Seidel-Stiftung, Peking
1 Xindonglu, Tayuan Diplomatic Compound
P.O.Box 5-2-122, 100600 Beijing, PR China
Tel: 010-6532-6180/81 | Fax: 010-6532-6155
Email: beijing@hss-china.com

=============================

Michael RÖDER Zhejiang Universtity
School of International Studies
Institute of German Studies
Zi Jin Gang Campus
Building 6, Room 203
Yuhangtang Lu 866
Hangzhou 310058 		roeder.daad@outlook.com

Karlsruhe Institute of Technology (KIT)
Herr Tobias Arndt
General Manager
KIT China Branch
Room 1101, Building A, Wisdom Center
No.10 Moon Bay Road, Suzhou Industrial Park
Suzhou 215123
Tel.: +86-512-6296 7399
Fax: +86-512-6296 7389
E-Mail: arndt.tobias [at] silu.asia

Technische Universit?t Darmstadt
Leitung: Frau Isabelle Harbrecht
TU Darmstadt Liaison Office
Tongji University
Chinese-German Building, Rm. 704
Chifeng Rd. No. 50
200092 Shanghai
Tel.: +86-21-6598 6669
E-Mail: harbrecht.is[at]pvw.tu-darmstadt.de
Sprechzeiten: Di. 10:00 – 11:30 Uhr und Do. 14:00 – 15:30 Uhr

Dr. Gabriele OTTO | Shanghai International Studies University (SISU) German Department Dalian Road (W) No. 550 200083 Shanghai | sisu-daad-otto@outlook.de
Dr. Gudrun L?RINCZ | Tongji University Deutschkolleg der Tongji-Universit?t Zhangwu Lu 100 Nan-Da-Lou 222 200092 Shanghai | gudrunlorincz@web.de
Sebastian UNGER | Tongji University Deutsche Fakult?t Siping Road No. 1239 Hao Huiwen Lou 420 Shi 200092 Shanghai | sebastian.unger@posteo.de
Julia WEBER (Lehrerfortbildung) | Tongji University Deutsche Fakult?t Siping Road No. 1239 Hao Huiwen Lou 420 200092 Shanghai | weber.julia@gmx.net
Deborah SCHLIMBACH | Tongji University Chinesisch-Deutsches-Hochschulkolleg Chifeng Road No. 50, Room 607 200092 Shanghai | deborahschlimbach@yahoo.de
Mike BERND | University of Shanghai for Science and Technology (USST) Shanghai-Hamburg-College Jun Gong Road No. 516 Yangpu District 200093 Shanghai | berndmike.daad@outlook.com
Dr. Jan-Helge WEIDEMANN | East China Normal University Dongchuan Road No. 500 Minhang District 200241 Shanghai | jweidema@uni-bonn.de
Marc ESSER | Shanghai Jiao Tong University Fakult?t f. Germanistik Dongchuan-Str. 800 200240 Shanghai | marc.esser11@web.de

Akademische Prüfstelle in Shanghai
German Center Tower 1, Office 619-620, 88 Keyuan Road,
Pudong District, 201203 Shanghai, PR China
Homepage: https://www.aps.org.cn/aps-am-gk-shanghai
E-Mail: sha-termin[at]aps.org.cn

Fraunhofer-Gesellschaft China
Landmark Tower 2, Raum 0606, Dongsanhuan Beilu 8
Chaoyang District, Beijing 100004, PR China
Homepage: www.fraunhofer.de
E-Mail: hanxd[at]fraunhofer.cn

Helmholtz-Gemeinschaft China
Landmark Tower 2, Raum 1723, Dongsanhuan Beilu 8
Chaoyang District, Beijing 100004, PR China
Homepage: www.helmholtz.de
E-Mail: info[at]helmholtz.cn

Chinesisch-Deutsches Zentrum für Wissenschaftsf?rderung
Shuangqing Lu 83
Haidian District, Beijing 100085, PR China
Homepage: www.sinogermanscience.org.cn
E-Mail: center[at]sinogermanscience.org.cn

Forschungs-gemeinschaft für deutsche Literatur

Seminare für Inter-kulturelle Germanistik

Deutsche Literatur in VR China und sonstiges

Sehr geehrte(r) Dame/Herr,

ich erfreue mich sehr, Ihnen zu schreiben, um sich mit Ihnen über deutsche Literatur zu unterhalten. Ich habe Ihren Kontakt per einen von meinen Freunden bekommen. Hoffentlich ist dieser Brief nicht unerwartet..

Ich bin ein 55-jähriger Chinese, aber am Alter von knapp 20 war ich schon 5 Fremdsprachen kennengelernt, dazwischen auch Deutsch, und zwar meine zweite und beliebteste Fremdsprache - die anderen waren Russisch, Französisch, Englisch und Esperanto, die ich weiterhin sudiere bis heute, plus Griechisch und einbißchen Lateinisch und Hebräisch.

Damals habe ich schon einige kurzen Romane und Dichtungen teilweise von deutsch ins chinesisch übersetzt, wenn ich an der sogannanten deutschen Klassen von 200 Studenten, an der Tongji Universität, Schanghai, studierte, wie z.B. die folgenden:

  • "Ein Fall für Moll"
  • "Kommisar Ermer's Schwierigster Fall"
  • "Tod vor dem Fernsehrschirm"
  • "Willkommen und Abschied (Goethe)"
  • "Emilia Galotti"
  • "Verheissung"
  • "Erleuchtung"
  • "Das Kind"
  • "Wartet Nur"
  • "Die Schlesischen Weber"
  • "Lobgesänge auf König Ludwig"
  • "Enfant Perdu"
  • "新上任的亚历山大大帝
  • “最后的战争”
  • "他不在犯罪现场的证据"
  • "失去的赌注"

Für die letzten vier kann ich die deutschen Titel nicht finden.

Die Tongji Uni war in 1907 bei einem deutschen med. Doktor gegründet und ist eins der wichtigsten akademischen Austauschszentren zwischen China und Deutschland.

Nach den Studien war ich auch bei deutschen Unternehmen wie Heimann Opto-Elektronik (damals eine Siemens Tochterfirma), der damaliger Deutsche Babcock and auch TüV Rheinland in China angestellt und deswegen bin ich ganz bequem mit deutscher Sprache, Handel und Industrie zu jenen Zeiten.

Jedoch seit dem Millenium bin ich mich getrennt von der deutschen Welt, und seitdem habe ich kaum Kontakte mit der deutschen Nation,physikalisch etwa,weil ich eigenständig geblieben bin und nun habe ich viel weniger Chancen mit den deutschen Räume, nachdem ich mich an mein Heimatdorf hier etwa 180 km südwestlich Schanghai angesiedelt habe.

Jedoch habe ich mich nie aufgehört, deusch weiterzustudieren. Mit Internet kann ich noch zu deutschen Websiten gehen, und manchmal kann ich auch einige Romane auf deutsch herunterladen und zuhause ruhig lesen. Aber ich möchte doch mit deutschsprachigen Leuten in Kontakt nehmen, sich über deutsche Literatur diskutieren, und sich miteinnander über tägliches Leben unterhalten. Überdies möchte ich auch einen Deutschen Kulturklub gründen. Ich weiß nicht, ob es so ähnliches schon gibt oder nicht.

Und was als bedeutendest ist, daß ich eine Biographie über meine Mutter schreiben, und vielleicht auch diese ins deutsch übersetzen will. Meine Mutter war letztes Jahr gestorben, für mich, am Alter 81. Ihre Biographie zu schreiben wird meine wichtigste Aufgabe meines Lebens. Und ich konnte vieleicht auch meine Autobiographie schreiben, vielleicht auch auf deutsch, neben Chinesisch und Englisch. Diese Schreibensprojekte werden jahrelang dauern, und sind auch abhängig davon, wie gut meine Lebenssituation aussehen könnte.

Nun, bitte sagen Sie mir, ob Sie mir bei meiner Studie deutscher Literatur helfen könnten oder nicht. Ich wollte manchmal nach Schanghai oder andere Städte fahren, um sich mit deutschen Freunden zu treffen. Vielleicht könnten Sie mir schon einige vorschlagen und einführen.

Eine weitere Möglichkeit wäre es, daß ich wieder für deutsche Unternehmen oder Organisationen arbeiten kann. Ich kann nur sehr schwierig mit der außen Welt kommunizieren, wenn ich in einem isolierten kleinen Dorf lebe.

Noch weitere Möglichkeit wäre es jedoch, daß ich mit meinen Erfahrungen und Kenntnissen deutsche Firmen, Technologien und Produkte in die Provinz Zhejiang einführen kann. Es gibt jetzt nicht viel deutsche Anwesentheit hier in der Provinz, während es viel zu viel dort in Schanghai schon existiert.

Und natürlich bin ich auch interessiert für die Übersetzung deutscher Literatur ins chinesisch und umgekehrt, wie ich vor gut 37 Jahre getan habe, obwohl ich keine Ahnungen zur Veröffentlichung im Kopf gehabt habe, damals.

Vielen dank im voraus und mit meinen besten Grüssen!

Mark Chen
aus Huzhou, Provinz Zhejiang, VR China
Weitere Informationen werden ich Ihnen gerne zur Verfügung stehen.

Email:

markchen2309@mail.com

Mobil:

15968252315


1 German literature (2007)

German literature (2007)

Like IT, I never considered languages as part of my research subjects, with one exception - German, although I was multilingual - English, German, French, Russian and a little Greek, Latin and Hebrew. There was time when I wanted to devote to German language and literature studies and researches, but I gave the plan up after failure to find a research institute to support my plan, such as Goethe Institute. Nevertheless I have spent quite some efforts to study the German literature and to prepare for that studies.

alleandere.doc
austausch.doc
autoren.doc
autoren.docx
autoren1.doc
china_alt.doc
china_alt1.doc
china_alt1xxx.doc
china_neu1.doc
china_neu2.doc
de_lernen.doc
einblick.doc
germanists.doc

German_Resources.doc
German_Resources1.doc
German_Resources2.doc

hochschulen.doc
hochschulen1.doc
magazin.doc
ngos.doc
ngos1.doc
prufung.doc

romane.doc
romane.docx
romane1.doc

TOC_German_Literature.doc
TOC_German_Literature1.doc

ubersetzungsfirmen.doc
websites.doc


7 Alte chinesische Literatur auf deutsch

古典中国文学德译 Alte chinesische Literatur auf deutsch

1. 哲学 PHILOSOPHIE 3
1.1. 孙子兵法， 附注释 SUN ZI: KRIEGSSTRATEGIE 3
1.2. 论语 65
1.3. LAO TSE 92
1.3.1. Das Tao Te King 92
1.3.2. Lao-tzu Tao Te Ching auf Deutsch Uebersetzung von Rudolf Bachofen 134
1.3.3. 老 子 道 德 经(gb) 165
2. 文学 183
2.1. 琴 知 杀 意 QIN SAGT DIE BEDROHUNG VORHER 183
2.2. 路 生 梦 狼 "EIN STUDENT NAMENS LU TRAEUMTE, DASS ER EIN WOLF WAR." 186
2.3. 献 县 冼 宪 贤 XIAN XIAN IM KREIS XIAN IST TUGENDHAFT 189
2.4. 蛇妇DIE SCHLANGENFRAU 190
2.5. 蛇儿DER SCHLANGENMAN 194
2.6. 蛇儿DER SCHLANGENMAN 200
2.7. 歧路亡羊 206
2.8. 蛇人DER SCHLANGENSPIELER 207
2.9. 庄子 ZHUANGZI 210
3. 诗词 DICHTUNG 215
3.1. 葬花诗 － 花谢花飞花满天 DIE BEERDIGUNG DER BLUMEN 215
3.2. 美人首 225
3.3. 陈毅 CHEN YI 227
3.3.1. 大雪压青松 Grosse Last von Schnee liegt auf der Kiefer 227
3.4. 唐 崔护 CUI HU IN TANG DYNASTIE 227
3.4.1. 题 都 城 南 庄 Im suedlichen Dorf des Hauptstadt geschrieben 227
3.5. 杜 甫 DU FU 228
3.5.1. 春 望 Frühlingshoffnung 229
3.6. 唐 - 杜秋娘 DU QIUNIANG 230
3.6.1. 金缕衣 230
3.7. 贺 知 章 HE ZHIZHANG 231
3.7.1. 回乡偶书 231
3.8. 贾岛 JIA DAO 232
3.8.1. 赠剑客 232
3.8.2. 访隐者不遇 232
3.9. 金昌绪 JIN CHANGXU 233
3.9.1. 春 怨 233
3.10. 唐 - 李白 LI BAI 234
3.10.1. 望庐山瀑布 234
3.10.2. 李白乘舟将欲行 234
3.10.3. 将进酒 (Hier kommt der Wein) 235
3.10.4. 独坐敬亭山 (Am Berge Ging-Ting-Schan einsam sitzend) 237
3.10.5. 静 夜 思 239
3.11. 唐 - 李贺 LI HE 240
3.11.1. 此马非凡马 240
3.11.2. 莫 种 树 Pflanze keinen Baum ... 241
3.12. 李商隐 LI SHANGYING 242
3.12.1. 登乐游原 242
3.12.2. 无 题 243
3.13. 毛 泽 东 MAO ZEDONG 248
3.13.1. 沁园春.长沙 249
3.14. 孟浩然 MENG HAORAN 250
3.14.1. 春 晓 250
3.15. 苏轼 SU SHI 251
3.15.1. 惠 崇 春 江 晚 景 (Daemmerungsansicht des Flusses im Hui Chong in Fruehling) 251
3.16. 唐寅 TANG BO HU 252
3.16.1. 把酒对月歌 Mit Wein zum Monde 252
3.16.2. 山外青山楼外楼 253
3.17. 唐 - 王建 WANG JIAN 254
3.17.1. 新嫁娘 254
3.18. 唐 - 王维 WANG WEI 254
3.18.1. 竹里馆 255
3.19. 唐 王之焕 WANG ZHIHUAN IN TANG DYNASTIE 255
3.19.1. 登 鹳 雀 楼 Auf dem Pavillon Guanque 255
3.20. 杨慎（1488-1559），字用修，号升庵 YANG SHENG 256
3.21. 张 继 ZHANG JI 257
3.21.1. 枫 桥 夜 泊 257
3.22. 郑板桥 ZHENG BANQIAO 258
3.22.1. Rundum sind Trauerweiden, ueberall hoert man Kuckuke 东西南北柳树，前后上下杜鹃 258

现代中国文学德译 Moderne chinesische Literatur auf deutsch

1. 诗词 DICHTUNGEN 2
1.1. 花儿为什么这样红？WIESO IST DIE BLUME SO ROT? 2
1.2. 十里平湖霜满天 EISESKAELTE LIEGT UEBER DEN ZEHN LI, 4
1.3. 沧海一声笑 滔滔两岸潮 STUERMISCH PRALLT DER FLUT AN DIE BEIDEN UFER, DAS MEER FREUT SICH 5
1.4. 情非得已 ES IST MEIN SCHICKSAL 7
1.5. 北岛 BEI DAO 9
1.5.1. 一 切 (Alles) 9
1.5.2. 回答 (Die Antwort) 11
1.6. 顾城 GU CHENG 13
1.6.1. 一 代 人 (Eine Generation) 13
1.6.2. 螳 螂 的 婚 事 (Hochzeit einer Gottesanbeterin) 15
1.7. 徐志摩 XU ZHIMO 17
1.7.1. 偶然 (Zufaellig) 17
1.7.2. 再别康桥 (Zweiter Abschied von Cambridge) 18


4 Zusammenfassung deutsches Sprachlernens

“德语学习资料” Zusammenfassung deutsches Sprachlernens
这里收集的是德语学习方面的其他资料的目录：

Deutsche Literaturquelle

Verzeichnis

1. 德语文学概述 2
2. 中德文化交流 3
3. DLK - ERKL?RUNG 4
4. 德语专家及书籍资料 4
5. 德语学习 10
6. 德语/德国学校 10
7. 政府与非政府组织 13
8. 德语翻译 14
9. 外国文学杂志报纸 14
10. 德语考试介绍 14
11. ALLE ANDERE 15
12. 德文网址 15

详细目录见下面的文件：

  • 德语文学资源目录。


8 Chinesische Germanisten

德语文学专家 Chinesische Germanisten
1 德国文学作品集成赏析 8
2 陈良梅 CHEN LIANGMEI 9
2.1 介绍 EINLEITUNG 9
2.2 著作 WERKE 10
2.2.1 《德国转折文学研究》Studie über deutscher übergangsliteratur 10
2.2.1.1 《外国文学如何融入本国精神生活？ ——读《德国转折文学研究》》2005年3月31日 10
2.2.2 德国文学名著汇编: 浓缩本 11
2.3 译作 12
2.3.1 公猫拿破仑——彩乌鸦系列 12
2.3.2 四个半朋友和妙探守则十条 12
2.3.3 四个半朋友和七根黄瓜的秘密 12
2.3.4 四个半朋友和失踪的生物老师 13
2.3.5 四个半朋友和老师办公室的惊叫 13
2.3.6 四个半朋友和网上鳄鱼 13
2.3.7 四个半朋友和“圣诞老人团伙” 13
2.3.8 四个半朋友和机警的花园陶俑 14
2.3.9 主体的退隐[中译文] 14
3 杜美 14
3.1 介绍 15
3.2 著作 15
3.2.1 德国文化史 15
3.3 译作 18
4 范大灿 18
4.1 介绍 18
4.2 著作 18
4.2.1 德国文学史(第一卷)》 18
4.2.2 德国文学史（第二卷） 28
4.3 译作 30
5 范捷平教授 30
5.1 介绍 30
5.2 著作 31
5.3 译作 31
6 方维规 31
6.1 介绍 31
6.2 著作 31
6.2.1 《德国文学中的中国形象，1871－1933 ─ 比较文学形象学研究》（德文） 31
6.3 译作 32
7 冯亚琳 32
7.1 介绍 32
7.2 著作 32
7.2.1 德语文学与文化 33
7.2.2 德语文学与文化--阐释与思辨 34
7.3 译作 36
8 冯至 36
8.1 介绍 36
8.1.1 冯至先生的德国文学史观 36
8.2 著作 38
8.3 译作 38
9 浮梁 38
9.1 介绍 39
9.2 著作 39
9.3 译作 39
9.3.1 阴谋与爱情 39
10 高中甫 39
10.1 介绍 40
10.2 著作 40
10.2.1 《20世纪德国文学史》 40
10.3 译作 42
11 郭力 42
11.1 介绍 42
11.2 著作 42
11.2.1 德国名诗精选精析 42
11.3 译作 43
12 谷裕 43
12.1 介绍 43
12.2 著作 43
12.2.1 现代市民史诗——十九世纪德语小说研究 43
12.3 译作 45
13 韩瑞祥 45
13.1 著作 45
13.1.1 德语文学选集(精)/北京外国语大学外国文学选集丛书 46
13.1.2 《20世纪奥地利瑞士德语文学史》 46
13.2 译作 47
13.2.1 一个无用人的生涯 47
14 李伯杰 47
14.1 介绍 48
14.2 著作 48
14.2.1 德国文化史 48
14.3 译作 50
15 李金發 LI JINFA 50
15.1 介绍 50
15.2 著作 50
15.2.1 德國文學ABC (Deutsche Literatur ABC) 51
15.3 译作 51
16 梁米教授 51
16.1 介绍 51
16.2 著作 52
16.3 译作 52
17 麻文琦 52
17.1 介绍 52
17.2 著作 52
17.3 译作 52
17.3.1 轮下 52
18 马文韬 53
18.1 介绍 53
18.2 著作 53
18.2.1 《瑞士德语文学史》 53
18.3 译作 54
19 孟军 54
19.1 介绍 54
19.2 著作 54
19.2.1 纳粹德国文学史（NEW） 54
19.3 译作 56
20 缪雨露 56
20.1 介绍 56
20.2 著作 56
20.3 译作 56
20.3.1 强盗 57
21 秦露 57
21.1 介绍 57
21.2 著作 57
21.2.1 文学形式与历史救赎:论本雅明《德国哀悼剧起源》——政治哲学文库 58
21.3 译作 59
22 钱文彩 59
22.1 介绍 59
22.2 著作 59
22.3 译作 59
22.3.1 垃圾教授 60
23 孙坤荣 60
24 介绍 60
24.1 著作 60
24.1.1 《德语文学选读》 60
24.2 译作 61
25 卫茂平 61
25.1 介绍 61
25.2 著作 61
25.2.1 中国对德国文学影响史述 61
25.2.2 《德语文学汉译史考辨：晚清和民国时期》 61
25.3 译作 63
26 吴涵志 63
26.1 介绍 63
26.2 著作 64
26.2.1 德国文学简史 64
26.3 译作 64
27 吴麟绶 64
27.1 介绍 64
27.2 著作 65
27.3 译作 65
27.3.1 四川好人 65
28 邢来顺 65
28.1 介绍 66
28.2 著作 66
28.2.1 德国贵族文化史 66
28.3 译作 67
29 薛思亮 68
29.1 介绍 68
29.2 著作 68
29.2.1 现代德语文学选读 (一) 68
29.2.2 现代德语文学选读 （2） 69
29.3 译作 69
30 杨劲 69
30.1 介绍 69
30.2 著作 69
30.3 译作 70
30.3.1 爱米丽雅?伽洛蒂 70
31 杨武能 70
31.1 介绍 70
31.2 著作 70
31.2.1 三叶集：德语文学?文学翻译?比较文学 71
31.2.2 德语文学大花园 73
31.3 译作 75
32 姚紹基 75
32.1 介绍 76
32.2 著作 77
32.3 译作 77
33 叶廷芳 77
33.1 介绍 77
33.2 著作 78
33.3 译作 78
34 余匡复 78
34.1 介绍 78
34.2 著作 78
34.2.1 当代德国文学史纲(正版复印本) 78
34.2.2 德国文学简史 (Kurze Geschichte der Deutschen Literatur) 80
34.2.3 《战后瑞士德语文学史》 83
34.3 译作 83
35 苑建华 83
35.1 介绍 83
35.2 著作 83
35.3 译作 84
35.3.1 米夏埃尔?科尔哈斯 84
36 张宝发/翟永庚 84
36.1 介绍 84
36.2 著作 84
36.2.1 无师自通德语50课(磁带5盘) 85
36.3 译作 85
37 张崇智 85
37.1 介绍 85
37.2 著作 85
37.3 译作 85
37.3.1 德语文学名著丛书:少年维特之烦恼 (缺货) 86
38 张宁 86
38.1 介绍 86
38.2 著作 86
38.3 译作 86
38.3.1 艾菲?布里斯特 87
39 张威廉 87
39.1 介绍 87
39.2 著作 87
39.3 译作 87
40 张玉书 87
40.1 介绍 88
40.2 著作 88
40.2.1 德语文学与文学批评 第一卷.2007年 88
40.2.2 茨威格评传：伟大心灵的回声 88
40.3 译作 89
41 曾新 89
41.1 介绍 89
41.2 著作 89
41.3 译作 89
41.3.1 德国文学史/比较文学与世界文学教研丛书 89
42 朱建华 92
42.1 介绍 92
42.2 著作 92
42.2.1 德语 92
42.2.2 新编大学德语阅读训练3-4. 92
42.2.3 《德语学习》 93
42.2.4 《专业语言复合词的形态、语义和功能》 93
42.2.5 《德汉构词法比较》 93
42.2.6 《从语用及篇章角度观察专业语言复合词》 93
42.2.7 《科技德语的交际方式》 93
42.2.8 《中国大学德语教学的现状和前景》 93
42.3 译作 93
43 朱尚志 94
43.1 介绍 94
43.2 著作 94
43.3 译作 94
43.3.1 动荡中的繁荣--巍玛时期德国文化的详细信息 94


3 Zusammenfassung deutscher Literaten

“德语文学”介绍 Zusammenfassung deutscher Literaten
1 DIE ALT- UND MITTELHOCHDEUTSCHE LITERATUR (750 - 1350) 7
1.1 《梅尔塞堡咒语》(800 -) 8
1.2 《魏索布隆创世歌》(770-790) 8
1.3 DAS HILDEBRANDSLIED《希尔布兰特之歌》《希尔德布兰特之歌》(900 -) 9
1.4 OTFRID VON WEI?ENBURG奥特弗里德 (800 - 870) 9
1.5 WOLFRAM VON ESCHENBACH沃尔夫拉姆?封?埃申巴赫 (1160/80- 1220) 10
1.6 赖因玛尔?封?哈格瑙 (1160～1210) 10
1.7 WALTHER VON DER VOGELWEIDE 瓦尔特?封?德尔?福格威德 (1170-1230) 10
1.8 NEIDHART VON REUENTAL (C.1180–C.1245) 10
1.9 《尼贝龙根之歌》（C.1198～1204） 10
1.10 MECHTHILD VON MAGDEBURG (1207 - 1282) 11
1.11 HARTMANN VON AUE哈特曼?封?奥埃 (1210 - 1220) 11
1.12 《古德龙》《谷德伦》(1210～1220) 12
1.13 GOTTFRIED VON STRA?BURG 戈特夫里德?封?斯特拉斯堡 (1210) 12
1.14 WERNHER DER GARTENAERE (1280-) 12
2 DIE FRüHNEUHOCHDEUTSCHE LITERATUR (1350 - 1600) 12
2.1 JOHANNES VON TEPL (C. 1350 – C. 1415) 13
2.2 JOHANN GEILER VON KAISERSBERG (1445 - 1510)) 14
2.3 JOHANNES REUCHLIN 约翰?罗伊希林 -约翰?赖希林(1455 - 1522) 14
2.4 SEBASTIAN BRANT泽巴斯蒂安?布兰特(1457 OR 1458 - 1521) 14
2.5 ERASMUS VON ROTTERDAM德西德利乌斯? 埃拉斯慕斯 (1466-1536) 14
2.6 THOMAS MURNER (1475 - 1537) 14
2.7 MARTIN LUTHER马丁?路德 (1483-1546) 15
2.8 ULRICH VON HUTTEN乌利希?封?胡登 (1488-1523) 15
2.9 THOMAS MüNTZER 托马斯?闵采尔 (1490 – 1525) 15
2.10 HANS SACHS汉斯?萨克斯(1494-1576) 15
2.11 JOHANN FISCHART菲舍尔特(1548 -1590 OR 1591) 15
2.12 JAKOB BIDERMANN (1578-1627) 16
2.13 GEORG RUDOLF WECKHERLIN (1584–1653) 16
2.14 DOCTOR FAUSTUS 《约翰?浮士德博士的一生》 《浮士德博士的生平》《约翰?浮士德的一生》(1587) 16
2.15 《法力无边的约翰?浮士德博士》(1587) 16
2.16 《希尔德市民故事集》(1597) 16
3 BAROCK (1600 - 1720) 16
3.1 MARTIN OPITZ马丁?奥皮茨 (1597-1639) 17
3.2 FRIEDRICH VON LOGAU (1604-1655) 17
3.3 GEORG PHILIPP HARSD?RFER (1607–1658) 18
3.4 JOHANN VON RIST (1607-1667) 18
3.5 弗莱明(1609-1640) 18
3.6 CHRISTIAN HOFMANN VON HOFMANNSWALDAU (1616 - 1679) 18
3.7 ANDREAS GRYPHIUS格吕菲乌斯 (1616-1664) 18
3.8 PHILLIP VON ZESEN (1619-1689) 19
3.9 HANS JAKOB CHRISTOFFEL VON GRIMMELSHAUSEN汉斯?雅科布?克里斯托弗?封?格里美尔斯豪森 (1622-1676) 19
3.10 SIGMUND VON BIRKEN (1626-1681) 19
3.11 DANIEL CASPER VON LOHENSTEIN (1635-83) 19
3.12 GOTTFRIEND WILHELM LEIBNIZ 莱布尼茨 (1646-1716) 20
3.13 戈特弗里德?奥古斯特?比格尔 GOTTFRIED AUGUST BüRGER (1747-1794) 20
3.14 DANIEL DEFOE (1660-1731) 20
3.15 HEINRICH ANSELM VON ZIGLER UND KLIPHAUSEN (1663-1696) 20
3.16 CHRISTIAN ERNST GRAF ZU STOLBERG-WERNIGERODE (1691-1771) 20
3.17 JOHANN CHRISTOPH GOTTSCHED (1700-1766) 21
3.18 GOTTSCHED, JOHANN CHRISTOPH 戈特舍德 (1700-1766) 21
4 AUFKL?RUNG (1720 - 1785) 21
4.1 ALBRECHT VON HALLER (1708 - 1777) 22
4.2 JOHANN HEINRICH VOSS (1714-1778) 22
4.3 EWALD CHRISTIAN VON KLEIST (1715-1759) 22
4.4 CHRISTIAN FüRCHTEGOTT GELLERT (1715-1769) 22
4.5 JOHANN JOACHIM WINCKELMANN温克尔曼(1717-1768) 23
4.6 FRIEDRICH GOTTLIEB KLOPSTOCK克洛卜施托克 (1724-1803) 23
4.7 GOTTHOLD EPHRAIM LESSING莱辛(1729-1781) 23
4.8 SALOMON GE?NER (1730-1788) 24
5 STURM UND DRANG (1767 - 1785) 25
5.1 JOHANN GEORG HAMANN哈曼 (1730-1788) 26
5.2 SOPHIE VON LA ROCHE (1731 - 1807). 26
5.3 CHRISTOPH MARTIN WIELAND克洛普施托克。维兰德 (1733-1813) 26
5.4 鲁道尔夫?埃里希?拉斯伯（1737-1794） 26
5.5 CHRISTIAN FRIEDRICH DANIEL SCHUBART舒巴特 (1739-1791) 28
5.6 MATTHIAS CLAUDIUS马蒂亚斯 克劳迪乌斯 (1740-1815) 28
5.6.1 Dichtung 28
5.7 JOHANN GOTTFRIED VON HERDER赫尔德(1744-1803) 30
5.8 HEINRICH CHRISTIAN BOIE (1744-1806) 30
5.9 BüRGER, GOTTFRIED AUGUST戈特弗里德?奥古斯特?比格尔(1747-1794) 30
5.10 HEINRICH LEOPOLD WAGNER瓦格纳(1747–1779) 31
5.11 LUDWIG HEINRICH CHRISTOPH H?LTY (1748-1776) 31
6 KLASSIK (1786 - 1832) 31
6.1 JOHANN WOLFGANG GOETHE歌德 (1749－1832) 32
6.1.1 浮士德 (Faust) 36
6.1.2 Dichtung 38
6.2 JOHANN CHRISTOPH FRIEDRICH SCHILLER席勒 (1759-1805) 49
6.2.1 巨星辉映德国文坛------纪念席勒逝世二百年05-11-01 52
7 ROMANTIK (1794 - 1835) 53
7.1 JAKOB MICHAEL REINHOLD LENZ (1751-1792) 55
7.2 JOHANN PETER HEBEL (1760-1826) 55
7.3 JEAN PAUL (1763 -1825) 55
7.4 JOHANN GOTTLIEB FICHTE (1762–1814) 55
7.5 JOHANN GOTTFRIED SEUME索伊默(1763～1810) 55
7.6 维兰德(1766～1767) 56
7.7 AUGUST WILHELM SCHLEGEL奥古斯特?威廉?史雷格尔 - 奥古斯特?威廉?施莱格尔(1767-1845) 56
7.8 JOHANN CHRISTIAN FRIEDRICH H?LDERLIN 约翰?克里斯蒂安?弗里德里希?荷尔德林 (1770-1843) 56
7.9 FRIEDRICH SCHLEGEL弗里德里希?史雷格尔 -弗里德里希?施莱格尔 (1772-1829) 57
7.10 FRIEDRICH VON HARDENBERG [=NOVALIS] 诺瓦利斯原名弗里德里希?封?哈尔登贝尔格 (1772-1801) 57
7.11 FRIEDRICH LEOPOLD (1772-1801) 57
7.12 LUDWIG TIECK鲁德维希?蒂克 (1773-1853) 57
7.13 WILHELM HEINRICH WACKENRODER瓦肯罗德 (1773-1798) 58
7.14 ERNST THEODOR AMADEUS WILHELM HOFFMANN恩斯特?台奥多尔?阿马德乌斯?霍夫曼 (1776-1822) 58
7.15 HEINRICH VON KLEIST亨利希?封?克莱斯特 (1777-1811) 59
7.16 FRIEDRICH DE LA MOTTE FOUQUE (1777-1843) 59
7.17 CLEMENS BRENTANO (1778-1842) 59
7.18 ADELBERT VON CHAMISSO阿德贝尔特?封?沙米索 (1781-1838) 59
7.19 鲁特维希?约阿黑姆?封?阿尔尼姆 -布伦塔诺和阿尔尼姆(1781-1831) 60
7.20 《闵希豪森男爵历险记》（1786） 60
7.21 JACOB UND WILHELM GRIMM格林兄弟：雅科布?格林和威廉?格林 (1785/1786～1859/1863) 60
7.21.1 德国童话之星--不朽的格林兄弟 Gebrüder Grimm 61
7.21.2 格林童话何以诞生在德国？ 64
8 BIEDERMEIER (1815 - 1848) 65
8.1 JUSTINUS KERNER (1786-1862) 66
8.2 KARL LUDWIG BORNE (1786-1837) 66
8.3 LUDWIG UHLAND (1787-1862) 66
8.4 JOSEPH FREIHERR VON EICHENDORFF 约瑟夫?封?艾兴多尔夫(1788-1857) 67
8.4.1 Dichtung 67
8.5 FERDINAND RAIMUND (1790-1836) 69
8.6 FRANZ GRILLPARZER (1791-1872) 69
8.7 GUSTAV SCHWAB (1792-1850) 69
8.8 KARL LEBERECHT IMMERMANN伊默尔曼(1796–1840) 70
8.9 海蒂 70
8.10 JEREMIAS GOTTHELF (1797-1854) 70
9 JUNGES DEUTSCHLAND UND VORM?RZ (1835 - 1848) 70
9.1 HEINRICH HEINE海涅 (1797-1856) 71
9.1.1 Dichtung 71
9.2 ANNETTE VON DROSTE-HüLSHOFF德罗斯特－许尔斯霍夫 (1797-1848) 80
9.3 AUGUST HEINRICH HOFFMANN VON FALLERSLEBEN (1798-1874) 80
9.4 JOHANN NEPOMUK NESTROY (1801-1862) 80
9.5 CHRISTIAN DIETRICH GRABBE (1801-1836) 80
9.6 威廉?豪夫 WLHELLN HAUFF (1802-1827） 81
9.7 EDUARD M?RIKE (1804-1875) 83
9.8 ADALBERT STIFTER (1805-1868) 83
9.9 ANASTASIUS GRüN (1808-1876) 83
9.10 FERDINAND FREILIGRATH弗赖利格拉特 (1810-1876) 84
9.11 KARL GUTZKOW古茨科 (1811～1878) 84
9.12 GEORG BüCHNER 格奥尔格?比希讷毕希纳 (1813-1837) 84
10 REALISMUS (1840 - 1897) 84
10.1 CHRISTIAN FRIEDRICH HEBBEL黑贝尔 (1813-1863) 86
10.2 RICHARD WAGNER (1813-1883) 86
10.3 OTTO LUDWIG (1813-1865) 86
10.4 盖贝尔(1815-1884) 86
10.5 GUSTAV FREYTAG (1816-1895) 86
10.6 THEODOR STORM特奥多?施托姆 - 施笃姆（(1817-1888) 87
10.7 GEORG HERWEGH黑尔韦格 (1817-1875) 87
10.8 THEODOR MOMMSEN特奥多尔?蒙森 (1817-1903) 88
10.9 THEODOR FONTANE台奥多尔?冯塔纳 (1819- 1898) 88
11 MODERNE 88
11.1 GOTTFRIED KELLER凯勒 (1819–1890) 89
11.2 罗伯特?施韦策 (1821-1907) 89
11.3 CONRAD FERDINAND MEYER (1825–1898) 89
11.4 JOHANNA SPYRI 约翰娜?史比里 (1827-1901) 89
11.5 保尔?约翰?路德维希?冯?海塞 (1830-1914) 90
11.6 PAUL HEYSE海泽 (1830 -1914) 90
11.7 WILHELM RAABE (1831-1910) 90
11.8 WILHELM BUSCH 威廉?布施 (1832-1908) 90
11.9 明娜?考茨基 (1837—1912) 91
11.10 盖尔维努斯 (1839 91
11.11 FRIEDRICH WILHELM NIETZSCHE (1844-1900) 91
11.12 李林克隆-李利恩克龙 (1844-1909) 91
11.13 魏尔顿勃洛赫 (1845-1909) 91
11.14 弗朗茨?梅林 (1846-1919) 92
11.15 RUDOLF EUCKEN 鲁道尔夫?欧肯 (1846-1926) 92
11.16 约翰内斯?史拉夫(1862-1941) 92
11.17 GERHART HAUPTMANN霍普特曼 (1862－1946) 92
11.18 RICHARD DEHMEL 戴默尔 (1863-1920) 94
11.19 阿尔诺?霍尔茨 (1863-1929) 94
11.20 盖奥尔格 (1868-1933) 94
11.21 亨利希?曼 (1871-1950) 95
11.22 HUGO VON HOFMANNSTAHL霍夫曼斯泰尔 (1874-1929) 95
11.23 RAINER MARIA RILKE里尔克 (1875－1926) 95
11.24 托马斯?曼 (1875-1955) 96
11.24.1 托马斯.曼－揭露丑陋德国人的德国作家 (1875-1955) 96
11.25 HERMANN HESSE黑塞 (1877－1962) 97
11.25.1 黑塞——想变成中国人的德国人 98
11.25.2 Dichtung 100
11.26 ALFRED D?BLIN艾弗烈?德布林 - 阿?德布林 (1878—1957) 101
11.27 ERICH MüHSAM埃里希?米萨姆 (1878-1934) 101
11.28 CARL SPITTELER卡尔?施皮特勒 () 101
11.29 ROBERT WALSER罗伯特?瓦尔泽 (1878-1956) 101
11.30 R. ROBERT MUSIL穆齐尔 (1880－1942) 102
11.31 ACHIM VON ARNIM阿尔尼姆 (1881-1940) 102
11.32 STEFAN ZWEIG斯蒂芬?茨威格 (1881－1942) 102
11.33 FRANZ KAFKA卡夫卡 (1883－1924) 102
11.33.1 现代派文学大师 - 卡夫卡 103
11.34 F LION EUCHTWANGER福伊希特万格-利翁?福伊希特万格 (1884–1958) 108
11.35 GEORG TRAKL特拉克尔 (1887-1914) 108
11.36 HANS MARCHWITZA马尔希维查 (1890-1965) 108
11.37 ERICH WEINERT魏纳特(1890～1953) 108
11.38 J.R.BECHER约翰尼斯?贝希尔 (1891-1958) 108
11.39 瓦尔特?本雅明：(1892-1940) 109
11.39.1 现代“文人”：本雅明和他笔下的波特莱尔 109
11.40 ERNST TOLLER恩斯特?托勒尔 (1893- 1939) 112
11.41 汉HANS FALLADA斯?法拉达 (1893—1947) 112
11.42 NELLY SACHS奈莉?萨克斯 (1891-1970) 112
11.43 TILL EULENSPIEGELS LUSTIGE STREICHE 《梯尔 ?欧伦施皮格尔》民间故事 (1894～1895) 113
11.44 CARL ZUCKMAYER楚克迈耶 (1896～1977) 113
11.45 ERICH MARIA REMARQUE雷马克（(1898－1970) 113
11.46 BERTOLT BRECHT 贝托尔德?布莱希特 (1898-1956) 113
11.46.1 Dichtung 114
11.47 ERICH KASTNER凯斯特纳 (1899～1974) 118
11.48 安娜?西格斯 (1905- ) 118
11.49 STEPHAN GEORGE KUTTNER施特凡?格奥尔格 (1907- 1996) 121
11.50 CLAUDE LéVI-STRAUSS列维-斯特劳斯 (1908 - ) 122
11.51 MAX FRISCH马克思?费里施，(1911-1991) 122
11.52 MAX FRISCH 马克斯?弗里施 (1911- 1991) 122
11.53 ROLAND BARTHES罗朗?巴特 (1915- ) 128
11.54 KURT HüBNER许布纳尔 (1915- ) 128
11.55 HEINRICH BOLL海因里希-伯尔 (1917－1985) 129
11.56 HANS BLUMENBERG布鲁门贝尔格 (1920 -) 129
11.57 MARCEL REICH-RANICKI马塞尔?赖希-拉尼茨基 (1920 - ) 129
11.57.1 赖希—拉尼茨基“文学教皇”与格拉斯——德国最著名评论家和最著名作家之间的恩恩怨怨/ 2000-10-07 129
11.58 FRIEDRICH DüRRENMATT 弗里德里希?迪伦马特 (1921 - 1990) 131
11.59 IHAB HASSAN哈桑 (1925 - ) 131
11.60 SIEGFRIED LENZ西格弗里德?伦茨 (1926 - ) 131
11.60.1 德国经典小说《德语课》中文新译本问世 132
11.61 GüNTER GRASS 君特-格拉斯 (1927 - ) 132
11.61.1 《铁皮鼓》Blechtrommel 136
11.61.2 狗年月"Hundejahre" (1963) 136
11.61.3 猫与鼠"Katz und Maus" (1961) 136
11.61.4 《比目鱼》"Der Butt" (Roman, 1977) 136
11.61.5 长篇小说《辽阔的田野》"Ein weites Feld" (1995) 136
11.61.6 "Die R?ttin" (1986) 137
11.61.7 "Unkenrufe" (Erz?hlung 1992) 137
11.61.8 "Mein Jahrhundert": (1999) 137
11.61.9 "Im Krebsgang" (2002) 137
11.61.10 Günter Grass - Biografie und Werk 137
11.61.11 德国诺贝尔文学奖获得者君特-格拉斯1999年12月13日 139
11.62 HEINER MüLLER海纳?米勒 海纳尔?米勒（1929-1995） 140
11.63 CHRISTA WOLF克里斯塔?沃尔夫（1929-） 140
11.64 THOMAS BERNHARD 托马斯?伯恩哈德 (1931-1989) 145
11.65 ALEXANDER KLUGE亚历山大?克鲁格 (1932- ) 146
11.66 彼特?黑尔特林 - 彼特?赫尔特林 (1933- ) 147
11.67 ULRICH PLENZDORF乌尔里希?普伦茨多夫 (1934-2007) 148
11.68 HERBERTACHTERNBUSCH 赫伯特?阿赫特布施 (1938 - ) 148
11.69 VOLKER BRAUN弗尔克?布劳恩 (1939- ) 148
11.70 乌韦-提姆 (1940 - ) 149
11.70.1 德国著名作家乌韦-提姆先生在我校举办作品朗诵会 149
11.71 PETER HANDKE汉德克 (1942 - ) 149
11.72 ELKE HEIDENREICH 埃尔克?海登赖希 (1943 - ) 150
11.73 CHRISTOPH HEIN克里斯多夫?海因 - 克里斯朵夫?海茵 (1944-) 150
11.74 BOTHO STRAU?博托?施特劳斯 (1944– ) 151
11.75 BERNHARD SCHLINK 本哈德﹒施林克 (1944 - ) 151
11.76 ELFRIEDE JELINEK艾尔弗雷德?耶利内克 (1946 - ) 152
11.77 PATRICK SüSKIND帕特里克?聚斯金德 (1949 - ) 157
11.78 MARTIN MOSEBACH 马丁?莫泽巴赫 (1951 -) 159
11.79 CHRISTOPH RANSMAYR克里斯托夫?兰斯迈尔 (1954 - ) 160
11.80 JON FOSSE琼?弗瑟 (1959 - ) 160
11.81 INGO SCHULZE 英果?舒尔策 (1962 - ) 160
11.82 DEA LOHER德阿?洛尔(1964 - ) 161
11.83 FERIDUN ZAIMOGLU 费里顿?蔡莫格鲁 (1964 - ) 161
11.84 ROLAND SCHIMMELPFENNIG罗兰德?西莫尔普芬尼希 (1967 - ) 161
11.85 ARNO GEIGER 阿尔诺?盖格 (1968 - ) 161
11.86 GESINE DANKWART葛西娜?当克瓦特 (1969 - ) 162
11.87 JUDITH HERMANN尤迪特?海尔曼 (1970 - ) 162
11.88 JAKOB HEIN 雅各布?海因 (1971 - ) 162
11.89 IWAN WYRYPAJEW伊万?维利帕耶夫 (1974 - ) 163
11.90 JULI ZEH 朱丽?泽 (1974 - ) 163
11.91 BAS B?TTCHER 巴斯?波特舍 (1974 - ) 164
11.92 DANIEL KEHLMANN 丹尼尔?凯尔曼 (1975 - ) 164
11.93 维罗尼卡?彼得斯 165
11.94 克里斯多夫?彼德斯 165
11.95 彼得?施达姆 165
11.96 塔尼亚?丢克斯 165
11.97 蒂莫?布伦克 165
11.98 伊利亚?特罗亚诺夫 166
11.99 塔尼亚?杜克斯 166


2 Einfürung

“德语文学”简介 Einfürung
1 AUTOREN 3
2 作品精选 4
3 文学分期 4
4 作品分类 16
5 德语文学网站 19
6 引言 19
7 德国文学 （范大灿） 21
8 德国文学的拯救者--丹尼尔?凯尔曼2006年07月07日 28
9 德国文学中的后现代印痕 29
10 2007-05-12 | 德语文学史 33
11 二十世纪德语文学发展概况 2005-12-27 36
12 20世纪德国文学回顾（世纪回眸） 38
13 十九世纪末前的德语文学世界 2007-08-20 41
14 德国文学史 (德语版） 42
15 德国古典文学　（范大灿） 59
16 欧洲文学史 - 德国文学 60
17 柏林墙倒塌之后的德国新文学 苌苌=文 2006年11月28日 62
18 政治史与思想史路径中的德国文学：2006-1-9 64
19 德国文学2005-12-22 66
20 德国文学：2005-10-27 67
21 德国文学的历史 74
22 请问为什么德国文学在巴洛克时期没有产生比较有影响的作品？ 80
23 狂飙突进运动 81
24 神话思维与理性精神——论当代德国文学中的后现代主义 82
25 德国文学：老的不去 新的已来2007-09-18 88
26 德国文学选读 92
27 德国文学和莱辛 2005-12-22 97
28 德国文学和歌德、席勒 102
29 德国文学和海涅、维尔特 114
30 德国中青年作家的文学世界2007-09-08 120
31 瑞士德语文学的发展2005-05-06 122
32 新教文化与德语文学 兼谈德语启蒙文学中牧师身份的作家2006-12-07 123


9 Deutsche Literature im Netz

德语文学网站 Deutsche Literature

在这个部分，我准备将德语文学作全面介绍，特别是当代文学。目前我还没有发现专门的网站介绍德语文学。

In dieser Rubrik habe ich vorgehabt, eine volle Einfürung der deutschen Literatur zu erwirklichen, insbesondere der modernen deuschen Literatur. Bis jetzt habe ich noch keine Website gefunden, die sich ausschliesslich zu diesem Zweck gebaut ist.

我正在陆续收集整理扥与文学的资料，目前还处于初级阶段。以下是目前收集的资料的目录。这个目录将不定期更新：有需要其中内容的清与我联系。

Ich bin in dem Zug der Sammlung der Materialien aus verschiedenen Informationsquellen, deswegen diese Website ist noch am Anfang des Aufbaus. Folgendes sind ein Verzeichnis, das oftenmals erneut werden sollte. Falls Sie irgendwelche davon brauchen, bitte ruhig mit mir in Kontakt nehmen!


6 übersetze Werke

德语文学译作 Übersetze Werke
1 布莱希特(BERTOLT BRECHT) 3
1.1 四川好人 3
2 冯?艾兴多夫(JOSEPH VON EICHENDORFF) 3
2.1 一个无用人的生涯 3
3 冯塔纳(THEODOR FONTANE) 4
3.1 艾菲?布里斯特 4
4 GOETHE 4
4.1 德语文学名著丛书:少年维特之烦恼 (缺货) 4
5 古琼?高乐 GUDRUN GORLA 4
5.1 德国文学史/比较文学与世界文学教研丛书 5
6 黑塞(HERMANN HESSE) 7
6.1 轮下 7
7 克莱斯特(KLEIST,H.VON) 7
7.1 米夏埃尔?科尔哈斯 7
8 莱辛(LESSING,G.E.) 8
8.1 爱米丽雅?伽洛蒂 8
9 亨利希?曼(HEINRICH MANN) 8
9.1 垃圾教授 8
10 克利斯托夫?彼得斯等 9
10.1 红桃J当代德语小说集 /《红桃——德语新小说选》 9
11 席勒(FRIEDRICH SCHILLER) 10
11.1 阴谋与爱情 10
11.2 强盗 10
12 吴涵志（WUST,K）KARL-HZ-INZ-WUST 11
12.1 德国文学简史 11
13 斯蒂芬.茨威格 11
13.1 人类命运攸关的时辰-德语文学精品读(德汉对照)南开德语系列读物 11


Languages

Today (September 12, 2016) I am only reporting on my English learning activities, but just yesterday I have determined to give up all my other languages – German, French, Russian, Esperanto, Greek, Latin, and Hebrew. They are in different level of proficiency. It took me 11 years to make this fatal decision. It was one of my most painful decisions since I have spent 3 decades on language studies consistently and roughly speaking, about 1/5 to 1/5 of my past life was spent on languages. That was a huge loss to me, and rather a major loss of life. But I have no other choice. The reasons is again the same as I have given up computer chip studies as described in the “graph theory” section. What’s more, all these languages except English are no more useful in my life and career.

Some language certificates
  • 01ielts1992.jpg - IELTS (International English Language Test System) score
  • 02gre1992.jpg - GRE score
  • 03toefl1993.jpg - TOEFL score

为什么学那么多外语？

世界上估计没有一个国家的人民象中国人那样花费如此巨大的努力去学别人的语言。 绝大多数中国人似乎从幼儿园开始就准备学好英语，以便有朝一日留学移民。世界上没有那一个国家的国民象中国人那样为了离开自己的国家而不顾一切。这里必定有某种很奇怪的因素起作用。什么因素？笔者愚拙，不得其解。

我不能说自己有语言天才。这个世界上什么奇迹都有，但都轮不到我。 论语言天才，据我所知，就有俄罗斯人会100种语言，有13岁少年会13种语言等等。数不胜数的例子。

俄语是我们那个时代的必修外语， 就如同现在的英语，因为当时中苏友好（不过等我们学的时候中苏已经交恶，而且在黑龙江珍宝岛打了一架，还好只是热身）。

德语是因为某某大学要跟德国恢复传统的交往， 而这个大学是原来德国人创办的（当今中国的许多老牌大学多有西方教会等背景），而我恰巧被选中进入那个德语班。

法语纯粹是个人的爱好，没有人叫我学，当时也没有说要用到哪里去。

英语也是我自学，只花了6个月就通过了英语硕士考试。 我学英语的出发点是，没有英语，等于是聋子，德语法语不管用。

世界语纯粹是爱好，当时1982-1984年间在神州大地掀起了学世界语热，我也置身其中。

希腊语是很晚才学的，是因为意识到，现代（西方）文明 – 语言，科学，文化，艺术等都来自希腊。 当然，希腊文化又来自古代叙利亚，伊拉克，埃及，阿拉伯一带（可以说西方文明源自阿拉伯世界）。 作为一个学者， 就必须懂得希腊语， 阅读希腊语原著，尤其是欧几里德的“几何原本”。 学希腊语的另一个原始冲动是我当时热终于基督教（现在当然已经消退），而所谓“圣经”的新约的原文就是由希腊语写成。但希腊语之难不是一般人所能克服的。 相比之下， 德语法语俄语真是容易极了。 例如，一个只有2个字母的动词，经变换后，增加到十几个字母，跟原来的字母完全看不出来，没有任何痕迹的地步。单词变格之多令人眼花缭乱。 过去，西方学校里希腊语是必修课，现在如何不得而知。

学希伯来语纯粹是当时对基督教的狂热，不过基本上没有学到什么。过去我跟许多人一样，把犹太人捧得很高，看作是世界上最优秀的民族或至少是之一。 但我现在不怎么看。 前一段时间报道，他们的前总统犯猥琐女性罪判了刑坐监了。 我接触的以色列人也不过如此。 以色列人会赚钱是事实，那也不过是近畿百年的事情，他们在科学，文化，等等领域有不俗表现， 也是在最近几百年的事。 犹太人为了金钱可以不顾一切，所以世界各国都很反感犹太人。 莎士比亚的戏剧就有讽刺犹太人的。 但跟希腊相比，就不是一个等级的了。 希腊文明奠定了现代文明的基础， 而犹太人只是会赚钱， 同时在某些科学领域作出了巨大贡献（爱因斯坦就是犹太籍德国人）。

这些语言就是这样陆陆续续学到的了。在我职业生涯的前期， 有些是发挥了巨大作用， 有些根本是点缀而已。

俄语从未派过用场， 唯一一次是上个月跟一个俄罗斯人谈发电设备业务，后来我俄语不想写了就不跟他谈了。

德语是我过去十几年职业生涯的基础。我在西门子，巴高克，莱茵技术等德国公司，德语充分发挥了作用。

法语也在阿尔斯通工作期间稍微有点用场， 特别是跟公司高层交往时，因为法国人特别感冒英语。

世界语没有半点用处。 前一段时间我还想跟世界语爱好者通过世界语交流，可惜没有任何反应。

英语就不言自明了。

希腊语没有用。

希伯来语更没用。

在最近的11年里， 我时不时在想，到底要不要维持那么多外语。 跟过去不同， 除了英语，其它外语都没有用场了。 我不可能再有去德国，法国，美国或其它国家公司工作的机会， 也没有去那些国家的大学研究机构搞研究的机会（这些事情我以后会提到），一句话， 什么机会都没有。居然这样，还要维护这些语言干嘛？这些问题困扰我11年，有时决定彻底放弃，有时又舍不得放弃，来来回回反反复复考虑决定撤回决定等等等等，整整11年时间，最后才真正决定，还是保留，不过希伯来语和世界语就彻底放弃。 我的基本出发点是，我保留的语言要我比较能使用，而且有许多伟大的作品可阅读。

但不管怎样， 对一般人来讲， 我建议除了英语， 不必再去学其它语言。除非你有特殊情况。

I started to learn Russian – my first foreign language – at high school at home. I did quite well at it, and could get a fairly good score in an entry exam to University four years later. But I have not shown any special talent in language learning after well three to four years when I have completed my German studies at Tongji University. Only afterwards I was very much attracted by foreign languages and their cultures and by then I have already completed the studies of basic languages skills of English, German, French, Russian and even Esperanto, an universal and man-made language. Among them, only Russian and German were learned through school teachers, the rest three by self-studies.

After finishing my schools, I’ve never stopped learning foreign languages and reading their literatures for a single days, to maintain at least or even to improve them a little bit. For example I was able to work in a number of foreign companies of nationalities of the U.S., U.K., Germany, France and several others, so at that time period I was able also to practice thus to improve my spoken English, German, and French. Around 1991/2 I passed an IELTS done at the British Embassy in Beijing with an overall score of 7.0 – which is considered high as the highest is 10.0 -? and my oral score was even 9.0 and the examiner commented my oral English as “near native”.

But in all I have not made major progress in all of these languages, either in depth or in width. I’ve not tried to learn more languages nor to learn more sophisticated linguistics such as literatures.

However, just a year ago (it was about 2007, but this essay was written in about 2008), out of my desire to study ancient Greek, Latin science literatures and Hebrew Scripture, I was very keen to learn these languages, after a year’s delay and hesitation, I finally decided to move on with the studies of these three languages. Although language studies are now not among my priority, I still plan to finish the studies in about three years, so that I will be able to understand the basics of these languages after three years. I will also complement my studies with listening practices and literature reading, not just lessons.

So as a result I have to maintain a total of 8 languages in different level of competency:

  • English at working level
  • German quite OK
  • French so and so
  • Russian simple reading
  • Greek a few sentences
  • Latin mamahuhu
  • Hebrew almost nothing
  • Esperanto a few words but will soon replace English as my working language.

I consider it absurd to learn a language of another nationality and in the end I shall only use a world language that is most likely Esperanto. There are hundreds of world languages, but I don't want to research which one is the best for me, because Esperanto is the one I learned the earliest and so far the only world language.

Language Studies

Every student starts learning a foreign language in China after their primary school.

At my days we all were learning Russian, although China and the Soviet Union were fighting for more than a decade since the early 60's. Apparently there was no alternatives - english, german, french all capitalistic, Japan our traditional rivalry and what else ?

I don't have talent in language - I was a shy, taciturn and introvert boy. To speak chinese makes me even uneasy in some cases, not talking foreign languages. It is completely a mistake to work in that direction, but no other choices.

Enrolled at Tongji, I continued my Russian studies, and my scores were quite good. I was able to read some scientific literature such as math, physics. I studied for a semester then as you know I was regrouped in a german class. After the german class, I continued my Russian studies, and at the same time also my german studies during my bachelor studies from 1978 to 1983.

At that time, learning materials were scarcely to be found. I went to the foreign language bookstore at Fuzhou Road not far from the People's Square, and bought whatever was available. I also went to the Shanghai Library located at the end of the East Nanjing Road close to the Square to find any german literature.

About two years before graduation in 1981, I found people were all learning english, was also found that english is more popular and useful than my languages. If I couldn't learn english, it might be difficult to survive in the world. And I turned to english, and happily to find it much easier to learn, especially if you have already learned russian and german whose grammars were much more complex than english. For example, russian and german verbs, adjectives have to be changed along with the subjects, english have not such necessary or much simpler. The "Nebensatz" or subordinate sentences are very complicated in german, and many times I would simply forget to put the verbs at then end in speaking. The prepositions are also sophisticated, and even today they make me headaches.

There are no other tips as reading, writing, speaking and listening if you want to command a language. I read every book I can found, newspaper, magazines, radio and so on. And you must learn it in an intensive and fast pace - I remembered about 50 new words a day. And a book took me normally a week or so for a quick reading. Of course, I will come back later, perhaps more than once, or never if this is only a light reading. Nowadays, my learning speed is even faster. I remember the Spring Festival day in 1992, when I have to stay in Shenzhen, I managed to finish reading an english novel of 500 pages in a day or two. And in 1999-2000 period, very often I bought a IT book of 300 pages, and the next morning, it was a old book - hence I vowed never to buy IT books ever since.

If you try to learn a language by "Daily Collection and Monthly Accumulation" approach, I would say, the failure rate will be high. It is my firm view that to accomplish something you have to be quick and decisive. A moment's hesitation means a total retreat in many cases.

After six months' diligent studies, my english level caught up with others' and I was thinking about other languages - french. In fact, I tried japanese, but the strange characters (like old chinese signs) prevented my learning desire. French was much more difficult. Particularly the pronunciation. Without a good teacher you have difficulties to learn that language. The techniques in english learning cannot be simply implanted into french. I was too confident in learning languages so I attended no school and very seldom listened to radio, cassettes or conversed with french speaking people.

Nevertheless, I ventured to conquer that language, one year before my bachelor graduation. At the same time, I also started learning Esperanto, an artificial language invented by a polish doctor in the late 19's century. Esperanto combines the grammar, vocabularies and syntaxes of the major european languages and therefore is easy to learn, but easy to forget as well, because its use is rarely to be found. I have no single word of Esperanto now, as with Russian.

As your language base becomes larger and larger, your time spent on learning, maintaining and improving those languages will be more and more. More than 1/3 of my time has been devoted to languages and sometime I found it not worthwhile.

During my postgraduate studies, I continued my studies in English, German and French but forgot all others. I couldn't manage the others. If I don't want to be a linguist then stop there.

I have studied relatively more languages, not for immigrating to other countries. Like many other colleagues, I am also not keen to leave China for a better life in western countries. By mastering the prevailing world languages, I am freely accessibly to all information of the outside world so that nobody can cheat me. Just like mastering the IT technologies has opened the information age in front of me, although I don't need to be a linguist or an IT industrialist.

Now language skills are still one of my strong points and will remain to be one of my qualifications for my career and daily life. It's fun to learn a language and a culture.

Languages - tools to other worlds

Languages - either spoken or in writing - are the most important instruments of mankind for understanding other people of the same race or other races, and to the daily life. Without languages no mankind.

The first language which I knew is of course my mother language, the language my mother spoke or speaks before and after my birth and also now. It's not the native language - the mandarin or the dialect of my hometown though. The mother language is the most important language in my whole private life.

Then the family language, which comes a little different from the dialect in my hometown, as every family has its own language. The dialect is also a language which I can never forget. Our dialect is covered in the surrounding areas of the so-called WU culture region, an area that includes the southern Jiangsu province, Shanghai and the northern Zhejiang province. Within this region man can understand each other without much difficulty. Nevertheless there are hundred of variations - the smaller or larger - among different counties, towns even villages.

Mandarin (Putonghua) is the legal language of China, which origins from the north. Mandarin is being used through my life and career in China.

The first "foreign language" was the Russian, which I started to learn in 1976. Until 1989 I can still read Russian literature, but I nearly know no single Russian word now. That is very unfortunate. Russia is one of the greatest countries in the world. I believe, in few years Russia will become strong again.

The second foreign language is now the German, which I have studies and used very intensively ever since 1979. But my writing abilities and speaking are now only about 40-50% of my best time (around 1989).

English comes already very late. One year before my graduation from university study I decided to learn English. I was of the opinion, without English one can't survive, although I had already rather good Russian and German. Within half a year I had a quite reasonable English already, And what's more, I took the entry exam of master degree where I chose English as foreign language, not German.

I have also strong desire for French however it sounds difficult to me. From 1982 I began to study French, however my french level is not high. At my best time I can only understand 70% spoken French, now I can only read the simplest french literature.

In the the 80's years I have also tried several other languages, like Esperanto, Japanese, but the attempt did not last long. After the graduation in 1983 and 1989 I have hardly time to learn other languages. Then I have also scarcely time to improve the existing languages.

Languages are not my specialty, but they took me 1/4 - 1/3 of my time, and now perhaps a little more (50%).

(machine-translated from German, sounds strange ???)

Multilinguistic

Multilinguistic has become a special label of mine to differ me from other people. Each time I am introduced to new friends, they always say oh Mr Chen can speak several languages, great! And they wonder how I can manage the four without confusion.

Over the last 30 years or so, I have been spending at least one hour on reading foreign language materials.

I will continue to read literatures and some of the other cultural relics of the four major languages – English, German, French and Russian to keep my language level not declining too quickly. I am not planning to improve my linguistic competence, but I also don’t want say farewell to them because I have spent too much time on them.

I’m now proficient in English, German and French with some basics in Russian and am still planning to expand this listing.

I also used to have a plan to devote completely to the studies and teaching of German literature, therefore I have learned quite intensively the German literature from Classic to Post-modern.

I also plan to give up all other studies, leaving only the above two areas – a little foreign languages and lots of Solar and Solar Aviation.

Ironically, I didn’t like foreign languages at all at the beginning of my university days, but some time around the early 80’s, suddenly I found foreign languages very fun, and ever since I have been keeping learning these languages – English, German, French and Russia – occasionally also some others – till now. It’s part of my life now.

Here below some history of language studies.

I started to learn Russian – my first foreign language – at high school at home. I did quite well at it, and could get a fairly good score in an entry exam to University four years later. But I have not shown any special talent in language learning after well three to four years when I have completed my German studies at Tongji University. Only afterwards I was very much attracted by foreign languages and their cultures and by then I have already completed the studies of basic languages skills of English, German, French, Russian and even Esperanto, an universal and man-made language. Among them, only Russian and German were learned through school teachers, the rest three by self-studies.

After finishing my schools, I’ve never stopped learning foreign languages and reading their literatures for a single days, to maintain at least or even to improve them a little bit. For example I was able to work in a number of foreign companies of nationalities of the U.S., U.K., Germany, France and several others, so at that time period I was able also to practice thus to improve my spoken English, German, and French. Around 1991/2 I passed an IELTS done at the British Embassy in Beijing with an overall score of 7.0 – which is considered high as the highest is 10.0 -? and my oral score was even 9.0 and the examiner commented my oral English as “near native”.

But in all I have not made major progress in all of these languages, either in depth or in width. I’ve not tried to learn more languages nor to learn more sophisticated linguistics such as literatures.

However, just a year ago (it was about 2007, but this essay was written in about 2008), out of my desire to study ancient Greek, Latin science literatures and Hebrew Scripture, I was very keen to learn these languages, after a year’s delay and hesitation, I finally decided to move on with the studies of these three languages. Although language studies are now not among my priority, I still plan to finish the studies in about three years, so that I will be able to understand the basics of these languages after three years. I will also complement my studies with listening practices and literature reading, not just lessons.

So as a result I have to maintain a total of 8 languages in different level of competency:

  • English at working level
  • German quite OK
  • French so and so
  • Russian simple reading
  • Greek a few sentences
  • Latin mamahuhu
  • Hebrew almost nothing
  • Esperanto a few words but will soon replace English as my working language.

I consider it absurd to learn a language of another nationality and in the end I shall only use a world language that is most likely Esperanto. There are hundreds of world languages, but I don't want to research which one is the best for me, because Esperanto is the one I learned the earliest and so far the only world language.

Languages

Today (September 12, 2016) I am only reporting on my English learning activities, but just yesterday I have determined to give up all my other languages – German, French, Russian, Esperanto, Greek, Latin, and Hebrew. They are in different level of proficiency. It took me 11 years to make this fatal decision. It was one of my most painful decisions since I have spent 3 decades on language studies consistently and roughly speaking, about 1/5 to 1/5 of my past life was spent on languages. That was a huge loss to me, and rather a major loss of life. But I have no other choice. The reasons is again the same as I have given up computer chip studies as described in the “graph theory” section. What’s more, all these languages except English are no more useful in my life and career.

Some language certificates
  • 01ielts1992.jpg - IELTS (International English Language Test System) score
  • 02gre1992.jpg - GRE score
  • 03toefl1993.jpg - TOEFL score

为什么学那么多外语？

世界上估计没有一个国家的人民象中国人那样花费如此巨大的努力去学别人的语言。 绝大多数中国人似乎从幼儿园开始就准备学好英语，以便有朝一日留学移民。世界上没有那一个国家的国民象中国人那样为了离开自己的国家而不顾一切。这里必定有某种很奇怪的因素起作用。什么因素？笔者愚拙，不得其解。

我不能说自己有语言天才。这个世界上什么奇迹都有，但都轮不到我。 论语言天才，据我所知，就有俄罗斯人会100种语言，有13岁少年会13种语言等等。数不胜数的例子。

俄语是我们那个时代的必修外语， 就如同现在的英语，因为当时中苏友好（不过等我们学的时候中苏已经交恶，而且在黑龙江珍宝岛打了一架，还好只是热身）。

德语是因为某某大学要跟德国恢复传统的交往， 而这个大学是原来德国人创办的（当今中国的许多老牌大学多有西方教会等背景），而我恰巧被选中进入那个德语班。

法语纯粹是个人的爱好，没有人叫我学，当时也没有说要用到哪里去。

英语也是我自学，只花了6个月就通过了英语硕士考试。 我学英语的出发点是，没有英语，等于是聋子，德语法语不管用。

世界语纯粹是爱好，当时1982-1984年间在神州大地掀起了学世界语热，我也置身其中。

希腊语是很晚才学的，是因为意识到，现代（西方）文明 – 语言，科学，文化，艺术等都来自希腊。 当然，希腊文化又来自古代叙利亚，伊拉克，埃及，阿拉伯一带（可以说西方文明源自阿拉伯世界）。 作为一个学者， 就必须懂得希腊语， 阅读希腊语原著，尤其是欧几里德的“几何原本”。 学希腊语的另一个原始冲动是我当时热终于基督教（现在当然已经消退），而所谓“圣经”的新约的原文就是由希腊语写成。但希腊语之难不是一般人所能克服的。 相比之下， 德语法语俄语真是容易极了。 例如，一个只有2个字母的动词，经变换后，增加到十几个字母，跟原来的字母完全看不出来，没有任何痕迹的地步。单词变格之多令人眼花缭乱。 过去，西方学校里希腊语是必修课，现在如何不得而知。

学希伯来语纯粹是当时对基督教的狂热，不过基本上没有学到什么。过去我跟许多人一样，把犹太人捧得很高，看作是世界上最优秀的民族或至少是之一。 但我现在不怎么看。 前一段时间报道，他们的前总统犯猥琐女性罪判了刑坐监了。 我接触的以色列人也不过如此。 以色列人会赚钱是事实，那也不过是近畿百年的事情，他们在科学，文化，等等领域有不俗表现， 也是在最近几百年的事。 犹太人为了金钱可以不顾一切，所以世界各国都很反感犹太人。 莎士比亚的戏剧就有讽刺犹太人的。 但跟希腊相比，就不是一个等级的了。 希腊文明奠定了现代文明的基础， 而犹太人只是会赚钱， 同时在某些科学领域作出了巨大贡献（爱因斯坦就是犹太籍德国人）。

这些语言就是这样陆陆续续学到的了。在我职业生涯的前期， 有些是发挥了巨大作用， 有些根本是点缀而已。

俄语从未派过用场， 唯一一次是上个月跟一个俄罗斯人谈发电设备业务，后来我俄语不想写了就不跟他谈了。

德语是我过去十几年职业生涯的基础。我在西门子，巴高克，莱茵技术等德国公司，德语充分发挥了作用。

法语也在阿尔斯通工作期间稍微有点用场， 特别是跟公司高层交往时，因为法国人特别感冒英语。

世界语没有半点用处。 前一段时间我还想跟世界语爱好者通过世界语交流，可惜没有任何反应。

英语就不言自明了。

希腊语没有用。

希伯来语更没用。

在最近的11年里， 我时不时在想，到底要不要维持那么多外语。 跟过去不同， 除了英语，其它外语都没有用场了。 我不可能再有去德国，法国，美国或其它国家公司工作的机会， 也没有去那些国家的大学研究机构搞研究的机会（这些事情我以后会提到），一句话， 什么机会都没有。居然这样，还要维护这些语言干嘛？这些问题困扰我11年，有时决定彻底放弃，有时又舍不得放弃，来来回回反反复复考虑决定撤回决定等等等等，整整11年时间，最后才真正决定，还是保留，不过希伯来语和世界语就彻底放弃。 我的基本出发点是，我保留的语言要我比较能使用，而且有许多伟大的作品可阅读。

但不管怎样， 对一般人来讲， 我建议除了英语， 不必再去学其它语言。除非你有特殊情况。

I started to learn Russian – my first foreign language – at high school at home. I did quite well at it, and could get a fairly good score in an entry exam to University four years later. But I have not shown any special talent in language learning after well three to four years when I have completed my German studies at Tongji University. Only afterwards I was very much attracted by foreign languages and their cultures and by then I have already completed the studies of basic languages skills of English, German, French, Russian and even Esperanto, an universal and man-made language. Among them, only Russian and German were learned through school teachers, the rest three by self-studies.

After finishing my schools, I’ve never stopped learning foreign languages and reading their literatures for a single days, to maintain at least or even to improve them a little bit. For example I was able to work in a number of foreign companies of nationalities of the U.S., U.K., Germany, France and several others, so at that time period I was able also to practice thus to improve my spoken English, German, and French. Around 1991/2 I passed an IELTS done at the British Embassy in Beijing with an overall score of 7.0 – which is considered high as the highest is 10.0 -? and my oral score was even 9.0 and the examiner commented my oral English as “near native”.

But in all I have not made major progress in all of these languages, either in depth or in width. I’ve not tried to learn more languages nor to learn more sophisticated linguistics such as literatures.

However, just a year ago (it was about 2007, but this essay was written in about 2008), out of my desire to study ancient Greek, Latin science literatures and Hebrew Scripture, I was very keen to learn these languages, after a year’s delay and hesitation, I finally decided to move on with the studies of these three languages. Although language studies are now not among my priority, I still plan to finish the studies in about three years, so that I will be able to understand the basics of these languages after three years. I will also complement my studies with listening practices and literature reading, not just lessons.

So as a result I have to maintain a total of 8 languages in different level of competency:

  • English at working level
  • German quite OK
  • French so and so
  • Russian simple reading
  • Greek a few sentences
  • Latin mamahuhu
  • Hebrew almost nothing
  • Esperanto a few words but will soon replace English as my working language.

I consider it absurd to learn a language of another nationality and in the end I shall only use a world language that is most likely Esperanto. There are hundreds of world languages, but I don't want to research which one is the best for me, because Esperanto is the one I learned the earliest and so far the only world language.

Language Studies

Every student starts learning a foreign language in China after their primary school.

At my days we all were learning Russian, although China and the Soviet Union were fighting for more than a decade since the early 60's. Apparently there was no alternatives - english, german, french all capitalistic, Japan our traditional rivalry and what else ?

I don't have talent in language - I was a shy, taciturn and introvert boy. To speak chinese makes me even uneasy in some cases, not talking foreign languages. It is completely a mistake to work in that direction, but no other choices.

Enrolled at Tongji, I continued my Russian studies, and my scores were quite good. I was able to read some scientific literature such as math, physics. I studied for a semester then as you know I was regrouped in a german class. After the german class, I continued my Russian studies, and at the same time also my german studies during my bachelor studies from 1978 to 1983.

At that time, learning materials were scarcely to be found. I went to the foreign language bookstore at Fuzhou Road not far from the People's Square, and bought whatever was available. I also went to the Shanghai Library located at the end of the East Nanjing Road close to the Square to find any german literature.

About two years before graduation in 1981, I found people were all learning english, was also found that english is more popular and useful than my languages. If I couldn't learn english, it might be difficult to survive in the world. And I turned to english, and happily to find it much easier to learn, especially if you have already learned russian and german whose grammars were much more complex than english. For example, russian and german verbs, adjectives have to be changed along with the subjects, english have not such necessary or much simpler. The "Nebensatz" or subordinate sentences are very complicated in german, and many times I would simply forget to put the verbs at then end in speaking. The prepositions are also sophisticated, and even today they make me headaches.

There are no other tips as reading, writing, speaking and listening if you want to command a language. I read every book I can found, newspaper, magazines, radio and so on. And you must learn it in an intensive and fast pace - I remembered about 50 new words a day. And a book took me normally a week or so for a quick reading. Of course, I will come back later, perhaps more than once, or never if this is only a light reading. Nowadays, my learning speed is even faster. I remember the Spring Festival day in 1992, when I have to stay in Shenzhen, I managed to finish reading an english novel of 500 pages in a day or two. And in 1999-2000 period, very often I bought a IT book of 300 pages, and the next morning, it was a old book - hence I vowed never to buy IT books ever since.

If you try to learn a language by "Daily Collection and Monthly Accumulation" approach, I would say, the failure rate will be high. It is my firm view that to accomplish something you have to be quick and decisive. A moment's hesitation means a total retreat in many cases.

After six months' diligent studies, my english level caught up with others' and I was thinking about other languages - french. In fact, I tried japanese, but the strange characters (like old chinese signs) prevented my learning desire. French was much more difficult. Particularly the pronunciation. Without a good teacher you have difficulties to learn that language. The techniques in english learning cannot be simply implanted into french. I was too confident in learning languages so I attended no school and very seldom listened to radio, cassettes or conversed with french speaking people.

Nevertheless, I ventured to conquer that language, one year before my bachelor graduation. At the same time, I also started learning Esperanto, an artificial language invented by a polish doctor in the late 19's century. Esperanto combines the grammar, vocabularies and syntaxes of the major european languages and therefore is easy to learn, but easy to forget as well, because its use is rarely to be found. I have no single word of Esperanto now, as with Russian.

As your language base becomes larger and larger, your time spent on learning, maintaining and improving those languages will be more and more. More than 1/3 of my time has been devoted to languages and sometime I found it not worthwhile.

During my postgraduate studies, I continued my studies in English, German and French but forgot all others. I couldn't manage the others. If I don't want to be a linguist then stop there.

I have studied relatively more languages, not for immigrating to other countries. Like many other colleagues, I am also not keen to leave China for a better life in western countries. By mastering the prevailing world languages, I am freely accessibly to all information of the outside world so that nobody can cheat me. Just like mastering the IT technologies has opened the information age in front of me, although I don't need to be a linguist or an IT industrialist.

Now language skills are still one of my strong points and will remain to be one of my qualifications for my career and daily life. It's fun to learn a language and a culture.

Languages - tools to other worlds

Languages - either spoken or in writing - are the most important instruments of mankind for understanding other people of the same race or other races, and to the daily life. Without languages no mankind.

The first language which I knew is of course my mother language, the language my mother spoke or speaks before and after my birth and also now. It's not the native language - the mandarin or the dialect of my hometown though. The mother language is the most important language in my whole private life.

Then the family language, which comes a little different from the dialect in my hometown, as every family has its own language. The dialect is also a language which I can never forget. Our dialect is covered in the surrounding areas of the so-called WU culture region, an area that includes the southern Jiangsu province, Shanghai and the northern Zhejiang province. Within this region man can understand each other without much difficulty. Nevertheless there are hundred of variations - the smaller or larger - among different counties, towns even villages.

Mandarin (Putonghua) is the legal language of China, which origins from the north. Mandarin is being used through my life and career in China.

The first "foreign language" was the Russian, which I started to learn in 1976. Until 1989 I can still read Russian literature, but I nearly know no single Russian word now. That is very unfortunate. Russia is one of the greatest countries in the world. I believe, in few years Russia will become strong again.

The second foreign language is now the German, which I have studies and used very intensively ever since 1979. But my writing abilities and speaking are now only about 40-50% of my best time (around 1989).

English comes already very late. One year before my graduation from university study I decided to learn English. I was of the opinion, without English one can't survive, although I had already rather good Russian and German. Within half a year I had a quite reasonable English already, And what's more, I took the entry exam of master degree where I chose English as foreign language, not German.

I have also strong desire for French however it sounds difficult to me. From 1982 I began to study French, however my french level is not high. At my best time I can only understand 70% spoken French, now I can only read the simplest french literature.

In the the 80's years I have also tried several other languages, like Esperanto, Japanese, but the attempt did not last long. After the graduation in 1983 and 1989 I have hardly time to learn other languages. Then I have also scarcely time to improve the existing languages.

Languages are not my specialty, but they took me 1/4 - 1/3 of my time, and now perhaps a little more (50%).

(machine-translated from German, sounds strange ???)

Multilinguistic

Multilinguistic has become a special label of mine to differ me from other people. Each time I am introduced to new friends, they always say oh Mr Chen can speak several languages, great! And they wonder how I can manage the four without confusion.

Over the last 30 years or so, I have been spending at least one hour on reading foreign language materials.

I will continue to read literatures and some of the other cultural relics of the four major languages – English, German, French and Russian to keep my language level not declining too quickly. I am not planning to improve my linguistic competence, but I also don’t want say farewell to them because I have spent too much time on them.

I’m now proficient in English, German and French with some basics in Russian and am still planning to expand this listing.

I also used to have a plan to devote completely to the studies and teaching of German literature, therefore I have learned quite intensively the German literature from Classic to Post-modern.

I also plan to give up all other studies, leaving only the above two areas – a little foreign languages and lots of Solar and Solar Aviation.

Ironically, I didn’t like foreign languages at all at the beginning of my university days, but some time around the early 80’s, suddenly I found foreign languages very fun, and ever since I have been keeping learning these languages – English, German, French and Russia – occasionally also some others – till now. It’s part of my life now.

Here below some history of language studies.

I started to learn Russian – my first foreign language – at high school at home. I did quite well at it, and could get a fairly good score in an entry exam to University four years later. But I have not shown any special talent in language learning after well three to four years when I have completed my German studies at Tongji University. Only afterwards I was very much attracted by foreign languages and their cultures and by then I have already completed the studies of basic languages skills of English, German, French, Russian and even Esperanto, an universal and man-made language. Among them, only Russian and German were learned through school teachers, the rest three by self-studies.

After finishing my schools, I’ve never stopped learning foreign languages and reading their literatures for a single days, to maintain at least or even to improve them a little bit. For example I was able to work in a number of foreign companies of nationalities of the U.S., U.K., Germany, France and several others, so at that time period I was able also to practice thus to improve my spoken English, German, and French. Around 1991/2 I passed an IELTS done at the British Embassy in Beijing with an overall score of 7.0 – which is considered high as the highest is 10.0 -? and my oral score was even 9.0 and the examiner commented my oral English as “near native”.

But in all I have not made major progress in all of these languages, either in depth or in width. I’ve not tried to learn more languages nor to learn more sophisticated linguistics such as literatures.

However, just a year ago (it was about 2007, but this essay was written in about 2008), out of my desire to study ancient Greek, Latin science literatures and Hebrew Scripture, I was very keen to learn these languages, after a year’s delay and hesitation, I finally decided to move on with the studies of these three languages. Although language studies are now not among my priority, I still plan to finish the studies in about three years, so that I will be able to understand the basics of these languages after three years. I will also complement my studies with listening practices and literature reading, not just lessons.

So as a result I have to maintain a total of 8 languages in different level of competency:

  • English at working level
  • German quite OK
  • French so and so
  • Russian simple reading
  • Greek a few sentences
  • Latin mamahuhu
  • Hebrew almost nothing
  • Esperanto a few words but will soon replace English as my working language.

I consider it absurd to learn a language of another nationality and in the end I shall only use a world language that is most likely Esperanto. There are hundreds of world languages, but I don't want to research which one is the best for me, because Esperanto is the one I learned the earliest and so far the only world language.


Esperanto

I have learned Esperanto – one of the man-made universal language – sometime in 1983, just days before graduation. Later on I forgot it and now I have no intention to renew it. Whether or not I will catch it up, I have no idea yet. I will take decision when my studies of Greek, Hebrew and Latin will come to an end. Of course, Japanese, Spanish and Arabic have already come to my mind, but that’s years away!

Esperanto.docx
EsperantoEnglish20141124.docx

kurso.exe

Bible

?

La Sankta biblio p1541

4? /? 11

?

Malnova testamento 1 p454

Malnova testamento 3 p448

Nova testamento p485

?Textbooks

Albro An Elementary Esperanto Primer p43.pdf???????? ok

?

okokok

Baker The_American_Esperanto_Book.pdf .................

?

?

?

okokok

Corsetti Esperanto estas facila 2012 p137

?

?

English-Esperanto Vocabulary.pdf

?

?

okokok

Esperanto-30-minutes-mini-cours-cafe-EO

?

?

esperanto-vocabulary-list.pdf

?

FRYER THE ESPERANTO TEACHER 2007 p164.pdf

FRYER The Esperanto Teacher 2009 p64.pdf ................... 40

?

HOGBEN interglossa.pdf ..................... ok

?

Okokok

Kellerman A COMPLETE GRAMMAR OF ESPERANTO 2007 p216.pdf

?

Kellerman A COMPLETE GRAMMAR OF ESPERANTO 1910 p352.pdf? ........

200

?

?

?

?

okokok

MALOVEC GRAMATIKO DE ESPERANTO p100

?

?

?

Martha? Esperanto_por_Infanoj-trilingva.pdf ................ ok

?

okokok

Vessella The International Language Esperanto A Course????????

?

?

?Literature in Esperanto

?

Literature in Esperanto?

http://www.gutenberg.org/browse/languages/eo

http://www.beletraalmanako.com/

?

Alcott Mia Kontrabandulo.txt

Andersen Fabeloj de Andersen.txt

Boulton ne nur leteroj de plum-amikoj p76.pdf

Dickens La Batalo de l' Vivo.txt

Dickens La Batalo de l' Vivo1.txt

Dumas La kolomba premio.txt

Goethe Ifigenio En Tauxrido.txt

Irving La Legendo de Dorm-Valeto.txt

Irving Tri Noveloj p52.pdf

Irving Tri Noveloj p52

9

KARDEC LA LIBRO DE LA SPIRITOJ p475.pdf

KARDEC LA GENEZO p436.pdf

Mudie The Esperantist, Complete.txt

RUSSELL Kial mi ne estas kristano.pdf

Schwartz la stranga butiko p130.pdf

Shakespeare Hamleto.txt

Shakespeare Makbeto.txt

?

?Scientists in Esperanto

?

Science books in Esperanto

?

Graph theory

grafeteorio

?

http://www.dmoz.org/World/Esperanto/

http://bitlibroj.com/

?

Barandovská-Frank Kiel planlingvoj povas helpi la sciencon.pdf
Bernard Fiziko p107.pdf
Kiselman Konveksaj aroj kaj funkcioj.pdf
Kiselman La teoremo de Siu por abstraktaj nombroj de Lelong.pdf
Paiva La relativeca tempo.pdf
Revizio La matematiko kaj statistiko en Plena Ilustrita Vortaro.pdf
Teixeira Eksperimenta havigo de metriko en ?generala relativeco.pdf
Teixeira Movoj sub newtona logaritma potencialo.pdf
Teixeira Taub, Rindler,kaj la gravito de statika plato.pdf
tout_est_relatif_esperanto p64.pdf

tout_est_relatif_esperanto p64

11

?

?
Websites

?

!!!!!!!!!!!!!!!!!!!!!

http://akademio-de-esperanto.org

http://www.akademio-de-esperanto.org/

www.aktuale.info

!!!!!!!!!!!!!!!!!!!!!!

http://www.bretaro.net/

!!!!!!!!!!!!!!!!!!!!!!!!!

http://qgsx.chinareports.org.cn/

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.ciesp.cn/

?????????????????

http://www.cursodeesperanto.com.br/

!!!!!!!!!!!!!!!!!!!!!!!

http://www.davinci-china.com/

http://www.davinci-china.com/chat

http://www.ebudhano.cn/

http://www.elerno.cn/

www.esperantic.org

http://www.esperanto.ca

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.esperanto.cn/

!!!!!!!!!!!!!!!!!!!!!!!

http://esperanto.com/

http://www.esperanto.de/

http://www.esperanto.de/lehrbuch/

http://www.esperanto.de/sprache/kurse/brazila/

http://esperanto.dk/

http://www.esperanto.it/

!!!!!!!!!!!!!!!!!

http://esperanto.net/

http://www.esperanto.org/

http://www.esperanto.org/hkjea

http://esperanto.org.br/

http://esperanto.se/

http://esperanto-france.org/

http://www.esperanto-nederland.nl/

http://esperanto-usa.org/

!!!!!!!!!!!!!!!!!!!!!!!

http://www.esperapekino.com/

http://www.espero.com.cn/

!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.europo.eu/

http://www.europo.eu/eo/chefpagho

http://www.czea.js.cn/

http://www.hzsk.com

http://www.hzsk.com/asp_xhgl_100/d11.shtml

www.ikso.net

www.ilei.info

!!!!!!!!!!!!!!!!!!!!!!!

http://www.ineast.com/sjy/

???????????????????

http://www.interrilatoj.com/

????????????

http://www.komerco.com/

?

??????????????????

http://www.kurso.com.br

http://www.kurso.com.br/elshuto.php?de

?????????????

http://learnesperanto.org/

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.lernu.net/

http://en.lernu.net/

http://de.lernu.net/lernado/index.php

http://www.lz-esperanto.org/

http://pacujo.net/esperanto/course/

http://pacujo.net/esperanto/course/materialo/

http://www.pasportaservo.org/

绿网

http://www.reto.cn/

!!!!!!!!!!!!!!!!!!!!!

http://www.rima-con.net/

!!!!!!!!!!!!!!!!!!!!!

http://www.satesperanto.org/

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.simplavortaro.org/

?

???????????????????

http://www.skotlando.org/

http://www.southern.edu/~caviness/cge/

http://www.tejo.org

http://www.tejo.org/uea/Kurso_De_Esperanto_En_La_Indonezia

http://traduku.net/

http://www.uea.org/


Francais

I started to learn French in 1992 almost at the same time with my English learning. I did alone too. French seems more difficult than English especially its spelling and pronunciation. Frankly speaking my French level is not good, although I used to be able to speak a little while working at French company (Alstom, 1996-1997), but I have never reached a level compatible with those of English or German. Now I can only read French literature but still difficult to understanding the talking.

French.doc
French20060802.doc
French20060823.doc

Littérature

??????

Littérature grecque? page 3

Greek Literature

L'Iliade

?

http://www.armance.com/

http://abu.cnam.fr/

http://abu.cnam.fr/cgi-bin/go?nddp1,1541,1560

http://www.lacitoyennete.com/perso/oeuvres/oeuvres.php

http://www.livresse.com

http://www.senscritique.com/liste/Les_100_meilleurs_livres_de_tous_les_temps/442921

http://clicnet.swarthmore.edu/litterature/litterature.html

https://fr.wikipedia.org/wiki/Les_100_meilleurs_livres_de_tous_les_temps

http://www.vousnousils.fr/ebooks-gratuits/

?Cent ans de solitude et
Les Mille et une Nuits??? -????? Inde/Iran/Iraq/ égypte

Le Monde s'effondre????? Chinua Achebe?????? Nigeria

La Divine Comédie Dante Alighieri????? Italie

Les Contes d'...?????? Andersen Danemark

Orgueil et préjugés Jane Austen??? Angleterre

Balzac Le colonel Chabert p144.pdf?????????? 11

Balzac Eugénie Grandet - Scènes de la vie de province p144
Balzac Illusions perdues - Scènes de la vie de province p487
Balzac le pere goriot p527.pdf
Balzac Splendeurs et misères des courtisanes - Scènes de la vie parisienne p407

Beaumarchais Le Mariage de Figaro p203

Philippe Beaussant
Molloy, Malone meurt, L'Innombale???? Trilogie de Samuel Beckett??? Irlande

Le Decameron Jean Boccace? Italie

Fictions?? Jorge Luis Borges?? Argentine

Les Hauts de Hurle-Vent Emily Bronte? Angleterre

L'étranger????? Albert Camus? France

Les poèmes de...???? Paul Celan????? Roumanie

Voyage au bout de la nuit????? Louis-Ferdinand Céline? France

Cervantes Don Quichotte p151

Les Contes de Cantorbéry????? Goeffrey Chaucer?? Angleterre

Nostromo?????? Joseph Conrad Angleterre

De grandes espérances??? Charles Dickens???? Angleterre

Diderot Le Neveu de Rameau p71
Jacques le fataliste? Denis Diderot France

Berlin Alexanderplatz??? Alfred Doblin Allemagne

Dolstoievski L’Idiot p623
Crime et Chatiment Fedor M. Dosto?evski??? Russie
Les Possédés?? Fedor M. Dosto?evski??? Russie
Les Frères Karamazov??? Fedor M. Dosto?evski??? Russie

Dumas les_trois_mousquetaires p529.pdf
Dumas les_trois_mousquetaires p914.pdf
Dumas les_trois_mousquetaires p1029.pdf
Dumas_Le_comte_de_Monte_Cristo_1.pdf
Dumas_Le_comte_de_Monte_Cristo_p328.pdf

Middlemarch? George Eliot?? Angleterre

Homme invisible, pour qui chantes-tu? Ralph Ellison? états-Unis

Médée???? Euripide? Grèce

Absalon!, Absalon! William Faulkner?? états-Unis
Le Bruit et la Fureur????? William Faulkner?? états-Unis

Madame Bovary???? Gustave Flaubert??? France
Une éducation sentimentale?? Gustave Flaubert??? France

Flaubert bouvard_et_pecuchet p391.pdf
Flaubert Madame Bovary p206.pdf
FlaubertGustave Madame Bovary_fr p420.pdf
Flaubert Trois contes p77

Goethe Faust p475
Faust, une tragédie Johann Wolfgang von Goethe?????? Allemagne

?mes mortes?? Nikolai Gogol Russie

Le Tambour??? Guenter Grass Allemagne

Grimm Contes de la famille p37

La Faim? Knut Hamsun? Norvège

Le Vieil Homme et la Mer???? Ernest Hemingway états-Unis

L'Iiade et l'Odyssée Homère?? Grèce

Hugo chanson_des_rues p153.pdf
Hugo Les Contemplations - Tome I p192
Hugo Les Contemplations - Tome II p219
Hugo La Légende des siècles - Tome I p175
Hugo La Légende des siècles - Tome II p209
Hugo Les Misérables p743
Hugo Les Misérables - Tome I – Fantine p262
Hugo Les Misérables - Tome II – Cosette p278
Hugo Les Misérables - Tome III – Marius p252
Hugo Les Misérables - Tome IV - L'Idylle rue Plumet et l'Epopée rue Saint-Denis p345
Hugo Les Misérables - Tome V - Jean Valjean p289
Hugo Notre Dame de Paris p333.pdf
Hugo Notre Dame de Paris p374.pdf
Hugo Notre Dame de Paris p407.pdf
Hugo quatre_vingt_treize p279.pdf
Hugo quatre_vingt_treize p560.pdf

Maison de poupée?? Henrik Ibsen?? Norvège

Le Livre de Job????? -????? Isra?l

Ulysse???? James Joyce??? Irlande

Le Procès et Le Chateau Franz Kafka??? Rép. Tchèque

L'Anneau de Sakuntala?? Kalisada? Inde

Le Grondement de la montagne???? Yasunari Kawabata Japon

Zorba le Grec? Nikos Kazantzakis? Grèce

Amants et fils DH Lawrence? Angleterre

Le Livre du peuple Halldor K. Laxness Islande

Les poèmes de...???? Giacomo Leopardi? Italie

Le Carnet d'or Doris Lessing? Angleterre

Fifi Brindacier?????? Astrid Lindgren????? Suède

Romancero Gitan?? Federico Garcia Lorca??? Espagne

Diary of a Madman et Other Stories???? Lu Xun?? Chine

Children of Gebelawi???? Mahfouz? égypte

Mahabharata?? -????? Inde

Les Buddenbrook?? Thomas Mann Allemagne
La Montagne magique??? Thomas Mann Allemagne

L'Amour au temps du choléra Gabriel Garcia Marquez Colombie

Maupassant Le Horla p112
Maupassant Pierre et Jean p119

Moby Dick???? Herman Melville??? états-Unis

Molière Le Bourgeois gentilhomme p121
Molière L'Ecole des femmes p104
Molière Les Femmes savants p103
Molière Les Fourberies de Scapin p85
Molière Le Malade imaginaire p91

Essais????? Montaigne????? France

La Storia Elsa Morante? Italie

Beloved?? Toni Morrison états-Unis

The Tale of Genji Genji? Shikibu Murasaki?? Japon

L'Homme sans qualités?? Robert Musil?? Autriche

Lolita????? Vladimir Nabokov? Russie / états-Unis

Njaals Saga???? -????? Islande

1984?????? George Orwell?????? Angleterre

Les Métamorphoses Ovide????? Italie

Le Livre de l'intranquillité???? Fernando Pessoa???? Portugal

Les Contes d'...?????? Edgar Allan Poe???? états-Unis

à la recherche du temps perdu????? Marcel Proust France

Gargantua et Pantagruel Fran?ois Rabelais?? France

The Devil to Pay in the Backlands Joao Guimaraes Rosa???? Brésil

Rousseau Les Confessions p510
Rousseau Discours sur l'origine et les fondements de l'inégalité parmi les homes p92

Pedro Paramo Juan Rulfo????? Mexique

Mathnawi?????? Jalal ad-din Rumi?? Iran

Enfants de minuit?? Salman Rushdie???? Inde/Angleterre

The Orchard?? Sheikh Musharrif ud-din Sadi?????? Iran

Season of Migration to the North Tayeb?????? Salih?????? Soudan

L'Aveuglement?????? Jose Saramago?????? Portugal

Hamlet??? William Shakespeare????? Angleterre
Le Roi Lear??? William Shakespeare????? Angleterre
Othello??? William Shakespeare????? Angleterre

Oedipe Roi???? Sophocle Grèce

Stendhal LeRouge_et_leNoir p1086?????????????
557

Vie et Opinions de Tristam Shandy?????? Laurence Sterne???? Irlande

La Conscience de Zeno?? Italo Svevo???? Italie

Les Voyages de Gulliver Jonathan Swift?????? Irlande

Guerre et Paix Leo Tolsto????? Russie
Anna Karenina?????? Leo Tolsto????? Russie
La Mort d' Ivan Illitch??? Leo Tolsto????? Russie

Récits divers?? Anton P. Tchekhov Russie

Huckleberry Finn?? Mark Twain??? états-Unis

Ramayana?????? Valmiki?? Inde

Verne Le_tour_du_monde_en_quatre-vingt_jours p179.pdf
Verne LE TOUR DU MONDE EN QUATRE-VINGTS JOURS p356.pdf

Vigny Oeuvres complètes - Tome I p181

L'énéide? Virgile??? Italie

voltaire candide p47.pdf
Voltaire Candide - ou L'Optimisme p90
voltaire candide p116.pdf
Voltaire le ingenu p25.pdf
Voltaire le ingenu p73.pdf
Voltaire Romans et contes p110

Feuilles d'herbe????? Walt Whitman états-Unis

Mrs Dalloway Virginia Woolf?????? Angleterre
Promenade au phare????? Virginia Woolf?????? Angleterre

Les Mémoires d'Hadrien Marguerite Yourcenar??? France

Zola Au Bonheur des Dames p344
Zola Germinal p372
Zola L’Assommoir p346
Zola La Curée p233
Zola La Fortune des Rougon p260
Zola Nana p372

Scientists

?

Jean le Rond d'Alembert, mathematician, mechanician, physicist and philosopher

?

André-Marie Ampère, physicist and mathematician

?

okokok

Nicolas Léonard Sadi Carnot, physicist and military engineer

Carnot Reflexions1824 p130.pdf?????????????

?

?

?

Augustin-Louis Cauchy

Augustin-Louis Cauchy, mathematician and physicist

http://portail.mathdoc.fr/OEUVRES/

http://portail.mathdoc.fr/cgi-bin/oetoc?id=OE_CAUCHY_1_8

http://mathdoc.emath.fr/cgi-bin/oetoc?id=OE_CAUCHY_1_2

?

okokok

Cauchy Analyse algébrique p602.pdf???????????????????

?

Cauchy Analyse algébrique1 p602.pdf

?

okokok

Cauchy Cours de analyse p481.pdf????????????????

?

Cauchy notes1823 calcul infenitesmal p253.pdf?????????? 9

?

?

Charles-Augustin de Coulomb, physicist

?

?

okokok

COMTE Discours sur lesprit positif p72.pdf?????????

?

?

?

Marie Curie, physicist and chemist

?

Pierre Curie, physicist and chemist

?

Henry Darcy

?

René Descartes, scientist and philosopher

?

Pierre de Fermat, mathematician

Fermat Oeuvres de fermat p304.pdf?

66

?

?

Joseph Fourier, mathematician and physicist

?

Augustin-Jean Fresnel, physicist

?

évariste Galois, mathematician

?

Jacques Hadamard, mathematician

?

Humboldt Cosmos essai d'une description physique du monde p480

Humboldt Cosmos essai d'une description physique du monde p602

?

okokok

HUMBOLDT éCRITURE DU VOYAGE ET CONSTRUCTION SAVANTE DU MONDE p69

?

?

Huygens Oeuvres complètes Tome XIV. Probabilités Travaux de mathématiques pures 1655-1666 p644

?

Joseph Louis Lagrange, mathematician

Lagrange Mechanique Analytique_p530zzz.pdf

?

?

Pierre-Simon Laplace, mathematician and physicist

Laplace Mecanique celeste p401.pdf???????? 43

Laplace Mecanique celeste p537.pdf???????? 43

?

Antoine Lavoisier

[13] 拉瓦锡《化学原论》? Antoine-Laurent de Lavoisier? Traité élémentaire de chimie

http://www.antoine-lavoisier.com/

http://www.taieb.net/auteurs/Lavoisier/traite.html

?

?

Legendre Méthodes numériques p140

?

LEIBNIZ NOUVEAUX ESSAIS sur L'ENTENDEMENT HUMAIN p279

?

Marin Mersenne, mathematician

?

?

Montaigne Essais p198.pdf??????????????

4

?

?

孟德斯鸠《论法的精神》 C·L·Montesquieu? Esprit des Lois

http://www.archive.org/details/lespritdeslois03montuoft

http://www.efm.bris.ac.uk/het/montesquieu/index.htm

http://www.etudes-litteraires.com/montesquieu.php

http://www.gutenberg.org/etext/27573

?

?

De_l_esprit_des_lois

?

?

De_l_esprit_des_lois-1

De_l_esprit_des_lois-2

De_l_esprit_des_lois-3

delespritdesloix12montuoft

espritdeslois00montuoft

lespritdeslois01montuoft

lespritdeslois02montuoft

lespritdeslois03montuoft

lespritdeslois04montuoft

?

Montesquieu De_l_esprit_des_lois-1 p292.pdf

Montesquieu De_l_esprit_des_lois-2 p298.pdf

Montesquieu De_l_esprit_des_lois-3 p497.pdf

Montesquieu De_l_esprit_des_lois-4 p274.pdf

Montesquieu delespritdesloix12montuoft p488.pdf

Montesquieu lespritdeslois00montuoft p616.pdf

Montesquieu lespritdeslois01montuoft p613.pdf

Montesquieu lespritdeslois02montuoft p405.pdf

Montesquieu lespritdeslois03montuoft p477.pdf

Montesquieu lespritdeslois04montuoft p605.pdf

?

Blaise Pascal, mathematician and philosopher

étienne Pascal, mathematician

Pascal Pensées sur la religion et sur quelques autres sujets p204.pdf?????? ?????7

?

Louis Pasteur, microbiologist and chemist

?

?

Henri Poincaré, mathematician and physicist

Lucien Poincaré, physicist

POINCARE Calcul de probabilite p337

POINCARE Capillarite p208.pdf??????????????? 5

Poincare Dernieres pensees p148.pdf ……………..? 8

POINCARE Electricite et optique p660.pdf ………………. 13

Poincare The Value of science p124

Poincare La Valeur de la science p124.pdf …………………6

POINCARE Mecanique celeste p408.pdf? ……………? 4

Poincare Science et methode p164.pdf?????????? 8

Poincare Science et methode p314.pdf

Poincare science-hypothesis p120.pdf

POINCARéSCIENCE AND HYPOTHESIS p306

POINCARE Theorie analytic de propagation de chaleur p327.pdf? …….. 15

POINCARE Theorie de tourbillons p222.pdf ……………. 26

POINCARE Theorie potentiell newtonian p369

POINCARE Theorie potentiell newtonian p380.pdf ,,,,,,,,,,,,,,,,,, 20

POINCARE Thermodynamique p477.pdf …………………12

?

?

Siméon Poisson, mathematician and physicist

Poisson recherches sur la probabilite des jugements p428 …………. 16

Poisson Theorie mathematique de la chaleur p96

?

Proust A_la_recherche_du_temps_perdu_01 p467.pdf

?

Rousseau Contrat_social p93.pdf

Rousseau Contrat_social p97.pdf

?

?

Rousseau Discours sur l'origine et les fondements de l'inégalité parmi les homes p92.pdf

28

?

?

Rousseau DU CONTRAT SOCIAL ou Principes du droit politique p110

4? /? 11

?

?

Rousseau DU CONTRAT SOCIAL ou Principes du droit politique p118

?

Rousseau Les Confessions p510.pdf

?

Fran?ois Viète, mathematician

Site web

?

http://www.afp.com/home/

http://www.alternativelibertaire.org/

http://www.asiepassion.com/

http://www.bbc.co.uk/education/asguru/english/tvtimecodes.shtml

http://www.bfm.be/

http://broadband-television.com/tv/english.html

http://www.business-digest.fr/

http://www.canalplus.fr/

http://www.capital.fr/

http://www.challenges-eco.com/

http://www.comfm.com

http://www.courrierinternational.com/

http://www.elle.fr/

http://www.lefigaro.fr/

http://www.france-jeunes.net/

http://www.france2.fr/

?

http://www.france3.fr/

http://www.france5.fr/

http://www.lci.fr/

http://tf1.lci.fr/infos/media/jt/0,,3721658,00-journal-televise-fevrier-2008-20h-.html

www.illustre.ch

http://www.infopresse.com/

http://www.infopresse.fr/

mms://vipmms.itele.fr/cpi_itele

http://www.journaux.fr/

http://www.kompass.fr/

http://www.lagardere.fr/

www.lapresse.com

http://www.largeur.com/

http://www.latribune.fr/

http://www.lavoixdunord.fr/

http://www.ledevoir.com/

www.lemonde.fr

http://www.leparisien.fr/

http://www.lerevenu.com/

http://www.les4verites.com/

http://www.lesechos.fr/

http://www.lesoir.be/

www.lexpress.fr

http://www.liberation.fr

http://librepresse.com/

http://www.lidealiste.com/

http://www.lien-social.com/

http://www.livresse.com/

http://www.m6.fr/

http://www.magazine-histoire.com/

http://www.melissa-theuriau.fr/videos.html

http://www.metropoint.com/

http://www.nostalgie.fr/

http://player.nostalgie.fr/V4/nostalgie/webradios/index_V1.html?webradio=nostalgie

http://www.ouest-france.fr/

www.parismatch.com

http://www.pathe.fr/

http://www.portail-presse.com/

http://www.pressclub.fr/

http://www.pressedefrance.com/

http://www.publicsenat.fr/

http://www.radio-canada.ca/??

http://www.radio86.fr/decouvrir-et-apprendre/chine-hebdo

http://www.radiobfm.com/

http://www.radiofrance.fr/

http://www.radioneo.org/

http://www.revues.org/

http://www.rfi.fr/

http://www.rfo.fr/

http://www.rmcinfo.fr/

http://www.strategies.fr/

http://www.theworldpress.com/

http://www.tf1.fr/

http://www.tourmag.com/

http://www.toytownmunich.com/wiki/English_language_television

http://www.tv.com/diane-english/person/21566/summary.html

http://www.tv5.fr/

www.voila.fr

www.wanadoo.fr

http://wwitv.com/

http://www.wwitv.com/portal.htm

mms://vipmms9.yacast.net/bfm_bfmtv

http://cache.yacast.fr/V4/rmc/rmc_main_V2.html

http://cache.yacast.fr/V4/ouifm/ouifm_main_V2.html?id=numericable&laun

www.yahoo.fr?

?

Radio

?

http://www.bfm.be/

http://www.comfm.com

http://www.europeinfos.com/

http://www.nostalgie.fr/

http://www.radio-canada.ca/

http://www.radiofrance.fr/

http://www.rfi.fr/

http://www.rfo.fr/

http://www.radioneo.org/

http://www.rmcinfo.fr/

?

Chinese

?

http://afnanjing.org/

?

http://www.afshanghai.org/

?

http://www.bjinformation.com/

?

http://www.bonjourshanghai.net/

?

http://french.china.org.cn/

?

http://www.chine.campusfrance.org

?

http://www.clubfrancechine.org

?

http://french.cri.cn/

?

http://www.faguowenhua.com/

?

http://www.fayujob.com/

?

http://www.fayurumen.com/

?

http://www.for68.com/fayu/

?

http://frenchfriend.cn/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.frenchparadis.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://fr.hjenglish.com/

?

http://lecoinfrancais.org/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.loferclub.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.mimifr.com/

法语之友

http://mimifr.frcn.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.monfr.com/

法语交流

http://bbs.monfr.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.myfrfr.com/

?

http://french.peopledaily.com.cn/

?

http://www.qjfy.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.sinofrance.org/

?

http://francais.sisu.edu.cn/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.studyfr.net

法国留学论坛

http://bbs.studyfr.net/?

?

http://fr.tingroom.com/

?

http://www.french.xinhuanet.com/french/index.htm

?

!!!!!!!!!!!!!!!!? GOOD

http://www.yuanfr.com/??

法语社区

http://frbbs.yuanfr.com/

http://www.yuanfr.com/lesson/

http://www.yuanfr.com/lesson/lascars/index.htm

http://www.yuanfr.com/lesson/merciprofesseur/mecipro.htm

!!!!!!!!!!!!!!!!? GOOD

http://www.yuanfr.com/frtv.html

http://www.yuanfr.com/frradio/

http://www.yuanfr.com/frradio.html

http://www.yuanfr.com/Html/200664174253-1.html

?

Bible

bible_fr.chm?????????????????

Genèse?

Chapitre

12


http://www.re-cit.eu/contact/

citl@atlas-citl.org

http://www.academie-francaise.fr/

contact@academie-francaise.fr

http://www.institutfrancais.com/fr/contact

XXXXXXXXXXXX

http://www.institutfrancais-pekin.com/

http://www.institutfrancais-pekin.com/

XXXXXXXXXXXX

http://www.etudes-litteraires.com/

http://www.chine.campusfrance.org

antenne_hangzhou@campusfrancechine.org

http://www.clubfrancechine.org
http://www.sinofrance.org/

http://www.comitefrancechine.com/

cfc@medef.fr
http://www.ccifc.org/
http://www.ambafrance-cn.org/
www.iisd.ca
http://www.espacefrancais.com/
https://www.franceculture.fr/
http://www.france-chine50.com/
http://www.faguowenhua.com/

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
法语文学
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

Littérature française

Aide financière de littérature française

Littérature française en la République populaire de Chine et autres

Chère Madame / Monsieur,

Je suis très heureux de vous écrire pour vous parler de la littérature fran_aise.

Je suis un Chinois de 55 ans, mais à l'age de 20 ans, je connaissais déjà 5 langues étrangères, le français, ma langue étrangère préférée - les autres étaient le russe, l'allemand, l'anglais et l'espéranto Grec et un peu de latin et d'hébreu.

A cette époque, j'ai déjà traduit de courts romans et poèmes en partie du français au chinois.

Après les études, j'étais également employé par des entreprises françaises comme Alstom en Chine, donc je suis à l'aise avec la langue française, le commerce et l'industrie à cette époque.

Cependant, depuis le millénaire, je suis séparé du monde français et depuis, je n'ai guère été en contact avec la nation française, physiquement parce que je suis resté indépendant et maintenant j'ai beaucoup moins de chances avec les espaces françaises après je me suis installé en mon village ici à environ 180 km au sud-ouest de Shanghai.

Cependant, je n'ai jamais cessé d'apprendre le français. Avec Internet je peux toujours aller sur les sites françaises, et parfois je peux aussi télécharger des romans en français et lire tranquillement chez moi. Mais j'aimerais entrer en contact avec des francophones, discuter de la littérature française et parler de la vie quotidienne. Je voudrais aussi fonder un club de culture française. Je ne sais pas s'il y a quelque chose comme ça ou pas.

Et ce qui est le plus significatif, c'est que je veux écrire une biographie sur ma mère, et peut-être aussi la traduire en français. Ma mère était morte l'année dernière, pour moi, à l'age de 81 ans. Ecrire sa biographie sera ma tache la plus importante de ma vie. Et je pourrais aussi écrire m'autobiographie, peut-être aussi en français, en plus du chinois et de l'anglais. Ces projets d'écriture prendront des années et dépendront également de l'état de ma vie.

Eh bien, dites-moi si vous pouviez m'aider dans mon étude de la littérature française ou non. Je voulais parfois aller à Shanghai ou dans d'autres villes pour rencontrer des amis français. Peut-être pourriez-vous proposer et en présenter quelques-uns.

Une autre possibilité serait que je puisse à nouveau travailler pour des entreprises ou des organisations françaises. Je ne peux que très difficilement communiquer avec le monde extérieur quand je vis dans un petit village isolé.

Une autre possibilité, cependant, est qu'avec mon expérience et mes connaissances, je puisse introduire des entreprises, des technologies et des produits français dans la province du Zhejiang. Il n'y a pas beaucoup de perspective française ici dans la province, alors qu'il y en a beaucoup trop à Shanghai.

Et, bien sùr, je m'intéresse aussi à la traduction de la littérature française en chinois et vice versa, comme je l'ai fait il y a trente-cinq ans, même si je n'avais pas de prémonitions à publier dans mon esprit.

Merci beaucoup d'avance et avec mes meilleures salutations!

Mark Chen

Huzhou, province du Zhejiang, République populaire de Chine
Je serai heureux de vous fournir de plus amples informations.

Email:

markchen2309@mail.com

Mobil:

15968252315


Greek

I started learning Greek in 2008 when I was trying to study ancient Greek literature and science books such as those of Euclid’s Elements, because I found the English translation very dull. I guess it does not transmit the true meaning of the originals and especially those subtle implicit meanings which are difficult to be translated to other languages. The plan was stopped for half a year, but now I am solid enough to finish my learning in about three years.

Greek.doc

Books

The fear of GOD is the beginning of wisdom.

Ο φ?βο? του Θεο? ε?ναι η αρχ? τη? σοφ?α?.?

?

000AS_First_Greek_Writer.pdf?????????? 72?? /? 237

000Grec sans larmesXXX.pdf????????? ??29

000hws_Greek_Grammar_AR5.pdf??????? 66??? /? 799

?

000JWW_First_Greek_Book_AR5 ??J W White ??

129

?

000PVN_short_syntax_of_new_testament_greek.pdf?????

000SSG_Intro_NT_Greek_Grammar.pdf???

000WGR_First_Greek_Grammar_Accidence.pdf

000WGR_First_Greek_Grammar_Syntax.pdf

?

000WS_A_First_Greek_CourseXXX.pdf?

?

000WWG_greek_grammar_AR5.pdf?

?

http://gr.chineseembassy.org/chn/xglj/yqlj/t563748.htm

?
Lexicon

?

?Greek_Dictionary_of_the_New_Testament1997-1997Strong_James.pdf

?Remata.xls

?XXXGreek50%List.pdf

?ZZZelgkvoc.pdf

?ZZZelgkvoc2.pdf

?ZZZgk3vocab.pdf

?ZZZgreek_boy_vocab.pdf

?ZZZNTG-VocabBuilder.pdf

?ZZZocr_29983_sm_gcse_unit_b401_voc_list.pdf

?ZZZocr_33600_sm_gcse_unit_b042_voc_list.pdf

?Learning Websites

Greek

Griechisch

LE grec

Греческий язык?

XXXXXXXXXXX? cannot open

??????????????? not viewed yet

********************?? not interesting

?

http://www.perseus.tufts.edu/hopper/

text?doc=Perseus%3Atext%3A1999.04.0007&redirect=true

http://www.perseus.tufts.edu/hopper/text?doc=Perseus%3Atext%3A1999.04.0019&redirect=true

http://www.perseus.tufts.edu/hopper/text?doc=Perseus%3Atext%3A1999.04.0020&redirect=true

http://www.perseus.tufts.edu/hopper/text?doc=Perseus%3Atext%3A1999.04.0021&redirect=true

http://www.perseus.tufts.edu/hopper/text?doc=Perseus%3Atext%3A1999.04.0074&redirect=true

http://www.perseus.tufts.edu/hopper/text?doc=Perseus%3Atext%3A1999.04.0065&redirect=true

http://www.perseus.tufts.edu/hopper/text?doc=Perseus%3Atext%3A1999.04.0052&redirect=true

http://www.perseus.tufts.edu/cgi-bin/morphindex?lang=Greek?

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! GOOD

http://www.xanthi.ilsp.gr/filog/

http://www.xanthi.ilsp.gr/filog/ch8/voc/voc1.asp?

?

希腊语学习资料?

http://163.30.0.78/arxigk/language.htm?

?

!!!!!!!!!!!!!!!!!!? GOD

http://bcs.fltr.ucl.ac.be/GraGre/00.Plan.htm

?

?????????????????????/

http://www.ancientlibrary.com/eng-grk/

?

http://www.ancientscripts.com/greek.html?

?

GOD

http://www.areopage.net/ ?

?

!!!!!!!!!!!!!!!!!!? Exercises GOD

http://artemis.austincollege.edu/acad/cml/jjohnson/athenaze/index.html

http://artemis.austincollege.edu/acad/cml/jjohnson/athenaze/02/verbmorph2.htm

?

!!!!!!!!!!!!!!!!!! GOD

http://www.bbc.co.uk/languages/greek/??

?

!!!!!!!!!!!!!!!!!!

http://www.bbc.co.uk/languages/greek/talk/

http://faculty.bbc.edu/rdecker/rd_rsrc.htm

http://www.bcbsr.com/greek/grklnk.html

?

!!!!!!!!!!!!!!!!!!? GOD

http://socrates.berkeley.edu/~ancgreek/

?

??????????????

http://www.bibleparser.fr/?

?

!!!!!!!!!!!!!!!!!!

http://www.biblicalgreek.org/grammar/

?

http://www.biblicaltraining.org/classes/greek/greek_f.html?

?

!!!!!!!!!!!!!!!!!!

http://www.bibliques.com/weft/gr/glec0a.php

?

!!!!!!!!!!!!!!!!!!? finished

http://wangli.blshe.com/post/168/429228

?

http://www.blueletterbible.org/search.html#lexiconc

?

!!!!!!!!!!!!!!!! slow to show

http://visualiseur.bnf.fr/Visualiseur?Destination=Gallica&O=NUMM-33079

?

!!!!!!!!!!!!!!!! Grammar

www.Canoo.net

?

!!!!!!!!!!!!!!!! Grammar

http://www.ccel.org/

http://www.ccel.org/ccel/goodwin/greekgrammar/Page_Index.html

http://www.ccel.org/ccel/conybeare/greekgrammar.html

?

!!!!!!!!!!!!!!!!!!!!!! GOD

http://www.cornellcollege.edu/classical_studies/reviewgreek/index.shtml?

?

!!!!!!!!!!!!!!!! Grammar

http://www.cranfordville.com/Gk-links.htm#Grammar?

?

!!!!!!!!!!!!!!!! Bible lexicon in Greek

http://bible.crosswalk.com/Lexicons/NewTestamentGreek/

?

http://www.croixsens.net/grec/

?

GOD

http://www.dabar.org/BurtonMoodsTenses/Main-Burton.html

?

!!!!!!!!!!!!!!!!!!!!!!? Good

http://www.dramata.com/? http://home.att.net/~w.e.major/greekhelp/?

?

!!!!!!!!!!!!!!!!!!!!!!? Grammar GOD

http://www.earlychristianwritings.com/davis/

?

!!!!!!!!!!!!!!!!!!!!!!? Grammar GOD

http://www.ellopos.net/elpenor/greek-language.asp

http://www.ellopos.net/elpenor/greek-language.asp

http://www.ellopos.net/elpenor/lessons/strong.asp

http://www.ellopos.net/elpenor/lessons/pharr.asp

http://www.ellopos.net/elpenor/greek-texts/interlinear-iliad.asp

?

http://www.fh-augsburg.de/%7Eharsch/graeca/Auctores/g_alpha.html?

?

!!!!!!!!!!!!!!!!!!!!!!? Grammar GOD%%%%%%%%%%

http://www.foundalis.com/lan/greek.htm

http://www.foundalis.com/lan/grkmore1.htm

http://www.foundalis.com/lan/grknum.htm

http://www.foundalis.com/lan/grkverbs.htm

http://www.foundalis.com/lan/grknouns.htm

http://www.foundalis.com/lan/grphdetl.htm

http://www.foundalis.com/lan/grkgram.htm

?

http://www.foundalis.com/lan/grstress.htm

?

!!!!!!!!!!!!!!!!!!!!!!

http://marmouget.free.fr/ressources/grec_cours.pdf ?

http://ugo.bratelli.free.fr/Lexique/LexiqueAntiquitesGrecques.pdf

http://fdier02140.free.fr/Eulalie.pdf

http://fdier.free.fr/LSJ.pdf

http://fdier02140.free.fr/STR_GREK.PDF

http://ugo.bratelli.free.fr/Lexique/LexiqueAntiquitesGrecques.pdf?

!!!!!!!!!!!!!!!!!!!!!!

http://www.freelang.com/dictionnaire/grec_ancien.html? ?

!!!!!!!!!!!!!!!!!!!!!!

http://www.gbt.org/greek.html?

!!!!!!!!!!!!!!!!!!!!!!? good

http://www.gottwein.de/GrGr/GrGramm.php?

http://www.gottwein.de/grueb/gr000.php

http://www.gottwein.de/GrWk/GrWk00.php

http://www.gottwein.de/GrFu/FUeb00.php?

!!!!!!!!!!!!!!!!!!!! good

http://www.greece.org/gr-lessons/

http://www.greece.org/gr-lessons/gr-english/?

!!!!!!!!!!!!!!!!!!!! good

http://greek-language.com/??

http://www.greek-language.com/?

http://greek-language.com/grammar/??

?

!!!!!!!!!!!!!!!!!!!!!!

http://www.greek-language.gr/greekLang/index.html

http://www.greek-language.org/?

http://www.greekbible.com/?

http://www.greeklanguage.gr/

http://www.hau.gr/?i=conferences.en.hellas-alive

http://www.hau.gr/hau/en/edu_hellasalive.html ?

!!!!!!!!!!!!!!!!!!!!!!

http://www.heme.at/ue-gr/schnupp/schnupp.php?

??????????????????

http://members.home.nl/petjoeprietveld/muomgram/grammar/? ?

!!!!!!!!!!!!!!!!!!!!!! GOD

http://www.ibiblio.org/koine/greek/lessons/

http://www.ilearngreek.com/

http://www.iliadeodyssee.com/? ?

!!!!!!!!!!!!!!!!!!!!!! GOD

http://www.instructioneducation.info/inhaltgriech.html ?

http://www.inthebeginning.org/ntgreek/learn.htm?

http://www.internetpolyglot.com/chinese/lessons-el-ln?

http://www.komvos.edu.gr/fryktories/ ?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://perswww.kuleuven.be/~u0013314/greekg.htm

http://perswww.kuleuven.be/%7Eu0013314/greekg.htm ?

Finished

http://kwoodward.net/greek/template/xample13.htm ?

http://www.kreienbuehl.ch/lat/altgriechisch/altgriechischx.html

http://www.kypros.org/LearnGreek/

http://didymos.kypros.org/LearnGreek

http://www.librarius.net/boutique/catalog/

http://www.linguanet-europa.org/plus/welcome.htm?

http://www.livemocha.com

!!!!!!!!!!!!!!!!!!? GOOD

http://community.middlebury.edu/%7Eharris/GreekGrammar.html? ?

http://www.monachos.net/greek/?

!!!!!!!!!!!!!!!!!!? GOOD

http://chss2.montclair.edu/classics/javascript/Greek/greekjava.html? ?

http://www.mylanguageexchange.com/Learn_chisim/Greek.asp ?

!!!!!!!!!!!!!!!!!!? GOOD

http://www.ntgreek.org/learn_nt_greek/grkindex.htm? ?

http://www.odysseasproject.com/

http://www.oeaw.ac.at/kal/agp/

http://www.omniglot.com/writing/greek.htm

http://home.pacbell.net/meldridg/songofthelamb/greek/index.html?

!!!!!!!!!!!!!!!!!!? GOOD

http://pagesperso-orange.fr/jc.ingelaere/grecbib/index.html

http://jc.ingelaere.pagesperso-orange.fr/grecbib/gramm/gramm.html

http://jc.ingelaere.pagesperso-orange.fr/grecbib/index.html?

http://remacle.org/bloodwolf/textes/index.htm?

http://www.ryedu.net/Article/qtl/200701/1836.html

http://home.scarlet.be/tabularium/bailly/? ?

Finished

http://skwoodward.net/greek/greekbook.html

http://skwoodward.net/greek/ch1-13.pdf? ?

http://www.slovoed.com/cs/Greek.html

http://www.somdom.com/archiver/tid-676.html

http://www.swisseduc.ch/altphilo/griech/gsprache/ggrammatik/thwirth.html

http://www.teknia.com/classes/ ?

!!!!!!!!!!!!!!!!!!? fini

http://www.textkit.com/?

!!!!!!!!!!!!!!!!!!? GOOD

http://www.theology.edu/greek01.htm ?

http://www.tidbits.com/matt/default2.html#agthings

http://www.tlg.uci.edu/demo/fontsel?

!!!!!!!!!!!!!!!!!!?

http://www.class.uh.edu/MCL/faculty/pozzi/grnl1/grnl1.gateway.htm?

!!!!!!!!!!!!!!!!!!? GOOD

http://web.uvic.ca/hrd/greek/index.htm ?

http://www.vroma.org/%7Eabarker/thrascontents.html

http://www.vroma.org/~abarker/thrascontents.html

http://www.weblettres.net/languesanc/index.php?page=traductionsg?

!!!!!!!!!!!!!!!!!!?

http://www.webwinds.com/thalassa/grlang.htm?

!!!!!!!!!!!!!!!!!!?

http://mkatz.web.wesleyan.edu/grk101/word_formation/grk101.word_formation.html?

!!!!!!!!!!!!!!!!!!?

http://glirby.people.wm.edu/GreekIntermediate/flashcards/?? ?

http://www.wrightclassics.com/mathos/index.htm ?

http://www.xilayu.com/

http://www.xilayu.com/news/view.asp?id=138

http://www.xilayu.com/news/view.asp?id=176 ?

http://www-users.cs.york.ac.uk/%7Efisher/gnt/chapters.html ?

http://www.chinawaiyu.com/

?

Greek literature

Greek literature

?Greek literature

?

Ομ?ρου Ιλι?δα p433.pdf

5?

ΟΜΗΡΟΥ ΟΔΥΣΣΕΙΑ p303

?

ΟΜΗΡΟΥ ΟΔΥΣΣΕΙΑ p439

ΟΜΗΡΟΥ ΟΔΥΣΣΕΙΑ p510

?

ΟΜΗΡΟΥ ΟΔΥΣΣΕΙΑ p524

Ομ?ρου Οδ?σσεια p524

7

?
Scientists

Euclid 《几何原本》 page

Elements with comments

Euclid Elements??

Στοιχε?α του Ευκλε?δη

Ευκλε?δη Στοιχε?α

Τα Στοιχε?α του Ευκλε?δη

?

?

>>>Euclid

?

EUCLIDS ELEMENTS OF GEOMETRY

Euclid Elements.pdf?????????????

248? ??/? 545????

?

Euclid's Elements with comments.pdf

Page? -à? 36?? / 1317

Page? ?--- 1143 / 1317

page? ?---? Book I 1134 –1221 –

?

?

Ευκλε?δειο? γεωμετρ?α p357

?

?

Ευκλε?δη Στοιχε?α tomos-1 p522.pdf????????? 156??? /? 522

Ευκλε?δη Στοιχε?α tomos-1_1 p522.pdf

Ευκλε?δη Στοιχε?α tomos-1_2 p522.pdf

?

Ευκλε?δη Στοιχε?α τ?μο?-ιι-θεωρ?α-αριθμ?ν p396.pdf

?

Ευκλε?δη Στοιχε?α τ?μο?-ιιι-η-γεωμετρ?α-του-χ?ρου p213.pdf

?

Λυκε?ου ΕΥΚΛΕΙΔΕΙΑ ΓΕΩΜΕΤΡΙΑ p161

λυκε?ου ευκλε?δειο?-γεωμετρ?α-α p204.pdf

λυκε?ου ευκλε?δειο?-γεωμετρ?α-β-και-γ p316.pdf

λυκε?ου ευκλε?δειο?-γεωμετρ?α-β-και-γ_1 p316.pdf.pdf

?

?

?

>>>euclid

?

>>>euclid_ie6

?

>>>euclid_w9x

?

>>>Others

?

Aristotelikh teleologia p15.pdf?????????? ok

?

?

Aristotle Graece1 p91.pdf

?

?

okokok

APIΣTOTEAOTΣ Graece1 p91

?

?

AristotleYYY Graece p684.pdf

?

Aristotle Graece1 p812.pdf??????????? 25

?

Aristotle Metaphysica p964.pdf ...................... 27

?

?

?

diophantus_Arithmetica vol_I p495.pdf??????????? 20

?

?

?

okokok

mathimatika_tetradia_teyhos_1

?

?

okokok

?γγελου Απ? τι? προσπ?θειε? για απ?δειξη του 5ου Αιτ?ματο? του Ευκλε?δη στι? μη Ευκλε?δειε? Γεωμετρ?ε? Διπλωματικ? Εργασ?α p127

?

?

okokok

Παπαντων?ου Η εξ?λιξη τη? γεωμετρικ?? σκ?ψη? απ? τον Ευκλε?δη μ?χρι σ?μερα p27

?

?

okokok

Χαραλ?μπου?Ιστορ?α των Μαθηματικ?ν p53

?

?

http://users.ntua.gr/dimour/euclid/

http://users.ntua.gr/dimour/euclid/index.html

?

http://free-ebooks.gr

?

https://el.wikipedia.org/wiki/

%CE%A3%CF%84%CE%BF%CE%B9%CF%87%CE%B5%CE%AF%CE%B1

https://el.wikisource.org/wiki/

%CE%A3%CF%84%CE%BF%CE%B9%CF%87%CE%B5%CE%AF%CE%B1

?

http://www.freeinquiry.gr/pro.php?id=3100

?

http://www.mathher.gr/s/2011-02-04-18-06-41/2011-02-12-11-02-00

?

?

?

?

?

?Greek Websites

http://www.acci.gr

http://www.aegean.gr/

http://www.agoda.gr/

http://www.antagonistikotita.gr/

http://www.aodos.gr/

http://www.blogle.gr/

http://www.books-in-greek.gr

http://www.cine.gr

http://www.contra.gr/

http://www.e-socrates.org/

http://www.ebge.gr

http://www.elea.gr/

http://www.ellinika.gr/

http://www.ellinikanea.gr/

http://www.ellinikoslogos.gr/

http://www.elta.gr/

http://www.enet.gr

http://www.epea.gr/

http://www.e-radio.gr

http://www.gr50.eu/

http://www.greekbooks.gr/

http://greekradios.gr/

http://www.hellaspath.gr

http://www.herbalife.gr/

http://www.hfc.gr

http://www.inpatra.gr/

http://www.kairatos.com.gr

http://www.neemo.gr/

http://www.onradio.gr/

http://lexicon.pathfinder.gr/

http://www.perizitito.gr/

http://www.routes.gr/

http://www.sarantakos.com

http://www.trtgreek.com/

http://www.united-hellas.com

http://www.visitgreece.gr

http://www.ypepth.gr

Bible

?

bible_gr_modern.chm????????????

Genesis


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希腊语文学
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
德语文学
deutsche literatur
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

http://www.dw.com/

Lei Li
Programmvertrieb: China, Taiwan, Hongkong, Singapur, Vietnam, Myanmar
T.+49.228.429-2603
lei.li@dw.com

dw-akademie@dw.com
info@dw.com

=============================

http://deutsche-literaturgesellschaft.de/

Empfang@Deutsche-Literaturgesellschaft.de

=============================

http://china.ahk.de/about-us/contact-us-in/east-china/#c113002

Simone Pohl

Delegate and Chief Representative of Delegation of German Industry and Commerce Shanghai Executive Director and Board Member of German Chamber of Commerce in China – Shanghai

+86-21-5081-2266

office@sh.china.ahk.de

=============================

https://www.goethe.de/ins/cn/de/sta/sha.html

Generalkonsulat der Bundesrepublik Deutschland Shanghai
101 Cross Tower
318 Fu Zhou Lu
Shanghai 200001, VR China

Tel.: +86 21 63912068
Fax.:?+86 21 63840269
info@shanghai.goethe.org

=============================

http://www.literaturcafe.de/infos-und-impressum/

Chefredakteur, Herausgeber und inhaltlich Verantwortlicher gem?? § 55 Rundfunkstaatsvertrag (RfStV) und Absatz 5 Telemediengesetz (TMG): Wolfgang Tischer

tischer@literaturcafe.de

=============================

http://www.spiegel.de/

Sehr geehrte(r) Dame/Herr,

ich erfreue mich sehr, Ihnen zu schreiben, um sich mit Ihnen über deutsche Literatur zu unterhalten. Ich besuche die Website spiegel.de sehr often, um mich stets mit der zeitlichen Entwicklung Deutschlands bekannt zu machen, und auch deutsche Nachrichten zu lesen und mein Deutsch weiter zu verbessern. Früher las ich noch viel die Zeitschrift Spiegel von der Bibliothek.

Ich bin ein 55-jähriger Chinese, aber am Alter von knapp 20 war ich schon 5 Fremdsprachen kennengelernt, dazwischen auch Deutsch, und zwar meine zweite und beliebteste Fremdsprache - die anderen waren Russisch, Französisch, Englisch und Esperanto, die ich weiterhin sudiere bis heute, plus Griechisch und einbißchen Lateinisch und Hebräisch.

Damals habe ich schon einige kurzen Romane und Dichtungen teilweise von deutsch ins chinesisch übersetzt, wenn ich an der sogannanten deutschen Klassen von 200 Studenten, an der Tongji Universität, Schanghai, studierte, wie z.B. die folgenden:

  • "Ein Fall für Moll"
  • "Kommisar Ermer's Schwierigster Fall"
  • "Tod vor dem Fernsehrschirm"
  • "Willkommen und Abschied (Goethe)"
  • "Emilia Galotti"
  • "Verheissung"
  • "Erleuchtung"
  • "Das Kind"
  • "Wartet Nur"
  • "Die Schlesischen Weber"
  • "Lobgesänge auf König Ludwig"
  • "Enfant Perdu"
  • "新上任的亚历山大大帝
  • “最后的战争”
  • "他不在犯罪现场的证据"
  • "失去的赌注"

Für die letzten vier kann ich die deutschen Titel nicht finden.

Die Tongji Uni war in 1907 bei einem deutschen med. Doktor gegründet und ist eine der wichtigsten akademischen Austauschszentren zwischen China und Deutschland.

Nach den Studien war ich auch bei deutschen Unternehmen wie Heimann Opto-Elektronik (damals eine Siemens Tochterfirma), der damaliger Deutsche Babcock and auch TüV Rheinland in China angestellt und deswegen bin ich ganz bequem mit deutscher Sprache, Handel und Industrie zu jenen Zeiten.

Jedoch seit dem Millenium bin ich mich getrennt von der deutschen Welt, und seitdem habe ich kaum Kontakte mit der deutschen Nation,physikalisch etwa,weil ich eigenständig geblieben bin und nun habe ich viel weniger Chancen mit den deutschen Räume, nachdem ich mich an mein Heimatdorf hier etwa 180 km südwestlich Schanghai angesiedelt habe.

Jedoch habe ich mich nie aufgehört, deusch weiterzustudieren. Mit Internet kann ich noch zu deutschen Websiten gehen, und manchmal kann ich auch einige Romane auf deutsch herunterladen und zuhause ruhig lesen. Aber ich möchte doch mit deutschsprachigen Leuten in Kontakt nehmen, sich über deutsche Literatur diskutieren, und sich miteinnander über tägliches Leben unterhalten.

Und was als bedeutendest ist, daß ich eine Biographie über meine Mutter schreiben, und vielleicht auch diese ins deutsch übersetzen will. Meine Mutter war letztes Jahr gestorben, für mich, am Alter 81. Ihre Biographie zu schreiben wird meine wichtigste Aufgabe meines Lebens. Und ich konnte vieleicht auch meine Autobiographie schreiben, vielleicht auch auf deutsch, neben Chinesisch und Englisch. Diese Schreibensprojekte werden jahrelang dauern, und sind auch abhängig davon, wie gut meine Lebenssituation aussehen könnte.

Nun, bitte sagen Sie mir, ob Sie mir bei meiner Studie deutscher Literatur helfen könnten oder nicht. Ich wollte manchmal nach Schanghai oder andere Städte fahren, um sich mit deutschen Freunden zu treffen. Vielleicht könnten Sie mir schon einige vorschlagen und einführen.

Eine weitere Möglichkeit wäre es, daß ich wieder für deutsche Unternehmen oder Organisationen arbeiten kann. Ich kann nur sehr schwierig mit der außen Welt kommunizieren, wenn ich in einem isolierten kleinen Dorf lebe.

Noch weitere Möglichkeit wäre es jedoch, daß ich mit meinen Erfahrungen und Kenntnissen deutsche Firmen, Technologien und Produkte in die Provinz Zhejiang einführen kann. Es gibt jetzt nicht viel deutsche Anwesentheit hier in der Provinz, während es viel zu viel dort in Schanghai schon existiert.

Vielen dank im voraus und mit meinen besten Grüssen!

Mark Chen
aus Huzhou, Provinz Zhejiang, VR China
Weitere Informationen werden ich Ihnen gerne zur Verfügung stehen.


Hebrew

It was mainly for understanding Hebrew Bible that I started the learning process. Right now I am still unable to write the Hebrew alphabet and it is extremely difficult to learn a language very different from all others. My another motive is to learn Hebrew (Jewish, Israelites) people who I consider as one of the two nations who have contributed to the world civilization in the human history – the another is Greek.?

Upto now I can’f find a book or listening materials on the Internet, although I did borrow a book or two from the library but they seems old. Below are websites with some kinds of Hebrew information and learning materials:

000Hebrew.doc
000Hebrew201111271.doc
000Hebrew201111272.doc

Lectures

?Barrick WORKBOOK FOR A GRAMMAR FOR BIBLICAL HEBREW p76

?

Benner The Ancient Hebrew Language and Alphabet p230.pdf

Benner The Ancient Hebrew Lexicon of the Bible p616.pdf

Cook Biblical Hebrew A Student Grammar p244 2009.pdf

Cook Biblical Hebrew A Student Grammar p244 2010.pdf

?

Cook Biblical Hebrew A Student Grammar p244 2011.pdf?????????

24

?

?

?

Cook THE BIBLICAL HEBREW VERBAL SYSTEM A GRAMMATICALIZATION APPROACH p355.pdf

?

?

Davidson An introductory Hebrew grammar p162

15

?

?

Franz hebr1 p22.pdf

Franz hebr2 p17.pdf

Franz hebr3 p26.pdf

?

?

fsi.pdf??????????????? 52

?

GalEnei The Hebrew Letters p186.pdf

?

KAUTZSCH Gesenius - Hebrew Grammar p486.pdf

?

Kittel Biblical Herbrew a Text and work book p451

27

?

?

?

Kreuzer Hebr?isch – Grundwortschatz hebr-500 p9.pdf

?

Lang Hebr?isch mit der Brechstange p32.pdf

?

>>>palgemayim>>>

1-1_diyice_di01danyuan.pdf????????? 24 / 36

?

?

Putnam Toward Reading & Understanding Biblical Hebrew p403

13

?

?

Stitz stone The Online Hebrew Tutorial p72.pdf????????????????????? 16

?

Strong A CONSISE DICTIONARY OF THE WORDS IN THE HEBREW BIBLE p1570.pdf

?

?

OKOKOK

The Hebrew Café lesson 2 p15

?

?

thompson_Learning Biblical Hebrew Vocabulary_2011 p200.pdf

waltke An Introduction to Biblical Hebrew Syntax p826.pdf

?

?

?

Websites

!!!!!!!!!!!!!!!!!!!!!!!!!?

http://www.101languages.net/hebrew/?

?

http://www.shalom.50megs.com/ ????????????????????

?

!!!!!!!!!!!!!!!!!!!!!!!!!? with sound

http://hebrewverb.hul.huji.ac.il/steps/run.htm

?

!!!!!!!!!!!!!!!!!!!!!!!!!?

http://www.akhlah.com/?

?

!!!!!!!!!!!!!!!!!!!!!!!!!?

http://www.ancient-hebrew.org/?

?

http://www.ancientscripts.com/hebrew.html

?

!!!!!!!!!!!!!!!!!!!!!!!!!? with sound

http://www.animatedhebrew.com/lectures/index.html

http://www.animatedhebrew.com/lectures/chapter_5/chapter_5.html

?

Hebrew Audio Bible

http://aoal.org/hebrew_audiobible.htm

?

http://www.associatedhebrewschools.com/

?

???????????????????????

http://www.avinou.org/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.beverlyhillschabad.com/reading-hebrew/pages/main-page.htm

?

http://www.bhu.edu/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.biblicalhebrew.com/

?

http://www.biblicalulpan.org/

http://www.classicalhebrew.com/

?

?????????????????

http://www.dailyhebrew.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://gloss.dliflc.edu/Default.aspx

?

http://www.easyhebrew.com/

?

????????????????????

http://hebrew.fhl.net/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hebrew.ecott.ch/

?

!!!!!!!!!!!!!!!!!!!!!!!!!

http://foundationstone.com.au/OnlineHebrewTutorial.html

http://www.fourmilab.ch/etexts/www/hebrew/Bible/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://freelanguage.org/learn-hebrew

?

http://www.ha-mtl.org/

http://www.haaretz.co.il/

?

??????????????????????????

http://www.hagalil.com/iwrith/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hareshima.com/Study/hebrew.asp

?

???????????????????

http://www.hebraicum.de/

?

????????????????????????

http://www.hebraeischkurs.de/

?

???????????????????

http://www.hebreu.org/

?

????????????????????

http://www.hebreunet.org/

?

http://hebrew-academy.huji.ac.il/english.html

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hebrew-language.com/

?

http://www.hebrew-learning-center.com/eng_info.php

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hebrew-verbs.co.il/

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hebrew4christians.com/

?

http://www.hebrewbooks.org/

http://www.hebrewcollege.edu/

http://www.hebrewetymology.com/

http://www.hebrewinstituteofboston.org/

http://www.hebrewlanguage.biz/

?

????????????????????

http://www.hebrewlanguage.com/

?

????????????????????

http://www.hebrewlanguage.net/

?

http://hebrewlearningcircles.com/

http://www.hebrewletters.com/?

http://www.hebrewmadeeasy.com/main.html

http://www.hebrewnational.com/index.jsp

http://www.hebrewonline.com/default.asp

http://hebrewonlineblog.com/

http://www.hebrewonthego.txt.co.il/

http://hebrewpodcasts.com/?

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hebrewpsalms.org/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://hebrewresources.com/viewpage.php?page_id=57

?

http://www.hebrewsoft.com/

http://www.hebrewsongs.com/

http://www.hebrewworld.com/

http://www.hebrewtrans.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.hebrewoldtestament.com/

?

http://www.hebroots.org/

http://www.hlacharterschool.org/

http://www.huc.edu/

http://www.huji.ac.il/huji/eng/

http://hebrewverb.hul.huji.ac.il/ab_project/login/mainmenu.html#

http://hebrewverb.hul.huji.ac.il/sipuratz/run.htm

http://bet.iba.org.il/

http://www.ihcindy.org/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.in-hebrew.co.il/

?

http://www.instanthebrew.com/?

?

??????????????????????????????

http://www.instructioneducation.info/inhalthebr.html

?

http://www.ithl.org.il/

http://www.ivrit.org/

http://www.jerusalem-online.org

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.jewfaq.org/alephbet.htm

?

http://www.jewish-languages.org/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.jr.co.il/aliyah/hebrew.htm

http://www.jr.co.il/hotsites/j-hebrew.htm

http://www.jr.co.il/hotsites/j-hebrew.htm

?

?????????????????????????

http://www.languageguide.org/hebrew/

?

http://www.learn-hebrew.co.il/

?

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.learn-hebrew-phrases.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.learnhebrew.org.il/

?

http://www.learnhebrewisrael.com/

http://learnhebrewpod.com/?

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.linguanaut.com/learn_hebrew.htm

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.lonweb.org/link-hebrew.htm

?

http://www.middlebury.edu/academics/ls/hebrew/

http://www.milingua.com/

?

?????????????????????

http://www.milon.li/

http://www.milon.li/Hebraeische_Grammatik.html

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.morim.com/games.htm

?

http://www.multilingualbooks.com/hebrew.html

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.my-hebrew-dictionary.com/

?

http://www.myhebrewtutor.com/

http://www.mylanguageexchange.com/Learn/Hebrew.asp

?

?????????????????????

http://mylanguages.org/fr/hebreu_apprendre.php

?

http://www.nirdagan.com/hebrew/

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.njop.org/html/interactive_hebrew.html

http://hebrewjudaic.as.nyu.edu/page/home

http://www.ochjs.ac.uk/

http://www.omniglot.com/writing/hebrew.htm

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.palgemayim.net/

?

http://www.qsm.co.il/Hebrew/hebrew.htm

?

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.qwlearning.com/learnhebrew/

?

???????????????????

http://www.sefarim.fr/

?

http://www.stanford.edu/class/hebrew/

http://www.studylight.org/lex/heb/

http://www.snunit.k12.il/heb_new.html

http://www.tau.ac.il/~hebrew/

http://www.thehebrewhammer.com/

?

?????????????????????

http://www.themelios-genji.net/

?

http://www.arts.ualberta.ca/JHS/

?

!!!!!!!!!!!!!!!!!!!!!!

http://www.clas.ufl.edu/llc/IsraeliHebrew/

?

?

!!!!!!!!!!!!!!!!!!!!!!

http://www.ulpan.net/

http://www.ulpanet.com/

http://www.ulpanor.com/ ?

?

!!!!!!!!!!!!!!!!!!!!!!

http://www.carla.umn.edu/lctl/VAVA/audio/hebrew/

http://carla.acad.umn.edu/lctl/VAVA/audio/hebrew/

?

????????????????????????

http://www.hebraeisch.unibas.ch/?

http://www.unitedhebrew.org/Home.aspx

?

!!!!!!!!!!!!!!!!!!!!!!

http://babel.uoregon.edu/yamada/fonts/hebrew.html

http://darkwing.uoregon.edu/~ylcflx/Aleph-Bet/tutorials.html

http://darkwing.uoregon.edu/~ylcflx/Aleph-Bet/tutorials/0220.html

?

!!!!!!!!!!!!!!!!!!!!!!

http://www.laits.utexas.edu/hebrew/heblang/video_clips.shtml

http://www.laits.utexas.edu/hebrew/

http://www.laits.utexas.edu/hebrew/heblang/tutorials/new/b1flashcards.html

http://www.laits.utexas.edu/hebrew/heblang/tutorials.shtml?

?

http://www.washington.edu/students/crscat/hebrew.html

http://www.whctemple.org/

http://www.words.co.il/

?

!!!!!!!!!!!!!!!!!!!!!!

http://artsci.wustl.edu/~etzion/lessons.html

?

http://www.zigzagworld.com/hebrewforme

?

!!!!!!!!!!!!!!!!!!!!!!

http://www.zionism-israel.com/hebrew/

?

fsi.pdf??????????????? 40
2017-02-12


Latin

My idea to learn Latin was initiated when I was reading “the Mathematical Principles of Natural Philosophy or Principia” by Isaac Newton. I tried both the English and Chinese translations but both were hard to read. And not only this, but also because I want to read original works of the greatest scientists in the time period of the 16th to mid 19th centuries where most scientific books were written in Latin.

Latin.doc

Books

?

<DIR> Cambridge

okokok

Cambridge Latin Course Book 1 p204.pdf?????????????

?

?

okokok

Cambridge Latin Course Book 2 p189.pdf????????

?

?

?

okokok

Cambridge Latin Course book4_Excerpt_001

?

?

okokok

Cambridge Latin Course book4_Excerpt_002

?

?

?

http://www.somdom.com/latin/t37624

http://www.mediafire.com/download/8ivxf7mnd2bwxoz/Cambridge+Latin+Book+1.pdf

http://www.mediafire.com/?8ivxf7mnd2bwxoz

http://www.mediafire.com/download/0455t556dgg9oc3/Cambridge+Latin+Book+2.pdf

http://www.mediafire.com/?0455t556dgg9oc3

http://internetclassics.blogspot.com/2012/01/cambridge-latin-course-2-levels.html

http://www.drshirley.org/latin/links01.html

http://srdt.sotite.com/pdf/1/cambridge-latin-course-book-2-translation.html

?

?

Collar Beginners Latin Book 1891 p293

163

?

?

?

?

DOOGE Latin For Beginners 1909 p365

DOOGE Latin For Beginners 1911 p123

DOOGE Latin For Beginners p358

?

?

?

?

<DIR> LatinFosterxxx

Foster First Experience 2002 p149.pdf

Latin_Main_PageX.pdf

Third_Experience.pdf

?

Reed Julia p114

?

?

<DIR> Wheelock

Wheelock.pdf????????????????? 34

Wheelock's Latin-6th Ed.pdf????????????? 56

XXXWheelock's Latin Reader, The Wheelock Latin Series.pdf

韦洛克拉丁语教程中文OCR版带书签.pdf???????????? 25

?

?

?Scientists

?

AnglicusAlfredus_De_motu_cordis p146.pdf??????? 30

?

Boskovic-Theoria_philosophiae_naturalis p362.pdf?????????? 11

?

Des-Cartes Meditationes p41.pdf???????????? ??8

?

Diophauti

?

Euler Enestrom_Indexxxx.pdf

?

okokok

Euler INSTITUTIONUM CALCULI DIFFERENTIALIS Vol I p299.pdf

?

?

?

Euler INSTITUTIONUM CALCULI INTEGRALIS Vol III p532.pdf

82

?

Euler INSTITUTIONUM CALCULI INTEGRALIS VOL II part4ch3xxx.pdf

Euler Institutionum calculi integralis_VOL2.pdf????? 31?? / 459

?

Gauss Disquisitiones arithmeticae p527.pdf????????????? 22

Gauss Disquisitiones arithmeticae p703.pdf????????????? 25

?

Gauss DISQUISITIONES GENERALES CIRCA SUPERFICIES CURVAS p37

?

Kepler Mysterium cosmographicum p171

?

Lagrange

?

?

Leibniz Dissertatio Arte Combinatoria p85

16

?

?

?

Legendre

?

?

Newton Philosophiae Naturalis Principia Mathematica p316.pdf?????????

22

?

?

Newton Philosophiae Naturalis Principia Mathematica p496.pdf

?

?

Newton Principia p574.pdf

?

?

?Latin literature

?

Latin literature?

?

http://ucblibraries.colorado.edu/research/subjectguides/classics/greek&latinliterature.htm#OnlineRESGREEK

http://ucblibraries.colorado.edu/research/subjectguides/classics/greek&latinliterature.htm#OnlineRESCOM

http://www.thelatinlibrary.com/

https://www.gutenberg.org/wiki/Gutenberg:Offline_Catalogs

http://www.paralumun.com/romelit.htm

http://www.thelatinlibrary.com/classics.html

https://en.wikipedia.org/wiki/Latin_literature

?

?

Cicero De finibus bonorum et malorum p557

41

?

?

Cicero De oratore p524.pdf

?

?

Websites

?

http://vip.6to23.com/changkzl/qihua/latin/

http://www.auxilium-online.net/?? ??

http://www.babylon.com/define/112/Latin-Dictionary.html?

?

???????????????????????

http://www.cambridgeonlinelatin.com/

?

???????????????????????

http://www.cambridgescp.com/page.php?p=clc%5Eoa_book1%5Estage1??

?

!!!!!!!!!!!!!!!!!? finished

http://www.cherryh.com/www/latin_language.htm

?

http://www.churchlatin.com/

?

!!!!!!!!!!!!!!!!!

$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

http://humanum.arts.cuhk.edu.hk/Lexis/Wheelock-Latin/??

http://humanum.arts.cuhk.edu.hk/Lexis/Wheelock-Latin/grote-note.html

http://humanum.arts.cuhk.edu.hk/Lexis/Wheelock-Latin/wheelock.zip

?

!!!!!!!!!!!!!!!!!

www.du.edu/~etuttle/classics/latin/learnlat.htm?

?

!!!!!!!!!!!!!!!!!dictionary

http://users.erols.com/whitaker/words.htm

?

!!!!!!!!!!!!!!!!!

http://www.frcoulter.com/latin/??

?

http://www.cherryh.com/www/latin1.htm

?

!!!!!!!!!!!!!!!!dictionary

http://www.freedict.com/onldict/lat.html??

?

!!!!!!!!!!!!!!!!!

http://avitus.alcuinus.net/schola_latina/conjugatio_en.php

?

http://freelanguage.org/learning-latin/learning-latin-free

?

!!!!!!!!!!!!!!!!? Great? Finished

http://www.gettingstartedwithlatin.com/

?

!!!!!!!!!!!!!!!!?

?

???????

http://groups.google.com/groups?q=alt.language.latin&hl=en ?

?

!!!!!!!!!!!!!!!!?

http://www.hhhh.org/perseant/libellus/aides/allgre/allgre.contents.html?

?

!!!!!!!!!!!!!!!!? ?????????????

http://www.ilatin.net/talks/c217906?

?

http://www.inrebus.com/assistant.php

?

!!!!!!!!!!!!!!!!?

http://latin-language.co.uk/

?

http://www.latin-mass-society.org/simplicissimus/index.htm

http://www.latin-mass-society.org/simplicissimus/unit3.pdf

http://www.latin-mass-society.org/simplicissimus/index.htm

http://latinforum.org/??

?

!!!!!!!!!!!!!!!!? ?????????????

www.latinlanguage.net

?

www.latinlanguage.org/

?

http://www.lexiconer.com/power-glide/power-glide-latin-ultimate-course.html

?

!!!!!!!!!!!!!!!!! Grammar

http://www.lifeisaprayer.com/other_sites/latin/resource_page.html

http://www.lifeisaprayer.com/other_sites/latin/resource_files/study_guides/study_guide.html

?

http://www.lvpa.de/

?

!!!!!!!!!!!!!!!!? ????????????

http://www.memorare.com/latin/

?

http://www.memoriapress.com/descriptions/Henle1.html

http://community.middlebury.edu/~harris/EngLatGrammar.html

http://www.mylanguageexchange.com/Learn/Latin.asp ?

http://latinum.mypodcast.com/?

?

!!!!!!!!!!!!!!!!?

?

?

!!!!!!!!!!!!!!!!? Grammar

http://lysy2.archives.nd.edu/cgi-bin/words.exe

http://archives.nd.edu/latgramm.htm ?

?

http://openlearn.open.ac.uk/mod/resource/view.php?id=210271

?

!!!!!!!!!!!!!!!!? dictionaries

http://www.perseus.org/cgi-bin/enggreek?lang=la ?

?

http://www.quasillum.com/latin/latin-activities.php

?

!!!!!!!!!!!!!!!!? A Latin-to-English Translation Assistant

http://www.quicklatin.com/

?

???????????????????

http://www.radiovaticana.org/

http://www.ravendays.org/latin/lists/listindex.html

?

?????????????

http://www.semi-fluent.com/

?

!!!!!!!!!!!!!!!!?

http://www.slu.edu/colleges/AS/languages/classical/latin/tchmat/wh-prax.html?

?

???????????????

http://flclp.sourceforge.net/? http://sourceforge.net/projects/flclp/ ??

?

!!!!!!!!!!!!!!!!!!!!

http://www.textkit.com/

?

http://www.thelatinlibrary.com/

?

Glossary of Latin Words

http://comp.uark.edu/~mreynold/recint1.htm ?

?

!!!!!!!!!!!!!!!!?? Dictionary

http://www.sunsite.ubc.ca/LatinDictionary/index.html

?

?????????????

www.unavoce.org/latin.htm

?

!!!!!!!!!!!!!!!!!!!!

http://www.wheelockslatin.com/chapters/one/index.html??

http://www.wheelockslatin.com/chapters/six/index.html

?

http://groups.yahoo.com/group/ctnlatin/

?

?Bible

?

Latin Bible

?

The Holy Bible: Latin Vulgate Translation p1066

3

?

The Holy Bible: Latin Vulgate Translation p1388

The Holy Bible: Latin Vulgate Translation p1839
2017-02-12


Russian

Russian was my first foreign language and I began my Russian study at middle school in 1994. In 1980 my Russian level was at its peak when I was able to read scientific books in Russian. But later I have completely ignored it and suddenly in 2007 I found it impossible to even pronounce the Russian words. It terrified me and I decided to recover my Russian proficiency to a degree of the 1980’s, i.e. to read simple scientific literature. Now two years later, after some hesitation – there was time when I did want to maintain my language proficiency other than English – I could catch up with the Russian level a bit. And now I can of course pronounce Russian words and sentences but although can understand simple Russian texts. Another year is needed to fully recover my previous level.

Documents

Russian.doc

Russian20060802.doc
Russian20080915.doc

Русская литература

Verbrechen und Strafe??? Fyodor M. Dostoyevsky

Die D?monen? Fyodor M. Dostoyevsky

Der Idiot Fyodor M. Dostoyevsky

Dolstoievski L’Idiot p623

?

Die Brüder Karamasow? Fyodor M. Dostoyevsky

Fjodor Dostojewski, Die D?monen

Dostoevsky Crime and Punishment p767

Dostoevsky Notes from the Underground p167

Dostoevsky The Brothers Karamazov p1313

Dostoyevsky The Idiot p913

Dostoevsky The Possessed

?

Николай Васильевич Гоголь

Gogol

Dead Souls

Die toten Seelen????

?

Арабески

Вечера на хуторе близ Диканьки

Вий

Выбранные места из переписки с друзьями

Коляска

маленького человека

Мёртвые души

?

okokok

Миргород

Гоголь Миргород Tom 2.pdf

?

?

?

Невский проспект

Нос

Петербургские повести

Повесть о том, как поссорился Иван Иванович с Иваном Никифоровичем

Портрет

Ревизор

Записки сумасшедшего

Тарас Бульба

Старосветские помещики

Шинель

?

Iwan Gontscharow

Oblomow

?

?

?

okokok

Кантор

Кантор Война и мир p609.pdf???????

?

?

?

Vladimir Nabokov

Lolita?????

?

Orczy

The Scarlet Pimpernel p343

?

okokok

Пушкин

Пушкин Евгений Онегин p150

?

?

okokok

Сент

Сент-Экзюпери Маленький принц

?

?

?

?

Толстой

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.levtolstoy.org.ru/lib/sb/book/1803

?

?

http://voinaimir.com/

http://voinaimir.tv/

?

?

?

http://www.culture.ru/movies/467

?

!!!!!!!!!!!!!!!!!!!!

http://www.etextlib.ru/Book/Details/6065

?

http://goldlit.ru/tolstoy/16-voina-i-mir-janr

?

!!!!!!!!!!!!!!!!!!!!

http://greatnote.ru/vojna_i_mir/

?

http://www.litra.ru/shortwork/get/swid/00056001184919816753/

?

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.litres.ru/lev-tolstoy/voyna-i-mir-kniga-1/

?

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://modernlib.ru/series/voyna_i_mir/

?

http://predanie.ru/tolstoy-lev-nikolaevich/

?

http://readly.ru/book/57637/

?

http://www.russianculture.ru/formp.asp?id=476?

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://rvb.ru/tolstoy/toc.htm

http://rvb.ru/tolstoy/tocvol_4.htm

http://rvb.ru/tolstoy/tocvol_5.htm

http://rvb.ru/tolstoy/tocvol_6.htm

http://rvb.ru/tolstoy/tocvol_7.htm

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://vk.com/

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

?

Krieg und Frieden

Anna Karenina

Der Tod des Iwan Illjitsch

?

?

Толстой Война И Мир Том1 p154

36

?

?

Толстой Война И Мир Том1 p249

?

Толстой Война И Мир Том1 p326

?

Толстой Война И Мир Toм1 p1452

?

Толстой Война И Мир Том2 p157

?

Толстой Война И Мир Том2 p277

?

Толстой Война И Мир Toм2 p414

?

Толстой Война И Мир Том3 p111

?

Толстой Война И Мир Том3 p156

?

Толстой Война И Мир Том3 p291

?

Толстой Война И Мир Toм3 ЧАСТЬ ПЕРВАЯ? p107

?

Толстой Война И Мир Том3_4 p1295

?

Толстой Война И Мир Toм3_4 p1295

80

?

Толстой Война И Мир Том4 p88

?

Толстой Война И Мир Том4 p249

?

?

Leo Trotzki

Mein Leben

?

?

Anton P. Tsjekhov

Erz?hlungen.?

?

?

Iwan Turgenew

V?ter und S?hne

?

?

okokok

Михаил Шолохов

Шолохов Тихий Дон doc

Тихий Дон

* КНИГА ПЕРВАЯ *

* ЧАСТЬ ПЕРВАЯ *

I

?

?

?

?

?

http://www.alterlit.ru/

?

http://www.culture.ru/

?

!!!!!!!!!!!!!!!!!!

http://www.etextlib.ru/

?

http://feb-web.ru/

?

http://www.fplib.ru/

?

http://goldlit.ru/

?

http://www.gramma.ru/LIT/

!!!!!!!!!!!!!!!!!!

http://www.klassika.ru/

http://www.klassika.ru/read.html?proza/tolstoj/voskr.txt

?

?

http://lib.ru/RUSSLIT/

http://www.librar.ru/

http://www.liter.ru/

http://www.literature-xix.ru/

http://www.literature-xix.ru/gogol/

?

http://www.litra.ru/

?

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.litres.ru

?

http://www.litrusia.ru/

http://modernlib.ru/

http://rulitera.narod.ru

?

http://www.peremeny.ru/

http://www.reallit.ru/

http://rulinet.ru/

?

http://www.russianculture.ru/

?

http://russkay-literatura.ru/

?

http://www.rvb.ru/

?

Scientists

Nikolai Basov

Никола?й Генна?диевич Ба?сов

?

Sofia Kovalevskaya

Со?фья Васи?льевна Ковале?вская

?

?

?

?

Mikhail Vasilievich Lomonosov

Михаи?л Васи?льевич Ломоно?сов

?

http://feb-web.ru/

http://feb-web.ru/feb/lomonos/default.asp

?

!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://www.runivers.ru/lib/book6872/192765/

?

http://www.rvb.ru/18vek/lomonosov/toc.htm

?

okokok

Ломоно?сов Physics and Chemistry p627

?

?

?

okokok

Dmitri Mendeleev

Dmitri Mendeleev

Дми?трий Ива?нович Менделе?ев

Мендел?евъ КЪ ПОЗНАНИЮ РОССИ p158

?

?

?

?

Ivan Pavlov

Ива?н Петро?вич Па?влов

?

?

Study

俄语教程

Russian literature

Russian books / lessons / lectures / courses

Русский язык

Le Russe

Russisch

lernziele-russisch_b1.pdf?????????? 60

大学俄语词汇语法精解???????? 30

《学俄语讲俄语》系列俄语教学 28

http://www.eyxxw.com/

http://ru.hujiang.com/

http://www.livemocha.com/??

http://masterrussian.com/

http://www.myruru.com/

http://polusharie.com/?

http://www.rambler.ru/

http://www.rusns.cn/

http://www.russefacile.fr/

www.russianlessons.net??

http://www.russianshanghai.com/

www.russnet.org

?

Bible

?

Russian_Bible_80_Old_Testament.pdf?????????

10

Russian_Bible_90_New_Testament.pdf
2017-02-12


@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
俄语文学
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德语文学
deutsche literatur
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

http://www.dw.com/

Lei Li
Programmvertrieb: China, Taiwan, Hongkong, Singapur, Vietnam, Myanmar
T.+49.228.429-2603
lei.li@dw.com

dw-akademie@dw.com
info@dw.com

=============================

http://deutsche-literaturgesellschaft.de/

Empfang@Deutsche-Literaturgesellschaft.de

=============================

http://china.ahk.de/about-us/contact-us-in/east-china/#c113002

Simone Pohl

Delegate and Chief Representative of Delegation of German Industry and Commerce Shanghai Executive Director and Board Member of German Chamber of Commerce in China – Shanghai

+86-21-5081-2266

office@sh.china.ahk.de

=============================

https://www.goethe.de/ins/cn/de/sta/sha.html

Generalkonsulat der Bundesrepublik Deutschland Shanghai
101 Cross Tower
318 Fu Zhou Lu
Shanghai 200001, VR China

Tel.: +86 21 63912068
Fax.:?+86 21 63840269
info@shanghai.goethe.org

=============================

http://www.literaturcafe.de/infos-und-impressum/

Chefredakteur, Herausgeber und inhaltlich Verantwortlicher gem?? § 55 Rundfunkstaatsvertrag (RfStV) und Absatz 5 Telemediengesetz (TMG): Wolfgang Tischer

tischer@literaturcafe.de

=============================

http://www.spiegel.de/

Sehr geehrte(r) Dame/Herr,

ich erfreue mich sehr, Ihnen zu schreiben, um sich mit Ihnen über deutsche Literatur zu unterhalten. Ich besuche die Website spiegel.de sehr often, um mich stets mit der zeitlichen Entwicklung Deutschlands bekannt zu machen, und auch deutsche Nachrichten zu lesen und mein Deutsch weiter zu verbessern. Früher las ich noch viel die Zeitschrift Spiegel von der Bibliothek.

Ich bin ein 55-jähriger Chinese, aber am Alter von knapp 20 war ich schon 5 Fremdsprachen kennengelernt, dazwischen auch Deutsch, und zwar meine zweite und beliebteste Fremdsprache - die anderen waren Russisch, Französisch, Englisch und Esperanto, die ich weiterhin sudiere bis heute, plus Griechisch und einbißchen Lateinisch und Hebräisch.

Damals habe ich schon einige kurzen Romane und Dichtungen teilweise von deutsch ins chinesisch übersetzt, wenn ich an der sogannanten deutschen Klassen von 200 Studenten, an der Tongji Universität, Schanghai, studierte, wie z.B. die folgenden:

  • "Ein Fall für Moll"
  • "Kommisar Ermer's Schwierigster Fall"
  • "Tod vor dem Fernsehrschirm"
  • "Willkommen und Abschied (Goethe)"
  • "Emilia Galotti"
  • "Verheissung"
  • "Erleuchtung"
  • "Das Kind"
  • "Wartet Nur"
  • "Die Schlesischen Weber"
  • "Lobgesänge auf König Ludwig"
  • "Enfant Perdu"
  • "新上任的亚历山大大帝
  • “最后的战争”
  • "他不在犯罪现场的证据"
  • "失去的赌注"

Für die letzten vier kann ich die deutschen Titel nicht finden.

Die Tongji Uni war in 1907 bei einem deutschen med. Doktor gegründet und ist eine der wichtigsten akademischen Austauschszentren zwischen China und Deutschland.

Nach den Studien war ich auch bei deutschen Unternehmen wie Heimann Opto-Elektronik (damals eine Siemens Tochterfirma), der damaliger Deutsche Babcock and auch TüV Rheinland in China angestellt und deswegen bin ich ganz bequem mit deutscher Sprache, Handel und Industrie zu jenen Zeiten.

Jedoch seit dem Millenium bin ich mich getrennt von der deutschen Welt, und seitdem habe ich kaum Kontakte mit der deutschen Nation,physikalisch etwa,weil ich eigenständig geblieben bin und nun habe ich viel weniger Chancen mit den deutschen Räume, nachdem ich mich an mein Heimatdorf hier etwa 180 km südwestlich Schanghai angesiedelt habe.

Jedoch habe ich mich nie aufgehört, deusch weiterzustudieren. Mit Internet kann ich noch zu deutschen Websiten gehen, und manchmal kann ich auch einige Romane auf deutsch herunterladen und zuhause ruhig lesen. Aber ich möchte doch mit deutschsprachigen Leuten in Kontakt nehmen, sich über deutsche Literatur diskutieren, und sich miteinnander über tägliches Leben unterhalten.

Und was als bedeutendest ist, daß ich eine Biographie über meine Mutter schreiben, und vielleicht auch diese ins deutsch übersetzen will. Meine Mutter war letztes Jahr gestorben, für mich, am Alter 81. Ihre Biographie zu schreiben wird meine wichtigste Aufgabe meines Lebens. Und ich konnte vieleicht auch meine Autobiographie schreiben, vielleicht auch auf deutsch, neben Chinesisch und Englisch. Diese Schreibensprojekte werden jahrelang dauern, und sind auch abhängig davon, wie gut meine Lebenssituation aussehen könnte.

Nun, bitte sagen Sie mir, ob Sie mir bei meiner Studie deutscher Literatur helfen könnten oder nicht. Ich wollte manchmal nach Schanghai oder andere Städte fahren, um sich mit deutschen Freunden zu treffen. Vielleicht könnten Sie mir schon einige vorschlagen und einführen.

Eine weitere Möglichkeit wäre es, daß ich wieder für deutsche Unternehmen oder Organisationen arbeiten kann. Ich kann nur sehr schwierig mit der außen Welt kommunizieren, wenn ich in einem isolierten kleinen Dorf lebe.

Noch weitere Möglichkeit wäre es jedoch, daß ich mit meinen Erfahrungen und Kenntnissen deutsche Firmen, Technologien und Produkte in die Provinz Zhejiang einführen kann. Es gibt jetzt nicht viel deutsche Anwesentheit hier in der Provinz, während es viel zu viel dort in Schanghai schon existiert.

Vielen dank im voraus und mit meinen besten Grüssen!

Mark Chen
aus Huzhou, Provinz Zhejiang, VR China
Weitere Informationen werden ich Ihnen gerne zur Verfügung stehen.


Untitled Document

IC Technologies

VLSI is the most important technology of the world today and tomorrow, and this is the reason I have chosen it as my research focus in retation with math, particularly graph theory.

Nowadays CMOS based VLSI technology has reached its limits, therefore I will no more follow the silicon based IC technology, but the upcoming new promising computation circuits with radically new physics and chemistry and even biological fundamentals. But at the moment there is no sight of breakthrough. Just follow me to find out where this great leap will come true.

Before VLSI was my final science focus, there were several other science branches where I have spent a decade on studying, incl. fluid dynamics, solar science and thermodynamics.

since 2008-10-1

I've been learning IC technologies since long. Earlier I have compiled a listing of my study plan, see this one: vlsi.chm. This file was prepared in February 2017, and since then I have made a lot of changes ot my plan.

G:\studies\000VLSIChip\_Literature

?????????????????????????

?????????????????????????

AULETTA Quantum Mechanics p758

GENNARO AULETTA

19

?????????????????????????

?????????????????????????

Ballentine Quantum mechanics p673

25

Binney The Physics of Quantum Mechanics p310
James Binney

Branson Quantum Physics p548

Jim Branson

CHEW Quantum Mechanics Made Simple: Lecture Notes p218
Weng Cho CHEW

Cohen Lecture Notes in Quantum Mechanics p293
Doron Cohen

Cresser Quantum Physics Notes p238
J D Cresser

Dawson Quantum Mechanics: Fundamental Principles and Applications p435
John F. Dawson

DeGrand Quantum Mechanics p356
Thomas DeGrand

EISBERG QUANTUM PHYSICS of Atoms, Molecules, Solids, Nuclei, and Particles p866
Second Edition
ROBERT EISBERG

?????????????????????????

?????????????????????????

Fitzpatrick Quantum Mechanics p222

Richard Fitzpatrick

Greensite Lecture Notes on Quantum Mechanics p391
J. Greensite

?????????????????????????

?????????????????????????

Gruska QUANTUM COMPUTING p438

96

operational quantum physics

quantum superoperator circuits

MERZBACHER Ouantum Mechanics p670
THIRD EDITION
EUGEN MERZBACHER

Gregory Naber
Naber Foundations of Quantum Mechanics p575

[Nielsen2010]

Nielsen Quantum Computation and Quantum Information p698

31

Orden Quantum Mechanics p293
Lecture Notes
J. W. Van Orden

Rae Quantum Physics A Beginner’s Guide p235
Alastair I. M. Rae

Styer The Physics of Quantum Mechanics p294

Dan Styer

Thankappan QUANTUM MECHANICS p553
Second Edition
V.K. Thankappan

van Dommelen Quantum Mechanics for Engineers p1623
Leon van Dommelen

van Dommelen Fundamental Quantum Mechanics for Engineers p324
Leon van Dommelen

Weinberg Lectures on Quantum Mechanics p378
Steven Weinberg

?????????????????????????

?????????????????????????

Weste CMOS VLSI Design A Circuits and Systems Perspective p867

2011

78

www.cmosvlsi.com

My VLSI Design Project

Study schedule and literature index

VLSI design Case studies

###############################################################
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00000designproject
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1frontend >>>

01规格制定详细设计

FinTek

FinTek F75373S/F75373SG Fintek Hardware Monitor IC Datasheet p49

Winbond

,

Old Chips/VLSI

chip_tech_general

Attention!!!

Directory Structure and File Names of the Computer Chip Technologies, particularly the next generations of IC technologies

If you have problems in display, then open the PDF file instead.

chiptech.htm

benchmark_chip.pdf

###############################################################
###############################################################
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Old Chips/VLSI
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graph matching
graph/subgraph isomorphism
simulated annealing

??????????????????????????????????????????????????????????????????
Baker CMOS Circuit Design Layout and Simulation 3rdEdition p1214
170
90

??????????????????????????????????????????????????????????????????
Glesner VLSI Design of Integrated Circuits p562

??????????????????????????????????????????????????????????????????
??????????????????????????????????????????????????????????????????
??????????????????????????????????????????????????????????????????
Harris Digital Design and Computer Architecture p561
76

2 . 7 KARNAUGH MAPS

??????????????????????????????????????????????????????????????????
Kaeslin Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication p879
386

??????????????????????????????????????????????????????????????????
Kang CMOS DIGITAL INTEGRATED CIRCUITS - Analysis and Design p683
2003
167

??????????????????????????????????????????????????????????????????
okokok
Mukherjee Introduction to NMOS and CMOS VLSI Systems Design p367
74

??????????????????????????????????????????????????????????????????
WAKERLY DIGITAL DESIGN PRINCIPLES PRACTICES p795
319

chip_design_general

00design.htm

0chip_design.pdf

design.htm

0contents.htm

0eda.htm

0flow.htm

0methodologies.htm

1specifications.htm

2architectural.htm

3functional.htm

4logic.htm

5circuit.htm

6physical.htm

7simulation.htm

8verification.htm

misc.htm

chip_design_physical

chip_design_physical.pdf

floorplanning .htm

partitioning.htm

placement.htm

routing.htm

routing_detailed.htm

routing_detailed_channel_routing.htm

routing_detailed_switchbox.htm

routing_global.htm

timing.htm

chip_design_routing
chip_design_routing.pdf

>>> routing_channel

  • 2layers_channel_routing.htm
  • dogleg_channel_routing.htm
  • left_edge_channel_routing.htm
  • manhattan_channel_routing.htm
  • over_the_cell_channel_routing.htm
  • topological_routing.htm
  • virtual_channel_router.htm
  • yoshimurakuh_channel_routing.htm

chip_special

00special.htm

0chip_special.pdf

3dic.pdf

3dvlsi.htm

3dvlsi_literature_a2g.htm

3dvlsi_literature_h2n.htm

3dvlsi_literature_o2z.htm

asic.htm

fpga.htm

fpga.pdf

integrated_optics.htm

@@@@@@@@@@@@@@@@@@@@@@@@

>>>3DIC

@@@@@@@@@@@@@@@@@@@@@@@@

Ferreira Architectural exploration methods and tools for heterogeneous 3D-IC p179

FPGA

New Generations of IC

My VLSI studies have been shifted many times, from quantum chips, to graphe FETS, to single electronics, to superconducting, to spintotronics, to molybdenum and to all other chips technologies such as

  • Nano IC technologies
  • DNA chips
  • Cellular chips
  • Gallium
  • Germanium
  • Indium
  • Molecular chips
  • Membrane chips
  • Neural computer
  • Photonic chips
  • Resonant tunneling IC
  • Reversible computing
  • Strained silicon chips
  • 3D IC

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New Generations of Chips
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List of literature

Graph Theory and Math for Advanced Computing (pdf)

@@@@@@@@@@@@@@@@@@@@@@@@
00spin
@@@@@@@@@@@@@@@@@@@@@@@@

spin.pdf

???????????????????????????????????????????
000Bürgler Spintronics p183
83

okokok
Chetan spin-electronics p14

???????????????????????????????????????????
000Fabian SEMICONDUCTOR SPINTRONICS p343
28

okokok
Maekawa Spin Current

okokok
Westervelt Spintronics p39.pdf

XXXXXXXXXXXXXXXXXXXXXXXXX
Winkler Spinelektronik p6.PDF
3

@@@@@@@@@@@@@@@@@@@@@@@@
graphene
@@@@@@@@@@@@@@@@@@@@@@@@

graphene_literature.htm

graphene_review.htm

????????????????????????
Anteroinen Graphene Transistors -Challenges and Opportunities p103
11

????????????????????????
Anteroinen Structure and Electrical Characteristics of Graphene Field Effect Transistors p71
5

Banerjee Non linear behaviour of three terminal graphene devices p74

Ferrari Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems p213

Lee Graphene Nanoelectronics - From Synthesis to Device Applications p158

Lindgren Electrochemical Functionalization of Epitaxial Graphene p55

Mahmood Towards Graphene based mono-molecular electronics Structural and electrical characterization of side-gated devices p214

Ou Graphene Semiconductor Heterojunctions and Devices p139

Pascal Graphene three-terminal nanojunction rectifiers p124

Pembroke Chemical and Physical Graphene Modifications p196

Rizzi On the fabrication and characterization of high-performance graphene electronic devices p81

Ruiz-Vargas SYNTHESIS, MORPHOLOGY AND PROPERTIES OF POLYCRYSTALLINE GRAPHENE MEMBRANES p134

Singh Quantum Hall Effect and Electromechanics in Graphene p186

Stander Transport measurements on graphene p-n junctions p141

okokok
SAGAR Graphene-based Field-effect Transistors p113

okokok
Thiele Carbon Nanotubes and Graphene for Electronics Applications 2010-2020 Technologies, Players & Opportunities p228

okokok
Yeric Graphene for Future VLSI p59

@@@@@@@@@@@@@@@@@@@@@@@@
carbon_nanotube OKOKOK
@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@@@@
0nano_deep_submicron
@@@@@@@@@@@@@@@@@@@@@@@@

nano_deep_submicron.pdf

Haselman The Future of Integrated Circuits A Survey of Nano-electronics p57.pdf
5

okokok
Lundstrom Understanding the Nanoscale MOSFET p64.pdf

Veendrick Deep-submicron CMOS ICs p286
19

@@@@@@@@@@@@@@@@@@@@@@@@
resonant_tunnellingOK
@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@
resonant_tunnellingOK
G:\studies\000VLSIChip\NGIPC\resonant_tunnellingOK
@@@@@@@@@@@@@@@@@@@@@@@@

Figueiredo Optoelectronic Properties of Resonant Tunnelling Diodes p260
2000
33

@@@@@@@@@@@@@@@@@@@@@@@@
molecularOK
@@@@@@@@@@@@@@@@@@@@@@@@

molecular_membrane.pdf

okokok
Cardelli Computing with Molecules p78.pdf

okokok
Kumar Molecular Diodes and Applications p7

okokok
Pischel Information Processing with Molecules – Quo Vadis p60.pdf

okokok
Walczak Simulations of molecular logic gates p6

@@@@@@@@@@@@@@@@@@@@@@@@
molybdeniumOK
@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@@@@
neural
@@@@@@@@@@@@@@@@@@@@@@@@

neural.pdf

@@@@@@@@@@@@@@@@@@@@@@@@
photonic
@@@@@@@@@@@@@@@@@@@@@@@@

photon.pdf

Hendry Architectures and Design Automation for Photonic Networks On Chip p161

@@@@@@@@@@@@@@@@@@@@@@@@
reversible_computingOK
@@@@@@@@@@@@@@@@@@@@@@@@

Aaronson The Classification of Reversible Bit Operations p66

????????????????????????????????

Car?e Design of Reversible Computing Systems Logic, Languages, and Circuits p54

July 7, 2012

15

Giles An investigation of some theoretical aspects of reversible computing p220

Kerntopf REVERSIBLE LOGIC CIRCUITS p53

Ollinger Periodicity and Immortality in Reversible Computing p69

@@@@@@@@@@@@@@@@@@@@@@@@
single_electronOK
@@@@@@@@@@@@@@@@@@@@@@@@

Acharya Development of room temperature operating single electron transistor using FIB etching and deposition technology p210

DUBEJSKY FABRICATION AND DC CHARACTERIZATION OF SINGLE ELECTRON TRANSISTORS AT LOW TEMPERATURE p148

Park Electron Transport in Single Molecule Transistors p165

?????????????????????????

Perry Digital to Analog Converter Design using Single Electron Transistors p73

April 29, 2005

14

Pott Gate-All-Around Silicon Nanowires for Hybrid Single Electron TransistorCMOS Applications p154

Simonian Design and Simulation of Single-Electron Molecular Devices p121

@@@@@@@@@@@@@@@@@@@@@@@@
superconducting not practicle
@@@@@@@@@@@@@@@@@@@@@@@@

superconduct.pdf

FELDMAN Josephson Junction Digital Circuits -- Challenges and Opportunities p22
3

Sterling Enabling Technologies for Peta FLOPS Computing p202
16

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&

@@@@@@@@@@@@@@@@@@@@@@@@
biocomputing OKOKOK no future
@@@@@@@@@@@@@@@@@@@@@@@@

>>>biocomputingOK

>>>biocomputing

OKOKOK
Moe-Behrens The biological microprocessor, or how to build a computer with biological parts p18

OKOKOK
Paun BIO-INSPIRED COMPUTING Achievements and Dreams p48

>>>Biomolecular Computing

OKOKOK
Grathwohl The Biological Plausibility of the Blob Model p116
OKOKOK
Reif Alternative Computational Models A Comparison of Biomolecular and Quantum Computation p51
OKOKOK
Wang Rapid engineering of versatile molecular logic gates using heterologous genetic transcriptional modules p4

>>>cellular

okokok
Abelson AMORPHOUS AND CELLULAR COMPUTING p88
okokok
Amos Molecular and Cellular Computing p44
okokok
Enaganti Cellular Computing p21
okokok
TerAvest Bacteria-based biocomputing with Cellular Computing Circuits to sense decide signal and act p10

>>>Amorphous Cellular Computing

>>>membrane

okokok
Bernardini Membrane Computing - current results and future problems p5
okokok
Bernardini Membrane Systems for Molecular Computing and Biological Modelling p164
okokok
Buitendijkmt Part II Membrane Computing p28
okokok
Csuhaj-Varju Proceedings 13th International Conference on Membrane Computing CMC13 p464
okokok
Dzitac Impact of Membrane Computing and P Systems in ISI WoS. Celebrating the 65th Birthday of Gheorghe P?un p10
okokok
Freund Pre-Proceedings of the 6th International Workshop on Membrane Computing WMC6 p549
okokok
Gheorghe The 15th International Conference on Membrane Computing p389
okokok
Giavitto The Topological Structures of Membrane Computing p27
okokok
Ibarra Membrane Computing A General View p19
okokok
Narayanan An Overview of Membrane Computing p63
okokok
Newton Visualization and Simulation of Membrane Computing p11
okokok
Nguyen AN IMPLEMENTATION OF MEMBRANE COMPUTING USING RECONFIGURABLE HARDWARE p19
okokok
Noack PRINCIPLES OF BIOLOGICAL INFORMATION PROCESSING MEMBRANE COMPUTING p33
okokok
Paun A guide to membrane computing p28

Paun Introduction to Membrane Computing p43

>>>DNA

okokok
Adleman Computing with DNA p8
okokok
AMOS DNA Computing p27

okokok
Amos Molecular and Cellular Computing p44
okokok
CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319
okokok
Cavaliere Biomolecular Implementation of Computing Devices with Unbounded Memory p15
okokok
Formanowicz DNA computing p10.pdf
okokok
Franco Biomolecular Computing – Combinatorial Algorithms and Laboratory Experiments p189

Fuentes Inference models in DNA COMPUTING p164
7

Rambidi Biomolecular computer roots and promises p15

>>>DNAzyme computing

>>>enzyme

>>>RNA Computing

mathematics for vlsi chip design
graph theory for vlsi chip design

After several years of learning I have realized that all these technologies are all not very optimistic in finding a practical way to replace silicon for faster computing. Therefore I have to think about whether ot not to continue in this direction.

Quantum Computer / Quantum Circuits / Quantum Registers / Quantum Gates / Quantum Algorithms / Quantum Programming / Quantum Physics

See

QUANTUM_BASICS

quantum_arithmetic.htm
quantum_communication.htm
quantum_complexity.htm
quantum_device.htm
quantum_electronics.htm
quantum_informatics.htm
quantum_information.htm
quantum_mechanics.htm
quantum_optics.htm
quantum_physics.htm
quantum_probability.htm
quantum_technologies.htm
quantum_theory.htm
quantum_wires.htm

QUANTUM_COMPUTER

graph4quantum_1.htm
graph4quantum_2.htm
graph4quantum_3.htm
graph4quantum_4.htm
graph4quantum_5.htm
graph4quantum_6.htm
graph4quantum_7.htm
graph4quantum_chimera.htm
graph4quantum_trees.htm
quantum_algorithms.htm
quantum_chip.htm
quantum_circuits.htm
quantum_computation.htm
quantum_computer.htm
quantum_computing.htm
quantum_gates.htm
quantum_general.htm
quantum_logic.htm
quantum_network.htm
quantum_processor.htm
quantum_programming.htm
quantum_qubits.htm
quantum_register.htm
quantum_researchers.htm
quantum_switching.htm

quantum_Turing_machine.htm

WIDeR reports and others
Apart from quantum circuits, I will also plan some time for others, and apart from the WIDeR reports, see here, I may also prepare for similar reports in specific areas such as graphene field effect transistors and all other IC technologies, depending on my time availability.

More Info

Check for the document here for my latest study scale.
  • 0resources.htm
  • Designers.htm
  • EDADevelopers.htm
  • EDAPortals.htm
  • Foundries.htm
  • Others.htm
  • VLSIEDAResources.htm
  • WebSources.htm
  • vlsi_snapshot.txt
  • vlsi_snapshot.htm.html


VLSI Technology

VLSI is the most important technology of the world today and tomorrow, and this is the reason I have chosen it as my research focus in retation with math, particularly graph theory.

Nowadays CMOS based VLSI technology has reached its limits, therefore I will no more follow the silicon based IC technology, but the upcoming new promising computation circuits with radically new physics and chemistry and even biological fundamentals. But at the moment there is no sight of breakthrough. Just follow me to find out where this great leap will come true.

Before VLSI was my final science focus, there were several other science branches where I have spent a decade on studying, incl. fluid dynamics, solar science and thermodynamics.

IC Studies

>>> chiptech

Attention!!!

Directory Structure and File Names of the Computer Chip Technologies, particularly the next generations of IC technologies

If you have problems in display, then open the PDF file instead.

chiptech_basic.htm

chiptech_other.htm

chiptech_special.htm

chiptech_special_reconfigurable_ref.htm

>>> design

  • design.htm
  • 00contents.htm
  • 00eda.htm
  • 00flow.htm
  • 00methodologies.htm
  • 1specifications.htm
  • 2architectural.htm
  • 3functional.htm
  • 4logic.htm
  • 5circuit.htm
  • 6physical.htm
  • 7simulation.htm
  • 8verification.htm
  • misc.htm

>>> physical design

  • floorplanning .htm
  • partitioning.htm
  • placement.htm
  • routing.htm
  • routing_detailed.htm
  • routing_detailed_channel_routing.htm
  • routing_detailed_switchbox.htm
  • routing_global.htm
  • timing.htm

>>> routing_channel

  • 2layers_channel_routing.htm
  • dogleg_channel_routing.htm
  • left_edge_channel_routing.htm
  • manhattan_channel_routing.htm
  • over_the_cell_channel_routing.htm
  • topological_routing.htm
  • virtual_channel_router.htm
  • yoshimurakuh_channel_routing.htm

>>> special_chips

  • 3dvlsi.htm
  • 3dvlsi_literature_a2g.htm
  • 3dvlsi_literature_h2n.htm
  • 3dvlsi_literature_o2z.htm
  • asic.htm
  • fpga.htm
  • integrated_optics.htm

More info pls refer to this complete document below:

ICStudies.pdf

Other Researches / List of My Writings:

During the last years since 2003 I have written hundreds or even thousands of academic, business and commentary notes in the forms of papers, presentation slides, reports, booklets and books in the areas such as solar physics, thermodynamics, fluid dynamics, IT (incl cryptography), VLSI chip design and mathematics, incl math for VLSI design, among them are selected about 200+ pieces of quite comprehensive and indepth review and research as listed below, amounting to more than 40 000 pages (200 pages each on average) of essays, and some of them can be published after a little finetuning. And again, this 200+ papers, books and so alike were based on thousands of records, notes and reports produced during my preparations over the 2003-2015 period alone. The exact number is not known, a preliminary statistics indicates it at the range of 3000 to 3500.

See the reference for details:

WhatsWrittenSince2003.pdf
?

Supporting Document List

The above mentioned writing is based on yet thousands more drafts I have prepared since 2003, see below for a glimpse of my draft document lists:

Document listing

2017-02-11


Special Technologies

Chip Technologies - Special Systems

Special chip types such as ASIC, FPGA, NOC, SOC, ASSP, DSP, 3D chips ect

3D VLSI - 3 Dimensional VLSIs

Check for more details as follows:

3d VLSI design

3d VLSI literature 1

3d VLSI literature 2

3d VLSI literature 3

AMS - Analog/Mixed-Signal

GIELEN, GEORGES G. E. AND RUTENBAR, ROB A: Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits, PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000, p28

許志賢 Mixed-Signal IC Design Kit Training Manual Dec 2003, p157

AsAP - Asynchronous Array of Simple Processors - 2006

Baas, Bevan et al: Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors p31 ..........ok

Spars?, Jens: Asynchronous Circuit Design, A Tutorial, 2006 p182.

WILLINGHAM, David John: ASYNCHROBATIC LOGIC FOR LOW-POWER VLSI DESIGN, PhD thesis, March 2010, p264

ASIC - Application Specific IC

EM ASIC

T3 ASIC

3D ASIC

Click to learn more ...

Batten, Christopher: ECE 5745 Complex Digital ASIC Design Topic 13 Physical Design Automation Algorithms p55, March 2013 .

Batten, Christopher: ECE 5950 Complex Digital ASIC Design Topic 8: CAD Algorithms – Placement and Routing p56 May 2012 .

Kommuru, Hima Bindu: ASIC Design Flow Tutorial Using Synopsys Tools p130, Oct 2013 ..................... 6

Mehrotra, Alok et al: Design Flow and Methodology for 50M gate ASIC, ....Nov 2002 .

ASSP - Application Specific Standard Product

CMP - Chip Multi Processors

Also Known As:

  • Multi-core processors
  • multi-core microprocessors
  • Single chip multiprocessors
  • On-chip multiprocessors

Burton, Trevor: SYSC5603 Paper Analysis: Multiprocessors for DSP p12 February 6, 2006

Chip Multiprocessors (CMP) Exploiting Parallelism April 2005 p25

Kumar, Rakesh et al: Heterogeneous Chip Multiprocessors p7

Olukotun, Kunle et al: Chip Multiprocessor Architecture - Techniques to Improve Throughput and Latency 2003 p24.

Torrellas, Josep: Chip Multiprocessors 2008 p17.

Vachharajani, Neil et al: Chip Multi-Processor Scalability for Single-Threaded Applications Oct 2005 p10

Configurable Processors late - 1990s
Configurable processors

post- RISC, configurable processors

Data Path

Askar, Serkan and Ciesielski, Maciej: ANALYTICAL APPROACH TO CUSTOM DATAPATH SYNTHESIS 2000, p44.ppt

Deep Submicron Technologies

Design of deep submicron (DSM) Scale

?

Design of deep submicron (DSM) Scale

A flow consisting of logic synthesis followed by place-and-route cannot work with deep submicron (DSM). At 0.18μm and beyond, interconnect becomes a dominant factor and breaks the dichotomy between the logical and physical domains. First, we can no longer neglect the impact of the interconnect on timing because interconnect dominates gate delays. Second, increasing design complexity makes managing congestion more challenging. Third, finer geometry, higher clock frequency, and lower voltage produce signal integrity problems. Logical and physical aspects are tied together and can no longer be looked at separately: there is a need for design tools and design flows that enable the simultaneous optimization of the logical and physical aspects of a design. ?

Routing in deep sub-micron design

– Thin wire
? Large interconnect delay
? delay μ (wire length)2
--> Al --> Cu
– H > W
? Delay due to larger edge (horizontal) capacitance
? Cross-talk with neighboring wires
--> Permutation of signal wires or Interleaving with power and ground wires

DSP - Digital Signal Processor

digital signal-processing chips

digital signal-processors

DSP Processors

Programmable Digital Signal Processor (PDSP)

media processors

Multimedia PDSPs

Kittitornkun, Surin and Hu, Yu Hen: Programmable Digital Signal Processor (PDSP): A Survey, 8/25/03 p39

Keutzer, Kurt: Lecture 9 Digital Signal Processors Applications and Architectures p61 February 2000

FPGA - Field Programmable Gate Array - 1990s

Click to learn more ...

FPGA ASIC

Floating Point Unit (FPU) - Integrated FPUs, Add-on FPUs

GPU - Graphics Processing Unit
CUDA - Compute Unified Device Architecture

Trefftz, Christian et al: CUDA Introduction 2008 p71..

Integrated Optics – Silicon Photonics
Click to learn more ...

Lab-on-a-Chip

MCM - Multichip Module - 1970s

MultiChip Modules (MCMs)

Chattopadhyay, Subhomoy et al: An overview of placement and routing algorithm for multichip modules, 1995, p43 .

Frisbee, Charles N.: An Overview of Placement and Routing Algorithms for PCB VLSI and MCM Designs with a Proposal for a New MCM Routing Algorithm, May 1996, p51.

Lan, Sanko et al: Placement and Routing For A Field Programmable MultiChip Module p6

Sherwani Physical design automation of MCMS, 1992, p24.

MCP - Multi-Core Processors

Schurman, Kyle: AMD Multi-Core Processors February 2006 p4 .

Schauer, Bryan: Multicore Processors – A Necessity 2008 p14

MCU - Micro Controller Unit - 1971

Microcontrollers

MCU环境

microcontroller unit (MCU)

MPSoC - Multiprocessor System-on-Chip

multiprocessor system-on-chip (MPSoC)

Wolf, Wayne et al: Multiprocessor System-on-Chip (MPSoC) Technology p13 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 p13

MPU - High-Volume Custom Microprocessor Unit

microprocessor unit, also known as a central processing unit

multi-core processing unit

memory protection unit

Nanometer IC

nanometer silicon lithography

Basic routing algorithms
– Global routing
– Detailed routing

Scalable routing paradigm
– Hierarchical routing
– Multilevel routing

Nanometer Routing

Cong, Jason: Advanced Routing Techniques for Nanometer IC Designs ICCAD 2006 ..p96

Vishvanathan, V. et al: Design Technology Challenges in the Sub-100 Nanometer Era p5 Periodical of the VLSI Society of India – VSI VISION Vol 1, Issue 1, 2005

NOC - Network on Chip May - 2007

Network on Chip Routing

Deterministic algorithms

Oblivious algorithms

Adaptive algorithms

Minimal algorithms

Dimension-Order Routing in Tori and Meshes

Network-on-Chip (NoC) Channel Routers

Asynchronous Bypass Channel Routers
for Network-on-Chip (NoC) designs

Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. Typically, these systems require fully balanced clock distribution trees to enable synchronous communication between all nodes on-chip, resulting in higher power consumption. One approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) mesochronous clocking scheme. NoCs implemented with a GALS clocking scheme, however, tend to have high latencies as packets must be synchronized at every hop between source and destination.

The novel router microarchitecture for GALS NoCs features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. The new network topology also leverages the advantages of the bypass channel offered by the router design. Experiments show that the design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 11%.

Network on Chip

?

Networks-On-Chip (NoCs)

Multiple Network-On-Chip Design?

Nanoscale silicon photonic integrated circuitry?

Photonic network-on-chip architecture

Terminology

for Network-on-Chip (NoC) designs

traditional shared-bus designs

on-chip communications

fully balanced clock distribution trees

globally-asynchronous, locally-synchronous (GALS) mesochronous clocking scheme

high latencies

Asynchronous Bypass Channels (ABCs)

on-chip networks.

macro-scale multi-hop networks

Literature

Ahmed, Akram Ben: LA-XYZ Low Latency High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture p8

de Faria Corrêa, Edgard: Fitting the Router Characteristics in NoCs to Meet QoS Requirements p6

Feero, Brett Stanley: Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation p14

Jain, Tushar N. K.et al: Asynchronous Bypass Channel Routers, Sept. 7, 2009

Li, Xi: Survey of Wireless Network-on-Chip Systems p34

Lu, Zhonghai: Embedded Interconnet NoC Topology, Routing p38 - 2/18/2014.

Morris, Randy et al: Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance 2012 IEEE/ACM 45th Annual International Symposium on Microarchitecture p12

Sander, Ingo: Network-on-Chip Routing, 2007

Vangal, Sriram R.: Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures p69

Xue, Licheng et al: Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip, 2011 EDAA p6

Yang, Bo: Parameter-Optimized Simulated Annealing for Application Mapping on Networks-on-Chip p15

OCN - On-Chip Networks

Kavaldjiev, Nikolay , Smit, Gerard J. M. , and Jansen, Pierre G.: A Virtual Channel Router for On-chip Networks. July 9, 2004 .........p5

Kim, John: Low-Cost Router Microarchitecture for On-Chip Networks p12, MICRO’09, December 12–16, 2009, New York, NY, USA.

Mullins, Robert , West, Andrew and Moore, Simon: Low-Latency Virtual-Channel Routers for On-Chip Networks.

PLD - Programmable Logic Device (PLD, PLA, PAL, ...)

Programmable Logic Device (PLD, PLA, PAL, ...)

?

Programmable logic

Programmable logic device (PLD, PLA, PAL, ...)

Complex PLD (CPLD)

?

Programmable Logic Devices (PLDs)

Complex Programmable Logic Devices (CPLDs)

Process On-Chip

VanAckern, Gary: Design Guide for CMOS Process On-Chip 3D Inductors using Thru-Wafer Vias May 2011 p143.

PSoC - Programmable System-on-Chip - 2002

专用 PSoC（可编程片上系统）

SiP - System-in-Package - 2005

System-in-Package (SiP) technology

?
SiP

System-on-Package (SoP) or System-in-Package (SiP)

SIPs - Silicon Intellectual Properties

SOC - System-on-Chip

SOC Design

?
?

SoC, SoPC

SOC总线架构?

SOC芯片的参考设计，从规划到设计到量产验证的过程

SoC芯片完整设计流程，从规划到设计到量产验证；

SoC芯片的总线架构/memory架构/时钟树/电源域的设计与仿真

SoC芯片的总线架构/memory架构/时钟树/电源域设计与仿真

Carloni COPING WITH LATENCY IN SOC DESIGN p12

Gerlach, Joachim: System-on-Chip Design with SystemC p98

Kaeslin, H: . SoC Encounter for Designers II p46

Martin, Alain J: . Asynchronous Techniques for System-on-Chip Design, Vol. 0018-9219 IEEE 94, No. 6, June 2006 Proceedings of the IEEE p1089-1112 .................

Nagel, Jean-Luc: Algorithms and VLSI Architectures for Low-Power Mobile Face Verification, 2006 p288 ......................

Pande, Partha: EE 587 SoC Design & Test p41

SOI - Silicon-on-Insulator - 1998
Koob, John C. et al: Design of a 3-D Fully Depleted SOI Computational RAM MARCH 2005 p12

SOP - System-on-Package

Minz, Jacob R. and Lim, Sung Kyu: A Global Router for System-on-Package Targeting Layer and Crosstalk Minimization 2004 p4

Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package 2007 p8

SOPC - System-on-a-Programmable Chip - 2002

Dimetr System on a Programmable Chip Design p8

Hall, Tyson S. and Hamblen, James O. : System-on-a-Programmable-Chip Development Platforms in the Classroom NOVEMBER 2004 p6

SOS Silicon on Sapphire

USIC - User-specific integrated circuit

A Comprehensive Listing

special
├<000fpga>
│ ├Abbas PRINCE IP-core on Field Programmable Gate Arrays (FPGA) p9.pdf
│ ├ALAOUI ISMAILI Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA p8.pdf
│ ├Aloisio High-Resolution Time-to-Digital Converter in Field Programmable Gate Array p5.pdf
│ ├Altera FPGA Run-Time Reconfiguration Two Approaches p6.pdf
│ ├Altera FPGAs Provide Reconfigurable DSP Solutions p6.pdf
│ ├Banerjee Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198.pdf
│ ├BANERJEE FPGA Placement using Space Filling Curves Theory Meets Practice p21.pdf
│ ├Bani-Hani High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard DES p12.pdf
│ ├BUCUR PARTITIONING COMBINATIONAL CIRCUITS FOR K-LUT BASED FPGA MAPPING p10.pdf
│ ├Chakrabarti Crypto Hardware Design for Embedded Applications p56.pdf
│ ├Chen FPGA Design Automation A Survey p137.pdf
│ ├Chen FPGA design automation a survey p151.pdf
│ ├Chodowiec Very Compact FPGA Implementation of the AES Algorithm p15.pdf
│ ├CHRISTIANSEN FPGA p19.pdf
│ ├Coman Cryptographic Applications using FPGA Technology p7.pdf
│ ├Coyne A FIELD PROGRAMMABLE GATE ARRAY CO-PROCESSOR FOR THE BASIC LOCAL ALIGNMENT SEARCH TOOL p4.pdf
│ ├<doc_fpga>
│ │ └fpga.docx
│ ├Dutt Efficient Incremental Rerouting for Fault Reconfiguration in Field Programmable Gate Arrays p4.pdf
│ ├Gaikwad Active Noise Control Using Field Programmable Gate Arrays p7.pdf
│ ├Ghosal A Compact FPGA Implementation of Triple-DES Encryption System with IP Core Generation and On-Chip Verification p6.pdf
│ ├Ghosal Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA p5.pdf
│ ├Good AES on FPGA from the Fastest to the Smallest p10.pdf
│ ├Gore FPGA Implementation of Area Optimized AES for Image EncryptionDecryption Process p4.pdf
│ ├Goslin A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance p11.pdf
│ ├Gupta Successfully Designing FPGA-Based Systems p7.pdf
│ ├Hauck Reconfigurable Computing The Theory and Practice of FPGA-Based Computation p945.pdf
│ ├Hauck The Roles of FPGAs in Reprogrammable Systems p37.pdf
│ ├Heinrich Comparison of FPGA-based Implementation Alternatives p8.pdf
│ ├Hussain BASICS OF FIELD PROGRAMMABLE GATE ARRAYS p11.pdf
│ ├Inoue Universal Test Complexity of Field-Programmable Gate Arrays p9.pdf
│ ├Jang Energy- and Time-Efficient Matrix Multiplication on FPGAs p15.pdf
│ ├J?rvinen Elliptic Curve Cryptography on FPGAs How Fast Can We Go with a Single Chip p10.pdf
│ ├J?rvinen Elliptic curve cryptography on FPGAs How fast can we go with a single chip p87.pdf
│ ├Karthik REMOTE FIELD-PROGRAMMABLE GATE ARRAY FPGA LAB p4.pdf
│ ├Kean Secure Configuration of Field Programmable Gate Arrays p10.pdf
│ ├Koh MODULE GRAPH MERGING AND PLACEMENT TO REDUCE RECONFIGURATION OVERHEADS IN PAGED FPGA DEVICES p6.pdf
│ ├Kohli FPGA Implementation of Cryptographic Algorithms using Multi-Encryption Technique p9.pdf
│ ├Kuon FPGA Architecture Survey and Challenges p119.pdf
│ ├Lamoureux An Overview of Low-Power Techniques for Field-Programmable Gate Arrays p8.pdf
│ ├Lamoureux Modeling and Reduction of Dynamic Power in Field-Programmable Gate Arrays p148.pdf
│ ├Leong A Microcoded Elliptic Curve Processor Using FPGA Technology p10.pdf
│ ├Levin FPGA-based Reconfigurable Computer Systems for digital image processing p6.pdf
│ ├Li Power Modeling and Characteristics of Field Programmable Gate Arrays p13.pdf
│ ├Lin A Low-Power Field-Programmable Gate Array Routing Fabric p14.pdf
│ ├Maache A Prototype Parallel Multi-FPGA Accelerator for SPICE CMOS Model Evaluation p207.pdf
│ ├MARVASTI AN ANALYSIS OF NOCS IN FPGAS p232.pdf
│ ├MASUD FPGA ROUTING STRUCTURES A NOVEL SWITCH BLOCK AND DEPOPULATED INTERCONNECT MATRIX ARCHITECTURES p80.pdf
│ ├Maxfield The Design Warriors Guide to FPGAs p560.pdf
│ ├Mehta Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs p13.pdf
│ ├MENON Field Programmable Gate Arrays in safety related instrumentation and control applications p68.pdf
│ ├Meyer-Baese Digital Signal Processing with FPGAs 3rd Edition p795.pdf
│ ├MILLER Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation p22.pdf
│ ├Montone Floorplacement for Partial Reconfigurable FPGA-Based Systems p13.pdf
│ ├Niu Rapid FPGA-based Delay Estimation for the HardwareSoftware Partitioning p8.pdf
│ ├OMONDI FPGA Implementations of Neural Networks p363.pdf
│ ├PANDYA A HANDEL-C IMPLEMENTATION OF THE BACK-PROPAGATION ALGORITHM ON FIELD PROGRAMMABLE GATE ARRAYS p218.pdf
│ ├Panella A Design Workflow for Dynamically Reconfigurable Multi-FPGA Systems p7.pdf
│ ├Peel Occam on Field-Programmable Gate Arrays - Optimising for Performance p13.pdf
│ ├Pham Area and Power optimisation for AES encryption module implementation on FPGA p6.pdf
│ ├POON A Detailed Power Model for Field Programmable Gate Arrays p28.pdf
│ ├Rose Flexibility of Interconnection Structures for Field-Programmable Gate Arrays p6.pdf
│ ├Rouvroy Compact and Effficient EncryptionDecryption Module for FPGA Implementation of the AES Rijndael p8.pdf
│ ├Salem Field Programmable Gate Array-Based System-on-Chip for Real-Time Power Process Control p13.pdf
│ ├Salim FPGA Implementation of Hiding Information using Cryptography p7.pdf
│ ├SANGIOVANNI-VINCENTELLI Synthesis Methods for Field Programmable Gate Arrays p27.pdf
│ ├Schelle Exploring FPGA Network on Chip Implementations Across Various Application and Network Loads p6.pdf
│ ├SCHMIT Pipeline Reconfigurable FPGAs p18.pdf
│ ├Shivaraj Design and FPGA implementation of TDEA using Light Weight Processor based multiprocessing system p4.pdf
│ ├Shnidman On-Line Fault Detection for Bus-Based Field Programmable Gate Arrays p11.pdf
│ ├Shylashree FPGA IMPLEMENTATIONS OF ADVANCED ENCRYPTION STANDARD A SURVEY p21.pdf
│ ├Srinivas Implementation of FPGA in the design of Embedded Systems p78.pdf
│ ├Stroop Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators p113.pdf
│ ├strouce Field Programmable Gate Arrays p20.pdf
│ ├Thamrin A Secure Field Programmable Gate Array Based System-on-Chip for Telemedicine Application p5.pdf
│ ├Thanh Protecting FPGA-based Partially Reconfigurable Embedded Systems and IP Cores from Remote Update p7.pdf
│ ├Trivedi FIELD PROGRAMMABLE GATE ARRAY BASED CONTROL SIGNAL GENERATOR FOR PULSED RADAR p10.pdf
│ ├Varnavas The Use of Field Programmable Gate Arrays (FPGA) in Small Satellite Communication Systems p4.pdf
│ ├VERMA VLSI-cell placement technique for Architecture of Field Programmable Gate Array (FPGA) design p9.pdf
│ ├Viele APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL p185.pdf
│ ├Wanderley Security FPGA Analysis p41.pdf
│ ├Watteyne Les FPGA pour des applications à très hautes performances CETIC groupe de discussion sur la technologie FPGA p13.pdf
│ ├Wilhelmsson Field Programmable Gate Arrays and Reconfigurable Computing in Automatic Control p102.pdf
│ ├Wilton The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays p10.pdf
│ ├Wright FIELD PROGRAMMABLE GATE ARRAY (FPGA) BASED SOFTWARE DEFINED RADIO (SDR) DESIGN p127.pdf
│ ├Wu Introduction to FPGA p37.pdf
│ ├Ye Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits p244.pdf
│ ├Ye Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits p12.pdf
│ ├Zain-ul-Abdin A Study of Design Efficiency with a High-Level Language for FPGAs p8.pdf
│ ├Zaretsky DESIGN AND EVALUATION OF MATLAB FUNCTIONS ON FIELD PROGRAMMABLE GATE ARRAYS FPGAS p238.pdf
│ ├Zhang A review of high-level synthesis for dynamically reconfigurable FPGAs p13.pdf
│ └Zhang Fast Marching Method Seismic Traveltimes with Reconfigurable Field Programmable Gate Arrays p9.pdf
├<000reconfigurable>
│ ├Abnous Evaluation of a Low-Power Reconfigurable DSP Architecture p6.pdf
│ ├Aggarwal Bridging Parallel and Reconfigurable Computing with Multilevel PGAS and SHMEM p8.pdf
│ ├Ahmad Efficient Reconfigurable Architectures for 3-D Medical Image Compression p207.pdf
│ ├Akoglu Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing p8.PDF
│ ├Al-Wattar Efficient Scheduling,Mapping and Resource Prediction for Dynamic Run time Operating Systems p272.pdf
│ ├Alsolaim A DYNAMICALLY RECONFIGURABLE SYSTEM-ON-A-CHIP ARCHITECTURE FOR FUTURE MOBILE DIGITAL SIGNAL PROCESSING p4.pdf
│ ├Alsolaim DYNAMICALLY RECONFIGURABLE ARCHITECTURE FOR THIRD GENERATION MOBILE SYSTEMS p327.pdf
│ ├Amarnath A Self-Configurable Architecture on an Irregular Reconfigurable Fabric p93.pdf
│ ├ANANDAN VLSI Implementation of Reconfigurable Low Power Fir Filter Architecture p9.pdf
│ ├Andrade Software Synthesis from Dataflow Models for G and LabVIEW p5.pdf
│ ├Andreas Mapping Framework for Heterogeneous Reconfigurable Architectures p127.pdf
│ ├Attia CyGraph A Reconfigurable Architecture for Parallel Breadth-First Search p8.pdf
│ ├Azarian Reconfigurable Computing Architecture Survey and introduction p5.pdf
│ ├Babst Practical Reconfigurable Computing p42.pdf
│ ├Beadle Software-Based Reconfigurable Computing Platform (AppSTARTM) for Multi-Mission Payloads in Spaceborne and Near-Space Vehicles p7.pdf
│ ├Becker Configurable Systems-on-Chip Commercial and Academic Approaches p4.pdf
│ ├Becker Configware and morphware going mainstream p16.pdf
│ ├Beckett Towards a Reconfigurable Nanocomputer Platform p8.pdf
│ ├Benkrid High Performance Reconfigurable Computing From Applications to Hardware p8.pdf
│ ├Bhatia Reconfigurable Computing p185.pdf
│ ├Bhatia Reconfigurable Computing p85.pdf
│ ├Bhattacharyya Dynamic Dataflow Graphs p40.pdf
│ ├Bhattacharyya Software Synthesis from Dataflow Graphs p49.pdf
│ ├Bhattacharyya2001 Software Synthesis Trade-offs in Dataflow Representations of DSP Applications p26.pdf
│ ├Bittner Colt An Experiment in Wormhole Run-Time Reconfiguration p8.pdf
│ ├Bobda Synthesis of Dataflow Graphs for Reconfigurable Systems using Temporal Partitioning and Temporal Placement p90.pdf
│ ├Bollman SCALABLE COMPUTING Practice and Experience p127.pdf
│ ├Bondalapati Reconfigurable Computing Systems p12.pdf
│ ├Borgatti A 1GOPS Reconfigurable Signal Processing IC with Embedded FPGA and 3-Port 1.2GBs Flash Memory Subsystem p10.pdf
│ ├Boschetti A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications p6.PDF
│ ├Boysen A development environment for configurable computing p10.pdf
│ ├Brebner Reconfigurable Computing for High Performance Networking Applications p30.pdf
│ ├Brenner Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures p72.pdf
│ ├Brodie Dynamic Reconfigurable Computing p8.pdf
│ ├Burleson DYNAMICALLY PARAMETERIZED ALGORITHMS AND ARCHITECTURES TO EXPLOIT SIGNAL VARIATIONS FOR IMPROVED PERFORMANCE AND REDUCED POWER p5.pdf
│ ├Campi Re-Configurable Solutions for the high-volume ASSP Market p56.pdf
│ ├Campi Run-Time Reconfigurable Processors p47.pdf
│ ├Cardoso ARC2005 INTERNATIONAL WORKSHOP ON APPLIED RECONFIGURABLE COMPUTING 2005 p190.pdf
│ ├Carroll Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency p11.pdf
│ ├Chen A Reconfigurable Architecture for Load-Balanced Rendering p11.pdf
│ ├CHEN Graph Minor Approach for Application Mapping on CGRAs p22.pdf
│ ├Cheng Reconfigurable Computing p16.pdf
│ ├Cheung Reconfigurable Elliptic Curve Cryptosystems on a Chip p7.pdf
│ ├CHIU The Multi-context Reconfigurable Processing Unit for Fine-grain Computing p15.pdf
│ ├Cho Diastolic Arrays Throughput-Driven Reconfigurable Computing p8.pdf
│ ├Ciricescu The Reconfigurable Streaming Vector Processor (RSVPTM) p10.pdf
│ ├Compton An Introduction to Reconfigurable Computing p9.pdf
│ ├Compton Programming Architectures For Run-Time Reconfigurable Systems p34.pdf
│ ├COMPTON Reconfigurable Computing A Survey of Systems and Software p40.pdf
│ ├COMPTON1999 Reconfigurable Computing A Survey of Systems and Software p39.pdf
│ ├Coughlan Introduction to Programmable Logic p28.ppt
│ ├Cre? The CREC Reconfigurable Computer p15.pdf
│ ├CURRERI Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing p19.pdf
│ ├David DART A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints p8.PDF
│ ├Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166.pdf
│ ├DeHon Reconfigurable Architectures for General-Purpose Computing p368.pdf
│ ├DeHon Reconfigurable Computing What Why and Implications for Design Automation p6.pdf
│ ├Delgado-Frias A MEDIUM-GRAIN RECONFIGURABLE CELL ARRAY FOR DSP p6.pdf
│ ├Densmore Platform Based Reconfigurable Architecture Exploration via Boolean Constraints p 81.pdf
│ ├Densmore Reconfigurable Architectures Overview and Commercial Examples p57.pdf
│ ├Designing Debugging and Deploying Configurable Computing Machin.pdf
│ ├Diessel Operating Systems Support for Dynamically Reconfigurable Architectures p12.pdf
│ ├Dittmann Exploration partitioning and simulation of reconfigurable systems p8.pdf
│ ├Dittmann Methods to Exploit Reconfigurable Fabrics Making Reconfigurable Systems Mature p211.pdf
│ ├DORDOPULO Reconfigurable computer systems for digital image processing p6.pdf
│ ├Drutarovsky CUSTOM FPGA CRYPTOGRAPHIC BLOCKS FOR RECONFIGURABLE EMBEDDED NIOS PROCESSOR p7.pdf
│ ├Duarte Reconfigurable Computing A Survey of Architectures and Synthesis Tools p45.pdf
│ ├Dubach Java Byte Code Synthesis for Reconfigurable Computing Platforms p71.pdf
│ ├Eguro Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development p10.pdf
│ ├Engel Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications p8.pdf
│ ├Enzler The Current Status of Reconfigurable Computing p22.pdf
│ ├Ernst A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF p18.pdf
│ ├Ersfolk Scheduling Dynamic Dataflow Graphs with Model Checking p225.pdf
│ ├ESHAGHIAN-WILNER The Systolic Reconfigurable Mesh p14.pdf
│ ├Filho Description and Specialization of Coarse-grained Reconfigurable Architectures p182.pdf
│ ├Fukushi Self-Reconfigurable Mesh Array System on FPGA p9.pdf
│ ├Galuzzi Graph Theory and Application Specific Processors p7.pdf
│ ├Ghazawi Parallel Programming of High-Performance Reconfigurable Computing Systems with Unified Parallel C p7.pdf
│ ├Giani Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity p7.pdf
│ ├Goldstein Reconfigurable Computing and Electronic Nanotechnology p12.pdf
│ ├Gomez-Prado Optimizing Data Flow Graphs to Minimize Hardware Implementation p6.pdf
│ ├Gong Synthesizing Sequential Programs onto Reconfigurable Computing Systems p237.pdf
│ ├Gotz Runtime reconfigurable rtos for reconfigurable system on chip p180.pdf
│ ├Govindarajan Algorithm for design space exploration p216.pdf
│ ├Govindarajan Algorithm for design space explorationUN p216.pdf
│ ├Gray Object-Oriented Reconfigurable Processing for Wireless Networks p5.pdf
│ ├Grudnitsky Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures p6.PDF
│ ├Guccione Reconfigurable Computing p22.pdf
│ ├Guneysu CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES p213 .pdf
│ ├Guo Programmability and Efficiency in Reconfigurable Computer Systems p7.pdf
│ ├Halstead Compiling irregular applications for reconfigurable systems p11.pdf
│ ├Hannig REGULAR MAPPING FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURES p4.pdf
│ ├Harb A Reconfigurable Platform Architecture for an Automotive Multiple-Target Tracking System p5.pdf
│ ├Hauck The Future of Reconfigurable Systems p7.PDF
│ ├Havinga Energy Management for Dynamically Reconfigurable Heterogeneous Mobile Systems p13.pdf
│ ├Hendriks High Level Synthesis Performance Analysis and Code Optimization p105.pdf
│ ├Heyne A PURE CORDIC BASED FFT FOR RECONFIGURABLE DIGITAL SIGNAL PROCESSING p4.pdf
│ ├Hsu A 110 GOPSW 16-bit Multiplier and Reconfigurable PLA Loop in 90-nm CMOS p9.pdf
│ ├HSU Hybrid LUT and SOP Reconfigurable Architecture p20.pdf
│ ├Hudson Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines p97.pdf
│ ├Huynh An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization p23.pdf
│ ├Ihrig Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric p30.pdf
│ ├Iqbal Performance Oriented Design Perspectives of Run-Time Reconfigurable Computing Systems p10.pdf
│ ├Jijina Low Power Architecture for Reconfigurable Fir Filter for SDR p5.pdf
│ ├Jose Compiling Packet Programs to Reconfigurable Switches p14.pdf
│ ├Kadam An Overview of Reconfigurable Hardware for Efficient Implementation of DSP p10.pdf
│ ├Karkooti Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding p7.pdf
│ ├Kastner Synthesis Techniques and Optimizations for Reconfigurable Systems p152.pdf
│ ├Kastrup Seeking (the right) Problems for the Solutions of Reconfigurable Computing p6.pdf
│ ├Kindratenko High-Performance Reconfigurable Computing Application Programming in C p33.pdf
│ ├Kirasic Reconfigurable Processor Architectures Varieties and Representations p6.pdf
│ ├Koch Architectures and Tools for Heterogeneous Reconfigurable Systems p2.pdf
│ ├Koch Architectures Methods and Tools for Distributed Run-time Reconfigurable FPGA-based Systems p295.pdf
│ ├KOONAR A RECONFIGURABLE HARDWARE IMPLEMENTATION OF GENETIC ALGORITHMS FOR VLSI CAD DESIGN p173.pdf
│ ├Koutroumpezis Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-grain Implementations p10.pdf
│ ├Krishnamurthy A Survey of Next-Generation Reconfigurable Architectures for Embedded Computing p32.pdf
│ ├Kumar An Automated High-level Design Framework for Partially Reconfigurable FPGAs p6.pdf
│ ├Lagger SELF-RECONFIGURABLE PERVASIVE PLATFORM FOR CRYPTOGRAPHIC APPLICATION p4.pdf
│ ├Lechner The Java Environment for Reconfigurable Computing p10.pdf
│ ├Lehn Framework for architecture-independent run-time reconfigurable applications p11.pdf
│ ├Lenart Design of Reconfigurable Hardware Architectures for Real-time Applications Modeling and Implementation p195.pdf
│ ├Liang SmartCell An Energy Efficient Reconfigurable Architecture for Stream Processing p130.pdf
│ ├Lodi A VLIW Processor With Reconfigurable Instruction Set for Embedded Applications p11.pdf
│ ├Lodi Reconfigurable Architectures p50.pdf
│ ├Louri An Optical Data -Flow Computer p12.pdf
│ ├Maestre A Framework for Reconfigurable Computing Task Scheduling and Context Management p16.pdf
│ ├MANOLOPOULOS Reconfigurable Fast Fourier Transform Architecture for Orthogonal Frequency Division Multiplexing Systems p6.pdf
│ ├Markovskiy Quasi-Static Scheduling for SCORE p115.pdf
│ ├marlene A Low-Energy Heterogeneous Reconfigurable DSP IC p10.pdf
│ ├Masselos SYSTEM LEVEL ARCHITECTURE EXPLORATION FOR RECONFIGURABLE SYSTEMS ON CHIP p6.pdf
│ ├McMahon High Performance Reconfigurable Computing for Science and Engineering Applications p135.pdf
│ ├Mehra Reconfigurable Cost Effective Design of Digital up Converter for Mobile Communication p9.pdf
│ ├Mehra Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization p7.pdf
│ ├MILLER Embedding-Based Placement of Processing element Networks on FPGAs for Physical Model Simulation p17.pptx
│ ├Miramond Design Space Exploration for Dynamically Reconfigurable Architectures p7.pdf
│ ├Mucci Software tools for embedded reconfigurable peocessors p243.pdf
│ ├Myjak A TWO-LEVEL RECONFIGURABLE ARCHITECTURE FOR DIGITAL SIGNAL PROCESSING p7.pdf
│ ├Mykyta Reconfigurable Computing Case Studies p24.pdf
│ ├Najjar High-Level Language Abstraction for Reconfigurable Computing p7.pdf
│ ├Nane IP-XACT Extensions for Reconfigurable Computing p4.pdf
│ ├NICHOLS A RECONFIGURABLE COMPUTING ARCHITECTURE FOR IMPLEMENTING ARTIFICIAL NEURAL NETWORKS ON FPGA p235.pdf
│ ├Niu EXPLOITING RUN-TIME RECONFIGURATION IN STENCIL COMPUTATION p8.pdf
│ ├Noguera HWSW Codesign Techniques for Dynamically Reconfigurable Architectures p17.pdf
│ ├Noguera Research in Reconfigurable Computing An Industrial Perspective p35.pdf
│ ├Oh Dynamic Partial Reconfigurable FIR Filter Design p6.pdf
│ ├Olson Programming a Pipelined Image Processor p41.pdf
│ ├Ostadzadeh Parallelism Utilization in Embedded Reconfigurable Computing Systems A Survey of Recent Trends p11.pdf
│ ├PANDYA A HANDEL-C IMPLEMENTATION OF THE BACK-PROPAGATION ALGORITHM ON FIELD PROGRAMMABLE GATE ARRAYS p218.pdf
│ ├Parithy ADVANCED TOOLS IN RECONFIGURABLE COMPUTING p6.pdf
│ ├Park Modulo Graph Embedding Mapping Applications onto Coarse Grained Reconfigurable Architectures p11.pdf
│ ├Park Modulo Graph Embedding Mapping Applications onto CoarseGrained Reconfigurable Architectures p11.pdf
│ ├Paulino Generation of Reconfigurable Circuits from Machine Code p125.pdf
│ ├Pelkonen System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC p8.PDF
│ ├Petersen An assessment of the suitability of reconfigurable systems for digital signal processing p149.pdf
│ ├Pillement DART A Functional-Level Reconfigurable Architecture for High Energy Efficiency p13.pdf
│ ├Pillement DART A Functional-Level Reconfigurable Architecture for High Energy Efficiency p15.pdf
│ ├Poon An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications p9.pdf
│ ├Popescu More exotic processor approaches p16.pdf
│ ├Pottier AN INTEGRATED PLATFORM FOR HETEROGENEOUS RECONFIGURABLE COMPUTING p10.pdf
│ ├Purna Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers p12.pdf
│ ├Rabaey Reconfigurable Computing The Solution to Low Power Programmable DSP p10.pdf
│ ├Raffin Scheduling Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture p8.pdf
│ ├Rajagopal Reconfigurable stream processors for wireless base-stations p30.pdf
│ ├Reda EN2911X Reconfigurable Computing Topic 00 Introduction p20.pdf
│ ├Reda EN2911X Reconfigurable Computing Topic 03 Reconfigurable Computing Design Methodologies p93.pdf
│ ├Reiner Coarse Grained Reconfigurable Architectures p28.pdf
│ ├Rinker An Automated Process for Compiling Data flow Graphs into Reconfigurable Hardware p10.pdf
│ ├Rosado A Reconfigurable Digital Signal Processing System for Eddy Currents Non-Destructive Testing p6.pdf
│ ├Saidani Self-Reconfigurable Robots Topodynamic p5.pdf
│ ├Saleeba A self reconfiguring computer system p321.pdf
│ ├Sanchez Reconfigurable computing p48.pdf
│ ├Saqib A Compact and Efficient FPGA Implementation of DES Algorithm p20.ppt
│ ├Sarrigeorgidis Massively Parallel Wireless Reconfigurable Processor Architecture and Programming p8.PDF
│ ├SAY A RECONFIGURABLE COMPUTING PLATFORM FOR REAL TIME EMBEDDED APPLICATIONS p154.pdf
│ ├Say A reconfigurable computing platform for real time embedded applications p20.pdf
│ ├Schier RECONFIGURABLE IMAGE PROCESSING ARCHITECTURE WITH SIMULINK PROTOTYPING SUPPORT p4.pdf
│ ├Sghaier Efficient Implementations of WiMAX OFDM Functions on Reconfigurable Platforms p143.pdf
│ ├Shafer A Development Method for Reconfigurable Hardware Systems With Real-Time Wavelet Image Compression Application p8.pdf
│ ├Shoup Reconfigurable Systems New Tools and New Math p12.pdf
│ ├Sigdel System-Level Design Space Exploration of Reconfigurable Architectures p223.pdf
│ ├SILVA A Dynamic Dataflow Architecture using Partial Reconfigurable Hardware as an option for Multiple Cores p16.pdf
│ ├Silva Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System p13.pdf
│ ├Singh Partitioning and Mapping of Computation Structure on a Coarse-Grained Reconfigurable Architecture p121.pdf
│ ├Singh Reconfigurable Computing A review of the technology and its architecture p7.pdf
│ ├Sinha FIELD PROGRAMMABLE DSP ARRAYS A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFFICIENT REALIZATION OF DIGITAL SIGNAL PROCESSING FUNCTIONS p18.pdf
│ ├Skliarova Intelligent Systems Engineering with Reconfigurable Computing p10.pdf
│ ├Slade Reconfigurable Computing Application Frameworks p10.pdf
│ ├Sripornprasert The AES Encryption Circuit on a Reconfigurable Hardware p4.pdf
│ ├STALIN A STUDY ON LOW POWER RECONFIGURABLE FIR FILTERS WITH DYNAMIC CHANGE IN FILTER ORDER p8.pdf
│ ├Steinbach UML-BASED CO-DESIGN FOR RUN-TIME RECONFIGURABLE ARCHITECTURES p15.pdf
│ ├Stekelenburg Low Cost Fast Turnaround Reconfigurable Graph-Based Execution Units p5.pdf
│ ├Stitt Reconfigurable Computing A Plan for Post-Moore's Law Sustainability p17.pdf
│ ├STOJANOVIC An Overview of Selected Hybrid and Reconfigurable Architectures p25.pdf
│ ├Streichert Self-Adaptive Hardware Software Reconfigurable Networks p253.pdf
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│ ├Sutter Coarse-Grained Reconfigurable Array Architectures p39.pdf
│ ├Svensson Reconfigurable Architectures for Embedded Systems p183.pdf
│ ├Synplicity Reconfigurable System-on-a-Chip p12.pdf
│ ├TANIGUCHI Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model p20.pdf
│ ├Teich Reconfigurable Computing Systems p4.pdf
│ ├Templin DESIGN OF AN ADAPTABLE RUN-TIME RECONFIGURABLE SOFTWARE-DEFINED RADIO PROCESSING ARCHITECTURE p63.pdf
│ ├Thahir Compiling for Reconfigurable Computing p25.pdf
│ ├Tiwari Hardware Software Co-debugging for Reconfigurable Computing p81.pdf
│ ├VANCOURT Elements of High-Performance Reconfigurable Computing p45.pdf
│ ├Venkataramani A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture p10.pdf
│ ├Vorbach Reconfigurable Processor Architectures for Mobile Phones p6.PDF
│ ├Wang Loop Kernel Pipelining Mapping onto Coarse- Grained Reconfigurable Architecture for Data- Intensive Applications p9.pdf
│ ├WANKAR RECONFIGURABLE ARCHITECTURES AND ALGORITHMS A RESEARCH SURVEY p16.pdf
│ ├WANKAR2009 RECONFIGURABLE ARCHITECTURES AND ALGORITHMS A RESEARCH SURVEY p15.pdf
│ ├Ward Dynamically-Reconfigurable-Computing p6.pdf
│ ├Windh High-Level Language Tools for Reconfigurable Computing p19.pdf
│ ├Wu Reconfigurable Architectures from Physical Implementation to Dynamic Behaviour Modelling p136.pdf
│ ├YANG TISA Reconfigurable System for Template-Based Stream Computing p5.pdf
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│ ├ZHANG Auto-adaptive reconfigurable architecture for scalable multimedia applications p7.pdf
│ └ZhangXJ Module Allocation for Dynamically Reconfigurable Systems p9.pdf
├<ams>
├<analog>
│ └Allen CMOS Analog Circuit Design-1 p477.pdf
├<asynchronous>
│ ├Beerel Semi-Modularity and Self-Diagnostic Asynchronous Control Circuits p15.pdf
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│ └Benini NETWORKS ON CHIPS TECHNOLOGY AND TOOLS p404.pdf
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│ └Sharma A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices p59.pdf
└<soc>
└Wang SYSTEM-ON-CHIP TEST ARCHITECTURES NANOMETER DESIGN FOR TESTABILITY p893.pdf
2017-02-11


3D IC - 3 Dimensional ICs

three-dimensional structure

three-dimensional (3D) structure, such as fin-FET or DG-FET, or Tri-gate -FET

three-dimensional (3-D) integration

3D integration technology

three-dimensional (3-D) integrated circuits

three-dimensional (3-D) IC

3D Integrated Circuits

3-D integrated circuits

3D IC

3-D IC

Asynchronous 3D ICs

3D晶体管

3-D grid

Tru3D

self-contained 3-D unit

self-powering 3D IC

Graph theory for 3d IC design

Graph theory for 3d integrated circuits

Graph and 3d IC design

Graph models for 3d IC

Steiner 3d IC

Steiner tree 3d IC

General Info

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A threedimensional integrated circuit (3-D IC) is any circuit in which the active devices are not confined to a single plane. We may consider such a circuit to be a collection of distinct 2-D (conventional) ICs, each of which individually is called a “device layer”, “tier”, “stratum” or simply a “wafer” (although the latter term does not strictly apply in some technologies). These conventional layers, together with a means of interconnecting devices on separate layers, make up a three-dimensional integrated circuit.

3D integration technologies can be classified into three categories

:(i) 3D packaging,

the package level (3D system-on-a-package)

The 3D packaging techniques, including the wire-bonded die-stack technique and the Ball-Grid-Array (BGA)-stack technique, have been widely used in many consumer products, especially the handheld devices.

the chip level (3D system-on-a-chip)

3D bonding technologies (e.g., wafer to- wafer, die-to-wafer, and die-to-die bonding)

The bonding technology could be oxide-to oxide bonding [53], copper-to-copper bonding [13, 104, 121], and dielectric adhesive bonding [53].

(ii) 3D TSV-based integration (top-down, parallel integration), and through-silicon vias (TSVs),

The 3D TSV-based integration fabricates individual wafers in parallel, and stacks the wafers or dies with TSVs as die-to-die interconnections. Recently this technology has attracted significant research and development efforts from both industry and academia.

the circuit-level 3D-integration

the circuit level (3D integrated circuit or 3D IC)

multi-layer buried structures (MLBS)

(iii) 3D monolithic integration (bottom-up, sequential integration).

3D monolithic integration, which builds active semiconductor device layers sequentially on a single wafer, is still at an early R&D stage.

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silicon on insulator (SOI) technology

3D Architecture Exploration

Architectural Design of a Three Dimensional FPGA

Parametric Yield and Profits of 3D ICs
integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs.

Thermal Analysis

Compact Thermal Modeling

finite difference method (FDM)

Finite Element Method (FEM)

computational fluid dynamics (CFD).

Mapping
combined mapping and routing algorithm based on Answer Set Programming (ASP)

Layout

graph layout problems
genetic algorithms

Floorplanning

communication demand graph (CDG)

Thermal-Aware 3D Floorplanning

Simulated Annealing

3D B*-tree structure is applied in our algorithm as a floorplan representation

3D B*-tree floorplan representation

Partitioning

min-cut partitioning

hypergraph

Multi-level hypergraph partitioning

Integer Linear Programming (ILP)

convex programming problem

approximate convex problems

CLIP/CDIP

simulated annealing

sequence of knapsack problems

Fiduccia-Mattheyees (F-M) algorithm

hMetis

PaToH

Kernighan-Lin

3D IC Design Partitioning with Power Consideration

3D Placement

hypergraph

circuit or sub-circuit is represented as a hypergraph

Placement Algorithm: Partitioning

min-cut partitioning

recursive min-cut partitioning

recursive minimum-cut partitioning

Fiduccia- Mattheyses (FM) algorithm

multi-level FM partitioning

Kernighan-Lin algorithm

iterative deletion

Rectilinear Steiner Tree

dynamic programming

Quadratic placement

Reinforcement Learning (RL)

simulated annealing

divide and conquer approach

Two-opt algorithm

Support Vector Machines (SVMs)

analytical approach by Tanprasert

a placement algorithm due to Ohmura

force-directed algorithm

(Thermal) 3D interconnect TS (Through-the-Silicon) Via Planning
3D interconnect

Non-Linear Programming Formulation

convex programming

non-convex quadratic programming

geometric programming

Thermal Through-the-Silicon (TTS) Via Planning

Thermal TS Via Planning

constrained nonlinear programming problem (NLP)

SAT-based system synthesis

based on the thermal resistive model and develop an efficient heuristic algorithm, named m-ADVP, which solves a sequence of simplified via planning subproblems in alternating direction in a multilevel framework.

Routing

Evolutionary 3D Over?the?Cell Router - genetic algorithms

heuristic techniques called genetic algorithms

Simulated Annealing

Global Routing Using Integer Programming

linear programming (LP)

integer linear programming (ILP)

progressive ILP

Dynamic programming

Dynamic programming based layer assignment technique that carefully consider net routing structure and routing resources to minimize via count.

combined mapping and routing algorithm based on Answer Set Programming (ASP)

AUCTION BASED DETOUR TECHNIQUE

breadth-first-search technique

bread first search

A* search

A* algorithm

divide and conquer approach

Reinforcement Learning (RL)

Two-opt algorithm

Support Vector Machines (SVMs)

probability theory

graph

2 layer global routing grid graph model

shortest path algorithm

modified Dijkstra’s shortest path algorithm

Steiner Tree

Steiner minimum tree

3D Routing based on MST (Minimum Steiner Tree)

Rectilinear Minimal Steiner Tree (RMST)

look-up table based Steiner Tree generation technique

congestion-driven Steiner tree topology generation technique

Multi-Level Grid Graphs

Multicast Routing Graph (MRG) and Multicast Routing Tree (MRTree)

edge shifting technique

3D Interconnects and Routing

3D IC Global Routing

3D maze routing

min-cost maze routing

3D Field-Programmable Gate Array (FPGA) routing

3D hierarchical routing

network flow based routing

multi-commodity ow approximation algorithm to solve the global routing problem

channel routing

3D channel routing

multilayer routing algorithms

multi?layer channel router

multilayer channel routing

YACR2

over?the?cell (OTC) routing

3-D Global Routing

concurrent (hierarchical) router

traditional maze router based on the A* algorithm

overthe- cell routing strategy

nonlinear-programming formulation

Three-Dimensional Channel Routing

The number of layers is called the height of the 3-D channel.

What's that???

Three-Dimensional Channel Routing

Three-Layer Channel Routing

Channel Routing for Three-Dimensional IC

3-dimensional Routing Problem (3DRP)

3-D channel

3-D channel routing

3-dimensional channel routing

3DCRP - 3-dimensional Channel Routing Problem

3-dimensional Γ Routing Problem (3DΓ RP)

three-dimensional (3-D) integration

3D integration technology

3D integrated circuits

3-D integrated circuits

SALRP - Single Active Layer Routing Problem

cubic grids

3-D grid

vertex- disjoint Steiner-trees (trees with given sets containing specific terminals) on a 3-dimensional cubic grid

The three-dimensional (3-D) integration is an emerging technology to implement large circuits, and currently being extensively investigated.

The emerging three-dimensional (3D) integration technology is one of the promising solutions to overcome the barriers in interconnect scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. As the fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques are imperative for the successful adoption of 3D integration technology.

The 3-D channel routing is a fundamental problem on the physical design of 3-D integrated circuits. In the 3-D channel routing, the channel is a 3-D grid G consisting of columns, rows, and layers which are planes defined by fixing x-, y-, and z-coordinates, respectively. A terminal is a vertex of G located in the top or bottom layer. A net is a set of terminals to be connected. A net containing k terminals is called a k-net. A tree connecting the terminals in a net is called a wire. The object of the 3-D channel routing problem is to connect the terminals in each net with a wire in G using as few layers as possible and as short wires as possible in such a way that wires for distinct nets are disjoint. The number of layers is called the height of the 3-D channel.

Again, we are supposed to connect certain given subsets of the devices by wires and this routing is to be realized in a 3-dimensional cubic grid above the layer that contains the devices. In other words, we have to find vertex disjoint trees with given vertex sets in a 3-dimensional rectangular grid. Clearly, the number of required layers, that is the height of the routing should be optimized. Because of the difficulty of the problem, most of the routing algorithms are approximate and they will not necessarily find the best solutions. As we will see, the problem is not always solvable even with an arbitrary height, moreover even for small instances (e.g. when the circuit board is 2x2) there does not exist a sufficient routing. Consequently, we introduce extra rows and columns to guarantee solvability.

Finally, we will consider the case in which the terminals are placed on two layers, so called 3-dimensional channel routing.

For the 3-D channel routing, it has been known that the problem of deciding if a given set of nets is routable in a 3-D channel is NP-complete

It has been also known that if G is a (2N; 2N; 3N)-channel, the terminals are located on vertices with odd x- and y-coordinates, and each net has terminals both on top and bottom layers, then any set of 2-nets is routable in G . Moreover, if G is a (2N; 2N;N=2??)-channel for any  > 0, the terminals are located on vertices with odd x- and y-coordinates, and each net has terminals both on top and bottom layers, then there exists a set of 2-nets that is not routable in G.

For the 3-D single-active-layer routing, it has been known that if G is a (2N; 2N; 3N)-channel, and the terminals are located on vertices with odd x- and ycoordinates, then any set of 2-nets is routable in G . It has been also known that if G is a (2N; 2N; 6N)- channel, the terminals are located on vertices with odd x- and y-coordinates, then any set of multiterminal nets is routable in G. Moreover if G is a (2N; 2N;N=4 ?? )-channel for any  > 0, and the terminals are located on vertices with odd x- and ycoordinates, then there exists a set of 2-nets that is not routable in G.

Theorem 1 If G is a (2N; 2N; 5N=2)-channel, and the terminals are located on vertices with odd x- and y-coordinates either on the top or bottom layer, then any set of multiterminal nets is routable in G.

Theorem 1: If the layers are square 2-D grids of area 4n, the terminals are located on vertices with even x- and y- coordinates, and each net has terminals both in top and bottom layers, then any set of n 2-nets can be routed in a 3-D channel of height O(pn) using wires of length O(pn).

Theorem 1 implies that any set of n 2-nets can be routed in a 3-D channel of volume O(n3=2). It should be noted that for the ordinary 2-D channel routing there exists a set of n 2-nets requiring a 2-D channel of area (n2) to be routed.

Theorem 2: There exists a set of n 2-nets that requires a 3-D channel of height (pn) to be routed.
=============================================

Combined 3D (4?layer) and over?the?cell (OTC) routing based on genetic algorithms

the framework of GALOPPS ("Genetic Algorithm Optimized for Portability and Parallelism" System)
=============================================

the 3-D SOP Optical Routing Problem

is defined formally as follows:

  • generate a routing topology for each net ,
  • assign to optical or electrical routing layer or both,
  • and assign all pins of to legal locations.

All conflicting nets are assigned to a different routing layer.

The goal is to minimize a weighted sum of:

1) the maximum delay among all nets;

2) total wirelength of all nets; and

3) total routing layers (electrical and optical) used.

The constraints include via and wire capacity for each routing region in a given 3-D SOP structure
=============================================

3-Dimensional VLSI routing, 2007, p19..

Arai, Yohei: A Note on the Three-Dimensional Single-Active-Layer Routing, Februaru 2007, p1

Cong, Jason and Zhang, Yan: Thermal-Driven Multilevel Routing for 3-D ICs, Nov 2004, p6..

DeNava, Erick et al: Three-Dimensional Off-Axis Component Placement and Routing for Electronics Integration using Solid Freeform Fabrication, September 10, 2008, p8

Goni, B. M. and Arslan, T.: An Evolutionary 3D Over?the?Cell Router, July 1999, . p4 ..

HARALAMBIDES, JAMES: Multilevel Routing for 3-Dimensional Circuits, p5, Proceedings of the 10th WSEAS International Conference on COMPUTERS, Vouliagmeni, Athens, Greece, July 13-15, 2006 (pp1224-1228)

Kiss, Attila: 3-dimensional routing in VLSI design on a cube. 2005, p1

Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8

Recski, Andras and Szeszler, David: 3-dimensional Routing, Aug 2008. p8

Reiss, Attila and Szeszler, David: 3-dimensional Channel Routing, Nov 2007. p10

Tayu, Satoshi and Ueno, Shuichi: A Note on the Three-Dimensional Channel Routing, Proceedings of the IEEE International Symposium on Circuits and Systems, pp.180-183, 2005 , p1

Tayu, Satoshi et al: On the Three-Dimensional Channel Routing, 0-7803-8834-8/05, IEEE, 2005, p4.

Tayu, Satoshi and Ueno, Shuichi: The Complexity of Three-Dimensioal Channel Routing (Extended Abstract), p10

Xie, Yuan et al: Three-dimensional Integrated Circuits: Design, EDA, and Architecture, June 2011, p156 .

Temperature-Aware Routing in 3D ICs

thermally-driven 3D routing algorithm

Thermal-Driven Multilevel Routing for 3-D ICs

thermally driven maze routing

Thermal vias correspond to vertical interlayer vias that do not have any electrical function, but are explicitly added as thermal conduits. Thermal wires perform a similar function, but conduct heat laterally within the same layer.

linear programming (LP) based thermal via/wire insertion is performed to reduce temperature.

NP-complete

3D Component Modeling and Testing

Testing 3D Chips Containing Through-Silicon Vias

Design Tools for 3-D Integrated Circuits

The absence of 3D EDA tools that can explore the 3D design space is an impediment to the adoption of the new technology.

Standard-cell placement tool

  • quadratic placement
  • simulated annealing
  • placement by min-cut partitioning

?

Global routing tool

FastRoute 4.0

There are two academic 3D global routers, FGR and GRIP

NTHU-R 2.0

NTUgr

NCTU-R

BoxRoute 2.0

MaizeRouter

Archer

layout editor

Clock tree, Clock skew

Security for 3D integration

graph

constraint (SAT) solver

greedy heuristic

Spectrum of Challenges in 3-D ICs

Manufacturing
?Plane alignment and bonding
?Through silicon vias

Testing
?Pre-bond testing
?Post-bond testing
?Built-in-self-test

Design
?Interconnect design techniques
?Thermal management techniques
?Physical design techniques
?Routing
?Electrical and thermal characterization
?Floorplanning
?Heterogeneous system design
?Memory on processor
?MEMS/NEMS
?RF/Analog/Mixed Signal
?EDA tool development
?DRC, LVS, place & route

Related Math

Linear Partial Differential Equations

quadratic uniformity modeling

Numerical Optimization

Finite Element Method (FEM)

linear programming

linear and non-linear programming

Non-Linear Programming

Non-linear Optimization System and Method

constrained nonlinear programming problem (NLP)

quadratic programming and slicing optimization

Optimization by Vector Space Methods

Convex Optimization

convex programming

convex programming problem

graph

The Minimum Weight Bipartite Matching Problem

edge-weighted bipartite graph

hypergraph partitioning

Multi-level hypergraph partitioning

Steiner minimum tree

MST (Minimum Steiner Tree)

3D B*-tree structure

min-cut partitioning

Simulated Annealing

Evolutionary 3D Over?the?Cell Router - genetic algorithms

GALOPPS ("Genetic Algorithm Optimized for Portability and Parallelism" System)

Multilevel optimization

New three-dimensional integration technology using self-assembly technique


3D IC Literature

3-Dimensional VLSI Routing p19
Graph Models for Global Routing: Grid Graph p17

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“3D IC and TSV Report”, http://www.yole.fr/pagesAN/products/Report_sample/3DIC.pdf, 2007.

graph

tree

Literature
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“3D IC and TSV Report”, http://www.yole.fr/pagesAN/products/Report_sample/3DIC.pdf, 2007.

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Terminology

Literature


ASIC Design
An ASIC is an Application Specific Integrated Circuit. An Integrated Circuit designed is called an ASIC if we design the ASIC for the specific application. Examples of ASIC include, chip designed for a satellite, chip designed for a car, chip designed as an interface between memory and CPU etc. Examples of IC’s which are not called ASIC include Memories, Microprocessors etc. The following paragraphs will describe the types of ASIC’s.

ASIC

逻辑综合、DFT等ASIC流程

Full-custom ASIC

Cell-based ASIC

Semi-Custom ASICs

Semi-custom ASICs, in which all of the logic cells are predesigned and some (possibly all) of the mask layers are customised. Using predesigned cells from a cell library makes designers’ task much easier.

Semi-custom ASICs are classified into

  • standard-cell based ASICs and
  • gatearray based ASICs.

In programmable ASICs all of the logic cells are predesigned and none of the masked layers is customised. There are two types of programmable ASICs, namely, programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs).

Full-custom ASICs.

In a full-custom ASIC the engineer designs some or all of the logic cells, circuits, or layout specifically for one ASIC. This means the designer abandons the approach of using pretested and precharacterised cells for all or part of the design. It makes sense to take this approach only if there are no suitable cell libraries available that can be used for the entire design. This might be because existing cell libraries are not fast enough, or the logic cells are not small enough or consume a large power.

Full-Custom ASIC: For this type of ASIC, the designer designs all or some of the logic cells, layout for that one chip. The designer does not used predefined gates in the design. Every part of the design is done from scratch.

Standard cell-based ASICs.

A cell-based ASIC (CBIC) uses predesigned logic cells (AND gates, OR gates, multiplexers, and flip-flops) known as standard cells. The standard cells in a CBIC fit together like bricks in a wall. The standard-cell areas may be used in combination with larger predesigned cells, such as microcontrollers or even microprocessors, known as mega cells. Mega cells are also called mega functions, full-custom blocks, system-level macros, fixed blocks, cores, or functional standard blocks.

Standard Cell ASIC: The designer uses predesigned logic cells such as AND gate, NOR gate, etc. These gates are called Standard Cells. The advantage of Standard Cell ASIC’s is that the designers save time, money and reduce the risk by using a predesigned and pre-tested Standard Cell Library. Also each Standard Cell can be optimized individually. The Standard Cell Libraries is designed using the Full Custom Methodology, but you can use these already designed libraries in the design. This design style gives a designer the same flexibility as the Full Custom design, but reduces the risk.

Gate-array based ASICs.

In gate-array based ASICs the transistors are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the base array, and the smallest element that is replicated to make the base array is the base cell. Only the top few layers of metal, which define the interconnects between the transistors, are defined by designers using custom masks. To distinguish this type of gate array from other types of gate arrays, it is often called the masked gate array (MGA). MGA ASICs are classified into the following types:

  • 1. Channelled gate arrays
  • 2. Channelless gate arrays
  • 3. Structured gate arrays

Gate Array ASIC: In this type of ASIC, the transistors are predefined in the silicon wafer. The predefined pattern of transistors on the gate array is called a base array and the smallest element in the base array is called a base cell. The base cell layout is same for each logic cell, only the interconnect between the cells and inside the cells is customized. The following are the types of gate arrays:

a. Channeled Gate Array

b. Channelless Gate Array

C. Structured Gate Array

There are two types of programmable ASICs, namely,

  • programmable logic devices (PLDs) and
  • field-programmable gate arrays (FPGAs).

=================================================

Kernighan-Lin (KL) Algorithm

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 2: Netlist and System Partitioning

Given: A graph with 2n nodes where each node has the same weight.
Goal: A partition (division) of the graph into two disjoint subsets A and B with minimum cut cost and |A| = |B| = n.

Cost D(v) of moving a node v

D(v) = |Ec(v)| – |Enc(v)| ,
where
Ec(v) is the set of v’s incident edges that are cut by the cut line, and
Enc(v) is the set of v’s incident edges that are not cut by the cut line.
High costs (D > 0) indicate that the node should move, while low costs (D < 0) indicate that the node should stay within the same partition.

Gain of swapping a pair of nodes a und b

Δg = D(a) + D(b) - 2* c(a,b),
where
? D(a), D(b) are the respective costs of nodes a, b
? c(a,b) is the connection weight between a and b:
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.
The gain Δg indicates how useful the swap between two nodes will be
The larger Δg, the more the total cut cost will be reduced
============================================

Min-Cut Placement

I Use partitioning algorithm (such as KL) to divide netlist into two regions
I Use partitioning algorithm to recursively divide the two partitions into two smaller regions (four regions total)
I Each cut heuristically minimizes the number of cut nets
============================================

Analytical Placement with Quadratic Placement Algorithm

? KLMH
4.3.2 Analytic Placement – Quadratic Placement
? Objective function is quadratic; sum of (weighted) squared Euclidean distance represents placement objective function
where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
? Only two-point-connections
? Minimize objective function by equating its derivative to zero which reduces to solving a system of linear equations
============================================

Routing Algorithm Taxonomy

Routing

  • Multi-Stage Routing of Signal Nets
    • Global Routing
      • Coarse-grain assignment of routes to routing regions
    • Detailed Routing
      • Fine-grain assignment of routes to routing tracks
    • Timing-Driven Routing
      • Net topology optimization and resource allocation to critical nets
  • Large Single- Net Routing
    • Power (VDD) and Ground (GND) routing
  • Geometric Techniques
    • Non-Manhattan and clock routing
============================================

Heuristic Sequential Steiner Tree Algorithm

1. Find the closest (in terms of rectilinear distance) pin pair, construct their minimum bounding box (MBB)
2. Find the closest point pair (pMBB,pC) between any point pMBB on the MBB and pC from the set of pins to consider
3. Construct the MBB of pMBB and pC
4. Add the L-shape that pMBB lies on to T (deleting the other L-shape). If pMBB is a pin, then add any L-shape of the MBB to T.
5. Goto step 2 until the set of pins to consider is empty
============================================

Horizontal Constraint Graphs
? Let S(col) denote the set of nets that pass through column col
? S(col) contains all nets that either (1) are connected to a pin in column col or (2) have pin connections to both the left and right of col
? Since horizontal segments cannot overlap, each net in S(col) must be assigned to a different track in column col
? S(col) represents the lower bound on the number of tracks in colum col; lower bound of the channel height is given by maximum cardinality of any S(col)
============================================

Vertical Constraint Graphs
============================================

Left-Edge Algorithm

1. Generate VCG and zone representation

2. Consider next track
3. Find left-to-right ordering of all unassigned nets
4. Delete placed nets (A, J ) in VCG and zone represenation
============================================

full chip RTL timing closure for very large ASIC’s

The methodology is based on the concept of a “Silicon Virtual Prototype”. The methodology is based on the scalable technique of clustering and cluster placement and leverages the tight integration between the algorithms by means of a common, unified data model.

silicon virtual prototype
============================================


FPGA

field programmable gate arrays (FPGAs)

FPGA Basics

symmetrical FPGA

symmetric island style FPGA model

hybrid FPGAs

T3 FPGA
FPGA IP

Field Programmable Gate Arrays (FPGAs)

LPGA (Laser Programmable Gate Array)

Gate array

field programmable gate arrays (FPGAs)

Island FPGA Architecture

Abstract Logic Block

3D FPGA

3D FPGA

3D-FPGA

three-dimensional FPGA architecture

Multi-Chip Module 3D FPGA

The Rothko Architecture

Monolithically stacked FPGAs

Sparsely connected architectures

Sunny Egg architecture

Software support

  • Spiffy - Simultaneous placement and global routing. Placement is recursive partition based.
  • Three-dimensional Place & Route (TPR) – Placement (recursive partition based and simulated annealing based, routing is based on PathFinder algortihm)
  • SA-TPR: In addition to the partitioning-based 3D placement tool, we have also developed a Simulated Annealing based version of TPR (called SA-TPR) to provide speed / quality tradeoffs.
  • 3D MEANDER
heat dissipation, thermal stress, and physical design considerations – remain to be addressed for some 3D architectures

Design General

See Altera My First FPGA Design Tutorial p52 July 2008 for a complete design procedure using Altera's software

The FPGA design flow can be divided into the following stages:

1. Design Entry

a) Performing HDL coding for synthesis as the target (Xilinx ISE)

b) Using Cores (Xilinx Core Generator)

. Behavioral Simulation of synthesizable HDL code (ModelSim)

3. Design Synthesis (Translation) (Xilinx ISE)

4. Design Implementation (Map, Place & Route) (Xilinx ISE)

5. Timing (Post Implementation) Simulation (ModelSim)

FPGA design flow
The standard FPGA design flow starts with design entry using schematics or a hardware description language (HDL), such as Verilog HDL or VHDL. In this step, you create the digital circuit that is implemented inside the FPGA. The flow then proceeds through compilation, simulation, programming, and verification in the FPGA hardware

FPGA design flow includes:

Design Entry

The design entry can be done using: a) HDLs such as verilog and VHDL, b) schematic diagrams, and, c) combination of both a) and b). The schematic input provides more visibility of hardware to designers than HDL input.

Synthesis

During synthesis, the circuit which is represented using verilog or VHDL code is translated into netlist. The design hierarchy is analyzed and the netlist is generated for each design element in the circuit. Some amount of design optimization is also done during synthesis.

physical synthesis, RT-level and behavior-level synthesis,

RTL to Logic Synthesis

Technology Independent Synthesis
Technology Dependent Synthesis

Synthesis
– Parses HDL design
– Infers Xilinx primitives
– Generates design netlist

Translate

– Merges incoming netlists and constraints into a design file

Logic Minimization

Logic minimization is a process by which the redundant logic circuits are identified and removed. Employing the logic minimization there are two approaches namely, Boolean and Netlist approaches. The Boolean based approach analyzes the logic representation used in the circuit and optimizes it. The Boolean methods are very effective in logic minimization and less efficient in execution time. The Netlist method depends on the identification of faults for describing the redundant elements. The existence of redundant circuit elements is equivalent to undetectable faults, means the presence and absence of that does not change the functionality of the circuit.

Technology Mapping

technology mapping and architecture-specific optimization,

FPGA technology mapping transforms a network of technology-independent logic gates into one comprised of logic cells in the target FPGA architectures. It divides the whole circuit with logical elements into sub blocks that can be fitted into the FPGA logic blocks. As a result, technology mapping has a significant impact on the quality (area, performance, power, etc.) of the final implementation.

Map

– Maps (places) design into the available resources on the target device

Place and Route

– Places and routes design to the timing constraints

Place and Route

The place and route is the next step in the FPGA design flow after technology mapping. Placement algorithm places different partitioned blocks of the net-list on the logic resources of the FPGA. After the blocks are placed in the FPGA, routing algorithms establish connections among those blocks.

FPGA Routing - based on Geometric Routing

The geometric routers like CGE, SEGA, PathFinder, VPR uses the global and detailed routing. These algorithms uses the ripped up and reroute and negotiation approach to route the given layout. The geometric routing algorithms are efficient even though it has several short comings. The basic routing algorithms has the limitations like dependence on net ordering, conventional one-net-at-a time routing is unable to predict the routability if a problem has tight routing constraints.

Coarse Graph Expansion (CGE)

SEGment Allocator (SEGA)

PathFinder

Versatile Place and Route (VPR)

FPGA Routing – based on Boolean Satisfiability

FPGA Detailed Routing Approach via Search – Based Boolean Satisfiability

Hybrid Algorithm for FPGA Routing (F-R-SDR)

Optimization of FPGA Routing Algorithm (V-sub-PBS)

Optimization of FPGA Routing Algorithm (P-PBS)

Global Routing

Detailed Routing

Partitioning

Kernighan-Lin (KL) Algorithm

circuit clustering

power optimization

Device Programming

The device programming is final step of the CAD flow diagram. After the completion of placement and routing, a bit-stream file is generated this is used to configure the FPGA. The device can be programmed through the dedicated pins of configuration ports. The ports can be either parallel or USB port. After the implementation the final verification takes place on FPGA based on various parameters. Completion of successful verification the FPGA design can be migrated as ASIC.

FPGAs were first debuted in the mid- to late-80s

Altera’s Stratix II

Xilinx’s Virtex-4 chips

programmable logic cells (i.e., lookup tables LUTs)

macro blocks

  • embedded memories,
  • DSP blocks,
  • embedded processors,
  • high-speed IOs,
  • clock synchronization circuitry

system-on-a-chip (SoC) designs

FPGA CAD

FPGA architectures

core programmable fabric

programmable logic blocks

configurable logic blocks (CLBs)

programmable routing architectures

island-style FPGA

switch blocks

programmable switches

connection blocks

3D-FPGA

Simulation
There are two types of simulation, RTL and timing. RTL (or functional) simulation allows you to verify that your code is manipulating the inputs and outputs appropriately. Timing (or post place-and-route) simulation verifies that the design meets timing and functions appropriately in the device.

Design Entry

The design entry can be done using: a) HDLs such as verilog and VHDL, b) schematic diagrams, and, c) combination of both a) and b). The schematic input provides more visibility of hardware to designers than HDL input.

– Timing analysis & delay modeling

Optimization & Synthesis

Synthesis tools produce a netlist of
– inputs / outputs, combinational Boolean functions, and registers

During synthesis, the circuit which is represented using verilog or VHDL code is translated into netlist. The design hierarchy is analyzed and the netlist is generated for each design element in the circuit. Some amount of design optimization is also done during synthesis.

physical synthesis, RT-level and behavior-level synthesis,

RTL to Logic Synthesis

Technology Independent Synthesis
Technology Dependent Synthesis

Synthesis
– Parses HDL design
– Infers Xilinx primitives
– Generates design netlist

Synthesis Optimizations (I)

? global_opt on|off
Optimization routines that operate on the fully assembled netlist after initial packing. These optimizations include logic remapping and trimming, logic and register replication. This option can optimize blackboxed portions of the design.
? logic_opt on|off
Post‐placement logic restructuring. Operates on a placed netlist to optimize timing critical connections through restructuring and resynthesis, followed by incremental placement and incremental timing analysis. Option is enabled in conjunction with “‐timing”.

register_duplication on|off
The option is only available when running timing‐driven packing and placement with the –timing option. The option duplicates registers to improve timing when running timing‐driven packing (“‐timing”).
? retiming on|off
When this option is on, registers are moved through the logic to balance out the delays in a timing path to increase the overall clock frequency. By default, this option is off. It requires global_opt “on” to operate.
? timing
Enables packing and placement interaction based on timing goals. When activated, placement is done during the MAP phase, therefore the “‐ logic_opt on|off” option should be used along with it.

? Logic Duplication
If a LUT or flip‐flop drives multiple loads, and the placement of one or more of those loads is too far away from the source to meet timing requirements, the LUT or flip‐flop can be replicated and placed close to that group of loads, thus reducing routing delays.
? Logic Recombination
If the critical path traverses through multiple LUTs and through multiple slices, the logic can be reassembled utilizing fewer slices by using a more timing efficient combination of LUTs and MUXes to reduce the routing resources needed for that path.
? Basic Element Switching
If a function is built with LUTs and MUXes within a slice, physical synthesis and optimization can rearrange the function to give the fastest path (usually through the MUX select pin) to the most critical signal.
? Pin Swapping
Each input pin of a LUT may have a different delay. MAP has the ability to swap pins (and change the LUT equation accordingly) so that the most critical signal is assigned to the fastest pin.

? Under‐constraining in synthesis prevents it from generating the best optimizations→ tightly constrain synthesis until the tool reports negative slack.
? Design reuse netlist used as “black‐boxes” in synthesis may limit the amount of possible optimization. Synthesis has the capability in the traditional flow to “read” netlists from black‐boxes. This helps the tools analyze paths going to and coming from the black boxes. → add these black boxes to the synthesis project and this is where physical synthesis options can have a great impact.

Optimization Problems

Objectives

– area: minimize the required chip area
– delay: minimize the delay on the critical path
– power: minimize the dynamic power dissipation
– routability: facilitate successful routing
→ these goals are often conflicting, eg. area and delay'

Cost models (estimates)

– area models: number of LUTs (logic blocks), routing area
– delay models: logic block delay, routing delay
– power models: the power can be estimated by the output load capacitances and transition frequencies

Timing Analysis & Delay Modeling
 Timing analysis determines the delays of the paths in the circuit
– after place and route
 to determine the minimum required clock period (maximum clock frequency) for a design
 should be accurate
– during technology mapping, placement, and routing
 estimates are needed to compare different mappings, placements, routes
 should be fast and show high fidelity (rather than a high accuracy)
 Timing analysis is based on delay models
– the logic block delay can be determined by simulation at the physical level (eg. with SPICE); this delay is roughly constant for all logic blocks of an FPGA
– the routing delay depends on the actual routes for a net (ie. the assigned wires, connection blocks, and switch boxes)

Timing Analysis & Timing Graph

There are several routing delay models with different accuracies

 unit delay model: each net has the same constant delay
 net delay model: each net can have a different delay
 edge delay model: each branch of a net can have a different delay
 nominal delay model: net delay is proportional to the net size
 Elmore delay model: takes physical parameters of wires, pass transistors, and buffers along the routes into account

The circuit is modeled as a netlist with annotated delays

– the netlist is a graph with nodes (PIs, POs, LUTs, registers) and edges (nets)
– nodes and edges have annotated delays (setup times for registers are included in the delays for the input nets)

Timing Graph

The annotated netlist is transformed into a timing graph

– the nodes of the timing graph are the PIs and POs and the inputs and outputs of the LUTs and registers; register inputs and outputs are not connected →the timing graph is acyclic
– the edges are labelled with the delays of nets and LUTs

Minimum required clock period (maximum frequency) is computed by a breadth-first traversal of the timing graph

– starting from the PIs, each node i is assigned an arrival time Ta(i)
 PIs and register outputs have Ta=0
 for all other nodes i:
– the minimum required clock period is the largest arrival time of any node

Timing Graph - Slack

 The slack measures the criticalness of a path in the circuit
– with Dmax as the maximum delay of any node in the circuit, the slack is the amount of delay that can be added to a path without increasing Dmax
 Computation of the slack
– second traversal of the timing graph:
 starting from the POs, each node i is assigned a required time Tr(i)
 POs and register inputs have Tr= Dmax
 for all other nodes i:
– the slack of a connection from node i to node j is given by
– a connection with slack zero is on the critical path

Elmore Delay Model

 RC element
– the Elmore delay is t = RiCi
– approximation for the 50% propagation delay, ie. the time it takes until y(t)=0.5 when x(t)=s(t)
 RC tree
– the Elmore delay between a node x and a node y is
– where Ri is the resistor at node i, and C(Ti) is the total capacitance of the subtree Ti rooted at node i
Ci
Rx(t) i y(t)
Σ
?
= ×
( , )
, ( )
i path x y
x y i i t R C T
R (3C) R (C) 4RC

Delay Models for Routing Elements (1)

 Wire
– Rw and Cw are determined by the length of the wire and material parameters
 Pass transistor
– Rp is the on resistance of the pass transistor
– Cp is the diffusion capacitance

Delay Models for Routing Elements (2)

 Buffer
– Rb is the buffer resistance
– Cin and Cout are input and output capacitances
– td is the intrinsic delay (not load-dependent)

Delay Models for Routing Elements (3)

 Routing delay
– the Elmore delay model can be applied because all routing elements
are modeled as RC trees
– the Elmore delay between a node x and a node y is
 td,i is the intrinsic buffer delay td if i is a buffer; zero otherwise
 buffers drive their subtrees
→when determining C(Ti), only the capacitances up to the next
buffer are taken into account (including Cin)
Σ

Translate

– Merges incoming netlists and constraints into a design file

Logic Minimization

Logic minimization is a process by which the redundant logic circuits are identified and removed. Employing the logic minimization there are two approaches namely, Boolean and Netlist approaches. The Boolean based approach analyzes the logic representation used in the circuit and optimizes it. The Boolean methods are very effective in logic minimization and less efficient in execution time. The Netlist method depends on the identification of faults for describing the redundant elements. The existence of redundant circuit elements is equivalent to undetectable faults, means the presence and absence of that does not change the functionality of the circuit.

Technology Mapping

technology mapping and architecture-specific optimization,

FPGA technology mapping transforms a network of technology-independent logic gates into one comprised of logic cells in the target FPGA architectures. It divides the whole circuit with logical elements into sub blocks that can be fitted into the FPGA logic blocks. As a result, technology mapping has a significant impact on the quality (area, performance, power, etc.) of the final implementation.

– Technology mapping
 network decomposition
 LUT mapping
 sequential mapping
 logic block packing (algorithm VPack)

Technology mapping
– maps the combinational functions to K-LUTs (LUT mapping, LUT covering)
– combines LUTs and registers into logic blocks

Map

– Maps (places) design into the available resources on the target device

Physical Design

timing-driven partitioning

simulated annealing based placement algorithms

detailed routing tool for 3D FPGA integration

Partitioning
min-cut hMetis partitioning algorithm

Placement and Routing

Simultaneous Placement and Routing Techniques

A set of new performance driven simultaneous placement/routing techniques has been developed for both row-based and island-style FPGA designs. These techniques rely on an iterative improvement placement algorithm augmented with fast, complete routing heuristics in the placement loop. For row-based designs, this new layout strategy yielded up to 28% improvements in timing and 33% in wirability for several MCNC benchmarks when compared to a traditional sequential place and route system.

Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines

an artificial neural network (ANN) based parallel evolutionary solution to the placement and routing problems

PLACEMENT

Placement Definition

?Input:

?Netlistof logic blocks
?I/O pads
?Inter connections

?Output:

?Coordinates (xi, yi) for each block.
?The total wire length is minimized.
?Also need to consider delay and routability.

Major Placement Techniques

?Partitioning-Based Placement
?Simulated Annealing Placement

Analytical method-based placement
?Quadratic Placement
?Hybrid and Hierarchical Placement

Serial algorithm

? Analytical based method
? Simulated annealing based method
A hybrid parallelization method of the simulated annealing based placement algorithm

Parallel acceleration

Partitioning-Based Placement

?Partitioning: Decomposition of a complex system into smaller subsystems
?Partitioning-based placement recursively apply min-cut partitioning to map the netlistinto the layout region
?Cutsize: the number of nets not contained in just one side of the partition
?e.g. FM partitioning algorithm

Simulated Annealing Placement

?Simulated annealing algorithm mimics the annealing process used to gradually cool molten metal to produce high quality metal structures
?Initial placement improved by iterative swaps and moves
?Accept swaps if they improve the cost
?Accept swaps that degrade the cost under some probability conditions to prevent the algorithm from being trapped in a local minimum

– Placement
 simulated annealing (algorithm VPR)

Quadratic Placement

?Use squared wire length as objective function
?Minimize the objective function by solving linear equations
?Expand the design to entire chip area

Hybrid and Hierarchical Placement

?The scale of logic circuits grows fast
?Compile time grows exponential with the number of logic blocks
?Hierarchical methods are introduced to reduce the compile time
?in different hierarchies use different algorithms
?E.g.
?GORDIAN quadratic + partitioning
?Dragon: partitioning + Simulated Annealing

Dominating Placement algorithm: VPR

?Simulated Annealing based
?Adaptive annealing schedule
?Use delay profile of target FPGA to evaluate the delay of each connection
?Trades off between circuit delay and wiring cost optimization

linear congestion method used in the state-of-the-art FPGA place and route package VPR

T-VPlace is the simulated annealing based placement algorithm used in VPR

congestion driven placement algorithm

Routing
Faster FPGA Routing Solution using DNA Computin

DNA search algorithm

DNA Satisfiability Detailed Router (DSDR)

Boolean satisfiability problem (SAT)
Through Silicon Via (TSVs)
TSV based 3D thermal optimization model for Tree-based FPGA
Mesh based FPGAs
3D Tree-based FPGA architecture
3D place and route (TPR)
– Routing
 Pathfinder (algorithm VPR)

FPGA Routing Channels Architecture

There are many different FPGA architectures available from various vendors including Altera, Xilinx, Actel, Lucent, Quick Logic and Cypress. The layout structure of these FPGAs depends upon three parameters configurable logic blocks, I/O blocks and programmable routing. Our main consideration in this paper is on programmable FPGA routing shown in [Section 2].

========================================

FPGA routing consists of pre-fabricated metal wires and programmable switches Interconnect between wire and CLB
I/O blocks.

FPGAs consist of a large number of programmable logic blocks, which can each implement a small amount of digital logic, and programmable routing which allows the logic block inputs and outputs to be connected to form larger circuits. The delay of a circuit implemented in an FPGA is mostly due to routing delays, rather than logic block delays, and most of an FPGA?s area is devoted to programmable routing. Furthermore, as FPGAs move into increasingly deep submicron IC processes, the fraction of total delay due to routing is increasing with each process generation. Consequently, one must devise routing architectures which are both fast and area-efficient to create an FPGA that fully exploits the performance and density potential of deep-submicron technologies.

===============================

Serial algorithm

Geometric routing algorithm

Geometric based method

Geometric routing algorithm

The geometric routing algorithm is based on rip-up and re-route approach

===============================

Boolean based method

Boolean SAT-based routing algorithm

Boolean Satisfiability routing algorithm

Boolean-based routing

=================================

Boolean SAT based FPGA detailed routing formulation

=================================

ant colony optimization algorithm (ASDR) for solving FPGA routing

===============================

Ant Colony Optimization

===============================

Hardware and parallel acceleration

Stochastic Chaotic Simulated Annealing

===============================

GRADUAL NEURAL NETWORK ALGORITHM

===============================

Hybrid routing algorithm

===============================

Segmented Channel Routing? 1971

An ap- proach that all FPGAs use to improve programmable in- terconnect performance is segmentation

Routing on Regular Segmented 2-D FPGAs

regular segmented FPGA routing architectures

REGULAR SEGMENTED FPGA ARCHITECTURE

segmented routing channel design

simulated- annealing procedure is used,

only for FPGA???

Exact Segmented Channel Routing (ESCR) and K-ESCR

K-ESCR heuristic

greedy ESCR algorithm

===============================

Hybrid Neural-Genetic Algorithm FPGA Segmented Channel Routing

===============================

meta-heuristic FPGA segmented channel routing

hybrid algorithms - a Hopfield neural network, mixed with a Genetic Algorithm (GA) and a Simulated Annealing (SA).

row-based segmented channel routing model

===============================

SEGA (for SEGment Allocator)

detailed routing for symmetrical FPGAs

===============================

array-based FPGAs with segmented channels

Negotiation Based Routing

Negotiated Congestion Algorithm

Iterative Deletion for Standard Cell Global Routing

Multi-Commodity Flow (MCF) Based Global Routing

Approximation Algorithm for Fractional Global Routing

VPR’s router is based on the Pathfinder negotiated congestion algorithm

Dijkstra’s algorithm i.e. a maze router

architectural routability optimization aspect for the regular segmentation type FPGAs

pin topology issue

optimizing programmable inter- connect is key to improving FPGA performance

Graph Based Analysis of 2-D FPGA Routing

FPGA IP Design Framework

Literature

Ababei, Cristinel; Moga, lHushrav and Bazargan, Kia: Three-dimensional Place and Route for FPGAs, p6, Oct 2004.................

Altera My First FPGA Design Tutorial p52 July 2008 very good

Baruch, Zoltan et al: ROUTING FOR FPGA CIRCUITS p6 1997

Baruch, Zoltan et al: CAD SYSTEM FOR THE ATMEL FPGA CIRCUITS p10 1998

Betz, Vaughn and Rose, Jonathan: VPR: A New Packing, Placement and Routing Tool for FPGA Research, 1967??? 1997 International Workshop on Field Programmable Logic and Applications, p10 .

Betz, Vaughn and Rose, Jonathan: FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density 1999 p10

@@@@@@@@@@@@@@@@@@@@@@@@@@@

Borra, Siva Nageswara Rao et al: A novel approach to the placement and routing problems for field programmable gate arrays October 2005 p16

BROWN, STEPHEN: FPGA and CPLD Architectures A Tutorial p16, 0740-7475/96 1996 IEEE, page 42-58

Brown, Stephen: Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays 1994 p24

Brown, Stephen and Rose, Jonathan: Architecture of FPGAs and CPLDs A Tutorial p41 March 2000

Chang, Yao-Wen: Matching-Based Algorithm for FPGA Channel Segmentation Design p8

Chen, Deming , Cong, Jason and Pan, Peichen: FPGA Design Automation: A Survey, Foundations and Trends in Electronic Design Automation, Vol. 1, No 3 (November 2006) 195–330, p137.........................4

Chip Design College: FPGA ASIC Technologies and Design Flow p42 2007

Chopra, Vinay and Singh, Amardeep: Ant Colony Based Approach for Solving FPGA routing, IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 4, No 2, p335-340, July 2011

de Dinechin, Florent: The Price of Routing in FPGAs, Septembre 1999, p22.

del Solar, Manuel Rubio et al: Genetic algorithms for solving the placement and routing problem of an FPGA with area constraint p5, 2003

FPGA Fabrics p60

Gómez-Pulido, Juan A.: Introduction to FPGA design with Xilinx ISE 13 and prototyping boards, October 2011, p30

Gomez-Prado, Daniel: A Tutorial on FPGA Routing p16

Greene, Jonathan et al: Segmented Channel Routing p6, 27th ACM/IEEE Design Automation Conference, 1990, p 567-573

Harikrishna B and RAVI, S.: A STUDY OF ARCHITECTURE OF FPGA ROUTING, Journal of Electronics and Communication Engineering (JECE) Vol. 2, Issue 1, Feb 2013, 1-8, p8..

HARIKRISHNA, B. & RAVI, S.: A STUDY OF ARCHITECTURE OF FPGA ROUTING p8 International Journal of Electronics and Communication Engineering (IJECE) ISSN 2278-9901 Vol. 2, Issue 1, Feb 2013, 69-76

Haritaoglu, Ismail: A Global Routing Heuristic for FPGAs Based on Mean Field Annealing p12

Kallio, Janne and Finland, Arrow: Altera FPGA Seminar, 2008, p59 .

Khalid, Mohammed A. S. and Rose, Jonathan A Novel and Efficient Routing Architecture for Multi-FPGA Systems p17

Khalid, Mohammed A. S. : ROUTING ARCHITECTURE AND LAYOUT SYNTHESIS FOR MULTI-FPGA SYSTEMS p146

Kwon, Young-Su et al: A 3-D FPGA Wire Resource Prediction Model Validated using a 3-D Placement and Routing Tool, Sept 2005, p25

LEESER, MIRIAM et al: Rothko A Three-Dimensional FPGA p8

Lemieux, Guy G. and Brown, Stephen D. A: Detailed Routing Algorithm for Allocating Wire Segments in Field-Programmable Gate Arrays 1992 p12

Lin, Mingjie and El Gamal, Abbas: TORCH a design tool for routing channel segmentation in FPGAs p8

Ling, Andrew C.: Field-Programmable Gate Array Logic Synthesis Using Boolean Satisfiability p74 2005

Luu, Jason et al: VPR User’s Manual, VPR 6.0 Full Release, January 19, 2012, p38..

Madurawe, Raminda: 3D FPGA & 3D ASIC, Worlds first unified 3D IC design platform, Hot Chips, August 2010, p16..

Mak Channel segmentation design for Symmetrical FPGAs p6

Manimegalai R. et al: Placement and Routing for 3D-FPGAs using Reinforcement Learning and Support Vector Machines 2003 p6

Markovic, Dejan: EE216B: VLSI Signal Processing-FPGA Architecture, 5/16/2012, p24.

MASUD, MUHAMMAD IMRAN: FPGA ROUTING STRUCTURES: A NOVEL SWITCH BLOCK AND DEPOPULATED INTERCONNECT MATRIX ARCHITECTURES p80

McMurchie Guest Lecture Placement and Routing for FPGAs, March 2011, p27.

Mok FPGA Placement and Routing p17.pdf.

Nag, Sudip: Performance-Driven Simultaneous Placement and Routing for FPGAs, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 6, JUNE 1998, p 499-518 ......................2

Nam, Gi-Joon et al: Satisfiability-Based Layout Revisited Detailed Routing of Complex FPGAs Via Search-Based Boolean SAT p9, FPGA 99 Montery, CA USA

Nilangshu 3D Field Programmable Gate Arrays, April 2012, p47

OLUKOTUN 0. A. AND MUDGE, T. N.: Hierarchical Gate-Array Routing on a Hypercube Multiprocessor, JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 8,3 13-324 ( 1990), p12 ...............?? 3

Pangracious, Vinod and Mehrez, Habib: Designing 3D Tree-based FPGA: Interconnect Optimization And Thermal Analysis, New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International Paris France, 2013-10-15

Pedram p Design and analysis of segmented routing channels for row-based FPGAs 10

Platzner, Marco: CAD for PFGAs, Nov 2006, p36 ..................10

Roychowdhury,Vwani P. et al: Segmented channel routing p17 Jan 1993 ............................

SALCEDO-SANZ, SANCHO AND BOUSO?O-CALZóN, CARLOS : A Hybrid Neural-Genetic Algorithm for FPGA Segmented Channel Routing Problems 1998 p4

SALCEDO-SANZ, SANCHO et al: : Meta-Heuristic Algorithms for FPGA Segmented Channel Routing Problems with Non-standard Cost Functions, Genetic Programming and Evolvable Machines, 6, 359–379, 2005, p21.

Singh, Manpreet et al: Faster FPGA Routing Solution using DNA Computing, World Academy of Science, Engineering and Technology Vol:12 2007-12-24

Strukov, Dmitri B and Likharev, Konstantin K: CMOL FPGA a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices, Nanotechnology 16 (2005) 888–900, p25..

Texas A&M University: ECEN 449 – Microprocessor System Design, FPGAs and Reconfigurable Computing, February 2008, p47

Venugopal, Nagalakshmi: Survey on FPGA Routing Techniques p6, International Journal on Computer Science and Engineering (IJCSE), page 1304-1309, Vol. 4 No. 07 July 2012 .

WANG, Lipo and ZHANG, Wensong: Using Stochastic Chaotic Simulated Annealing in the FPGA Segmented Channel Routing Problem, IEEE Int. Workshop VLSI Design & Video Tech. Suzhou, China, May 28~30, 2005, p4

Wood, R. Glenn: FPGA Routing and Routability Estimation Via Boolean Satisfiability p10

Wu, Yu-Liang: Routing on Regular Segmented 2-D FPGAs July 1995 p6 .

Yang, Meng: An Investigation on FPGA Placement Using Mixed Genetic Algorithm with ? Simulated Annealing, p18 (ppt slides)

Yang, Meng: Algorithms in Computer Aided Design of VLSI Circuits p210, June 2006

Yu, Chi Wai et al:Routing Optimization For Hybrid FPGAs, 2009, p4..

Zhang, Chenxin: Introduction to FPGA designs p4 Sept 2010

Zhao, Qian et al: An FPGA Design And Implementation Framework Combined With Commercial VLSI CADs p21, ReCoSoC 2013

Zhao, Xin: FPGA Placement and Routing Algorithm A Survey, 2011, p8

Zhuo, Yue et al: A CONGESTION DRIVEN PLACEMENT ALGORITHM FOR FPGA SYNTHESIS p4, 2004


Silicon-based Integrated Optics – Silicon Photonics

Generals

Silicon photonics

Si-photonics integration

Silicon photonics technology

on-chip photonics integration

on-chip nano-photonic integration

CMOS Integrated Silicon Nanophotonics

Photonic CMOS

integrated optic design

INTEGRATED OPTICAL PROCESSOR

photonic devices

optical devices

Integrated Optic Devices: Integrated optical devices transmit and route light using optical waveguides, which are created as guiding layers on the substrate using lithographic and deposition methods.

silicon nano-photonic devices

photonic networks-on-chips

Photonic Networkon-Chip architecture on SOI

holistic photonic Networks-on-Chip architecture

Photonic Chip

programmable quantum photonic chip

WDM (Wavelength Division Multiplex) On-Chip

optoelectronic IC (OEIC)

光子芯片

Google??? 1

硅光子芯片

硅基光子芯片

纳米线激光电脑芯片

用光束制造可擦写的电脑芯片的技术

能够用一束光重写并且改变电路图形，能够制造不同的电路以适应不同的需求

VLSI photonics applications

photonic waveguides

integrated optical waveguides

integrated waveguide systems

On-Chip Optical Waveguide

Si Photonic Wire Waveguide Devices

the open foundary initiatives and developmental programs such as the OPSIS framework

Logic Design and Synthesis

optical digital logic

electro-optic circuit synthesis

the use of optical switching devices for logic design and synthesis.

the use of conventional routing devices, specifically optical crossbar routing devices, as the building block for logic design

Optical logic design using crossbar routing devices

LOGIC DESIGN WITH VIRTUAL GATES

Logic Synthesis for Integrated Optics

Circuits

electro-optic circuit

integrated optical circuits

photonic integrated circuits (PICs)

Optical Integrated Circuits

Planar light wave circuits

Microring Resonator

Physical Design

physical design of integrated optical circuits

Routing

The primary optimization objective in our routing formulation is the minimization of the total number of waveguide crossings within the channel.

optical/photonic interconnect

on-chip interconnect technology

On-chip nano-photonic interconnect

Nano-photonics Optical Interconnect Library

carbon nano-tube bundle interconnection

Photonic switching and routing platform

on-chip packet routing (photonic Network-on- Chip)

Core-to-Core Network/Packet Routing

optical netlist mapping/routing

optical routing

Optical Channel Routing

planar channel routing

waveguide routing

photonic waveguide routing

insertion losses of planar waveguide crossings

the waveguide routing problem can be formulated as planar channel routing

automated, planar channel routing technique for integrated optical waveguides

CROSSING-AWARE CHANNEL ROUTING FOR PHOTONIC WAVEGUIDES

waveguide crossing constraints

with-in core wire routing (photonic waveguide routing)

Grid-Less Single-Layer Routing with Couplings within-core optical waveguide routing

vertical routing channels

horizontal routing channels

left-edge style channel routers

constrained left-edge channel routing

QCA routing

doglegging

YK = Yoshimura-Kuh router

optical cross-bar routing devices based on Mach-Zehnder Interferometry

Knock-knee track sharing

no signal sharing (fanout)

two-terminal net

left-edge-style track assignment

signal loss

channel height
Channel Routing for Integrated Optics

CROSSING-AWARE CHANNEL ROUTING? 2013

CROSSING-AWARE CHANNEL ROUTING FOR PHOTONIC WAVEGUIDES

Silicon photonics technology is progressing at a rapid pace. Despite greatly expanded manufacturing capability, physical design of integrated optical circuits currently lacks the level of automation found in VLSI design. A key component of integrated optic design is waveguide routing; however, unlike VLSI, where signal nets are routed with metal layers and vias, photonic waveguides are fabricated in planar substrates. For many applications, our studies show that the waveguide routing problem can be formulated as planar channel routing. Signal losses become a major factor due to the insertion losses of planar waveguide crossings. Channel routing must therefore take into account these losses. This paper investigates methods for adapting traditional VLSI channel routing techniques for integrated optics — specifically, a technique based on left-edge-style track assignment. We show how incorporating waveguide crossing constraints into the underlying constraint model affects the routing solution, and describe the necessary modifications and extensions to the routing technique to properly exploit optical technology. We implement the channel router, describe the experimental results, and compare the cost of solutions with respect to waveguide crossings, corresponding to signal loss, and channel height.

A key difference between traditional semiconductor routing and optical waveguide routing is in the planar nature of the optical substrate, permitting no transitions to other layers using vias.

The primary optimization objective in our routing formulation is the minimization of the total number of waveguide crossings within the channel. Though channel height minimization is the goal of traditional VLSI channel routers, signal loss is more important for optical applications; therefore channel height reduction is the secondary objective of this technique.

Artundo Basic silicon photonic building blocks for commercial applications p4

Bergman Photonic Networks for Intra-Chip Inter-Chip and Box Interconnects in High-Performance Computing p71

Condrat, Christopher: Channel Routing for Integrated Optics, May 2013

Condrat, Christopher; Kalla, Priyank and Blair, Steve: CROSSING-AWARE CHANNEL ROUTING FOR PHOTONIC WAVEGUIDES, April 2013, p4 ???????????????

Condrat, Christopher et al: Logic Synthesis for Integrated Optics, 2011 ACM 978-1-4503-0667-6/11/05, p6

Ding, Duo and Pan, David Z.: OIL A Nano-photonics Optical Interconnect Library for a New Photonic Networks-on-Chip Architecture, SLIP’09, July 26-27, 2009, San Francisco, California, USA. 2009 ACM 978-1-60558-576-5/09/07, p8

ESPROS epc OHC15L ESPROS Photonic CMOS Process, Overview, Options & Services Version 1.2, p15

Hofrichter, J.: Silicon Photonics … and how to actually make use of it in larger systems p16

Kaminow, Ivan P.: Optical Integrated Circuits A Personal Perspective p11, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 26, NO. 9, MAY 1, 2008

Knights, Andrew P. and Doylend, J. K.: Chapter 30 Silicon Photonics Recent Advances in Device Development p24

Mashanovich, G Z et al: Silicon photonic waveguides for different wavelength regions p9

Reed, Graham T.: SILICON PHOTONICS THE STATE OF THE ART p36

Ring Silicon Photonics Challenges and Future An OIDA Forum Report p92

Scherer Photonic crystals silicon photonics Luxtera the future p60

Sloper, D.K.: INTEGRATED OPTICAL PROCESSOR, October 1997 p85

Yamada,Hirohito et al: Si Photonic Wire Waveguide Devices p9, IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 12, NO. 6, NOVEMBER/DECEMBER 2006

Zhang, Ziyang: Silicon-based Photonic Devices Design, Fabrication and Characterization p66

Zuffada, Maurizio: Low Cost Silicon Photonics Technology Platform Plans, Perspectives and Roadmap p16


Reconfigurable Computing

Graph Literature

graph theory for

reconfigurable architectures

reconfigurable computing

parallel
Pipelined Architectures
3d

fpga

reconfigurable
[Abbas2015] PRINCE IP-core on Field Programmable Gate Arrays (FPGA) p9
simulation graph

M. Ade, R. Lauwereins, and J. A. Peperstraete, “Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets,” in Proceedings of the Design Automation Conference, 1994, pp. 64--69.

[Aggarwal2009] Bridging Parallel and Reconfigurable Computing with Multilevel PGAS and SHMEM p8
Ahmad Efficient Reconfigurable Architectures for 3-D Medical Image Compression p207
[Akoglu2002] Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing p8

data/control flow graphs

data flow graphs

control flow graphs

dynamically reconfigurable multimedia processor
[Al-Wattar2015] Efficient Scheduling,Mapping and Resource Prediction for Dynamic Run time Operating Systems p272

Data Graph

Data Flow Graph (DFG)

task graphs

task placement graph
[ALAOUI ISMAILI2009] Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA p8
[Aloisio(2008] High-Resolution Time-to-Digital Converter in Field Programmable Gate Array p5
[Alsolaim2002] DYNAMICALLY RECONFIGURABLE ARCHITECTURE FOR THIRD GENERATION MOBILE SYSTEMS p327
[Altera2008] FPGA Run-Time Reconfiguration Two Approaches p6
Altera FPGAs Provide Reconfigurable DSP Solutions p6
Amarnath A Self-Configurable Architecture on an Irregular Reconfigurable Fabric p93
XXXXXXXXXX
[Andrade1998] Software Synthesis from Dataflow Models for G and LabVIEW p5
[Andreas2010] Mapping Framework for Heterogeneous Reconfigurable Architectures p127

architecture graph

data flow graph

Control Data Flow Graph (CDFG)

Synchronous Data Flow (SDF) graphs

dependency graph

directed acyclic precedence graph

task graph

[Attia2014] CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search p8
De Bruijn graphs
[Azarian2009] Reconfigurable Computing Architecture Survey and introduction p5
???????????????
J. Babb, M. Frank, and A. Agarwal, \Solving graph problems with dynamic computation structures," SPIE Photonics East: Recon gurable Technology for Rapid Product Development and
Computing, November 1996.
[Babst2005] Practical Reconfigurable Computing p42
??????????????
[Banerjee2009] Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198

adjacency graph

cone adjacency graph

architecture graph

flow graph

network flow graph

netlist graph

Block netlist graph

adjacent subgraph

distance digraph

Rectangular dual graph

hypergraph

Netlist hypergraph

graph embedding

hypergraph partitioner

decomposition tree of a graph
??????????????
BANERJEE FPGA Placement using Space Filling Curves Theory Meets Practice p21
Benkrid High Performance Reconfigurable Computing: From Applications to Hardware p8
[Bhatia2004] Reconfigurable Computing p85

Directed Acyclic Data Flow Graph
[Bhatia2002] Reconfigurable Computing p185

Data Flow Graph

Directed Acyclic Data Flow Graph (DAG)

Program Dependency Graph
?????????????????????
Bhattacharyya Dynamic Dataflow Graphs p40

[Bha92a]? S. S. Bhattacharyya and E. A. Lee, ?Scheduling Synchronous Dataflow Graphs for Efficient Looping,? Journal of VLSI Signal Processing, 1992.
?????????????

[9] S. S. Bhattacharyya, P. K. Murthy, E. A. Lee. Software Synthesis from Dataflow Graphs (Synchronous Dataflow chapter), Kluwer Academic, 1996.
[Bhattacharyya2011] Software Synthesis from Dataflow Graphs p49
Shuvra S. Bhattacharyya
with contributions from William Plishker, Chung-Ching Shen and Hsiang-Huang Wu
Maryland DSPCAD Research Group
http://www.ece.umd.edu/DSPCAD/home/dspcad.htm
Department of Electrical and Computer Engineering, and
Institute for Advanced Computer Studies,
University of Maryland, College Park, MD

[Bhattacharyya2001] Software Synthesis Trade-offs in Dataflow Representations of DSP Applications p26

signal flow graphs

dataflow graph

stream flow graphs

processing graph

single-rate graphs
[Bittner1996] Colt: An Experiment in Wormhole Run-Time Reconfiguration p8

Wormhole Run-Time Reconfiguration (RTR)

By directly connecting functional units and guaranteeing that only one operand exists on an arc at a given time, the
implemented data flow graph is reduced to a set of interacting pipelines.

The hardware for such a system should consist of flexible functional units with fairly diverse interconnection abilities to allow subsections, or chunks, of the data flow graph to be directly mapped onto the system and to facilitate rapid swapping of chunks with little overhead to the active computation.

While this could have been accomplished using a classic mesh architecture, the run-time reconfiguration of data flow graphs should benefit from the added connectivity present in the Colt.

The Von Neumann-like configuration/execution cycle would continue until the final outputs from the data flow graph have been computed.

mesh topology
[Bobda2003] Synthesis of Dataflow Graphs for Reconfigurable Systems using Temporal Partitioning and Temporal Placement p90

Cluster Graph

configuration graph

data flow graph

distribution graph

interval graphs

network graph

partition graph

precedence graph

complete precedence graph

dynamic precedence graphs

task graph

dynamic task graphs

visibility graph

graph connectivity
????????????????
[17] C. Bobda. Temporal partitioning and sequencing of dataflow graphs on reconfigurable systems.
In International IFIP TC10 Stream on Distributed and Parallel Embedded Systems (DIPES 2002),
pages 185–194, Montreal, Canada, 2002. IFIP.
[Bollman2007] SCALABLE COMPUTING Practice and Experience p127

data flow graph

macro data flow graphs

global macro data flow graph

Control Flow Graphs
[Bondalapati1996] Reconfigurable Computing Systems p12

task graph
[Boschetti2004] A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications p6
data flow graph
[Boysen1998] A development environment for configurable computing p10

To address these issues, we use a technology independent description of a user design which contains all pertinent
information about the algorithm in a data flow graph.

The nodes in the data flow graph represent abstract operations in the design and are created by agents in the front
end. A set of analysis agents activated by the user refines and enhances the data flow graph by adding parameters
which constrain the final implementation. In the final step, back-end agents map the design to components.

CECAAD provides support for the agent collaboration model, as well as a common format for describing the dataflow graphs which represent the design. The format used is the Algorithm Description Format (ADF). The fundamental unit of the ADF is the Design Unit(DU), which represents a single graph. The vertices in the graph are called nodes, and each node contains a number of input and output ports. The edges in the graph are known as links and connect the ports. Each node and port in the system as well as the DU itself contains a list of attributes. Support for hierarchy is provided in ADF by placing an attribute on a node which references to another DU. Since DUs are implemented as object-oriented structures, the interface they present to the user keeps the graph in a consistent state.
[Brebner2011] Reconfigurable Computing for High Performance Networking Applications p30
[Brenner2005] Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures p72

dataflow graph

pattern graph

Subgraph Homeomorphism
[Brodie2006] Dynamic Reconfigurable Computing p8

[Buc93]?? J. T. Buck, ?Scheduling Dynamic Dataflow Graphs With Bounded Memory Using the Token Flow Model,? Memo. No. UCB/ERL M93/69 (Ph.D. Dissertation), EECS Dept., University of California, Berkeley, 1993
[Campi2011] Run-Time Reconfigurable Processors p47
Data Flow Graph
[Cardoso2005] ARC2005 INTERNATIONAL WORKSHOP ON APPLIED RECONFIGURABLE COMPUTING 2005 p190

small-world graph

ring graph

random graph

data flow graph

Hierarchical dataflow Graph

reconfiguration transition graph (RTG)

state transition graph

graph visualization
[Carroll2007] Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency p11

dataflow graph

datapath graph
[Chakrabarti2012] Crypto Hardware Design for Embedded Applications p56
[ChenJW2005] A Reconfigurable Architecture for Load-Balanced Rendering p11

stream graph
??????????????????
Chen FPGA Design Automation A Survey p137
[Chen2006] FPGA design automation a survey p151

interconnected component graph

control dataflow graph

expansion graph

netlist graph

routing-resource graph

coarse routing-resource graph

detailed routing-resource graph

routing graph

near-optimal Steiner tree

sub-graph isomorphism

graph embedding

mapping graph

graph matching

hypergraph clustering

data flow graph

The problem is formulated as follows: given (1) a data flow graph (DFG), (2) maximum allowable clock period and
execution time, which are usually part of the system specification, and (3) component power/performance tradeoff functions due to different implementations, identify whether there is a feasible RTL datapath solution or not.
[CHENLiang2014] Graph Minor Approach for Application Mapping on CGRAs p22

data flow graph

meeting graph

resource graph

routing resource graph

modulo routing resource graph

schedule and route graph (SRG)

Graph Minor

graph epimorphism

subgraph epimorphism

subgraph homeomorphism

subgraph isomorphism
[Cheng2007] Reconfigurable Computing p16

dataflow graph

folded edge coloring graph

replication graph
???????????????
Cheung Reconfigurable Elliptic Curve Cryptosystems on a Chip p7
[Cho2008] Diastolic Arrays: Throughput-Driven Reconfigurable Computing p8

recursive graph partitioning

????????????????????
[Choi1998] Software Synthesis for Dynamic Data Flow Graph p46

Dynamic Data Flow Graph

Data flow graph

Synchronous Data Flow (SDF) graph

program graph

multi-rate graph
[Ciricescu2003] The Reconfigurable Streaming Vector Processor (RSVPTM) p10

Programming the RSVP architecture involves describing the shape and location of vector streams in memory and
describing computations as data-flow graphs.

The data-flow graph describes a set of ordered, dependent computations applied to each element in the vector.

Deep pipelining is possible because instructions in the vector loop are treated as a data-flow graph of interconnected stream and function units.

The RSVP architecture does provide a mux-like select operation for simple predicated execution of dataflow graphs.

Programming the RSVP architecture consists of describing the input and output vectors and scalar values for a particular computation, and describing the computation itself as a data-flow graph.

Describing Computation Using Dataflow Graphs

linear data-flow graph

The natural choice was Synchronous Data-flow (SDF) graphs [1] with DMA-like sources and sinks.

graph compilation
??????????/
[23] N. Clark, H. Zhong, and S. Mahlke, “Automated custom instruction generation for domain-specific processor acceleration.” IEEE Transactions on Computers, vol. 54, no. 10, pp. 1258–1271, 2005.
????????????????
J. A. Clemente, C. Gonzlez, J. Resano, and D. Mozos, “A task graph execution manager for reconfigurable multi-tasking systems,” Microprocessors and Microsystems, vol. 34, no. 2-4, pp. 73–83, 6 2010.
[Compton2003] An Introduction to Reconfigurable Computing p9
[Compton1999] Programming Architectures For Run-Time Reconfigurable Systems p34
[COMPTON1999] Reconfigurable Computing: A Survey of Systems and Software p39
[COMPTON2002] Reconfigurable Computing: A Survey of Systems and Software p40

control flow graph

dataflow graph

dynamic graphs

Cooper K, Harvey T, and Waterman T (2002) Building a Control-Flow Graph from Scheduled Assembly Code. Technical Report 02-399. Department of Computer Science, Rice University, Houston, TX.
[Coughlan2007] Introduction to Programmable Logic p28
[Cre?2003] The CREC Reconfigurable Computer p15
execution graph
[CURRERI2008] Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing p19

control-flow graph

state machine graph

data-flow graph
????????????????
A. Dandalis, A. Mei, and V. K. Prasanna, \Domain Speci c Mapping for Solving Graph Problems on Recon gurable De- vices," in Recon gurable Architectures Workshop, April 1999.
Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166
[DeHon1996] Reconfigurable Architectures for General-Purpose Computing p368

computational graph

state graph

state transition graph

task description graph
[DeHon1999] Reconfigurable Computing What Why and Implications for Design Automation p6
?????????????
Delgado-Frias A MEDIUM-GRAIN RECONFIGURABLE CELL ARRAY FOR DSP p6
[Densmore2004] Platform Based Reconfigurable Architecture Exploration via Boolean Constraints p 81

task graph

Task Communication Graph
[Densmore2003] Reconfigurable Architectures Overview and Commercial Examples p57
[Diessel2008] Operating Systems Support for Dynamically Reconfigurable Architectures p12

combinational task graph
[Dittmann2007] Exploration partitioning and simulation of reconfigurable systems p8

process graph

specification graph

architecture graph

hierachichal architecture graph

dataflow graph
[Dittmann2007a] Methods to Exploit Reconfigurable Fabrics Making Reconfigurable Systems Mature p211

data flow graph

homogeneous dataflow graph

Architecture Graph

Task dependence graph

universal directed task dependence graph

interval graphs

Specification Graph

spectral graph

task graph

graph coloring
[DORDOPULO2013] Reconfigurable computer systems for digital image processing p6

information graph

task graph
Drutarovsky CUSTOM FPGA CRYPTOGRAPHIC BLOCKS FOR RECONFIGURABLE EMBEDDED NIOS PROCESSOR p7
[Duarte2005] Reconfigurable Computing: A Survey of Architectures and Synthesis Tools p45

data flow graph

data-dependence and control-flow graph
[Dubach2005] Java Byte Code Synthesis for Reconfigurable Computing Platforms p71

compatibility graph

strong compatibility graph

Control Flow Graph

data flow graph

World dependency graph

Sequencing graph

graph package

graph partitioning
[Dutt1999] Efficient Incremental Rerouting for Fault Reconfiguration in Field Programmable Gate Arrays p4

overlap graph

transition graph
[Eguro2003] Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development p10
[Ernst2001] A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF p18
[Ersfolk2014] Scheduling Dynamic Dataflow Graphs with Model Checking p225

computation graphs

data flow graph

CSDF Cyclo-dynamic data flowgraph

Dynamic Data flow Graph

static data flow graphs

SDF graph

dependency graph

Variable Dependency Graph

precedence graph

acyclic precedence graph

coupling relationship graph
[ESHAGHIAN-WILNER2003] The Systolic Reconfigurable Mesh p14
[Filho2010] Description and Specialization of Coarse-grained Reconfigurable Architectures p182

conflict graph

data flow graphs (DFGs)

incompatibility graph

instruction pattern graph

operation cluster graph

graph isomorphism

binary search tree
[Fukushi2000] Self-Reconfigurable Mesh Array System on FPGA p9

K.M. Gajjala Purna, aTemporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers,o Master's thesis, Dept. of Electrical and Computer Eng. and Computer Science, Univ. of Cincinnati, Oct. 1998.
[Galuzzi2004] Graph Theory and Application Specific Processors p7

dataflow graph

search tree
Ghazawi Parallel Programming of High-Performance Reconfigurable Computing Systems with Unified Parallel C p7
[Giani2007] Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity p7

Control and Data Flow Graph (CDFG)

data-flow graphs

Hierarchical Template Graph

Super Data Flow Graph (SDFG)
[Goldstein2003] Reconfigurable Computing and Electronic Nanotechnology p12

program call-graph

control-flow graph

dataflow graph

The next compilation phase stitches the hyperblocks together into a dataflow graph representing the whole procedure by creating dataflow edges connecting each hyperblock to its successors.

Registers Each operation in the dataflow graph has an associated register on its output.
!!!!!!!!!!!!!!!!!!!!!!!!
[Gomez-Prado2008] Optimizing Data Flow Graphs to Minimize Hardware Implementation p6

Data Flow Graph

TED graph
[Gong2007] Synthesizing Sequential Programs onto Reconfigurable Computing Systems p237

constraint graph

control flow graphs

control/data-flow graph

dependence graphs

program dependence graph

system dependence graph

value dependence graph

distribution graphs

dependence flow graph

demand-interpretable program graphs

control dependence subgraph

data dependence subgraph

graph-bisection

graph coloring

breadth-first graph transverses

syntax trees
ZZZZZZZZZ
[Gotz2007] Runtime reconfigurable rtos for reconfigurable system on chip p180

Runtime reconfigurable rtos

reconfigurable system on chip

task graph

partition

[Govindarajan2000] ALGORITHMS FOR DESIGN SPACE EXPLORATION AND HIGH-LEVEL SYNTHESIS FOR MULTI-FPGA RECONFIGURABLE COMPUTERS p216

Sriram Govindarajan

SANTOSH PANDE

CARLA PURDY

HAROLD CARTER

JOHN HINES

RANGA VEMURI

93

application graph

behavioral graph

Block Graph

Block Compatibility Graph

compatibility graph

Control Data Flow Graph (CDFG)

control-flow block graph

Data Flow Graph (DFG)

dependency graph

distribution graph

global compatilibilty graph

resource distribution graphs

flow graph (FG)

GUB graph

operation graph

task graph

depth of the graph (critical path length)

graph density

graph isomorphism

Clique Partitioning

graph-bisection

Graph Partitioning

subgraph pattern matching

DESIGN SPACE EXPLORATION

HIGH-LEVEL SYNTHESIS

MULTI-FPGA RECONFIGURABLE COMPUTERS
[Gray2002] Object-Oriented Reconfigurable Processing for Wireless Networks p5
control flow graph
[Grudnitsky2012] Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures p6

dataflow graphs
Guccione Reconfigurable Computing p22
Guneysu CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES p213
[Guo2002] Programmability and Efficiency in Reconfigurable Computer Systems p7

SA-C programs are compiled to FPGA configurations (via Data Flow Graphs), plus a C program that manages the FPGA in terms of downloading the configuration and data, triggering the FPGA, and uploading the results

[Ha92]???? S. Ha, ?Compile-Time Scheduling and Assignment of Dataflow Program Graphs with Dynamic Constructs,? Memo. No. UCB/ERL M92/43 (Ph.D. Dissertation), University of California, Berkeley, April 1992.

[Halstead2014] Compiling irregular applications for reconfigurable systems p11

data flow graph

control flow graph

graph traversal
[Hannig2004] REGULAR MAPPING FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURES p4
dataflow graph
Harb A Reconfigurable Platform Architecture for an Automotive Multiple-Target Tracking System p5

[Hauck2008] Reconfigurable Computing The Theory and Practice of FPGA-Based Computation p945

directed channel graph

circuit graph

communication graphs

computational graph

computation graph

compute graph

control flow graph

dataflow graph

data dependence graph

dependency graph

flow graph

implication graph

transitive implication graph

log–log graph

operator graph

dataflow operator graphs

hierarchical operator graphs

routing resource graph

transformation graph

Graph bipartitioning

graph covering

graph transformation

adder tree

explicit adder tree

binary tree

dataflow trees

minimum-cost and minimum-delay trees

operator trees

spatial orientation trees

critical path trees

routing tree

minimum spanning tree

forest of trees

tree-covering approach

recursive tree search
[Hauck1998] The Future of Reconfigurable Systems p7
[Havinga2001] Energy Management for Dynamically Reconfigurable Heterogeneous Mobile Systems p13
Process graph
[Hendriks2012] High Level Synthesis: Performance Analysis and Code Optimization p105

control and data ow graph (CDFG)

logic distribution graph

hierarchical task graph

graph traversal
[HSU2014] Hybrid LUT and SOP Reconfigurable Architecture p20
????????????????
M. Huang, V. K. Narayana, M. Bakhouya, J. Gaber, and T. El-Ghazawi, “Efficient mapping of task graphs onto reconfigurable hardware using architectural variants,” Computers, IEEE Transactions on, vol. 61, no. 9, pp. 1354–1360, 2012.
[Hudson2000] Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines p97

dataflow graph

computational dataflow graph

graph description language
[Huynh2007] An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization p23

data flow graph

reconfiguration cost graph

task graphs

graph partitioning
[Ihrig2008] Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric p30
[Iqbal2013] Performance Oriented Design Perspectives of Run-Time Reconfigurable Computing Systems p10

abstract data-flow and control-flow graphs
J?rvinen Elliptic curve cryptography on FPGAs How fast can we go with a single chip p87
[Jijina2014] Low Power Architecture for Reconfigurable Fir Filter for SDR p5

Adder Graph

Minimised Adder Graph

minimum adder graph
[Jose2015] Compiling Packet Programs to Reconfigurable Switches p14

Table Dependency Graph

parse graph
[Karkooti2003] Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding p7
Tanner graph
????????????
Karthikeya M. Gajjala Purna and Dinesh Bhatia. Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. on Computers, 48(6):579–590, June 1999.
[Kastner2002] Synthesis Techniques and Optimizations for Reconfigurable Systems p152

compatibility graph

resource compatibility graph

conflict graph

control data flow graph (CDFG)

control flow graphs

data flow graph

SDF graphs

synchronous data flow graphs

interval graph

sequence graph

hierarchical sequence graph

graph isomorphism

Gemini graph isomorphism

Quick Rejection Graph Isomorphism

subgraphs isomorphic

digraph

hypergraphs.

graph clustering

graph coloring

covering of the graph

decompose

matching of a graph

graph profiling
[Kastrup1999] Seeking (the right) Problems for the Solutions of Reconfigurable Computing p6
Kindratenko High-Performance Reconfigurable Computing Application Programming in C p33
[Kirasic2012] Reconfigurable Processor Architectures Varieties and Representations p6

datapath graph

Modulo Routing Resource Graph (MRRG)
[Koch2001] Architectures and Tools for Heterogeneous Reconfigurable Systems p2
Dataflow Graph

[Koch2009] Architectures, Methods, and Tools for Distributed Run-time Reconfigurable FPGA-based Systems p295

18

reconfigurable computing

runtime reconfiguration

reconfiguring the hardware and software of a system autonomously at runtime

runtime reconfigurable systems on FPGAs

Self-adaptive Reconfigurable Networks

p18-20

architecture graph

task graph

B-tree

clock tree

decoder tree

Huffman tree
[Koh2006] MODULE GRAPH MERGING AND PLACEMENT TO REDUCE RECONFIGURATION OVERHEADS IN PAGED FPGA DEVICES p6

communications graphs

MODULE GRAPH

task graph

graph merging

Mapping
[KOONAR2004] A RECONFIGURABLE HARDWARE IMPLEMENTATION OF GENETIC ALGORITHMS FOR VLSI CAD DESIGN p173

hypergraph

undirected hypergraph

Hypergraph Partitioning
[Kumar2013] An Automated High-level Design Framework for Partially Reconfigurable FPGAs p6

control flow graph (CFG)

task graph
??????????????????
[Kuon2007] FPGA Architecture Survey and Challenges p119

graph-matching
??????????????????
Lamoureux Modeling and Reduction of Dynamic Power in Field-Programmable Gate Arrays p148
[Lee91]??? E. A. Lee, ?Consistency in Dataflow Graphs,? IEEE Transactions on Parallel and Distributed Systems, Vol. 2, No. 2, April 1991.
[Lechner1997] The Java Environment for Reconfigurable Computing p10
[Lehn1999] Framework for architecture-independent run-time reconfigurable applications p11

dataflow and control graphs

task graph

In either case, automated spatial partitioning of designs for FPGAs is a NP-complete problem whose heuristic solutions are extremely sensitive to the topology of the computational dataflow graph and the target CCM20.
[Lenart2008] Design of Reconfigurable Hardware Architectures for Real-time Applications Modeling and Implementation p195

data-flow graph

flow graph
[Levin2015] FPGA-based Reconfigurable Computer Systems for digital image processing p6
information graph
[Li2005] Power Modeling and Characteristics of Field Programmable Gate Arrays p13

timing graph
[Liang2009] SmartCell: An Energy Efficient Reconfigurable Architecture for Stream Processing p130

buffer dependency graph

channel dependency graph
[Lin2009] A Low-Power Field-Programmable Gate Array Routing Fabric p14
routing graph
[Lodi2003] A VLIW Processor With Reconfigurable Instruction Set for Embedded Applications p11

data flow graph
[Lodi2004] Reconfigurable Architectures p50

Data Flow Graph
[Louri1989] An Optical Data -Flow Computer p12

data-flow graph

graph mapping
[Maache2011] A Prototype Parallel Multi-FPGA Accelerator for SPICE CMOS Model Evaluation p207

Behavioural Block graph

control- flow block graph

Module Call Graphs

circuit graph

compute graphs

Control and Data Flow Graphs

Control Data Flow Graph (CDFG)

random graph

Hypergraph

graph decomposition

graph partitioning

Data Flow Graphs
[Maestre2001] A Framework for Reconfigurable Computing: Task Scheduling and Context Management p16

task graph

Block dependency graph

data flow graphs

This information includes kernel execution time, data reuse among kernels, data size, data dependencies
(as data flow graphs) and context size of each kernel.

The target applications of this work are usually described by a data flow graph with loops, whose nodes are kernels.

Each edge of the DFG (data flow graph) is numbered in ascending order according to the amount of data reuse between the kernels connected by that edge [Fig. 6(a)].
[Markovskiy2004] Quasi-Static Scheduling for SCORE p115

cluster graph

computation graphs

compute graphs

dynamic dataflow graphs

SDF graph

scalable synchronous dataflow (SSDF) graphs

HDF graph

virtual page graph

SCORE graphs

virtual graph

graph topology

partitioning of compute graphs

transforms a graph

graph traversal
[Masselos2005] SYSTEM LEVEL ARCHITECTURE EXPLORATION FOR RECONFIGURABLE SYSTEMS ON CHIP p6

Control-Data Flow Graphs (CDFG)
[MASUD1998] FPGA ROUTING STRUCTURES A NOVEL SWITCH BLOCK AND DEPOPULATED INTERCONNECT MATRIX ARCHITECTURES p80
???????????????/
[Maxfield2004] The Design Warriors Guide to FPGAs p560
[McMahon2006] High Performance Reconfigurable Computing for Science and Engineering Applications p135

data dependency graph
???????????????
[Meyer2007] -Baese Digital Signal Processing with FPGAs 3rd Edition p795

Multiplier Adder Graph

reduced adder graph (RAG)

flow graph

signal flow graphs

graph transposition
???????????

MILLER Embedding-Based Placement of Processing element Networks on FPGAs for Physical Model Simulation p17

[MILLER2014] Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation p22

equation dependency graph

structured virtual processing element (PE) graph

hypergraph

graph drawing

graph embedding

graph folding
[Miramond2007] Design Space Exploration for Dynamically Reconfigurable Architectures p7

data flow graphs

precedence graph

search graph

task graph

graph partitioning
Miramond Design Space Exploration for Dynamically Reconfigurable Architectures p7
[Montone2011] Floorplacement for Partial Reconfigurable FPGA-Based Systems p13

horizontal constraint graph

Task graphs

scheduled task graph

three-dimensional transitive closure graph
[Mucci2006] Software tools for embedded reconfigurable peocessors p243

data flow graph

pipelined data flow graph

[Myjak2003] A TWO-LEVEL RECONFIGURABLE ARCHITECTURE FOR DIGITAL SIGNAL PROCESSING p7
[Najjar2003] High-Level Language Abstraction for Reconfigurable Computing p7

Architecture graphs

data dependence and control-flow graph

dataflow graph

Hierarchical dataflow graphs
Nane IP-XACT Extensions for Reconfigurable Computing p4
[NICHOLS2004] A RECONFIGURABLE COMPUTING ARCHITECTURE FOR IMPLEMENTING ARTIFICIAL NEURAL NETWORKS ON FPGA p235
[Niu2012] EXPLOITING RUN-TIME RECONFIGURATION IN STENCIL COMPUTATION p8
data flow graphs
[Niu2013] Rapid FPGA-based Delay Estimation for the HardwareSoftware Partitioning p8

data flow graph
[Noguera2002] HW/SW Codesign Techniques for Dynamically Reconfigurable Architectures p17

task graph
?????????????
Oh Rate Optimal VLSI Design from Data Flow Graph p4
??????????????
[Olson1995] Programming a Pipelined Image Processor p41

computation graph

dataflow graph

coarse-grained dataflow graphs

image processing graphs

VEIL graphs

graph-coloring

mapping

graph partitions
[OMONDI2006] FPGA Implementations of Neural Networks p363

connection graph

complex connection graph

dependency graph

FPNA graph

neural graph

parameterized task graphs

Partition
????????????
Ostadzadeh Parallelism Utilization in Embedded Reconfigurable Computing Systems A Survey of Recent Trends p11
??????????????
OMONDI FPGA Implementations of Neural Networks p363
[Panella2008] A Design Workflow for Dynamically Reconfigurable Multi-FPGA Systems p7
directed task-graph
[PANDYA2005] A HANDEL-C IMPLEMENTATION OF THE BACK-PROPAGATION ALGORITHM ON FIELD PROGRAMMABLE GATE ARRAYS p218

Architecture graph

Convergence Graph
[Parithy2014] ADVANCED TOOLS IN RECONFIGURABLE COMPUTING p6
Park Modulo Graph Embedding Mapping Applications onto Coarse Grained Reconfigurable Architectures p11
[Park2006] Modulo Graph Embedding: Mapping Applications onto CoarseGrained Reconfigurable Architectures p11

Affinity Graph

dataflow graph

modulo routing resource graph (MRRG)

Modulo Graph Embedding
[Paulino2011] Generation of Reconfigurable Circuits from Machine Code p125

atomic graphs

Control and Data Flow Graph

Control Flow Graph

Data flow Graph

non-atomic graphs

Graph Memory Addresses

graph detection

graph discovery

Graph Extractor

dynamic graph discovery

mapping of graphs

Graph Matching

transform
?????????????????
Pelkonen System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC p8
[Petersen1995] An assessment of the suitability of reconfigurable systems for digital signal processing p149
flow graph
Pillement DART A Functional-Level Reconfigurable Architecture for High Energy Efficiency p15
[Pillement2008] DART A Functional-Level Reconfigurable Architecture for High Energy Efficiency p13

control and dataflow graph (CDFG)

dataflow graph (DFG)
[POON2002] A Detailed Power Model for Field Programmable Gate Arrays p28
routing resource graph
[Popescu2010] More exotic processor approaches p16
[Pottier2007] AN INTEGRATED PLATFORM FOR HETEROGENEOUS RECONFIGURABLE COMPUTING p10

Control Data Flow Graph (CDFG)

application process graphs

computation graph

computational graph

operation sub-graphs

embed graph

graph mapping
???????????????????/

[37] K. M. G. Purna and D. Bhatia, “Temporal partitioning and scheduling data flow graphs for reconfigurable computers,” Transactions on Computers, vol. 48, no. 6, pp. 579–590, June 1999.
[Purna1999] Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers p12

Data Flow Graph

acyclic data flow graph

flow graph

PARTITIONING
[Raffin2010] Scheduling Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture p8

The contribution presented in [10] is particularly in line with our work because an ILP formulation for solving optimally and simultaneously the mapping, routing and scheduling of a given data flow graph on a coarse-grain architecture is presented.

To our knowledge, this is the first paper addressing the problem of solving simultaneously binding, routing and scheduling a data flow graph for the run-time reconfigurable operator based embedded architecture using CP.

Table I presents results obtained for applications from different multimedia benchmarks. Some of these applications are composed of several non-connected data flow graphs.

application graph (AG)

Hierarchical Conditional Dependency Graphs (HCDGs)

graph transformations

graph optimizations
Reda EN2911X: Reconfigurable Computing Topic 00: Introduction p20
Sherief Reda
School of Engineering, Brown University
Field-Programmable Gate Arrays (FGPAs) are one example of reconfigurable devices
[Reda2012] EN2911X: Reconfigurable Computing Topic 03: Reconfigurable Computing Design Methodologies p93
Data flow graphs
??????????????????
F. Redaelli, M. D. Santambrogio, and S. O. Memik, “An ilp formulation for the task graph scheduling problem tailored to bi-dimensional reconfigurable architectures,” in Reconfigurable Computing and FPGAs, 2008. ReConFig ’08. International Conference on, 2008, pp. 97–102, iD: 1.
[Reiner2002] Coarse Grained Reconfigurable Architectures p28
????????????????????
R. Rinker et al., “An Automated Process for Compiling Dataflow Graphs into Hardware,” IEEE Trans. VLSI, Feb. 2001, pp. 130-139.
[Rinker1999] An Automated Process for Compiling Data flow Graphs into Reconfigurable Hardware p10

Data flow Graph

S. Ritz, M. Pankert, and H. Meyr, “Optimum Vectorization of Scalable Synchronous Dataflow Graphs,” in Proceedings of the International Conference on Application Specific Array Processors, 1993.
[Saidani2004] Self-Reconfigurable Robots Topodynamic p5

dynamic graphs

random graphs

graph topodynamic

Graph Topology

graph of automata

Sequence of Graphs
[Saleeba1998] A self reconfiguring computer system p321
interconnect graph
[Sanchez2007] Reconfigurable computing p48
[SANGIOVANNI-VINCENTELLI1993] Synthesis Methods for Field Programmable Gate Arrays p27

pattern graphs
[Saqib2004] A Compact and Efficient FPGA Implementation of DES Algorithm p20
[Sarrigeorgidis2003] Massively Parallel Wireless Reconfigurable Processor Architecture and Programming p8

computational graphs

Dependence Flow Graph

dependence graph (graph of computation tasks)
[Say2011] A reconfigurable computing platform for real time embedded applications p20

dependency graph

task dependency graph

task graph
[SAY2011a] A RECONFIGURABLE COMPUTING PLATFORM FOR REAL TIME EMBEDDED APPLICATIONS p154

dependency graph

task dependency graph

hardware task dependency graph

reduced task dependency graph

task graph

[Shafer2002] A Development Method for Reconfigurable Hardware Systems With Real-Time Wavelet Image Compression Application p8

[Shoup2004] Reconfigurable Systems New Tools and New Math p12

www.boundary.org
shoup@boundary.org

Richard Shoup
Boundary Institute
Los Altos, California, USA
shoup@boundary.org
[Sigdel2011] System-Level Design Space Exploration of Reconfigurable Architectures p223

architecture graph

process graph
[SILVA2010] A Dynamic Dataflow Architecture using Partial Reconfigurable Hardware as an option for Multiple Cores p16

control dataflow graph

dataflow graph

Dynamic Dataflow graph

data dependency graph

program graph

parallel program graph

[Silva2011] Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System p13

Dataflow Graph

Asynchronous Dataflow Graph

Fibonacci dataflow graph

Static Dataflow Graph

[SinghGK2014] Partitioning and Mapping of Computation Structure on a Coarse-Grained Reconfigurable Architecture p121

Cayley Graph

communication graph

Control-flow Graph

Data Flow Graph (DFG)

de Bruijn Graph

Isomorphic Graph

resource graph

complete graph topology

graph embedding

graph mapping

graph partitioning

Graph Traversal

Cayley Tree

intermediate mapping tree
[SinghG2013] Reconfigurable Computing A review of the technology and its architecture p7
????????????
Silva Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System p13
[Skliarova2004] Intelligent Systems Engineering with Reconfigurable Computing p10
Hierarchical Graph-Schemes
[Slade2003] Reconfigurable Computing Application Frameworks p10
J. Smit et al, “Low cost and fast turnaround: reconfigurable graph-based execution units,” in Proc. 7th BELSIGN Workshop, Enschede, Netherlands, 1998.
[Srinivas2007] Implementation of FPGA in the design of Embedded Systems p78
Sripornprasert The AES Encryption Circuit on a Reconfigurable Hardware p4
[Steinbach2004] UML-BASED CO-DESIGN FOR RUN-TIME RECONFIGURABLE ARCHITECTURES p15
Steinbach UML-BASED CO-DESIGN FOR RUN-TIME RECONFIGURABLE ARCHITECTURES p15
!!!!!!!!!!!!
[Stekelenburg1998] Low Cost Fast Turnaround: Reconfigurable Graph-Based Execution Units p5

dataflow graph

execution graph

Reconfigurable Graph
!!!!!!!!!!!!
R. S. Stevens, “The Processing Graph Method Tool (PGMT),” in Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors, 1997, pp. 263--271.
Stitt Reconfigurable Computing: A Plan for Post-Moore's Law Sustainability p17
!!!!!!!!!!!!
[Streichert2007] Self-Adaptive Hardware/Software Reconfigurable Networks p253

architecture graph

hierarchical architecture graph

control/data flow graphs

dynamic graphs

hierarchical graph

permutation graphs

problem graph

hierarchical problem graph

sensor-controller-actuator (SCA) graph

specification graph

Hierarchical Specification Graph

topology graph
[STOJANOVIC2013] An Overview of Selected Hybrid and Reconfigurable Architectures p25
??????????????
[Stroop2012] Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators p113

flow graph

GNU Radio Companion Flow Graph

GNU Radio flow graph

GNU Radio Python Flow Graph
??????????????????
[Sun2004] Design of a Simulator for Mesh-based Reconˉgurable Architectures p10
Mesh
??????????????????
[Sung1998] Memory Efficient Software Synthesis from Dataflow Graph p20

Dataflow Graph

Synchronous SDF graph
[Sutter2011] Coarse-Grained Reconfigurable Array Architectures p39

Modulo Resource Routing Graphs (MRRGs)

Data Dependence Graph (DDG)

modulo graph embedding

graph mapping
[Svensson2008] Reconfigurable Architectures for Embedded Systems p183

call graph

data-flow graph

hierarchical conditional dependency graph (HCDG)

kernel graph
[Synplicity2005] Reconfigurable System-on-a-Chip p12
Thahir Compiling for Reconfigurable Computing p25
[TANIGUCHI2005] Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model p20

Data flow graph (DFG) is one method of task representation with execution dependency. Traditional DFG is composed of nodes and edges. Node represents an operation, and the edge connected to a pair of nodes means the data flow between them. Incoming edges of a node mean the input data used for the corresponding operation, and
outgoing edges of a node mean the results from corresponding operation.

When the data are used at some nodes, data read sometimes occurs but data write occurs only one time. The traditional DFG cannot precisely represent the number of memory accesses because the differences of the data represented by outgoing edges cannot be distinguished. Thus, we label the input/output of node of traditional DFG as “port”, which represents the input or output data. We call this DFG as port expansion DFG. Each node of the port expansion DFG has ports, and each edge connects to a pair of ports.

However, using a port expansion DFG, we can recognize that node 0 clearly outputs data used at nodes 2 and 3, and node 1 outputs two data that are respectively used at nodes 3 and 4. Thus, it can be obtained that three data
writes are required after configuration n.

Task Partitioning Problem
For given a port expansion DFG of the target application and a PRPmodel, to find a task partition and storage resource assignment whose execution cycles are minimum keeping the execution order defined by port expansion DFG.

The number of nodes in DCT8’s port expansion DFG is 50, which is 13 in CHENG.

Table 4 shows CPU time for more complex port expansion DFGs under the same conditions as previous. The number of port expansion DFG’s nodes N equals 100, 300, and 500, and the number of pPE npPE equals 8, 64, and 256.
Teich Reconfigurable Computing Systems p4

Polymorph
Hyperreconfigurable hardware
[Templin2010] DESIGN OF AN ADAPTABLE RUN-TIME RECONFIGURABLE SOFTWARE-DEFINED RADIO PROCESSING ARCHITECTURE p63

control- and data-flow graph

data flow graph
Tiwari Hardware/Software Co-debugging for Reconfigurable Computing p81
[VANCOURT2008] Elements of High-Performance Reconfigurable Computing p45
[Venkataramani2001] A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture p10

The operation-scheduling problem reduces to scheduling a data flow graph onto a single, sequential processor.

At the end of this optimization pass, there will be NI distinct data flow graphs corresponding to each iteration.

However, there may be some cross-edges between these data flow graphs that represent the re-use of computation. These edges are synthesized into registers during the register allocation phase.

Two nodes that have a direct data-dependence (i.e. an edge in the data flow graph) are assigned a higher weight
(say k) than all other nodes (default weight is 1).

Hierarchical Data flow graphs (HDFG) are used as intermediate representation in the compiler. An HDFG is an acyclic, directed, data flow graph, where some nodes can have sub-graphs within them. These graph representations are similar in structure to the data dependence control flow (DDCF) graphs [2].

program graph

iteration graphs

CLIQUE_PARTITIONING
[Viele2012] APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL p185

Graph Optimization
[Vorbach2003] Reconfigurable Processor Architectures for Mobile Phones p6
signal flow graph
[Wang2009] Loop Kernel Pipelining Mapping onto Coarse- Grained Reconfigurable Architecture for Data- Intensive Applications p9

reconfigurable architecture graph

virtual instruction data flow graph

program information aided control-dataflow task graph

task flow graph
[WANKAR2009a] RECONFIGURABLE ARCHITECTURES AND ALGORITHMS A RESEARCH SURVEY p16

[WANKAR2009b] RECONFIGURABLE ARCHITECTURES AND ALGORITHMS: A RESEARCH SURVEY p15

International Journal of Computer Science and Applications, ó2009 Technomathematics Research Foundation
Vol. 6, No. 1, pp. 108 – 123
108
RECONFIGURABLE ARCHITECTURES AND ALGORITHMS: A RESEARCH SURVEY
RAJEEV WANKAR
Department of Computer and Information Sciences, University of Hyderabad,
P.O. Central University,
Hyderabad, AP 500046, India
wankarcs@uohyd.ernet.in
http://uohyd.ernet.in/~wankarcs
RAJENDRA AKERKAR
Technomathematics Research Foundation
Kolhapur, India
raakerkar@yahoo.com
dynamically reconfigurable architecture

reconfigurable mesh

3-D Reconfigurable Mesh

Optical Reconfigurable Mesh

constant degree reconfigurable network

reconfigurable bus architecture

Array with Reconfigurable Optical Buses (AROB)

linear arrays with reconfigurable pipelined bus system (LARPBS)

reconfigurable parallel computation models

transitive closure of an undirected graph

path embedding

minimum spanning tree
Ward Dynamically Reconfigurable Computing A Novel Computation Technology with Potential to Improve National Security Capabilities by Dramatically Improving High-End Computing p6

Reconfigurable Supercomputing
[Wilhelmsson2007] Field Programmable Gate Arrays and Reconfigurable Computing in Automatic Control p102

data flow graphs
????????????????????
Windh High-Level Language Tools for Reconfigurable Computing p19
[Wright2009] FIELD PROGRAMMABLE GATE ARRAY (FPGA) BASED SOFTWARE DEFINED RADIO (SDR) DESIGN p127
[Wu2007] Reconfigurable Architectures: from Physical Implementation to Dynamic Behaviour Modelling p136

Control and Data Flow Graph

dataflow graph

task graph
[YANG2012] TISA Reconfigurable System for Template-Based Stream Computing p5
directed acyclic graph
[Ye2004] Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits p244

coarse-grain node graph (CNG)

routing resource graph
[Zain-ul-Abdin2007] A Study of Design Efficiency with a High-Level Language for FPGAs p8

data flow graphs

handshake graph
[Zain-ul-Abdin2009] High-Level Programming of Coarse-Grained Reconfigurable Architectures p80

control flow graph

data-flow graphs

handshake graph

stream graph

[Zaretsky2001] DESIGN AND EVALUATION OF MATLAB FUNCTIONS ON FIELD PROGRAMMABLE GATE ARRAYS FPGAS p238
!!!!!!!!!!!!!!!!!
[Zaretsky2004] Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15

Control and Data Flow Graphs

control flow graph

data flow graph
[ZhangXJ2000] A review of high-level synthesis for dynamically reconfigurable FPGAs p13

module call graphs

control data-flow graphs

control flow graph

complete data-flow graph

memory graph

task graph
???????????????
ZHANG Auto-adaptive reconfigurable architecture for scalable multimedia applications p7

[ZhangXJ1998] Module Allocation for Dynamically Reconfigurable Systems p9

extended control/data flow graph (ECDFG)

control and dataow graph (CDFG)

graph latency


Next Generation of ICs

NGIPC
├<000NGIPC>
│ ├000ngipc.docx
│ ├000ngipc_openproblems.docx
│ ├00chip_special.docx
│ ├Chang Emerging Interconnect Technologies for CMOS and beyond-CMOS Circuits p21.pdf
│ ├Iwai Future of Silicon Integrated Circuit Technology p5.pdf
│ ├Roy BEYOND CHARGE-BASED COMPUTING p80.pdf
│ ├Shukla NANO, QUANTUM AND MOLECULAR COMPUTING p377.pdf
│ ├The_Next_20_Years_of_Microchips.pdf
│ └Vgruev Digital Integrated Circuit Design and Architecture Chapter 1 Introduction p20.pdf
├<00spin>
│ ├0000emails_spin.txt
│ ├0000spin.docx
│ ├000Abdullah Spin Current Amplification by a Geometrical Ratchet Effect p155.pdf
│ ├000AMAND Spin dynamics and exchange interaction in semiconductor quantum dots p52.pdf
│ ├000Andrade Spin-FET based on InGaAsInP heterostructure p51.pdf
│ ├000Awschalom SPIN ELECTRONICS p168.pdf
│ ├000Balestro Molecular spintronics p55.pdf
│ ├000Baláz Current-induced dynamics in magnetic nanopillars p164.pdf
│ ├000Bercioux Spin-dependent transport in nanostructures p119.pdf
│ ├000Birk Spin Electronics in Metallic Nanoparticles p109.pdf
│ ├000Bonhomme CIRCUIT MODELING OF SPINTRONIC DEVICES A SPICE IMPLEMENTATION p66.pdf
│ ├000Br?uninger Tunnel barriers for spin injection into grapheme p148.pdf
│ ├000Bürgler Spintronics p183.pdf
│ ├000Carlegrim Development of Organic-Based Thin Film Magnets for Spintronics p67.pdf
│ ├000Carva Spin-dependent transport in layered magnetic nanostructures p121.pdf
│ ├000Chen ON-CHIP SPIN CONTROL IN SEMICONDUCTOR MICROAND NANO- STRUCTURES p171.pdf
│ ├000CHUREEMART MODELS OF SPIN TORQUE USING SELF-CONSISTENT SOLUTIONS OF THE MAGNETISATION AND SPIN ACCUMULATION p163.pdf
│ ├000Coey Chapter 14 Spin Electronics and Magnetic Recording p62.pdf
│ ├000Corbetta Spin-polarized Scanning Tunneling Microscopy and Spectroscopy Study of Fe and Co Nanostructures on Cu(111) p123.pdf
│ ├000Das Spintronics with quantum dots p64.pdf
│ ├000Dash Nanospintronics p117.pdf
│ ├000Duine Spintronics p81.pdf
│ ├000Dürrenfeld Spin Torque and Spin Hall Nano-Oscillators with Single Magnetic Layers p78.pdf
│ ├000Elste Quantum transport through single-molecule devices spin and vibration p126.pdf
│ ├000Elzerman Semiconductor Few-Electron Quantum Dots as Spin Qubits p72.pdf
│ ├000Fabian SEMICONDUCTOR SPINTRONICS p343.pdf
│ ├000Fert Présent et futur de la spintronique p51.pdf
│ ├000FLATTE SEMICONDUCTOR SPINTRONICS FOR QUANTUM COMPUTATION p52.pdf
│ ├000Folk SPIN TRANSPORT MEASUREMENTS IN GaAs QUANTUM DOTS p76.pdf
│ ├000Fragner Circuit Quantum Electrodynamics with Electrons on Helium p232.pdf
│ ├000Freitas Spin Electronics from data storage to biochips Part II MRAMS, hybrid semiconductor-magnetic devices p56.pdf
│ ├000Fu OPTICAL MANIPULATION OF ELECTRON SPINS BOUND TO NEUTRAL DONORS IN GAAS p127.pdf
│ ├000Galperin Spintronics p74.pdf
│ ├000Garello Symmetry and magnitude of spin-orbit torques in ferromagnetic heterostructures p51.pdf
│ ├000Golovatski Spin torque and interactions in ferromagnetic semiconductor domain walls p124.pdf
│ ├000Hachiya Spin relaxation in semiconductor nanostructures p116.pdf
│ ├000Hajj Etude mathematique et numerique de modeles de transport application a la spintronique p213.pdf
│ ├000Heers Effect of spin-orbit scattering on transport properties of low-dimensional dilute alloys p211.pdf
│ ├000Heers Effect of spin-orbit scattering on transport properties of low-dimensional dilute alloys p226.pdf
│ ├000Hoang Phase transition and Spin transport in Complex Systems Frustrated spin systems, Molecular and Liquid Crystals p164.pdf
│ ├000Huda Modeling and Design of Spin Torque Transfer Magnetoresistive Random Access Memory p120.pdf
│ ├000Ingenhoven Spin dependent electronic and transport properties of unconventional conductors p122.pdf
│ ├000Jansen Spin injection concept and technology p74.pdf
│ ├000Jaromirska Modeling spin transfer induced oscillations in spin valve nanostructures p190.pdf
│ ├000JOIBARI INTERPLAY OF CHARGE CURRENT AND SPIN IN NANOSTRUCTURES p101.pdf
│ ├000Kim Electrical injection and detection of spin polarization in InSb ferromagnet nanostructures p118.pdf
│ ├000Konig Semiconductor Spintronics p81.pdf
│ ├000Koo Control of Spin Precession in a Datta-Das Transistor Structure p80.pdf
│ ├000Krich Electron and nuclear spins in semiconductor quantum dots p150.pdf
│ ├000LeClair Fundamental aspects of spin polarized tunneling p187.pdf
│ ├000Leem MAGNETIC COUPLED SPIN-TORQUE DEVICE SPIN-BASED NON-VOLATILE LOGIC DEVICE AND APPLICATIONS p180.pdf
│ ├000Levy An idiosyncratic survey of spintronics p77.pdf
│ ├000Lin Organic spintronic devices utilizing spin-injection, spin-tunneling and spin-dependent transport p109.pdf
│ ├000Lin Spin polarization of ground state electron gas at low densities p139.pdf
│ ├000Lo Electrical Detection of Spin-Dependent Transport in Silicon p193.pdf
│ ├000Loh Mechanism and assessment of spin transfer torque based memory p70.pdf
│ ├000Mane Spin-polarized charged particle beams in high-energy accelerators p269.pdf
│ ├000Mann Determining the Spin Polarization of Heusler Compounds via Femtosecond Magnetization Dynamics p113.pdf
│ ├000Meijer RASHBA SPIN-ORBIT INTERACTION IN MESOSCOPIC SYSTEMS p149.pdf
│ ├000Moehlmann Spin transport in strained non-magnetic zinc blende semiconductor p130.pdf
│ ├000Morenzoni Introduction to SR Muon Spin RotationRelaxation p55.pdf
│ ├000Morten Coherent and Correlated Spin Transport in Nanoscale Superconductors p148.pdf
│ ├000Münzenberg Spin-wave and spin-current dynamics in ultrafast demagnetization experiments p56.pdf
│ ├000Münzenberg The magneto-Seebeck effect - THz Spintronics p55.pdf
│ ├000Neumann Electronic spin transport and thermoelectric effects in graphene p145.pdf
│ ├000NGUYEN TRANSPORT éLECTRONIQUE ET EFFETS DE SPIN DANS LES NANOSTRUCTURES DE GRAPHèNE p204.pdf
│ ├000Nikonov Benchmarking Spintronic Logic Devices p63.pdf
│ ├000NOSSA Nanospintronics With Molecular Magnets. Tunneling And Spin-Electric Coupling p219.pdf
│ ├000O'Brien Charge degrees of freedom on the kagome lattice p76.pdf
│ ├000Oshikawa Theory of Electron Spin Resonance p99.pdf
│ ├000Palmer Relaxation and Dynamic Processes p118.pdf
│ ├000PATHAK HALF-METALLIC CrO2 THIN FILMS FOR SPINTRONIC APPLICATIONS p112.pdf
│ ├000Podnieks Theory of Single Spin Detection Using an ESR-STM Technique p174.pdf
│ ├000POLI Spin transport in normal and superconducting nanowires p88.pdf
│ ├000Popa Insitu studies of spin electronics properties of magnetic nanocontacts p191.pdf
│ ├000Rieger Electron spin resonance p100.pdf
│ ├000Rohra Exact-Exchange Kohn-Sham Spin-Current Density-Functional Theory p165.pdf
│ ├000Ryan Polarised Neutron Scattering p63.pdf
│ ├000Saari Electronic structure and spin polarization in Silicene nanostructures p69.pdf
│ ├000Sahoo An Experimental Investigation of Spin Polarized Transport in Carbon Nanotubes p124.pdf
│ ├000SAITOH Spin current coupled with charge and heat currents p88.pdf
│ ├000Sanvito Ab-initio methods for spin-transport at the nanoscale p117.pdf
│ ├000Sanvito Giant Magnetoresistance and Quantum Transport in Magnetic Hybrid Nanostructures p192.pdf
│ ├000Sapkota Spin Dependent Transport Properties of Metallic and Semiconducting Nanostructures p139.pdf
│ ├000Sato Spintronics for next generation innovative devices p79.pdf
│ ├000Scharpf The spin of the neutron as a measuring probe p246.pdf
│ ├000Schindler Quantum spin transport in semiconductor nanostructures p187.pdf
│ ├000Sentef Linear-Response Theory of Spin Transport p90.pdf
│ ├000Shiraishi Molecular Spintronics p66.pdf
│ ├000Shiraishi Molecular Spintronics using Electron Molecules p63.pdf
│ ├000Shylau Electron transport, interaction and spin in graphene and graphene nanoribbons p80.pdf
│ ├000Sinno Polyelectrolyte-Gated Organic Field Effect Transistors – Printing and Electrical Stability p74.pdf
│ ├000Skinner Electrical control of spin dynamics in spin-orbit coupled ferromagnets p139.pdf
│ ├000Spielberg New Building Blocks for Molecular Spintronics p223.pdf
│ ├000Studer Spin manipulation in two-dimensional electron and hole gases p115.pdf
│ ├000Swaving Spin Transport and Dynamics in Antiferromagnetic Metals and Magnetic Insulators p108.pdf
│ ├000Tatara Introduction to microscopic theory of spin transport p89.pdf
│ ├000Toit SPIN CURRENTTHE CONTRIBUTION OF SPIN TO THE PROBABILITY CURRENT FOR NONRELATIVISTIC PARTICLES p96 .pdf
│ ├000Vila From Basic Magnetic Concepts To Spin Currents p60.pdf
│ ├000Wagemans Plastic Spintronics p131.pdf
│ ├000Walser Spin-orbit interaction and the persistent spin helix in two-dimensional electron gases p153.pdf
│ ├000Weymann Spin-Dependent Transport in Magnetic Nanostructures with Coulomb Blockade p145.pdf
│ ├000Winkler Spin–Orbit Coupling Effects in Two-Dimensional Electron and Hole Systems p236.pdf
│ ├000Woltersdorf SPIN-PUMPING AND TWO-MAGNON SCATTERING IN MAGNETIC MULTILAYERS p200.pdf
│ ├000Wu Nano Spintronics for Data Storage p50.pdf
│ ├000Yan Nonlinear Magnetic Dynamics and The Switching Phase Diagrams in Spintronic Devices p92.pdf
│ ├000Yang Electronic Spin Transport in Bilayer and Single Layer Graphene p140.pdf
│ ├000Yu Thermal Spin Transfer Torque and Transverse Spin Relaxation in Spin Valves p123.pdf
│ ├000ZHOU Spin momentum transfer effects for spintronic device applications p91.pdf
│ ├000Zuelicke Spin-dependent transport due to spin-orbit coupling p57.pdf
│ ├Adur Spin Pumping in Ferromagnetic Resonance and Electrical Detection Experiments p16.pdf
│ ├Amipara Nano Technology – Spintronics p5.pdf
│ ├Anane From spintronics to magnons-spintronics p41.pdf
│ ├Anjum Spintronics Fundamentals and Applications p9.pdf
│ ├Atsarkin Nuclear magnetic relaxation and spin diffusion in the local fields of paramagnetic centers p7.pdf
│ ├Awschalom Spin Dynamics in Semiconductors p41.pdf
│ ├Awschalom The Diamond Age of SPIN ELECTRONICS p8.pdf
│ ├BAKSALARY QUASICLASSICAL THEORY OF SPIN-VALVE MAGNETORESISTANCE ROLE OF SPIN-FLIP SCATTERING p4.pdf
│ ├Bandyopadhyay Supercomputing with spin-polarized single electrons in a quantum coupled architecture p21.pdf
│ ├BARLETTI QUANTUM DRIFT-DIFFUSION MODELING OF SPIN TRANSPORT IN NANOSTRUCTURES p22.pdf
│ ├Bercioux Spin-orbit interactions in semiconductor nanostructures p10.pdf
│ ├BERGENTI Organic spintronics p15.pdf
│ ├Bishnoi Architectural Aspects in Design and Analysis of SOT-based Memories p30.pdf
│ ├Bobo Recent advances in nanomagnetism and spin electronics p26.pdf
│ ├Bournel Theoretical and experimental considerations on the spin field effect transistor p5.pdf
│ ├Brataas Spin–orbit torques in action p3.pdf
│ ├Bruno Spin-dependent transport in layered magnetic metals p30.pdf
│ ├Bruno Spin-electronics a new challenge in science and technology p27.pdf
│ ├Buchenberg SPINTRONICS p39.pdf
│ ├Buhrman CHAPTER 4 SPIN INJECTION, SPIN TRANSPORT AND SPIN TRANSFER p10.pdf
│ ├Camarero Molecular vs. inorganic spintronics the role of molecular materials and single molecules p7.pdf
│ ├Chen All-electric Spin Transistors p34.pdf
│ ├Chen Phonon-assisted spin current in a hybrid system with a single molecular quantum dot system applied with ac magnetic fields p8.pdf
│ ├Chetan spin-electronics p14.doc
│ ├Chuang All-electric all-semiconductor spin field effect transistors p18.pdf
│ ├Chuang All-electric and all-semiconductor spin field effect transistors p17.pdf
│ ├Cimpoesu Dynamic and temperature effects in spin-transfer switching p8.pdf
│ ├Coronado MOLECULAR SPINTRONICS p28.pdf
│ ├Cottet Nanospintronics with carbon nanotubes p18.pdf
│ ├Crooker Electrical Spin Injection, Accumulation, and Detection in Lateral FerromagnetSemiconductor Devices p35.pdf
│ ├Crouzy How spin-flip scattering influences the minigap in a S-N junction p47.pdf
│ ├Culcer Spin procession and relaxation in semiconductors p24.pdf
│ ├DAHL THE SPINNING ELECTRON p36.pdf
│ ├Dankert Spin transport and precession in grapheme measured by nonlocal and three-terminal methods p5.pdf
│ ├Dargys WHY THE SPIN-FET DOES NOTWORK p10.pdf
│ ├Dash Electrical creation of spin polarization in silicon at room temperature p4.pdf
│ ├Datta From Spin Physics to Spin Electronics-I p10.pdf
│ ├Datta Non-volatile Spin Switch for Boolean and Non-Boolean Logic p10 .pdf
│ ├Demidov Spin-current nano-oscillator based on nonlocal spin injection p5.pdf
│ ├Demidov Spin-Hall nano-oscillators p24.pdf
│ ├Demokritov Magnetic dynamics driven by spin current p30.pdf
│ ├Dieny Spin-transfer effect and its use in spintronic components p21.pdf
│ ├Duan Nanowire spin torque oscillator driven by spin orbit torques p7.pdf
│ ├Dugaev Spin Currents in Magnetic Nanostructures p8.pdf
│ ├Ebert New effects in spintronics derived from the symmetry of response functions p28.pdf
│ ├Egues Novel spin FETs p2.pdf
│ ├Emberly Molecular spintronics spin-dependent electron transport in molecular wires p14.pdf
│ ├EURAMET Spintronic and spin-caloritronics in magnetic nanosystems p3.pdf
│ ├Fabian classical and quantum spin devices theoretical perspectives p30.pdf
│ ├Fabian Fundamental concepts of spintronics p34.pdf
│ ├Falk Engineered defects in wide band-gap semiconductors for single-spin sensing and computation p39.pdf
│ ├Fert Nobel Lecture Origin, development, and future of spintronics p14.pdf
│ ├Fert ORIGIN, DEVELOPMENT AND FUTURE OF SPINTRONICS p11.pdf
│ ├Fert THE ORIGIN, DEVELOPMENT AND FUTURE OF SPINTRONICS p22.pdf
│ ├Franklin FeFET Spintronics p17.pdf
│ ├Freitas Magnetoresistive sensors and applications I p45.pdf
│ ├Galperin Giant Magnetoresistance and Spintronics p47.pdf
│ ├Gelfond Symmetries of 4d higher-spin current interactions p16.pdf
│ ├Gerretsen Spin Transfer Torque in Ferromagnetic Materials p8.pdf
│ ├Getzlaff Spin-Polarized Scanning Tunneling Microscopy p48.pdf
│ ├Giulini Electron Spin or “Classically Non-Describable Two-Valuedness” p28.pdf
│ ├Gould Spintronics A half-time assessment p38.pdf
│ ├Grillo Quantum simulation of a spin polarization device in an electron microscope p25.pdf
│ ├Grundler Spintronics p5.pdf
│ ├Hahn Conduction of spin currents through insulating oxides p10.pdf
│ ├Hamrle Three-dimensional distribution of the spin-polarized current inside nanostructures p7.pdf
│ ├Han Graphene spintronics p14.pdf
│ ├Han Spin Transport and Relaxation in Graphene p41.pdf
│ ├Haron Emerging Non-CMOS Nanoelectronic Devices - What Are They p6.pdf
│ ├Hayashi Spin orbit torques and current induced domain wall motion in magnetic heterostructures p39.pdf
│ ├Heide Spin Orbit Driven Physics at Surfaces p39.pdf
│ ├Heidecker MRAM Technology Status p31.pdf
│ ├Heiman Nanostructures for Spintronics p33.pdf
│ ├Heinonen Spintronics in applications Hard drives, MRAM, and spin torque oscillators p36.pdf
│ ├Hien SIMULATION OF CURRENT-VOLTAGE CHARACTERISTICS OF SPIN FIELD EFFECT TRANSISTOR USING NEMO-VN2 p13.pdf
│ ├Idzuchi Spin transportinnon-magneticnano-structuresinducedbynon-local spin injection p25.pdf
│ ├Ikeda Magnetic Tunnel Junctions for Spintronic Memories and Beyond p12.pdf
│ ├Ilyasov Materials for Spintronics Magnetic and Transport Properties of Ultrathin (Monolayer Graphene)MnO(001) and MnO(001) Films p16.pdf
│ ├Irvin Gigahertz Optical Spin Transceiver p8.pdf
│ ├Isasa Temperature dependence of spin diffusion length and spin Hall angle in Au and Pt p13.pdf
│ ├Jacquod Spin Currents in Mesoscopic Systems p33.pdf
│ ├Jacquod Spin transport in mesoscopics p27.pdf
│ ├Jalil Spintronics in 2DEG Systems p12.pdf
│ ├Kalyani Spintronics- A Vision for Future in Electronics and Computers p7.pdf
│ ├Kang An Overview of Spin-based Integrated Circuits p27.pdf
│ ├KANTSER Materials and structures for semiconductor spintronics p14.pdf
│ ├Kartha SPINTRONICS AND SPINTRONIC DEVICES p30.pdf
│ ├Katsumoto Spin Transport p12.pdf
│ ├KENT Spin-Transport and Transfer in Magnetic Nanostructures p16.pdf
│ ├Kervalishvili Nanostructures, magnetic semiconductors and spintronics p6.pdf
│ ├Khodas Spintronics without Magnets“spin-optics” p41.pdf
│ ├Kim Gate-Control of Spin-Orbit Coupling in InAs HEMT Structures for a Spin Field-Effect Transistor p23.pdf
│ ├Kim Spin-Based Computing Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor p25.pdf
│ ├Konig Spin-Dependent Transport in Nanostructures p30.pdf
│ ├KRISHNAN Nanomagnetism and spin electronics materials, microstructure and novel properties p23.pdf
│ ├Kushwaha Spintronics Combination of Nanotechnology Superconductivity p6.pdf
│ ├Lee Spintronics Spin transfer torque in magnetic nanostructures and spin pumping effect p46.pdf
│ ├Lin Improvement of Spin Transfer Torque in Asymmetric Graphene Devices p8.pdf
│ ├Lindelof Electron Spin in Single Wall Carbon Nanotubes p19.pdf
│ ├Maekawa Concepts in Spin Electronics p4.pdf
│ ├Maekawa Concepts in Spin Electronics p6.pdf
│ ├Maekawa Spin Current and Spin Seebeck Effect p29.pdf
│ ├Maekawa Spin current vs charge current in magnetic nanostructures p31.pdf
│ ├Maekawa Spin Current.docx
│ ├Mangin Spin Transfer Torque Effects in Devices with Perpendicular Anisotropy p6.pdf
│ ├Manipatruni Circuit Theory for SPICE of Spintronic Integrated Circuits p14.pdf
│ ├Mavropoulos Spintronics Transport and Materials p24.pdf
│ ├Molnár CHAPTER 2 MATERIALS FOR SEMICONDUCTOR SPIN ELECTRONICS p8.pdf
│ ├Monaico Spintronics p13.pdf
│ ├Moodera Spin polarized tunneling in ferromagnetic junctions p26.pdf
│ ├Moreno New magnetic materials for Spintronics p25.pdf
│ ├Muller Spin transport p25.pdf
│ ├Myers Spin Torque and Magnetic Tunnel Junctions p38.pdf
│ ├Naber Organic spintronics p24.pdf
│ ├Newman Spintronics and Nanomagnetics p20.pdf
│ ├Nikolic Mesoscopics in Spintronics Quantum Interference Effects in Spin-Polarized Electron Transport p12.pdf
│ ├Nitta Semiconductor Spintronics p6.pdf
│ ├Niu Proper definition off spin current p16.pdf
│ ├OHNO Semiconductor Spin Electronics p10.pdf
│ ├Orellana Spin-polarized electrons in bilayer graphene ribbons p5.pdf
│ ├Osterwalder Spin-Polarized Photoemission p26.pdf
│ ├O’Connor Spin–orbit coupling in surface plasmon scattering by nanostructures p7.pdf
│ ├Pearton Advances in wide bandgap materials for semiconductor spintronics p32.pdf
│ ├Phil Electron Spin Resonance p49.pdf
│ ├Piéchon Boltzmann Theory of spin transfer torque in magnetic textures p17.pdf
│ ├Pramanik Spin dephasing in quantum wires p32.pdf
│ ├Ralph Spin transfer torques p27.pdf
│ ├Raman Interface-assisted molecular spintronics p12.pdf
│ ├RECAMI FIELD THEORY OF THE SPINNING ELECTRON ABOUT THE NEW NON-LINEAR FIELD EQUATIONS p10.pdf
│ ├Repain Spin polarized Scanning Tunneling Microscopy p32.pdf
│ ├ROCHA Towards molecular spintronics p5.pdf
│ ├Sanvito Molecular-Spintronics the art of driving spin through molecules p20.pdf
│ ├SARAGA Towards Quantum Communication with Electron Spins p15.pdf
│ ├Sasaki Spin Polarization of Fractional Quantum Hall States with ν 2 p17.pdf
│ ├Schindler Non-equilibrium Green‘s function approach to the Spin Hall effect in nanostructures p14.pdf
│ ├Schliemann Nonballistic Spin-Field-Effect Transistor p4.pdf
│ ├Schmidt Spin transport and spin devices p24.pdf
│ ├Schuhl Spintronics Opportunities and Challenges p18.pdf
│ ├Sham Control of Spin-Polarized Currents for Semiconductor Spintronics p20.pdf
│ ├Shen Spintronics and Spin Current p8.pdf
│ ├Shi Proper Definition of Spin Current in Spin-Orbit Coupled Systems p24.pdf
│ ├SPIN DYNAMICS p30.pdf
│ ├spin-injection_suzuki.pdf
│ ├Straub Electron Spin p4.pdf
│ ├Su Proposal for a graphene-based all-spin logic gate p5.pdf
│ ├Sun Angular Spin Current and Persistent Spin Current p47.pdf
│ ├Sun Simulation for Spin Relaxation in Semiconductor p13.pdf
│ ├Sverdlov Spin-Based Silicon FETsProgress and Challenges p12.pdf
│ ├Tahiliani A Review of Spintronics based Data Storage p18.pdf
│ ├Thingna Geometrical effects on spin injection 3D spin drift diffusion model p5.pdf
│ ├Tsymbal Interface-controlled tunneling spin polarization p21.pdf
│ ├Urazhdin Nanomagnonic devices based on the spin-transfer torque p5.pdf
│ ├VALENZUELA NONLOCAL ELECTRONIC SPIN DETECTION, SPIN ACCUMULATION AND THE SPIN HALL EFFECT p25.pdf
│ ├VALENZUELA SPIN CURRENTS AND SPIN CALORITRONICS p28.pdf
│ ├Valenzuela Spin Hall effect and Spin‐Orbit Torques An Overview p25.pdf
│ ├Valenzuela Spintronics An Overview p25.pdf
│ ├Vasileska Electron Spin p29.pdf
│ ├Villamor Contribution of defects to the spin relaxation in copper nanowires p10.pdf
│ ├Viret Spin electronics at the nanoscale p38.pdf
│ ├Vogel Spintronik p34.pdf
│ ├Wang From Nanoelectronics to Nano-Spintronics p8.pdf
│ ├Wang From Spin Torque Random Access Memory to Spintronic Memristor p23.pdf
│ ├Wang Nanoelectronics and Nanospintronics Fundamentals and Materials Perspective p29.pdf
│ ├WANG NONVOLATILE SPINTRONICS PERSPECTIVES ON INSTANT-ON NONVOLATILE NANOELECTRONIC SYSTEMS p22.pdf
│ ├Watanabe Polaron Spin Current Transport in Organic Semiconductors p21.pdf
│ ├Wegrowe Spin-Currents and Spin-Pumping Forces for Spintronics p16.pdf
│ ├Wernsdorfer Molecular Nanomagnets towards molecular spintronics p25.pdf
│ ├Westervelt Spintronics p39.pdf
│ ├Winkler Spinelektronik p6.PDF
│ ├Wolf Semiconductor Spintronics Electronics for the 21st century p14.pdf
│ ├Xie Spin current and its superfluid p46.pdf
│ ├YamadaSpin Spin-Related Transport in One One-Dimensional Conductors made at High High-In Content InGaAs InGaAsInAlAs Hetero Hetero-Junctions p37.pdf
│ ├Zhang Spin Hall Effects in Metallic Antiferromagnets p6.pdf
│ ├Zhang Spintronics for Low-Power Computing p6.pdf
│ ├ZHAO Runtime Reconfiguration FPGA Circuit p16.pdf
│ └Zhao Spin Transfer Torque (STT)-MRAM–Based Spin-electronics Based Logic Fabrics p6.pdf
├<0nano_deep_submicron>
│ ├0000nano_deep_submicron.docx
│ ├Andrés Developing Fault Models for Nanowire Logic Circuits p25.pdf
│ ├Aquilino Development of deep submicron CMOS process for fabrication of high performance 0.25 nm transistors p159.pdf
│ ├Balasubramanian Nanoscale thin-body MOSFET design and applications p185.pdf
│ ├Bazarjani Mixed Analog-Digital Design Considerations in Deep Submicron CMOS Technologies p183.pdf
│ ├Chaudhry Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability A Review p52.pdf
│ ├Chen CMOS vs. NANO p88.pdf
│ ├CUI MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT p157.pdf
│ ├Datta ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS p127.pdf
│ ├Deleonibus ELECTRONIC DEVICE ARCHITECTURES FOR THE NANO-CMOS ERA p440.pdf
│ ├Deleonibus Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices p88.pdf
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│ ├Haselman The Future of Integrated Circuits A Survey of Nano-electronics p57.pdf
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│ ├Lin Challenges for SoCDesign in Very Deep Submicron Technologies p52.pdf
│ ├Liu Multi-Voltage Nanoscale CMOS Circuit Techniques p247.pdf
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│ ├Piednoir Challenges of Deep Submicron Design p133.pdf
│ ├Rabaey Ultra deep submicron p38.pdf
│ ├RAKESH Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure p62.pdf
│ ├Routenberg Fabrication and Characterization of Silicon Nanowire Field Effect Sensors p165.pdf
│ ├Sicard Deep-submicron CMOS circuit design Simulator in hands p737.pdf
│ ├Staszewski Digital submicron CMOS frequency synthesis p319.pdf
│ ├Torres Recommendations on Beyond CMOS Nanoelectronics Research p59.pdf
│ ├Veendrick Deep-submicron CMOS ICs p286.pdf
│ ├Wong Nano CMOS Circuit and Physical Design encrypted p408.pdf
│ ├Wulff Effocient ADCs for nano-scale CMOS Technology p196.pdf
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│ │ │ ├Paun Membrane Computing Power, Efficiency, Applications (A Quick Introduction) p52.pdf
│ │ │ ├Paun Membrane Computing Power, Efficiency, Applications (Introduction and Some Recent Results) p79.pdf
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│ ├Leong Tuning the Threshold Voltage of MoS2 Field-Effect Transistors via Surface Treatment p35.pdf
│ ├Ranade Work Function Engineering of Molybdenum Gate Electrodes.pdf
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│ ├Ye Recent Advancement on the Optical Properties of Two-Dimensional Molybdenum Disulfide (MoS2) Thin Films p20.pdf
│ └Zhan Large Area Vapor Phase Growth and Characterization of MoS2 Atomic Layers on SiO2 Substrate p24.pdf
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│ ├Barnett A Graph Theoretic Interpretation of Neural Complexity p19.pdf
│ ├Berry Structure and dynamics of random recurrent neural networks p10.pdf
│ ├Campolucci A Circuit Theory Approach to Recurrent Neural Network Architectures and Learning Methods p140.pdf
│ ├DeVille Dynamics of Stochastic Neuronal Networks and the connections to Random Graph Theory p41.pdf
│ ├Dobnikar Structural Properties of Recurrent Neural Networks p14.pdf
│ ├Fox Massively parallel neural computation p106.pdf
│ ├Ghanbari A Graph-Laplacian-Based Feature Extraction Algorithm for Neural Spike Sorting p12.pdf
│ ├Hafliger Neuromorphic Electronics p166.pdf
│ ├Khouzam Neural networks as cellular computing models for temporal sequence processing p252.pdf
│ ├Kozma Hierarchical Random Cellular Neural Networks for System-Level Brain-Like Signal Processing p29.pdf
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│ ├Levy Neural Computation, Analogical Promiscuity, and the Induction of Semantic Roles A Preliminary Sketch p41.pdf
│ ├Mehrotra Elements of Artificial Neural Networks p345.pdf
│ ├Merolla A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface p40.pdf
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│ ├McLeod Silicon integrated optics p16.pdf
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│ ├<plasmonics>
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│ ├Cidronali Resonant Tunneling Devices physics, technology and applications p53.pdf
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│ ├Jacobs Development of Resonant Tunnelling Diode Terahertz Emitter p180.pdf
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│ ├Amato Reversible Computing p20.pdf
│ ├Bennett Logical Reversibility of Computation p8.pdf
│ ├Bennett Notes on Landauer’s principle, reversible computation, and Maxwell’s Demon p10.pdf
│ ├Bhatt OPTIMIZED STUDY OF ONE-BIT COMPARATOR USING REVERSIBLE LOGIC GATES p6.pdf
│ ├Bhattacharyya Design of a 4-bit ALU Using Reversible Fredkin Gates p39.pdf
│ ├Callan Reversible Logic as a Strategy for Computing p38.pdf
│ ├Car?e Design of Reversible Computing Systems Logic, Languages, and Circuits p54.pdf
│ ├De Vos Symmetry Groups for the Decomposition of Reversible Computers, Quantum Computers, and Computers in between p20.pdf
│ ├Di Pierro On Reversible Combinatory Logic p10.pdf
│ ├Drechsler Reversible Circuits Recent Accomplishments and Future Challenges for an Emerging Technology p8.pdf
│ ├Gandhi A NEW REVERSIBLE SMG GATE AND ITS APPLICATION FOR DESIGNING REVERSIBLE TWO’S COMPLEMENT ADDERSUBTRACTOR p4.pdf
│ ├Giles An investigation of some theoretical aspects of reversible computing p220.pdf
│ ├Green From reversible to irreversible computations p9.pdf
│ ├Heunen Reversible Monadic Computing p20.pdf
│ ├H?nninen Reversible and Adiabatic Computing Energy-Efficiency Maximized p16.pdf
│ ├Kamani Energy Efficient Reversible logic Design for Code Converters p5.pdf
│ ├Kari Periodicity and Immortality in Reversible Computing p28.pdf
│ ├Kaur Reversible and Fault Tolerant Reversible Gates p4.pdf
│ ├Kaur Reversible Multiplier – A Review p7.pdf
│ ├Kerntopf REVERSIBLE LOGIC CIRCUITS p53.pdf
│ ├LEVINE A NOTE ON BENNE’IT’S TIME-SPACE TRADEOFF FOR REVERSIBLE COMPUTATION p5.pdf
│ ├Levitin Thermodynamic cost of reversible computing p5.pdf
│ ├Mamataj A Review of Reversible Gates and its Application in Logic Design p11.pdf
│ ├Moraga On double gates for reversible computing circuits p8.pdf
│ ├Morita A Simple Universal Logic Element and Cellular Automata for Reversible Computing p12.pdf
│ ├Morita Design of Reversible and Quantum Circuits p15.pdf
│ ├Mu An Injective Language for Reversible Computation p21.pdf
│ ├Ollinger Periodicity and Immortality in Reversible Computing p69.pdf
│ ├Ouanaim Reversible Computing and Entropy p12.pdf
│ ├Parhami Fault-Tolerant Reversible Circuits p4.pdf
│ ├Pundir Study Of All-Optical Reversible Logic Gates p4.pdf
│ ├Rawat REVERSIBLE LOGIC GATES AND THEIR APPLICATIONS p4.pdf
│ ├Semenov A Prospective Approachto Energy Saving (Reversible) Computing p33.pdf
│ ├Semenov Reversible Computing with nSQUID Arrays.ppt
│ ├Soeken RevKit A Toolkit for Reversible Circuit Design p1.pdf
│ ├Thapliyal A New Design of The Reversible Subtractor Circuit p6.pdf
│ ├Tiffoli Reversible Computing p13.pdf
│ ├Tiffoli Reversible Computing p37.pdf
│ ├Tiffoli Reversible Computing p40.pdf
│ ├VAN RENTERGEM Optimal Design of A Reversible Full Adder p17.pdf
│ ├Vanusha Low Power Computing Logic Gates design using Reversible logic p7.pdf
│ ├Vitanyi Time, Space, and Energy in Reversible Computing p10.pdf
│ └Yokoyama Reversible Computation and Reversible Programming Languages p11.pdf
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│ ├000singleelectron.docx
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│ ├Buxboim Current characteristics of the single-electron transistor at the degeneracy point p17.pdf
│ ├Chawla Single Electron transistor- The future of transistors p6.pdf
│ ├DUBEJSKY FABRICATION AND DC CHARACTERIZATION OF SINGLE ELECTRON TRANSISTORS AT LOW TEMPERATURE p148.pdf
│ ├Fombah Single Electron Transistor p14.ppt
│ ├Goyal A Review towards Single Electron Transistor (SET) p4.pdf
│ ├HAI Reconfigurable Logic Gates Using Single-Electron Spin Transistors p31.pdf
│ ├Ionescu Hybrid CMOS Single-Electron-Transistor Device and Circuit Design p46.pdf
│ ├Kastner The single electron transistor and artificial atoms p10.pdf
│ ├Kim Single-Electron Logic Cells and SETFET Hybrid Integrated Circuits p7.pdf
│ ├Koerting Transport properties of a superconducting single-electron transistor coupled to a nanomechanical oscillator p19.pdf
│ ├Kumar Single Electron Transistor Applications and problems p6 (2).pdf
│ ├Kumar Single Electron Transistor Applications and problems p6.pdf
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│ ├Mittal BASIC INTRODUCTION TO SINGLE ELECTRON TRANSISTOR p5.pdf
│ ├Park Electron Transport in Single Molecule Transistors p165.pdf
│ ├Perry Digital to Analog Converter Design using Single Electron Transistors p73.pdf
│ ├Pott Gate-All-Around Silicon Nanowires for Hybrid Single Electron TransistorCMOS Applications p154.pdf
│ ├QuantumWise Benzene Single-Electron Transistor Tutorial p32.pdf
│ ├Schon Single-Electron Tunneling p65.pdf
│ ├Simonian Design and Simulation of Single-Electron Molecular Devices p121.pdf
│ ├Takahashi Silicon Single-Electron Devices and Their Applications p10.pdf
│ ├Uchida Programmable Single-Electron Transistor Logic for Future Low-Power Intelligent LSI Proposal and Room-Temperature Operation p8.pdf
│ ├Weis Single-Electron Devices p35.pdf
│ └Zhu Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems p14.pdf
├<superconductingOK>
│ ├0000superconduct.docx
│ ├Anacker Josephson Computer Technology An IBM Research Project p6.pdf
│ ├BERGEAL INTRODUCTION TO QUANTUM SUPERCONDUCTING CIRCUITS PART 1 p77.pdf
│ ├BERGGREN Quantum Computing With Superconductors p9.pdf
│ ├Deppe Superconducting flux quantum circuits characterization, quantum coherence, and controlled symmetry breaking p130.pdf
│ ├DEVORET QUANTUM SUPERCONDUCTING CIRCUITS p30.pdf
│ ├Devoret Superconducting Circuits for Quantum Information An Outlook p12.pdf
│ ├FELDMAN Josephson Junction Digital Circuits -- Challenges and Opportunities p22.pdf
│ ├Girvin Superconducting Qubits and Circuits Artificial Atoms Coupled to Microwave Photons p132.pdf
│ ├Guichard Superconducting quantum nano-circuits p23.pdf
│ ├Jiang Quantum Control of Superconducting Circuits p21.pdf
│ ├KUBO Hybrid Quantum Circuit with a Superconducting Qubit coupled to a Spin Ensemble p39.pdf
│ ├Langford Circuit QED — Lecture Notes p85.pdf
│ ├Martinis Design of a Superconducting Quantum Computer p28.pdf
│ ├Martinis Design of a Superconducting Quantum Computer p44.pdf
│ ├Singh A Magnetic Lattice and Macroscopic Entanglement of a BEC on an Atom Chip p171.pdf
│ ├STA SUPERCONDUCTING TECHNOLOGY ASSESSMENT p257.pdf
│ ├Sterling Enabling Technologies for Peta FLOPS Computing p202.pdf
│ └Weides Quantum simulation with superconducting circuits p5.pdf
├<yyynot_powerful_enough>
│ ├<3dic>
│ │ ├3dic.docx
│ │ ├McKibbin Towards Three Dimensional All-Epitaxial Silicon Architectures Patterned By Scanning Tunnelling Microscopy p228.pdf
│ │ ├Pavlidis Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits okokok p366.pdf
│ │ ├Souri 3D ICs Interconnect Performance Modeling and Analysis p123.pdf
│ │ ├YAMADA ON THREE-DIMENSIONAL LAYOUT OF DE BRUIJN NETWORKS p4.pdf
│ │ └Yamada ON THREE-DIMENSIONAL LAYOUT OF PYRAMID NETWORKS p6.pdf
│ ├<chemical>
│ │ ├000chemicalcomputing.docx
│ │ ├Adamatzky Designing a chemical computer p3.pdf
│ │ ├Adamatzky On some limitations of reaction-diffusion chemical computers in relation to Voronoi diagram and its inversion p11.pdf
│ │ ├Adamatzky Programming Reaction-Diffusion Processors p14 (2).pdf
│ │ ├Asai Towards reaction–diffusion computing devices based on minority-carrier transport in semiconductors p14.pdf
│ │ ├Giavitto Autonomic computing,chemical computing &induction principles on spatial computing media p19.pdf
│ │ ├Hartmann Stochastic Simulation of Reaction-Diffusion Systems p57.pdf
│ │ ├Molnár SIMULATION OF REACTION-DIFFUSION PROCESSES IN THREE DIMENSIONS USING CUDA p30.pdf
│ │ ├OBROVAC Chemical Computing for Distributed Systems Algorithms and Implementation p201.pdf
│ │ └Yamamoto Considerations on the Evolution of Programs Based on Chemical Computing p56.pdf
│ ├<gallium>
│ │ ├000gallium.docx
│ │ ├Alpha Low Noise Medium Power GaAs MESFET Chips p3.pdf
│ │ ├AMP 9 - 10 GHz GaAs MMIC Core Chip p18.pdf
│ │ ├Bock New Manufacturing Concepts for Ultra-Thin Silicon and Gallium Arsenide Substrates p4.pdf
│ │ ├Brown AlGaNGaN HFETs fabricated on 100-mm GaN on silicon (111) substrates p5.pdf
│ │ ├Crowe Integrated GaAs Diode Technology for Millimeter and Submillimeter-wave Components and Systems p6.pdf
│ │ ├Harmon Rad-Hard Photomultiplier Chips.ppt
│ │ ├Northrop GaAs IC Die Handling Assembly and Testing Techniques p10.pdf
│ │ ├Siddiqui GaAs Components for 60 GHz Wireless Communication Applications p4.pdf
│ │ ├Skyworks GaAs Schottky Flip Chip Diodes p4.pdf
│ │ ├Upton TA 5.5 A 160,000 Transistor GaAs Microprocessor p3.pdf
│ │ └Wohlgemuth Digital SiGe-Chips for Data Transmission up to 85 Gbits p4.PDF
│ ├<germanium>
│ │ ├000germanium.docx
│ │ ├Bardin Silicon-Germanium Heterojunction Bipolar Transistors For Extremely Low-Noise Applications p234.pdf
│ │ ├Brocato Silicon Germanium Design p18.pdf
│ │ ├Guo Silicon germanium programmable circuits for gigahertz applications p7.pdf
│ │ ├Masini A FULLY INTEGRATED SILICON-GERMANIUM X-BAND VCO p4.pdf
│ │ ├SUN POWER METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH STRAINED SILICON AND SILICON GERMANIUM CHANNEL p104.pdf
│ │ └Wolf Silicon Germanium (SiGe) Bipolor Dicke Radiometer Front End Receiver Chip p170.pdf
│ ├<indium>
│ │ ├000indium.docx
│ │ └Wohlgemuth Digital SiGe-Chips for Data Transmission up to 85 Gbits p4.PDF
│ ├<liquid>
│ │ └000liquid.docx
│ ├<natural>
│ │ ├00nature.docx
│ │ ├Corne Selected Applications of Natural Computing p80.pdf
│ │ ├de Castro Fundamentals of natural computing an overview p36.pdf
│ │ ├Gupta-REMINISCENT-STUDY-OF-NATURE-INSPIRED-COMPUTATION-p9.pdf
│ │ ├Kundra ASSORTMENT OF NATURE INSPIRED COMPUTING p8.pdf
│ │ ├Uyar Nature-Inspired Computing p26.pdf
│ │ ├Yao The Rise of Granular Computing p10.pdf
│ │ └Zomaya Handbook of Nature-Inspired and Innovative Computing p737.pdf
│ ├<organic>
│ │ ├000organiccomputing.docx
│ │ ├Agarwal Organic Computing p5.pdf
│ │ └Schmeck Organic Computing –a Generic Approach to Controlled Self-organization in Adaptive Systems p61.pdf
│ ├<others>
│ │ ├000others.docx
│ │ ├Klimo Fuzzy Computer Architecture Based on Memristor Circuits_2012_p4.pdf
│ │ └Ozkul Comparative Study of Alternative Computing Technologies for Speed and Density p8.pdf
│ ├<parallel_computing>
│ │ ├000ParallelComputing.docx
│ │ ├Barbara Linear Algebraic Primitives for Parallel Computing on Large Graphs p301.pdf
│ │ ├Bischof Parallel Computing Architectures Algorithms and Applications p830.pdf
│ │ ├Grama Introduction to Parallel Computing Second Edition p612.pdf
│ │ └Parhami Introduction to Parallel Processing Algorithms and Architectures p557.pdf
│ ├<phase_transition_memory>
│ │ ├000phasetransitionmemory.docx
│ │ ├Agarwal Watching Nanoscale Phase Change Memory Work in Real Time via In Situ Electron Microscopy p34.pdf
│ │ ├Burr Phase change memory technology p49.pdf
│ │ ├Cabrera Material Engineering for Phase Change Memory p72.pdf
│ │ ├Lai Phase Change MemoryA Memory Technology for All Applications p26.pdf
│ │ ├Lee PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY p11.pdf
│ │ ├Mittal A Survey of Power Management Techniques for Phase Change Memory p13.pdf
│ │ ├Objective_Analysis_PCM BECOMES A REALITY.pdf
│ │ ├Wong Phase Change Memory p28.pdf
│ │ ├XIONG ULTRA-LOW POWER PHASE CHANGE MEMORY WITH CARBON NANOTUBE INTERCONNECTS p49.pdf
│ │ └ZILBERBERG Phase-Change Memory An Architectural Perspective p33.pdf
│ ├<physarum>
│ │ ├000Physarum.docx
│ │ ├Adamatzky Physarum Chip Project Growing Computers From Slime Mould p5.pdf
│ │ ├Adamatzky Slim moulds are like general purpose computer.pdf
│ │ ├Baumgarten NETWORK COARSENING DYNAMICS IN A PLASMODIAL SLIME MOULD MODELLING AND EXPERIMENTS.pdf
│ │ ├Bonifaci Physarum Can Compute Shortest Paths.pdf
│ │ ├Douglas Slime molds.pdf
│ │ ├Physarum-Chip-Project-Growing-Computers-from-Slime-Mould.pdf
│ │ ├Schumann Physarum Syllogistic L-Systems.pdf
│ │ ├Schumann PhysarumSoft - a Software Tool for Programming Physarum Machines and Simulating Physarum Games.pdf
│ │ ├Schumann p-Adic Mathematics in Behavioural Models. The Case of Physarum Polycephalum.pptx
│ │ ├Schumann Timed Transition System Models for Programming Physarum Machines p4.pdf
│ │ ├Smith Whats Bugging You Slime Molds.pdf
│ │ ├Stepney Programming Unconventional Computers Dynamics,Development, Self-Reference.pdf
│ │ ├Tsuda The Phi-Bot A Robot Controlled by a Slime Mould.pdf
│ │ ├Tsuda Towards Physarum engines.pdf
│ │ └Zou Algorithms and Models for Genome Biology.pdf
│ └<strained_silicon>
│ ├000strained_silicon.docx
│ ├Bohr The Invention of Uniaxial Strained Silicon Transistors at Intel p4.pdf
│ ├Bulsara Strained Silicon Substrate TechnologyCommercialization Fundamentals p5.pdf
│ ├Chaudhry Mobility Models for Unstrained and Strained Silicon MOSFETS A Review p19.pdf
│ ├CHAUDRY REVIEW OF CURRENT STRAINED SILICON NANOSCALE MOSFET STRUCTURES p8.pdf
│ ├González Si, SiGe, Strained Si p76.ppt
│ ├Goyal Design and simulation of strained-Sistrained-SiGe dual channel hetero-structure MOSFETs p123.pdf
│ ├Habicht Strained and Unstrained Silicon Nanowire-Array MOSFETs Fabrication and Physical Analysis p154.pdf
│ ├Hamid Characterization and Fabrication of 90nm Strained Silicon PMOS using TCAD p7.pdf
│ ├Huang Electrical and Material Properties of Strained SiliconRelaxed Silicon Germanium Heterostructures for Single-Electron Quantum Dot Applications p127.pdf
│ ├LeeStrained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors p27.pdf
│ ├Lin Advanced Gate Stacks for Strained Silicon Devices p195.pdf
│ ├Lu Strained Silicon Technology Mobility Enhancement and Improved Short Channel Effect Performance by Stress Memorization Technique on nFET Devices p4.pdf
│ ├Madan PHYSICAL UNDERSTANDING OF STRAINED-SILICON AND SILICON GERMANIUM FETS FOR RF AND MIXED-SIGNAL APPLICATIONS p81.pdf
│ ├Pe?i?-Br?anin Strained Silicon Layer in CMOS Technology p7.pdf
│ ├Prager Strained Silicon p23.ppt
│ ├Ramakrishnan Strained Silicon Technology for Low-Power High-Speed Circuit Applications p203.pdf
│ ├Reiche Strained Silicon Devices p11.pdf
│ ├Schriever Strained Silicon Photonics p20.pdf
│ ├SUN POWER METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH STRAINED SILICON AND SILICON GERMANIUM CHANNEL p104.pdf
│ ├Takagi Strained-Si CMOS Technology p21.pdf
│ └Xu Effectiveness of Strain Solutions for Next-Generation MOSFETs p103.pdf
└<zzznot_chips>
├<amorphous>
│ ├000AmorphousComputing.docx
│ ├Abelson Amorphous Computing p20.pdf
│ ├Abelson Amorphous Computing p35.pdf
│ ├PRASAD AMORPHOUS COMPUTING AND SWARM INTELLIGENCE p35.pdf
│ └Streletz Amorphous Computing p55.ppt
├<artificialimmune>
│ └artificialimmune.docx
├<atom>
│ ├AtomChip.docx
│ ├CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319.pdf
│ └Wilzbach Single atom detection on an atom chip with integrated optics p184.pdf
├<crystallizationcomputers>
│ └000crystallizationcomputers.docx
├<dynamical_systems_computing>
│ ├000dynamicalsystemscomputing.docx
│ ├<biomemsXXX>
│ │ ├00biomems.docx
│ │ ├Bashir Introduction to BioMEMS & Bionanotechnology Lecture 1 p38.pdf
│ │ ├Chapter 1 Introduction to BioMEMS p11.pdf
│ │ ├Lan BIO-MEMS.pdf
│ │ ├Nikos BioMEMS (and Microfluidics) p36.pdf
│ │ ├Senez Introducing BioMEMS and their applications to electrical engineer students p17.pdf
│ │ └Wang Bio-MEMS Technologies and Applications p463.pdf
│ ├Bournet On the computational power of dynamical systems and hybrid systems p43.pdf
│ └Verstraeten Reservoir Computing computation with dynamical systems p190.pdf
├<evolutionary>
│ └evolutionary.docx
├<gas>
│ └000gas_discharge_analogue_path_finders.docx
├<genetic>
│ ├000geneticcircuits.docx
│ ├000Siuti Engineering genetic circuits that compute and remember p9.pdf
│ ├Ang Designing Synthetic Gene Circuits for Homeostatic Regulation and Sensory Adaptation p100.pdf
│ ├Jusiak Synthetic Gene Circuits p56.pdf
│ ├Madsen Stochastic Analysis of Synthetic Genetic Circuits p148.pdf
│ └Myers Genetic Circuit Design p66.pdf
├<Lsystems>
│ └000Lsystems.docx
├<maze>
│ └000maze_solving_micro_fluidic_circuits.docx
├<physiologicalcomputing>
│ └PHYSIOLOGICALCOMPUTING.docx
└<roll-away_computer_flexible_electronics>

2017-02-11


graphene chips

(2017-07-01 -- 2018-07-01)

graphene chips 石墨烯芯片
graphphene transistor

graphene chips 石墨烯芯片
graphene transistor

graphene chips 石墨烯芯片
graphphene transistor

graphene chips 石墨烯芯片
graphene transistor

graphene field-effect transistors (GFET)

can graphene field-effect transistors (GFET) replace CMOS?

can graphene replace CMOS?

IBM builds graphene chip that’s 10,000 times faster, using standard CMOS processes By Sebastian Anthony on January 30, 2014 at 9:28 am

http://graduate.physics.sunysb.edu/announ/theses/vora-heli-august-2014.pdf

[Anteroinen2011]

Anteroinen Structure and Electrical Characteristics of Graphene Field Effect Transistors p71

Anteroinen Structure and Electrical Characteristics of Graphene Field Effect Transistors p71
2011

Johanna Anteroinen

http://www.spinverse.com/contact/johanna-anteroinen/

johanna.anteroinen@spinverse.com

Prof. Harri Lipsanen

https://people.aalto.fi/new/harri.lipsanen

harri.lipsanen@aalto.fi

2017-07-15 sent

All-Graphene Three-Terminal Junction Field-Effect Devices as Rectifiers and Inverters

Kim, Wonjae; Li, Changfeng; Chekurov, Nikolai; Arpiainen, Sanna; Akinwande, Deji; Lipsanen, Harri; Riikonen, Juha
2015 in ACS NANO
ISSN: 1936-0851

Toward efficient graphene fabrication and ultrafast characterization

Riikonen, Juha; Kim, Kim; Li, Changfeng; S?yn?tjoki, Antti; Karvonen, Lasse; Lipsanen, Harri
2014

Investigation of optical nonlinearities in graphene and layered semiconductors by multiphoton microscopy

Karvonen, Lasse; S?yn?tjoki, Antti; Mehravar, Soroush; Riikonen, Juha; Peyghambarian, Nasser; K.Kieu, Khanh; Lipsanen, Harri
2014

Photo-thermal chemical vapor deposition of graphene on copper

Riikonen, Juha; Kim, Wonjae; Li, Changfeng; Svensk, Olli; Arpiainen, Sanna; Kainlauri, Markku; Lipsanen, Harri
2013 in CARBON
ISSN: 0008-6223

Nonlinear behavior of three-terminal graphene junctions at room temperature

Kim, Wonjae; Pasanen, Pirjo; Riikonen, Juha; Lipsanen, Harri
2012 in NANOTECHNOLOGY
ISSN: 0957-4484

Growth of CVD graphene on copper by rapid thermal processing

Kim, Wonjae; Riikonen, Juha; Arpiainen, Sanna; Svensk, Olli; Li, Changfeng; Lipsanen, Harri
2012

Graphene for Gigahertz Applications

Anteroinen, Johanna; Kim, Wonjae; Stadius, Kari; Riikonen, Juha; Lipsanen, Harri; Ryyn?nen, Jussi
2012
ISBN: 978-9949-23-265-9

Rapid Thermal CVD of Graphene on Copper

Arpiainen, Sanna; Svensk, Olli; Kim, Wonjae; Kainlauri, Markku; Jiang, Hua; Lipsanen, Harri
2011

Nonlinear behavior of three terminal graphene junctions at room temperature

Kim, Wonjae; Pasanen, Pirjo; Riikonen, Juha; Rouvala, Markku; Lipsanen, Harri
2011

Electrical Properties of CVD-Graphene FETs

Anteroinen, Johanna; Kim, Wonjae; Stadius, Kari; Riikonen, Juha; Lipsanen, Harri; Ryyn?nen, Jussi
2011

Circuits based on graphene transistors

Rouvala, Markku; Kim, Wonjae; Pasanen, Pirjo; Riikonen, Juha; Stadius, Kari; Ryyn?nen, Jussi; Lipsanen, Harri
2010

D.Sc. (Tech.) Kari Stadius

https://research.aalto.fi/portal/kari.stadius.html

kari.stadius@aalto.fi

Towards High-Frequency Graphene Electronics

Anteroinen, J., Kim, W., Stadius, K. & Ryyn?nen, J. 2013 XXXIII Finnish URSI Convetion on Radio Science and SMARAD Seminar 2013, Espoo, Finland, April 24-25, 2013. p. 169-172

Graphene for Gigahertz Applications

Anteroinen, J., Kim, W., Stadius, K., Riikonen, J., Lipsanen, H. & Ryyn?nen, J. 2012 Swedish Radio and Microwave Days, Solna, Sweden, March 6-8.2012.

Prof. Jussi Ryyn?nen

Jussi Ryyn?nen

https://people.aalto.fi/new/jussi.ryynanen

jussi.ryynanen@aalto.fi

Juha Riikonen

http://www.spinverse.com/contact/juha-riikonen/

juha.riikonen@spinverse.com

Anteroinen Graphene Transistors -Challenges and Opportunities p103

[Aroutiounian2013]

Aroutiounian Band Gap Opening in Graphene p8
Vladimir Aroutiounian

Aydogan Monitoring the operation of a graphene transistor in an integrated circuit by XPS p5
Pinar Aydogan

[Aydogan2016]

20 June 2016

???????????????????????????????????????

M.-H. Bae, Z.-Y. Ong, D. Estrada, and E. Pop, “Infrared microscopy of joule heating in graphene field effect transistors,” in Nanotechnology, 2009. IEEE-NANO 2009. 9th IEEE Conference on, july 2009, pp. 818 –821.

Banadaki Power and Delay Performance of Graphene-based Circuits Including Edge Roughness Effects p12

Banerjee Non linear behaviour of three terminal graphene devices p74

???????????????????????????????????????

S. K. Banerjee, L. F. Register, E. Tutuc, D. Basu, S. Kim, D. Reddy, and A. H. Mac-
Donald, “Graphene for cmos and beyond cmos applications,” Proceedings of the IEEE,
vol. 98, no. 12, pp. 2032 –2046, December 2010.

??????????????????????????

[Banerjee2000]

Banerjee Novel Transistor Concepts Based on 2D Systems‐ Graphene and Topological Insulators p47

(2000)

6

?????????????????????????????

Benfdila Graphene Material and Perspectives for Nanoelectronics p9
A. Benfdila

4

Britnell Field-Effect Tunneling Transistor Based on Vertical Graphene Heterostructures p14
L. Britnell

Chahardeh A Review on Graphene Transistors p5
Javad Bavaghar Chahardeh

Ferrari Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems p213

GALIB Graphene grown by chemical vapor deposition on evaporated copper thin films p31
O.F.M.ABDUL GALIB

B. Hardwidge, “Ibm: Graphene as it is won’t replace silicon in cpus,” January 2011. [Online]. Available:
http://www.bit-tech.net/news/hardware/2011/01/21/ibm-graphene-wont-replace-silicon-cpus/1

okokok
Hutchison Graphene Computer Chips

okokok
Hutchison Graphene Computer Chips

Jena Tunneling Transistors Based on Graphene and 2-D Crystals p18
Graphene-based tunneling transistors and how these compare to 2-D transistors made
from the GaAs/AlGaAs materials systems is the topic of discussion in this paper.
By Debdeep Jena

Jo Large-areagraphenesynthesisanditsapplicationtointerface-engineered field effecttransistors p9
Sae Byeok Jo

S. Kim, J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, and S. K.
Banerjee, “Realization of a high mobility dual-gated graphene field-effect transistor
with al[sub 2]o[sub 3] dielectric,” Applied Physics Letters, vol. 94, no. 6, p. 062107,
2009. [Online]. Available: http://link.aip.org/link/?APL/94/062107/1

Klekachev Graphene Transistors and Photodetectors p6

Lee Graphene Nanoelectronics - From Synthesis to Device Applications p158

M. Lemme, T. Echtermeyer, M. Baus, and H. Kurz, “A graphene field-effect device,”
Electron Device Letters, IEEE, vol. 28, no. 4, pp. 282 –284, april 2007.

Lemme Current Status of Graphene Transistors p11

2009

Y.-M. Lin, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, A. Grill, and P. Avouris, “100-GHz Transistors from Wafer-Scale Epitaxial Graphene,” Science, vol. 327, no. 5966, p. 662, 2010. [Online]. Available: http://www.sciencemag.org/content/327/5966/662.abstract

Y.-M. Lin, K. Jenkins, A. Valdes-Garcia, J. Small, D. Farmer, and P. Avouris, “Operation
of graphene transistors at gigahertz frequencies,” Nano Letters, vol. 9, no. 1, pp.
422–426, 2009. [Online]. Available: http://pubs.acs.org/doi/abs/10.1021/nl803316h

Lin Enhanced Performance in Epitaxial Graphene FETs With Optimized Channel Morphology p3
Yu-Ming Lin

Lindgren Electrochemical Functionalization of Epitaxial Graphene p55
2015

?????????????????

Lindgren Electrochemical Functionalization of Epitaxial Graphene p55
12

Mahmood Towards Graphene based mono-molecular electronics: Structural and electrical characterization of side-gated devices p214

MAJUMDAR Theory of High Field Transport in Graphene Transistor p12
KAUSIK MAJUMDAR

I. Meric, M. Y. Han, B. Ozyilmaz, P. Kim, and K. L. Shepard, “Current saturation in zero-bandgap, top-gated graphene field-effect transistors,” Nature Nanotechnology, vol. 3, pp. 654–659, 2008. [Online]. Available:
http://dx.doi.org/10.1038/nnano.2008.268

I. Meric, C. Dean, A. Young, J. Hone, P. Kim, and K. Shepard, “Graphene fieldeffect
transistors based on boron nitride gate dielectrics,” in Electron Devices Meeting
(IEDM), 2010 IEEE International, dec. 2010, pp. 23.2.1 –23.2.4.

okokok
MEIER Chips from a Sheet

okokok
Nouchi Metal-contact effect on grapheme p11

2010

K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A. Firsov, “Electric Field Effect in Atomically Thin Carbon Films,” Science, vol. 306, no. 5696, pp. 666–669, 2004. [Online]. Available:
http://www.sciencemag.org/cgi/content/abstract/306/5696/666

Parrish A Compact Model for Graphene FETs for Linear and Non-linear Circuits p4
Kristen N. Parrish

Pascal Graphene three-terminal nanojunction rectifiers p124

Pollard Growing Graphene via Chemical Vapor Deposition p47

Ponomarenko Tunable metal–insulator transition in double-layer graphene heterostructures p11
L. A. Ponomarenko

RAHMAN Growth of Graphene on Nickel using a Natural Carbon Source by Thermal Chemical Vapor Deposition p7
(Penumbuhan Grafin di atas Nikel dengan Menggunakan Sumber Karbon Semula
Jadi Melalui Pemendapan Berhaba Wap Kimia)
SHAHARIN FADZLI ABD RAHMAN

Rizzi On the fabrication and characterization of high-performance graphene electronic devices p81
Laura Giorgia Rizzi

Ruiz-Vargas SYNTHESIS, MORPHOLOGY AND PROPERTIES OF POLYCRYSTALLINE GRAPHENE MEMBRANES p134

okokok
SAGAR Graphene-based Field-effect Transistors p113

okokok
SAGAR Graphene-based Field-effect Transistors p113
Adarsh Singh SAGAR
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post-silicon electronics devices

okokok
Sahu Will graphene replace silicon in computer chips

F. Schwierz, “Graphene transistors,” Nature Nanotechnology, vol. 5, pp. 487–496,
2010. [Online]. Available: http://dx.doi.org/10.1038/nnano.2010.89

okokok
Schwierz Graphene Transistors p35

2012

F. Schwierz, “Electronics: Industry-compatible graphene transistors,” Nature, vol. 472,
pp. 41–42. [Online]. Available: http://dx.doi.org/10.1038/472041a

Sharma Graphene based field effect transistors: Efforts made towards flexible electronics p12
Bhupendra K. Sharma

Singh Quantum Hall Effect and Electromechanics in Graphene p186

okokok
Sordan Gigahertz Multi-Transistor Graphene Integrated Circuits p7

2013

R. Sordan, F. Traversi, and V. Russo, “Logic gates with a single graphene transistor,”
Applied Physics Letters, vol. 94, no. 7, p. 073305, 2009. [Online]. Available:
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Sreenath Compact model for switching characteristics of graphene field effect transistor p8
R. Sreenath

Suk Enhancement of the Electrical Properties of Graphene Grown by Chemical Vapor Deposition via Controlling the Effects of Polymer p6
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Ji Won Suk

okokok
Tahy Graphene Transistors p29

2010

S. Thiele, J. Schaefer, and F. Schwierz, “Modeling of graphene metal-oxidesemiconductor
field-effect transistors with gapless large-area graphene channels,”
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Thiele Carbon Nanotubes and Graphene for Electronics Applications 2010-2020 Technologies, Players & Opportunities p228

okokok
van den Berg ConceptGraphene New Electronics Concept: Wafer-Scale Epitaxial Graphene p10

2013

okokok
ConceptGrapheneD25Report

okokok
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Vargas-Bernal Carbon Nanotube- and Graphene Based Devices, Circuits and Sensors for VLSI Design p28
Rafael Vargas-Bernal

okokok
Vaziri Fabrication and Characterization of Graphene Field Effect Transistors p48

2011

Wall Uncovering the Secrets Governing the Chemical Vapor Deposition of Graphene with Rapid Raman Imaging p4
Mark H. Wall

X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, and H. Dai, “Room-temperature
all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors,” Phys.
Rev. Lett., vol. 100, no. 20, p. 206803, May 2008. [Online]. Available:
http://prl.aps.org/abstract/PRL/v100/i20/e206803

Y. Wu, Y.-M. Lin, K. Jenkins, J. Ott, C. Dimitrakopoulos, D. Farmer, F. Xia, A. Grill,
D. Antoniadis, and P. Avouris, “Rf performance of short channel graphene field-effect
transistor,” in Electron Devices Meeting (IEDM), 2010 IEEE International, dec. 2010,
pp. 9.6.1 –9.6.3.

Y. Wu, Y. Lin, A. Bol, K. Jenkins, F. Xia, D. Farmer, Y. Zhu, and P. Avouris,
“High-frequency, scaled graphene transistors on diamond-like carbon,” Nature, vol.
472, pp. 74–78. [Online]. Available: http://dx.doi.org/10.1038/nature09979

Wu Graphene Electronics: Materials, Devices, and Circuits p18
This paper demonstrates the use of graphene transistors in a four-port RF mixer.
This mixer is capable of operating at frequencies up to 10 GHz.
By Yanqing Wu

J. L. Xia, F. Chen, P. Wiktor, D. K. Ferry, and N. J. Tao, “Effect of top dielectric
medium on gate capacitance of graphene field effect transistors: Implications in
mobility measurements and sensor applications,” Nano Letters, vol. 10, no. 12, pp.
5060–5064, 2010. [Online]. Available: http://pubs.acs.org/doi/abs/10.1021/nl103306a

okokok
Xia Graphene Field-Effect Transistors with High On/Off Current Ratio and Large Transport Band Gap at Room Temperature p4

2009

okokok
Yan Graphene-based flexible and stretchable thin film transistors p13

2012

Yang Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier p5
Heejun Yang

Yeric Graphene for Future VLSI p59

okokok
Zhao SymFET: A Proposed Symmetric Graphene Tunneling Field Effect Transistor p7

2013


graphene chips

(2017-07-01 -- 2018-07-01)
IBM, the company leading the graphene research, has already stated that it is unlikely that graphene would ever replace silicon technology [33].

Graphene basics

Graphene is a 2D material

Graphene is a single layer of sp2-bonded carbon atoms, that are packed in a honeycomb lattice [2].

Graphene has a honeycomb (hexagonal) structure of sp2-bonded atoms.

The honeycomb lattice has 2 atoms per unit cell, hence the  bands of graphene have 2 x 2 Hamiltonian. The diagonal elements of the Hamiltonian describe the nearest neighbour interactions, while the off-diagonal elements describe the three nearest neighbour interactions in different sublattices.

bi-layer graphene

Bilayer graphene has two layers, but the electronic band structure is already quite different from single layer graphene. Band gaps of some hundreds of millielectron volts have been achieved with bilayer graphene by applying a perpendicular electric field to the bilayer [13].

The gap in Bernal stacked bilayer graphene arises from the forming of pseudospins between the layers, thus making it possible to electrically induce a band gap [14].

multilayer graphene can have up to ten layers, and still be called graphene.

Few layer graphene (FLG) has three to nine layers.

The limit where graphene becomes graphite is ten layers. If graphene is stacked vertically to hundreds
of layers, it would form three dimensional graphite.

When graphene is rolled into a tube, graphene forms 1D carbon nanotubes,

when graphene is rolled into in a ball shape it forms 0D fullerenes.
electrons and holes in graphene have not a mass and are Dirac–fermions and obey the linear energy dispersion.

high electron mobility

The most interesting electrical properties are high electron mobility and ballistic transport of charge carriers.

A high mobility value means a fast transistor.

Graphene has shown ultrahigh intrinsic carrier mobility, up to 200,000–250,000 cm 2 V –1 s –1 at low temperatures, a room-temperature mobility of ~ 10 000- 20 000 cm 2 V –1 s –1 was measured.

mobility parameters
Mobility is restricted by scattering caused by perturbations in the periodic lattice and by impurities [26].
Unlike semiconductor materials, such as silicon, graphene doesn’t have to be doped with impurities, which is in part the reason why graphene devices show very high mobilities.
The mobility of charge carriers is limited by defects in the supporting material or defects in graphene.

The previous claimis backed up by the much higher mobilities achieved with suspended graphene
sheets.

Electronic transport that is limited by scattering is called ballistic transport. Ballistic transport is possible in very pure and defect free graphene. Naturally, obtaining clean and defect free graphene is difficult and is often not achieved.

The electronic dispersion in graphene

The linearity of band dispersion in graphene means that the velocity of electrons is independent of energy or momentum. Furthermore, the velocity of electrons in graphene is at maximum the Fermi velocity, which
is 1/300 of the speed of light.

Another intriguing property is that backscattering through phonons or charged impurities is forbidden and the mean free path is in the range of hundreds of nanometres.

enhanced mobility due to better dielectric deposition and high-k material.
Drude model of electrical conduction can be used to calculate the conductivitymobility if the
sample length is much larger than the transport mean free path [39]. The transport mean free path for graphene is estimated to be around 100 nm, therefore the Drude model is applicable for samples in the micrometer range [22].

There are three types of mobilities that can be defined for a metal-oxide-semiconductor FET;

field-effect mobility/ Low field field-effect mobility

effective mobility

saturation mobility [26]

Hall mobility

conductivity mobilities

carrier mobilities
the mobility of graphene transistors is not so well defined figure of merit. It is not always clear which definition for mobility has been used in the previous studies on GFETs.
extract the mobility from measurements
The first one is to measure the transport curve -Vg and use the Equation μ = /(CgVg)
to fit mobility in a linear regime. This methods suffers from the fact that the transport curve is nonlinear, and choosing a linear regime is somewhat arbitrary.
The second method is to calculate the conductivity mobility with the equation below
μ =

nq
=

Cg(Vg ? Vdrc)
(2.9)
Equation (2.9) depends on charge carrier density or gate voltage. The problem with the second method is that it doesn’t apply near the Dirac point because the carrier density is not well-defined.

The third method is to use curve fitting to total resistance vs. gate voltage measurement. The third method is used in this thesis and the equations (4.3) that are used
to fit the curve are shown in Chapter 4.

Xia et al. [44] studied the effect of top dielectric medium on back gate capacitance. The observation is that the gate capacitance can increase by 2 orders of magnitude when the top gate dielectric size is varied, while the mobility stays constant. This could enable new types of GFET based sensors.

zero-bandgap

Actually, graphene is a zero-band gap 2D semimetal.

graphene is zero-bandgap semiconductor, or semimetal. The lack of bandgap in intrinsic graphene is perhaps, together with large scale manufacturing, the most difficult engineering issue. The zero-bandgap means that graphene cannot be switched from conductive state to non-conductive state. The lack of a band gap is a problem, if graphene is to be used in logic circuits in much the same way as silicon is used today as the material in complementary metal-oxide semiconductor logic circuits [3].
The band-structure of graphene differs from the band-structures of semiconductors in that the energy dispersion around the band edges is linear instead of quadratic [17].
Graphene room temperature on-off current ratios are not yet good enough for logic circuits.

The electronic band structure of graphene can be solved with tight binding approximation (TBA) or the similar linear-combination of atomic orbitals (LCAO), which is more commonly used in chemistry.
Even the existence of a band gap in large area graphene is controversial.

graphene with band gap, either bilayer or band engineered
In addition to band gap opening in bilayer graphene by applying an electric field,

One possibility to open the band gap in graphene is to use bilayer graphene combined with electric field or magnetic field (see Fig.2).

The existence of an energy gap between the conduction and valence bands makes possible for graphene to act as a semiconductor. In double-layer graphene, the conical conduction and valence bands meet at a point – the band gap is absent. Electrical fields (arrows) introduce asymmetry into the bilayered structure (bottom), yielding tuned band gap (Δ) that can be selective.
The band gap of bilayer graphene can be opened larger (up to 3.3 eV) by combination of strain (along z axis) and electrical field (Fig.3)
it is possible to create band gap by quantum confinement, i.e. by fabricating graphene nanoribbons [2].
The next strategy to open the band gap of graphene is to introduce a quantum confinement effect of carriers by narrowing the width of graphene to a nanometer scale. Such graphene called nanoribbon (NR). NRs were used as channels in FETs. The band gap since ~30 meV up to ~500 meV and corresponding FETs were reported when NRs were prepared with minimum width ~1 nm – several nm. A direct to indirect band gap transition is possible in NR by the application of an external bias along the width of NR.
Numerical modelling shows that strain induced band opening is also a possibility, though there is no experimental verification of strain induced band opening [16].
Band engineering of graphene is essential if graphene is ever to compete with silicon CMOS technology [14]. The energy gap is important for logic gate purposes to keep the power consumption at minimum i.e. going to a non-conductive state.
Epitaxial growth of graphene on the carbon face of SiC under vacuum leads to a gap of ≈?0.26 eV. This gap originates from the breaking of sublattice symmetry due to the graphene–substrate interaction. Recently, the research group at IBM has demonstrated SiC-based graphene field-effect transistors with a cutoff frequency over 300 GHz, which is very important for nanoelectronics. It is expected that graphene devices will operate in the terahertz frequency range and use for spintronics.
Graphene made on a Cu foil also can have the band gap under the strain.
The band gap in graphene can be opened also under infrared laser beam or at high level of humidity (0.26-0.73 eV) etc.
The band gap in graphene can be opened also under infrared laser beam or at high level of humidity (0.26-0.73 eV) etc.

other electrical properties
inaddition to mobility
Drain Current
Current Saturation

In order for the electron velocity to saturate, all electrons would need to move in the same direction in graphene [14].

This requires a driving voltage, that is greater than the Fermi energy,

but electron-electron interactions in graphene may make velocity saturation impossible.

Furthermore, hot spots emerge when under high current bias [45].

These hot spots show that current tansport in an irregular shaped graphene sheet is non-uniform.

Chen et al. [21], claim to have observed conductance saturation.

Their view is that in low carrier densities (low electric field strength) the long-range Coulomb scattering dominates and gives rise to the linear regime, whereas at high carrier densities the transport
is dominated by short-range scattering [21].

Meric et al. [40] demonstrated in 2008 a graphene FET with current saturation.

The current saturation demonstrated was incomplete, which raises the question, is it even possible to have complete saturation in graphene?

The exact mechanisms of current saturation in graphene are a topic of speculation. Meric et. al suggest that current saturation depends on charge carrier concentration influenced by interfacial phonon scattering in the SiO2 layer supporting the graphene channels.

Current saturation in graphene shown in Figure 2.9, has three regions. In the first region, the charge is carried by holes in the whole channel length. The second region shows a pinch-off region at the drain when the carrier minimal density point is reached. In the third section electrons start to form the channel.

For high-field regime unipolar channel, Meric et. al find that the carrier drift velocity saturates due to optical-phonon scattering. The current becomes independent of the drain-source voltage

Id =
W
L
Z L
0
qn(x)vdrift(x) dx (2.10)
where W is the channel width and L the channel length. The carrier drift velocity can be modelled as
vdrift =
μE
1 + μE/vsat
(2.11)
where E is the electric field and μ is the carrier mobility. The saturation velocity vsat can be expressed as
vsat =
vF~

EF
(2.12)
where ~ is the optical phonon energy.

Meric et al. [40] approximated the carrier concentration in the channel with a field effect
model
n(x) =
q
n20
+ [Ctop(Vgs?top ? V (x) ? V0)/q]2 (2.13)
where V0 is the device threshold voltage, V (x) is the potential in the channel, Ctop is the top gate capacitance consisting of electrostatic capacitance and quantum capacitance in series
and Vgs?top is the top gate voltage.

There are naturally other ways to calculate the carrier concentration, such as using the Fermi-Dirac distribution, as in [36].

Thiele et al. [36] used the same formulae as Meric et al. [40] to qualitatively investigate
the operation of GFETs. Thiele et al. improved the formula for saturation velocity from
Equation (2.12) to
vsat =

(sh)0.5+AV 2(x)
(2.14)
where A is a dimensionless empirical factor of the order of 10?3. The previous equation is an
empirical equation aimed to correct the overestimation of carrier-phonon interactions [36].

Barreiro et al. [46] studied a Hall-bar device, with a four-point configuration for measuring. The four-point configuration is employed to minimize the contribution of contact resistance at the graphene-electrode interface. Barreiro et al. report that their device has a tencency to saturate, but that complete saturation was not observed. Barreiro et al. explain that in lowfield, elastic scattering is the dominating process, and with higher fields, the optical phonon emission is activated leading to current saturation. Elastic scattering is caused by crystal defects in graphene.

Barreiro et al. claim that in order to have full saturation of current, the phonon emission would have to be instantaneous and elastic scattering processes would have to be negligible, which is impossible. Thus, current saturation is never complete at high fields. The high-field transport is sensitive to elastic scattering. Hot-phonon processes are expected to have a very small impact on the high-field transport. Barreiro et al. claim that the mobility would need to be increased by at least one order of magnitude to achieve high field current saturation [46].
current saturation velocity

The GFET intrinsic current gain follows the 1/f frequency dependence
DC circuit model and MOSFET small-signal model

mechanical properties
Mechanical and thermal properties of graphene are similar to those of carbon nanotubes.
the breaking strength of graphene is around 40 N/m

thermal properties
Mechanical and thermal properties of graphene are similar to those of carbon nanotubes.
thermal conductivity in the range of 5000W/mK,

The chemistry of graphene
Graphene can absorb and desorb different atoms and molecules, such as K and OH. Adsorbates can affect the electronic properties of graphene. There is even the possibility of localized doping.

the stability of graphene

In addition, the stability of graphene under various circumstances has not received much attention.

graphene preparations and manufacturing / Graphene Synthesis
produce graphene flakes with a technique called mechanical exfoliation or ’Scotch tape method’,
First, a piece of bulk graphite is repeatedly peeled with tape to separate layers of graphene, which is then
transferred onto a substrate, usually silicon dioxide SiO2 [2].
graphene grown with chemical vapor deposition (CVD)

Growing graphene with CVD is an attractive solution, because it is compatible with existing semiconductor industry processes [14].

Graphene has been grown with CVD on metal substrates, such as nickel (Ni) and copper (Cu).

With CVD, the graphene layer needs to be transferred to a substrate, which is somewhat difficult and may degrade the quality of the layer and lead to folding of the layer.

However, CVD synthetized graphene has larger grain size.

Researchers are optimistic about extending CVD growth to silicon wafer sizes.
The CVD GFETs were found to give much higher currents with lower drain-source voltage than the SiC GFETs. Also, the CVD GFETs had much less unintentional doping than the SiC GFETs, meaning that the Dirac points were usually found in the region of 0 to -10 V. S-parameters measurements were performed on the CVD GFETs.

GFET structure is as follows from bottom of the device:

  • back gate,
  • 300 nm layer of SiO2,
  • FLG graphene and
  • 25 nm Al2O3 as top gate dielectric.
  • The electrodes are similar to the ones in SiC GFETs, but the thickness of the gold layer on top of titanium layer was increased, because the probe tips damage the gold layer.

The shortest gate length transistors were found to operate similarly to the longer gate length transistors,

However, the gate effect is much weaker in the short gate length devices. It is possible that short-channel effects are the cause for diminished gate effect.

the short gate length GFETs have the highest current and current density.
The back-gate gives more freedom in adjusting the terminal transconductance [24].
the GFET is unable to provide amplification.
The GFETs studied showed cut-off frequencies between 30-80 MHz. Figure 4.16 shows that the highest cut-off frequency is achieved with -10 V at top gate. The relatively low fieldeffect and quite high contact resistance limit the operation.
and silicon carbide (SiC) desorption method [14].

Graphene can be synthetized by sublimation of silicon from SiC in high temperature (1200C) in ultra high vacuum [18].

The benefit of this method is that the SiC provides an insulating substrate and no transfer of the graphene layer is needed in order to fabricate top gated FETs.

Yet, the disadvantage of this method may outweigh its advantages; the high temperature is cost-ineffective, and thus may not be suitable for large scale manufacturing.

The graphene layer has different properties depending on the crystal growth face [8].

Graphene grown on Si-terminated face has poor homogeneity and crystal quality and is subject to unintentional doping.

Graphene grown on C-terminated SiC is often called ’turbostatic’ graphene, because of the rotatiotal disorder. Graphene grown on C-face has higher mobility than on Si-face and has less doping.
the SiC GFETs were found to be of very non-uniform quality with very low terminal transconductance. Due to the low transconductance of the GFETs, it was not possible to measure radio frequency characteristics with S-parameter measurement of the SiC GFETS.
The SiC GFET structure is as follows from bottom of the device: 500 nm of SiC, FLG graphene and 40 nm Al2O3 as top gate dielectric. The electrodes are 5nm of titanium with 40 nm of gold on top.
the uniformity of the transistors is very poor
the SiC GFET process variation is high
The random locations of Dirac points may be due to unintentional doping, poor gate dielectric or defects in the graphene layer
The calculated cut-off frequency of the SiC GFETs is so low that the VNA would not have been able to measure it.
epitaxial SiC process
GFETs were fabricated on a 2 inch graphene wafer. The gate dielectric was a spin-on dielectric poly-hydroxystyrene and HfO2 on top. Lin et al. had promising results with the uniformity of the graphene; the
dirac point was consistently at -3.5V gate bias.
direct chemical synthetization [8]
ion implantation [19]
crystal sonification [8]
unzipping carbon nanotubes to form graphene sheets [20]

Measurement and Testing

graphene layer detection:
Raman spectroscopy can be used to find out if the graphene flakes are single, few- or multilayer.
The doping levels of graphene
The doping levels of graphene can be monitored with Raman scattering [22]. The raman peak intensity and displacement varies according to the applied gate voltage.
contact resistivity measurement
The contact resistivity measurement is based on transmission line model (TLM), in which the metal-semiconductor interface is expected to be ohmic. In the setup a sequence of metal contacts is patterned on
graphene with increasing channel width. The resistances are measured and contact resistivity can then be calculated according to TLM. The sheet resistance of graphene is needed to calculate the conduction length.
Device calibration
Calibration performed in the beginning of measurements is assumed to be valid for one day.
input and output signal analysis
The input and output signals were analyzed with an oscilloscope.
DC measurements
durability measurements
stability measurements
S-parameter measurements

graphene field-effect transistors (GFET)
Graphene FET research was fueled by the discovery of the ambipolar electric field effect in graphene by nobelists Novoselov and Geim in 2004. Novoselov and Geim explain the ambipolar field effect by a 2D metal with a small overlap between valence and conductance bands [4]. The most studied graphene transistor today is the graphene field-effect transistor (GFET). The operation principle of a GFET is based on the ambipolar electric field effect in single and few-layer graphene [4]. The ambipolar field effect is due to a small overlap in the valence and conductance bands. The structure of a GFET resembles that of silicon FETs. The electric current through the device is controlled by the electric field.
The important metrics that must be met in order for graphene logic devices to replace CMOS are room temperature operation, higher speed, scalability and size, device gain and cost. CMOS technology excels in all of the metrics mentioned, and it remains to be seen if graphene logic devices can mature to replace CMOS.
It is claimed in [32], that there will be a trade-off between device size and performance when it comes to scaling down GFETs.
The ambipolarity of graphene makes it possible to operate a graphene transistor with either electrons, holes
or both simultaneously.The graphene bandstructure allows the conduction to shift from electrons to holes by changing the Fermi level.
graphene field effect structure
A graphene field effect structure is constructed from bottom to top as follows: substrate, graphene layer as the channel, dielectric layer and source-drain electrodes and top gate electrode.
GFET channel material, graphene, can be either monolayer, bilayer or few-layer graphene. The operation of the transistor is affected by the number of graphene layers in the channel, because the electrical properties change when going from single layers to few layers.
The back-gate was used to provide electrostatic doping in areas where the top gate does not reach, and thus lower access resistance.
insulating material for a graphene FET

The gate dielectric should be very thin and uniform with high dielectric constant, often denoted with the symbol  [14].

Contrary to choosing metal contacts, the density of states at the interface should be low.

High- materials are important in designing ever smaller transistors. Common high- materials are HfO2 and Al2O3, which can be deposited with atomic layer deposition (ALD) [27].

Graphene is chemically very inert, and this poses difficulties for the deposition of dielectrics. The dielectrics do not stick well to graphene and the use of ALD is challenging because graphene is hydrophobic. The hydrophobic nature of graphene can be circumvented by depositing nucleation centers of aluminium.
self-doping
Graphene is unique as a channel material, because unlike other semiconductors, graphene does not require impurity doping to conduct electricity. Graphene displays a phenomenon that is often called self-doping. Self-doping refers to the electric field effect in graphene, which allows the charge carrier type and concentration to be controlled with an outside electric field, or rather gate voltage.
Das et al. [22] estimated the doping concentration in an electrochemically top gated GFET as
VTG =h ~|vF |pn
e
+
ne
CTG
where F is the Fermi velocity, n the doping concentration, and CTG is the top gate capacitance calculated as a parallel plate capacitor.
Dirac point

The sheet resistivity of graphene was found to have a peak of a few kOhms and decays to some hundreds of Ohms with changing the gate voltage [4].

The resistivity peak, often called dirac point or minimum conductance point, is located approximately at zero gate voltage in pure graphene.

The location of the Dirac point depends on the difference between the work functions of the gate and the graphene, doping (electrical or chemical), and type and density of charges at the interfaces at the top and bottom of the channel.

The Dirac point changes with adsorbed water or other ambient adsorbing molecules [21].

Positive gate voltages promote n-type, electron, conduction and negative voltages give rise to p-type channel (hole conduction).

The 40 nm GFET has the Dirac point at -7V, and is due to impurity doping [32].
transport properties of graphene
transport properties of graphene are affected by the quality of the graphene layer, the interface with insulators and the metal contacts.
Hall coefficient
The Hall coefficient RH changes sign at dirac point [4].The Hall coefficient RH changes sign at dirac point [4].
contact and channel resistance
resistivity
The resistivity  of graphene is described by the classical equation
?1 =  = neμ (2.2)
where n is the doping concentration,  conductivity and μ the mobility of graphene.
reduction in access resistances
contact resistance

The contact between graphene and metal is most often ohmic, but the low density of states (DOS) in graphene may hinder current injection [25].

Typical metals used for contacts are Ti/AU, Cr/Au and Cr/Pt. A general guideline for choosing contact metals is to ensure that the contact is ohmic, and secondly to choose such a metal that its work function is as close to the semiconductor band gap as possible.

Contacts can be deposited with e.g. electron beam lithography [26].

contact resistance is affected by the processes used in fabrication. For example, sputtering leads to larger contact resistance than electron beam (EBM). The higher contact resistance caused by sputtering is possibly due to carbon vacancies in the graphene lattice. Liu et al. propose that the sometimes perceived asymmetry
between hole and electron transport may be due to the contacts changing from p-p-p junction to p-n-p under gate modulation. Interestingly, the contact resistance decreases as the number of graphene layer increases when using sputtering process. The same does not apply for electron beam.

According to [25], the current enters graphene preferentially at the edge of the contact metal instead of from the whole contact area between metal and graphene. For contact lengths shorter than the calculated conduction length, the conduction becomes area conduction. Typical values for graphene sheet resistance is 250 at μ = 5000 cm2/Vs and n = 5 · 1012 cm?2.
The result of [25] is that it is preferable to choose a metal with higher work function than that of graphene to increase the graphene DOS and reduce contact resitivity.

The significance of access resistance grows as the channel length shrinks.

Lin et al. report that they used a back-gate to modulate the access resistance through electrostatic doping.

The back-gate was used to provide electrostatic doping in areas where the top gate does not reach, and thus lower access resistance.

The total resistance of the graphene device was modelled by Lin et al. [24] as the sum of ideal graphene channel resistance modulated by the top gate, and a series resistance Rs
Rtotal = Rs +
2
4eμW
LG
s
n20
+

Ctot
e · (VTG ? VDRC)
2
3
5
?1
(2.3)
Ctot is the total capacitance of the top gate consisting of top gate capacitance and graphene channel quantum capacitance. The top gate dirac voltage is denoted as VDRC and n0 is the minimum sheet carrier density, determined by disorder and thermal excitation.
the cut-off frequency fT is dependent on the dc transconductance gm of the device and is given by
fT = gm/(2Cg) (2.4)
where Cg is the gate capacitance [31]. The cut-off frequency was deduced from S-parameter measurements by Lin et al. [31]. The cut-off frequency is also found to be inversely proportional to the square of the gate length.
dielectric layer
The high cut-off frequency was achieved by using diamond-like carbon (DLC) instead of SiO2 as the dielectric layer [32]. DLC has a higher phonon energy and lower surface trap density than SiO2. The single layer graphene was grown on copper foil at 1000 Celsius degrees and was then transferred on to the DLC using a PMMA as protecting layer and dissolving the Cu with FeCl3.
gate modulation
The GFET has lower gate modulation than longer transistors because the contact resistance has larger role in short channel FETs. The modulation is adversely affected by ’short-channel effects’, i.e. the electrostatic control efficiency of the top gate is reduced by the drain voltage.
short-channel effects
The short-channel effects are not yet well understood in graphene transistors.
conductances, such as transconductance
transconductance
The transconductance of the 40 nm GFET suffers from these short-channel effects and is at aximum roughly
35μS/μm with Vds=0.4 V. The transconductance is expected to decrease when scaling down the GFETs due to Klein tunneling and graphene p-n-junctions.
Terminal transconductance is defined as gmt = dId
dVg
at a constant drain
source voltage.

system capacitances

Quantum capacitance
According to reference [37], the quantum capacitance is influenced by impurities and defects.

Graphene shows a capacitive behaviour under electric field, that is referred to as quantum capacitance.

Quantum capacitance in graphene is due to the peculiar linear energy dispersion.

In graphene field-effect transistors, the graphene/insulator/semiconductor interface the graphene layer adds a capacitor in series with the insulator and semiconductor capacitance contributions. Graphene quantum capacitance is in series with the gate oxide capacitance and must be taken into calculations.

The quantum capacitance of the graphene channel has to be taken into account when the gate dielectric thickness is reduced.

The quantum capacitance is derived from the density of states (DOS) of graphene assuming the Fermi-Dirac distribution for charge carriers [36].

The quantum capacitance of graphene is approximately linearly dependent on the channel voltage quantum capacitance of graphene is linear with respect to the applied top gate voltage and has a minimumvalue around the minimum conductance point [37].

Furthermore, the capacitance is symmetric with respect to the Dirac point [38].

Quantum capacitance is expressed in reference [37] as [Anteroinen2011]

Cq =
2q2kBT
(~vF )2 ln

2

1 + cosh
qVch
kBT

(2.5)
where kB is the Boltzmann constant, ~ the Planck constant and Vch is the voltage over the graphene channel. Equation (2.5) can be simplified to
Cq  q2 2qVch
(~vF )2 =
2q2pn
~vFp
when qVch >> kBT.
BiSFET - Bi-layer pseudoSpin Field Effect Transistor (BiSFET)
Graphene Tunnel FETs
Pseudospintronics in Bilayers at low T, high B
transistor array
A transistor array was fabricated with a conventional topdown process.
graphene amplifier
Yang et al. [34], proposed a triple mode single-transistor graphene amplifier in 2010. The operation is made possible by the ambipolarity of graphene, which enables different points of operation. This device can be considered as proof of concept, though the properties of the proposed graphene amplifier are yet inferior to conventional MOSFET technology. Single transistor graphene amplifiers have several advantages over the current technology. Single transistor amplifiers take less space, and thus use less components and materials. In addition, it is beneficial that the transistor can be configured in-field, which in infeasible with MOSFETs. It has also been suggested that the 1/f noise is quite low in graphene transistors. At the moment, the small transconductance and very low current saturation limit the operation.
basic input logic gates

Sordan et al. [35], have demostrated four basic input logic gates with a single graphene transistor. Needless to say, it is desirable to have fewer transistors. Their idea is similar to the triple mode transistor of Yang et al. Sordan et al. graphene logic gate uses the charge neutrality point to implement boolean logic. The gate values are decoded with resistance values as shown in Figure 2.7.

The logic gates demonstrated, showed promise in the possibility of a configurable logic gate [35]. Alas, there are issues with the proposed design. The fact that graphene cannot be turned off, makes the power consumption unacceptably high. Sordan et al. suggest that the transistor resistance could be increased to lower the static power usage. Then again, a higher resistance would slow the response time of the transistor. Furthermore as the the input and output logic voltage levels are not the same, cascading the gates would require additional transistors.
operation of GFETs

The operation of GFETs near the minimum conductance point has not been thoroughly analyzed yet
operation near the Dirac point

as the operation near the Dirac point is not completely understood. For example, the exact mechanisms leading to widening of the Dirac point to a plateau have not been throughly studied.

Graphene transistors are generally known to exhibit instability in the location of the Dirac point. In top-gate sweep measurements, the location and, at times also the magnitude of the Dirac point would change with each sweep.
graphene cleaning

Graphene is easily contaminated because it is a surface, but there are ways to clean graphene.

First, annealing at ultrahigh vacuum or Ar/H2 environment is proven to clean graphene. The downside of this method is that the graphene samples may recontaminate when transferred from the annealing chamber.

Second method is to clean the graphene samples with driving a relatively high current (milliamperes) through the sample [49]. The current-induced cleaning is easily performed when measuring electrical characteristics of GFETs. The downside of this cleaning method is that the GFET may be damaged in the process, though according graphene can withstand significant currents without damage. This method is based on electromigration and Joule heating.


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Quantum Arithmetic

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

Quantum arithmetic

and function evaluations


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Quantum communication

Quantum communication


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quantum complexity

quantum complexity

QUANTUM COMPLEXITY THEORY


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Quantum device

Quantum device


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quantum electronics

quantum electronics

[ECHTERNACH2001]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

quantum electronics


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quantum Informatics

Quantum Informatics


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quantum information

quantum information

Quantum Information Processing

Quantum Information Engineering

Quantum Information Theory


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Quantum Mechanics

Quantum Mechanics

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

quantum correlation

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

quantum nonlocality

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

quantum transformation

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

quantum time evolution

????????????????????????????????

Ji Yanjiang季燕江 量子力学讲义 p251

2003年7月1日

16
1. 周世勋：《量子力学教程》，高等教育出版社；内容精练。
2. 曾谨言：《量子力学》卷I，科学出版社；内容深入浅出，讲解详细。
3. 曾谨言：《量子力学导论》，北京大学出版社；适合本科生初学使用。
4. 苏汝铿：《量子力学》，高等教育出版社；内容丰富，包括不少量子力 学的新进展。
5. 顾莱纳：《量子力学导论》，北京大学出版社；讲解详细，是作者理论 物理系列教材中的一本。
6. Ramamurti Shankar, Principles of Quantum Mechanics, Plenum Press, (1994). 美国研究生用标准教材。
7. David Bohm, Quantum Theory, Dover Publications (1989). 美国研究 生用标准教材，有中译本。
8. P. A. M. Dirac, The Principles of Quantum Mechanics, Clarendon Press, (1958). 量子力学经典著作，有中译本。
9. 钱伯初、曾谨言：《量子力学习题精选与剖析(上)》, 科学出版社。
10. 扬福家：《原子物理学》，高等教育出版社；有关于量子力学发展的大 量背景资料和对相关物理概念的讨论，适合阅读。


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Quantum Optics

Quantum Optics


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Quantum Physics

Finally I've decided to go back to quantum computing, because all other techniques rely on quantum physics for their further development. On other hand, quantum circuits might be most researched area for the next generations of IC, although its furutre is doubtful. Anyway, quantum physics is the fundamental science for most other IC technologies, therefore I have to study it intensively.

quantum teleportation! [Nielsen2010]
Quantum teleportation is a technique for moving quantum states around, even in the absence of a quantum communications channel linking the sender of the quantum state to the recipient.

????????????????????
????????????????????

Cresser Quantum Physics Notes p238

J D Cresser
31st August 2011
33

DIRAC THE PRINCIPLES OF QUANTUM MECHANICS p322
P. A. M. DIRAC

Fitzpatrick Quantum Mechanics p222
Richard Fitzpatrick

GROENEWOLD ON THE PRINCIPLES OF ELEMENTARY QUANTUM MECHANICS p56
by H. J. GROENEWOLD
Natuurkundig Laboratorium der Rijks-Universiteit

Ji Yanjiang季燕江 量子力学讲义 p251
季燕江(jyj@sas.ustb.edu.cn)
2003年7月1日

Andreas Wallraff

ETH Zurich quantum teleportation in a solid-state circuit

Woit Quantum Theory, Groups and Representations:An Introduction p585
(Final draft version)
Peter Woit

Quantum Entanglement

In short, quantum entanglement means that multiple particles are linked together in a way such that the measurement of one particle's quantum state determines the possible quantum states of the other particles.

Quantum entanglement is a quantum mechanical phenomenon in which the quantum states of two or more objects have to be described with reference to each other, even though the individual objects may be spatially separated.

http://www.ipod.org.uk/reality/reality_quantum_entanglement.asp

http://plato.stanford.edu/entries/qt-entangle/

http://www.extremetech.com/extreme/156673-the-first-quantum-entanglement-of-photons-through-space-and-time

https://en.wikipedia.org/wiki/Quantum_entanglement

https://simple.wikipedia.org/wiki/Quantum_entanglement

http://www.livescience.com/28550-how-quantum-entanglement-works-infographic.html

?

http://dwave.files.wordpress.com/2010/12/weightedmaxsat_v2.pdf

http://dwave.wordpress.com/2011/12/01/vesuvius-a-closer-look-512-qubit-processor-gallery/

24

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

quantum parallelism


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Quantum Probability

Quantum Probability


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Quantum Technologies

Quantum Technologies


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Quantum Theory

Quantum Theory

Peres Quantum Theory Concepts and Methods p464

Quantum Theory:
Concepts and Methods

Asher Peres
Department of Physics,
Technion-Israel Institute of Technology,
Haifa, Israel

1995


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quantum wires

quantum wires? [Chang2004]


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Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

0-C

graph types …… xxx graph

acyclic graphs?? !!!!!!!!!!!!!!!

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

acyclic graph

[Bera2008] Universal Quantum Circuits p12
www.cse.sc.edu/~fenner/papers/univcirc.pdf
Bera Universal quantum circuits p12
Bera Universal Quantum Circuits1 p12
Bera Universal Quantum Circuits p13

acyclic graphs

Westergaard Computational equivalence between quantum Turing machines and quantum circuit families p28

directed acyclic graph

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

directed acyclic graph

[Rotteler2005] R?tteler, Martin: Introduction to Quantum Algorithms Part I: Quantum Gates and Simon’s Algorithm, August 31, 2005 p247

directed acyclic graph

STADELHOFER Evolving blackbox quantum algorithms using genetic programming p13

directed acyclic graph
[Volovich1997] Volovich, I.V.:? Models of Quantum Computers and Decoherence Problem, Proc. of the International Conference on Quantum Information, Meijo University, Nagoya, 4-8 Nov.1997.
directed acyclic graph
[de) Wolf2014] de Wolf, Ronald: Quantum Computing: Lecture Notes, April 2014.

directed acyclic graph

Yamashita An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction p15

directed acyclic graph

[de) Wolf2014]
As in the classical case, a quantum circuit is a finite directed acyclic graph of input nodes,
gates, and output nodes.

Nodes

input nodes
There are n nodes that contain the input (as classical bits); in addition we may have some more input nodes that are initially |0i (“workspace”).

internal nodes
The internal nodes of the quantum circuit are quantum gates that each operate on at most 2 qubits of the state. The gates in the circuit transform the initial state vector into a final state, which will generally be a superposition.

Hu Spectral Descriptors for Graph Matching p15

directed acyclic graph
Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf

directed acyclic graph (DAG)

Antonelli Quantum-Dot Cellular Automata (QCA) Circuit Partitioning Problem Modeling and Solutions p6.pdf

directed acyclic graph
Bera On Finding Sensitivity of Quantum and Classical Gates p15

directed acyclic graph
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

directed acyclic graph

[Bera2008] Universal Quantum Circuits p12
www.cse.sc.edu/~fenner/papers/univcirc.pdf
Bera Universal quantum circuits p12
Bera Universal Quantum Circuits1 p12
Bera Universal Quantum Circuits p13

Directed Acyclic Graphs or DAGs

Brak Logics for Quantum Circuits p62
Brak Logics for Quantum Circuits p62

rooted, directed, acyclic graph

Goodman A QUANTUM CIRCUIT SIMULATOR BASED ON DECISION DIAGRAMS p76

rooted directed acyclic graph
Lin Reversible and Quantum Circuit Synthesis p209

universal directed acyclic graph

[Bera2008] Universal Quantum Circuits p12
www.cse.sc.edu/~fenner/papers/univcirc.pdf
Bera Universal quantum circuits p12
Bera Universal Quantum Circuits1 p12
Bera Universal Quantum Circuits p13

adjacency graph

Hamma A quantum Bose-Hubbard model with evolving graph as toy model for emergent spacetime p23

Adjacency graph

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

Region adjacency graph

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

amputated graphs

Schwartz Introduction to Quantum Field Theory p262

bicirculant graph

Godsil State Transfer on Graphs p37

Binary Decision Graph BDD graphs

H. Hasegawa and S. Kasai, “Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires,” Physica E, vol. 11, no. 2-3, pp. 149–154, 2001.

binatorial or discrete graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

bipartite graphs?? !!!!!!!!!!!!!!!

McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization

Budhathoki Automatic synthesis of quantum circuits for point addition on ordinary binary elliptic curves p14

Bipartite graph
Bunyk D-Wave Processor Control Circuitry p48.pdf

bipartite graph
Chung QCA Physical Design With Crossing Minimization p4.pdf

bipartite graphs
Cosentino Weight of quadratic forms and graph states p7

bipartite graph
Duan On zero-error communication via quantum channels in the presence of noiseless feedback p7

bipartite graph
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

bi-partite graphs
HEIN Entanglement in Graph States and its Applications p99

bipartite graph

Iblisdir Low depth quantum circuits for Ising models p47

bipartite graph
Jeffery Frameworks for Quantum Algorithms p166.pdf

bipartite graph
Klavzar Tensor 2-sums and entanglement p5

bipartite graph
Severini Two-colorable graph states with maximal Schmidt measure p6
bipartite graph
[de) Wolf2014] de Wolf, Ronald: Quantum Computing: Lecture Notes, April 2014.

Lidar Quantum annealing with hundreds of qubits

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Boixo Quantum annealing with more than one hundred qubits
bipartite graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits
bipartite graph

Balanced bipartite graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

complete bipartite graph

Johnson D-Wave: real quantum computer
complete bipartite graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

complete bipartite graph

Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf
[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.

complete bipartite graph

Severini Nondiscriminatory Propagation on Trees p5

complete bipartite graphs
Cosentino On some combinatorial properties of graph states p78

full bipartite graph

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

quantum bipartite graph

Duan On zero-error communication via quantum channels in the presence of noiseless feedback p7

call graph

Abhari ScaffCC: A Framework for Compilation and Analysis of Quantum Computing Programs p10

Cayley digraphs

Severini Graphs of unitary matrices p19

Cayley graph?? !!!!!!!!!!!!!!!

Cayley graph

Ambainis Quantum walks and their algorithmic applications p11
“Glued trees” graph
Cayley graphs of groups

Batty An application of the Deutsch-Josza algorithm to formal languages and the word problem in groups p14.pdf
Ben-Aroya Quantum expanders and the quantum entropy difference problem p30
Bernasconi Quantum Networks on Cubelike Graphs p11
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19
Cameron On the quantum chromatic number of a graph p7
Cosentino On some combinatorial properties of graph states p78
Godsil Colouring an Orthogonality Graph p13
Godsil State Transfer on Graphs p37
Harrow Efficient Quantum Tensor Product Expanders and k-designs p16
JAKOBSON EIGENVALUE SPACINGS FOR REGULAR GRAPHS p21
Osborne Quantum Algorithms and Covering Spaces p7
Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11.pdf
Vergnioux Paths in quantum Cayley trees and L2-cohomology p26

Ambainis Quantum walks and their algorithmic applications p11.pdf
Cayley graphs of groups

classical Cayley graphs

Vergnioux Paths in quantum Cayley trees and L2-cohomology p26

normal Cayley graph

Godsil Colouring an Orthogonality Graph p13

Quantum Cayley graph

Vergnioux Paths in quantum Cayley trees and L2-cohomology p26

[Vergnioux2012]? Vergnioux, Roland: Paths in quantum Cayley trees and L2-cohomology, Advances in Mathematics 229 (2012) p 2686–2711.
R. Vergnioux, Orientation of quantum Cayley trees and applications, J. Reine Angew. Math. 580 (2005) 101–138.

Definitions

Cayley graphs

Classical Cayley graphs

Usual Cayley graphs

Quantum Cayley graph

Rooted trees

Classical Cayley tree

Quantum Cayley trees

Cubelike graphs

Cubelike graphs are the Cayley graphs

Cubelike graphs are the Cayley graphs

Cubelike Graphs
Bernasconi Quantum Networks on Cubelike Graphs p11

Bernasconi Quantum Networks on Cubelike Graphs p11.pdf
Godsil State Transfer on Graphs p37

cubelike graph

Cosentino On some combinatorial properties of graph states p78

chain graph

Herrman Continuous Time Quantum Walks p1
Murphy An introduction to graphical models p19

Chain graph

channel hypergraph

Cubitt Improving zero-error classical communication with entanglement p6

channel hypergraph
Cubitt Improving zero-error classical communication with entanglement p6

characteristic graph

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lov′asz # Number and its Variants p15

characteristic graph
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Chimera Graph for Quantum Chips

Mapping = embedding = encoding = coupling
Chimera graph = hardware graph / hardware graph topology = processor graph = chip graph

(Unit) Cell Graph

[Lidar2014] Lidar, Daniel: Quantum annealing with hundreds of qubits, Nature Phys. 10, 218 (2014), Nature Comm. 5, 3243 (2014), Science 345, 420 (2014)

unit cell graph
Unit cell graph: a bipartite graph K4,4 of 8 qubits, representing a cell arranged in 4 qubits horizontally and 4 qubits vertically. The D-Wave Two chip is designed with 8x8 unit cells comprising 512 qubits.

Lidar2014 Fig1 Unit Cell

Lidar2014 Fig 2? Unit Cell Graph

Unit cell graph
[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

unit cell coupling graph

unit cell coupling graph

[Lidar2014] Lidar, Daniel: Quantum annealing with hundreds of qubits, Nature Phys. 10, 218 (2014), Nature Comm. 5, 3243 (2014), Science 345, 420 (2014)
Lidar Quantum annealing with hundreds of qubits

Lidar Quantum annealing with hundreds of qubits
“Chimera graph” couplings
“Chimera” coupling graph of entire chip
unit cell coupling graph

The D-Wave Two Processor Graph: a “Chimera” coupling graph of entire chip with
503/512 functional qubits with “Chimera graph” couplings see below:

Lidar2014 Fig 2? The D-Wave Two Processor Graph ?and the Constituent Unit Cell Graph

The D-Wave processor is a special-purpose computer that implements quantum annealing, designed to solve optimization problems captured by the classical Ising model.

p 32

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013
unit cell coupling graph
coupling graph
“Chimera” coupling graph of entire chip

Chimera graph

http://journals.aps.org/prx/abstract/10.1103/PhysRevX.4.021008

?????????????????
http://www.archduke.org/stuff/d-wave-comment-on-comparison-with-classical-computers/harder-qubo-instances-on-a-chimera-graph/
?????????????????
http://www.archduke.org/stuff/d-wave-comment-on-comparison-with-classical-computers/#AppendixB

https://www.cs.auckland.ac.nz/en/about/newsandevents/events/events-2014/2014/09/

theory-group-seminar--programming-d-wave-with-qubos-and-a-broadc.html

http://graphisya.forumactif.org/t171-partenaria-avec-chimera-graph

http://journal.frontiersin.org/Journal/10.3389/fphy.2014.00005/full

??????????????
http://books.google.com.sg/books?id=RsRSBAAAQBAJ&pg=PA37&lpg=PA37&dq=chimera+graph&

source=bl&ots=Y4_VSHJJyx&sig=PmLw0mLuNFm9hBotMg-glSe0I2k&hl=en&sa=

X&ei=wc51VPGwJI2IuASYoYKYBA&redir_esc=y#v=onepage& q=chimera%20graph&f=false

??????????????
https://www.ibm.com/developerworks/community/blogs/jfp/entry/will_quantum_computing_kill_cplex?lang=en
?????????????????
https://www.ibm.com/developerworks/community/blogs/jfp/entry/

d_wave_vs_cplex_comparison_part_3_wmax2sat?lang=en
???????????????????
https://www.ibm.com/developerworks/community/blogs/jfp/entry/

d_wave_vs_cplex_comparison_part_2_qubo?lang=en
???????????????????
https://www.ibm.com/developerworks/community/blogs/jfp/entry/

d_wave_vs_cplex_comparison_part_1_qap?lang=en

http://iopscience.iop.org/1367-2630/16/4/045006/article

????????????????
http://nextbigfuture.com/2008/10/operating-128-qubit-dwave-quantum.html

http://www.olympiqueforum.com/tag/graph%60

https://scirate.com/arxiv/1306.6943

?????????????????
http://www.scottaaronson.com/blog/?p=1400
Also pointed out is that in general the QUBO problem must be mapped onto a chimera graph – an instance of the subgraph isomorphism problem.
Evidence for a genuine speedup on what we’ve dubbed here the “D-Wave problem” (that is, finding a ground state of an Ising model with $\pm J$ random couplings on a chimera graph) will require significantly more than solid proof of better scaling for the D-Wave device than classical annealing.
However, classical annealing is not the fastest currently-known heuristic for solving random combinatorial minimization problems like the “D-Wave Problem” of a random Ising model on a chimera graph.
Without commenting on D-Wave’s “quantumness”, I doubt it is currently useful as a computational device. A proof that it is dominated would be to find a simple program that outperforms D-Wave Two on its native QUBO problem, which might be doable because the Chimera graph may be a bit too “thin” to be useful, at least at this size.
To show (2) is indeed a pertinent scenario, Smolin and Smith ran some simulations on the “D-Wave Problem” of random $\pm J$ couplings on a chimera graph with up to 108 O(2) classical vectors — i.e., the completely incoherent regime — and found that indeed at this size scale around 50% of the time such adiabatic “dragging” of the energy well happens and thus no energy barrier ever need be crossed to get from the initial state to the final state in these instances.
The program is here: https://github.com/alex1770/QUBO-Chimera , and there is a writeup here:

http://www.archduke.org/stuff/d-wave-comment-on-comparison-with-classical-computers/
In fact, there was indeed an example of this happening in Cathy’s talk. The algorithm akmaxsat was designed to run on “randomly generated instances with a high clauses-to-variables ratio.” When Cathy ran it on random weighted MAX-2SAT instances, it worked extremely well. When she ran it on the Chimera-graph structured QUBO instances, it performed very poorly.
New relevant result by Sanjeeb Dash at IBM: http://arxiv.org/abs/1306.1202 ?– A note on QUBO instances defined on Chimera graphs
We observe that after a standard reformulation of QUBO problems defined on 512 node Chimera graphs as mixed-integer linear programs (MILP), they can be solved to optimality with the CPLEX MILP solver in time comparable to the time reported by McGeogh and Wang for the D-wave quantum computer.

http://www.theregister.co.uk/Print/2014/02/04/boffins_say_dwave_machine_could_be_a_classic/

http://www.tylerdwyer.com/WordPress/2013/11/success-at-sc13-2/

??? Heuristic search of Chimera graph embedding

Taking a real world problem and converting it into a type of problem called “QUBO” can be difficult, but can be done in polynomial time. The hard part is that the QUBO algorithm assumes a fully connected graph. This isn’t the case in the D-Wave machine, their machine demands a graph structure called a chimera graph (Fig 1.). And herein lays our biggest problem. Converting a general QUBO algorithm into a D-Wave acceptable chimera graph is hard, very hard to do (NP-Hard I believe). But! D-Wave isn’t worried about this, as they are simply using heuristics to make the encoding, and they seem to think that is good enough. Maybe it is …

NASA also talked on this point and is also using heuristics to embed graph colouring problems into the chimera graph. Their presentation showed that some embedding’s work, some don’t, but the D-Wave machine is fast enough to evaluate several embedding’s quickly to find a solution.

http://dblp.kbs.uni-hannover.de/dblp/Search.action;jsessionid=DEE7C07E58253A0F3772CD5B88813AB3?

search=&q=by%3A%22Rishi+Saket%22&appliedFilters=topic_facet|chimera+graph+structure

???????????????
https://dwave.wordpress.com/category/superconducting-electronics/page/2/
????????????????
http://dwave.wordpress.com/2008/10/23/the-128-qubit-rainier-processor-ii-graph-embedding/
???????????????????
http://sangyoung123.wordpress.com/2014/04/04/how-does-d-wave-system-design-their-processor-core/

chimera graph
Boixo Quantum annealing with more than one hundred qubits

Chimera graph
[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.
quantum annealing processor
superconducting quantum annealing processor
flux qubits,
SQUID flux qubits,
rf-SQUID flux qubits,
coupled rf-SQUID flux qubits,
tunably coupled rf-SQUID flux qubits,
array of tunably coupled rf-SQUID flux qubits,
superconducting flux qubits
superconducting integrated circuit process
inter-qubit couplers
programmable inter-qubit couplers
quantum algorithm
embedded superconducting digital-to-analog flux converters (DACs)
flux DACs, or Φ-DACs
current biased SFQ demultiplexer circuitry
XYZ addressing scheme
flux qubit / qubits based on quantum dots / qubits based on individual trapped ions

P 4/9

[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014

D-Wave Two Processor Graph
Chimera graph ?couplings
unit cell coupling graph

adiabatic quantum computing
D-Wave chip
quantum annealers
quantum annealing

Chimera architecture
D-Wave Two Processor Graph
Chimera graph
Chimera graph couplings
Chimera coupling graph
unit cell coupling graph

Lidar Quantum annealing with hundreds of qubits
[Lidar2014] Lidar, Daniel: Quantum annealing with hundreds of qubits, Nature Phys. 10, 218 (2014), Nature Comm. 5, 3243 (2014), Science 345, 420 (2014)
“Chimera graph” couplings
“Chimera” coupling graph of entire chip

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013

Lucas Adiabatic Quantum Computing p47.pdf

Graph Embedding
Chimera graph
complete graph

McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization
adiabatic quantum computation
hardware graph
Chimera graph
bipartite graphs
complete graph
connectivity graph

Chimera graph
[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

Hen Quantum Computational Science p69.pdf
[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014
“Chimera graph” couplings
“Chimera” coupling graph of entire chip

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html

Kristen L Pudenz,?????? ?? Tameem Albash??? & Daniel A Lidar
Nature Communications?? 5,Article number:?? 3243??? doi:10.1038/ncomms4243

Received
08 November 2013
Accepted
10 January 2014
Published
06 February 2014

Figure 1: Unit cell and encoded graph.
http://www.nature.com/ncomms/2014/140206/ncomms4243/fig_tab/ncomms4243_F1.html

(a) Schematic of one of the 64 unit cells of the DW2 processor; unit cells are arranged in an 8 × 8 array forming a ‘Chimera’ graph between qubits (see Methods). Each circle represents a physical qubit and each line a programmable Ising coupling . Lines on the right (left) couple to the corresponding qubits in the neighbouring unit cell to the right (above). (b) Two ‘logical qubits’ (i, red and j, blue) embedded within a single unit cell. Qubits labelled 1–3 are the ‘problem qubits’, the opposing qubit of the same colour labelled P is the ‘penalty qubit’. Problem qubits couple via the black lines with tunable strength α both inter- and intraunit cell. Light blue lines of magnitude β are ferromagnetic couplings between the problem qubits and their penalty qubit. (c) Encoded processor graph obtained from the Chimera graph by replacing each logical qubit by a circle. This is a non-planar graph (see Methods for a proof) with couplings of strength 3α. Green circles represent complete logical qubits. Orange circles represent logical qubits lacking their penalty qubit (see Methods). Red lines are groups of couplers that cannot all be simultaneously activated.

Hadayat Seddiqi,

How does D-Wave system design their processor core?
Is there any HDL type language which can be used to develop quantum circuits? I'm a front end ASIC engineer without much knowledge about quantum computing or physics. Looking at D-wave's website, it seems like they are doing really exciting work!

Hadayat Seddiqi,
http://www.quora.com/How-does-D-Wave-system-design-their-processor-core

http://www.quora.com/Hadayat-Seddiqi
quantum computing @ ORNL

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How does D-Wave system design their processor core?
Is there any HDL type language which can be used to develop quantum circuits? I'm a front end ASIC engineer without much knowledge about quantum computing or physics. Looking at D-wave's website, it seems like they are doing really exciting work!
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Hadayat SeddiqiHadayat Seddiqi, quantum computing @ ORNL
12 upvotes by Marc Bodnick, Sang Young Noh, Uday Singh Saini, (more)
Good question.

There are two parts to this. The first is the actual hardware stuff they use for building qubits, controlling them, controlling and maintaining the entanglement, noise control (thermal and magnetic) and cooling. These are things I don't know much about, but here are some quick references:

[1004.1628] Experimental Investigation of an Eight Qubit Unit Cell in a Superconducting Optimization Processor
http://arxiv.org/abs/1004.1628
[0907.3757] A scalable control system for a superconducting adiabatic quantum optimization processor
http://arxiv.org/abs/0907.3757
[0909.4321] Experimental Demonstration of a Robust and Scalable Flux Qubit
http://arxiv.org/abs/0909.4321

And if Matthew Saul Leifer? http://www.quora.com/Matthew-Saul-Leifer or Adam Sears? http://www.quora.com/Adam-Sears want to answer that would be great (they both seem to understand the physics of quantum devices better).

The other side comes from the abstract. Ignoring the exact implementation details, what we want is a quantum annealing chip that can add some quantum noise H_x to a particular Hamiltonian H_z. H_z encodes the problem you wish to solve in the z-spin basis of the entire Hamiltonian--in other words, there are a bunch of particles living in some graph and the particles have up or down spin (well, quantum mechanically they are in a certain superposition of the two). We want a total Hamiltonian to look like

H_{total} = H_z + \Gamma(t) H_x

where notice that \Gamma is time-dependent. Typically \Gamma scales H_x to have a much larger contribution than H_z at first, dying off to zero over time (linearly, quadratically, whatever you want, this choice is called the annealing schedule).

If you have an understanding of simulated annealing, there's an analogous picture for quantum annealing. Instead of gradually lowering the temperature (i.e. thermal noise), you try to replace thermal noise with quantum noise. Said in a different way, we allow a particle searching an energy landscape to be able to tunnel through barriers if the tunneling energy is high. Just like simulated annealing, you start out with a high tunneling energy and gradually decrease that to zero until all that is left is the part of the total energy equation (read: Hamiltonian) that specifies the energy landscape being optimized over. Interestingly, there are ideas that say thermal + quantum noise could be a killer combination if they're scaled right.

The particles/nodes are basically the qubits, and in the D-Wave processors they're SQUIDs, and the [weighted] edges between them represent coupling or entanglement (the coupling strength is determined by other SQUIDs called bias qubits). The qubit configurations is called the hardware graph, which in a chip like this would be isomorphic to an Ising spin-glass. Note that in an arbitrary spin-glass you can set the couplings to be anything you want, but in practice you must specify a particular hardware graph. This is the other aspect of the design of the chip. In equations,

H_z = \sum_{ij} Q_{ij} z_i z_j
and all you care about here is Q, which is an adjacency matrix for the graph of the problem you want to optimize for (the off-diagonals specify the couplings, and the diagonals are the local field bias on each node, i.e. some bias for which way the spin should be, positive, negative, and how much). The z parts of H_z are just the spins of the qubits, and there is a specific configuration of ups and downs (think zeros or ones, if you like) that minimize the energy of this graph, which is defined by Q like we just noted. The one problem that remains is that Q may not be very compatible with the actual adjacency matrix representing the physical qubits and their couplings with each other.

So we must think what kind of graph we want. You cannot just build a complete graph, that will fail on a physical scale at some point and would be far too expensive. Instead, you come up with something that's relatively sparse that will also allow you to translate graphs representing problems to graphs that also represent the problem but can be morphed and molded into the hardware graphs representation. In other words, it's the problem of minor embedding, which itself is NP-Complete. That's not necessarily spelling out doom, we just need to be careful what the hardware graph construction will look like.

More explicitly, what we want out of the hardware graph is some level of sparsity, which leads to flexibility and scalability. It needs to be sparse so that it is inexpensive to fabricate, it needs to have good structure so that it is flexible in allowing many different problems, and it needs to scale well. Graph flexibility isn't a well-defined term, what I mean is that during the process of embedding, sometimes you must expand one node in the problem graph into two, three, or more terms in the hardware graph so that k physical qubits represent one logical qubit. This should be minimized as much as possible. Scaling of course means that as we create larger machines, we should be able to expand the graph structure to incorporate more nodes in a sensible way without having to come up with completely new tools (e.g. compilers, which is what a program embedding a problem graph into the hardware graph would be for this computer) each time a new chip is designed.

Presumably D-Wave Systems got together a lot of smart graph theorists and IC designers and thought really hard about these problems. What they came up with was the Chimera graph:

(the description on Alex Selby's page says: Collapsed view of the Chimera graph of order 8 where each blob represents four vertices, each diagonal line represents a K_{4,4} with all four vertices connected to each other by 16 edges, and each horizontal and vertical line segment represents four parallel edges connecting each vertex to its corresponding vertex). The above graph may not seem so clear since it doesn't show some detail, but essentially each diagonal line represents a graph that looks like this:

where each black line or dot represents a physical qubit and the blue line or dot represents a coupling between two qubits. The first graph shows how these so-called 8 qubit unit-cells can be put together to create a 128-qubit chip (and in theory you could just keep plugging together unit cells and create a chip with any number of qubits (mod 8)). To embed K_m (fully-connected graph with m nodes) into the Chimera graph requires m(m-1)/2 qubits). Not a lot of work has been done on this particular graph that I've seen, though the biggest chip right now (March 2014) is 512-qubits and there is still a huge debate http://arxiv.org/abs/1401.7087 ?over how well ?http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html this chip actually performs http://arxiv.org/abs/1401.2910 . I'll leave two references specifically about Chimera graphs here as well:

??? Minor Embedding With Hard Faults http://arxiv.org/abs/1210.8395 ??(an approximation scheme for embedding problem graphs into a D-Wave Chimera graph)
A PTAS for the Classical Ising Spin Glass Problem on the Chimera Graph Structure http://arxiv.org/abs/1306.6943? (an approximation scheme for finding the lowest-energy spin-glass configuration on a Chimera graph, which interestingly is what the quantum annealing chip is supposed to be doing too.. hmmm..)

Chimera coupling graph

Hen Quantum Computational Science p69.pdf
[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014
“Chimera graph” couplings
“Chimera” coupling graph of entire chip

Lidar Quantum annealing with hundreds of qubits
“Chimera graph” couplings
“Chimera” coupling graph of entire chip
unit cell coupling graph

Lidar Quantum annealing with hundreds of qubits
“Chimera graph” couplings
“Chimera” coupling graph of entire chip
unit cell coupling graph

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013
unit cell coupling graph
coupling graph
“Chimera” coupling graph of entire chip

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013
unit cell coupling graph
coupling graph
“Chimera” coupling graph of entire chip

Coupling graph

coupling graph

p10
[Bullock2004] Bullock, Stephen S.: Quantum Circuits for d-level Systems, Quantum Information Theory and Practice seminar, November 4, 2004 p36.pdf
Qudits (Quantum Multi-level Logics)
not bit but dit, values 0,1,. . . , d
bit – binary digit
dit – d-ary digit
qudit = quantum dit
Coupling graph
spanning tree

[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014
“Chimera graph” couplings
“Chimera” coupling graph of entire chip

[Iblisdir2014] Iblisdir, S. et al: Low depth quantum circuits for Ising models, Annals of Physics 340 (2014) 205–251.? p47
coupling graph
bipartite graph
7 / 47

Lidar Quantum annealing with hundreds of qubits
“Chimera graph” couplings
“Chimera” coupling graph of entire chip
unit cell coupling graph

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013
unit cell coupling graph
coupling graph
“Chimera” coupling graph of entire chip

encoded graph

encoded graph
Lidar Quantum annealing with hundreds of qubits

Pudenz,Error-corrected quantum annealing with hundreds of qubits
Kristen L Pudenz,??????
Tameem Albash?
& Daniel A Lidar?
Nature Communications??? 5,Article number:??? 3243??? doi:10.1038/ncomms4243
http://www.nature.com/ncomms/2014/140206/ncomms4243/fig_tab/ncomms4243_F1.html

Figure 1: Unit cell and encoded graph.

(a) Schematic of one of the 64 unit cells of the DW2 processor; unit cells are arranged in an 8 × 8 array forming a ‘Chimera’ graph between qubits (see Methods). Each circle represents a physical qubit and each line a programmable Ising coupling . Lines on the right (left) couple to the corresponding qubits in the neighbouring unit cell to the right (above). (b) Two ‘logical qubits’ (i, red and j, blue) embedded within a single unit cell. Qubits labelled 1–3 are the ‘problem qubits’, the opposing qubit of the same colour labelled P is the ‘penalty qubit’. Problem qubits couple via the black lines with tunable strength α both inter- and intraunit cell. Light blue lines of magnitude β are ferromagnetic couplings between the problem qubits and their penalty qubit. (c) Encoded processor graph obtained from the Chimera graph by replacing each logical qubit by a circle. This is a non-planar graph (see Methods for a proof) with couplings of strength 3α. Green circles represent complete logical qubits. Orange circles represent logical qubits lacking their penalty qubit (see Methods). Red lines are groups of couplers that cannot all be simultaneously activated.

?[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

processor graph? ???

processor graph

Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf
[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.

D-Wave One Processor Graph

Lucas Adiabatic Quantum Computing p47.pdf

DW1 graph

encoded DW1 graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

D-Wave Two Processor Graph

D-Wave Two Processor Graph
D-Wave Two Processor Graph
Hen Quantum Computational Science p69.pdf
[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014

DW2 graph

encoded DW2 graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

D‐Wave Two Processor Graph
[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

Encoded processor graph

http://www.nature.com/ncomms/2014/140206/ncomms4243/fig_tab/ncomms4243_F1.html
http://www.nature.com/ncomms/2014/140206/ncomms4243/fig_tab/ncomms4243_F1.html

Encoded processor graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

circle graphs

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

circle graphs
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

circuit graph

Markov Simulating quantum computation by contracting tensor networks p21

Aharonov The quantum FFT can be classically simulated p12

circuit graph
Markov Simulating quantum computation by contracting tensor networks p21

(Integral) Circulant Graphs

Integral Circulant Graphs
circulant integral graphs

integral connected circulant graph

Saxena Parameters of Integral Circulant Graphs and Periodic Quantum Dynamics p12.pdf

graph G(n; S) is a Cayley graph
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

circulant graph????????
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

circulant graph
Cabello Graph-Theoretic Approach to Quantum Correlations p6

Clebsch graph

Clebsch graph
Cosentino On some combinatorial properties of graph states p78
Godsil State Transfer on Graphs p37

Cluster graphs

Wu Randomized Graph States and their Entanglement Properties p17

Cluster graphs
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

cluster graph

Voufo Quantum Circuits: From a Network to a One-Way Model - A Tutorial Version p28

Cluster graphs
Wu Randomized Graph States and their Entanglement Properties p17

coentropic graphs

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7
coentropic graphs
(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

Cographs

Severini Two-colorable graph states with maximal Schmidt measure p6.pdf

Cographs
Severini Two-colorable graph states with maximal Schmidt measure p6

B?y?koglu cographs

Severini Two-colorable graph states with maximal Schmidt measure p6

collapsed graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

combinatorial graphs

Cosentino Weight of quadratic forms and graph states p7

combinatorial or discrete graph
HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

(cut-)commutativity graphs

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf

Compatibility graph

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf

complement graph

Cameron On the quantum chromatic number of a graph p7

complementary graph

PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31

complementary graph
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Complementary graphs
Cosentino On some combinatorial properties of graph states p78

complete graph?? !!!!!!!!!!!!!!!

McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization

A?meur Quantum Clustering Algorithms p8????????????

complete subgraph

Boyden III Quantum Computation: Theory and Implementation p181

complete graphs
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

complete graphs
Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf
complete graph
[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.

complete graph
Bunyk D-Wave Processor Control Circuitry p48.pdf

complete graph
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

complete graph
Cosentino Weight of quadratic forms and graph states p7

Complete graph
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

complete graph
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

complete graph
Feder Graphs in Quantum Information Theory p19.pdf

complete graph
HEIN Entanglement in Graph States and its Applications p99

complete graph

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

complete graph
Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

complete graphs

Klavzar Tensor 2-sums and entanglement p5

complete graph.
Lovett Application of quantum walks on graph structures to quantum computing p239

complete graph
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

complete graphs
Severini Nondiscriminatory Propagation on Trees p5

complete graph

Severini Two-colorable graph states with maximal Schmidt measure p6

complete graph
Shafaei Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures p6
Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

complete graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

complete (or fully connected) graph
Wu Randomized Graph States and their Entanglement Properties p17

complete graph
Cosentino On some combinatorial properties of graph states p78

http://www.quora.com/How-does-D-Wave-system-design-their-processor-core
complete graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

complete graph

Boixo Quantum annealing with more than one hundred qubits
complete graph

N-complete graph

Lucas Adiabatic Quantum Computing p47.pdf

computational graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

computational graph

condensed graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

confusability graph?? !!!!!!!!!!!!!!!okokok

Confusability graph

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15
Cubitt Improving zero-error classical communication with entanglement p6
Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19
FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

connected graph??

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

[Bergholm2011] ?Categorical Quantum Circuits p23 Journal of Physics A: Mathematical and Theoretical, Sep 28th, 2011
https://www.cs.ox.ac.uk/files/3724/cqc_poster.pdf

connected graph

Biamonte Algebra and Coalgebra on Categorical Tensor Network States p39

connected graphs

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

connected graph
Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75

connected graph
Cosentino Weight of quadratic forms and graph states p7

connected graphs
Feder Graphs in Quantum Information Theory p19

connected graph
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

connected graph
HEIN Entanglement in Graph States and its Applications p99

connected graphs

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

connected graph
Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

connected graph

Kirkland State Transfer in Quantum Spin Networks and the Matrix Exponential p78

connected graph
Lovett Application of quantum walks on graph structures to quantum computing p239

connected graph
[Nielsen2010] Nielsen, Michael A. & Chuang, Isaac L.: ?Quantum Computation and Quantum Information, Cambridge University Press, 2010, p698
58

connected graph

Severini Two-colorable graph states with maximal Schmidt measure p6

connected graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

connected graphs
Cosentino On some combinatorial properties of graph states p78

connected graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

fully connected graphs

Feder Graphs in Quantum Information Theory p19

fully connected graph
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

http://www.quora.com/How-does-D-Wave-system-design-their-processor-core

fully-connected graph

regular connected graph

Godsil Colouring an Orthogonality Graph p13

connected subgraph

Chung QCA Physical Design With Crossing Minimization p4.pdf

connection graph

connection graph

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

connectivity graph

Dash A note on QUBO instances defined on Chimera graphs p8.pdf

Szabo Evolutionary games on graphs p133

Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization

connectivity graph

connectivity graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

Chimera connectivity graph

chimera connectivity graph

Boixo Quantum annealing with more than one hundred qubits

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

constraint graph

vertical constraint graph (VCG)

Chung QCA Physical Design With Crossing Minimization p4.pdf

VCG (Vertical Constraint Graph)
Smith QCA Channel Routing With Wire Crossing Minimization p4.pdf

Convergence graph

Mukherjee Synthesis of Quantum Circuits Using Genetic Algorithm p5

correction graphs

vertex correction graphs

Schwartz Introduction to Quantum Field Theory p262

Cospectral graphs

Audenaert Symmetric Squares of Graphs p19

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7
cospectral graphs
(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

digraph
directed graph
(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

cospectral graphs
Emms Coined quantum walks lift the cospectrality of graphs and trees p15
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Cycle graphs

Wu Randomized Graph States and their Entanglement Properties p17

Cayley graphs
Ambainis Quantum walks and their algorithmic applications p11

cycle graph
Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75

cycle graph
Cosentino Weight of quadratic forms and graph states p7

cycle graph
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

cycle graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

Cycle graphs
Wu Randomized Graph States and their Entanglement Properties p17

cycle graph
Cosentino On some combinatorial properties of graph states p78

cycle graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Underwood Quantum Walk Schemes for Universal Quantum Computation p267


Untitled Document

Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

D-I

dataflow graph

Shahbazi Layout Optimization in Quantum Circuit using Simulated Annealing p7.pdf

de Bruijn digraph

Severini Graphs of unitary matrices p19

de Bruijn graph?? !!!!!!!!!!!!!!!

de Bruijn graph

[Severini2006] Severini, Simone: Universal quantum computation with unlabeled qubits, J. Physics A: Math. Gen. 39 (2006) 8507-8515.

Let Σ be an alphabet of cardinality d and let [image]?be the set of all words of length n over Σ. The d-ary n-dimensional de Bruijn graph is a directed graph denoted by B(d, n) and defined as follows [5]: the set of vertices is [image]; there is an arc from i to j if and only if the last n ? 1 letters of i are the same as the first n ? 1 letters of j. The graph B(2, n) is called (directed) binary de Bruijn graph. Notice that B(2, n) has exactly two loops: one loop is at the vertex 0 . . . 0; the other one at the vertex 1 . . . 1.

M.-C. Heydemann, Cayley graphs and interconnection networks, Graph symmetry (Montreal, PQ, 1996), 167–224, NATO Adv. Sci. Inst. Ser. C Math. Phys. Sci., 497, Kluwer Acad. Publ., Dordrecht, 1997.

De Bruijn graph

?(directed) binary de Bruijn graph

[Severini2006] Severini, Simone: Universal quantum computation with unlabeled qubits, J. Physics A: Math. Gen. 39 (2006) 8507-8515.

decorated graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

decoration graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

decoration graphs

compact decoration graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

dependency graph? ???

quantum instruction dependency graph (QIDG)?? ???

quantum instruction dependency graph (QIDG)
quantum instruction dependency graph (QIDG)? ???
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF
2012 EDAA

ion-trap quantum circuit fabric
NP-intermediate problems

Deutsch-Jozsa graphs / Hadamard graphs / orthogonality graphs

Deutsch-Jozsa graphs

Deutsch-Jozsa graphs

P
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
October 21, 2013
graph coloring
graph coloring games
quantum c-coloring
Hadamard graphs
Hadamard graphs are also known in literature as orthogonality graphs and Deutsch-Jozsa graphs

Hadamard graphs? okokok

Hadamard graphs

Cameron On the quantum chromatic number of a graph p7
Hadamard graphs [5, 7], which are a special case of orthogonality graphs

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
October 21, 2013
graph coloring
graph coloring games
quantum c-coloring
Hadamard graphs
Hadamard graphs are also known in literature as orthogonality graphs and Deutsch-Jozsa graphs

Scarpa Kochen-Specker Sets and the Rank-1 Quantum Chromatic Number p12.pdf

Orthogonality graph

orthogonality graph
Orthogonality Graph

Cameron On the quantum chromatic number of a graph p7

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

Godsil Colouring an Orthogonality Graph p13

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
October 21, 2013
graph coloring
graph coloring games
quantum c-coloring
Hadamard graphs
Hadamard graphs are also known in literature as orthogonality graphs and Deutsch-Jozsa graphs

dependency graph? ???

quantum instruction dependency graph (QIDG)?? ???

quantum instruction dependency graph (QIDG)
quantum instruction dependency graph (QIDG)? ???
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF
2012 EDAA

ion-trap quantum circuit fabric
NP-intermediate problems

Deutsch-Jozsa graphs / Hadamard graphs / orthogonality graphs

Deutsch-Jozsa graphs

Deutsch-Jozsa graphs

P
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
October 21, 2013
graph coloring
graph coloring games
quantum c-coloring
Hadamard graphs
Hadamard graphs are also known in literature as orthogonality graphs and Deutsch-Jozsa graphs

Hadamard graphs? okokok

Hadamard graphs

Cameron On the quantum chromatic number of a graph p7
Hadamard graphs [5, 7], which are a special case of orthogonality graphs

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
October 21, 2013
graph coloring
graph coloring games
quantum c-coloring
Hadamard graphs
Hadamard graphs are also known in literature as orthogonality graphs and Deutsch-Jozsa graphs

Scarpa Kochen-Specker Sets and the Rank-1 Quantum Chromatic Number p12.pdf

Orthogonality graph

orthogonality graph
Orthogonality Graph

Cameron On the quantum chromatic number of a graph p7

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

Godsil Colouring an Orthogonality Graph p13

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15
October 21, 2013
graph coloring
graph coloring games
quantum c-coloring
Hadamard graphs
Hadamard graphs are also known in literature as orthogonality graphs and Deutsch-Jozsa graphs

diag-graphs

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

directed graph / Digraph ???!!!!!!!!!!!!!!!

H. Hasegawa and S. Kasai, “Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires,” Physica E, vol. 11, no. 2-3, pp. 149–154, 2001.
directed graph

Boyden III Quantum Computation: Theory and Implementation p181

directed graph
Chung QCA Physical Design With Crossing Minimization p4.pdf

directed graph
Dribus Quantum Circuit Graphs p29

directed graph
Eachempati Reconfigurable BDD based Quantum Circuits p7

Digraph
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Digraph
Feder Graphs in Quantum Information Theory p19

directed graphs
Gutin Hamilton Cycles in Digraphs of Unitary Matrices p10

Digraph
Hall Locality for quantum systems on graphs depends on the number field p9

directed graph
HEIN Entanglement in Graph States and its Applications p99

Digraphs

Kauffman Quantum Topology and Quantum Computing p37

directed graphs

[Nielsen2010] Nielsen, Michael A. & Chuang, Isaac L.: ?Quantum Computation and Quantum Information, Cambridge University Press, 2010, p698
58

directed graph

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

digraphs
directed graph
Severini Nondiscriminatory Propagation on Trees p5

DIGRAPHS
directed graph

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

directed graph

[Severini2006] Severini, Simone: Universal quantum computation with unlabeled qubits, J. Physics A: Math. Gen. 39 (2006) 8507-8515.

directed graph

Smith QCA Channel Routing With Wire Crossing Minimization p4.pdf

directed graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

directed graph
Cosentino On some combinatorial properties of graph states p78

okokok
Zhao WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure
Zhao, Hong-Quan; Kasai, Seiya
Journal of Nanomaterials, 2012:
directed graph with hexagonal topology

directed graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Digraph
Tsai Quantum Boolean circuits and layout under locality constraint
Sunday, October 28, 2001—S3.1 Nanocircuits and Architectures, IEEE-NANO 2001

acyclic directed graph

Dribus Quantum Circuit Graphs p29

Cayley digraph

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

Connection Digraph

[Kuo2002] Kuo, Sy-Yen郭斯彥:The Circuit Perspective of Digital Quantum Switching PPT slide, Workshop on Quantum Information Science, Oct 18-19, 2002, Tainan, Taiwan

Connection Digraph for Digital Switching in the Quantum Domain

Connection Digraph [Kuo2002]
Connection Digraph -- Loopbacks and Null points
Connection Digraph – Queue
Connection Digraph – Cycle
Connection Digraph – Tree
Connection Digraph – Forest

Convert each connection digraph into cycles or loopbacks

Digraphs of Unitary Matrices

Gutin Hamilton Cycles in Digraphs of Unitary Matrices p10

line digraph

Hall Locality for quantum systems on graphs depends on the number field p9

line digraph
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

line digraph

line digraph

Hall Locality for quantum systems on graphs depends on the number field p9.pdf

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11.pdf

Emms A matrix representation of graphs and its spectrum as a graph invariant p14

Emms A matrix representation of graphs and its spectrum as a graph invariant p14

line digraph

Severini Graphs of unitary matrices p19

line graph
Cosentino On some combinatorial properties of graph states p78

line digraphs of eulerian digraphs

Gutin Hamilton Cycles in Digraphs of Unitary Matrices p10

Mediated Digraphs

Gutin Mediated Digraphs and Quantum Nonlocality p11

orthogonal digraphs

Hall Locality for quantum systems on graphs depends on the number field p9

regular digraphs

Gutin Mediated Digraphs and Quantum Nonlocality p11

regular digraph
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

strongly connected digraph

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

symmetric digraphs

Gutin Mediated Digraphs and Quantum Nonlocality p11

directed graph of implications

Nagaj Local Hamiltonian in quantum computation p176

discrete graphs

Smilansky Quantum chaos on discrete graphs p16

directed graphs
Bera On Finding Sensitivity of Quantum and Classical Gates p15

discrete graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

discrete graphs
Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6

distinguishability graph

distinguishability graph
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lov′asz # Number and its Variants p15

dynamical graphs

Caravelli Properties of Quantum Graphity at Low Temperature p21
Hamma Background independent condensed matter models for quantum gravity p17
Konopka Quantum Graphity: a model of emergent locality p25
Nicosia Co-evolution of networks and quantum dynamics: a generalization of preferential attachment p8

embedded graph

Lucas Adiabatic Quantum Computing p47.pdf

embedded graph

Lucas Adiabatic Quantum Computing p47.pdf

emission graphs

real emission graphs

Schwartz Introduction to Quantum Field Theory p262

Enumerating graphs

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

(bipartite) equivocation graph

Duan On zero-error communication via quantum channels in the presence of noiseless feedback p7

equivocation (bipartite) graph
equivocation graph (a quantum bipartite graph)
bipartite equivocation graph
Duan On zero-error communication via quantum channels in the presence of noiseless feedback p7

Erdos-Renyi graphs

Hamma A quantum Bose-Hubbard model with evolving graph as toy model for emergent spacetime p23

Wu Randomized Graph States and their Entanglement Properties p17

eulerian graph

Severini Graphs of unitary matrices p19

Eulerian subgraphs

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

Exclusivity graphs

Cabello Graph-Theoretic Approach to Quantum Correlations p6
Exclusivity graphs
Cabello Graph-Theoretic Approach to Quantum Correlations p6

simplest exclusivity graph

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf

expander graphs?? !!!!!!!!!!!!!!!

expander graphs

Ben-Aroya Quantum expanders and the quantum entropy difference problem p30
Markov Simulating quantum computation by contracting tensor networks p21
Underwood Quantum Walk Schemes for Universal Quantum Computation p167
expander graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Classical expander graphs

Classical expander graphs
Harrow Efficient Quantum Tensor Product Expanders and k-designs p16

D-regular expander graphs

Harrow Efficient Quantum Tensor Product Expanders and k-designs p16

F-graph

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

fabric graph

fabric graph
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF

undirected fermionic graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

glued-trees graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

fermionic graphs

undirected fermionic graphs

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Feynman graphs

Schwartz Introduction to Quantum Field Theory p262
P36, 255
Feynman graphs
tree level graph
loop graph
self-energy loop graph
self energy graph
electron self-energy graph
photon self-energy graph
vacuum polarization graph
one-particle irreducible graphs
counterterm graph
1PI graphs
1PI 4-point graph
vertex correction graphs
amputated graphs
real emission graphs
proper graphs

Connected Feynman Graphs

Tong Quantum Field Theory p155.pdf
P84
Feynman Graphs

finite graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

game graph

Chailloux Graph-theoretical Bounds on the Entangled Value of Non-local Games p10

Gate Rule Graph

Gate Rule Graph
Wong An Algorithm For Quantum Circuit Optimization p58.pdf

GHZ graphs

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
P186
GHZ graphs

grid graph

Markov Simulating quantum computation by contracting tensor networks p21

grid graph
Markov Simulating quantum computation by contracting tensor networks p21

Grid graph or a lattice graph
Wu Randomized Graph States and their Entanglement Properties p17

planar rectangular grid graph

Shahbazi Layout Optimization in Quantum Circuit using Simulated Annealing p7

Hamming graph

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Schrijver’s graph

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

hardware graph

Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf

[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.

hardware graph

Dash A note on QUBO instances defined on Chimera graphs p8.pdf

hardware graph
Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf

McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization
hardware graph

http://www.quora.com/How-does-D-Wave-system-design-their-processor-core

hardware graph

hardware graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

encoded hardware graph

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

homogeneous graph

GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

hypercubic graphs

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

hypergraph?? !!!!!!!!!!!!!!!

Cubitt Improving zero-error classical communication with entanglement p6

hypergraphs

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

hypergraph.
[Volovich1997] Volovich, I.V.:? Models of Quantum Computers and Decoherence Problem, Proc. of the International Conference on Quantum Information, Meijo University, Nagoya, 4-8 Nov.1997.

Hypergraph
Cosentino On some combinatorial properties of graph states p78

Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

k-uniform hypergraphs

[Rossi 2013] Rossi ,M.;? Huber, M;. Bru?, D. and Macchiavello, C.: Quantum Hypergraph States, New Journal of Physics, Volume 15, Issue 11, article id. 113022 (2013)., ?? 11/2013

k-uniform hypergraphs

[Rossi 2013] Rossi ,M.;? Huber, M;. Bru?, D. and Macchiavello, C.: Quantum Hypergraph States, New Journal of Physics, Volume 15, Issue 11, article id. 113022 (2013)., ?? 11/2013

n-uniform hypergraphs
Cosentino On some combinatorial properties of graph states p78

implication graph

Nagaj Local Hamiltonian in quantum computation p176

Incidence graphs

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Balanced incidence graphs

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Bipartite incidence graphs

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

in-split graphs

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11.pdf

in-split graphs
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

interaction graph

Lin Reversible and Quantum Circuit Synthesis p209.pdf
Shafaei Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures p6.pdf

Szabo Evolutionary games on graphs p133

interaction graph
Shafaei Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures p6

Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures

irreducible graphs

one-particle irreducible graphs

Schwartz Introduction to Quantum Field Theory p262

isomorphic graphs

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

isomorphic graphs
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

isomorphic graph
HEIN Entanglement in Graph States and its Applications p99

isomorphic graphs
Cosentino On some combinatorial properties of graph states p78

isomorphic sub-graphs

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf

interaction graph

Lin Reversible and Quantum Circuit Synthesis p209


Untitled Document

Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

J-R

Johnson graph

Johnson graph

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19
Jeffery Frameworks for Quantum Algorithms p166.pdf
Wolf Quantum Computing Lecture Notes p112.pdf
[de) Wolf2014] de Wolf, Ronald: Quantum Computing: Lecture Notes, April 2014.

K2 Graph

Herrman Continuous Time Quantum Walks p1

Kneser graphs

Kneser graphs

PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31
P29

Labeled Graphs

Aharonov The quantum FFT can be classically simulated p12

labeled graphs

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

Labeled graphs
Klavzar Tensor 2-sums and entanglement p5

labeled graphs
Cosentino On some combinatorial properties of graph states p78

lattice graphs

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

LCS-graphs / Local-Complementationand-Switching graphs

Cosentino On some combinatorial properties of graph states p78

learning graph

Jeffery Frameworks for Quantum Algorithms p166.pdf

line graph?? !!!!!!!!!!!!!!!

line graph

Godsil Colouring an Orthogonality Graph p13.pdf
Kirkland Spin systems dynamics and faults detection in threshold networks p6.pdf
Audenaert Symmetric Squares of Graphs p19

Markov Simulating quantum computation by contracting tensor networks p21

Caravelli Properties of Quantum Graphity at Low Temperature p21

Hamma Background independent condensed matter models for quantum gravity p17

line graph

Godsil Colouring an Orthogonality Graph p13

line graph

Markov Simulating quantum computation by contracting tensor networks p21

Line Graph
Oliveira Quantum Computation - Lecture 09 – Quantum Simulation p11

line graphs
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Line graphs

Nagaj Local Hamiltonian in quantum computation p176
line graph

line graphs of trees

Severini Two-colorable graph states with maximal Schmidt measure p6.pdf

line graphs of trees

Severini Two-colorable graph states with maximal Schmidt measure p6

linear graphs

linear graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

linear graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

parallel linear graphs

Feder Graphs in Quantum Information Theory p19

loop-free graph

Bishop Circuit Quantum Electrodynamics p168

loop graphs

Schwartz Introduction to Quantum Field Theory p262

m-graphs

Ruican Developing Automatic Synthesis Methodologies for Quantum Circuits using Genetic Algorithms p31.pdf

measurement graph

GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

mediated digraphs

mediated digraphs

Gutin Mediated Digraphs and Quantum Nonlocality p11.pdf

regular digraphs [10] and symmetric digraphs of diameter 2 are special families of mediated digraphs
in that paper mediated digraphs are called Totally Paired Graphs

Totally Paired Graphs

Gutin Mediated Digraphs and Quantum Nonlocality p11
Gutin Mediated Digraphs and Quantum Nonlocality p11
in that paper mediated digraphs are called Totally Paired Graphs

Multigraph

Feder Graphs in Quantum Information Theory p19

Multigraph
Cosentino On some combinatorial properties of graph states p78

finite directed multi-graphs

Kauffman Quantum Topology and Quantum Computing p37

multi-walker graphs

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

n-ladder graphs

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

neighborhood graph

INRIA Architectures, Languages and Compilers to Harness the End of Moore Years p40.pdf

neighbourhood graph

A?meur Quantum Clustering Algorithms p8????????????

non-commutative graphs?? !!!!!!!!!!!!!!! okokok

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

non-commutative graph

FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6.pdf

Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30

non-commutative graphs
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

non-commutative graph
FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6

confusability graph

FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6.pdf

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lov′asz # Number and its Variants p15
Cubitt Improving zero-error classical communication with entanglement p6

Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30

Non-Commutative Graphs

non-commutative (confusability) graph
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

non-commutative (confusability) graphs

FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6

E-graph

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

ρ-graph?? ???

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

ρ-graph
Such a noncommutative graph we call ρ-graph, and all we require for it is 11 ∈ S = S?.

nonsingular graphs

Severini Two-colorable graph states with maximal Schmidt measure p6.pdf

nonsingular graphs

Severini Two-colorable graph states with maximal Schmidt measure p6

obstruction graphs

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

oriented graph

Abramsky A categorical quantum logic p18

orthogonal digraphs

orthogonal digraphs

Hall Locality for quantum systems on graphs depends on the number field p9.pdf

outerplanar graph

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

P4-free graph

Severini Two-colorable graph states with maximal Schmidt measure p6

Paley graphs

Paley graphs
Osborne Quantum Algorithms and Covering Spaces p7

parallel graphs

series parallel graphs

Markov Simulating quantum computation by contracting tensor networks p21

series parallel graphs
Markov Simulating quantum computation by contracting tensor networks p21

path graph

Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75.pdf

Cosentino Weight of quadratic forms and graph states p7

path graph
Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75

path graph
Cosentino Weight of quadratic forms and graph states p7

path graph
Cosentino On some combinatorial properties of graph states p78

path graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

infinite path graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

pattern graph

MBQC graph / MBQC pattern graph

Pius Automatic Parallelisation of Quantum Circuits Using the Measurement Based Quantum Computing Model p72

Pauli (X,y.z)-graph? !!!!!!!!!!!! okokok

Pauli X-graph

Dribus Quantum Circuit Graphs p29

pentagon graph

Feder Graphs in Quantum Information Theory p19

perfect graphs

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20
Cabello Graph-Theoretic Approach to Quantum Correlations p6
Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30

perfect graphs
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

Perfect graphs
Cabello Graph-Theoretic Approach to Quantum Correlations p6

Petersen graph

Banerji A notion of graph likelihood and an infinite monkey theorem p6
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Godsil State Transfer on Graphs p37

Petersen graph

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Petersen Graph
HEIN Entanglement in Graph States and its Applications p99

Petersen graph??????????
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

Petersen graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Planar graphs?? !!!!!!!!!!!!!!!

Markov Simulating quantum computation by contracting tensor networks p21

planar graphs

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

planar graph

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

Planar graphs
Markov Simulating quantum computation by contracting tensor networks p21

planar graphs
Oliveira Quantum Computation - Lecture 09 – Quantum Simulation p11

planar graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

planar graphs

[Volovich1997] Volovich, I.V.:? Models of Quantum Computers and Decoherence Problem, Proc. of the International Conference on Quantum Information, Meijo University, Nagoya, 4-8 Nov.1997.

planar graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

point graph

nearest point graph

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

nearest point graph
Braunstein Some families of density matrices for which separability is easily tested p14

polarization graph? ???

vacuum polarization graph

Schwartz Introduction to Quantum Field Theory p262

process graph?? ???

Horsman Quantum picturalism for topological cluster-state computing p14.pdf

product graph

Klavzar Tensor 2-sums and entanglement p5

Propagation graph

Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75.pdf

Propagation graph
Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75

QCNOT graph? ???

QCNOT graph

Dribus Quantum Circuit Graphs p29

quantum graphs?? !!!!!!!!!!!!!!!

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
quantum graph (QG)
Quantum Tree Graphs
A quantum graph (QG) is a metric graph
rooted metric tree graph

T. Kottos and U. Smilansky. Periodic orbit theory and spectral statistics for quantum graphs. Ann. Phys.
274:76–124, 1999.
P. Kuchment. Quantum graphs: I. Some basic structures. Waves and random media, 14:S107–S128,
2004.
P. Kuchment. Quantum graphs II. Some spectral properties of quantum and combinatorial graphs,
preprint. To appear in J. Phys. A.

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
quantum graphs
quantum graphs, which are excellent paradigms of quantum chaos
Experimental investigation of the fidelity in microwave networks simulating quantum graphs
M.? Lawniczak, S. Bauch, O. Hul, and L. Sirko
The Elastic Enhancement Factor as an Experimental Measure of Quantum Chaos
Micha l? Lawniczak,1, ?Agata Nicolau-Kuklinska,1 Szymon Bauch,1 Oleh Hul,1 and Leszek Sirko1

Feder Graphs in Quantum Information Theory p19
quantum graphs

Hall Locality for quantum systems on graphs depends on the number field p9
quantum graphs

T. J. Osborne, Approximate Locality for Quantum Systems on Graphs, Phys. Rev. Lett. 101, 140503 (2008).arXiv:quant-ph/0611231v2
P. Pako′nski, K. ˙Zyczkowski, M. Ku′s, Classical 1D maps, quantum graphs and ensembles of unitary matrices, J.Phys. A 34, 9303-9317 (2001). arXiv:nlin/0011050v5 [nlin.CD]

Lovasz Very large graphs p63
quantum graph
A quantum graph is defined as a formal linear combination of a finite number of graphs with
real coefficients.

Quantum (metric) graphs?? !!!!!!!!!!!!!!! okokok

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
quantum graph (QG)
Quantum Tree Graphs
A quantum graph (QG) is a metric graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32
RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS
radial, tree-like, rooted quantum graphs
metric graphs
quantum graphs
infinite quantum graphs
radial quantum graph
random quantum graphs
unperturbed quantum graph
The metric graph together with a self-adjoint differential operator is usually called a quantum graph.
Michael Solomyak, On the spectrum of the Laplacian on regular metric trees, Waves Random Media 14 (2004), no. 1, S155–S171, Special section on quantum graphs.
M. J. Gruber, D. Lenz, and I. Veseli′c, Uniform existence of the integrated density of
states for combinatorial and metric graphs over Zd, Preprint arXiv:0712.1740 (2007).
M. J. Gruber, D. Lenz, and I. Veseli′c,, Uniform existence of the integrated density of states for random Schr¨odinger operators on metric graphs over Zd, J. Funct. Anal. 253 (2007), no. 2, 515–533.
M. Helm and I. Veseli′c, Linear Wegner estimate for alloy-type Schr¨odinger operators on metric graphs, J. Math. Phys. 48 (2007), no. 9, 092107, 7.
F. Klopp and K. Pankrashkin, Localization on quantum graphs with random vertex couplings,J. Statist. Phys. 131 (2008), 561–673.
V. Kostrykin and R. Schrader, [KS04] , A random necklace model, Waves Random Media 14 (2004), no. 1, S75–S90,Special section on quantum graphs.
P. Kuchment, Quantum graphs: I. Some basic structures, Waves Random Media 14
(2004), S107–S128.
P. Kuchment, [Ku05] , Quantum graphs. II. Some spectral properties of quantum and combinatorial
graphs, J. Phys. A 38 (2005), no. 22, 4887–4900.
P. Kuchment, [Ku08] , Quantum graphs: an introduction and a brief survey, Preprint
arXiv:0802.3442 (2008).
D. Lenz, C. Schubert, and P. Stollmann, Eigenfunction expansions for Schr¨odinger operators
on metric graphs, Preprint arXiv:0801.1376 (2008).
Beng-Seong Ong, On the limiting absorption principle and spectra of quantum graphs,
Preprint (2005).
G. Berkolaiko, R. Carlson, St. A. Fulling, and P. Kuchment (eds.), Quantum graphs
and their applications, Contemporary Mathematics, vol. 415, Providence, RI, American
Mathematical Society, 2006.
P. Exner, M. Helm, and P. Stollmann, Localization on a quantum graph with a random
potential on the edges, Rev. Math. Phys. 19 (2007), no. 9, 923–939.

Smilansky Quantum chaos on discrete graphs p16
quantum (metric) graphs
quantum chaos on quantum (metric) graphs [1], spectral? functions and trace formulae for discrete Laplacians on graphs
quantum (metric) graphs were proposed as a convenient paradigm for the study of quantum chaos in compact [1] and scattering [5] systems.
Tsampikos Kottos and Uzy Smilansky, Quantum Chaos on Graphs, Phys. Rev. Lett. 79,4794-
4797, (1997). and Periodic orbit theory and spectral statistics for quantum graphs, Annals of
Physics 274, 76-124 (1999).
Peter Kuchment, Quantum Graphs: I. Some basic structures. Waves in random Media 14 (2004),
S107-S128.
Sven Gnutzmann and Uzy Smilansky, Quantum Graphs: Applications to Quantum Chaos and
Universal Spectral Statistics. Advances in Physics bf 55 (2006) 527-625.

Vinci Hearing the Shape of the Ising Model with a Programmable Superconducting-Flux Annealer p13
metric graphs
non-isomorphic quantum co-Ising graphs

connected metric graph

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
quantum graph (QG)
Quantum Tree Graphs
A quantum graph (QG) is a metric graph
rooted metric tree graph
connected metric graph
metric graphs
finite metric graph
general metric tree graphs
metric tree graphs

T. Kottos and U. Smilansky. Periodic orbit theory and spectral statistics for quantum graphs. Ann. Phys.
274:76–124, 1999.
P. Kuchment. Quantum graphs: I. Some basic structures. Waves and random media, 14:S107–S128,
2004.
P. Kuchment. Quantum graphs II. Some spectral properties of quantum and combinatorial graphs,
preprint. To appear in J. Phys. A.

quantum graphs?? !!!!!!!!!!!!!!!

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
quantum graph (QG)
Quantum Tree Graphs
A quantum graph (QG) is a metric graph
rooted metric tree graph

T. Kottos and U. Smilansky. Periodic orbit theory and spectral statistics for quantum graphs. Ann. Phys.
274:76–124, 1999.
P. Kuchment. Quantum graphs: I. Some basic structures. Waves and random media, 14:S107–S128,
2004.
P. Kuchment. Quantum graphs II. Some spectral properties of quantum and combinatorial graphs,
preprint. To appear in J. Phys. A.

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
quantum graphs
quantum graphs, which are excellent paradigms of quantum chaos
Experimental investigation of the fidelity in microwave networks simulating quantum graphs
M.? Lawniczak, S. Bauch, O. Hul, and L. Sirko
The Elastic Enhancement Factor as an Experimental Measure of Quantum Chaos
Micha l? Lawniczak,1, ?Agata Nicolau-Kuklinska,1 Szymon Bauch,1 Oleh Hul,1 and Leszek Sirko1

Feder Graphs in Quantum Information Theory p19
quantum graphs

Hall Locality for quantum systems on graphs depends on the number field p9
quantum graphs

T. J. Osborne, Approximate Locality for Quantum Systems on Graphs, Phys. Rev. Lett. 101, 140503 (2008).arXiv:quant-ph/0611231v2
P. Pako′nski, K. ˙Zyczkowski, M. Ku′s, Classical 1D maps, quantum graphs and ensembles of unitary matrices, J.Phys. A 34, 9303-9317 (2001). arXiv:nlin/0011050v5 [nlin.CD]

Lovasz Very large graphs p63
quantum graph
A quantum graph is defined as a formal linear combination of a finite number of graphs with
real coefficients.

Quantum (metric) graphs?? !!!!!!!!!!!!!!! okokok

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
quantum graph (QG)
Quantum Tree Graphs
A quantum graph (QG) is a metric graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32
RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS
radial, tree-like, rooted quantum graphs
metric graphs
quantum graphs
infinite quantum graphs
radial quantum graph
random quantum graphs
unperturbed quantum graph
The metric graph together with a self-adjoint differential operator is usually called a quantum graph.
Michael Solomyak, On the spectrum of the Laplacian on regular metric trees, Waves Random Media 14 (2004), no. 1, S155–S171, Special section on quantum graphs.
M. J. Gruber, D. Lenz, and I. Veseli′c, Uniform existence of the integrated density of
states for combinatorial and metric graphs over Zd, Preprint arXiv:0712.1740 (2007).
M. J. Gruber, D. Lenz, and I. Veseli′c,, Uniform existence of the integrated density of states for random Schr¨odinger operators on metric graphs over Zd, J. Funct. Anal. 253 (2007), no. 2, 515–533.
M. Helm and I. Veseli′c, Linear Wegner estimate for alloy-type Schr¨odinger operators on metric graphs, J. Math. Phys. 48 (2007), no. 9, 092107, 7.
F. Klopp and K. Pankrashkin, Localization on quantum graphs with random vertex couplings,J. Statist. Phys. 131 (2008), 561–673.
V. Kostrykin and R. Schrader, [KS04] , A random necklace model, Waves Random Media 14 (2004), no. 1, S75–S90,Special section on quantum graphs.
P. Kuchment, Quantum graphs: I. Some basic structures, Waves Random Media 14
(2004), S107–S128.
P. Kuchment, [Ku05] , Quantum graphs. II. Some spectral properties of quantum and combinatorial
graphs, J. Phys. A 38 (2005), no. 22, 4887–4900.
P. Kuchment, [Ku08] , Quantum graphs: an introduction and a brief survey, Preprint
arXiv:0802.3442 (2008).
D. Lenz, C. Schubert, and P. Stollmann, Eigenfunction expansions for Schr¨odinger operators
on metric graphs, Preprint arXiv:0801.1376 (2008).
Beng-Seong Ong, On the limiting absorption principle and spectra of quantum graphs,
Preprint (2005).
G. Berkolaiko, R. Carlson, St. A. Fulling, and P. Kuchment (eds.), Quantum graphs
and their applications, Contemporary Mathematics, vol. 415, Providence, RI, American
Mathematical Society, 2006.
P. Exner, M. Helm, and P. Stollmann, Localization on a quantum graph with a random
potential on the edges, Rev. Math. Phys. 19 (2007), no. 9, 923–939.

Smilansky Quantum chaos on discrete graphs p16
quantum (metric) graphs
quantum chaos on quantum (metric) graphs [1], spectral? functions and trace formulae for discrete Laplacians on graphs
quantum (metric) graphs were proposed as a convenient paradigm for the study of quantum chaos in compact [1] and scattering [5] systems.
Tsampikos Kottos and Uzy Smilansky, Quantum Chaos on Graphs, Phys. Rev. Lett. 79,4794-
4797, (1997). and Periodic orbit theory and spectral statistics for quantum graphs, Annals of
Physics 274, 76-124 (1999).
Peter Kuchment, Quantum Graphs: I. Some basic structures. Waves in random Media 14 (2004),
S107-S128.
Sven Gnutzmann and Uzy Smilansky, Quantum Graphs: Applications to Quantum Chaos and
Universal Spectral Statistics. Advances in Physics bf 55 (2006) 527-625.

Vinci Hearing the Shape of the Ising Model with a Programmable Superconducting-Flux Annealer p13
metric graphs
non-isomorphic quantum co-Ising graphs

connected metric graph

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
quantum graph (QG)
Quantum Tree Graphs
A quantum graph (QG) is a metric graph
rooted metric tree graph
connected metric graph
metric graphs
finite metric graph
general metric tree graphs
metric tree graphs

T. Kottos and U. Smilansky. Periodic orbit theory and spectral statistics for quantum graphs. Ann. Phys.
274:76–124, 1999.
P. Kuchment. Quantum graphs: I. Some basic structures. Waves and random media, 14:S107–S128,
2004.
P. Kuchment. Quantum graphs II. Some spectral properties of quantum and combinatorial graphs,
preprint. To appear in J. Phys. A.

quantum (metric) graphs

Smilansky Quantum chaos on discrete graphs p16

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

quantum graphs metric graphs

infinite quantum graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

radial quantum graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

random quantum graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

radial random quantum graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

quartic graph

Cosentino On some combinatorial properties of graph states p78

Qubit graph?? !!!!!!!!!! okokok ???

Dribus Quantum Circuit Graphs p29
Dribus Quantum Circuit Graphs p29
10-qubit graph

Quotient graph

Audenaert Symmetric Squares of Graphs p19

quotient graph
Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

quotient graph or collapsed graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

quotient graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Ramanujan graphs

Ben-Aroya Quantum expanders and the quantum entropy difference problem p30

RANDOM GRAPHS?? !!!!!!!!!!!!!!!

RANDOM GRAPHS
random threshold graph
graph limits

graph growth
randomly grown graphs
Passerini The von Neumann entropy of networks p5

Cameron On the quantum chromatic number of a graph p7

Anand The Shannon and the Von Neumann entropy of random networks with heterogeneous expected degree p10

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

JAKOBSON EIGENVALUE SPACINGS FOR REGULAR GRAPHS p21

random graph
Severini Graphs of unitary matrices p19

Ben-Aroya Quantum expanders and the quantum entropy difference problem p30

Hamma A quantum Bose-Hubbard model with evolving graph as toy model for emergent spacetime p23

Hu Spectral Descriptors for Graph Matching p15
Konopka Quantum Graphity: a model of emergent locality p25

Lovasz Very large graphs p63
Perseguers Quantum complex networks p5
Szabo Evolutionary games on graphs p133

random graphs
Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

Random graphs
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

random graph
Duplantier Liouville Quantum Gravity as a Mating of Trees p122

random graphs

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

random graphs??????????
Verstraete_Simulating_Strongly_Correlated_Quantum_Systems.pdf

random graphs
Wu Randomized Graph States and their Entanglement Properties p17

Nagaj Local Hamiltonian in quantum computation p176
random graphs

Barab′asi-Albert (BA) random graph

Nicosia Co-evolution of networks and quantum dynamics: a generalization of preferential attachment p8

Erdos-Renyi random graphs

Wu Randomized Graph States and their Entanglement Properties p17

random multigraph

Marin Access Structure in Graphs in High Dimension and Application to Secret Sharing p16

Regular digraph

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11.pdf

Regular graph?? !!!!!!!!!!!!!!!

Regular graph

Kirkland α-Kuramoto partitions graph partitions from the frustrated Kuramoto model generalise equitable partitions p7.pdf
SMITH CELLULAR ALGEBRAS AND GRAPH INVARIANTS BASED ON QUANTUM WALKS p14.pdf

Vazquez Perturbation theory in a pure exchange non-equilibrium economy p7.pdf
Wolf Quantum Computing Lecture Notes p112.pdf

Emms A matrix representation of graphs and its spectrum as a graph invariant p14

Passerini The von Neumann entropy of networks p5

Smilansky Quantum chaos on discrete graphs p16

Audenaert Symmetric Squares of Graphs p19
GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

d-regular graphs
Markov Simulating quantum computation by contracting tensor networks p21

Anand The Shannon and the Von Neumann entropy of random networks with heterogeneous expected degree p10

JAKOBSON EIGENVALUE SPACINGS FOR REGULAR GRAPHS p21
Ben-Aroya Quantum expanders and the quantum entropy difference problem p30
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Gamble Two-particle quantum walks applied to the graph isomorphism problem p12

Godsil State Transfer on Graphs p37

Hamma A quantum Bose-Hubbard model with evolving graph as toy model for emergent spacetime p23

Konopka Quantum Graphity: a model of emergent locality p25
Osborne Quantum Algorithms and Covering Spaces p7

Perseguers Quantum complex networks p5

Szabo Evolutionary games on graphs p133

Regular graphs
strongly-regular graphs
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Regular graphs

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

regular graph
Feder Graphs in Quantum Information Theory p19

regular graphs

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

k-regular graph

Lovett Application of quantum walks on graph structures to quantum computing p239

regular graphs

Markov Simulating quantum computation by contracting tensor networks p21

regular graphs

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

regular graphs????????????????????

Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6

regular graph

Spalek Classical Simulation of Quantum Systems via Tensor Networks p30

regular graphs

[de) Wolf2014] de Wolf, Ronald: Quantum Computing: Lecture Notes, April 2014.

regular graph
Cosentino On some combinatorial properties of graph states p78

3-regular tree

Spalek Classical Simulation of Quantum Systems via Tensor Networks p30

Strongly regular graphs

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Relation graph

Dribus Quantum Circuit Graphs p29

reliability graph

Boncalo Simulation-Based Assessment of Quantum Circuit Reliability p33.pdf


Untitled Document

Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

S-W

scale-free graph

Passerini The von Neumann entropy of networks p5

Konopka Quantum Graphity: a model of emergent locality p25

Szabo Evolutionary games on graphs p133

scattering graph??? !!!!!!!!? okokok

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

scattering graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Schreier graph

Osborne Quantum Algorithms and Covering Spaces p7

Schreier graph

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

self-energy graph

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

electron self-energy graph

Schwartz Introduction to Quantum Field Theory p262

photon self-energy graph

Schwartz Introduction to Quantum Field Theory p262

Shrikhande graph

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

Shrikhande graph
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

signed graphs

Godsil State Transfer on Graphs p37

signed graphs
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

signed graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

Signed graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

simple graph

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

simple graph
HEIN Entanglement in Graph States and its Applications p99

simple graph
Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

simple graph

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

simple graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

simple graph
Cosentino On some combinatorial properties of graph states p78

social graph

Szabo Evolutionary games on graphs p133

spanning subgraph?? !!!!!!!!!!!!!!!!!!!!!!!!

Bernasconi Quantum Networks on Cubelike Graphs p11

spanning subgraph

Godsil Colouring an Orthogonality Graph p13
spanning subgraph

Gutin Hamilton Cycles in Digraphs of Unitary Matrices p10

spanning subgraph
Klavzar Tensor 2-sums and entanglement p5

spanning subgraph

Severini Nondiscriminatory Propagation on Trees p5

spanning subdigraph
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

spanning subgraphs
Wu Randomized Graph States and their Entanglement Properties p17

spectral graph theory

Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75.pdf

split graph

SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11

Star graphs!!!!!!!!!!!!!!!!!!!!!!!

Cosentino Weight of quadratic forms and graph states p7
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

star graph
Bera On Finding Sensitivity of Quantum and Classical Gates p15

star graph
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

star graphs
Banerji A notion of graph likelihood and an infinite monkey theorem p6
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Wu Randomized Graph States and their Entanglement Properties p17

Aharonov The quantum FFT can be classically simulated p12

star graphs
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

star graph
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

star graph
Cosentino Weight of quadratic forms and graph states p7

star graph
Feder Graphs in Quantum Information Theory p19

star graph
HEIN Entanglement in Graph States and its Applications p99

star graph
Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

Star graphs
Wu Randomized Graph States and their Entanglement Properties p17

star graph

Cosentino On some combinatorial properties of graph states p78

(Quantum) State Graph (SG)

State Graph (SG)

[Chang2004]
Chang 自動合成量子循序電路Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications p71.pdf

Background info about the quantum circuits

self-timed circuit specifications
sequential quantum Boolean circuits (SQBCs)
State graphs (SGs)
Toffoli gates
quantum gates

transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs)
State graphs (SGs) are used to describe the behaviors of self-timed circuits
and then are translated into SQBCs based on Toffoli gates

The concept of IP (Intellectual Property) reuse is applied to the constructed SQBCs to produce reusable and composable quantum Boolean circuits (CQBCs).

Complete State Coding State Graph (CSCSG)

[Chang2004]
Complete State Coding State Graph (CSCSG)

For each edge e with source node i and target node j in a CSCSG a corresponding transformation sub-graph (TSG) is formed for the target node j.

complete state coding state graph
[Chang2004] Chang, Li-Kai (張立楷):自動合成量子循序電路Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications, Master thesis, 大同大學Tatung University, Taiwan, Aug 2004.

Steane graph?? ???

Feder Graphs in Quantum Information Theory p19

tensor-elementary graph

Klavzar Tensor 2-sums and entanglement p5

Threshold graphs

Threshold graphs

Kirkland Spin systems dynamics and faults detection in threshold networks p6.pdf

threshold graphs

Severini Two-colorable graph states with maximal Schmidt measure p6

topological graphs

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

torus graph

Osborne Quantum Algorithms and Covering Spaces p7

m-torus graph

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

transformation digraph!!!!!!!!!!!!!!!!!!!!!!!? okokok

quantum state transformation digraph

quantum state transformation digraph ASTDG? [Chang2004]

permutation
A permutation consists of one or multiple disjoint cycles. Since disjoint cycles commute, each cycle in the permutation can be implemented individually. To do this, a quantum state transformation digraph, G = (V, E), where
V = {vi | vi = ? [i][*]}
E = {(vs, vd) | vs = ? [i][*], vd ? φ[i][*]} (3.2)
and 0 ≤ i ≤ 2t – 1.

vertices
The digraph has 2t vertices, corresponding to each of the 2t rows in the ? table.

edges
An edge is defined from vs to vd if it is possible for permutation Q to map vs to vd. The notation vd ? φ[i][*] is used to denote, where only u (u < t) qubits are specified in φ[i][*], all states that are compatible to the entry. This results in 2t-u edges to be generated for each of the possible (vs, vd) pairs. Filling in the t – u blank qubits in the φ table selects one of the possible edges and delete others.

quantum transformation table
ASTDG is used to generate the quantum transformation table

Figure 3.4: The quantum state transformation digraph of a half-adder

quantum state transformation digraph
[Chang2004] Chang, Li-Kai (張立楷):自動合成量子循序電路Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications, Master thesis, 大同大學Tatung University, Taiwan, Aug 2004.

transformation graph

Quantum state transformation graph

Tsai Quantum Boolean circuits and layout under locality constraint
quantum state transformation digraph

Tsai Quantum Boolean circuits and layout under locality constraint
Sunday, October 28, 2001—S3.1 Nanocircuits and Architectures, IEEE-NANO 2001
quantum state transformation digraph

transformation graph (TG) !!!!!!!!!!!!!!!!!!!!!!!? okokok

self-timed transformation graph (STTG) - a hyper-graph

[Chang2004]

self-timed transformation graph (STTG)
Thus a STTG is a hyper-graph.

Remark: 1. A STTG is a hyper-graph containing many TSGs.
Remark: 1. A STTG is a hyper-graph containing many TSGs.

For a state graph specifying a sequential circuit with m-bit input, n-bit output and e edges (i.e. e next-state functions), a self-timed transformation graph (STTG) corresponding the state graph has e transformation sub-graphs (TSG) and

Each edge in the STTG represents a transition from one state to another.

Self-Timed Transformation Graph
[Chang2004] Chang, Li-Kai (張立楷):自動合成量子循序電路Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications, Master thesis, 大同大學Tatung University, Taiwan, Aug 2004.

decomposed STTG

[Chang2004]
decomposed STTG

composable STTG??

[Chang2004]
composable STTG

To synthesize CQBCs, the composable STTGs are transferred from decomposed STTGs. An auxiliary qubit with initial value 0’s is appended to each state binary code of all nodes in STTGs. An auxiliary node with sbc(the corresponding target node) is added for each TSG in a STTG and then set the auxiliary bit of the auxiliary node to 1. The new STTGs is called composable STTGs. The algorithm of generating composable STTG is shown in Algorithm 6.

composable QBCs (CQBCs)
Composable Quantum Boolean Circuits

The composable STTGs contains two operation blocks: a core operation block representing the same circuit behavior of non-composable QBCs and a composable operation block preventing going to a wrong state if repeated operations are applied.
The core operation block is made by the quantum operations constructed with the source and target nodes and the composable operation block is made by the quantum operations with the target and auxiliary nodes.
The algorithm of constructing CQBCs is shown in Algorithm 7.

Algorithm 6 Transfer to Composable STTG
Input: A decomposed STTG, DSTTG
Output: A composable STTG, CSTTG
Remark: 1. A STTG is a hyper-graph containing many TSGs.
2. The state binary code of a node is defined as sbc(node).

Algorithm 7 Construct Composable Quantum Boolean Circuits
Input: A composable STTG, CSTTG
Output: A composable QBC, CQBC
Remark: 1. A STTG is a hyper-graph containing many TSGs.
2. A QBC contains quantum operations.
3. A TSG in CSTTG contains the source, target and auxiliary nodes

reusable STTG

[Chang2004]

reusable STTG

transformation sub-graphs (TSG)

[Chang2004]

transformation sub-graphs (TSG)

each TSG consists of two nodes connecting to each other by two direct edges. If the nodes in a TSG indicate the same state the sub-graph degenerates into a self-loop sub-graph. Thus a STTG is a hyper-graph.

For each edge e with source node i and target node j in a CSCSG a corresponding transformation sub-graph (TSG) is formed for the target node j. The TSG consists of two new nodes source and target connecting to each other by two direct edges (i.e. source → target, target → source). These two direct edges are called quantum links (marked in dashed lines). The state binary codes of the source and target nodes are labeled with ib(j) + ob(i) + sb(i) and ib(j) + ob(j) + sb(j), respectively. The function sb(i) is the state bits binary code function which is similar to ib(i) and ob(i) in the section 2.2.2.

transport graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p167
transport graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

transpose graph

Braunstein Some families of density matrices for which separability is easily tested p14

transposed graph

partially transposed graph

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

transitive graphs!!!!!!!!!!!!!!!!!!!!!!!

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

transitive graphs
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

edge transitive graph

GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

vertex-transitive graph

vertex-transitive graph

Godsil Colouring an Orthogonality Graph p13.pdf

Audenaert Symmetric Squares of Graphs p19

Cameron On the quantum chromatic number of a graph p7

GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

Godsil State Transfer on Graphs p37

Vinci Hearing the Shape of the Ising Model with a Programmable Superconducting-Flux Annealer p13

vertex transitive graph
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

vertex-transitive graph

Godsil Colouring an Orthogonality Graph p13
Godsil Colouring an Orthogonality Graph p13

tree graphs!!!!!!!!!!!!!!!!!!!!!!!

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

Tree graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

tree graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

tree graph

Verstraete_Simulating_Strongly_Correlated_Quantum_Systems.pdf

tree graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Trees Graph

Glued-Trees Graph

Glued trees graph
Ambainis Quantum walks and their algorithmic applications p11.pdf

glued-trees graph
Feder Graphs in Quantum Information Theory p19
P 8, 9

Lovett Application of quantum walks on graph structures to quantum computing p239

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

glued-trees graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

generalized radial tree graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Tree graphs
generalized radial tree graphs

metric tree graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

quantum tree graphs???

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Quantum Tree Graphs
Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

radial tree graph

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Random quantum tree graphs

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Binary Welded Tree (BWT) graphs

Herrman Continuous Time Quantum Walks p1

regular tree graph

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

rooted metric tree graph

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

rooted metric tree graph

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

tree-level graph

Schwartz Introduction to Quantum Field Theory p262

treelike graphs

Random, locally treelike graphs

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

triangular graph

Dribus Quantum Circuit Graphs p29

unicyclic graphs

Severini Two-colorable graph states with maximal Schmidt measure p6.pdf

uncyclic graphs

Severini Two-colorable graph states with maximal Schmidt measure p6

union graph

disjoint union graph

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

universal graph !!!!!!!!!!!!!!!!!!!!!!!

universal graph for Universal quantum circuits

[Valiant1976]
[Bera2008]
Valiant looked at a similar problem—trying to minimize the size of the universal circuit [Val76]. He considered classical circuits built from fanin 2 gates (but with unbounded fanout) and embedded the circuit in a larger universal graph. Using switches at key vertices of the universal graph, any graph (circuit) can be embedded in it. He managed to create universal graphs for different types of circuits and showed how to construct a O(c log c)-size and O(c)-depth universal circuit. He also showed that his constructions have size within a constant multiplicative factor of the information theoretic lower bound.

Then, Valiant shows how to construct a universal graph.
Theorem 8 ([Val76]). There is a constant k such that or all n there exists an acyclic graph G0 that is edge-universal for 2(n), and G0 has kn lg n vertices, each vertex having fanin and fanout 2.
It is fairly easy to construct a universal circuit using the universal graph.
In fact, the universal circuit for circuits with n inputs and c gates will be any edge-universal graph for 2(n + c).

BERA QUANTUM CIRCUITS POWER AND LIMITATIONS p117.pdf

Edge-universal graph

universal graph
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

Universal graph

[Bera2008] Universal Quantum Circuits p12
www.cse.sc.edu/~fenner/papers/univcirc.pdf
Bera Universal quantum circuits p12
Bera Universal Quantum Circuits1 p12
Bera Universal Quantum Circuits p13

Edge-universal graph

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

[Bera2008] Universal Quantum Circuits p12
www.cse.sc.edu/~fenner/papers/univcirc.pdf
Bera Universal quantum circuits p12
Bera Universal Quantum Circuits1 p12
Bera Universal Quantum Circuits p13

?????????????????????????????????????????????????????????????????????????????????????????????

weighted graph!!!!!!!!!!!!!!!!!!!!!!!

Ambainis New Developments in Quantum Algorithms p11.pdf
weighted graph

Ambainis New Developments in Quantum Algorithms p11

weighted graphs

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

weighted graph
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4

weighted graph

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

weighted graphs

HEIN Entanglement in Graph States and its Applications p99

weighted graph

Jeffery Frameworks for Quantum Algorithms p166.pdf

Weighted graph

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

weighted graph

Shafaei Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures p6

weighted graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

weighted graph
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

weighted graph
Tsai Quantum Boolean circuits and layout under locality constraint

vertex-weighted graph

Cabello Graph-Theoretic Approach to Quantum Correlations p6

widget graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

widget graphs
Underwood Quantum Walk Schemes for Universal Quantum Computation p267


Untitled Document

Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

graph operations

graph operations/structure graph

Graph /Hypergraph Clustering?

Graph /Hypergraph Colouring problems

graph colorings
Budhathoki Automatic synthesis of quantum circuits for point addition on ordinary binary elliptic curves p14

graph colouring problem in quantum information theory

Godsil Colouring an Orthogonality Graph p13.pdf

Scarpa Kochen-Specker Sets and the Rank-1 Quantum Chromatic Number p12.pdf

Enciso Introduction to Quantum Computing p11.pdf

Rieffel An Introduction to Quantum Computing for Non-Physicists p45.pdf
Cameron On the quantum chromatic number of a graph p7

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

HEIN Entanglement in Graph States and its Applications p99

graph coloring problem
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

graph colouring problem

Godsil Colouring an Orthogonality Graph p13

Graph coloring
Lucas Adiabatic Quantum Computing p47.pdf

graph coloring

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

graph colouring game

PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31

graph coloring
Reid On the Evolutionary Design of Quantum Circuits p93

Nagaj Local Hamiltonian in quantum computation p176
graph coloring

Graph 3-colorability

Nagaj Local Hamiltonian in quantum computation p176

Graph Covering Spaces

Osborne Quantum Algorithms and Covering Spaces p7

graph covering and equitable partitions
Severini Nondiscriminatory Propagation on Trees p5

graph decomposition

Raussendorf Measurement-based quantum computation on cluster states p37

graph expander

classical Cayley graph expander

Harrow Efficient Quantum Tensor Product Expanders and k-designs p16

graph expansion

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

graph game

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

graph growth

Nicosia Co-evolution of networks and quantum dynamics: a generalization of preferential attachment p8

graph infection

Burgarth Logic circuits from zero forcing p5

graph mining

Kondor The Graphlet Spectrum p8

Graph /Hypergraph Partitioning

graph partitions

Kirkland α-Kuramoto partitions graph partitions from the frustrated Kuramoto model generalise equitable partitions p7.pdf

Graph products

Scarpa Kochen-Specker Sets and the Rank-1 Quantum Chromatic Number p12.pdf
GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

graph products
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

graph product
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19
graph product
Klavzar Tensor 2-sums and entanglement p5

Graph tensor products

Klavzar Tensor 2-sums and entanglement p5

natural graph product

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

n-fold graph product

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

strong graph product

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

(strong) graph product
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

graph? propagation

Burgarth Logic circuits from zero forcing p5

Graph scattering

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

graph seriation

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Graph seriation
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

graph state reduction (GSR) and graph state extension (GSE) passes

Voufo Quantum Circuits From a Network to a One-Way Model - A Tutorial Version p28.pdf

graph transformations

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

graph transformations
Severini Two-colorable graph states with maximal Schmidt measure p6

graph transformations
Cosentino On some combinatorial properties of graph states p78

graph Fourier transform

Hu Spectral Descriptors for Graph Matching p15

Graph traversal

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

graph traversal technique

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11

graph traversal
Osborne Quantum Algorithms and Covering Spaces p7

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
graph traversal

graph union

Cosentino Weight of quadratic forms and graph states p7

Graph Union
Cosentino On some combinatorial properties of graph states p78

hypergraph-product

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

quantum hypergraph-product code

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

hypergraph-product ansatz

quantum hypergraph-product LDPC codes

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

hypergraph-product

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

quantum hypergraph-product code

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

hypergraph-product ansatz

quantum hypergraph-product LDPC codes

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf


Untitled Document

Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

Graph / Hypergrah features

graph ?…

Graph / Hypergrah features / instances / variables / parameters / relations

graph automorphism

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

graph codes

graph codes
graph codes
Cosentino On some combinatorial properties of graph states p78

HEIN Entanglement in Graph States and its Applications p99
HEIN Entanglement in Graph States and its Applications p99

Raussendorf Measurement-based quantum computation on cluster states p37

graph colorability

Reid On the Evolutionary Design of Quantum Circuits p93

graph complement

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

graph functional

PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31

Graph Gadget

Zhan Super-Polynomial Quantum Speed-ups for Boolean Evaluation Trees with Hidden Structure p1

graph geodesic

Matthias Perfect Transfer of Arbitrary States in Quantum Spin Networks p12

graph Hamiltonian

Herrman Continuous Time Quantum Walks p1

graph Hamiltonian
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

graphs homeomorphic

Severini Nondiscriminatory Propagation on Trees p5

graph homomorphisms

GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18
Chailloux Graph-theoretical Bounds on the Entangled Value of Non-local Games p10

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lov′asz # Number and its Variants p15
PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31

graph homomorphisms????????

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Graph homomorphisms

PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31

GRAPH INVARIANTS / regular graphs / graph isomorphism / equivalent graphs

SMITH CELLULAR ALGEBRAS AND GRAPH INVARIANTS BASED ON QUANTUM WALKS p14.pdf

Emms A matrix representation of graphs and its spectrum as a graph invariant p14
graph invariant
Banerji A notion of graph likelihood and an infinite monkey theorem p6

Vinci Hearing the Shape of the Ising Model with a Programmable Superconducting-Flux Annealer p13

Graph invariant?????????????????????????
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

graph invariants
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

graph invariants
Cosentino On some combinatorial properties of graph states p78

Graphlet Spectrum / graph invariants

Kondor The Graphlet Spectrum p8
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

graph isomorphism problem

Gruska QUANTUM COMPUTING p438.pdf

SMITH CELLULAR ALGEBRAS AND GRAPH INVARIANTS BASED ON QUANTUM WALKS p14.pdf

Rieffel An Introduction to Quantum Computing for Non-Physicists p45.pdf

Santha Introduction to quantum computing p31.pdf

MCKAY HADAMARD E UIVALENCE VIA GRAPH ISOMORPHISM p2

Audenaert Symmetric Squares of Graphs p19

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Gamble Two-particle quantum walks applied to the graph isomorphism problem p12

HEIN Entanglement in Graph States and its Applications p99

graph isomorphism
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20
Graph isomorphism
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

graph isomorphism problem
Feder Graphs in Quantum Information Theory p19.pdf

graph isomorphism problem
Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

Graph isomorphisms
HEIN Entanglement in Graph States and its Applications p99
graph isomorphism problem
Lovett Application of quantum walks on graph structures to quantum computing p239

graph isomorphism

[Nielsen2010] Nielsen, Michael A. & Chuang, Isaac L.: ?Quantum Computation and Quantum Information, Cambridge University Press, 2010, p698
58

graph isomorphism problem

[Rotteler2005] R?tteler, Martin: Introduction to Quantum Algorithms Part I: Quantum Gates and Simon’s Algorithm, August 31, 2005 p247

GRAPH ISOMORPHISM

Santha Introduction to quantum computing p31

graph isomorphism problem

Watrous An introduction to quantum information and quantum circuits p16

graph isomorphism
Cosentino On some combinatorial properties of graph states p78

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

graph isomorphism

Nagaj Local Hamiltonian in quantum computation p176

graph isomorphism
Cayley trees
infinite Cayley tree
infinite tree (Bethe lattice)
NAND tree

Sub-graph isomorphism

Lucas Adiabatic Quantum Computing p47.pdf

graph kernels

Kondor The Graphlet Spectrum p8

graph likelihood

Banerji A notion of graph likelihood and an infinite monkey theorem p6

GRAPH LIMITS

JANSON AN EXAMPLE OF GRAPH LIMITS OF GROWING SEQUENCES OF RANDOM GRAPHS p11.pdf

graph minors

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

graph nonisomorphism problem

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

graph polynomials

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20
Vinci Hearing the Shape of the Ising Model with a Programmable Superconducting-Flux Annealer p13

graph polynomials
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

graph powers

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

disjunctive graph powers?

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

strong graph powers

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Graph spectra

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

graph states

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
(Quantum Hypergraph States C. Macchiavello,1, ?M. Rossi,1 M. Huber,2, 3, 4 and D. Bru?5)

Braunstein Some families of density matrices for which separability is easily tested p14

H. J. Briegel and R. Raussendorf, Phys. Rev. Lett. 86 (2001) 910.

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

Cosentino On some combinatorial properties of graph states p78
Cosentino Weight of quadratic forms and graph states p7

Devitt Quantum Information Engineering: Concepts to Quantum Technologies p289

Feder Graphs in Quantum Information Theory p19.pdf

HEIN Entanglement in Graph States and its Applications p99

Hui Unconventional quantum gate based on Rydberg blockade mechanism p5.pdf??????????

Markov Simulating quantum computation by contracting tensor networks p21

Marin Access Structure in Graphs in High Dimension and Application to Secret Sharing p16

Raussendorf Measurement-based quantum computation on cluster states p37

[Rossi 2013] Rossi ,M.;? Huber, M;. Bru?, D. and Macchiavello, C.: Quantum Hypergraph States, New
Journal of Physics, Volume 15, Issue 11, article id. 113022 (2013)., ?? 11/2013

Voufo Quantum Circuits: From a Network to a One-Way Model - A Tutorial Version p28

Severini Two-colorable graph states with maximal Schmidt measure p6

Wu Randomized Graph States and their Entanglement Properties p17

edge graph states

Cosentino On some combinatorial properties of graph states p78

entangled graph states

Devitt Quantum Information Engineering: Concepts to Quantum Technologies p289
Lovett Application of quantum walks on graph structures to quantum computing p239
entangled graph states

geometric graph state

Devitt Quantum Information Engineering: Concepts to Quantum Technologies p289

quantum graph states

Cosentino Weight of quadratic forms and graph states p7

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf

Passerini The von Neumann entropy of networks p5

[Rossi 2013]
quantum graph state

Severini Two-colorable graph states with maximal Schmidt measure p6.pdf
Two-colorable graph states

Wu Randomized Graph States and their Entanglement Properties p17
quantum graph states

qudit graph states

Marin Access Structure in Graphs in High Dimension and Application to Secret Sharing p16

Randomized Graph States

Wu Randomized Graph States and their Entanglement Properties p17

two-colorable graph states

Severini Two-colorable graph states with maximal Schmidt measure p6

vertex graph states

Cosentino On some combinatorial properties of graph states p78

weighted graph states

HEIN Entanglement in Graph States and its Applications p99

Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6
weighted graph states

graph state extension (GSE)???

Voufo Quantum Circuits: From a Network to a One-Way Model - A Tutorial Version p28

graph state reduction (GSR)

Voufo Quantum Circuits: From a Network to a One-Way Model - A Tutorial Version p28

graph topology

Smilansky Quantum chaos on discrete graphs p16

complete-graph tensor network states

Verstraete_Simulating_Strongly_Correlated_Quantum_Systems.pdf


Untitled Document

Graph Theory for Quantum Circuits

Graph Theory and Quantum Chips

graphs from? … / … of graph / … on graph / graph components / characteristics…of graph

graphs from? …

graphs from anti-Hadamard matrices

graphs from anti-Hadamard matrices

Severini Two-colorable graph states with maximal Schmidt measure p6
Severini Two-colorable graph states with maximal Schmidt measure p6.pdf

… of graph?

Kotzig orbit of graphs

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

quantum chromatic number of graph

Cameron On the quantum chromatic number of a graph p7

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

?… on Graph

Quantum walks on Graphs

graph components / characteristics…of graph

Characteristics of graphs / hypergraphs

Cartesian product of graphs

GODSIL SABIDUSSI VERSUS HEDETNIEMI FOR THREE VARIATIONS OF THE CHROMATIC NUMBER p18

chromatic number of graph

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Cospectrality of graphs

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

density matrices of graphs

Braunstein Some families of density matrices for which separability is easily tested p14
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

density matrices of graphs
Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Density matrices of graphs
Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

graph of graphs

Dribus Quantum Circuit Graphs p29

independence number of graph

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

invariant of graphs

Cosentino On some combinatorial properties of graph states p78

partial transpose of graphs

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

projective rank of graph

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Shannon Capacity of Graph

Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30

spectrum of graph

Severini Two-colorable graph states with maximal Schmidt measure p6

strong product of graphs

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

strong product of two graphs

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

symmetric powers of graph

Audenaert Symmetric Squares of Graphs p19

Symmetric Squares of Graphs

Audenaert Symmetric Squares of Graphs p19

tensor powers of graphs

Klavzar Tensor 2-sums and entanglement p5

Tensor product of graphs

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Tensor product of graphs

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

tensor product of graphs

Klavzar Tensor 2-sums and entanglement p5

direct product of hypergraphs

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

Composition of graphs

digraph of unitary matrix

digraph of a unitary matrix

[SEVERINI2003] SEVERINI, SIMONE: ON THE DIGRAPH OF A UNITARY MATRIX, May 2002: SIAM Journal on Matrix Analysis and Applications, Volume 25, Number 1, pp.295-300, July 2003. p6

Graphs of unitary matrices

Severini Graphs of unitary matrices p19


Untitled Document

Graph Theory and Quantum Circuits

Chimera graph

Literature – Chimera graph

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

Albash Distinguishing Classical and Quantum Models for the D-Wave Device
“Chimera” graph ……..? Excluding the coupling to
Chimera hardware graph [30]. Then both Jij and Jjk are existing “legitimate” couplings in the unit cell
[30] R. Harris, J. Johansson, A. J. Berkley, M. W. Johnson, T. Lanting, S. Han, P. Bunyk, E. Ladizinsky, T. Oh, I. Perminov, E. Tolkacheva, S. Uchaikin, E. M. Chapple, C. Enderud, C. Rich, M. Thom, J. Wang, B. Wilson, and G. Rose, Phys. Rev. B 81, 134510 (2010).
http://dx.doi.org/%2010.1103/PhysRevB.81.134510
K4;4 bipartite graph which together form the “Chimera” connectivity graph [44]
[44] V. Choi, Quant. Inf. Proc. 10, 343 (2011).
http://dx.doi.org/10.1007/s11128-010-0200-3
embeddings spread across the Chimera graph

Albash Fluctuation theorems for quantum processes
Figure 6 is
a schematic of the device, showing the allowed couplings between the qubits which form a “Chimera” graph [51,52].
[51] V. Choi, Quantum Inf. Process. 7, 193 (2008).
http://dx.doi.org/10.1007/s11128-008-0082-9
[52] V. Choi, Quantum Inf. Process. 10, 343 (2010).
http://dx.doi.org/10.1007/s11128-010-0200-3

Albash Reexamining classical and quantum models for the D-Wave One processor
the Ising couplings along the edge set E of the Chimera graph G
the couplings Jij , subject to the Chimera graph connectivity
Chimera graph of the DW1. Black lines indicate couplings Jij

Ambainis New Developments in Quantum Algorithms p11.pdf

Ambainis Quantum walks and their algorithmic applications p11.pdf

????????????
D. Avis, J. Hasegawa, Y. Kikuchi, and Y. Sasaki. A quantum protocol to win the graph colouring game on all hadamard graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., E89-A(5):1378–1381, 2006. arXiv:quant-ph/0509047v4,doi:10.1093/ietfec/e89-a.5.1378.

Barnum Quantum circuits for OR and AND of ORs p15
Barnum Quantum circuits for OR and AND of ORs p11.pdf

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf

Boixo Evidence for quantum annealing with more than one hundred qubits
We performed our tests on a D-Wave One device, comprised of superconducting flux qubits with programmable couplings (see Methods). Of the 128 qubits on the device, 108 were fully functioning and were used in our tests. The `chimera' connectivity graph of these qubits is shown in Supplementary Fig. 1.
Because the tree width of the chimera graph scales as p N26, exact solvers making use of the graph structure scale asymptotically no worse than exp.c p N/ and similar scaling is observed also for the simulated annealers discussed below.
It will be interesting to explore whether a quantum annealer might exhibit better scaling than classical algorithms for these problem sizesand hence quantum accelerationor whether it can be e?ciently matched, or even surpassed by classical algorithms such as simulated annealing, simulated quantum annealing, mean-field approaches, or other algorithms that exploit the structure of the chimera graph.

Boixo Quantum annealing with more than one hundred qubits

Bozbey SFQ Analog and Digital Circuit Design: Circuit Optimization and Timing Analysis

[Bullock2004] Bullock, Stephen S.: Quantum Circuits for d-level Systems, Quantum Information Theory and Practice seminar, November 4, 2004 p36.pdf
[Bullock2004] Bullock, Stephen S.: Quantum Circuits for d-level Systems, Quantum Information Theory and Practice seminar, November 4, 2004 p36.pdf

Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf
[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.
[Bunyk2014]? Bunyk, P. I.et al: Architectural considerations in the design of a superconducting quantum annealing processor, 21 Jan 2014.
Bunyk D-Wave Processor Control Circuitry p48

Bunyk201401 Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor p9
Paul I. Bunyk, Member, IEEE, Emile M. Hoskinson, Mark W. Johnson, Member, IEEE, Elena Tolkacheva, Fabio Altomare, Andrew J. Berkley, Richard Harris, Jeremy P. Hilton, Trevor Lanting, Anthony J. Przybysz, and Jed Whittaker
P. I. Bunyk
email:
pbunyk@dwavesys.com
21 Jan 2014
P3

quantum annealing processor
tunable coupled rf-SQUID flux qubits
superconducting integrated circuit
programmable inter-qubit couplers
quantum algorithm
XYZ addressing scheme
qubit energy scale
qubit inductance and capacitance
Read-out infrastructure
hardware graph topology, which we named Chimera
non-planarity of the underlying graph
Ising-spin glass problems
embed complete graphs = map, or embed the problem graph into the available hardware graph
chains, trees, or other connected sub-components of the hardware graph (comprising physical qubits, strongly ferromagnetically coupled to each other) to represent a single node in the problem graph (logical qubit).
In the language of graph theory, we want the hardware graph to have largest possible variety of problem graphs as its minors [15].
control “knobs”
static flux biases
flux DACs, or Φ-DACs
coupling energy scale
coupling strengths
Flux qubits and couplers are rf SQUIDs
Processor graph
unit tile
Chimera topology
flux qubit
qubits based on quantum dots
qubits based on individual trapped ions
Josephson junction
qubit body loops
qubit to-qubit couplers [17]–[19]
Chimera unit tile (unit cell ???) topology
complete bipartite graph K4;4.
The Chimera graph is non-planar

Bunyk201408 Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor p10
AUGUST 2014
Our current hardware graph topology, which we named Chimera, was designed to satisfy a number of common-sense requirements related to its intended use for solving optimization problems, subject to a number of physical implementation constraints.
non-planarity of the underlying graph is an important condition to making the? corresponding Ising-spin problem NP-complete
The Chimera graph is non-planar

okokok
Bunyk D-Wave Processor Control Circuitry
Hamiltonian for AQC
Chimera Architecture
Adiabatic Quantum Optimization Processor
quadratic unconstrained binary optimization (QUBO) problem
classical Ising Hamiltonian
adiabatic quantum optimization or quantum annealing
Desired Hamiltonian
Flux qubits Hamiltonian
D-Wave Qubit – Variant of rf SQUID flux qubit
Qubit is an individual spin, a dot, node in a graph.
Coupler is a line between dots.
Would prefer a complete graph,
but would take something into which complete graphs can be embedded.
Should at least be non-planar (makes Ising spin problems NP-hard).
E.g., K4,4 Bipartite graph
Unit cell of what we call Chimera topology (C1),
physical implementation of K4,4 Bipartite graph
demultiplexer tree

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

Cameron On the quantum chromatic number of a graph p7
Cameron On the quantum chromatic number of a graph p7
P. J. Cameron, A. Montanaro, M. W. Newman, S. Severini, and A. Winter. On the quantum chromatic number of a graph. Electr. J. Comb., 14(1), 2007.arXiv:quant-ph/0608016.

CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16
CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16

Chiara Qubit Semantics and Quantum Trees p11

Cosentino On some combinatorial properties of graph states p78

Dash Two-branch split cuts for MIPs
Chimera graph

okokok
Denchev Robust Classification with Non-Convex Loss and Regularization designed for Adiabatic Quantum Computation
Qubits connected via Chimera graph
Adiabatic quantum optimization (AQO)
D-Wave architecture
Ising model
Ji;j are coupling strengths between pairs of qubits
hi are biases of individual qubits.
sz are Pauli matrices
QUBO
Weighted MAX-2-SAT
D-Wave processor
Linear binary classifier
Hyper lattice
ancillary qubits

arXiv: quant-ph/0811.0416

okokok
Denil Toward the Implementation of a Quantum RBM p1
Restricted Boltzmann Machines
Ising model f
complete graph of binary variables
Chimera structured hidden connections, which reflect the architecture of the D-Wave machine.
Quantum Annealing
A Chimera(M; N; L) graph is formed by connecting an M N grid of L? L dense bipartite graphs.

Denil Toward the Implementation of a Quantum RBM p9
A line diagram of a Chimera(3,3,4) graph showing the connections between qubits.
The connectivity matrix for a Chimera(4,4,4) graph.

Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF

Dribus Quantum Circuit Graphs p29

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

Duplantier Liouville Quantum Gravity as a Mating of Trees, slides p122
Duplantier Liouville quantum gravity as a mating of trees p211.pdf

Devoret Implementing Qubits with Superconducting Integrated Circuits p41.pdf
Devoret Superconducting Circuits for Quantum Information: An Outlook
Devoret Superconducting Qubits A Short Review p41.pdf
Dimov The asynchronous rapid single-flux quantum electronics – a promising alternative for the development of high-performance digital circuits

Dumoulin On the Challenges of Physical Implementations of RBMs

Dwave Fabrication Technology and Process Overview p10.pdf

Feder Graphs in Quantum Information Theory p19

GAJ Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Godsil Colouring an Orthogonality Graph p13

Gutin Mediated Digraphs and Quantum Nonlocality p11.pdf

Hadamard Discovering Hadamard matrices
Hen Performance of D-Wave Two on Problems with Planted Solutions
Hen Quantum Computational Science
Hen Quantum vs Classical Annealing: Seeking a Fair Comparison

H. Hasegawa and S. Kasai, “Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires,” Physica E, vol. 11, no. 2-3, pp. 149–154, 2001.

HEIN Entanglement in Graph States and its Applications p99
HEIN Entanglement in Graph States and its Applications p99

Hen Quantum Computational Science p69.pdf
[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014

[Hen2014] Hen, Itay: Quantum Computational Science p69.pdf, OLCF users meeting July 24, 2014

Herrman Continuous Time Quantum Walks p1

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Horsman Quantum picturalism for topological cluster-state computing p14.pdf

[Iblisdir2014] Iblisdir, S. et al: Low depth quantum circuits for Ising models, Annals of Physics 340 (2014) 205–251.? p47

INTISO Design of superconductor digital circuits for a 30 GHz DSP and for interface to qubits p71

Jeffery Frameworks for Quantum Algorithms p166.pdf

S. Kasai and H. Hasegawa, “A single electron binary-decision diagram quantum logic circuit based on Schottky wrap gate control of a GaAs nanowire hexagon,” IEEE Electron Device Letters, vol. 23, no. 8, pp. 446–448, 2002.

Katzgraber Glassy Chimeras Could Be Blind to Quantum Speedup: Designing Better Benchmarks for Quantum Annealing Machines p8

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Katzgraber Glassy Chimeras Could Be Blind to Quantum Speedup: Designing Better Benchmarks for Quantum Annealing Machines1 p8
Glassy Chimeras
Quantum Annealing Machines
programmable quantum annealing machine
adiabatically quenching quantum fluctuations
decohering thermal bath
random-bond Ising models
spin glasses with bimodal and Gaussian disorder
D-Wave Chimera topology
ground state of an Ising spin glass
Chimera graph
spin glasses on Chimera
spin glasses on the Chimera graph
quantum speedup
Chimera topology
disorder-temperature phase diagram
random-bond Ising model on the Chimera graph
finite-temperature ferromagnetic phase
zero-temperature spin-glass phase
quantum random number generators
programmable quantum simulator
capabilities ex-
D-Wave One quantum annealer
quantum annealing optimization method
quantum fluctuations
solid-state quantum bits
spin glass
embedding on the Chimera topology problems
finite-temperature transition
random-bond Ising problems
couplers
biases
spin-glass Hamiltonian
with Si ∈ {±1} Ising spins on the nodes of the Chimera graph
Gaussian disorder distribution with zero mean and unit variance
bimodal distribution P(Jij) = p(Jij ? 1) + (1 ? p)(Jij + 1)
spin-glass order parameter q
spin-glass sector
susceptibility scales
replica exchange Monte Carlo [26] method
spin-glass overlap
Levenberg-Marquard minimization
Monte Carlo sweeps
Gaussian disorder
bimodal disorder
Chimera graph being nonplanar
quantum algorithm
spin glass on a Chimera graph

Ising ferromag-net on the Chimera graph
two-dimensional superspin Ising model
Sherrington-Kirkpatrick model [49–51]
Rescaled Chimera systems
embed a two-dimensional Ising spin glass on a square lattice
spin glasses defined on graphs
Chimera topology
Chimera spin glass
spin glass on the Chimera topology

Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11

Lidar Quantum annealing with hundreds of qubits
[Lidar2014] Lidar, Daniel: Quantum annealing with hundreds of qubits, Nature Phys. 10, 218 (2014), Nature Comm. 5, 3243 (2014), Science 345, 420 (2014)
[Lidar2014] Lidar, Daniel: Quantum annealing with hundreds of qubits, Nature Phys. 10, 218 (2014), Nature Comm. 5, 3243 (2014), Science 345, 420 (2014)

[Lidar2013] Lidar, Daniel: Theoretical and experimental error correction of programmable quantum annealing, New Directions in the Quantum Control Landscape, KITP, Santa Barbara, March 1, 2013

Lovett Application of quantum walks on graph structures to quantum computing p239

Lucas Adiabatic Quantum Computing p47.pdf

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Lucas Adiabatic Quantum Computing p47.pdf

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Lucas Adiabatic Quantum Computing with the D-Wave One
Adiabatic Quantum Optimization
Rainier chip
compound-compound Josephson junction (CCJJ) rf SQUIDs ? flux qubit
Graph Embedding implemented on DW-1 via Chimera graph retains NP-hardness V. Choi (2010)

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Lucas Dawn of the Era of Quantum Computation
Adiabatic Quantum Annealing
adiabatic interpolation from transverse field
Graph Embedding implemented on DW-1 via Chimera graph retains NP-hardness (V. Choi, 2010)
D-Wave = what it stands for???
D-Wave Chimera Graph Topology
503 of 512 qubits calibrated and mapped
Quantum Signature: Degenerate Ising Hamiltonian
Simulated Quantum Annealing
144 embeddings
Direct embedding of Ising Model to Chimeral Graph
Mapping problem
to chimeral graph for large N is NP-Hard, Each additional strong coupling reduces effect of weaker couplings
Greedy embedding algorithm used to sequentially map dense
Hamiltonian to D-Wave Chimeral topology

Lucas Graph Partitioning.pdf

Lucas Ising formulations of many NP problems

Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15

Martín-Mayor Quantum versus Thermal annealing, the role of Temperature Chaos
McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization

McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization

Nagaj Local Hamiltonian in quantum computation p176

Nobumori Design and implementation of a fully asynchronous SFQ microprocessor SCRAM2

PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31

Pius Automatic Parallelisation of Quantum Circuits Using the Measurement Based Quantum Computing Model p72

Pratheepa Design and Operation Of Parallel Carry-Save Pipelined Rsfq Multiplier For Digital Signal Processing

[Pudenz2014] Error-corrected quantum annealing with hundreds of qubits
http://www.nature.com/ncomms/2014/140206/ncomms4243/full/ncomms4243.html
Pudenz Error-corrected quantum annealing with hundreds of qubits

Pudenz Error corrected quantum annealing with hundreds of qubits
Pudenz Error-corrected quantum annealing with hundreds of qubits
Pudenz Quantum annealing correction for random Ising problems

Raussendorf Measurement-based quantum computation on cluster states p37

R?tteler A quantum circuit to find discrete logarithms on ordinary binary elliptic curves in depth O(log2 n) p13

R?nnow Defining and detecting quantum speedup

Saket A PTAS for the Classical Ising Spin Glass Problem on the Chimera Graph Structure

Santra Max 2-SAT with up to 108 qubits1
Santra Max 2-SAT with up to 108 qubits.pdf

Scarpa Kochen-Specker Sets and the Rank-1 Quantum Chromatic Number p12.pdf

Schwartz Introduction to Quantum Field Theory p262
Schwartz Introduction to Quantum Field Theory p262

Hadayat Seddiqi,
How does D-Wave system design their processor core?
Is there any HDL type language which can be used to develop quantum circuits? I'm a front end ASIC engineer without much knowledge about quantum computing or physics. Looking at D-wave's website, it seems like they are doing really exciting work!
Hadayat Seddiqi,
http://www.quora.com/How-does-D-Wave-system-design-their-processor-core

Severini Two-colorable graph states with maximal Schmidt measure p6

Smilansky Quantum chaos on discrete graphs p16

Tarrataca Tree Search and Quantum Computation p25

Teh New BSFQ Circuit Designs with Wide Margins

Tong Quantum Field Theory p155.pdf

Troyer Quantum annealing

@@@@@@@@@@@@@@@@@@

Tsai Quantum Boolean circuits and layout under locality constraint
Sunday, October 28, 2001—S3.1 Nanocircuits and Architectures, IEEE-NANO 2001
P3
digraph
quantum state transformation digraph
weighted graph

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

=======================
Not downloaded yet
Venturelli Quantum Optimization of Fully-Connected Spin Glasses

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Volkmann Implementation of Energy Efficient Single Flux Quantum (eSFQ) Digital Circuits with sub-aJ/bit Operation

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Wang Local techniques in quadratic optimization and satisfiability and their applications p116?????? August 22nd, 2014
connectivity graph
the problem can be mapped directly onto the hardware and is solvable by the system
mapping
The problem of finding the optimal mapping is also known as the minor embedding problem which is NP-hard in general.
Although it is NP-hard to optimally embed arbitrary graphs onto the Chimera graph, there is a polynomial time algorithm to embed a complete graph of n vertices onto a k-by-k Chimera graph with k = 4n [36].
the connectivity graph of the Ising problem must be mapped to the hardware graph
Finding good algorithms and heuristics for computing minor-embeddings in Gh is an interesting problem for future research.
random graph

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Yoshikawa Topdown RSFQ? logic design based on a binary decision diagram
Directed graph
binary tree

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Young Numerical Studies of the Quantum Adiabatic Algorithm
Chimera graph
regular random graph
3-Regular means that each spin is connected to exactly three neighbors.

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Zhang Design and Simulation of RSFQ/RISC Computer System
Progress In Electromagnetics Research Symposium 2005, Hangzhou, China, August 22-26

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Zintchenko From local to global ground states in Ising spin glasses
8 Aug 2014
P2
chimera graphs
planar graph
complete graph
complete bipartite graph
cluster chimera graphs

Lidar

Accurate and decoherence-protected adiabatic quantum computation
Daniel Lidar, USC

Adiabatic approximation with exponential accuracy for many-body systems and quantum computation.pdf
Lidar

Atom scattering from disordered surfaces in the sudden approximation: double collisions effects and quantum liquids
Daniel A. Lidar (Hamburger)

Calculating the thermal rate constant with exponential speedup on a quantum computer
Daniel A. Lidar* and Haobin Wang?

Concatenating Decoherence-Free Subspaces with Quantum Error Correcting Codes
D. A. Lidar,1 D. Bacon,1,2 and K. B. Whaley1

Conditions for strictly purity-decreasing quantum Markovian dynamics
D.A. Lidar a,*, A. Shabani b, R. Alicki c

Decoherence-Free Subspaces and Subsystems
Daniel A. Lidar1 and K. Birgitta Whaley2

Decoherence-free subspaces for multiple-qubit errors. I. Characterization
Daniel A. Lidar,1,* Dave Bacon,1,2 Julia Kempe,1,3,4 and K. B. Whaley1

Decoherence-free subspaces for multiple-qubit errors.II. Universal, fault-tolerant quantum computation
Daniel A. Lidar,1,* Dave Bacon,1,2 Julia Kempe,1,3,4 and K. B. Whaley1

Decoherence-free subspaces for multiple-qubit errors.II. Universal, fault-tolerant quantum computation
Daniel A. Lidar,1,* Dave Bacon,1,2 Julia Kempe,1,3,4 and K. B. Whaley1

Decoherence-Free Subspaces for Quantum Computation
D. A. Lidar,1 I. L. Chuang,2 and K. B. Whaley1

Distance bounds on quantum dynamics
Daniel A. Lidar

Distance bounds on quantum dynamics
Daniel A. Lidar

Elastic scattering by deterministic and random fractals: Self-affinity of the diffraction spectrum
Daniel A. Hamburger-Lidar*

Encoded recoupling and decoupling: An alternative to quantum error-correcting codes applied
to trapped-ion quantum computation
D. A. Lidar and L.-A. Wu

Exponentially localized magnetic fields for single-spin quantum logic gates
D. A. Lidar

Fractal analysis of protein potential energy landscapes
D. A. Lidar,1,2,* D. Thirumalai,3 R. Elber,2 and R. B. Gerber2,4

Hybrid quantum error prevention, reduction, and correction methods
Daniel Lidar

Inversion of randomly corrugated surface structure from atom scattering data
Daniel A Lidar

Limited range fractality of randomly adsorbed rods
Daniel A. Lidar (Hamburger)a)

On the quantum computational complexity of the Ising spin glass partition function and of knot invariants.pdf
Lidar

Optical theorem and the inversion of cross section data for atom scattering from defects on surfaces
D. A. Hamburger

Protecting quantum information encoded in decoherence-free states against exchange errors
Daniel A. Lidar,1 David Bacon,1,2 Julia Kempe,1,3 and K. Birgitta Whaley1

Quantum Codes for Simplifying Design and Suppressing? Decoherence in Superconducting Phase-Qubits
Daniel A. Lidar,1,3 Lian-Ao Wu,1 and Alexandre Blais
Quantum Codes for Simplifying Design and Suppressing Decoherence in Superconducting Phase-Qubits
Daniel A. Lidar,1,3 Lian-Ao Wu,1 and Alexandre Blais2

Quantum Computers and Decoherence: Exorcising the Demon from the Machine
Daniel A. Lidar and Lian-Ao Wu

RANDOMNESS AND APPARENT FRACTALITY
D.A. LIDAR (HAMBURGER)

Reducing Constraints on Quantum Computer Design by Encoded Selective Recoupling
D. A. Lidar and L.-A. Wu

Review of Decoherence Free Subspaces, Noiseless Subsystems, and Dynamical Decoupling
Daniel A. Lidar

ROBUST DYNAMICAL DECOUPLING: FEEDBACK-FREE ERROR CORRECTION*

Simulating Ising spin glasses on a quantum computer.pdf
Lidar

Lidargroup

Dreams versus Reality: Plenary Debate Session on Quantum Computing
Derek Abbott,1 Charles R. Doering,2 Carlton M. Caves,3 Daniel M. Lidar,4 Howard E. Brandt,5 Alex R. Hamilton,6 David K. Ferry,7 Julio Gea-Banacloche,8 Sergey M. Bezrukov,9 and Laszlo B. Kish10

Fluctuation theorems for quantum processes
Tameem Albash,1,2 Daniel A. Lidar,1,2,3,4 Milad Marvian,2,3 and Paolo Zanardi1,2

Albash Reexamining classical and quantum models for the D-Wave One processor.pdf

Albash Distinguishing Classical and Quantum Models for the D-Wave Device.pdf

Quantum adiabatic Markovian master equations
Tameem Albash1,2,6, Sergio Boixo2,3,4, Daniel A Lidar2,4,5 and Paolo Zanardi1,2

Internal consistency of fault-tolerant quantum error correction in light of rigorous derivations of the quantum Markovian limit
Robert Alicki,1 Daniel A. Lidar,2 and Paolo Zanardi3

Channel capacities of an exactly solvable spin-star system
Nigum Arshed,1 A. H. Toor,1 and Daniel A. Lidar2

Robustness of decoherence-free subspaces for quantum computation
D. Bacon,1,2 D. A. Lidar,2 and K. B. Whaley2

Robustness of multiqubit entanglement in the independent decoherence model
Somshubhro Bandyopadhyay1,* and Daniel A. Lidar1,2

Entangling capacities of noisy two-qubit Hamiltonians
Somshubhro Bandyopadhyay and Daniel A. Lidar

Analysis of generalized Grover quantum search algorithms using recursion equations
Eli Biham,1 Ofer Biham,2 David Biron,2,* Markus Grassl,3 Daniel A. Lidar,4,? and Daniel Shapira2

An implementation of the Deutsch–Jozsa algorithm on molecular vibronic coherences through four-wave mixing:a theoretical study
Zsolt Bihary a,David R. Glenn b,Daniel A. Lidar c,*,1,V. Ara Apkarian a

Generalized Grover Search Algorithm for Arbitrary Initial Amplitude Distribution
David Biron,1 Ofer Biham,1 Eli Biham,2 Markus Grassl,3 Daniel A. Lidar4

Experimental signature of programmable quantum annealing
Sergio Boixo1,2,3, Tameem Albash3,4, Federico M. Spedalieri1,3, Nicholas Chancellor4
& Daniel A. Lidar2,3,4,5

Boixo Evidence for quantum annealing with more than one hundred qubits.pdf

Quantum computing with quantum dots on quantum linear supports
K. R. Brown, D. A. Lidar,* and K. B. Whaley

Overview of quantum error prevention and leakage elimination
MARK S. BYRDy*, LIAN-AO WUz and DANIEL A. LIDARz

Empirical determination of dynamical decoupling operations
Mark S. Byrd*,? and Daniel A. Lidar

Combined error correction techniques for quantum computing architectures
MARK S. BYRD and DANIEL A. LIDAR

Universal leakage elimination
Mark S. Byrd,1 Daniel A. Lidar,2 Lian-Ao Wu,2 and Paolo Zanardi3

Bang–Bang Operations from a Geometric Perspective
Mark S. Byrd1 and Daniel A. Lidar1

Analysis of the quantum Zeno effect for quantum control and computation
Jason M Dominy1,4, Gerardo A Paz-Silva1,4, A T Rezakhani1,4,5 and D A Lidar1,2,3,4

A general framework for complete positivity
Jason M. Dominy(2;4), Alireza Shabani(5;6), and Daniel A. Lidar(1;2;3;4)

Evolution prediction from tomography
Jason M. Dominy(1;4), Lorenzo Campos Venuti(3;4), Alireza Shabani(5), and Daniel A. Lidar(1;2;3;4)

Control of decoherence: Analysis and comparison of three different strategies
P. Facchi,1 S. Tasaki,2 S. Pascazio,1 H. Nakazato,3 A. Tokuse,2 and D. A. Lidar4

Efficient Multiqubit Entanglement via a Spin Bus
Mark Friesen,1,* Asoka Biswas,2 Xuedong Hu,3 and Daniel Lidar2

Adiabatic Quantum Algorithm for Search Engine Ranking
Silvano Garnerone,1,2,5 Paolo Zanardi,2,5 and Daniel A. Lidar2,3,4,5

Classical Ising model test for quantum circuits
Joseph Geraci1,2,4 and Daniel A Lidar3,5

Quantum logic gates in iodine vapor using time–frequency resolved coherent anti-Stokes Raman scattering: a theoretical study
DAVID R. GLENN*yx, DANIEL A. LIDARy and V. ARA APKARIANz

Optimal Dynamical Decoherence Control of a Qubit
Goren Gordon and Gershon Kurizki

Encoding a qubit into multilevel subspaces
Matthew Grace1, Constantin Brif1, Herschel Rabitz1,6, Ian Walmsley2, Robert Kosut3 and Daniel Lidar4,5

Optimal control of quantum gates and suppression of decoherence in a system of interacting two-level particles
Matthew Grace1, Constantin Brif1, Herschel Rabitz1, Ian A Walmsley2, Robert L Kosut3 and Daniel A Lidar4

Fidelity of optimally controlled quantum gates with randomly coupled multiparticle environments
Matthew D. Grace a , Constantin Brif a , Herschel Rabitz a , Daniel A. Lidar b , Ian A. Walmsley c & Robert L. Kosut d

Adiabatic Preparation of Topological Order
Alioscia Hamma1 and Daniel A. Lidar1,2

Entanglement and area law with a fractal boundary in a topologically ordered phase
Alioscia Hamma,1 Daniel A. Lidar,2 and Simone Severini3

Theory of decoherence-free fault-tolerant universal quantum computation
J. Kempe,1,3,4 D. Bacon,1,2 D. A. Lidar,1,* and K. B. Whaley1

Arbitrarily Accurate Dynamical Control in Open Quantum Systems
Kaveh Khodjasteh,1 Daniel A. Lidar,2 and Lorenza Viola

Universal Fault-Tolerant Quantum Computation in the Presence of Spontaneous Emission and Collective Dephasing
K. Khodjasteh

Rigorous bounds on the performance of a hybrid dynamical-decoupling quantum-computing scheme
Kaveh Khodjasteh

Fault-Tolerant Quantum Dynamical Decoupling
K. Khodjasteh1 and D. A. Lidar2,3

Robust Quantum Error Correction via Convex Optimization
Robert L. Kosut,1 Alireza Shabani,2 and Daniel A. Lidar2,3

Quantum error correction via convex optimization
Robert L. Kosut · Daniel A. Lidar

Non-Markovian dynamics of a qubit coupled to an Ising spin bath
Hari Krovi,1 Ognyan Oreshkov,2 Mikhail Ryazanov,3 and Daniel A. Lidar1,2,3

Quadratic dynamical decoupling: Universality proof and error analysis
Wan-Jung Kuo*

Universality proof and analysis of generalized nested Uhrig dynamical decoupling
Wan-Jung Kuo, Gregory Quiroz, Gerardo Andres Paz-Silva, and Daniel A. Lidar

Coarse graining can beat the rotating-wave approximation in quantum Markovian master equations
Christian Majenz,1,2 Tameem Albash,2,3 Heinz-Peter Breuer,1 and Daniel A. Lidar2,4

How to Teleport Superpositions of Chiral Amplitudes
Christopher S. Maierle, Daniel A. Lidar, and Robert A. Harris

Scaling range and cutoffs in empirical fractals
Ofer Malcai,* Daniel A. Lidar,? and Ofer Biham?

Quantum error suppression with commuting Hamiltonians: Two-local is too local
Iman Marvian1, 2 and Daniel A. Lidar1, 2, 3, 4

Simple Proof of Equivalence between Adiabatic Quantum Computation and the Circuit Model
Ari Mizel,1 Daniel A. Lidar,2 and Morgan Mitchell3

Three- and Four-Body Interactions in Spin-Based Quantum Computers
Ari Mizel

Exchange interaction between three and four coupled quantum dots: Theory and applications to
quantum computing
Ari Mizel

Direct Characterization of Quantum Dynamics
M. Mohseni1,2 and D. A. Lidar2,3

Fault-Tolerant Quantum Computation via Exchange Interactions
Masoud Mohseni1 and Daniel A. Lidar2

Direct characterization of quantum dynamics: General theory
M. Mohseni1,2 and D. A. Lidar2,3

Combining dynamical decoupling with fault-tolerant quantum computation
Hui Khoon Ng,1,* Daniel A. Lidar,2 and John Preskill1

Magnetic Resonance Realization of Decoherence-Free Quantum Computation
Jason E. Ollerenshaw,1 Daniel A. Lidar,1 and Lewis E. Kay1,2,3,*

Operator quantum error correction for continuous dynamics
Ognyan Oreshkov,1,2,3 Daniel A. Lidar,2,3,4,5 and Todd A. Brun2,3,5,6

Scheme for fault-tolerant holonomic computation on stabilizer codes
Ognyan Oreshkov,1,2,3 Todd A. Brun,2,3,4 and Daniel A. Lidar2,3,4,5

Zeno Effect for Quantum Computation and Control
Gerardo A. Paz-Silva,1,4 A. T. Rezakhani,1,4,5 Jason M. Dominy,1,4 and D. A. Lidar1,2,3,4

Optimally combining dynamical decoupling and quantum error correction
Gerardo A. Paz-Silva1,4 & D. A. Lidar1,2,3,4

Optimally combining dynamical decoupling and quantum error correction
Gerardo A. Paz-Silva1,4 & D. A. Lidar1,2,3,4

High fidelity quantum memory via dynamical decoupling: theory and experiment
Xinhua Peng1,3, Dieter Suter1 and Daniel A Lidar21

Quantum adiabatic machine learning
Kristen L. Pudenz · Daniel A. Lidar

Pudenz Error-corrected quantum annealing with hundreds of qubits.pdf
Pudenz Error corrected quantum annealing with hundreds of qubits.pdf

Pudenz Quantum annealing correction for random Ising problems.pdf

High-fidelity adiabatic quantum computation via dynamical decoupling
Gregory Quiroz

Quadratic dynamical decoupling with nonuniform error suppression
Gregory Quiroz

Accuracy versus run time in an adiabatic quantum search
A. T. Rezakhani,1,2,3 A. K. Pimachev,1,2 and D. A. Lidar1,2,4,5

Intrinsic geometry of quantum adiabatic evolution and quantum phase transitions
A. T. Rezakhani,1,2 D. F. Abasto,2,3 D. A. Lidar,1,2,3,4 and P. Zanardi2,3

Quantum Adiabatic Brachistochrone
A. T. Rezakhani,1 W.-J. Kuo,1 A. Hamma,2 D. A. Lidar,1 and P. Zanardi1

Bang-bang control of a qubit coupled to a quantum critical spin bath
D. Rossini,1 P. Facchi,2,3 R. Fazio,1,4 G. Florio,3,5 D. A. Lidar,6 S. Pascazio,3,5 F. Plastina,7 and P. Zanardi8,9

Santra Max 2-SAT with up to 108 qubits.pdf

Abelian and non-Abelian geometric phases in adiabatic open quantum systems
M. S. Sarandy1 and D. A. Lidar2

Consistency of the Adiabatic Theorem
M.S. Sarandy,1,2 L.-A. Wu,1 and D.A. Lidar1

Adiabatic Quantum Computation in Open Systems
M. S. Sarandy1,2 and D. A. Lidar1,3

Adiabatic approximation in open quantum systems
M. S. Sarandy* and D. A. Lidar?

Theory of initialization-free decoherence-free subspaces and subsystems
Alireza Shabani1,* and Daniel A. Lidar2,?

Optimized entanglement-assisted quantum error correction
Soraya Taghavi,1 Todd A. Brun,1 and Daniel A. Lidar2

Channel-Optimized Quantum Error Correction
Soraya Taghavi, Robert L. Kosut, Life Fellow, IEEE, and Daniel A. Lidar, Senior Member, IEEE

Rigorous bounds for optimal dynamical decoupling
G¨otz S. Uhrig1,* and Daniel A. Lidar2,?

High Fidelity Quantum Gates via Dynamical Decoupling
Jacob R. West,1 Daniel A. Lidar,2 Bryan H. Fong,1 and Mark F. Gyure1

Near-Optimal Dynamical Decoupling of a Qubit
Jacob R. West,1 Bryan H. Fong,1 and Daniel A. Lidar2

Few-body spin couplings and their implications for universal quantum computation
RyanWoodworth1, Ari Mizel1,2 and Daniel A Lidar3,4

Quantum Malware
Lian-Ao Wu1 and Daniel Lidar1,2

Quantum Phase Transitions and Bipartite Entanglement
L.-A. Wu, M. S. Sarandy, and D. A. Lidar

Qubits as parafermions
L.-A. Wu and D. A. Lidara)

Universal quantum logic from Zeeman and anisotropic exchange interactions
Lian-Ao Wu and Daniel A. Lidar

Dressed Qubits
L.-A.Wu and D. A. Lidar

Holonomic Quantum Computation in Decoherence-Free Subspaces
L.-A. Wu,1 P. Zanardi,2 and D. A. Lidar1,3

One-Spin Quantum Logic Gates from Exchange Interactions and a Global Magnetic Field
Lian-AoWu and Daniel A. Lidar

Efficient Universal Leakage Elimination for Physical and Encoded Qubits
L.-A.Wu, M. S. Byrd, and D. A. Lidar

Polynomial-Time Simulation of Pairing Models on a Quantum Computer
L.-A. Wu, M. S. Byrd,* and D. A. Lidar

Universal quantum computation using exchange interactions and measurements of single- and two-spin observables
Lian-Ao Wu and Daniel A. Lidar

Entanglement observables and witnesses for interacting quantum spin systems
L.-A. Wu, S. Bandyopadhyay,* M. S. Sarandy, and D. A. Lidar?

No-go theorem for passive single-rail linear optical quantum computing
Lian-Ao Wu1, Philip Walther2 & Daniel A. Lidar3

Rigorous performance bounds for quadratic and nested dynamical decoupling
Yuhou Xia

Quantum Tensor Product Structures are Observable Induced
Paolo Zanardi,1,2 Daniel A. Lidar,3 and Seth Lloyd1

The important

Cabello Graph-Theoretic Approach to Quantum Correlations p6.pdf

Dribus Quantum Circuit Graphs p29.pdf

Feder Graphs in Quantum Information Theory p19.pdf

Qu Encoding Hypergraphs into Quantum States p16.pdf

Severini Graphs of unitary matrices p19.pdf


Untitled Document

Graph Theory for Quantum Circuits

Trees

graph_trees_quantum_chips computing

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf
Abhari ScaffCC A Framework for Compilation and Analysis of Quantum Computing Programs p10.pdf
Abramsky A categorical quantum logic p18.pdf
Aharonov The quantum FFT can be classically simulated p12.pdf
Aharonov The quantum FFT can be classically simulated2 p12.pdf
Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20.pdf
Ambainis New Developments in Quantum Algorithms p11.pdf
Ambainis Quantum walks and their algorithmic applications p11.pdf
Antonelli Quantum-Dot Cellular Automata (QCA) Circuit Partitioning Problem Modeling and Solutions p6.pdf
Arita Integration of Optical Waveguides With Single Flux Quantum Circuits p4.pdf
A?meur Quantum Clustering Algorithms p8.pdf
Barnum Quantum circuits for OR and AND of ORs p11.pdf
Barnum Quantum circuits for OR and AND of ORs p15.pdf
Batty An application of the Deutsch-Josza algorithm to formal languages and the word problem in groups p14.pdf
Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7.pdf
Ben-Aroya Quantum expanders and the quantum entropy difference problem p30.pdf
Bera On Finding Sensitivity of Quantum and Classical Gates p15.pdf
BERA QUANTUM CIRCUITS POWER AND LIMITATIONS p117.pdf
Bera Universal Quantum Circuits p12.pdf
Bera Universal Quantum Circuits p13.pdf
Bera Universal quantum circuits3 p12.pdf
Bergholm Categorical Quantum Circuits p23.pdf
Bernasconi Quantum Networks on Cubelike Graphs p11.pdf
Biamonte Algebra and Coalgebra on Categorical Tensor Network States p39.pdf
BigelowZZZ NIRT Next Generation Atom Chips for Quantum Information Technology p3.pdf
Bishop Circuit Quantum Electrodynamics p168.pdf
Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
Boixo Quantum annealing with more than one hundred qubits.pdf
Boixo Quantum annealing with more than one hundred qubits2.pdf
Boncalo Simulation-Based Assessment of Quantum Circuit Reliability p33.pdf
Boyden III Quantum Computation Theory and Implementation p181.pdf
Bozbey SFQ Analog and Digital Circuit Design Circuit Optimization and Timing Analysis.pdf
Brak Logics for Quantum Circuits p62.pdf
Brak Logics for Quantum Circuits1 p62.pdf
Braunstein Some families of density matrices for which separability is easily tested p14.pdf
Braunstein The laplacian of a graph as a density matrix a basic combinatorial approach to separability of mixed states p19.pdf
Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75.pdf
Buchleitner Quantum Accelerator Modes from the Farey Tree p4.pdf
Budhathoki Automatic synthesis of quantum circuits for point addition on ordinary binary elliptic curves p14.pdf
Bullock Quantum Circuits for d-level Systems p36.pdf
Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf
Bunyk D-Wave Processor Control Circuitry p48.pdf
Burgarth Zero forcing, linear and quantum controllability for systems evolving on networks p12.pdf
B?UTU QUANTUM CIRCUIT DESIGN BY MEANS OF GENETIC PROGRAMMING p8.pdf

B?UTU QUANTUM CIRCUIT DESIGN BY MEANS OF GENETIC PROGRAMMING p8.pdf
Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20.pdf
Cabello Graph-Theoretic Approach to Quantum Correlations p6.pdf
Caha Quantum 2-SAT in 1D geometry p70.pdf
Calude A Glimpse into Natural Computing.pdf
Cameron On the quantum chromatic number of a graph p7.pdf
Caravelli Properties of Quantum Graphity at Low Temperature p21.pdf
Casaccino Entanglement manipulation via dynamics in multiple quantum spin systems p7.pdf
Casaccino Quantum state transfer through a qubit network with energy shifts and fluctuations p6.pdf
Chailloux Graph-theoretical Bounds on the Entangled Value of Non-local Games p10.pdf
Chang 自動合成量子循序電路Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications p71.pdf
Chen陳羿安 量子排序 Quantum Permutations p28.pdf
CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16.pdf
Chiara Qubit Semantics and Quantum Trees p11.pdf
Childs Discrete-Query Quantum Algorithm for NAND Trees p5.pdf
Childs Exponential algorithmic speedup by quantum walk p6.pdf
Childs Universal computation by quantum walk p9.pdf
Chung QCA Physical Design With Crossing Minimization p4.pdf
Clark Bioreaction Quantum Computing without Quantum Diffusion.pdf
Cosentino On some combinatorial properties of graph states p78.pdf
Cosentino Weight of quadratic forms and graph states p7.pdf
Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz Number and its Variants p15.pdf
Cubitt Improving zero-error classical communication with entanglement p6.pdf
Dasgupta Algorithms p318.pdf

Dash A note on QUBO instances defined on Chimera graphs p8.pdf
Denil Toward the Implementation of a Quantum RBM p9.pdf

Devitt Quantum Information Engineering Concepts to Quantum Technologies p289.pdf
Devoret Implementing Qubits with Superconducting Integrated Circuits p41.pdf
Devoret Superconducting Circuits for Quantum Information An Outlook.pdf
Devoret Superconducting Qubits A Short Review p41.pdf
Dimov The asynchronous rapid single-flux quantum electronics – a promising alternative for the development of high-performance digital circuits.pdf
Dorojevets On the road towards superconductor computers twenty years later.pdf
Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4.PDF
Dribus Quantum Circuit Graphs p29.pdf
Duan On zero-error communication via quantum channels in the presence of noiseless feedback p7.pdf
Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30.pdf
Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19.pdf
Duplantier Liouville Quantum Gravity as a Mating of Trees p122.pdf
Duplantier Liouville quantum gravity as a mating of trees p211.pdf
Dwave Fabrication Technology and Process Overview p10.pdf
Eachempati Reconfigurable BDD based Quantum Circuits p7.pdf
Emms Coined quantum walks lift the cospectrality of graphs and trees p15.pdf
Enciso Introduction to Quantum Computing p11.pdf
Engseth Experimental Verification of Superconductor Digital Circuits p76.pdf
Feder Graphs in Quantum Information Theory p19.pdf
FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6.pdf

Fukuhara Lower bounds on quantum query complexity for read-once decision trees with parity nodes p10.pdf

GAJ Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.pdf
Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf
Geraci On the relation between quantum computation and classical statistical mechanics p138

Gildert Quantum Computing for Beginners Building Qubits p19.pdf
Godsil Colouring an Orthogonality Graph p13.pdf
Goodman A QUANTUM CIRCUIT SIMULATOR BASED ON DECISION DIAGRAMS p76.pdf
Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438.pdf
Gruska QUANTUM COMPUTING p390
Guhne Entanglement and nonclassical properties of hypergraph states p29.pdf
Gutin Hamilton Cycles in Digraphs of Unitary Matrices p10.pdf
Gutin Mediated Digraphs and Quantum Nonlocality p11.pdf
Hall Locality for quantum systems on graphs depends on the number field p9.pdf
Hamma A quantum Bose-Hubbard model with evolving graph as toy model for emergent spacetime p23.pdf
Hamma Background independent condensed matter models for quantum gravity p17.pdf
Hamma Lieb-Robinson bounds and the speed of light from topological order p4.pdf
Harrow Efficient Quantum Tensor Product Expanders and k-designs p16.pdf
Hasegawa Hexagonal Binary Decision Diagram Quantum Logic Circuits Using Schottky In-Plane and Wrap Gate Control of GaAs and InGaAs Nanowires.pdf
HEIN Entanglement in Graph States and its Applications p99.pdf
Hen Quantum Computational Science p69.pdf
Hen Quantum Computational Science p69
Herrman Continuous Time Quantum Walks p1.pdf
Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20.pdf
HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32.pdf
Horsman Quantum picturalism for topological cluster-state computing p14.pdf
Houches QUANTUM SUPERCONDUCTING CIRCUITS p32.pdf
Hoyer Quantum Circuits with Unbounded Fan-out p12.pdf
Hoyer Quantum Fan-out is Powerful p24.pdf
Hui Unconventional quantum gate based on Rydberg blockade mechanism p5.pdf
Iblisdir Low depth quantum circuits for Ising models p47.pdf
Ide Localization of Discrete Time QuantumWalks on the Glued Trees p14.pdf
INTISO Design of superconductor digital circuits for a 30 GHz DSP and for interface to qubits p71.pdf
Jackson Properties of minimum spanning trees and fractional quantum Hall states p220.pdf
JANEZ Automatic Design of Optimal Logic Circuits Based on Ternary Quantum-dot Cellular Automata p10.pdf
Jeffery Frameworks for Quantum Algorithms p166.pdf
Jeffery Frameworks for Quantum Algorithms p166
Johnson D-Wave real quantum computer.pdf
Jordan On the degeneracy of SU(3)k topological phases p6.pdf
Jozsa On the simulation of quantum circuits p12.pdf
Kauffman Quantum Topology and Quantum Computing p37.pdf
Kirkland State Transfer in Quantum Spin Networks and the Matrix Exponential p78.pdf

Klappenecker Wavelets and Wavelet Packets on Quantum Computers p11.pdf

Klavzar Tensor 2-sums and entanglement p5.pdf
Konopka Quantum Graphity a model of emergent locality p25.pdf
Kovalev Improved quantum hypergraph-product LDPC codes p5.pdf
Kruger Atom chips for quantum technologies p9.pdf
KUBO Hybrid Quantum Circuit with a Superconducting Qubit coupled to a Spin Ensemble p39.pdf
Kudrow Quantum Rotations A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11.pdf
Kuo 郭斯彥The Circuit Perspective of Digital Quantum Switching PPT slide, p29.ppt
Laplante Lower bounds using Kolmogorov complexity p21.pdf
LeGall OPEN PROBLEMS IN QUANTUM GRAVITY AT LES DIABLERETS p5.pdf
Leier Evolving Hogg’s Quantum Algorithm Using Linear-Tree GP p11.pdf
Li Efficient Synthesis of Optimal 3-qubit Reversible Circuits Using Bit Operation p7.pdf
Lidar2013 Theoretical and experimental error correction of programmable quantum annealing.pdf
Lidar2014 Quantum annealing with hundreds of qubits.pdf
Lin Reversible and Quantum Circuit Synthesis p209.pdf
Lirakis Quantum Computation With Superconducting Qubits a Journey from GeV to ueV.pdf
Lovasz Very large graphs p63.pdf
Lovett Application of quantum walks on graph structures to quantum computing p239.pdf
Lu Quantum decision tree classifier p14.pdf
Lucas Adiabatic Quantum Computing p47.pdf
Malkoc Quantum computation with superconducting qubits p15.pdf
Mancinska A Generalization of Kochen-Specker Sets Relates Quantum Coloring to Entanglement-Assisted Channel Capacity p15.pdf
Markov Simulating quantum computation by contracting tensor networks p21.pdf
Maslov Techniques for the Synthesis of Reversible Toffoli Networks p18.pdf
Mataloni Quantum information processing with photons Integrated quantum photonics.pdf
Matthias Perfect Transfer of Arbitrary States in Quantum Spin Networks p12.pdf
McGeoch Experimental Evaluation of an Adiabiatic Quantum System for Combinatorial Optimization.pdf
Michel INTRODUCTION TO QUANTUM SUPERCONDUCTING CIRCUITS PART 1 p77.pdf
Moghadaszadeh Quantum Circuit Automatic Synthesizer (QCAS) p5.pdf

Montanaro Almost all decision trees do not allow significant quantum speed-up p7.pdf

Mukherjee Synthesis of Quantum Circuits Using Genetic Algorithm p5.pdf
Nagaj Local Hamiltonian in quantum computation decrypt p176.pdf
Nagaj Local Hamiltonian in quantum computation p176.pdf
Nielsen Quantum Computation and Quantum Information p698.pdf
Nobumori Design and implementation of a fully asynchronous SFQ microprocessor SCRAM2.pdf
Oliveira Quantum Computation - Lecture 09 – Quantum Simulation p11.pdf
Orlando Chapter 21. Superconducting Circuits and Quantum Computation p10.pdf
Osborne Quantum Algorithms and Covering Spaces p7.pdf
Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf
PAULSEN ESTIMATING QUANTUM CHROMATIC NUMBERS p31.pdf
Pius Automatic Parallelisation of Quantum Circuits Using the Measurement Based Quantum Computing Model p72.pdf
Pratheepa Design and Operation Of Parallel Carry-Save Pipelined Rsfq Multiplier For Digital Signal Processing.pdf
Pudenz Error-corrected quantum annealing with hundreds of qubits.pdf
Pudenz Error-corrected quantum annealing with hundreds of qubits1.pdf
Pudenz Error-corrected quantum annealing with hundreds of qubits2.pdf
Qu Encoding Hypergraphs into Quantum States p16.pdf
Raussendorf Measurement-based quantum computation on cluster states p37.pdf
Reid On the Evolutionary Design of Quantum Circuits p93.pdf
Rieffel An Introduction to Quantum Computing for Non-Physicists p45.pdf
Rosenbaum Optimal Quantum Circuits for Nearest-Neighbor Architectures p14.pdf
Rossi Quantum Hypergraph States p14.pdf
Rotteler Introduction to Quantum Algorithms Part I Quantum Gates and Simons Algorithm p247.pdf
Ruican Developing Automatic Synthesis Methodologies for Quantum Circuits using Genetic Algorithms p31.pdf
Ruican Prerequisites of Synthesis Methodology for Quantum Circuits p37.pdf
R?tteler A quantum circuit to find discrete logarithms on ordinary binary elliptic curves in depth O(log2 n) p13.pdf
Santha Introduction to quantum computing p31.pdf
Scarpa Kochen-Specker Sets and the Rank-1 Quantum Chromatic Number p12.pdf
Schwartz Introduction to Quantum Field Theory p262.pdf
Scrucca Advanced Quantum Field Theory p137.pdf
Severini Graphs of unitary matrices p19.pdf
Severini Nondiscriminatory Propagation on Trees p5.pdf
SEVERINI THE UNDERLYING DIGRAPHS OF A COINED QUANTUM RANDOM WALK p11.pdf
Severini Two-colorable graph states with maximal Schmidt measure p6.pdf
Severini Universal quantum computation with unlabeled qubits p6.pdf
Shafaei Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures p6.pdf
Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures.pdf
Shahbazi Layout Optimization in Quantum Circuit using Simulated Annealing p7.pdf
Shende Synthesis of Quantum Logic Circuits p19.pdf
Shukla NANO QUANTUM AND MOLECULAR COMPUTING Implications to High Level Design and Validation p377.pdf
Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6.pdf
Smilansky Quantum chaos on discrete graphs p16.pdf
Smith QCA Channel Routing With Wire Crossing Minimization p4.pdf
Spalek Classical Simulation of Quantum Systems via Tensor Networks p30.pdf
STADELHOFER Evolving blackbox quantum algorithms using genetic programming p13.pdf
Steinwandt Low-depth quantum circuits for computing discrete logarithms on binary elliptic curves p13.pdf
Sterling Enabling Technologies for Peta FL OPS Computing p202.pdf
Svore A Layered Software Architecture for Quantum Computing Design Tools p10.pdf
Tarrataca Tree Search and Quantum Computation p25.pdf
Tarrataca Tree Search and Quantum Computation1 p25.pdf
Teh New BSFQ Circuit Designs with Wide Margins.pdf
Tong Quantum Field Theory p155

Tong Quantum Field Theory p155.pdf
Trung Constructing a software framework for synthesizing high accuracy quantum circuits p76.pdf
Tsai Quantum Boolean circuits and layout under locality constraint.pdf
Tsai Quantum Boolean circuits and layout under locality constraint.txt
Underwood Quantum Walk Schemes for Universal Quantum Computation p267.pdf
Verstraete_Simulating_Strongly_Correlated_Quantum_Systems.pdf
Vidal A class of entangling quantum circuits that can be efficiently simulated p55.pdf
Vinci Hearing the Shape of the Ising Model with a Programmable Superconducting-Flux Annealer p13.pdf
Volovich Models of Quantum Computers and Decoherence Problem p14.pdf
Voufo Quantum Circuits From a Network to a One-Way Model - A Tutorial Version p28.pdf
Wang Topological quantum error correction and quantum algorithm simulations p140 .pdf
Wang Characterization and properties of weakly optimal entanglement witnesses p7.pdf
Wang Universal methods for extending any entanglement witness from the bipartite to the multipartite case p7.pdf
Watrous An introduction to quantum information and quantum circuits p16.pdf
Westergaard Computational equivalence between quantum Turing machines and quantum circuit families p28.pdf
Wolf Quantum Computing p112.pdf
de Wolf, Ronald: Quantum Computing: Lecture Notes, Feb-May 2011
Wolf Quantum Computing p112???????????? 9
Wolf Quantum Computing Lecture Notes p112.pdf
Wolf Quantum ComputingZZZ p112.pdf
Wong An Algorithm For Quantum Circuit Optimization p58.pdf
Wu Randomized Graph States and their Entanglement Properties p17.pdf
Yamashita An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction p15.pdf
Yanushkevich Decision Diagram Techniques for Micro- and Nanoelectronic Design Handbook.pdf
Yumoto Graph-Based Quantum Logic Circuits and Their Realization by Novel GaAs Multiple Quantum Wire Branch Switches Utilizing Schottky Wrap Gates.pdf
Zhan Super-Polynomial Quantum Speed-ups for Boolean Evaluation Trees with Hidden Structure p1.pdf
Zhandry HOW TO CONSTRUCT QUANTUM RANDOM FUNCTIONS p41.pdf

Zhang Design and Simulation of RSFQRISC Computer System.pdf
Zhao WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure.pdf

?

Tree??

addition tree

R?tteler A quantum circuit to find discrete logarithms on ordinary binary elliptic curves in depth O(log2 n) p13

addition trees
Steinwandt Low-depth quantum circuits for computing discrete logarithms on binary elliptic curves p13.pdf

AND-OR tree

Ambainis New Developments in Quantum Algorithms p11.pdf

Barnum Quantum circuits for OR and AND of ORs p15
Barnum Quantum circuits for OR and AND of ORs p11.pdf
AND/OR tree

Ambainis New Developments in Quantum Algorithms p11
AND-OR tree
[de) Wolf2014] de Wolf, Ronald: Quantum Computing: Lecture Notes, April 2014.

binary AND/OR trees

Barnum Quantum circuits for OR and AND of ORs p8.pdf
Barnum Quantum circuits for OR and AND of ORs p15

full binary AND-OR tree

Lovett Application of quantum walks on graph structures to quantum computing p239

uniform binary AND/OR trees

Barnum Quantum circuits for OR and AND of ORs p8.pdf
Barnum Quantum circuits for OR and AND of ORs p15

Barnum Quantum circuits for OR and AND of ORs p15
Barnum Quantum circuits for OR and AND of ORs p11.pdf
uniform binary AND/OR trees

balanced tree

A?meur Quantum Clustering Algorithms p8????????????
balanced trees
Severini Nondiscriminatory Propagation on Trees p5

bias-feeding tree

Engseth Experimental Verification of Superconductor Digital Circuits p76.pdf

[Engseth2005] Engseth, Henrik: Experimental Verification of Superconductor Digital Circuits p76
9

binary tree ???!!!!!!!!!!!!!!!

binary tree
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

binary tree
Barnum Quantum circuits for OR and AND of ORs p8.pdf
Barnum Quantum circuits for OR and AND of ORs p15
Binary tree
Emms Coined quantum walks lift the cospectrality of graphs and trees p15
binary trees
HEIN Entanglement in Graph States and its Applications p99
binary tree
Hoyer Quantum Circuits with Unbounded Fan-out p12.pdf
binary tree
Hoyer Quantum Fan-out is Powerful p24
binary trees
Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
binary trees
Lovett Application of quantum walks on graph structures to quantum computing p239

binary tree
Rosenbaum Optimal Quantum Circuits for Nearest-Neighbor Architectures p14
binary trees
Severini Nondiscriminatory Propagation on Trees p5
binary tree
Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6
binary tree
Tarrataca Tree Search and Quantum Computation p25
Tarrataca Tree Search and Quantum Computation1 p25

binary trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

binary trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Barnum Quantum circuits for OR and AND of ORs p15
Barnum Quantum circuits for OR and AND of ORs p11.pdf
binary tree

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
binary trees

balanced binary tree

Severini Nondiscriminatory Propagation on Trees p5
balanced binary tree
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

full binary tree

Ambainis New Developments in Quantum Algorithms p11
full binary trees
Ambainis Quantum walks and their algorithmic applications p11

Ambainis New Developments in Quantum Algorithms p11.pdf
full binary tree

Ambainis New Developments in Quantum Algorithms p11.pdf

Ambainis Quantum walks and their algorithmic applications p11.pdf
full binary trees

Homogeneous binary trees

Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6

uniform binary tree

Barnum Quantum circuits for OR and AND of ORs p8.pdf
Barnum Quantum circuits for OR and AND of ORs p15
uniform binary-tree
Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6

binary trees / Wallace / Binary tree

Dorojevets On the road towards superconductor computers twenty years later

glued binary trees

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Cayley tree?? !!!!!!!!!!!!!!!

Cayley tree
Lovett Application of quantum walks on graph structures to quantum computing p239

Nagaj Local Hamiltonian in quantum computation p176

Cayley trees

Cayley trees

Vergnioux Paths in quantum Cayley trees and L2-cohomology p26

Cayley tree
Verstraete_Simulating_Strongly_Correlated_Quantum_Systems.pdf

infinite Cayley tree

Nagaj Local Hamiltonian in quantum computation p176

quantum Cayley trees

Vergnioux Paths in quantum Cayley trees and L2-cohomology p26

wired Cayley tree

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

clock distribution tree

Zhang Design and Simulation of RSFQ/RISC Computer System
Progress In Electromagnetics Research Symposium 2005, Hangzhou, China, August 22-26

CNOT trees

R?tteler A quantum circuit to find discrete logarithms on ordinary binary elliptic curves in depth O(log2 n) p13

complete tree

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf
complete tree
Li Efficient Synthesis of Optimal 3-qubit Reversible Circuits Using Bit Operation p7

Configuration trees

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

constant-depth trees

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

constant-depth trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

d-ary tree

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

decision tree?? !!!!!!!!!!!!!!!

Decision tree
Bera On Finding Sensitivity of Quantum and Classical Gates p15

decision tree
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

decision tree
Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

Decision trees
Laplante Lower bounds using Kolmogorov complexity p21

decision trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

algebraic decision trees

Bera On Finding Sensitivity of Quantum and Classical Gates p15

algebraic decision trees
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

binary decision tree

Goodman A QUANTUM CIRCUIT SIMULATOR BASED ON DECISION DIAGRAMS p76

complete binary decision tree

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf

complete binary decision tree

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf

deterministic decision trees

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

generalised decision trees

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

k-query decision tree

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

quantum decision trees

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

quantum decision tree
STADELHOFER Evolving blackbox quantum algorithms using genetic programming p13

randomized decision trees

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117
Randomized decision trees
Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

decorated tree

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

deformed tree

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

randomly deformed tree

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

demultiplexing tree

binary demultiplexing tree

Dwave Fabrication Technology and Process Overview p10
January 2009

Demux Tree / demultiplexer tree

Bunyk D-Wave Processor Control Circuitry p48.pdf

Derivation tree

Trung Constructing a software framework for synthesizing high accuracy quantum circuits p76

formula tree

Ambainis New Developments in Quantum Algorithms p11
Ambainis New Developments in Quantum Algorithms p11.pdf
formula tree

formula tree
Lovett Application of quantum walks on graph structures to quantum computing p239

fractal-tree network

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

binary fractal-tree structure

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

game tree

Ambainis New Developments in Quantum Algorithms p11

game trees

Sterling Enabling Technologies for Peta FL OPS Computing p202.pdf

glued tree

Ambainis New Developments in Quantum Algorithms p11

Glued trees
Ambainis Quantum walks and their algorithmic applications p11

glued-trees
Lovett Application of quantum walks on graph structures to quantum computing p239

Glued trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p167

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

glued trees
Ambainis New Developments in Quantum Algorithms p11.pdf

randomized glued trees

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

traversing glued trees

Underwood Quantum Walk Schemes for Universal Quantum Computation p167

H-tree

H-tree

Arita Integration of Optical Waveguides With Single Flux Quantum Circuits p4

H-tree

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4.pdf

H-tree

Shahbazi Layout Optimization in Quantum Circuit using Simulated Annealing p7

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4

Ouchi 8-QUBIT QUANTUM-CIRCUIT PROCESSOR p4

Tree qubit quantum circuit
binary fractal-tree structure
fractal-tree network
H-tree type fractal structure
H-tree

Quantum-Circuit Processor (QCP) is a parallel processor that executes quantum algorithms at a processing speed comparable to a quantum computer.

quantum superposition
fractal hardware-architecture

8-qubit QCP
Programmable logic device.
8-qubit-hardware quantum computing
factoring algorithm

infinite tree (Bethe lattice)

Nagaj Local Hamiltonian in quantum computation p176

invasion tree

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

Levy trees

Duplantier Liouville quantum gravity as a mating of trees p211

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

line tree

flow line tree

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

flow-line and dual-flow-line trees

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

linear-tree

Wong An Algorithm For Quantum Circuit Optimization p58

search tree

Wong An Algorithm For Quantum Circuit Optimization p58

Linear-Tree GP

Leier Evolving Hogg’s Quantum Algorithm Using Linear-Tree GP p11

m-ary tree

balanced m-ary tree

Severini Nondiscriminatory Propagation on Trees p5

metric tree

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
metric tree
HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

rooted metric tree

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

NAND tree

Zhao WPG-Controlled Quantum BDD Circuits with BDD Architecture on GaAs-Based Hexagonal Nanowire Network Structure
nand trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
NAND trees

NAND tree
Nagaj Local Hamiltonian in quantum computation p176

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11

nand trees
Underwood Quantum Walk Schemes for Universal Quantum Computation p167
NAND tree
Zhan Super-Polynomial Quantum Speed-ups for Boolean Evaluation Trees with Hidden Structure p1

parse tree

Trung Constructing a software framework for synthesizing high accuracy quantum circuits p76

perfect trees

Severini Two-colorable graph states with maximal Schmidt measure p6

Quantum Tree

Quantum trees
Quantum trees
Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20
CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16
Chiara Qubit Semantics and Quantum Trees p11

Random quantum trees

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

qubit trees

CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16

qumix trees

CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16

radix tree

Jeffery Frameworks for Quantum Algorithms p166.pdf

quantum radix tree

Jeffery Frameworks for Quantum Algorithms p166.pdf

recursion tree

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
recursion tree

random tree

Duplantier Liouville quantum gravity as a mating of trees p211

Continuum random trees (CRTs)

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

regular tree??

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

rooted tree

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

search tree?? !!!!!!!!!!!!!!!

JANEZ Automatic Design of Optimal Logic Circuits Based on Ternary Quantum-dot Cellular Automata p10
search tree

Shafaei Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures p6

search tree
Wong An Algorithm For Quantum Circuit Optimization p58

binary search tree

Lovett Application of quantum walks on graph structures to quantum computing p239
Lovett Application of quantum walks on graph structures to quantum computing p239

multidimensional binary search trees, known as kd-trees stands for “k-dimensional tree”

A?meur Quantum Clustering Algorithms p8????????????

N-ary search tree

Lin Reversible and Quantum Circuit Synthesis p209

space-fllling trees

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

spanning tree

[Bullock2004] Bullock, Stephen S.: Quantum Circuits for d-level Systems, Quantum Information Theory and Practice seminar, November 4, 2004 p36.pdf

spanning tree
Devoret Implementing Qubits with Superconducting Integrated Circuits p41
[Devoret2004] Devoret, Michel H. and Martinis, John M.: Implementing Qubits with Superconducting Integrated Circuits p41.pdf
Quantum Information Processing, Vol. 3, Nos. 1–5, October 2004.

spanning tree
Devoret Superconducting Qubits: A Short Review p41

spanning tree?? !!!!!!!!!!!!!!!

Spanning tree
Bishop Circuit Quantum Electrodynamics p168

spanning tree
Bullock Quantum Circuits for d-level Systems p36

spanning tree
Duplantier Liouville Quantum Gravity as a Mating of Trees p122

SPANNING TREE
Houches QUANTUM SUPERCONDUCTING CIRCUITS p32

Spanning trees
Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

minimum spanning tree

A?meur Quantum Clustering Algorithms p8????????????

minimum spanning trees
Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

random minimal spanning tree (MST)

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

uniform spanning tree

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

Steiner tree

Minimum Steiner tree

Lucas Adiabatic Quantum Computing p47.pdf

syntactical tree

CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16

syntactical tree
Chiara Qubit Semantics and Quantum Trees p11

syntax trees

[B?UTU 2007] QUANTUM CIRCUIT DESIGN BY MEANS OF GENETIC PROGRAMMING p8 the 7th International Balkan Workshop on Applied Physics, 5–7 July, 2006, Constanta, Romania. Rom. Journ. Phys., Vol. 52, Nos. 5–7, P. 697–704, Bucharest, 2007.

transition tree

Gruska QUANTUM COMPUTING p390.pdf
Gruska QUANTUM COMPUTING p438

traversal tree

Bera On Finding Sensitivity of Quantum and Classical Gates p15

traversal tree
BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

Welded Tree

Binary Welded Tree (BWT)

Herrman Continuous Time Quantum Walks p1

Binary Welded Tree

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11

Kudrow Quantum Rotations: A Case Study in Static and Dynamic Machine-Code Generation for Quantum Computers p11
Binary Welded Tree

Binary Welded Tree (BWT)

Abhari ScaffCC: A Framework for Compilation and Analysis of Quantum Computing Programs p10

XOR tree

uniform XOR tree

Barnum Quantum circuits for OR and AND of ORs p15
Barnum Quantum circuits for OR and AND of ORs p11.pdf

tree ?…

tree decompositions

Jozsa On the simulation of quantum circuits p12

tree-decompositions
Markov Simulating quantum computation by contracting tensor networks p21

tree decomposition
Oliveira Quantum Computation - Lecture 09 – Quantum Simulation p11

tree decomposition of a graph

Boixo Quantum annealing with more than one hundred qubits

tree encoding of polynomials

Reid On the Evolutionary Design of Quantum Circuits p93

tree search

quantum tree search

Tarrataca Tree Search and Quantum Computation p25
Tarrataca Tree Search and Quantum Computation1 p25

tree search?? !!!!!!!!!!!!!!!

Tree Search
Tarrataca Tree Search and Quantum Computation p25
Tarrataca Tree Search and Quantum Computation1 p25

Reed-Muller based tree search

Maslov Techniques for the Synthesis of Reversible Toffoli Networks p18

-tree states

homogeneous binary-tree states

Silvi Homogeneous binary trees as ground states of quantum critical Hamiltonians p6

tree tensor networks

Verstraete_Simulating_Strongly_Correlated_Quantum_Systems.pdf
tree tensor network
Vidal A class of entangling quantum circuits that can be efficiently simulated p55

tree traversal

Trung Constructing a software framework for synthesizing high accuracy quantum circuits p76

tree of

tree of circles

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

tree of disks

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

trees of loops

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

trees of quantum disks

Duplantier Liouville Quantum Gravity as a Mating of Trees, slides p122
September 30, 2014
continuum random tree (CRT)
random discrete trees
Levy tree
trees of quantum disks

Duplantier Liouville quantum gravity as a mating of trees p211.pdf
24 Sep 2014
random graph
discrete graph
adjacency graph
continuum random trees (CRTs)
Levy tree
discrete tree/dual-tree pair
quantum disk trees
spanning tree
geodesic tree
space-filling trees
flow-line and dual-flow-line trees
Gluing trees of disks
trees of quantum disks
tree of quantum spheres

tree of quantum spheres

Duplantier Liouville Quantum Gravity as a Mating of Trees, slides p122
September 30, 2014
continuum random tree (CRT)
random discrete trees
Levy tree
trees of quantum disks

Duplantier Liouville quantum gravity as a mating of trees p211.pdf
24 Sep 2014
random graph
discrete graph
adjacency graph
continuum random trees (CRTs)
Levy tree
discrete tree/dual-tree pair
quantum disk trees
spanning tree
geodesic tree
space-filling trees
flow-line and dual-flow-line trees
Gluing trees of disks
trees of quantum disks
tree of quantum spheres
continuum random trees (CRTs)
Levy tree
discrete tree/dual-tree pair
quantum disk trees
spanning tree
geodesic tree
space-filling trees
flow-line and dual-flow-line trees
Gluing trees of disks
trees of quantum disks
tree of quantum spheres

tree of spheres

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

Cospectrality of trees

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Mating of trees

Duplantier Liouville quantum gravity as a mating of trees p211
Mating of trees
Duplantier Liouville Quantum Gravity as a Mating of Trees p122


Untitled Document

Quantum Algorithms

Deutsch-Jozsa's algorithms
[de) Wolf2014]
[Rossi 2013]

Grover's. algorithms
[de) Wolf2014]
[Rossi 2013]

Simon’s Algorithm
[de) Wolf2014]

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Chapter 10 Quantum algorithms p20

Cieslak Why aren’t there more quantum algorithms p12
Quantum Programming Languages
By : Amanda Cieslak and Ahmana Tarin

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Cleve On quantum algorithms p15
Richard Cleve, Artur Ekert, Leah Henderson, Chiara Macchiavello and Michele Mosca

de Wolf Main Quantum Algorithms: Shor and Grover p23
Ronald de Wolf

Jordan Quantum Algorithms Lecture #2 p73
Stephen Jordan

Kerenidis Quantum Algorithms and Machine Learning p67
Iordanis Kerenidis

Kimmel Quantum Algorithms p52
Shelby Kimmel

Lipton QUANTUM ALGORITHMS VIA LINEAR ALGEBRA A Primer p204
Richard J. Lipton
Kenneth W. Regan

Montanaro A brief overview of some recent quantum algorithms p139
Ashley Montanaro

Roland Quantum algorithms I Basic tools and algorithms p28
Jérémie Roland

SHOR Why Haven’t More Quantum Algorithms Been Found? p4
PETER W. SHOR

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Strubell An Introduction to Quantum Algorithms p35
Emma Strubell

8

van Melkebeek Lecture 4: Elementary Quantum Algorithms p5
Instructor: Dieter van Melkebeek


Untitled Document

Quantum Chip

Quantum Chip

Quantum Chip Technologies

quantum computing chip

quantum relay chip

量子芯片

量子芯片技术

砷化镓量子芯片


Untitled Document

Quantum Circuits
quantum network

quantum circuits / quantum network / quantum gate array
[Chang2004]
quantum circuits are made of a sequence of unitary operations which are represented by quantum gates and quantum wires

[de) Wolf2014]
A quantum circuit (also called quantum network or quantum gate array) generalizes the idea of
classical circuit families, replacing the AND, OR, and NOT gates by elementary quantum gates.

quantum Boolean circuits [Chang2004]

sequential quantum Boolean circuits (SQBCs) [Chang2004]

Universal Quantum Circuits [Bera2008]
Fix n > 0 and let C be acollection of quantum circuits on n qubits. A quantum circuit U on n+m qubits
is universal for C if, for every circuit C 2 C, there is a string x 2 {0, 1}m (the encoding) such that for all strings y 2 {0, 1}n (the data),U(|yi? |xi) = C|yi? |xi.

Depth-Universal Quantum Circuits? [Bera2008]
Fix a family F of unitary quantum gates. A family of quantum circuits {Un,d}n,d>0 is depth-universal
over F if
1. Un,d is universal for n-qubit circuits with depth d using gates from F,
2. Un,d only uses gates drawn from F,
3. Un,d has depth O(d), and
4. the number of encoding qubits of Un,d is polynomial in n and d.

Composable Quantum Boolean Circuits

Categorical Quantum Circuits
[Bergholm2011]?

combinational quantum Boolean circuits? [Chang2004]

Quantum circuit

[Volovich1997]

a quantum circuit is a sequence of unitary matrices of the special form associated with a (hyper)graph.
A pair (L; ) where L is a set and is a family of its subsets is called a hypergraph. If one of the members of the family is marked then such a hypergraph is called a network or circuit. We will deal with the hypergraph (L; ), where L = f1; :::; lg and = fL1; :::; LT g is a family of subsets from L; Li L.

A quantum curcuit Sl is a 5-tuple
Sl = f(L; ); HL; U; U g
Here (L; ); HL and U are the described above hypergraph, Hilbert space and the basis of gates, and U is a unitary operator in HL of the form
U = LT (UT)::: L1(U1);
where Ui are unitary operators from the basis U. It is assumed that the hypergraph and the basis are consistent in the sence that Ui acts in Hr
(i) and jLij = r
(i); i = 1; :::; T.
Here
is a function from f1; :::; Tg to f1; :::; qg.

[ECHTERNACH2001]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

SCB-based quantum circuits

Single Cooper Pair Box (SCB)

[Han2013]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

simulating small-scale quantum circuits using traditional, linear optical devices

simulating small-scale quantum circuits only using traditional, linear optical devices including

  • beam splitters,
  • phase shifters and
  • polarization rotators

An optical symmetric beam splitter is known to act as a quantum square root of NOT gate or Hadamard gate since the output ports are indeed in a superposition state between 0 and 1 if we take one input port as the vacuum state 0 and the second one as a single-photon state 1.

Similarly, phase-shifters (quarter or half-waveplates) can be used as quantum phase-shifting gates acting on one mode of the photon.

Cerf and co. suggested that using nine beam splitters (seven symmetric beam splitters and two polarizing beam splitters), six quarter wave-plates, two polarization rotators and a number of mirrors/prisms, we could build a three-qubit quantum circuit which will allow us simulate quantum entanglement and teleportation.

Reference Quantum circuits

graph
Tree

Aaronson The_Limits_of_Quantum_Computers p8.pdf

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6
Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p6.pdf
3

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

Abhari ScaffCC: A Framework for Compilation and Analysis of Quantum Computing Programs p10

Abramsky A categorical quantum logic p18

[Aharonov1998] Quantum computation p77

26
quantum cellular automaton

finite state quantum automaton

quantum Turin machine

quantum circuits

Uniform quantum circuits

Non-uniform quantum circuits

Universal quantum gaes

Aharonov The quantum FFT can be classically simulated p12
Aharonov The quantum FFT can be classically simulated p12

A?meur Quantum Clustering Algorithms p8????????????

Aizenman Absolutely Continuous Spectra of Quantum Tree Graphs with Weak Disorder p20

Ambainis An Elementary Proof of the Quantum Adiabatic Theorem p12
[AR04] Andris Ambainis and Oded Regev. An elementary proof of the quantum adiabatic theorem. Technical report, 2004. Available at http://arxiv.org/PS_cache/quant-ph/pdf/0411/0411152v1.pdf.

Ambainis New Developments in Quantum Algorithms p11.pdf
Ambainis Quantum walks and their algorithmic applications p11.pdf

Amin Quantum Annealing With Superconducting Qubits

Antonelli Quantum-Dot Cellular Automata (QCA) Circuit Partitioning Problem Modeling and Solutions p6.pdf

Arita Integration of Optical Waveguides With Single Flux Quantum Circuits p4

okokok
Bakolo NEW? IMPLEMENTATION? OF? RSFQ? SUPERCONDUCTIVE DIGITAL GATES

[Barenco1995] Elementary gates for quantum computing p27

Barnum Quantum circuits for OR and AND of ORs p8.pdf
Barnum Quantum circuits for OR and AND of ORs p11

Barnum Quantum circuits for OR and AND of ORs p15

Batty An application of the Deutsch-Josza algorithm to formal languages and the word problem in groups p14.pdf

okokok
Bauch Superconducting qubits An artificial atom in a transmission line p17

[B?UTU 2007] QUANTUM CIRCUIT DESIGN BY MEANS OF GENETIC PROGRAMMING p8 the 7th International Balkan Workshop on Applied Physics, 5–7 July, 2006, Constanta, Romania. Rom. Journ. Phys., Vol. 52, Nos. 5–7, P. 697–704, Bucharest, 2007.

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

Belokurov PHYSICS OF QUANTUM COMPUTATION p10

Ben-Aroya Quantum expanders and the quantum entropy difference problem p30.pdf

Bera Efficient Universal Quantum Circuits p10
Debajyoti Bera1, Stephen Fenner2, Frederic Green3, and Steve Homer1
1 Boston University, Department of Computer Science, Boston, MA 02134. ?
2 University of South Carolina, Department of Computer Science and Engineering,
Columbia, SC 29208. ??
3 Clark University, Department of Mathematics and Computer Science, Worcester,
MA 01610. ? ? ?

Bera On Finding Sensitivity of Quantum and Classical Gates p15

BERA QUANTUM CIRCUITS: POWER AND LIMITATIONS p117

?[Bera2008] Universal Quantum Circuits p12
www.cse.sc.edu/~fenner/papers/univcirc.pdf
Bera Universal quantum circuits p12
Bera Universal Quantum Circuits1 p12
Bera Universal Quantum Circuits p13

BERGGREN Quantum Computing With Superconductors p9

[Bergholm2011]? Categorical Quantum Circuits p23 Journal of Physics A: Mathematical and Theoretical, Sep 28th, 2011
https://www.cs.ox.ac.uk/files/3724/cqc_poster.pdf

okokok
Bergholm From the control of quantum systems to multiqubit logic p59.pdf

Berkley A scalable readout system for a superconducting adiabatic quantum optimization system1 p16
[BJB+10] A. J. Berkley, M. W. Johnson, P. Bunyk, R. Harris, J. Johansson, T. Lanting, E. Ladizinsky, E. Tolkacheva, M. H. S. Amin, and G. Rose. A scalable readout system for a superconducting adiabatic quantum optimization system, March 2010.
Available at http://arxiv.org/abs/0905.0891.

hysteretic dc SQUID

rf SQUID

Bernasconi Quantum Networks on Cubelike Graphs p11

Bian The Ising model teaching an old problem new tricks p32
[Bian2010] The Ising model: teaching an old problem new tricks p32

The Ising model: teaching an old problem new tricks
Zhengbing Bian, Fabian Chudak,William G. Macready, Geordie Rose
D-Wave Systems
August 30, 2010

[HJB+10, JBM+10, BJB+10]

Biamonte Algebra and Coalgebra on Categorical Tensor Network States p39

BigelowZZZ NIRT Next Generation Atom Chips for Quantum Information Technology p3.pdf

Bishop Circuit Quantum Electrodynamics p168

Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
Bj?ork 20th Central European Workshop on Quantum Optics p205

okokok
Black Quantum Computing and Communication p52.pdf
Black, Paul E.: Quantum Computing and Communication, 2011???????????????? 15

Boncalo Simulation-Based Assessment of Quantum Circuit Reliability p33
Boncalo Simulation-Based Assessment of Quantum Circuit Reliability p33

Boyden III Quantum Computation: Theory and Implementation p181
Boyden III Quantum Computation Theory and Implementation p181

A. Bozbey (Invited), TOBB ETü
“SFQ Analog and Digital Circuit Design: Circuit Optimization and Timing Analysis”

Brak Logics for Quantum Circuits p62
Brak Logics for Quantum Circuits p62

Braunstein Some families of density matrices for which separability is easily tested p14.pdf

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Braunstein Quantum computation p13

Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75
[Breuckmann2013] From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75

8

Brush History of the Lenz-Ising model p13

[Bru67] Stephen G. Brush. History of the Lenz-Ising model. Reviews of Modern Physics, 39(4):883 – 893, 1967. Available at http://personal.rhul.ac.uk/UHAP/027/PH4211/PH4211_files/brush67.pdf.

okokok
Bub Introduction to Quantum Information p128

Budhathoki Automatic synthesis of quantum circuits for point addition on ordinary binary elliptic curves p14

Bullock Quantum Circuits for d-level Systems p36

Bunyk Architectural considerations in the design of a superconducting quantum annealing processor p9.pdf

Bunyk D-Wave Processor Control Circuitry p48.pdf

P. Bunyk, M. Leung, J. Spargo, and M. Dorojevets, “A FLUX-1 RSFQ micro-processor: Physical design and test results, A FLUX-1 microprocessor and beyond,”” IEEE Trans. Appl. Supercond., vol. 13, pp. 433-436, June 2003.

Paul, Bunyk, Mike Leung, John Spargo, Mikhail Dorojevets, “Flux-1 Rsfq Microprocessor: Physical Design and Test Results,” IEEE Transactions on Applied Superconductivity, Vol. 13, 433-436, 2003.

Bunyk, P., Kidiyarova-Shevchenko, A. Yu, P. Litskevitch, “Rsfq Microprocessor: New Design Approaches,”IEEE Transactions on Applied Superconductivity, Vol. 7, 2697-2704, June 1997.

Burrell High Fidelity Readout of Trapped Ion Qubits p218
Burrell High Fidelity Readout of Trapped Ion Qubits p218.pdf
Alice Heather Burrell
Trinity Term
2010
Exeter College
Oxford
p 47

Cabello Exclusive disjunction structures and graph representatives of local complementation orbits p20

Cabello Graph-Theoretic Approach to Quantum Correlations p6

Caha Quantum 2-SAT in 1D geometry p70

Calude A Glimpse into Natural Computing
5

Cameron On the quantum chromatic number of a graph p7.pdf

Caravelli Properties of Quantum Graphity at Low Temperature p21.pdf

[Chang2004] Chang, Li-Kai (張立楷):自動合成量子循序電路Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications, Master thesis, 大同大學Tatung University, Taiwan, Aug 2004.

Charemza An Introduction to Quantum Computing p61.pdf
Charemza, Michal: An Introduction to Quantum Computing, March 2005?????????????? 11

Chen Quantum Dot Computing Gates p69.pdf

Chen陳羿安 量子排序 Quantum Permutations p28 ?????????/

CHIARA COMPOSITIONAL AND HOLISTIC QUANTUM COMPUTATIONAL SEMANTICS p16

Chiara Qubit Semantics and Quantum Trees p11

Chow Quantum Information Processing with Superconducting Qubits p322.pdf

Chow Quantum Information Processing with Superconducting Qubits 2010 p322 ..........

Chung QCA Physical Design With Crossing Minimization p4.pdf

Clark Bioreaction Quantum Computing without Quantum Diffusion

CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319
Taylor and Francis
London, New York, 2000
120

DNA a Computing
p48
directed graph
Hamiltonian paths
p57
vertex-colourability problem
maximum clique in a graph
graph isomorphism
complementary graph

Membrane Computing

Cosentino On some combinatorial properties of graph states p78
Cosentino Weight of quadratic forms and graph states p7

A. Cottet, Implementation of a quantum bit in a superconducting circuit,PhD Thesis, Universite Paris 6, 2002

Cottet Implementation of a quantum bit in a superconducting circuit p259

Cottet Implementation of a quantum bit in a superconducting circuit p259.pdf

Cubitt Bounds on Entanglement Assisted Source-channel Coding via the Lovasz # Number and its Variants p15

Cubitt Improving zero-error classical communication with entanglement p6

Dasgupta Algorithms p318

DEUTSCH Quantum theory, the Church-Turing principle and the universal quantum computer p19
DAVID

Devitt Quantum Information Engineering: Concepts to Quantum Technologies p289

Devitt Quantum Information Engineering Concepts to Quantum Technologies p289

?[deWolf1999] Quantum computation and Shors factoring algorithm p9

Devoret Implementing Qubits with Superconducting Integrated Circuits p41.pdf
Devoret Superconducting Qubits A Short Review p41.pdf

[Devoret2004] Devoret, Michel H. and Martinis, John M.: Implementing Qubits with Superconducting Integrated Circuits p41.pdf
Quantum Information Processing, Vol. 3, Nos. 1–5, October 2004.

okokok
DiVincenzo Prospects for Superconducting Qubits p34

Dorojevets, M., “Cool Multithreading in Htmt SPELL-1 Processors,” International Journal of High Speed Electronics and Systems, Vol. 10, No. 1, 247-253, 2000.

M. Dorojevets, P. Bunyk, and D. Zinoviev, “FLUX chip: design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-m LTS technology,” IEEE Trans. Appl. Supercond., vol. 11, no. 1, pp. 326-332, Mar. 2001.

Dousti Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric p4

Dribus Quantum Circuit Graphs p29

Duan On zero-error communication via quantum channels in the presence of noiseless feedback p7

Duan Quantum Effects in Zero-Error Communication and Non-Commutative Graphs p30

Duan Zero-error communication via quantum channels non-commutative graphs and a quantum Lovasz function p19

Duce Quantum Logic Circuits for Solid-State Quantum Information Processing p175
Andrea Del

Duplantier Liouville quantum gravity as a mating of trees p211
Duplantier Liouville quantum gravity as a mating of trees p211

Duplantier Liouville Quantum Gravity as a Mating of Trees p122

Eachempati Reconfigurable BDD based Quantum Circuits p7

Edalat Quantum Computing p142.pdf

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Farhi Quantum Adiabatic Evolution Algorithms versus Simulated Annealing p16

[FGG02] Edward Farhi, Jeffrey Goldstone, and Sam Gutmann. Quantum adiabatic evolution algorithms versus simulated annealing. 2002. Available at http://arxiv.org/abs/quant-ph/0201031.

[Farhi2000] Quantum Computation by Adiabatic Evolution p20

[FGGS00] Edward Farhi, Jeffrey Goldstone, Sam Gutmann, and Michael Sipser. Quantum computation by adiabatic evolution. 2000. Available at http://arxiv.org/abs/quant-ph/0001106.

satisfiability problem

adiabatic evolution

Hamiltonian

Feder Graphs in Quantum Information Theory p19.pdf

FENG QUANTUM CHANNELS FROM ASSOCIATION SCHEMES p6

Feng Model checking quantum Markov chains p47

Franson Quantum Computing Using Single Photons and the Zeno Effect p34
J.D.

Freedman Topological Quantum Computation p12

FSK FWF Elementary Quantum Processor with trapped Ions p53 .pdf

Furia Quantum Informatics A Survey p58.pdf

Furusawa Quantum Teleportation and Entanglement p76 .pdf

FWF Elementary Quantum Processor with trapped Ions p53

Kris Gaj, Chin-Hong Cheah, “Functional Modeling of Rsfq Circuits Using Verilog HDL,” IEEE Transactions on Applied Superconductivity, Vol. 7, 3151-3154, 1997.

[Gay2006] Quantum Programming Languages Survey and Bibliography p20

Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf
Geraci On the relation between quantum computation and classical statistical mechanics p138

Gerster Adiabatic Quantum Computation An alternative approach to a quantum computer p27

okokok
Gildert Quantum Computing for Beginners Building Qubits p19

okokok
Girvin Superconducting Qubits and Circuits Artificial Atoms Coupled to Microwave Photons p132

Girvin Superconducting Qubits and Circuits Artificial Atoms Coupled to Microwave Photons p132.pdf

okokok
Gkourasas Quantum vs. DNA Computing p34

Godsil Colouring an Orthogonality Graph p13

Goodman A QUANTUM CIRCUIT SIMULATOR BASED ON DECISION DIAGRAMS p76

[Gramss1994] A Quantum Turing Machine with a Local Hamiltonian p19

Grover A fast quantum mechanical algorithm for database search p8
[Gro96] Lov K. Grover. A fast quantum mechanical algorithm for database search. In 28th Annual ACM Symposium on the Theory of Computing, page 212, 1996. Available at
http://arxiv.org/abs/quant-ph/9605043

Gruska QUANTUM COMPLEXITY THEORY p81

???????????????

Gruska QUANTUM COMPUTING p438
Gruska QUANTUM COMPUTING p390.pdf

110

quantum bits
quantum registers
quantum gates
quantum networks

Guhne Entanglement and nonclassical properties of hypergraph states p29.pdf

Gutin Hamilton Cycles in Digraphs of Unitary Matrices p10

Gutin Mediated Digraphs and Quantum Nonlocality p11

Hall Locality for quantum systems on graphs depends on the number field p9

Hamma A quantum Bose-Hubbard model with evolving graph as toy model for emergent spacetime p23.pdf
Hamma Background independent condensed matter models for quantum gravity p17.pdf

Harris Adiabatic Quantum Optimization Processor Performance p59
Richard

Harris Experimental Demonstration of a Robust and Scalable Flux Qubit p20
[HJB+10] R. Harris, J. Johansson, A. J. Berkley1, M. W. Johnson, T. Lanting, Siyuan Han, P. Bunyk, E. Ladizinsky, T. Oh, I. Perminov, E. Tolkacheva, S. Uchaikin, E. M. Chapple, C. Enderud, C. Rich, M. Thom, J.Wang, B.Wilson, , and G. Rose. Experimental demonstration of a robust and scalable flux qubit. Phys. Rev. B, 81:134510, 2010. Available at http://arxiv.org/abs/0909.4321.

Harrow Efficient Quantum Tensor Product Expanders and k-designs p16

Hasegawa Quantum Devices and Integrated Circuits Based on Quantum Confinement in III-V Nanowire Networks Controlled by Nano-Schottky Gates

Y. Hashimoto, S. Yorozu, Y. Kameda, and V. K. Semenov, “A design approach to passive interconnects for single flux quantum logic circuits,” IEEE Trans. Appl. Supercond., vol. 13, no. 2, pp. 535-538, Jun. 2003.

okokok
Hayakawa Superconducting Digital Electronics Based on Single Flux Quantum

HEIN Entanglement in Graph States and its Applications p99

Hen Quantum Computational Science p69.pdf

Herrman Continuous Time Quantum Walks p1

Hildebrand Combinatorial Laplacians and Positivity Under Partial Transpose p20

W. Hioe, M. Hosoya, S. Kominami, H. Yamada, R. Mita, and K. Takagi, “Design and operation of a Quantum Flux Parametron bit-slice ALU,” IEEE Trans. Appiled Supercond., vol. 5, no. 2, pp. 2992-2995, Jun. 1995.

HISLOP ANDERSON LOCALIZATION FOR RADIAL TREE-LIKE RANDOM QUANTUM GRAPHS p32

Horsman Quantum picturalism for topological cluster-state computing p14.pdf

Houches QUANTUM SUPERCONDUCTING CIRCUITS p32

Hoyer Quantum Circuits with Unbounded Fan-out p12.pdf

Hoyer Quantum Fan-out is Powerful p24

Hui Unconventional quantum gate based on Rydberg blockade mechanism p5.pdf??????????

Iblisdir Low depth quantum circuits for Ising models p47

okokok
IBM Reports Significant Progress in Superconducting Qubit

Ilievski ADIABATIC QUANTUM COMPUTATION p20

K. Inoue, N. Takeuchi, Y. Yamanashi, N. Yoshikawa, “Design and Test of Basic Cells for Adiabatic Quantum-Flux-Parametron Logic With Magnetic-Shielding Structures,” The 6th Superconducting SFQ VLSI Workshop (SSV 2013), Ibaraki, Japan, Nov. 2013

K. Inoue, N. Takeuchi, K. Ehara, Y. Yamanashi, N. Yoshikawa, “Cell-Base Design of a 1-bit Arithmetic Logic Unit Using Ultra-Low-Power Adiabatic Quantum- Flux-Parametron,” The 5th Superconducting SFQ VLSI Workshop (SSV 2012), Nagoya, Japan, Dec. 2012

M. Ito, N. Nakajima, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu, \Design and implementation of SFQ programmable clock generators," Physica C: Superconductivity and its Applications, vol. 412-414, no.SPEC ISS, pp. 1550 { 1554, 2004.

Iwama, K.; Kambayashi, Y.; Yamashita, S.; “Transformation Rules for Designing CNOT-based Quantum Circuits”, Design Automation Conference, 2002. Proceedings. 39th, 10-14 June 2002 Pages:419 – 424.

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

JANEZ Automatic Design of Optimal Logic Circuits Based on Ternary Quantum-dot Cellular Automata p10

Jarret Adiabatic optimization without local minima p20

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Jeffery Frameworks for Quantum Algorithms p166

?????????????????????

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Jordan How Powerful are Adiabatic Optimization Algorithms p13

Jozsa On the simulation of quantum circuits p12

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Kalai Why Quantum Computers Cannot Work p60 .pdf

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Katzgraber Quantum Computing p21

Kauffman Quantum Topology and Quantum Computing p31

Kauffman Quantum Topology and Quantum Computing p37

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Y. Kawaguchi, Kyoto Univ.
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T. Kawaguchi, Kyoto Univ.
“A Design Framework for SFQ Circuits using Clockless Gates”

Kirkland State Transfer in Quantum Spin Networks and the Matrix Exponential p78

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N. Kito, Chukyo Univ.
“Automatic Detailed Layout Method for SFQ Circuit Blocks”

Klavzar Tensor 2-sums and entanglement p5

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Okokok

M. Kozaka, Nagoya Univ.
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KUBO Hybrid Quantum Circuit with a Superconducting Qubit coupled to a Spin Ensemble p39

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MERMIN Quantum Computer Science An Introduction p237 ................ 59XXX

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8

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S. Sakamoto, Nagoya Univ.
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Y. Sakashita, Yokohama National Univ.
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Santha Introduction to quantum computing p31

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Shende Synthesis of Quantum Logic Circuits p19

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directed acyclic graph (DAG) p301
directed graph? p302
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graph traversal p337
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Shunmugavel RAPID SINGLE FLUX QUANTUM LOGIC IN HIGH TEMPERATURE
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SSV2013 6th Superconducting SFQ VLSI Workshop (SSV 2013) Technical Program.pdf

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SSV2014-YS Superconducting SFQ VLSI Workshop for Young Scientists (SSV2014-YS) Technical Program.pdf

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Svore A Layered Software Architecture for Quantum Computing Design Tools p10

K. Takagi, Kyoto Univ.
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A. Takahashi, Yokohama National Univ.
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K. Takatoku, Saitama Univ.
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N. Takeuchi, Y. Saito, Y. Yamanashi, and N. Yoshikawa, “Design and implementation of RSFQ microwave choppers for controlling Josephson junction qubits,” The 12th International Superconductive Electronics Conference (ISEC 2009), Fukuoka, Japan, June 2009

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M. Tanaka, Nagoya Univ.
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=================================

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Graph

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Untitled Document

quantum computation

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum computation

quantum computation is defined as a unitary evolution of the network which takes its initial state “input” into some final state “output”. We have chosen the network model of computation, rather than Turing
machines, because it is relatively simple and easy to work with and because it is much more relevant when it comes to physical implementation of quantum computation.

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

Ensemble quantum computation


Untitled Document

Quantum Computer

qumputer = quantum computer

量子计算

量子计算机

Quantum computer

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum computer

A quantum computer will be viewed here as a quantum network (or a family of quantum networks).

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

NMR ensemble quantum computers

D-Wave处理器

D-Wave Hardware

[Britt2014]
http://dwave.wordpress.com/2011/12/01/vesuvius-a-closer-look-512-qubit-processor-gallery/
http://www.dwavesys.com/sites/default/files/Map%20Coloring%20WP2.pdf

D-Wave Hardware

data teleportation = quantum data transfer

Quantum teleportation, though not the kind of "beam me up" transportation we imagine, is the moving of quantum data -- meaning classical bits are off the table for now -- from one location to another without having to travel the distance between them.

Quantum teleportation is not a form of transportation, but of communication; it provides a way of transporting a qubit from one location to another, without having to move a physical particle along with it.

https://en.wikipedia.org/wiki/Quantum_teleportation

?

Literature

G:\studies\000VLSIChip\NGIPC\_quantum_computer

Abdollahi Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams p7

Barnum Quantum circuits for OR and AND of ORs p11

Black Quantum Computing and Communication p52

Paul E. Black, D. Richard Kuhn, Carl J. Williams
National Institute of Standards and Technology
Gaithersburg, MD 20899
{paul.black, kuhn, carl.williams}@nist.gov

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Black Quantum Computing and Communication p52

Paul E. Black, D. Richard Kuhn, Carl J. Williams
National Institute of Standards and Technology
Gaithersburg, MD 20899
{paul.black, kuhn, carl.williams}@nist.gov

36

Quantum Mechanics

Quantum mechanics describes the interactions of electrons, photons, neutrons, etc. at atomic and subatomic scales.

Mesearuement of Qubits

In quantum systems it is not possible to measure qubit values without destroying the superposition that quantum computing needs

Universal Quantum Computer

power of quantum computing

the power of quantum computing derives in large part from the ability to take advantage of the unique properties of quantum mechanics— superposition and entanglement.

isolated quantum system

all transformations of an isolated quantum system are unitary

In particular, they are linear.

If a system undergoes decoherence or collapse because of some outside influence, the transformation is not necessarily unitary.

But when an entire system is considered in isolation from any other influence, all transformations are unitary.

No-Cloning Theorem

the “No-Cloning Theorem” proves we cannot make an exact copy of an unknown quantum state.

Not only could qubits not be exactly measured, they cannot even be arbitrarily copied by any conceivable scheme for detecting and correcting errors

Quantum Error Correction

One of the most serious problems for quantum information processing is that of decoherence, the tendency for quantum superpositions to collapse into a single, definite, classical state.

The qubits that comprise a quantum computer must inevitably interact with other components of the system, in order to perform a computation. This interaction inevitably will lead to errors. To prevent the state of qubits from degrading to the point that quantum computations fail requires that errors be either prevented or corrected.

Single Bit-flip Errors

Fault tolerant quantum computing

Quantum Teleportation

Burrell High Fidelity Readout of Trapped Ion Qubits p218

CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319

Charemza An Introduction to Quantum Computing p61

Michal Charemza
University of Warwick
March 2005

Chow Quantum Information Processing with Superconducting Qubits p322

Cottet Implementation of a quantum bit in a superconducting circuit p259

Devitt Quantum Information Engineering Concepts to Quantum Technologies p289

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Duce Quantum Logic Circuits for Solid-State Quantum Information Processing p175

2000

page 35

some quantum algorithms were discovered which are able to solve some specific problems more efficiently than classical computers

  • Deutsch-Jozsa algorithm
  • Shor?s factoring algorithm
  • Grover's quantum search algorithm

features

  • parallelism
  • interference
  • entanglement

presence of errors

  • decoherence
  • non-optimal control of the devices

measures

  • quantum error correction codes
  • fault-tolerant quantum computation schemes

physical systems for implementing a quantum computer

  • interactions of photons
  • cavity quantum electrodynamics
  • ion-traps
  • nuclear magnetic resonance
  • silicon NMR
  • Josephson junctions
  • donor spin qubits as in the Kane proposal
  • nitrogen-vacancy in diamond
  • spin of electrons trapped in quantum dots
  • qubits stored in the nuclear spin of phosphorus atoms

SFG model / SFG gates

Stoneham, Fisher and Greenland

quantum gates

  • controlled-not (C-NOT)
  • controlled-phase gate
  • entangling gates

quantum logic circuits

automated quantum circuit design process based on a genetic programming approach

quantum logic simulator

???????????????????????

okokok

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

Ekert Basic concepts in quantum computation p37
Artur Ekert, Patrick Hayden and Hitoshi Inamori
Centre for Quantum Computation,
University of Oxford, Oxford OX1 3PU, United Kingdom
February 1, 2008

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

qubit

A qubit is a quantum system in which the Boolean states 0 and 1 are represented by a prescribed pair of normalised and mutually orthogonal quantum states labeled as {|0>, |1>}. The two states form a ‘computational basis’ and any other (pure) state of the qubit can be written as a superposition α|0>+β|1> for some α and β such that |α|2 + |β|2 = 1. A qubit is typically a microscopic system, such as an atom, a nuclear spin, or a polarised photon. A collection of n qubits is called a quantum register of size n.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum register

A collection of n qubits is called a quantum register of size n.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum logic gate

A quantum logic gate is a device which performs a fixed unitary operation on selected qubits in a fixed period of time

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

Hadamard gate

The most common quantum gate is the Hadamard gate, a single qubit gate H performing the unitary transformation known as the Hadamard transform.
It is defined as

The matrix is written in the computational basis {| 0> , | 1>} and the diagram on the right provides a schematic representation of the gate H acting on a qubit in state | x>, with x = 0, 1.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

phase shift gate

We will need another single qubit gate – the phase shift gate φ defined as
| 0>→ | 0> and | 1>→ eiφ | 1>, or, in matrix notation,

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

controlled-NOT (CNOT) gate

controlled-NOT (c-not), also known as the xor or the measurement gate. It flips the second (target) qubit if the first (control) qubit is | 1> and does nothing if the control qubit is | 0>. The gate is represented by the unitary matrix

where x, y = 0 or 1 and ⊕ denotes XOR or addition modulo 2. If we apply the c-not to Boolean data in which the target qubit is |0> and the control is either |0> or |1> then the effect is to leave the control unchanged while the target becomes a copy of the control, i.e.
|x>|0> → |x>|x>, x = 0, 1.

One might suppose that this gate could also be used to copy superpositions such as | > = α |0> + β |1>, so that
| i|0> → | >|>i (20)
for any | i. This is not so! The unitarity of the c-not requires that the gate turns superpositions in the control qubit into entanglement of the control and the target. If the control qubit is in a superposition state | i = α|0i + β|1i, (α, β 6= 0), and the target in |0i then the c-not generates the entangled state
(α|0i + β|1i) |0i 7→ α|00i + β|11i. (21)
Let us notice in passing that it is impossible to construct a universal quantum cloning machine effecting the transformation in Eq.(20), or even the more general
| i|0i|Wi 7→ | i| i|W′i (22)
where |Wi refers to the state of the rest of the world and | i is any quantum state [3]. To see this take any two normalised states | i and |i which are nonidentical (|h| i| 6= 1) and non-orthogonal (h| i 6= 0 ), and run the cloning machine,
| i|0i|Wi 7→ | i| i|W′i (23)
|i|0i|Wi 7→ |i|i|W′′ i (24)

As this must be a unitary transformation which preserves the inner product hence we must require
h| i = h| i2hW′ |W′′ i (25)
and this can only be satisfied when |h| i| = 0 or 1, which contradicts our assumptions. Thus states of qubits, unlike states of classical bits, cannot be faithfully cloned. This leads to interesting applications, quantum cryptography being one such.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

controlled phase shift gate B(φ)

Another common two-qubit gate is the controlled phase shift gate B(φ) defined as

Again, the matrix is written in the computational basis {| 00i , | 01i , | 10i , | 11i} and the diagram on the right shows the structure of the gate.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

controlled-U gate

More generally, these various 2-qubit controlled gates are all of the form controlled-U, for some single-qubit unitary transformation U. The controlled-U gate applies the identity transformation to the auxiliary (lower) qubit when the control qubit is in state | 0i and applies an arbitrary prescribed U when the control qubit is in state | 1i. The gate maps | 0i | yi to | 0i | yi and | 1i | yi to
| 1i (U | yi), and is graphically represented as

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

universal gate

The Hadamard gate, all phase gates, and the c-not, form an infinite universal set of gates i.e. if the c-not gate as well as the Hadamard and all phase gates are available then any n-qubit unitary operation can be simulated exactly with O(4nn) such gates [4]. (Here and in the following we use the asymptotic notation – O(T (n)) means bounded above by c T (n) for some constant c > 0 for
sufficiently large n.) This is not the only universal set of gates. In fact, almost any gate which can entangle two qubits can be used as a universal gate [6, 8]. Mathematically, an elegant choice is a pair of the Hadamard and the controlled- V (c-V ) where V is described by the unitary matrix

The two gates form a finite universal set of gates – networks containing only a finite number of these gates can approximate any unitary transformation on two (and more) qubits. More precisely, if U is any two-qubit gate and ε > 0

then there exists a quantum network of size O(logd(1/ε)) (where d is a constant) consisting of only H and c-V gates which computes a unitary operation U′ that is within distance ε from U [49]. The metric is induced by the Euclidean norm - we say that U′ is within distance ε from U if there exists a unit complex number λ (phase factor) such that ||U ?λU′|| ≤ ε. Thus if U′ is substituted for U in a quantum network then the final state Px α′x |xi approximates the final
state of the original network Px αx |xi as follows: pPx |λα′x ? αx|2 ≤ ε. The probability of any specified measurement outcome on the final state is affected
by at most ε.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum network

a quantum network is a device consisting of quantum logic gates whose computational steps are synchronised in time. The outputs of some of the gates are connected by wires to the inputs of others. The size of the network is the number of gates it contains.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum computer

A quantum computer will be viewed here as a quantum network (or a family of quantum networks).

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[Ekert2008]

quantum computation

quantum computation is defined as a unitary evolution of the network which takes its initial state “input” into some final state “output”. We have chosen the network model of computation, rather than Turing
machines, because it is relatively simple and easy to work with and because it is much more relevant when it comes to physical implementation of quantum computation.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

Quantum arithmetic

and function evaluations

Gruska QUANTUM COMPUTING p390

?????????????????????????
Gruska QUANTUM COMPUTING p438
30

Hayes Quantum Logic Circuits p49

John P. Hayes

Jackson Properties of minimum spanning trees and fractional quantum Hall states p220

Lin Reversible and Quantum Circuit Synthesis p209

Lovett Application of quantum walks on graph structures to quantum computing p239

MERMIN Quantum Computer Science An Introduction p237

Miranowicz Methods of Quantum Information Processing p601

Muthukrishnan Classical and Quantum Logic Gates p22

Neumann Towards a room temperature solid state quantum processor — The nitrogen-vacancy center in diamond p205

[Nielsen2010]

Nielsen Quantum Computation and Quantum Information p698

31

[Nielsen2010]

Quantum computation and quantum information is the study of the information processing tasks that can be accomplished using quantum mechanical systems.

One of the goals of quantum computation and quantum information is to develop tools which sharpen our intuition about quantum mechanics, and make its predictions more transparent to human minds.

Nielsen Quantum Computation and Quantum Information p698

O'Donnell Introduction to the Quantum Circuit Model p17

Rodrigues Superconducting Charge Qubits p196

Rotteler Introduction to Quantum Algorithms Part I Quantum Gates and Simons Algorithm p247

Schwartz Introduction to Quantum Field Theory p262

Shende Synthesis of Quantum Logic Circuits p4

Shukla NANO QUANTUM AND MOLECULAR COMPUTING Implications to High Level Design and Validation p377

okokok

Oskin Quantum Computing - Lecture Notes p57

Quantum mechanics is a mathematical language, much like calculus.

Just as classical physics uses calculus to explain nature, quantum physics uses quantum mechanics to
explain nature.

Just as classical computers can be thought of in boolean algebra terms, quantum computers are reasoned about with quantum mechanics.

There are four postulates to quantum mechanics, which will form the basis of quantum computers:

Postulate 1: Definition of a quantum bit, or qubit.

Postulate 2: How qubit(s) transform (evolve).

Postulate 3: The effect of measurement.

This is the remarkable thing about entanglement. By measuring one qubit we can affect the probability
amplitudes of the other qubits in a system!

Postulate 4: How qubits combine together into systems of qubits.

Teleportation

Contrary to its sci-fi counterpart, quantum teleportation is rather mundane. Quantum teleportation
is a means to replace the state of one qubit with that of another. It gets its out-of-this-world name
from the fact that the state is “transmitted” by setting up an entangled state-space of three qubits
and then removing two qubits from the entanglement (via measurement). Since the information
of the source qubit is preserved by these measurements that “information” (i.e. state) ends up in
the final third, destination qubit. This occurs, however, without the source (first) and destination
(third) qubit ever directly interacting. The interaction occurs via entanglement

Super-dense Coding

Super dense coding is the less popular sibling of teleportation. It can actually be viewed as the
process in reverse. The idea is to send two classical bits of information by only sending one
quantum bit.

Bloch Sphere

The block sphere is a useful visualization tool for single quantum bits.

Universal Quantum Gates

[Shukla2004]

Quantum computing is a new and promising technology with the potential of exponentially powerful computation - if only a large-scale one can be built. The power of quantum computing comes from the
ability to store a complex state in a single bit.

[Shukla2004]

Shukla NANO QUANTUM AND MOLECULAR COMPUTING Implications to High Level Design and Validation p377

Strauch THEORY OF SUPERCONDUCTING PHASE QUBITS p371

Underwood Quantum Walk Schemes for Universal Quantum Computation p267

Wille From Reversible Logic to Quantum Circuits p7

?????????????????????????
Wolf Quantum Computing Lecture Notes p114
19

[Wolf2015]:

Quantum computation is the field that investigates the computational power and other properties
of computers based on quantum-mechanical principles.

An important objective is to find quantum algorithms that are significantly faster than any classical algorithm solving the same problem.

[Wolf2015]

Wolf Quantum Computing Lecture Notes p114

Ronald de Wolf
July 2015, Amsterdam


Untitled Document

quantum computing

Quantum computing

Quantum Computing Models

The gate model

Adiabatic model

Adiabatic Quantum Computation

the two models are equivalent

Quantum Cellular Automata

Models of Quantum Computation

Quantum computation is any model for computation that requires the ability to create, manipulate and measure quantum states.

https://dl.acm.org/citation.cfm?id=1571513

http://www.quantiki.org/wiki/Category:Models_of_Quantum_Computation

http://planetsave.com/2013/03/10/researchers-propose-new-quantum-computation-model-a-multi-particle-quantum-walk/

https://en.wikipedia.org/wiki/Quantum_computing

http://tph.tuwien.ac.at/~oemer/doc/quprog/node9.html

?

DEUTSCH Quantum theory, the Church-Turing principle and the universal quantum computer

Nielsen Quantum Computation p27

MISZCZAK Models of quantum computation and quantum programming languages p23

MISZCZAK Models of quantum computation and quantum programming languages p20

Kalai How Quantum Computers Fail p17

Duncan Types for Quantum Computing p175?

?

Gate/Circuit Model / quantum circuits

Uniform quantum circuits

Non-uniform quantum circuits

?

Bacon CSE 599d - Quantum Computing The Quantum Circuit Model and Universal Quantum Computation p8

Watrous An introduction to quantum information and quantum circuits p16

?

one-way quantum computing using cluster states

?

?

Quantum automata

quantum finite automata (QFA),
quantum sequential machines (QSM),
quantum pushdown automata (QPDA),
quantum Turing machines (QTM),
quantum cellular automata (QCA),

?

Adiabatic Model

https://www.quora.com/How-does-adiabatic-quantum-computation-work-in-laymans-terms

http://www.morganclaypool.com/doi/abs/10.2200/S00585ED1V01Y201407QMC008

?

Ilievski ADIABATIC QUANTUM COMPUTATION p17

?

?

Topological model

http://www.anyonsys.com/technology_TQC.html

Rowell TOPOLOGICAL QUANTUM COMPUTATION.pdf

Rowell Topological Quantum Computation p26

Fendley Topological Quantum Computation from non-abelian anyons p43

FREEDMAN TOPOLOGICAL QUANTUM COMPUTATION p8

Pachos Introduction to Topological Quantum Computation p41

?

Anyonic Quantum Computing

zhewang Anyonic Quantum Computing p32

?

xxx.lanl.gov/abs/quant-ph/quant-ph/0104023

xxx.lanl.gov/abs/quant-ph/0301052

xxx.lanl.gov/abs/quant-ph/0209084

xxx.lanl.gov/abs/quant-ph/0303048

xxx.lanl.gov/abs/quant-ph/0304074

xxx.lanl.gov/abs/quant-ph/0304085

xxx.lanl.gov/abs/quant-ph/0307176

xxx.lanl.gov/abs/quant-ph/0404132

?

Teleportation Model

?

Hamiltonian Q.C.

?

?

simulated anealing model

?

?

Cluster model of Q.C.

?

Novosad Lecture 2 Quantum Computation 2 Cluster model of QC.pdf

?

BLIND QUANTUM COMPUTATION

?

HERDER BLIND QUANTUM COMPUTATION p10

?

toy models of quantum computation

Pavlovic Relating toy models of quantum computation: comprehension, complementarity and dagger mix autonomous categories p10

?

Categorical Models for Quantum Computing

Wester Categorical Models for Quantum Computing p96

?

?

Quantum computation via entanglement and single- qubit measurements

quantum computation based upon measurement

Quantum computation via measurement alone

Michael A. Nielsen

http://xxx.lanl.gov/abs/quant-ph/0111122

?

?

Quantum computation as equation-solving

?

Ising Model

[Britt2014]
http://dwave.files.wordpress.com/2010/12/weightedmaxsat_v2.pdf

?

[ECHTERNACH2001]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

SCB-based quantum computing

Single Cooper Pair Box (SCB)

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

ensemble quantum computing via NMR


Untitled Document

Quantum Gates

(quantum logic gate)

Wikipedia:

In quantum computing and specifically the quantum circuit model of computation, a quantum gate (or quantum logic gate) is a basic quantum circuit operating on a small number of qubits. They are the building blocks of quantum circuits, like classical logic gates are for conventional digital circuits.

quantum gates
[Chang2004]

[de) Wolf2014]
A unitary that acts on a small number of qubits (say, at most 3) is often called a gate, in analogy o classical logic gates like AND, OR, and NOT;
A quantum gate is a unitary transformation on a small (usually 1, 2, or 3) number of qubits.
[Edalat2009]
A quantum gate is the quantum analogue of a classical gate. It takes a tuple of qubits and outputs another such tuple.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum logic gate

A quantum logic gate is a device which performs a fixed unitary operation on selected qubits in a fixed period of time

quantum logic gate
[Edalat2009]

A quantum logic gate is a device that carries out a given unitary operation on its input qubits in a fixed period of time.

quantum boolean gates [Kuo2002]

[Han2013]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

quantum-mechanical gate

quantum logic gates are reversible

All quantum logic gates must be reversible, which means if the outputs of an operation are put through the machine in the reverse direction, the original inputs have to be recovered,

Classical AND and OR gates do not obey this rule as we inevitably lose information when two input bits are reduced to a single output bit.

Therefore, we do not have AND gates or OR gates in quantum logic.

However, some classical gates such as NOT, CNOT gates do exist in quantum logic but their effects when
combined with a “genuine” quantum logic gate such as the Hadamard gate mentioned above become
quite remarkable and distinct from what we would expect from a classical setup.
Here below are some of the main quantum gates developed so far:

Toffoli gate

also CCNOT gate

also called the controlled-controlled-NOT gate

TOFFOLI is reversible and universal

TOFFOLI gate is universal for classical reversible computing

Hadamard gate

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

Hadamard gate

The most common quantum gate is the Hadamard gate, a single qubit gate H performing the unitary transformation known as the Hadamard transform.
It is defined as

The matrix is written in the computational basis {| 0> , | 1>} and the diagram on the right provides a schematic representation of the gate H acting on a qubit in state | x>, with x = 0, 1.

Walsh-Hadamaard gates

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

Walsh-Hadamaard gates

Walsh-Hadamaard transform, which in its one-qubit guise, takes the form

For example, UW-H maps the eigenstate |1? to 2-1/2 [|0? – |1?], and vice versa. The Walsh- Hadamaard transform is a quantum gate that has no classical analog. It takes each input eigenstate to more than one eigenstate, with different alternating phases (+1 or –1).

Pauli-X gate (= NOT gate)

quantum NOT gate [Chang2004]
The process of NOT gate takes state |0? to state |1?, and vice versa. In fact, the NOT gate acts linearly, that is, take this state, α|0? + β|1?, to the corresponding state, α|1? + β|0?, in which the role of |0? and |1? have been interchanged.

[de) Wolf2014]
It negates the second bit of its input if the first bit is 1, and does nothing if it’s 0:

Pauli-Y gate

Pauli-Z gate

Square root of NOT gate (√NOT)

Phase shift gates

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

phase shift gate

We will need another single qubit gate – the phase shift gate φ defined as
| 0>→ | 0> and | 1>→ eiφ | 1>, or, in matrix notation,

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

controlled phase shift gate B(φ)

Another common two-qubit gate is the controlled phase shift gate B(φ) defined as

Again, the matrix is written in the computational basis {| 00i , | 01i , | 10i , | 11i} and the diagram on the right shows the structure of the gate.

Swap gate

Square root of Swap gate

Controlled gates

controlled NOT gate (or CNOT)

quantum controlled-NOT (CNOT) type logic gates (n-bit Toffoli gates) [Chang2004]
CNOT type logic gates is denoted by [t, C], where t is an integer and C is a finite set of integers (t ? C). |xt? is called a target bit and |xk? is called a control bit if k ∈ C.

The effect of the “controlled”- NOT gate is to flip the bit value of the second bit if and only if the first bit is set to 1.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

controlled-NOT (CNOT) gate

controlled-NOT (c-not), also known as the xor or the measurement gate. It flips the second (target) qubit if the first (control) qubit is | 1> and does nothing if the control qubit is | 0>. The gate is represented by the unitary matrix

where x, y = 0 or 1 and ⊕ denotes XOR or addition modulo 2. If we apply the c-not to Boolean data in which the target qubit is |0> and the control is either |0> or |1> then the effect is to leave the control unchanged while the target becomes a copy of the control, i.e.
|x>|0> → |x>|x>, x = 0, 1.

One might suppose that this gate could also be used to copy superpositions such as | > = α |0> + β |1>, so that
| i|0> → | >|>i (20)
for any | i. This is not so! The unitarity of the c-not requires that the gate turns superpositions in the control qubit into entanglement of the control and the target. If the control qubit is in a superposition state | i = α|0i + β|1i, (α, β 6= 0), and the target in |0i then the c-not generates the entangled state
(α|0i + β|1i) |0i 7→ α|00i + β|11i. (21)
Let us notice in passing that it is impossible to construct a universal quantum cloning machine effecting the transformation in Eq.(20), or even the more general
| i|0i|Wi 7→ | i| i|W′i (22)
where |Wi refers to the state of the rest of the world and | i is any quantum state [3]. To see this take any two normalised states | i and |i which are nonidentical (|h| i| 6= 1) and non-orthogonal (h| i 6= 0 ), and run the cloning machine,
| i|0i|Wi 7→ | i| i|W′i (23)
|i|0i|Wi 7→ |i|i|W′′ i (24)

As this must be a unitary transformation which preserves the inner product hence we must require
h| i = h| i2hW′ |W′′ i (25)
and this can only be satisfied when |h| i| = 0 or 1, which contradicts our assumptions. Thus states of qubits, unlike states of classical bits, cannot be faithfully cloned. This leads to interesting applications, quantum cryptography being one such.

[Levinkron2010]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

CNOT gate

implementation of the CNOT gate in NMR Spectroscopy

In NMR Spectroscopy we use the internal spins of molecules as our qubits, and RF pulses interacting with the spins as our gates.

SFG model / SFG gates

Stoneham, Fisher and Greenland

Fredkin gate

also controlled-SWAP / CSWAP gate

FREDKIN is reversible and universal

FREDKIN gate is universal for classical reversible computing

Deutsch gate

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

Deutsch gate

The Deutsch gate operates on three qubits at a time,

As a function of the parameter α, Eq. (17) really describes a family of gates. However, due to the property that D(α) D(α′) = i D(α+α′), the parameter α can be fixed as an irrational multiple of π, isolating one gate that can generate the whole family of gates, D(α), asymptotically. Note that D(π/2) = T3, the three-bit Toffoli gate shown in table (9). The Deutsch gate is universal for
quantum logic in the sense that any unitary transform on an arbitrary number of qubits can be simulated by repeated applications of D(α) on three qubits at a time.As a function of the parameter α, Eq. (17) really describes a family of gates. However, due to the property that D(α) D(α′) = i D(α+α′), the parameter α can be fixed as an irrational multiple of π, isolating one gate that can generate the whole family of gates, D(α), asymptotically. Note that D(π/2) = T3, the three-bit Toffoli gate shown in table (9). The Deutsch gate is universal for quantum logic in the sense that any unitary transform on an arbitrary number of qubits can be simulated by repeated applications of D(α) on three qubits at a time.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

controlled-U gate

More generally, these various 2-qubit controlled gates are all of the form controlled-U, for some single-qubit unitary transformation U. The controlled-U gate applies the identity transformation to the auxiliary (lower) qubit when the control qubit is in state | 0i and applies an arbitrary prescribed U when the control qubit is in state | 1i. The gate maps | 0i | yi to | 0i | yi and | 1i | yi to
| 1i (U | yi), and is graphically represented as

Universal quantum gates

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

universal gate

The Hadamard gate, all phase gates, and the c-not, form an infinite universal set of gates i.e. if the c-not gate as well as the Hadamard and all phase gates are available then any n-qubit unitary operation can be simulated exactly with O(4nn) such gates [4]. (Here and in the following we use the asymptotic notation – O(T (n)) means bounded above by c T (n) for some constant c > 0 for
sufficiently large n.) This is not the only universal set of gates. In fact, almost any gate which can entangle two qubits can be used as a universal gate [6, 8]. Mathematically, an elegant choice is a pair of the Hadamard and the controlled- V (c-V ) where V is described by the unitary matrix

The two gates form a finite universal set of gates – networks containing only a finite number of these gates can approximate any unitary transformation on two (and more) qubits. More precisely, if U is any two-qubit gate and ε > 0

then there exists a quantum network of size O(logd(1/ε)) (where d is a constant) consisting of only H and c-V gates which computes a unitary operation U′ that is within distance ε from U [49]. The metric is induced by the Euclidean norm - we say that U′ is within distance ε from U if there exists a unit complex number λ (phase factor) such that ||U ?λU′|| ≤ ε. Thus if U′ is substituted for U in a quantum network then the final state Px α′x |xi approximates the final
state of the original network Px αx |xi as follows: pPx |λα′x ? αx|2 ≤ ε. The probability of any specified measurement outcome on the final state is affected
by at most ε.

zero-active controlled gates (denoted by open circles)? [Chang2004]

one-active controlled gates (denoted by closed circles)? [Chang2004]

[ECHTERNACH2001]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

SCB-based quantum gates

Single Cooper Pair Box (SCB)

[ECHTERNACH2001]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

square root of complex SWAP” (or “ iSWAP ” for short)

iSWAP and all 1-qubit gates is universal for quantum computation.

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

permutation gates

Literature

G:\studies\000VLSIChip\NGIPC\_quantum_gates

ABDOLLAHI REVERSIBLE LOGIC SYNTHESIS BY QUANTUM ROTATION GATES p22
AFSHIN ABDOLLAHI, MEHDI SAEEDIy, MASSOUD PEDRAM

Altani On the generation of sequential unitary gates from continuous time Schrodinger equations driven by external fields p12
Claudio Altani

Angelakis A proposal for the implementation of quantum gates with photonic-crystal waveguides p4
Dimitris G. Angelakis

Aruna A Study on Reversible Logic Gates of Quantum Computing p6
A.G.Aruna1, K H Vani2, C Sathya3, R.Sowndarya Meena4

[Barenco1995]

Barenco Elementary gates for quantum computation p31
Adriano Barenco
Physical Review A, March 22, 1995 (AC5710)

Beterov Quantum gates in mesoscopic atomic ensembles based on adiabatic passage and Rydberg blockade p5
I. I. Beterov

Bocharov From Reversible Logic Gates to Universal Quantum Bases p24
Alex Bocharov, Krysta M. Svore

BRUNE entanglement engineering with quantum gates p47
Michel BRUNE

Burkard Coupled quantum dots as quantum gates p9
Guido Burkard* and Daniel Loss

Chapter 4 REVERSIBLE LOGIC AND QUANTUM GATES p15

???????????????????????

???????????????????

Chapter 4 REVERSIBLE LOGIC AND QUANTUM GATES p15

9

quantum simulation

Chiesa Robustness of quantum gates with hybrid spin-photon qubits in superconducting resonators p9
A. Chiesa

Choi Ferritin-Templated Quantum-Dots for Quantum Logic Gates p20
Sang H. Choi

Cordourier-Maruri Graphene-enabled low-control quantum gates between static and mobile spins p8
G. Cordourier-Maruri

Cordourier-Maruri Implementing quantum gates through scattering between a static and a flying qubit p7
G. Cordourier-Maruri

Daboul Quantum gates on hybrid qudits p12
Jamil Daboul1,2, XiaoguangWang1 and Barry C Sanders1

Dam Self-Testing of Universal and Fault-Tolerant Sets of Quantum Gates p15

Wim van Dam Fr′ed′eric Magniezy Michele Moscaz Miklos Santhax

Daskaloyannis One qubit gates p16

???????????????????????

DiVincenzo quantum gates and circuits p17

Dong Learning robust pulses for generating universal quantum gates p9
Daoyi Dong

okokok

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ECHTERNACH UNIVERSAL QUANTUM GATES FOR SINGLE COOPER PAIR BOX BASED QUANTUM COMPUTING p8

ECHTERNACH UNIVERSAL QUANTUM GATES FOR SINGLE COOPER PAIR BOX BASED QUANTUM COMPUTING p8

P. ECHTERNACH1, C. P. WILLIAMS2, S.C. DULTZ1, S. BRAUNSTEIN3, AND
J. P. DOWLING2

Quantum Information and Computation, Vol. 1, Special (2001) 143-150
? Rinton Press

[ECHTERNACH2001]

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quantum electronics

[ECHTERNACH2001]

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SCB-based qubits

Single Cooper Pair Box (SCB)

A Single Cooper Pair Box is an artificial two-level quantum system comprising a nanoscale superconducting electrode connected to a reservoir of Cooper pair charges via a Josephson junction.

The logical states of the device, |0> and |1> , are implemented physically as a pair of charge-number states differing by 2e (where e is the charge of an electron).

Typically, some 109 Cooper pairs are involved.

Transitions between the logical states are accomplished by tunneling of Cooper pairs through the Josephson junction.

Although the two-level system contains a macroscopic number of charges, in the superconducting regime they behave collectively, as a Bose-Einstein condensate, allowing the two logical states to be superposed coherently. This property makes the SCB a candidate for the physical implementation of a qubit.

[ECHTERNACH2001]

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SCB-based quantum gates

Single Cooper Pair Box (SCB)

[ECHTERNACH2001]

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SCB-based quantum circuits

Single Cooper Pair Box (SCB)

[ECHTERNACH2001]

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SCB-based quantum computing

Single Cooper Pair Box (SCB)

[ECHTERNACH2001]

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square root of complex SWAP” (or “ iSWAP ” for short)

iSWAP and all 1-qubit gates is universal for quantum computation.

Eich Implementing Gates in Quantum Dot Spin Qubits p21
Marius Eich and Patrick Pietsch

Fernandez Encoding LogicalWords as Quantum Gates: The Higher Dimensional Case p48
Marco Fernandez

Florio Robust gates for holonomic quantum computation p11
Giuseppe Florio

Gajewski Analysis of Groups Generated by Quantum Gates p104
by
David C Gajewski

Gaulec Quantum Gates Based on Polarization p7
Transfer NMR Spectroscopy
A. Gaulec and S. Bahc?eli¤

Ghosh Quantum Information and Computing- Multiple Qubit States and Quantum Gates p10
Dipan Kumar Ghosh

Goerz Optimizing Robust Quantum Gates in Open Quantum Systems p238
Dipl.-Phys. Michael Goerz

Gómez-Mu?oz Gallery of Quantum Gates p30
by José Luis Gómez-Mu?oz

Gregoric Quantum Gates and Quantum Algorithms with Clifford Algebra Technique p9
M. Gregoric · N.S. Mankoˇc Bor?tnik

[Gregoric2007]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates]

Gregoric Quantum Gates and Quantum Algorithms with Clifford Algebra Technique p8

BLED WORKSHOPS
IN PHYSICS
VOL. 8, NO. 2
Proceedings to the 10th Workshop
What Comes Beyond ::: (p. 86)
Bled, Slovenia, July 17-27, 2007
M. Gregoric and N.S. Mankoˇc Borˇstnik
Department of Physics, University of Ljubljana, Jadranska 19, 1000 Ljubljana, Slovenia

Clifford Algebra

geometrical algebra

to demonstrate these gates and their functioning

Lorentz algebra

Cartan subalgebra

????????????????

Gulde Experimental realization of quantum gates p145

Haack Resonant quantum gates in circuit quantum electrodynamics p6
G. Haack,1 F. Helmer,2 M. Mariantoni,3 F. Marquardt,4 and E. Solano5,6

okokok

[Han2013]

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Han Optical Simulation of Quantum Logic gates p6

3

quantum factoring algorithm

quantum logic

[Han2013]

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quantum-mechanical gate

[Han2013]

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quantum logic gates are reversible

All quantum logic gates must be reversible, which means if the outputs of an operation are put through the machine in the reverse direction, the original inputs have to be recovered,

Classical AND and OR gates do not obey this rule as we inevitably lose information when two input bits are reduced to a single output bit.

Therefore, we do not have AND gates or OR gates in quantum logic.

However, some classical gates such as NOT, CNOT gates do exist in quantum logic but their effects when
combined with a “genuine” quantum logic gate such as the Hadamard gate mentioned above become
quite remarkable and distinct from what we would expect from a classical setup.

[Han2013]

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simulating small-scale quantum circuits using traditional, linear optical devices

simulating small-scale quantum circuits only using traditional, linear optical devices including

  • beam splitters,
  • phase shifters and
  • polarization rotators

An optical symmetric beam splitter is known to act as a quantum square root of NOT gate or Hadamard gate since the output ports are indeed in a superposition state between 0 and 1 if we take one input port as the vacuum state 0 and the second one as a single-photon state 1.

Similarly, phase-shifters (quarter or half-waveplates) can be used as quantum phase-shifting gates acting on one mode of the photon.

Cerf and co. suggested that using nine beam splitters (seven symmetric beam splitters and two polarizing beam splitters), six quarter wave-plates, two polarization rotators and a number of mirrors/prisms, we could build a three-qubit quantum circuit which will allow us simulate quantum entanglement and teleportation.

Hanson Universal Set of Quantum Gates for Double-Dot Spin Qubits with Fixed Interdot Coupling p4
Ronald Hanson and Guido Burkard2

Hanson Universal set of quantum gates for double-dot spin qubits with fixed interdot coupling p3
(Auxiliary material)
Ronald Hanson1 and Guido Burkard2

Harrow Robustness of quantum gates in the presence of noise p13
Aram W. Harrow1,2,* and Michael A. Nielsen2,?
1MIT Physics, 77 Massachusetts Avenue, Cambridge, Massachusetts 02139, USA
2School of Physical Sciences, University of Queensland, Queensland 4072, Australia
~Received 24 January 2003; published 11 July 2003!

Hayes Tutorial: Basic Concepts in Quantum Circuits p18
John P. Hayes

12

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Hines Quantum Walks, Quantum Gates, and Quantum Computers p17
Andrew P. Hines1, 2 and P.C.E. Stamp1

Huang Interaction- and measurement-free quantum Zeno gates for universal computation with single-atom and single-photon qubits p13
Y. P. Huang

Ikonen Optimal Quantum Driving for Single-Qubit Gates p64
Joni Ikonen

Ivanov Efficient construction of three- and four-qubit quantum gates by global entangling gates p8
Svetoslav S. Ivanov

Jaksch Fast Quantum Gates for Neutral Atoms p4
D. Jaksch, J. I. Cirac, and P. Zoller

Kauffman Braiding operators are universal quantum gates p40
Louis H Kauffman

Knight Ion trap quantum gates decoherence and error correction p19

Knill Randomized benchmarking of quantum gates p7
E. Knill,* D. Leibfried, R. Reichle,? J. Britton, R. B. Blakestad, J. D. Jost, C. Langer,? R. Ozeri,§
S. Seidelin, and D. J. Wineland

[Levinkron2010]

Levinkron The CNOT Quantum Gate p3
Submitted by: Ohad Levinkron

[Levinkron2010]

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CNOT gate

implementation of the CNOT gate in NMR Spectroscopy

In NMR Spectroscopy we use the internal spins of molecules as our qubits, and RF pulses interacting with the spins as our gates.

Mahmoud On the Formal Verification of Optical Quantum Gates in HOL p14
Mohamed Yousri Mahmoud1(), Prakash Panangaden2, and Sofi`ene Tahar1

Michoel Implementing quantum gates using the ferromagnetic spin-J XXZ chain with kink boundary conditions p16
Tom Michoel1, Jaideep Mulherkar2 and Bruno Nachtergaele2,3

Molotkov Single-electron computing: Quantum dot logic gates p9
S. N. Molotkov and S. S. Nazin

PHYSICAL REVIEW A 89, 032301 (2014)

[Malinovsky2014

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Malinovsky Phase-controlled two-qubit quantum gates p5
Vladimir S. Malinovsky
U.S. Army Research Laboratory, 2800 Powder Mill Road, Adelphi, Maryland 20783, USA
Ignacio R. Sola
Departamento de Quimica Fisica I, Universidad Complutense, 28040 Madrid, Spain
Jiri Vala
Department of Mathematical Physics, National University of Ireland, Maynooth, Ireland
(Received 20 January 2014; published 3 March 2014)

Muller Optimizing entangling quantum gates for physical systems p8
M. M. Muller

[Muthukrishnan1999]

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Muthukrishnan Classical and Quantum Logic Gates p22

Muthukrishnan Classical and Quantum Logic Gates p22

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates

Friday, Sep. 3, 1999
Ashok Muthukrishnan
Rochester Center for Quantum Information (RCQI)

Hilbert space

classical nat

the analog unit of memory used in classical continuous computation

Entanglement

[Muthukrishnan1999]

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quantum correlation

[Muthukrishnan1999]

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quantum nonlocality

quantum communication

quantum teleportation

[Muthukrishnan1999]

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quantum transformation

[Muthukrishnan1999]

G:\studies\000VLSIChip\NGIPC\0000quantum\quantum_computer\_quantum_gates[Muthukrishnan1999]

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quantum time evolution

Hamiltonian

unitary operation

[Muthukrishnan1999]

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unitary transformations

[Muthukrishnan1999]

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transpose (or hermitian adjoint) of the corresponding unitary matrix

[Muthukrishnan1999]

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Walsh-Hadamaard gates

Walsh-Hadamaard transform, which in its one-qubit guise, takes the form

For example, UW-H maps the eigenstate |1? to 2-1/2 [|0? – |1?], and vice versa. The Walsh- Hadamaard transform is a quantum gate that has no classical analog. It takes each input eigenstate to more than one eigenstate, with different alternating phases (+1 or –1).

[Muthukrishnan1999]

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Deutsch gate

The Deutsch gate operates on three qubits at a time,

As a function of the parameter α, Eq. (17) really describes a family of gates. However, due to the property that D(α) D(α′) = i D(α+α′), the parameter α can be fixed as an irrational multiple of π, isolating one gate that can generate the whole family of gates, D(α), asymptotically. Note that D(π/2) = T3, the three-bit Toffoli gate shown in table (9). The Deutsch gate is universal for
quantum logic in the sense that any unitary transform on an arbitrary number of qubits can be simulated by repeated applications of D(α) on three qubits at a time.As a function of the parameter α, Eq. (17) really describes a family of gates. However, due to the property that D(α) D(α′) = i D(α+α′), the parameter α can be fixed as an irrational multiple of π, isolating one gate that can generate the whole family of gates, D(α), asymptotically. Note that D(π/2) = T3, the three-bit Toffoli gate shown in table (9). The Deutsch gate is universal for quantum logic in the sense that any unitary transform on an arbitrary number of qubits can be simulated by repeated applications of D(α) on three qubits at a time.

Nader-Ali Implementation of Single-Qutrit Quantum Gates via Tripod Adiabatic Passage p10
R. Nader-Ali, A. Jafari Dolama, and M. Amniat-Talab

ORSZAG Logical gates and quantum processors with trapped ions and cavities p150

???????????????????????

[Parodi2007]

Parodi Environmental noise reduction for holonomic quantum gates p6
Daniele Parodi,1,2 Maura Sassetti,1,3 Paolo Solinas,4 and Nino Zanghì1,2
1Dipartimento di Fisica, Università di Genova, Genova, Italy
2Istituto Nazionale di Fisica Nucleare (Sezione di Genova), Genova, Italy
3INFM-CNR Lamia, Via Dodecaneso 33, 16146 Genova, Italy
4Laboratoire de Physique Théorique de la Matière Condensée, Université Pierre et Marie Curie, Place Jussieu,
75252 Paris Cedex 05, France
Received 3 April 2007; published 31 July 2007

stimulated raman adiabatic passage STIRAP

stimulated raman adiabatic passage STIRAP gates.

Abelian / non- Abelian holonomies

holonomic quantum computation HQC

holonomic quantum gates

holonomic gates

the disturbance of the environment on holonomic gates can be suppressed and the performance of the gate optimized for particular environments purely superohmic thermal bath.

geometrical structure of HQC

Pavicic Energy-Exchange-Free Quantum Gates p48
ITAMP, Harvard, March 30, 2010
Mladen Pavicic

Peralta Diabatic quantum gates p10
P.J. Salas Peralta

Planat On group theory, quantum gates and quantum coherence p30
Michel Planat (joint work with Philippe Jorrand)
Institut FEMTO-ST, 32 Avenue de l’Observatoire, F-25044 Besancon
(michel.planat@femto-st.fr)
Quantum Information and Graph Theory: emerging connections, Waterloo (PI), April 28- May 2 (2008)

Planat On group theory for quantum gates and quantum coherence
Michel Planat, Philippe Jorrand

Poornima Matrix Representation of Quantum Gates p6

International Journal of Computer Applications (0975 - 8887)
Volume 159 - No.8, February 2017

Aradhyamath Poornima
Physics Department
Vijayanagar Science College
Hosapete, Karnataka, India
Naghabhushana N. M.
Physics Department
RYM Engineering College
Ballari, Karnataka, India
Rohitha Ujjinimatad
Electronics and Communication Department
Proudhadevaraya Institute of Technology
Hosapete, Karnataka, India

Poyatos Quantum Gates with “Hot” Trapped Ions p4
J. F. Poyatos,1,2 J. I. Cirac,1,2 and P. Zoller2

Prevedel Experimental Realization of a Simple Entangling Optical Gate for Quantum Computation p111
Robert Prevedel

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

Price Construction and Implementation of NMR Quantum Logic Gates for Two Spin Systems p8

M. D. Pric

April 7, 1999

Journal of Magnetic Resonance 140, 371–378 (1999)

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

quantum parallelism

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

Ensemble quantum computation

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

NMR ensemble quantum computers

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

ensemble quantum computing via NMR

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

permutation gates

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

geometric algebra

The tools of geometric algebra (10) provide a useful means of constructing pulse sequences for quantum logic operations from the permutation matrix (note that the systematic derivation of a pulse sequence in this manner is analogous to the work of Briand and Sorensen found in Refs. (19) and (20)). The method is based on the use of primitive idempotents.

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

permutation group

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

symmetric group of degree n

Qader Simulation of Controlled Physical Quantum Gates by using Mathematica p7
Ibrahim N. Qader and Ramazan Ko?

Rahman Quantum Gates to Reduce the Quantum Cost of Reversible Circuit p10
Md. Mazder Rahman

Reda Lecture 18: Quantum gates, Deutsch algorithm/circuit p12
Prof. Sherief Reda

???????????????????????

Rigetti Quantum Gates for Superconducting Qubits p248
A Dissertation
Presented to the Faculty of the Graduate School
of
Yale University
in Candidacy for the Degree of
Doctor of Philosophy
by
Chad Tyler Rigetti
Dissertation Director: Professor Michel Devoret
May 2009

22

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Rotteler Introduction to Quantum Algorithms Part I: Quantum Gates and Simon’s Algorithm p247
Martin Rotteler

safronova Lectures 4 - 5 Quantum gates and Quantum circuits p12

Saha Local Implementations of Non-Local Quantum Gates in Linear Entangled Channel p7
Debashis Saha

Salman Quantum Set Intersection and its Application to Associative Memory p30
Tamer Salman

Schmassmann Universality of Quantum Gates p22
Markus Schmassmann

Schmidt-Kaler Realization of the Cirac–Zoller controlled-NOT quantum gate p4
Ferdinand Schmidt-Kaler,

Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures p6

SIMON Optimal quantum cloning and universal NOT without quantum gates p14
CHRISTOPH SIMON, GREGOR WEIHS and ANTON
ZEILINGER

Slepoy Quantum Gate Decomposition Algorithms p12
Alexander Slepoy

Strauch THEORY OF SUPERCONDUCTING PHASE QUBITS p371

Su High-speed quantum gates with cavity quantum electrodynamics p5
Chun-Hsu Su,1,* Andrew D. Greentree,1 William J. Munro,2,3 Kae Nemoto,3 and Lloyd C. L. Hollenberg1

Szumniak All-electrical control of quantum gates for single heavy-hole spin qubits p12
P. Szumniak

Timoney Quantum gates and memory using microwave-dressed states p5
N. Timoney

T?yr? Fidelity of geometric and holonomic quantum gates for spin systems p33
Daniel T?yr?

van der Sar Decoherence-protected quantum gates for a hybrid solid-state spin register p21
T. van der Sar

???????????????????????

[vazirani2013]

vazirani Chapter 3 Quantum Gates, Circuits & Teleportationp10

Unitary Operators

Hadamard Gate

Rotation Gate

This rotates the plane by θ

Phase Flip (Gate)

Verdenhalven Universal Quantum Gates p30
Eike Verdenhalven

White Measuring two-qubit gates p12
Andrew G. White and Alexei Gilchrist

Wikipedia Quantum gate p6

Williams Explorations in Quantum Computing Chapter 2 Quantum Gates p73

C.P. Williams, Explorations in Quantum Computing

22

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Williams Explorations in Quantum Computing Chapter 2 Quantum Gates p73

Yu Quantum Gates and Clifford Algebras p10

Alexander Yu. Vlasov
E-mail: Alexander.Vlasov@pobox.spbu.ru
12{23 July, 1999

Zhu Implementation of universal quantum gates based on nonadiabatic geometric phases p5
Shi-Liang Zhu1, Z. D. Wang1;2
1Department of Physics, University of Hong Kong, Pokfulam Road, Hong Kong, China.
2 Texas Center for Superconductivity, University of Houston, Houston, Tx 77204, USA.


Untitled Document

quantum general

Introduction

量子芯片技术

我原先以为量子芯片能一劳永逸地解决计算机的运算速度问题。理论上量子芯片似乎能无限提升芯片的计算速度，但许多研究者认为，量子芯片根本无法实现， 即使能实现，也只能解决一部份问题的计算能力问题，在许多其它问题上，计算速度反而比常规芯片速度慢，或至多持平。量子计算机的电路实现还是一个问题。
当然，量子理论还是很有用的，它是许多其它理论的基础。在微观领域离不开量子物理的帮助。

In this paper, we will observe the latest development of VLSI chip technology from the graph theoretical point of views and will be trying to find out what graph theory and techniques may contribute to the further development of that industry.

Atom chip

Benchmark Circuits

Problems with Quantum Computer/Computing/Chips

It is not yet clear whether large quantum computers suitable for practical use are possible
to build.

decoherence of quantum superpositions due to the interaction with the environment.
Decoherence can be defined as the decay of the off-diagonal matrix elements of the density operator
in the computational basis.

The problems of noise and decoherence have to some extent been solved in theory by the discovery of quantum error-correcting codes and fault-tolerant computing, but these problems are by no
means solved in practice. [de) Wolf2014]

In other words, quantum mechanics tells us how things work but cannot tell us why they work that way. [Edalat2009]


Untitled Document

quantum logic

quantum logic


Untitled Document

quantum network

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum network

a quantum network is a device consisting of quantum logic gates whose computational steps are synchronised in time. The outputs of some of the gates are connected by wires to the inputs of others. The size of the network is the number of gates it contains.

quantum network
[Edalat2009]

A quantum network is a device consisting of a number of quantum logic gates whose computational steps are synchronized in time.


Untitled Document

Quantum processor

Quantum processor


Untitled Document

Quantum Programming

(quantum computer programming)

微软发布量子开发套件预览版

作者 Sergio De Simone 译者 薛命灯 发布于 2017年12月15日.

据InfoQ之前报道，微软曾在Ignite大会上宣布开发量子计算机的计划，并提供一个开发套件。现在，微软发布了Quantum Development Kit（QDK）预览版。

QDK集成在Visual Studio中，使用Q#编程语言，并提供了一个量子模拟器，可以在笔记本上模拟最多30个逻辑量子位，这需要16GB的内存。如果要增加到40个逻辑量子位，内存需要呈指数级增长，比如增加10个逻辑量子位，就需要增加2的10次方那么多内存。微软为此提供了一个基于Azure的模拟器。开发者可以使用QDK来学习如何在量子计算机上编程，同时等待微软推出拓扑量子计算机。微软声称，在模拟器开发的程序最终可以不做任何修改就可以在真实的量子计算机上运行。

微软量子处理器使用了拓扑量子位，相关信息并不是保存在某个特定位置，而是进行全局保存，从拓扑结构的全局视图可以直接看出一个串是不是打结了。这种方式的好处在于量子信息的表示只需要少量的误差校正，而误差校正是限制量子处理器伸缩的主要因素。

在编程语言方面，微软将Q#定位成一门特定领域的编程语言，拥有原生的量子位类型系统、算子和其他抽象。它同时支持传统的语言控制流程和量子逻辑演算。

下面是Q#代码示例，目的是将一个量子位设置成给定的状态，如果它不在指定的状态，那么就翻转它：

namespace Quantum.Bell {

open Microsoft.Quantum.Primitive;

operation Set (desired: Result, q1: Qubit) : () {

body {

let current = M(q1);

if (desired != current) {

X(q1);

}

}

}

}

Visual Studio的调试器可以用来调试Q#程序，可以设置断点并逐步跟踪执行流程，还可以通过跟踪模拟器来评估运行一个量子程序需要的资源。

除了QDK，微软还发布了相关文档，涵盖了量子计算基础和高级概念，比如如何管理量子机器和驱动器，以及特定的开发技术。

现在就可以下载QDK，并在Visual Studio 2017里使用，VS 2017的社区版是免费的。

查看英文原文： Microsoft Quantum Development Kit Available to Developers

微软发布量子编程语言 5年内或推工作机

2017-12-12

微软、Alphabet旗下谷歌、IBM及一些小型专业化公司都在开发量子计算机，从理论上讲，量子计算机比现有计算机强大很多。微软最近表示，它已经找到一种不同的方法，可以让降低商用量子计算技术的出错率、让它更稳定。如果微软所说的技术真的管用，也许可以推动量子计算快速走向商业化。

本周一，微软推出一门新的程序语言，名叫“Q#”（念作Q Sharp），这是一个工具，可以帮助编程人员为量子计算机编写软件。微软还发布一些模拟器，让程序员在传统台式计算机上测试软件，或者通过Azure云计算服务测试。

微软CEO萨蒂亚·纳德拉（Satya Nadella）认为，与AI、VR一样，量子计算也是一门先进技术，这些技术对于微软的未来发展至关重要。和IBM、谷歌一样，微软极可能会通过互联网以服务的形式向客户出租量子机器计算时间。

2011年，D-Wave Systems率先开始销售量子计算机，不过D-Wave Systems技术一直存在争议，因为计算机只能解决特定数学问题。谷歌IBM的量子计算机更强大，更有可能帮助公司确立“量子霸权”地位，换言之，它们的技术可以解决复杂问题，这些复杂问题是标准超级计算机无法解决的。IBM和创业公司Rigetti Computing还为量子计算机开发了软件。

微软不同，它想开发一台工作机。微软的设计相当新颖，系统可以控制一种难以捉摸的粒子，这种粒子名叫Majorana（马约拉纳费米子），几年前人类甚至还不确定这种粒子是否存在。微软量子计算主管托德·霍姆达尔（Todd Holmdahl）在接受采访时表示，在工程师的努力下，微软已经接近达成控制粒子的目标，让粒子执行计算任务。Xbox、HoloLens项目也是由霍姆达尔负责的，他认为5年之内微软量子计算机就可以进入市场。他还说：“我们目前正在与多位客户谈判，我们认为可以用量子服务解决特定问题。”

人类也许可以用量子计算机开发药物、开发新材料，或者解决复杂的化学难题。微软量子计算软件负责人克里斯塔·斯诺弗（Krysta Svore）认为，量子计算还有一个“杀手级应用”，我们可以用它寻找更高效的合成氨技术，用于化肥生产，目前这一处理过程要消耗全球3%的天然气。

一直以来，科学家不断研究量子计算，研究过程很漫长，至今仍然没有走出研究阶段，量子技术真的实用吗？大家意见不一。研究人员目前只能在几分之一秒的时间内让量子位（qubits）保持量子态。一旦量子位脱离量子态，计算就会出错，这样一来使用量子计算机的好处就会被抹杀。

微软说它所使用的设计完全不同，微软管种设计叫作“拓扑量子计算机”，从理论上讲它可以创造更稳定的量子位。霍姆达尔认为，从出错的角度看，用微软新设计制造的量子计算机比其它公司制造的量子计算机好1000-10000倍。

伦敦帝国理工学院先进材料研究人员乔纳森?布雷兹(Jonathan Breeze)认为，如果想将量子技术变成商用技术，减少或者修正量子计算错误是关键。

微软设计可以降低出错率，放在实际应用中也许更实用，即使量子位少一些（可能不到100个）也会更实用。微软量子计算软件负责人克里斯塔·斯诺弗（Krysta Svore）说，她所率领的团队已经从算术角度证明，使用量子技术的算法可以大幅提高机器学习应用的速度，最高加快4000倍。

[Sofge2008]

Sofge A Survey of Quantum Programming Languages: History, Methods, and Tools p6
Donald A. Sofge, Member, IEEE

quantum information theory

quantum logic

Linear logic

Imperative Programming Languages

Functional Quantum Programming Languages


Untitled Document

Qubits

A qubit is a quantum system in which the Boolean states 0 and 1 are represented by a prescribed pair of normalised and mutually orthogonal quantum states labeled as {|0i, |1i} [1]. The two states form a ‘computational basis’ and any other (pure) state of the qubit can be written as a superposition α|0i+β|1i for some α and β such that |α|2 + |β|2 = 1. A qubit is typically a microscopic system, such as an atom, a nuclear spin, or a polarised photon. A collection of n qubits is called a quantum register of size n.

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

qubit

A qubit is a quantum system in which the Boolean states 0 and 1 are represented by a prescribed pair of normalised and mutually orthogonal quantum states labeled as {|0>, |1>}. The two states form a ‘computational basis’ and any other (pure) state of the qubit can be written as a superposition α|0>+β|1> for some α and β such that |α|2 + |β|2 = 1. A qubit is typically a microscopic system, such as an atom, a nuclear spin, or a polarised photon. A collection of n qubits is called a quantum register of size n.

preserved qubits? [Chang2004]
are defined to be the input qubits that have to stay unchanged after the operation,

quantum bits (Qubits)
[Chang2004]

[Edalat2009]
A qubit (quantum bit) is a quantum state of the form |ψ> = α|0> + β|1> where α and β are complex numbers with |α|2 + |β|2 = 1.

auxiliary qubits?? [Chang2004]

volatile qubits? [Chang2004]
are the input qubits that can be over-written by the output qubits.

[ECHTERNACH2001]

G:\studies\000VLSIChip\NGIPC\_quantum_gates

SCB-based qubits

Single Cooper Pair Box (SCB)

A Single Cooper Pair Box is an artificial two-level quantum system comprising a nanoscale superconducting electrode connected to a reservoir of Cooper pair charges via a Josephson junction.

The logical states of the device, |0> and |1> , are implemented physically as a pair of charge-number states differing by 2e (where e is the charge of an electron).

Typically, some 109 Cooper pairs are involved.

Transitions between the logical states are accomplished by tunneling of Cooper pairs through the Josephson junction.

Although the two-level system contains a macroscopic number of charges, in the superconducting regime they behave collectively, as a Bose-Einstein condensate, allowing the two logical states to be superposed coherently. This property makes the SCB a candidate for the physical implementation of a qubit.

Literature


Untitled Document

Quantum Registers

G:\studies\000VLSIChip\NGIPC\_quantum_computer

[Ekert2008]

quantum register

A collection of n qubits is called a quantum register of size n.

Quantum Registers
[Edalat2009]

Quantum register: [Rotteler2005]
A quantum register of length n is a collection of qubits q1, . . . , qn.


Untitled Document

Quantum Computer
Researchers

Researchers

英国布里斯托大学, ?东芝、诺基亚、Oclaro、苏格兰赫瑞瓦特大学及荷兰代尔夫特大学

量子芯片技术获突破 将极大提升电脑运算速度 2012-09-04

据国外媒体报道，一国际研究团队研发了一项新的量子芯片技术，该技术将能够使得手机变得非常安全，计算机的运算能力也将远远超过当前的水平。

取得该技术突破的是总部位于英国布里斯托大学的一个国际研究团队，本周该团队将在英国科技节上详细介绍该技术进展。

该研究是与东芝、诺基亚、Oclaro、苏格兰赫瑞瓦特大学及荷兰代尔夫特大学合作开展的，被认为是光学量子计算机迈向微型化的重要一步。

短期内，该团队将把该技术应用于手机和电脑的安全通讯，这将使得在线银行和网购变得更加安全，手机也将能够防止黑客攻击行为。

量子技术长久以来一直是科学界的梦想。上述由硅制成的量子芯片，大小比玻璃芯片要小数千倍。它将促进量子技术的量产，率先用于增强手机的安全性，最终则将用于超快的量子计算机。

用硅制成量子电路的一大好处是，与现代电子设备兼容。据布里斯托大学物理学教授杰里米·奥布莱恩（Jeremy O’Brien）称，未来三至五年量子处理器将可以整合到传统的微电子电路当中。

诺基亚剑桥研究中心的研究主管安蒂·尼斯卡内恩（Antti Niskanen）指出，“理解量子光学将打开进一步研究安全、感应器和信息处理之门，这让人感到兴奋。个人数据的安全、设备感应周遭环境的能力以及迅速解读信息的能力，均将给未来的设备用户带来极大的益处。”

与用于电脑和智能手机的微处理器一样，该新芯片也是由硅制成。与通过控制电流运行的传统硅芯片不同的是，量子芯片通过控制光子进行运算。理论上，拥有100个光子的量子计算设备每秒钟的运算能力可高达1万亿次。

由于该技术使用的硅制造工艺与传统芯片一样，生产商们将能够轻易地生产数百万个量子芯片。

量子芯片的电路将与当前用于宽带通信的光纤基础设施兼容，因为它们运行在相同的波长上。布里斯托大学量子光学中心副主任马克·汤普森（Mark Thompson）表示，“包括互联网在内的全球通信网络都是由光纤驱动的。我们采用量子芯片的设备将与之直接兼容——在某种意义上说它们说的是同一种语言。”

量子计算机能够较快解决超级计算机通常要耗费很长时间才能解决的任务。这些任务包括，金融风险分析、数据库搜索、新材料的设计等等。

奥布莱恩教授说道，“正如风洞不再用于飞机设计，为计算机模拟所替代那样，未来我们也许能够用量子计算机替代大多数的化学实验室。”(乐邦)

纽约城市大学（The City College of New York ，CCNY）和加州大学伯克利分校（UCB）

Jeffrey Reimer
物理教授卡洛斯·梅里雷斯（Carlos Meriles ）
UCB的博士研究生乔纳森·金（ Jonathan King）
CCNY的李云普（Yunpu Li）
The City College of New York
加州大学伯克利分校（UCB

用光束制造可擦写的电脑芯片的技术
砷化镓
电子的自旋
自旋电子电路
能够用一束光重写并且改变电路图形，能够制造不同的电路以适应不同的需求

用光束重写量子芯片：超高速计算临近 2012-07-06

用激光束制造的可擦写芯片使量子计算机朝实用化又迈进了一步。

量子计算机是我们长期寻求的一种高性能计算机，它的计算速度比现有计算机快很多倍。在一种用光束制造可擦写的电脑芯片的技术帮助下，超高速的量子计算向实用化又迈进了一步。来自纽约城市大学（The City College of New York ，CCNY）和加州大学伯克利分校（UCB）的研究人员通过光束来控制原子核的自旋，实现了信息的编码。这项技术可能为量子计算铺平道路。这个小组在今年6月26日发表的《自然通信》（Nature Communications）上公布了他们的实验结果。这项研究由美国国家科学基金会支持。

现有的电子元件在处理速度上正在接近它们的上限。人们通过在半导体上蚀刻图形来为这些电子元件生产芯片或者集成电路。这些相互连接的图形充当了在电路中传递信息的高速公路，但是传统的电路有一个缺陷。“一旦芯片被印刷出来，它的功能就固定了。”UCB的化学和生物工程博士杰弗里·雷蒙（Jeffrey Reimer）博士解释到，他也是这项研究的合作者。

这个团队包括CCNY的物理教授卡洛斯·梅里雷斯（Carlos Meriles ）和UCB的博士研究生乔纳森·金（ Jonathan King）以及CCNY的李云普（Yunpu Li）。他们见证了在自旋电子学和量子计算这两个新兴学科中针对传统电路这些问题而寻求到的补救措施。

他们开发了一项使用激光来让原子内部的“自旋”按模式对齐的技术，利用这项技术，他们可以飞速地改写“自旋”的对齐模式。可能在未来的某一天，从这项技术会产生可擦写的自旋电子电路。

数字电路和常规的计算程序依靠的是把电荷信息转化成只含0和1的二进制编码。而在另一方面，一个“自旋电子”计算机应用的是电子自旋的量子属性，这让电子能够存储0到1之间的任意数字。我们可以把电子想象成一个“阴阳”图，“阴阳”图的暗区和亮区的比例代表着0倒1的任意取值。这意味着我们将能够进行并行计算，它能够扩大我们的处理能力。

然而，由于电子的自旋状态转换得太快，人们在尝试利用电子进行量子计算的道路上从来都是障碍重重。因为，他们用一个极不稳定的载体来运载信息。为了抑制电子快速转换的随机性，UCB和CCNY的研究人员们用激光来产生长效的核自旋“磁体”，这个“磁体”可以用来推，拉或者稳定电子的自旋。

砷化镓是在我们手机芯片中使用的一种半导体。研究人员用一种特定模式的光照射一份砷化镓样本，这和我们把物理图形光刻到传统的集成电路上很像。被照射的样本使所有原子核的自旋对齐，从而它们的电子会立即形成一个自旋电子电路。

“你将拥有一个只用光束就可实现飞速擦除和重写的芯片。”梅里雷斯教授说到。改变光照模式就能迅速地改变电路的布局。

“如果你能够用一束光重写并且改变这个电路图形，你就能够制造不同的电路以适应不同的需求。”他补充道。“设想一下，还有什么系统能满足你各种各样的需求！”

D-Wave公司

D-Wave公司量子计算机芯片交由赛普拉斯公司生产 2013-10-25

[据美国电子周刊网站2013年10月22日报道] 加拿大D-Wave系统公司宣布将制造量子计算微处理器的工艺技术所有权转移至美国赛普拉斯（Cypress）半导体公司。量子计算公司D-Wave选择赛普拉斯公司作为其代工厂，并已于2013年1月转移至赛普拉斯公司进行生产，赛普拉斯公司已于6月26日生产出首块芯片。

D-Wave公司联合创始人兼首席科学家埃里克说：“D-Wave公司将生产移至赛普拉斯公司，将能持续使用先进工艺生产从根本上超越传统计算平台的量子处理器。首块硅片的结果超出我们的预期，证实赛普拉斯公司选择我们技术研发和处理器制造作为代工厂是正确的。”

加拿大D-Wave公司的主要产品--512量子比特D-Wave Ⅱ电脑，以全新超导处理器为基础，使用量子力学以显著增加运算能力。近日，D-Wave公司宣布D-Wave Ⅱ电脑已安装于美国国家航空航天局（NASA）、谷歌和高校空间研究协会（USRA）共同建立的新量子人工智能实验室中。随后，洛克希德·马丁公司也将其128量子比特D-Wave OneTM系统升级为512量子比特D-Wave Ⅱ电脑。（工业和信息化部电子科学技术情报研究所 张倩）

谷歌,加拿大量子计算技术公司D-Wave,航太总署NASA量子计算实用化技术现身Glass平台2013-10-11

?
今年五月，谷歌公司宣布与加拿大量子计算技术公司D-Wave和航太总署NASA联合筹建量子人工智能实验室。不过在消息公布之后的几个月里，此前宣布的野心勃勃的很多研究项目，包括深度探究量子计算架构和探索宇宙静态力之间关系的研究，似乎都以一种非常相当低调的姿态逐渐铺开而不为人所知。

这种静悄悄的学术研究气质直到昨天才被打破。谷歌公司在纽约举办的一场科幻电影年度盛会上公布了一部90秒钟的短视频，揭示了5个月当中量子人工智能实验室的收获。其中令人瞩目的研究方向包括在零度超临界状态下的高级计算超导体，这项研究在现有的电子计算机结构下提供了深度互联和超复杂的海量计算能力，其未来客户是航太总署发射到地球高轨道的深空探测望远镜。有该项技术的帮助，NASA未来的深空望远镜将不必使用核动力电池提供热量和电能就可以使成像组件和计算单元在超低温临界状态下满负荷运行。

虽然短片中展示出来的是各种平易近人的概念铺陈和高精尖的技术，但是实际上谷歌公司已经从量子实验室中获得了不错的回报，基于量子缠结算法研发的量子芯片将给予谷歌公司介于虚拟连接和实际物理连接之间的高级计算芯片。此前在该领域获得显著业绩的D-Wave公司为自己的技术成果找到了谷歌这样大体量的超级买家。

量子计算芯片的测试片据称已经被试装在谷歌眼镜上，这部被谷歌公司寄予厚望的智能佩戴技术产品将借助量子芯片获得惊人的处理能力。在进行相对复杂的“眨眼分析”功能运算时，分析自然的眨眼和有意的“眨巴眼”对目前的谷歌眼镜ARM系统架构几乎是不可能完成的任务，但是借助量子芯片高效低功耗的过人能力，谷歌眼镜将有可能实现微体量大能量的设计期望。

虽然由于工程设计的原因，量子芯片目前不能完美地被嵌入谷歌眼镜，但是经由正在研发的超临界数据链路，量子芯片提供的强大计算能力有可能借助其它方式提供给谷歌眼镜，这将是下一个阶段量子人工智能实验室的主要工作内容。

南加州大学研究人员初步验证D-Wave量子芯片 2013-06-30

南加州大学研究人员称量子效应确实存在于D-Wave处理器中。D-Wave是第一台商用量子计算机。在实验中，D-Wave的运行方式显示量子动力学确实起到了预期的作用。但是这项实验只涉及该芯片128个量子位的一个小子集，也就是说，D-Wave处理器目前还只是看起来像是个量子处理器，到底是不是还有待进一步验证。

富士通公司/富士通量子器件(Fujistu Quantum Device)公司

富士通公司的研究人员已经研制出了一种实验型的量子芯片，他们说它每秒钟的运算能力可高达１万亿次。

HYPRES, Inc. Elmsford, NY

IBM

IBM Says It's 'On the Cusp' of Building a Quantum Computer

IBM Qubit Chip

IBM scientists said Tuesday that they have made several breakthroughs in quantum computing that put them "on the cusp of building systems that will take computing to a whole new level."

The IBM researchers said they have established three new records "for retaining the integrity of quantum mechanical properties in quantum bits, or qubits, and reducing errors in elementary computations." Those advances, presented at this week's annual American Physical Society meeting, get the team "close to the minimum requirements for a full-scale quantum computing system as determined by the world-wide research community."

Quantum computing, first proposed by the Nobel Prize-winning physicist Richard Feynman in 1981, is still highly theoretical, with experiments in the science and its cousin, quantum cryptography, limited to laboratory settings thus far. In other words, there are no practical quantum computers yet, just experimental ones.

The basic concept is to use the odd nature of the entangled qubits (a magnified qubit is pictured below) that one uses to build a quantum computer to perform computational tasks much faster and much more securely than is possible on digital computers that use silicon transistors.

Magnified Qubit

At the exceedingly tiny level where quantum mechanics operates, particles of matter can exist in multiple states—such as "on" and "off" to reference the binary process by which digital computing operates—at the same time. We may not be able to comprehend what this means outside of mathematics, but scientists have theorized for several decades that harnessing these properties for computing would be a natural way past the issues that loom for today's nanoscale silicon-based transistors, which are running up against atomic-level barriers to functionality the smaller they get.

"The special properties of qubits will allow quantum computers to work on millions of computations at once, while desktop PCs can typically handle minimal simultaneous computations," the IBM researchers said. "For example, a single 250-qubit state contains more bits of information than there are atoms in the universe.

"These properties will have wide-spread implications foremost for the field of data encryption and other possible applications such as searching databases of unstructured information, performing a range of optimization tasks and solving previously unsolvable mathematical problems," the team added, further elaborating on the possibilities of quantum computing in the video below.

IBM's superconducting qubit device suspends a roughly one-millimeter qubit in the center of a cavity on a small Sapphire chip (pictured below). The cavity "is formed by closing the two halves, and measurements are done by passing microwave signals to the connectors," the team said. The "3D" device looks rather big relative to the tiny conventional computer chips currently in use, but the team said that future scaling should make it possible to operate hundreds or even thousands of qubits in just such a device.

3D Qubit Chip

The team has also demonstrated a two-dimensional chip that houses three qubits (pictured below, with qubits 1 through 3 identified). This 8mm-by-4mm chip "is back-mounted on a PC board and connects to I/O coaxial lines via wire bonds. IBM scientists also envision scaling this design to the point where a larger assembly of qubits would be possible on such a chip.

2D Three-Qubit Chip

It should be noted that the recent scientific paper published by a different group of international researchers concerning the successful fabrication of an atom-sized silicon transistor isn't an advance in quantum computing, per se.

The team led Michelle Simmons of the University of New South Wales in Sydney demonstrated a repeatable process for making a working microchip transistor comprised of a single atom—nearly 100 times smaller than the 22-nanometer cutting-edge transistors fabricated by Intel—but the process is compatible with the CMOS technology used in transistor fabrication today.

Simmons and her colleagues have taken the miniaturization of silicon-based processors to the limit of what may be possible within the confines of current microprocessor architectures and manufacturing processes, but quantum computing researchers are attempting to redefine computing (and possibly semiconductor manufacturing) entirely.

That said, the IBM team noted that it has chosen to "employ superconducting qubits which use established microfabrication techniques developed for silicon technology, providing the potential to one day scale up to and manufacture thousands or millions of qubits."

Developers wanted: Quantum computing, Python, and Jupyter Notebooks

https://developer.ibm.com/code/2017/03/10/developers-wanted-quantum-computing-python-jupyter-notebooks/

https://developer.ibm.com/open/docs/lev-bishop-ibm-quantum-computing/

https://developer.ibm.com/open/docs/andrew-cross-ibm-research/

QISKit open source project

https://developer.ibm.com/open/openprojects/qiskit/

IBM Quantum Experience

http://www.research.ibm.com/quantum/

IBM Q

https://www.research.ibm.com/ibm-q/

https://www.research.ibm.com/ibm-q/

英特尔推出十七个超导量子位芯片

2017年10月12日

芯片巨头英特尔公司开始为量子计算机制造芯片。英特尔10日通过其官网宣布，公司生产出一种包含17个超导量子位的全新芯片，并交付给合作伙伴对该款量子芯片进行各种性能测试。这一举动标志着量子计算正从学术实验室进入半导体产业，向实用领域迈进。

    与传统计算机通过0和1进行数据储存和处理不同，量子计算机运用量子位处理数据，一次不只一种的量子态并行处理，从而用一种完全不同的方式来并行计算信息，克服了“摩尔定律”对传统计算机的速度限制。量子计算机相关研究近几年虽然发展很快，但还是停留在实验室阶段，仍面临着极不稳定的困境，即任何背景噪音或无意干扰都会让量子位丢失数据。

    英特尔公司利用自身在芯片制造业的丰富经验，基于现有电子电路设计，生产出这款超导量子芯片。但超导量子位相当脆弱，需要在比外太空温度还低250倍的极低温度下工作，这对量子芯片的组装提出了挑战。但英特尔采用已有的300纳米“覆晶技术”（flip chip），通过修改材料、电路设计以及不同组件之间的链接，克服了超导芯片低温集成的问题，使芯片能在更高温度下更加稳定，量子位之间的射频干扰也更小。

    量子计算机之前是谷歌和IBM间的较量，英特尔近年加大投入，加上公司自身的芯片集成专长，开始赶超竞争对手。英特尔加强与其他公司的合作，比如2015年向荷兰代尔夫特大学的QuTech公司投入5000万美元，研发更稳定的量子位。QuTech现在已经拿到这款17个量子位芯片，即将用最新算法模型对其进行性能测试。除了超导量子位芯片，公司还在同时研发基于硅芯片的自旋量子位，这些自旋电子位类似单电子晶体管，因而在许多方面与传统晶体管相似，很可能与现有制造工艺兼容。聂翠蓉

奥地利因斯布鲁克大学Gregor Weihs博士

奥地利砷化镓半导体量子芯片研究取得重大突破2012/5/11

量子芯片的研究是为了使量子技术可以应用于日常生活中，如量子密码和更高性能的日常用量子计算机等。

近日由奥地利因斯布鲁克大学Gregor Weihs博士领导的奥地利和加拿大的科学家们组成的课题小组首次在实验室中一块由砷化镓制成的半导体上实现了具有可行性的光子对源。据实验数据，该芯片仍具有较高的功率损耗。但据Gregor Weihs博士介绍，“其效果非常好，在此条件下接收到了良好的信号。”其突破加快了日常用量子光学元件制造和信息量子化的进程。

April 19, 2012

Thanks to Austro-Canadian cooperation the long term objective of developing a quantum chip comes within reach.

?An international team headed by Photonics Professor Gregor Weihs from Innsbruck, managed to build a chip, which creates entangled photons. This is a first step to the development of quantum chips and quantum computers.

In order to achieve this goal, scientists from the University of Innsbruck ( http://www.uibk.ac.at/ ), the University of Toronto ( www.utoronto.ca ), and the University of Waterloo ( http://uwaterloo.ca ) got together and shared their knowledge and expertise.

The scientists were able to build a chip, from tiny layers of Gallium-Arsenid, each not more than a few nanometers thick. The specific way of construction prevents the entangled photon pairs of being separated again. This means a significant increase in efficiency. Entanglement again is one of the crucial preconditions for quantum informatics.

Physicists like Professor Weihs and his colleagues have long dreamed of such an integrated source of entangled photons, which now has finally come true. This technology will help to facilitate high complex calculations standard computers cannot handle in adequate time. Additionally it will help to replace the costly and extensive make-up of todays laboratory benches.

Gregor Weihs is Professor of Photonics at the University of Innsbruck and also holds the Canada Research chair in Quantum Photonics of the University of Waterloo.

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Nokia/Toshiba

Nokia/Toshiba to put breakthrough silicon based Quantum Chip in smart phones by 2015?

Not certain a "quantum chip" will be adapted into smartphones within 3 years myself, but I am no toshiba or nokia. Wish there were more concise info on this breakthrough.

Scientists from Bristol will this week show a quantum computing chip, which partners such as Toshiba and Nokia hope to build into commercial phones and other systems within the next few years, securing communications and attacking previously insolvable problems.

Quantum computing has the potential to massively speed up calculations and provide more secure communications.

The Bristol Centre for Quantum Photonics hopes to establish and patent key technologies which can be licensed to manufacturers, becoming a central player in the technology which could push electronics beyond the limitations of Moore’s Law.

“We are envisaging a model like ARM or CSR,” said Dr Mark Thompson, the Bristol physicist leading the work, referring to two British chip designers whose low-power processors are manufactured in the Far East, but dominate the world’s smartphones and tablets in the case of ARM, and are important for radio communications in the case of CSR.

“Already, the South West [of England] has the biggest cluster of silicon designers outside of Silicon Valley.”

??? The proposal is more radical than ARM or CSR, however, as Thompson’s team are building quantum computers with optical waveguides on silicon, instead of simply creating a better design for a conventional chip.

??? A group of scientists have developed a quantum computer chip that could lead to ultra-fast computer processors, which would outperform those found in today’s standard electronics and smartphones.

??? The group, led by researchers from the University of Bristol’s Centre for Photonics, will unveil the new silicon quantum chip at the 2012 British Science Festival, which starts Tuesday.

??? The new silicon chips are significant because they work by manipulating light particles to perform calculations, an improvement over current chips that use electrical currents.

??? The new chips are also 1,000 times smaller than older chips made of glass, and could eventually be used to develop tiny hybrid processors – a mix of conventional and quantum processors -- in all computers and smartphones.

??? The centre’s deputy director Mark Thompson said the development of the new, smaller chips means researchers can use the technology in devices that were previously not compatible with older chips.
This means new areas of science can be explored, said Thompson.

??? “This is very much the start of a new field of quantum-engineering, where state-of-the-art micro-chip manufacturing techniques are used to develop new quantum technologies and will eventually realize quantum computers that will help us understand the most complex scientific problems,” he said in a press release.
LONDON – Quantum computing has been brought a step closer to mass production by a research team led by scientists from the University of Bristol that has made a transition from using glass to silicon.

??? The Bristol team has been demonstrating quantum photonic effects in glass waveguides for a number of years but the use of a silicon chip to demonstrate photonic quantum mechanical effects such as superposition and entanglement, has the advantage of being a match to contemporary high volume manufacturing methods, the team claimed.

??? This could allow the creation of hybrid circuits that mix conventional electronic and photonic circuitry with a quantum circuit for applications such as secure communications.

NSA

NSA seeks to build quantum computer that could crack most types of encryption? 2014-1-3

By Steven Rich and Barton Gellman, Friday, January 3, 5:24 AM E-mail the writers

In room-size metal boxes -secure against electromagnetic leaks, the National Security Agency is racing to build a computer that could break nearly every kind of encryption used to protect banking, medical, business and government records around the world.

According to documents provided by former NSA contractor Edward Snowden, the effort to build “a cryptologically useful quantum computer” — a machine exponentially faster than classical computers — is part of a $79.7 million research program titled “Penetrating Hard Targets.” Much of the work is hosted under classified contracts at a laboratory in College Park, Md.
Explore the documents

annotated nsa document
Penetrating Hard Targets

Explore an annotated version of the NSA's description of its effort to build "a cryptologically useful quantum computer." Read it.

Classifying the NSA's efforts

The agency describes classification levels for information related to quantum computing. Read it.

Snowden, in interview, says his mission’s accomplished
Snowden, in interview, says his mission’s accomplished

Barton Gellman DEC 24

His leaks have fundamentally altered the U.S. government’s relationship with its citizens, the rest of the world.
Full coverage: NSA Secrets
Full coverage: NSA Secrets

Read all of the stories in The Washington Post’s ongoing coverage of the National Security Agency’s surveillance programs.

"If you think you understand quantum mechanics, you don't understand quantum mechanics," said the late Nobel laureate Richard Feynman, widely regarded as the pioneer in quantum computing. The science video blog Vertiasium tries to help make sense of it.
Click here to subscribe.

[Read an annotated description of the Penetrating Hard Targets project]

The development of a quantum computer has long been a goal of many in the scientific community, with revolutionary implications for fields such as medicine as well as for the NSA’s code-breaking mission. With such technology, all current forms of public key encryption would be broken, including those used on many secure Web sites as well as the type used to protect state secrets.

Physicists and computer scientists have long speculated about whether the NSA’s efforts are more advanced than those of the best civilian labs. Although the full extent of the agency’s research remains unknown, the documents provided by Snowden suggest that the NSA is no closer to success than others in the scientific community.

“It seems improbable that the NSA could be that far ahead of the open world without anybody knowing it,” said Scott Aaronson, an associate professor of electrical engineering and computer science at the Massachusetts Institute of Technology.

The NSA appears to regard itself as running neck and neck with quantum computing labs sponsored by the European Union and the Swiss government, with steady progress but little prospect of an immediate breakthrough.

“The geographic scope has narrowed from a global effort to a discrete focus on the European Union and Switzerland,” one NSA document states.

Seth Lloyd, an MIT professor of quantum mechanical engineering, said the NSA’s focus is not misplaced. “The E.U. and Switzerland have made significant advances over the last decade and have caught up to the U.S. in quantum computing technology,” he said.

The NSA declined to comment for this article.

The documents, however, indicate that the agency carries out some of its research in large, shielded rooms known as Faraday cages, which are designed to prevent electromagnetic energy from coming in or out. Those, according to one brief description, are required “to keep delicate quantum computing experiments running.”

[Read a document describing classification levels related to quantum computing efforts]

The basic principle underlying quantum computing is known as “quantum superposition,” the idea that an object simultaneously exists in all states. A classical computer uses binary bits, which are either zeroes or ones. A quantum computer uses quantum bits, or qubits, which are simultaneously zero and one.

This seeming impossibility is part of the mystery that lies at the heart of quantum theory, which even theoretical physicists say no one completely understands.

“If you think you understand quantum mechanics, you don’t understand quantum mechanics,” said the late Nobel laureate Richard Feynman, who is widely regarded as the pioneer in quantum computing.

Here’s how it works, in theory: While a classical computer, however fast, must do one calculation at a time, a quantum computer can sometimes avoid having to make calculations that are unnecessary to solving a problem. That allows it to home in on the correct answer much more quickly and efficiently.

Quantum computing is difficult to attain because of the fragile nature of such computers. In theory, the building blocks of such a computer might include individual atoms, photons or electrons. To maintain the quantum nature of the computer, these particles would need to be carefully isolated from their external environments.

“Quantum computers are extremely delicate, so if you don’t protect them from their environment, then the computation will be useless,” said Daniel Lidar, a professor of electrical engineering and the director of the Center for Quantum Information Science and Technology at the University of Southern California.

A working quantum computer would open the door to easily breaking the strongest encryption tools in use today, including a standard known as RSA, named for the initials of its creators. RSA scrambles communications, making them unreadable to anyone but the intended recipient, without requiring the use of a shared password. It is commonly used in Web browsers to secure financial transactions and in encrypted -e-mails. RSA is used because of the difficulty of factoring the product of two large prime numbers. Breaking the encryption involves finding those two numbers. This cannot be done in a reasonable amount of time on a classical computer.

In 2009, computer scientists using classical methods were able to discover the primes within a 768-bit number, but it took almost two years and hundreds of computers to factor it. The scientists estimated that it would take 1,000 times longer to break a 1,024-bit encryption key, which is commonly used for online transactions.

A large-scale quantum computer, however, could theoretically break a 1,024-bit encryption much faster. Some leading Internet companies are moving to 2,048-bit keys, but even those are thought to be vulnerable to rapid decryption with a quantum computer.

Quantum computers have many applications for today’s scientific community, including the creation of artificial intelligence. But the NSA fears the implications for national security.

“The application of quantum technologies to encryption algorithms threatens to dramatically impact the US government’s ability to both protect its communications and eavesdrop on the communications of foreign governments,” according to an internal document provided by Snowden.

Experts are not sure how soon a quantum computer would be feasible. A decade ago, some experts said that developing a large quantum computer was likely 10 to 100 years in the future. Five years ago, Lloyd said the goal was at least 10 years away.

Last year, Jeff Forshaw, a professor at the University of Manchester, told Britain’s Guardian newspaper, “It is probably too soon to speculate on when the first full-scale quantum computer will be built but recent progress indicates that there is every reason to be optimistic.”

“I don’t think we’re likely to have the type of quantum computer the NSA wants within at least five years, in the absence of a significant breakthrough maybe much longer,” Lloyd told The Washington Post in a recent interview.

Some companies, however, claim to already be producing small quantum computers. A Canadian firm, D-Wave Systems , says it has been making quantum computers since 2009. In 2012, it sold a $10 million version to Google, NASA and the Universities Space Research Association, according to news reports.

That quantum computer, however, would never be useful for breaking public key encryption like RSA.

“Even if everything they’re claiming is correct, that computer, by its design, cannot run Shor’s algorithm,” said Matthew Green, a research professor at the Johns Hopkins University Information Security Institute, referring to the algorithm that could be used to break encryption like RSA.

Experts think that one of the largest hurdles to breaking encryption with a quantum computer is building a computer with enough qubits, which is difficult given the very fragile state of quantum computers. By the end of September, the NSA expected to be able to have some building blocks, which it described in a document as “dynamical decoupling and complete quantum -control on two semiconductor qubits.”

“That’s a great step, but it’s a pretty small step on the road to building a large-scale quantum computer,” Lloyd said.

A quantum computer capable of breaking cryptography would need hundreds or thousands more qubits than that.

The budget for the National Intelligence Program, commonly referred to as the “black budget,” details the “Penetrating Hard Targets” project and noted that this step “will enable initial scaling towards large systems in related and follow-on efforts.”

Another project, called “Owning the Net,” is using quantum research to support the creation of quantum-based attacks on encryptions like RSA, documents show.

“The irony of quantum computing is that if you can imagine someone building a quantum computer that can break encryption a few decades into the future, then you need to be worried right now,” Lidar said.

NSA Building A $2 Billion Quantum Computer Artificial Intelligence Spy Center

?
NSA Building 2 Billion Dollar Quantum Computer Center

The NSA is a data center to house a 512 qubit quantum computer capable of learning, reproducing the brain’s cognitive functions, and programming itself.

The National Security Center is building a highly fortified $2 Billion highly top secret complex simply named the “Utah Data Center” which will soon be home to the Hydrogen bomb of cybersecurity – A 512 Qubit Quantum Computer — which will revitalize the the “total information awareness” program originally envisioned by George Bush in 2003.

The news of the data center comes after Department of Defense contractor Lockheed Martin secured a contract with D-Wave for $10 million for a 512 qubit Quantum Computer code-named Vesuvius.

Vesuvius is capable of executing a massive number of computations at once, more than 100,000,000,000,000,000,000,000,000,000,000,000,000, which is would take millions of years on a standard desktop.

The computer will be able to crack even the most secure encryption and will give the US government a quantum leap into technologies once only dreamed of including the rise of the world’s very first all-knowing omniscient self-teaching artificial intelligence.

The D-Wave Quantum computer boasts of a wide array of features including:

Binary classification – Enables the quantum computer to be fed vast amounts of complex input data, including text, images, and videos and label the material
Quantum Unsupervised Feature Learning QUFL – Enables the computer to learn on its own, as well as create and optimize its own programs to make itself run more efficiently.
Temporal QUFL – Enables the Computer to predict the future based in information it learns through Binary classification and the QUFL feature.
Artificial Intelligence Via Quantum Neural Network – Enables the computer to completely reconstruct the human brain’s cognitive processes and teach itself how to make better decisions and better predict the future based.

Ohio State University

QUANTUM COMPUTER CHIPS NOW ONE STEP CLOSER TO REALITY

COLUMBUS, Ohio -- In the quest for smaller, faster computer chips, researchers are increasingly turning to quantum mechanics -- the exotic physics of the small.

The problem: the manufacturing techniques required to make quantum devices have been equally exotic.
Paul Berger

That is, until now.

Researchers at Ohio State University have discovered a way to make quantum devices using technology common to the chip-making industry today.

This work might one day enable faster, low-power computer chips. It could also lead to high-resolution cameras for security and public safety, and cameras that provide clear vision through bad weather.

Paul Berger, professor of electrical and computer engineering and professor of physics at Ohio State University, and his colleagues report their findings in an upcoming issue of IEEE Electron Device Letters.

The team fabricated a device called a tunneling diode using the most common chip-making technique, called chemical vapor deposition.

“We wanted to do this using only the tools found in the typical chip-makers toolbox,” Berger said. “Here we have a technique that manufacturers could potentially use to fabricate quantum devices directly on a silicon chip, side-by-side with their regular circuits and switches.”

The quantum device in question is a resonant interband tunneling diode (RITD) -- a device that enables large amounts of current to be regulated through a circuit, but at very low voltages. That means that such devices run on very little power.

RITDs have been difficult to manufacture because they contain dopants -- chemical elements -- that don’t easily fit within a silicon crystal.

Atoms of the RITD dopants antimony or phosphorus, for example, are large compared to atoms of silicon. Because they don’t fit into the natural openings inside a silicon crystal, the dopants tend to collect on the surface of a chip.

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“Chip makers today are having a great difficulty boosting performance in each generation, so they pack chips with more and more circuitry, and end up generating a lot of heat,” Berger said. “That’s why a laptop computer is often too hot to actually sit atop your lap. Soon, their heat output will rival that of a nuclear reactor per unit volume.”

“It’s like when you’re playing Tetris and you have a big block raining down, and only a small square to fit it in. The block has to sit on top,” Berger said. “When you’re building up layers of silicon, these dopants don’t readily fit in. Eventually, they clump together on top of the chip.”

In the past, researchers have tried adding the dopants while growing the silicon wafer one crystal layer at a time -- using a slow and expensive process called molecular beam epitaxy, a method which is challenging for high-volume manufacturing. That process also creates too many defects within the silicon.

Berger discovered that RITD dopants could be added during chemical vapor deposition, in which a gas carries the chemical elements to the surface of a wafer many layers at a time. The key was determining the right reactor conditions to deliver the dopants to the silicon, he found.

“One key is hydrogen,” he said. “It binds to the silicon surface and keeps the dopants from clumping. So you don’t have to grow chips at 320 degrees Celsius [approximately 600 degrees Fahrenheit] like you do when using molecular beam epitaxy. You can actually grow them at a higher temperature like 600 degrees Celsius [more than 1100 degrees Fahrenheit] at a lower cost, and with fewer crystal defects.”

Tunneling diodes are so named because they exploit a quantum mechanical effect known as tunneling, which lets electrons pass through thin barriers unhindered.

In theory, interband tunneling diodes could form very dense, very efficient micro-circuits in computer chips. A large amount of data could be stored in a small area on a chip with very little energy required.

Researchers judge the usefulness of tunneling diodes by the abrupt change in the current densities they carry, a characteristic known as “peak-to-valley ratio.” Different ratios are appropriate for different kinds of devices. Logic circuits such as those on a computer chip are best suited by a ratio of about 2.

The RITDs that Berger’s team fabricated had a ratio of 1.85.
“We’re close, and I’m sure we can do better,” he said.

He envisions his RITDs being used for ultra-low-power computer chips operating with small voltages and producing less wasted heat.

“Chip makers today are having a great difficulty boosting performance in each generation, so they pack chips with more and more circuitry, and end up generating a lot of heat,” Berger said. “That’s why a laptop computer is often too hot to actually sit atop your lap. Soon, their heat output will rival that of a nuclear reactor per unit volume.”

“That’s why moving to quantum devices will be a game-changer.”
RITDs could form high-resolution detectors for imaging devices called focal plane arrays. These arrays operate at wavelengths beyond the human eye and can permit detection of concealed weapons and improvised explosive devices. They can also provide vision through rain, snow, fog, and even mild dust storms, for improved airplane and automobile safety, Berger said. Medical imaging of cancerous tumors is another potential application.

His coauthors on the paper included Si-Young Park, and R. Anisha, both doctoral students in electrical engineering at Ohio State; and Roger Loo, Ngoc Duy Nguyen, Shotaro Takeuchi, and Matty Caymax, all of? IMEC, an industrial research center in Belgium.

This work was partially supported by the National Science Foundation.

#

Contact:? Paul R. Berger, (614) 247-6235; pberger@ieee.org
Written by Pam Frost Gorder, (614) 292-9475; Gorder.1@osu.edu

Purdue University builds quantum-computing semiconductor chip

R. Colin Johnson
9/24/2001

qubit.org

www.qubit.org

Schoelkopf, Robert and Girvin, Steven

Robert Schoelkopf and Steven Girvin

Quantum computing a step closer to commercial reality

0 comments

Posted by IT-Online on Sep 26, 2007 in News | 0 comments

Two major steps toward putting quantum computers into real practice have been taken by scientists at Yale.

The group has reported how it can send a photon signal on demand from a qubit on to wires and transmit the signal to a second, distant qubit in the journal Nature.

Over the past several years, the research team of Professors Robert Schoelkopf in applied physics and Steven Girvin in physics has explored the use of solid-state devices resembling microchips as the basic building blocks in the design of a quantum computer. Now, for the first time, they report that superconducting qubits, or artificial atoms, have been able to communicate information not only to their nearest neighbor, but also to a distant qubit on the chip.

This research now moves quantum computing from "having information" to "communicating information".

In the past, information had only been transferred directly from qubit to qubit in a superconducting system. Schoelkopf and Girvin's team has engineered a superconducting communication 'bus' to store and transfer information between distant quantum bits, or qubits, on a chip. This work, according to Schoelkopf, is the first step to making the fundamentals of quantum computing useful.

The first breakthrough reported is the ability to produce on demand – and control – single, discrete microwave photons as the carriers of encoded quantum information. While microwave energy is used in cell phones and ovens, their sources do not produce just one photon. This new system creates a certainty of producing individual photons.

"It is not very difficult to generate signals with one photon on average, but, it is quite difficult to generate exactly one photon each time. To encode quantum information on photons, you want there to be exactly one," according to postdoctoral associates Andrew Houck and David Schuster who are lead co-authors on the first paper.

"We are reporting the first such source for producing discrete microwave photons, and the first source to generate and guide photons entirely within an electrical circuit," says Schoelkopf.

In order to successfully perform these experiments, the researchers had to control electrical signals corresponding to one single photon. In comparison, a cell phone emits about

100,000,000,000,000,000,000,000 photons per second. Further, the extremely low energy of microwave photons mandates the use of highly sensitive detectors and experiment temperatures just above absolute zero.?

"In this work we demonstrate only the first half of quantum communication on a chip – quantum information efficiently transferred from a stationary quantum bit to a photon or 'flying qubit,'" says Schoelkopf. "However, for on-chip quantum communication to become a reality, we need to be able to transfer information from the photon back to a qubit."

This is exactly what the researchers go on to report in the second breakthrough. Postdoctoral associate Johannes Majer and graduate student Jerry Chow, lead co-authors of the second paper, added a second qubit and used the photon to transfer a quantum state from one qubit to another. This was possible because the microwave photon could be guided on wires – similarly to the way fiber optics can guide visible light – and carried directly to the target qubit.

"A novel feature of this experiment is that the photon used is only virtual," say Majer and Chow, "winking into existence for only the briefest instant before disappearing."

To allow the crucial communication between the many elements of a conventional computer, engineers wire them all together to form a data "bus," which is a key element of any computing scheme. Together the new Yale research constitutes the first demonstration of a "quantum bus" for a solid-state electronic system. This approach can in principle be extended to multiple qubits, and to connecting the parts of a future, more complex quantum computer.

However, Schoelkopf likens the current stage of development of quantum computing to conventional computing in the 1950's, when individual transistors were first being built.? Standard computer microprocessors are now made up of a billion transistors, but first it took decades for physicists and engineers to develop integrated circuits with transistors that could be mass produced.

Stevens Institute of Technology

http://research.stevens.edu/index.php/strauf-nsf-career-award

Assistant Professor Stefan Strauf
Dr. Stefan Strauf,
Assistant Professor of Physics and Engineering Physics

东京大学

日本科学家正研制比现在使用的速度快数倍的量子芯片。东京大学的研究人员正在一间无尘净室中寻找一种新型的半导体，他们使用价值８００万美元的设备把几种材料的仅有几个原子厚的显微层结合在一起，使它比较容易让电子四处流动。他们把这种新化合物叫做实验性的量子芯片。

TU Delft

TU Delft researchers lay solid foundation for a ‘quantum internet’ 24 April 2013

Webredactie

Researchers at TU Delft have managed to bring two electrons, three metres from each other, into a quantum- entangled state. This result marks a major step towards realizing a quantum network that can be used to connect future quantum computers and to send information in a completely secure way by means of ‘teleportation’. The results have been published online on 24 April in Nature.

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Entanglement
Entanglement is arguably the most intriguing consequence of the laws of quantum mechanics. When two particles become entangled, their identities merge: their collective state is precisely determined but the individual identity of each of the particles has disappeared. The entangled particles behave as one, even when separated by a large distance. Einstein doubted this prediction, which he called ‘spooky action at a distance’, but experiments have proven its existance.?

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Entangled states are interesting for computers as they allow a huge number of calculations to be carried out simultaneously. A quantum computer with 400 basic units (‘quantum bits’) could, for example, already process more bits of information simultaneously than there are atoms in the universe. In recent years, scientists have succeeded in entangling quantum bits within a single chip. Now, for the first time, this has been successfully achieved with quantum bits on different chips.

Stable
Prof. Ronald Hanson’s research group at TU Delft’s Kavli Institute of Nanoscience makes quantum bits from electrons in diamonds. ‘We use diamonds because they form ‘mini-prisons’ for electrons if there is a nitrogen atom in the position of one of the carbon atoms. As we can examine these mini-prisons individually, we can study and monitor an individual electron and even a single atomic nucleus. We can prepare the spin (direction of rotation) of these particles in a previously determined state, control the spin and subsequently read it out. We do all this using a material from which chips can be made. That is important it is believed that only chip-based systems can be scaled up to a practical technology’, Hanson explains.

Entanglement over a distance of three metres

Co-financed by the FOM Foundation and in cooperation entity. ‘Incidentally, the three-metre distance between the electrons was chosen quite arbitrarily. We could conduct this experiment over much larger distances’, Hanson adds.with the British firm Element Six, Hanson and his colleagues succeeded in bringing two electrons in different diamonds, situated at several metres’ distance from each other, into an entangled state. As the two electrons do not feel each other at this large distance, the researchers used light particles to mediate the required interaction. To prove the resulting entanglement, the spin orientation of both electrons was read out and compared. Although the spin orientation of each electron individually was completely random, exactly as predicted by quantum mechanics, the researchers found that the two orientations were always exactly opposite to each other. This proves that the two electrons are entangled and behave as a single entity. ‘Incidentally, the three-metre distance between the electrons was chosen quite arbitrarily. We could conduct this experiment over much larger distances’, Hanson adds.

TeleportationThe next step for the research is the teleportation of electrons. Hanson: ‘In theory it is possible to ‘teleport’ the state of a particle over a large distance to another particle by making smart use of entanglement. Quantum teleportation does not relocate the material itself, but only the state of that material. But given the fact that all elementary particles are identical, quantum teleportation of one electron to another has the same effect as relocating the electron.’

Sending information safely
According to Hanson, in addition to new fundamental insights, there are two further reasons why the publication in Nature is likely to be an important impulse for the development of new technologies. ‘Firstly, because this is an important step towards creating a quantum network for communication between future quantum computers – a quantum internet. We are already working on expanding the experiments using more quantum bits per chip. Entanglement could be used to link such a network of quantum computers.’

‘Secondly, teleportation offers the possibility of sending information in a completely secure way. With teleportation, the information does not travel through the intermediate space and therefore cannot be intercepted.’??

University of Michigan

University of Michigan scientists announced that they have created the first quantum microchip, which could be a giant stride in the race to produce a new generation of extremely fast and powerful supercomputers. On a semiconductor chip roughly the size of a postage stamp, the scientists designed and built a device known as an ion trap, which allowed them to isolate individual charged atoms and manipulate their quantum states. An ion expresses a positive or negative charge, depending on whether its parent atom has a missing or an extra electron. And ions are the preferred building blocks for a quantum system. The new chip, should be easily scaled and mass-produced, because it’s made using microlithography — the same process that makes microchips.

First Mass Producible Quantum Computer Chip

December 15th, 2005 by Thomas Herold Print Email

Researchers at the University of Michigan have produced what is believed to be the first scalable quantum computer chip, which could mean big gains in the worldwide race to develop a quantum computer.

Using the same semiconductor fabrication technology that is used in everyday computer chips, researchers were able to trap a single atom within an integrated semiconductor chip and control it using electrical signals, said Christopher Monroe, U-M physics professor and the principal investigator and co-author of the paper, "Ion Trap in a Semiconductor Chip." The paper appeared in the Dec. 11 issue of Nature Physics.

Quantum computers are promising because they can solve certain problems much faster than any possible conventional computer, owing to the bizarre features of quantum mechanics. For instance, quantum computers can process multiple inputs at the same time in the same device, and quantum circuitry can be wired via the quantum feature of entanglement, dubbed by Einstein as "spooky action-at-a-distance."

One of the most favored candidate quantum computer architectures is the use of individual atoms to store quantum bits ( qubits) of information, where each qubit can hold the number 1 or 0, or even both 1 and 0 simultaneously, Monroe said. Electrically charged atoms (ions) for such quantum computers are stored in what are known as ion traps. Trapping is necessary in order to isolate the qubits from the rest of the world, which is absolutely essential for the system to behave quantum mechanically. It is well known how to program a quantum computer composed of any number of trapped ions; the problem is to get the ions trapped in the first place.

Current ion traps can only hold a few atoms or qubits, and are not easily scaled. Rather, these ion traps are assembled laboriously by hand. Therefore, one of the obstacles to perfecting the quantum computer is making a scalable integrated quantum computer chip that can store thousands or more atomic ions. For this reason, efforts in the area of quantum computing are now focused on making ion traps on a chip that are scalable and mass producible, and can host larger numbers of qubits.
"The semiconductor chip we demonstrated holds an individual atom in free space inside the chip—we levitate the atom in the chip by applying certain electrical signals to the tiny nearby electrodes," Monroe said. "We directly view this single atom with specially-tuned lasers and a sensitive camera. This type of ion trap has never been demonstrated at such a small level and in an integrated chip structure."

The chip produced at U-M is about as big as a postage stamp. It is etched with electrodes using a process called lithography, which eliminates the need for manual assembly. Each electrode is connected to a separate voltage supply, and these various electrical voltages serve to control the ion by moving it in different ways as it hovers in a space carved out of the chip.

Using existing microfabrication technology, the quantum chip developed at U-M could be scaled up to include hundreds of thousands of electrodes, Monroe said.

"There is a worldwide race to build these (chips) right now, as such an integrated chip structure shows a way to scale the quantum computer to bigger systems—just like the microfabrication of conventional chips have given us the impressive gains in conventional computing speed and power," Monroe said.

The next step is to build the chip bigger with many more electrodes, so that it can store more ions. "There is still a great deal of work to be done in order to learn how to control lots of ions in one of these chips. It won’t be nearly as easy as it was with conventional computer chips, but at least we know what to do in principle," Monroe said.

Doctoral student Daniel Stick, in Monroe’s group in the U-M Physics Department and FOCUS Center (Frontiers in Optical, Coherent, and Ultrafast Science), led this work in collaboration with the Laboratory for Physical Sciences at the University of Maryland.

University of Toronto Engineering

Faculty of Applied Science and Engineering | University of Toronto

Research Breakthrough Takes Supercomputing Out of the Lab

HelmyGraph

The semiconductor chip schematic shown here is a depiction of the integrated circuits designed by the Helmy research group, where the chip takes in photons from an external source (blue) and through the intricate design of the circuit. The result is two photons (red) that are entangled without the need for other circuitry or components.

April 30, 2012

In the age of high-speed computing, the photon is king. However, producing the finely tuned particles of light is a complex and time-consuming process, until now.

Thanks to the work by a team of engineers led by Professor Amr Helmy of The Edward S. Rogers Sr. Department of Electrical & Computer Engineering, a novel solution has been identified that will make the production of special class of photons faster and easier.

Advanced computing technologies – such as ultra-secure communication systems and optical quantum computers – use light to quickly relay information. To enable these technologies to work, a photon – the smallest unit of energy – has to be tightly coupled with another photon. These are known as entangled photon pairs. The current means of production uses relatively bulky optical equipment in specialized labs. The photons are also extremely delicate to construct and are very sensitive to mechanical vibrations. This complexity and associated cost currently makes the use of this technology in homes or offices impracticable.

Professor Helmy’s team offers an innovative solution. These engineers have successfully designed a new integrated counterpart to the delicate laboratory equipment that could produce the entangled photon pairs using an integrated circuit. Ultimately, the entire production of the photons could be completed using a single chip. The team in Toronto along with their colleagues at the University of Waterloo and Universit?t Innsbruck, have tested the first generation of these devices. They reported their findings in a recent issue of Physical Review Letters.

“The research offers the prospect of unleashing the potential of the powerful and underutilized quantum technologies into the main stream commercial world, out of the lab,” explained Professor Helmy.

While other attempts at creating a chip-based solution didn’t permit the addition of other components, Professor Helmy’s team used a semiconductor chip that would function with the other existing equipment. This makes it possible to have all of the required components that traditionally exist in a laboratory be on the same chip.

Utilizing quantum optical computing will be key in solving extremely difficult computational problems, such as complex data sorting. Optical computers are much faster than any classical computer thanks to their ability to use advanced modern algorithms. Producing entangled pairs using this chip is a first and significant step towards making them commercially available and perhaps might lead to future quantum-optical gadgets.

University of Waterloo

Quantum computing the ‘Holy Grail’ for University of Waterloo scientists

At the Institute for Quantum Computing, scientists on quest for something that is at once almost unimaginably small and yet colossally powerful.

?“Before we make one chip that works, we make 1,000 that don’t,” says physicist Raymond Laflamme at the University of Waterloo.

Oakland Ross / Toronto Star Order this photo

“Before we make one chip that works, we make 1,000 that don’t,” says physicist Raymond Laflamme at the University of Waterloo.
By: Oakland Ross Feature Writer, Published on Sun Jan 06 2013

WATERLOO, ONT.—Say hello to Raymond Laflamme — and forget everything you thought you knew about computers.

Forget about bits and bytes and silicon chips. Forget about mega-this and giga-that. Discard the impatience you sometimes feel while waiting for your laptop to perform some supposedly “complicated” function. Rid your mind of all those annoying little icons — from primitive-looking wristwatches to twirling coloured spheres — that indicate time is passing, and passing, while your doddering digital device stumbles from one slowpoke application to another.

Be done with all of that and, instead, start thinking about quantum mechanics.

Where computers are concerned, quantum mechanics are the future.

“It’s not an instantaneous transition,” says Laflamme, 50, formerly of Quebec City and now executive director of the Institute for Quantum Computing at the University of Waterloo. “It’s a process. But a quantum computer is the Holy Grail.”

Comparing a fully realized quantum computing device to even the most powerful classical computers now in existence is a bit like comparing a vast galaxy of swirling planets and radiant stars to a basement bachelor apartment in a transit-starved neighbourhood of Toronto.

In other words, there is really no comparison at all.

But there are two formidable obstacles facing anyone in the fledgling quantum computing business.

First, quantum computers are extremely difficult to build, so difficult that we haven’t actually built one yet, or not really.

Second, no matter how difficult they might be to fabricate, quantum computers are even more difficult to explain.

Despite these obstacles, quantum computing, or the prospect of quantum computing, is very much of the moment. Last month, two scientists — Frenchman Serge Haroche and American David J. Wineland — gathered in Stockholm to receive this year’s Nobel Prize for physics, honouring work they have done separately to advance the development of quantum computers.

They are far from alone.

In offices and laboratories scattered around the globe — in Russia, China, Singapore, Europe, the United States and Canada — some of the finest scientific minds are busily pursuing the same goal, a computing device whose fundamental components are so small as to be invisible to humans but whose calculating power would far outstrip any conventional computer you could imagine, even one as big as the universe itself.

Here in Canada, the main centre for this area of research — there are others — was founded 10 years ago at the University of Waterloo. Now the Institute for Quantum Computing is in the process of moving into palatial new quarters, the Mike & Ophelia Lazaridis Quantum-Nano Centre, designed by Toronto architectural firm KPMB and built at a cost of $160 million.

Headed by Laflamme, the institute brings 25 faculty members from roughly half a dozen countries together with about 40 post-doctoral fellows and roughly 90 students in the quest for something that is at once almost unimaginably small — on the scale of atoms and electrons — and yet colossally powerful.

Perhaps the best way to begin an explanation of what a quantum computer is might be to explain what it is not.

It is not a classical computer.

“A small quantum computer can do things no classical computer can do,” says Laflamme, a wiry, animated man with mobile facial features and a changeable yet nearly constant grin. “It’s a totally different class.”

Let’s face it, a classical computer is essentially a pretty stupid device. Its guts are a network of electrical circuits that can do just two things. They can be on or they can be off. They can be set at either “one” or “zero.”

Essentially, that’s all that classical computing is, a highly developed narrative of zeros or ones.

Here’s how it works.

A single computer circuit, called a bit, has just two possible states (0 or 1). Double that to two circuits and you get four states (00, 11, 01 or 10). With three circuits, you double the possible number of combinations yet again, this time to eight (001, 011, 111, 110, 100, 000, 101, 010). When you get to eight circuits, you have 256 possible combinations, and this arrangement is called a “byte.”

The processing power and memory capacity of laptop computers are nowadays calculated in gigabytes, meaning billions of bytes, and these numbers just keep getting bigger — but the trend is not going to last forever, not for classical computers.

At least since the 1970s, computer scientists have been familiar with a phenomenon known as Moore’s law, the principle that technological innovation causes computing power to double on average every two years. Or, to put the same idea another way, a computer circuit decreases in size, on average, by 50 per cent every two years, meaning you can fit twice as many into the same space.

At this rate, the computer industry is on track to run head-on into an immovable wall in approximately 10 years. Sometime between 2020 and 2030, processing circuits will have become so small — as small as atoms — that they will be regulated by the same physical imperative that governs atoms: the inability to get any smaller.

A laptop in 2025 will be vastly more powerful than any laptop today, but that will be the end of it. Classical computing will have reached a natural limit and will cease to evolve.

With any luck, however, this is where quantum computing will come in.

Put in its sparest terms, the difference between classical computing and quantum computing is a simple matter of a single conjunction — the substitution of “and” for “or.”

Recall that a conventional computer circuit, or a bit, can represent a 0 or a 1. It can be switched off or it can switched on. One or the other.

But a quantum bit is a device of an entirely different kind.

Owing to the bizarre properties that govern the microscopic realm of quantum mechanics, a quantum bit — known as a “qubit” — can represent a 0 and a 1, both of them at the same time. It can be simultaneously off and on.

Known as the uncertainty principle, this seemingly impossible attribute has no equivalent in the world that we humans can see and touch and feel, the domain of automobiles, maple trees, wide-screen TVs, bachelor apartments, cufflinks, pumpkin pie and classical computers.

But it seems to be critical to the nature of atomic and subatomic particles (including electrons, photons, protons, neutrinos and other minuscule dots of nature) that they exist in a haze of possibility rather than in any fixed state.

A microscopic particle can be both here and there at the same instant of time, which means that it can also be in every intermediate location between here and there, also at the same time.

“It turns out that this is incredibly powerful,” says Laflamme. “Just changing an ‘or’ to an ‘and.’”

If you don’t understand how a thing can be in two places at once, don’t worry. Nobody does. Nonetheless, it’s true.

Even though an atom-sized classical bit would be extremely small, it would still be restricted to just two possible states — off and on. By contrast, an atom-sized qubit would possess a near infinity of states, simultaneously.

What this means, by a common calculation, is that a quantum computer consisting of just 300 atoms would possess more sheer calculating power than a conventional machine harnessing every last atom in the universe, yielding an almost unimaginable increase in our ability to solve problems of immense complexity.

Such a machine could perform in an instant certain difficult calculations — for example, the factoring of very large numbers — that the largest conventional computer would need billions of years to figure out, if it could figure them out at all.

It turns out that classical computers are not very good at factoring large numbers, a weakness that has long been exploited by cryptographers to safeguard data on the Internet. It is easy to multiply two prime numbers in order to produce a much larger number, but it turns out to be horrendously difficult to engineer the same process in reverse, to find the two prime divisors of a large number, a process called factoring.

The only way classical computers can address the challenge is by systematic trial and error — trying out two numbers to see if they work, discarding them, trying out two different numbers, and so on. There’s no shortcut.

This defect in conventional computers is used to secure your banking information on the Internet, along with much else. Even armed with powerful computers, would-be hackers still cannot find a way to expose the key — the two original prime numbers used to secure the code that protects your data. The only method available is trial and error, examining every possible combination of divisors, one pair at a time, which could take forever.

By contrast, a quantum computer could crack such privacy barriers in an instant, by the dazzling expedient of testing every possible combination of divisors, not one by one, but all at once, something no conventional computer could do. The right answer would reveal itself almost immediately.

No wonder governments around the world are pouring huge amounts of money into quantum computing. Whoever is first to build a sophisticated quantum machine would suddenly be able to crack just about every secret code in cyberspace.

But that is far from all.

According to Laflamme, quantum computers will eventually ignite a revolution in a variety of fields other than cryptography. These might well include the development of new drugs, or the creation of new superconducting materials, or a range of other innovations currently impossible to predict.

“We are just scratching at the surface of this,” he says. “Today, we are just dipping our big toe in the shallow end.”

At least in a very basic form, quantum computers do now exist, but they are extremely limited both in complexity and capability, restricted to no more than a dozen qubits and able to perform only the simplest of mathematical feats. The highest number so far factored by a quantum device, using an algorithm developed in the 1990s by U.S. scientist Peter Shor, is 21.

This calculation might not seem very impressive — the answer is three and seven, as anybody with a Grade 8 education already knows — but quantum computing is in its infancy.

Laflamme takes a visitor on a tour of the laboratory facilities at IQC’s existing premises — windowless rooms cluttered with an endless variety of complicated machines and devices, pipes and wires, including equipment that fabricates qubit chips from aluminum and niobium. The resulting slivers of metal are about the size of a baby’s fingernail and are extremely difficult to produce.

“Before we make one chip that works, we make 1,000 that don’t,” says Laflamme.

Even the chips that do work aren’t up to much in computational terms.

“If you want to add two plus two, we can do it,” he says. “If you want to add very large numbers, we can’t.”

But the journey is made in stages, and Laflamme believes that a quantum machine able to outpace conventional computers is no longer such a distant prospect.

“The boundary is about 50 qubits,” he says. “When we get there, we’re reaching a place where we’re departing the classical world.”

One big obstacle involves the inherent instability of the quantum universe, a territory where superposition — the ability of particles to occupy multiple locations at once — mysteriously collapses the very instant a human observer interferes with the process in any way, even by looking at a particle through an electron microscope.

Somewhat like a performer struck by stage fright, an observed particle will instantly stop behaving in a quantum fashion and instead adopt just one position or state. Somehow, researchers will have to overcome this phenomenon.

Laflamme, for one, is certain they will.

“In five to 10 years,” he says, “our goal is to get a quantum device to the market.”

UNSW大学

UNSW School of Electrical Engineering and Telecommunications (Dr Andrea Morello and Professor Dzurak), University of Melbourne , University College, London.量子芯片由澳大利亚新南威尔士州立大学研究成功，速度为现有芯片的几十亿倍? 2012-9-21

http://www.sbs.com.au/news/article/1694526/Ultra-fast-processors-around-the-corner

https://newsroom.unsw.edu.au/news/technology/breakthrough-bid-create-first-quantum-computer

Australian researchers have created the world’s first 'quantum bit' -which may lead to the creation of ultra-powerful computers in the future.
They’ve created a single atom - a quantum bit - in a silicon chip.
It’s the first building block for a revolutionary piece of hardware capable of processing information billions of times faster than today’s technology.
Ricardo Goncalves spoke to the people behind the discovery.

Breakthrough in bid to create first quantum computer
20 September 2012
A research team led by Australian engineers has created the first working quantum bit based on a single atom in silicon, opening the way to ultra-powerful quantum computers of the future.

In a landmark paper published today in the journal Nature, the team describes how it was able to both read and write information using the spin, or magnetic orientation, of an electron bound to a single phosphorus atom embedded in a silicon chip.

“For the first time, we have demonstrated the ability to represent and manipulate data on the spin to form a quantum bit, or ‘qubit’, the basic unit of data for a quantum computer,” says Scientia Professor Andrew Dzurak. “This really is the key advance towards realising a silicon quantum computer based on single atoms.”

Dr Andrea Morello and Professor Dzurak from the UNSW School of Electrical Engineering and Telecommunications led the team, which includes researchers from the University of Melbourne and University College, London.

“This is a remarkable scientific achievement – governing nature at its most fundamental level – and has profound implications for quantum computing,” says Dzurak.

Dr Morello says that quantum computers promise to solve complex problems that are currently impossible on even the world’s largest supercomputers: “These include data-intensive problems, such as cracking modern encryption codes, searching databases, and modelling biological molecules and drugs.”

The new finding follows a 2010 study also published in Nature, in which the same UNSW group demonstrated the ability to read the state of an electron’s spin. Discovering how to write the spin state now completes the two-stage process required to operate a quantum bit.

The new result was achieved by using a microwave field to gain unprecedented control over an electron bound to a single phosphorous atom, which was implanted next to a specially-designed silicon transistor. Professor David Jamieson, of the University of Melbourne’s School of Physics, led the team that precisely implanted the phosphorous atom into the silicon device.

UNSW PhD student Jarryd Pla, the lead author on the paper, says: “We have been able to isolate, measure and control an electron belonging to a single atom, all using a device that was made in a very similar way to everyday silicon computer chips.”

As Dr Morello notes: “This is the quantum equivalent of typing a number on your keyboard. This has never been done before in silicon, a material that offers the advantage of being well understood scientifically and more easily adopted by industry. Our technology is fundamentally the same as is already being used in countless everyday electronic devices, and that’s a trillion-dollar industry.”

The team’s next goal is to combine pairs of quantum bits to create a two-qubit logic gate – the basic processing unit of a quantum computer.

Morello and Dzurak are team leaders at the ARC Centre of Excellence for Quantum Computation and Communication Technology. Quantum bit devices were constructed at UNSW, the Australian National Fabrication Facility and University of Melbourne. Research funders: Australian Research Council; US Army Research Office; NSW Government; UNSW; University of Melbourne.

Media contacts:? Andrea Morello a.morello@unsw.edu.au 0422 543 261 |? Andrew Dzurak? a.dzurak@unsw.edu.au 0432 405 434 |? UNSW media: Myles Gough? myles.gough@unsw.edu.au 0420 652 825

For a full backgrounder, with high-res images and a detailed Q&A, visit this website.
Video: Animation and video overlay are also available, please contact Brad Hall from UNSWTV, 02 9385 3673

University of Wisconsin

Chip design aims for quantum leap

By Eric Smalley, Technology Research News

The first step toward making phenomenally powerful quantum computers is capturing and manipulating individual subatomic particles, which is a bit like getting a fly to venture onto your desk, then perform tricks like "sit up" and "roll over" on command.

The second step is harnessing, controlling and coordinating thousands or millions of particles at once. Making a practical quantum computer also means doing this using ordinary electronics rather than exotic laboratory equipment.

University of Wisconsin researchers are tackling these issues with a quantum computer design that would incorporate thousands of individually-controlled electrons into a silicon chip that could be made much the same way as today's computer chips.

Practical quantum computers would be many orders of magnitude faster than today's computers for problems that involve massive amounts of data, like cracking secret codes and searching large databases.

The researchers' idea is to "trap single electrons in tiny silicon sandwiches about a millionth of an inch across," said Robert Joynt, a physics professor at the University of Wisconsin at Madison. The silicon sandwiches are quantum dots, microscopic specks of semiconductor material that can hold one or a few electrons.

These dots can represent bits of information because an electron acts like a tiny spinning top, and depending on which way it is spinning it can represent a 1 or a 0. Conventional computers use the presence or absence of electric current running through transistors to indicate the 1s and 0s of digital information.

Proposals for making quantum computers out of quantum dots have been around for several years. The Wisconsin researchers' design plots out some of the difficult details -- it allows individual electrons to be loaded into the quantum dots and allows interactions between electrons held in neighboring dots is to be closely controlled.

Each dot would consist of a bottom layer of silicon germanium that has been chemically altered to allow electrons to flow more easily. This layer would serve as a reservoir of electrons.

The middle layers would consist of an extremely thin layer of silicon sandwiched between layers of unaltered silicon germanium. The silicon layer would hold the individual electron used by the quantum computer, and the silicon germanium layers would act as barriers to keep additional electrons out. The researchers could coax individual electrons to tunnel through the barriers to the silicon layer by changing the electrical current running through the chip.

Metal electrodes that move the electrons laterally would form the chip's top layer. The electrodes would be used to bring pairs of electrons in adjacent dots together to perform the basic logic operations of computing. The quantum interactions of a pair of electrons can be represented mathematically, and that math can be used to generate the binary logic that is the foundation of computing. This allows logic operations like adding binary numbers to be carried out by controlling the electron interactions.

"The biggest hurdle is fabrication," said Joynt. "This needs to be done with exquisite control of the quality of the material and to very high measurement specs," he said.

Because the quantum dots are made from layers of metal and semiconductors, like computer chips, the researchers' proposed device could be built using standard chipmaking processes, according to Joynt. "The dots are only slightly smaller than the features on commercial chips, which have millions of transistors," he said.

Unless the optical lithography used in the commercial chip industry improves, however, this minor decrease in size means that the researchers will have to use electron beam lithography, said Joynt. "This is slower and more expensive, but perhaps not prohibitively so," he said.

Today's optical lithography uses ultraviolet light with wavelengths ranging from 200 to 300 nanometers and can etch features as small as 130 nanometers. Electron beams can be focused with magnetic fields to around 10 nanometers and so can etch much smaller features.

The potential benefits of a practical quantum computer are enormous.

"Quantum computing is massively parallel," said Joynt. This means that many inputs can be processed at the same time, which makes for a computer that can solve problems that would take a regular computer "essentially forever" to work out, he said.

When an electron is isolated from its environment it is in the weird quantum state of superposition, meaning it is spinning in both directions at once. An electron in superposition can represent a mix of 1 and 0, and a string of electrons in superposition can represent every combination of 1s and 0s at the same time.

The power of a quantum computer comes from the ability to check every possible combination of numbers at once to find the answer to a problem that can have more possibilities than there are atoms in the universe. Ordinary computers have to check each possible answer one at a time.

Researchers have already come up with software that would allow quantum computers to crack secret codes and search massive databases.

The Wisconsin work is a good effort that adds "many realistic details" to quantum dot research, said IBM Research physicist David DiVincenzo. DiVincenzo and Daniel Loss, a physics professor at University of Basel in Switzerland, developed an earlier quantum dot quantum computer proposal.

"I am very encouraged generally by the efforts of the University of Wisconsin group," said DiVincenzo. "They have started a big, integrated effort involving both theory and experiment," he said.

Practical quantum computers are likely to take 25 years to develop, said Joynt. "And I'm an optimist," he said. "We are working on fabricating a prototype, step by step," he added. "The next step is to make sure that our [silicon layer] is properly trapping the electrons."

Joynt's research colleagues were Mark Friesen, Paul Rugheimer, Donald Savage, Max Lagally, Daniel van der Weide and Mark Eriksson. They published the research in the July 15, 2002 issue of the journal Physical Review B. The research was funded by the U.S. Army Research Office (ARO) and the National Science Foundation (NSF).

Timeline:?? 25 years
Funding:?? Government
TRN Categories:?? Quantum Computing and Communications
Story Type:?? News
Related Elements:? Technical paper, "Design and proof of concept for silicon-based quantum dot quantum bits," posted on the arXiv physics preprint archive at arXiv.org/abs/cond-mat/0204035; Technical paper, "Decoherence of electron spin qubits in Si-based quantum computers," Physical Review B, July 15, 2002

University of Science and Technology of China中国科技大学

中科院量子信息重点实验室郭国平半导体量子芯片研究组/砷化镓量子芯片

中科大研究团队又破半导体量子芯片世界纪录 2013年02月06日

从中国科技大学获悉，中科院量子信息重点实验室郭国平教授半导体量子芯片研究组及其合作者又破世界纪录，通过实验成功实现世界上最快速量子逻辑门操作，取得半导体量子芯片研究的重要突破。

郭国平教授介绍，研究组从可大规模集成化的半导体单电子晶体管的设计制备出发，在砷化镓铝异质结中制备出一种集成了双路量子探测通道的栅型双量子点复合结构，并且通过调节加载在栅电极上电秒冲的高度和宽度，成功实现了世界上最快速的皮秒量级单比特超快普适电控量子逻辑门，比国际上公开报道的电控半导体逻辑门的运算速度提高近两个数量级，相关研究成果发表在最新一期权威学术期刊《自然通讯》上。

更快和更大规模的集成始终是芯片技术的核心梦想。郭国平教授说，更快的量子逻辑门操作，才有可能将量子计算从小规模的实验室演示推向真正的实用化。

China makes breakthrough on quantum computer
(People's Daily Online)
16:45, February 07, 2013

The solid-state quantum research crew from the University of Science and Technology of China succeeded in performing the quantum logic gate operation on one single electron at 10 picoseconds, renewing the previous world records by nearly 100 times, making a big step toward the semiconductor-based “quantum computer”.

It is inferable from the Moore's Law that around 2020, each transistor might be as small as an electron, also known as single-electron transistor. According to Guo Guoping, director of the research project, the information representation with “0” and “1” in the computer information processing is achieved by switch closure. Once the tunneling occurs as the transistor becomes increasingly smaller, the electron will go directly through the transistor and be uncontrollable by the switch closure.

The world’s major computer chip manufacturers are still trying to avoid tunneling. But in the opinion of Guo, it is wiser to utilize than avoid in the long term, advancing the use of “quantum computing” to represent the information “0” and “1” with the horizontal and vertical properties of one single electron.

“Any complicated computer operation is achieved by arithmetic operations of single and two bits, just like the building of houses in round and square bricks.

“The research achievement is a breakthrough in the single-bit operational speed, representing the elements of ‘0’ and ‘1’ with one single electron at 10 picoseconds,” said Guo.

Previously, the U.S. and Japanese research institutes achieved the electrically controlled semiconductor logic gate at 1,000 picoseconds. The achievement by Guo and his colleagues increases the operational speed by almost 100 times to 10 picoseconds, making a significant step in promoting the quantum computing from laboratory demonstration to practical use. The Nature Communications, a branch of the academic journal Nature, has published the achievement in its entirety recently.

Guo said that China has launched the solid-state quantum chip project in efforts to gain a foothold in the global competition in the next-generation computer chips. Once the quantum chip is introduced to the computer, it will make the quantum computer characterized by exponentially increased operational speed and greatly improved data processing capabilities.

Integrated photonic qubit quantum computing on a superconducting chip

Lianghui Du, Yong Hu, Zheng-Wei Zhou, Guang-Can Guo and Xingxiang Zhou

Key Laboratory of Quantum Information, University of Science and Technology of China, Chinese Academy of Sciences, Hefei 230026, People's Republic of China

We study a quantum computing system using microwave photons in transmission line resonators on a superconducting chip as qubits. We show that linear optics and other controls necessary for quantum computing can be implemented by coupling to Josephson devices on the same chip. By taking advantage of the strong nonlinearities in Josephson junctions, photonic qubit interactions can be realized. We analyze the gate error rate to demonstrate that our scheme is realistic even for Josephson devices with limited decoherence times. As a conceptually innovative solution based on existing technologies, our scheme provides an integrated and scalable approach to the next key milestone for photonic qubit quantum computing.

GENERAL SCIENTIFIC SUMMARY

Introduction and background. Photons have long been recognized as an attractive candidate for qubits because of their strong quantum coherence. However, the long-term prospect of photonic quantum computers is undermined by some inconvenient facts; photons do not interact easily, and optical systems based on bulk optical devices on an optical table are hard to miniaturize and scale. Without overcoming these difficulties, it would be unfeasible to construct a large-scale photonic quantum computer capable of solving problems of practical significance.

Main results.

We offer an unconventional and innovative solution to these major difficulties in photonic quantum computing. We use the microwave photons in a transmission line on a superconducting chip as qubits. They are manipulated by Josephson devices fabricated on the same chip, which play the role of optical devices. By taking advantage of the strong nonlinearity in Josephson junctions, photon interactions can also be induced. With Josephson-device-based photon generators and detectors on the same chip, we realize a fully integrated photonic quantum computing system on a single chip, as shown in the figure. It is demonstrated that high-fidelity quantum gates can be implemented, making our system a scalable and reliable photonic quantum computer on a chip.

Wider implications.

Our Josephson-device-based 'photonic quantum computer on a chip' is a realistic and attractive system, realized with mature integrated circuit technologies. It can also be used as a platform to study quantum optics problems in an integrated system.


Untitled Document

Quantum Switching

Multicast Quantum Switching [Kuo2002]

Quantum Switching? [Kuo2002]

Unicast Quantum Switching [Kuo2002]


Untitled Document

quantum Turing machine

multidimensional quantum Turing machine [Volovich1997]

quantum Turing machine (QTM) [Volovich1997]
quantum Turing machine (QTM) is obtained by quantization of a classical Turing machine (TM),


Basic Chip Technology

chip_techsall.docx

Chip/VLSI Technology Development Trends

芯片技术发展趋势
  • Inductive effects will become increasingly important
  • Additional metal patterns or ground planes for inductive shielding
  • Thinner metallization
  • Lower line-to-line capacitance
  • Increasing pitch and thickness at each conductor level to alleviate the impact of interconnect delay

nano-CMOS technology

nano-CMOS microchips

nano-CMOS downsizing and manufacturing

nano-CMOS IC fabrication

Integrated Optics

system-on-chip (SOC)

System-on-Chip design methodology. Block-level chip design (using cores, IP blocks)

silicon on insulator (SOI)

silicon-on-insulator

3D晶体管

three-dimensional structure

three-dimensional (3D) structure, such as fin-FET or DG-FET Tri-gate -FET

system-in-package

chip-embedded-chip

asynchronous circuit design

Integrating analog circuits on large digital chips

神经网络芯片

射频芯片与数字芯片的单片全集成

在集成电路封装方面，传统的扁平封装已经不能满足对于系统高集成度的要求，3D封装、SOP等也都是目前新颖的封装技术之一。

=============================

Carbon Nano Tube 碳纳米管芯片

Quantum Chips

Plasmonics

石墨烯芯片

铟芯片

砷芯片

镓芯片

自旋电子芯片 电子的自旋 自旋电子电路

相变存储技术

Microchip

多核应用处理芯片

多集成单芯片

Polycell

System-level synthesis, MEMS design tools. Mixed-signal design tools.

Hardware-Software Codesign

interconnect delay due to the increase in the resistance and the capacitance values of narrow and dense interconnection metal lines

elevated source/drain

plasma doping with flash or laser annealing

NiSi silicide

strained Si channel for mobility enhancement

high dielectric constant (high-k) gate insulator

metal gate

low dielectric constant (low-k) interlayer insulator for interconnects

parallel processing architecture

dual Vt transistors

Chip Technology

Chips, Processors, VLSIs, Microcontrollers etc

  • Processor architecture
  • Chip, Processors, VLSI

Chips芯片
芯片

国内有多少芯片设计企业

Chips

芯片技术

Chip technology

电脑芯片

Computer chips

微芯片

Microchip

移动芯片

基带及射频芯片

多频多模芯片

六模基带芯片

多模基带芯片

64位ARMv8指令集的芯片

应用处理芯片

多核应用处理芯片

多集成单芯片

Polycell

芯片设计

Chip design

Chip designer

Chip foundry

Chip manufacturer

Processors微处理器

微处理器

Microprocessor

multi-core processors

The terms CPU, microprocessor (μP)? and MPU (microprocessor unit)

Thumb? instruction set based on Thumb-2 technology

SCARCE RISC processor framework

VLSI

集成电路

集成电路

IC

SSI

MSI

大规模集成电路

Large scale integration? LSI

超大规模集成电路

Very large scale integration? VLSI

ULSI

– Ultra Large Scale Integration

GSI

Giga Scale Integration Gigantic Scale Integration

?WSI

– Wafer Scale Integration

ASIC

– Application-Specific IC

集成电路设计

IC design

集成电路IP技术

集成电路的主要工艺技术，如：热扩散掺杂、离子注入、化学气相淀积、光刻、金属化等；

集成电路的常用测试方法，如：设计错误测试、功能测试、圆片测试等；

集成电路的封装工艺及要求，如封装对散热性能的影响；

PM、PLL、ADC/DAC、RF等各种模拟电路

加密芯片
加密芯片设计

密码芯片
密码芯片设计

保密芯片
保密芯片设计

电话加密芯片
传真加密芯片
手机加密芯片
网络加密芯片
电脑加密芯片
复印机加密芯片
扫描仪加密芯片
所有信息产生，加工，传输，处理，存储等设备的加密芯片
@@@@@@@@@@@@@@@@@@@@@@@@@@@@

Encryption chip
google
encrypted chip
Encrypting chip
Clipper Chip
Cipher chip
Ciphering chip
Cryptographic chip
Crypto chip

Literature

ARM Limited: ARM926EJ-S (r0p4/r0p5) Technical Reference Manual, 2001-2003, p248?

ARM Limited: ARM Developer Suite, Version 1.2, Developer Guide, 1999-2001 .k

ARM Limited: ARM Developer Suite, Version 1.0.1, Tools Guide, 1999,2000

ARM Cortex M4 Devices, Generic User Guide, 2010, p276?

ARM: Cortex?-M4 Devices, Generic User Guide, 2010 .

ARM Limited: Cortex?-A8 Revision: r3p2 Technical Reference Manual, 2006-2009, p764.

ARM Cortex?-A Series Version: 3.0 Programmer’s Guide, 2011, 2012, p451

Hedlund, Kye Sherrick: Wafer Scale Integration of Parallel Processors p245 1981

Sloss, Andrew N. et al: ARM System Developer’s Guide, Designing and Optimizing System Software, Elsevier Inc., 2004 ????.p703

Chip Architectures

Processor Architecture 处理器总线架构

Harvard Architecture

Princeton Architecture

基于Silvermont微架构的SoC芯片多数冠以Atom品牌

AtomCPU架构

AMBA总线AMBA AHB/AXI总线协议

AMBA总线结构

Advanced Microprocessor Bus Architecture (AMBA)

Advanced Extensible Interface (AXI)

ARM

MIPS

X86

ARM AMBA? 3 APB Protocol v1.0 Specification 2004 p34 .

ARM Limited AMBA AXI Protocol v1.0 Specification 2004 p108 ..............

ARM Limited: ARM Architecture Reference Manual, 1996-1998, 2000, 2004, 2005

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition, 1996-1998, 2000, 2004-2012, p2734...........

ARM Architecture Reference Manual ARMv8 for ARMv8-A architecture profile Errata markup, 2013, p5158............

ARM Limited AMBA AXI Protocol v1.0 Specification 2004 p108

ARM Limited: ARM Architecture Reference Manual, 1996-1998, 2000, 2004, 2005, p1138............

ARM Limited: ARMv7-M Architecture Application Level Reference Manual, 2006, p534 ???????????

ARM Limited: ARMv7-M Architecture Reference Manual, 2006-2010, p716 ........................... 39

Math, Shaila S and Manjula, R B: Design of AMBA AXI4 protocol for System-on-Chip communication p5 International Journal of Communication Network and Security (IJCNS), Vol-1, Issue-3 ISSN: 2231-1882

Perlmutter, Dadi: Introducing Next Generation Low Power Microarchitecture: Silvermont p38 April 2013

Usha, Kalluri and Kumar, T.Ashok: Axi To Apb Interface Design Using Verilog p9 IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 8, Issue 5 (Nov. - Dec. 2013), PP 01-09

XILINX AXI Reference Guide p120 UG761 (v13.4) January 18, 2012

Yeh, Yuan-Hau and Lee, Chen-Yi: Cost-Effective VLSI Architectures and Buffer Size Optimization for Full-Search Block Matching Algorithms IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 3, SEPTEMBER 1999 p345-359.

(Chip) Assembly Languages

Assembly Language General

===============================

ARM Instruction Sets

===============================

Intel Assembly

========================

DSP Assembly DSP汇编编程

ARM Limited: ARM Developer Suite, Version 1.2, Assembler Guide, 2000, 2001, p354??k

ARM Limited: ARM Developer Suite, Version 1.2, Developer Guide, 1999-2001, p226

Blum, Richard: Professional Assembly Language, Wiley Publishing, 2005, p577

Brey, BARRY B.: The Intel Microprocessors Architecture Programming and Interfacing, Fourth Edition, Prentice-Hall, 1997, p920?????????

Hyde, Randall: The Art of Assembly Language, 2001, p1566 ????????? 158

@@@@@@@@@@@@@@@@@@@

INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986, Edited 2001-02-01, p421???????? ???????????70

Intel 8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1981, p222 ??????????

Intel Intel? StrongARM? SA-1100 Microprocessor Developer’s Manual, August 1999 p388??????????????? 115

IRVINE, Kip R: Assembly Language for x86 Processors, Sixth Edition, Pearson Education, Inc.,2011, p747???????????????????????????? 74

Kauler, Barry: WINDOWS ASSEMBLY LANGUAGE SYSTEMS PROGRAMMING, 1997, ? p421?..............?? 92

STMicroelectronics, PM0214 Programming manual STM32F4xxx Cortex-M4 programming manual, July 2012, p243 .

Texas Instrument, ARM Assembly Language Tools v4.9 User's Guide, p336, August 2011

===============================

芯片编程

Chip programming

软件程序的编制 -->软件程序的 仿真à烧到单片机芯片中去

芯片编程器/芯片烧录器/芯片编程机器人/芯片编程软件

芯片编程器
Chip Programmer

芯片烧录器
Chip burner

编程器烧写芯片

芯片编程机器人
Chip programming robots
Chip Programmer robot

芯片编程软件
Chip Programmer software

支持5类器件的编程：

  • E（E）PROM
  • BPROM
  • DRAM/SRAM???
  • PLD/EPLD???
  • MPU/MCU

芯片是PAL或GAL

http://www.bios.net.cn/

http://www.bios.net.cn/BIOSJS/xinpianzhishi/858.html

http://www.biosdiy.cn

http://www.biosdiy.cn/bbs/Show.asp?ID=52&BoardID=8&TB=1

http://www.ce.org

http://www.ce.org/Consumer-Info/CE-Cares/V-chip-Technology.aspx

http://www.chaoyue360.net/Product/xinpian/

http://www.china-ecu.com/product_view.asp?id=464

http://blog.chinabyte.com/archives/2912761

http://hc.chinaocs.com/others/projects!show?id=609

http://www.chinesechip.com/

http://www.chinesechip.com/chip/class_20_113.html

http://www.cppblog.com/

http://www.cppblog.com/stuos/archive/2005/10/20/744.html

http://www.daniweb.com/

http://www.daniweb.com/community-center/threads/51868/chip-programming

http://www.elecfans.com/

http://www.elecfans.com/tags/%E8%8A%AF%E7%89%87%E7%BC%96%E7%A8%8B/

http://www.autoelectric.cn/

http://auto2013.gotoip2.com/MiniPro/MinProVehicle.htm

http://wenku.it168.com/d_000823822.shtml

http://www.mcufan.com/

http://www.mcufan.com/article/picbianchengqi.htm

http://www.microchipdirect.com/

http://www.microchipdirect.com/programming/

http://microcontrollershop.com/

http://microcontrollershop.com/default.php?

cPath=92&sort=1a&page=2&gclid=CJ-poK2Ju7sCFRFgfgod3D0A9Q

www.pcbpc.org

http://bios.vip.sina.com/

http://bios.vip.sina.com/eeprom/bios7.htm

http://www.xcar360.com/ecu-chip-programmer.html

Advanced, Non-Si Chip Technologies (quantum/photonic, atomic, bio/DNA etc)

Advanced chip technologies being coming up now (quantum/photonic, atomic, biotic/DNA etc)

Bio/DNA

Biochips 蛋白质芯片 生物芯片

Biochips

DNA biochips

DNA chips

DNA Microarray

Proteain biochips

Digital Microfluidic Biochip

pin-constrained design of biochips

蛋白质芯片

生物芯片

DNA芯片

基因芯片

Yuh, Ping-Hung et al: BioRoute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips, 2007

Yuh, Ping-Hung et al: BioRoute A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips, 1-4244-1382-6/07, 2007 IEEE, p6 (page 752-758)?? ???

Carbon Nano Tube

碳纳米管芯片

interconnect solution: carbon nanotubes

Integrated Optics since 1969 (S. E. Miller’s proposal in the 1969 Bell Systems Technical
Journal)

Quantum Chips, Quantum Computing

Quantum and reversible computation

量子芯片

砷化镓量子芯片

量子芯片技术

D-Wave处理器

Quantum chip

quantum computing chip

quantum relay chip

integrated optical circuit on lithium niobate

量子计算

量子计算机

quantum computing

Google???

quantum computer

quantum communication

quantum cryptography

quantum information technology.

Black, Paul E.: Quantum Computing and Communication, 2011 ??????????????? 15

Chen, Goong: Quantum Dot Computing Gates, 2009-12-12 ????????? 8

==============================

Charemza, Michal: An Introduction to Quantum Computing, March 2005 ????????????? 11

Chung, Wook Jin et al: QCA Physical Design With Crossing Minimization, Proceedings of 2005 5th IEEE Conference on Nanotechnology Nagoya, Japan, July 2005, 0-7803-9199-3/05/ 2005 IEEE, p4

Coudert, Olivier: Chapter 7, LOGICAL AND PHYSICAL DESIGN: A FLOW PERSPECTIVE, May 2011

de Wolf, Ronald: Quantum Computing: Lecture Notes, Feb-May 2011

Edalat, Abbas: Quantum Computing, 2009 ?????????? ??????18

Wolf Quantum Computing p112???????????? 9

Atom Chips

Atom chip technology today is rapidly gaining popularity as a convenient and powerful approach to achieving precise control over an atom’s motion and internal state.

Atom optics - Control and manipulation of atomic deBroglie waves

Alloschery, O. ; Weiner J. and Mathevet, R.: further experimentations on all optical atom chips 2008 Optical Society of America p11

Armijo, J. et al: Thermal properties of AlN-based atom chips European Physical Journal D 56 (2009) 33 p7

Bigelow, N. P. et al: NIRT: Next Generation Atom Chips for Quantum Information Technology p3 NSF Nanoscale Science and Engineering Grantees Conference, Dec 16-18, 2003

Bouchoule I. et al: Atom chips and one-dimensional Bose gases p34 January 26, 2009

Extavour, Marcius H.T. et al: Fermions on Atom Chips p30 .

Fortier, K. et al: Atom Chips at Sandia p1 .

Hinds, E.A.: Cold atoms in microscopic traps p59 19 August 2004

Kruger, Peter: Atom chips for quantum technologies March 2013 p9

Ong, Congwen: Development and fabrication of single and multilayer atom chips for applications in atomic physics p87 July 2011

Schmiedmayer, J?rg: Atom Chips for Quantum Information Processing 2001 p28

Schmiedmayer, J?rg: Atom Chips Mesoscopic physics with Ulta-cold Atoms 1d traps coherent splitting of matter waves 2002 p35................ok

Schwindt, Peter D. D.: Magnetic Traps and Guides for Bose-Einstein Condensates on an Atom Chip: Progress toward a Coherent Atom Waveguide Beamsplitter p155 2003

Vale, Chris: Atom Chips and Bose-Einstein Condensates Dec 2004 p34

Volk M et al: Scanning magnetoresistance microscopy of atom chips, REVIEW OF SCIENTIFIC INSTRUMENTS 79, 023702 2008, p7

Plasmonics

surface plasmon-polaritons (SPPs)

Atwater, Harry A.: The Promise of PLASMONICS 2007 SCIENTIFIC AMERICAN p8

Fang, Nick: Plasmonics-Metamaterials p37 2009

Maier, Stefan: Plasmonics - Merging Photonics with Nanotechnology p38 ASEPS 2013, Chiba

Ozbay, Ekmel: Plasmonics: Merging Photonics and Electronics at Nanoscale Dimensions p5

Qiu, Min: Basics of plasmonics p38 March 2010

石墨烯芯片

铟芯片

砷芯片

镓芯片

自旋电子芯片

  • 电子的自旋
  • 自旋电子电路

相变存储技术

Basic Technologies

Electronics/Circuits

Electrical Engineering 电工

电工

电工技术

电工原理

principles of electric engineering

Circuits

电路

Electrical circuit

模拟电路

analog electronics

数字电路

Digital circuit

电子电路

Electronic circuit

电路技术

电路设计

Circuit Design

Digital Circuit Design

Electrical engineering, Electric circuits

Agarwal, Anant: Foundations of Analog and Digital Electronic Circuits, Elsevier 2005

Bird, John: Electrical and Electronic Principles and Technology p422, Third edition, Elsevier, 2007

Kuphaldt, Tony R.: Lessons In Electric Circuits, Volume IV–Digital p517, November 01, 2007?

Pettit, Joseph Mayo: Electronic amplifiers circuits - theory and design, McGraw-Hill, 1961, p340

Rizzoni Principles and Applications of Electrical Engineering p1013,? 2004?

Microelectronics

微电子技术

MOS, Transistors

Transistor

晶体管

transistor

场效应管（MOS管）

Metal-Oxide-Semiconductor (MOS) Devices:

绝缘栅型场效应管（MOS管）

CMOS

CMOS电路制造的工艺流程，如：N阱区光刻、N阱离子注入、Si3N4层淀积等；

http://cmosedu.com/cmos1/book.htm

场效应晶体管

CMOS

BICMOS

BIPOLAR

Bipolar Transistors:

MOSFET

增强型PMOS、NMOS

耗尽型PMOS、NMOS

MOSFET transistors

Discrete power MOSFETs

bipolar power junction transistors (BJTs)

Junction Field Effective Transistor (JFET):

结型场效应管

IGFET insulated-gate field-effect transistor

MISFET? metal–insulator–semiconductor FET

BCD基本器件结构

ECE-V-FUNDAMENTALS OF CMOS VLSI p214????????????

Lin Dalton: Bipolar Junction Transistors (BJTs) p119 2005

Sabar Chapter 1-Bipolar junction transistor (BJT) p78?

Others

Cryptochip

Fluiddynamics of Chips

Solar Technology and Chips

Thermodynamics and Chips

Lakhssassi, Ahmed and Bougataya, Mohammed: VLSI thermal analysis and monitoring p18 2009

Math for Chip Design >>> Chip Technologies >>> Other Chip Processes

Chip Research & Development

Physico-Mathematical Modeling
  1. Microscopic models
    1. Boltzmann-Poisson
    2. Wigner-Poisson model
  2. Macroscopic models
    1. energy transport
    2. hydrodynamic
    3. drift diffusion (DD) model

Numerical Simulation

Chip Fabrication

Fabrication:

After layout and verification, the design is ready for fabrication (called tapeout). Layout data is converted into photo-lithographic masks.

Two common formats for mask descriptions are the Caltech Interchange Format (CIF) (mainly used in academia) and the Calma GDS II Stream Format (GDS) (used in industry).

Crystal Growth, Wafer Preparation, Epitaxy and Oxidation

Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing consideration, Vapor phase Epitaxy, Molecular Beam Epitaxy, Epitaxial Evaluation, Growth Mechanism and kinetics, Thin Oxides, Oxidation Techniques and Systems, Oxide properties, Redistribution of Dopants at interface, Oxidation of Poly Silicon, Oxidation induced Defects.

Lithography and Reactive Plasma Etching

Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Nano imprint Lithography, Plasma properties, Feature Size control and Anisotropic Etch mechanism, reactive Plasma Etching techniques

Deposition, Diffusion and Ion Implantation

Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids, Fick’s one dimensional Diffusion Equation - Measurement techniques - Range theory- Implant equipment – Annealing- Shallow junction, High - energy implantation.

Metallization and VLSI Process Integration

Physical Vapour Deposition (PVD) –Patterning- NMOS IC Technology – CMOS IC Technology – BICMOS IC Technology- MOS Memory IC technology - Bipolar IC Technology –Silicon on Insulator Technology–Noise in VLSI Technologies

Literature

Baravelli, Emanuele: Introductionto VLSI Fabrication Technologies p27 Sept 2005

Groover, M. P. : Fundamentals of Modern Manufacturing 2/e, 2002 John Wiley & Sons, Inc. p89

SECTION2 BASIC INTEGRATED CIRCUIT MANUFACTURING Reference Manual Sept 1997 p110

Chip Packaging
Analytical, Assembly Techniques and Packaging of VLSI Devices

Analytical Beams – Beams Specimen interactions - Chemical methods – Package types – packaging design consideration – VLSI assembly technology – Package fabrication technology.

Packaging styles

  • WSI
  • MCM
  • PCB

Package Physical Design

ISQED’05 9

Typical Package Design Cycle

Package/Substrate Architecture Exploration

(start ~4/5 months before Tapeout)

Defining Interfaces, Signals,

PLL, Power, Clock, # pins, # IOs

Manufacturing and NRE Costs;

Die, Substrate, Package

Floorplanning of IO/Pad/Pins;

Define Netlist hierarchy/manipulations

Pad/package Iteration: P&R of IO/Pad cells,

Pins; Pwr/gnd and inter-cell connections;

PCB pin locations (x,y);

Package/Pad/IO Rule checking (PRC):

SI, timing, clocks, IO voltages,

assembly rules, special regions

Verify user specified requirements and rules;

PCB pins, Power grid, # VSS/VDD,

decoupling caps, EMI, ESD, Vias

Finalize IOs/Pads/Pins;

Package Tapeout

Package Modeling

Package Simulation

Literature

Dragan, Feodor F. et al: Practical Approximation Algorithms for Separable Packing Linear Programs p13 June 2001.????????

Fang, Jia-Wei and Chang, Yao-Wen: A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007, p13 (page 1417-1430)

Minz, Jacob and Lim, Sung Kyu: Channel and Pin Assignment for Three Dimensional Packaging Routing p6 1999

OZDAL, MUHAMMET MUSTAFA: Routing Algorithms for High-Performance VLSI Packaging p169 2005

Chip Testing

Genetic Algorithm for VLSI Testing

Testing and Debugging:

 After fabrication, each die is tested.
 The wafer is diced into individual chips.
 Each chip is packaged and tested.

Literature
Wang, Laung-Terng; Wu, Cheng-Wen and Wen, Xiaoqing: VLSI Test Principles and Architectures: Design for Testability, Elsevier, 2006, p809

Chip Simulation

Logic simulation

Postlayout simulation

Runtime simulation

Chip Operation


Math for Chip Design

Methodologies | Contents | Flow | Specifications | Architectural | Functional | Logic
Circuit | Physical | Simulation | Verification | EDA | MISC | -

design
├<doc_general>
│ ├benchmark_chip.docx
│ ├chip_design.docx
│ ├chip_design_physical.docx
│ └VLSI Design.docx
└<doc_routing>
└chip_design_routing.docx

General

The design of VLSI chips is a multi-objective design optimization problem.

Design technology (DT) comprises algorithms, software and hardware tools, and design methodologies (manifest as design flows) that are used for the efficient conception, implementation, verification, and testing of microelectronics- based systems. Aspects of design technology have been referred to as electronic computer-aided design (ECAD), electronic design automation (EDA), and high-level design automation (HLDA). Without design technology, it would be impossible to implement, verify, and test the complex, single-chip electronic systems that are the foundation of today’s information technology revolution. It is through design technology that the ideas and objectives of the electronic systems designer are transformed into reality; the quality of the design tools and associated methodologies determine the design time, performance, cost, and correctness of the final system product.

One unpopular approach is flat device-level layout synthesis where the entire design is
created in a single step by working in a component by component fashion.

The inherent complexity is addressed by another approach — a hierarchical design process where a higher process can work by placing components treated as black-boxes. These black-boxes are designed by another design process that works with components at a lower level of abstraction. Thus there are various design processes each working at a different level of abstraction. Some of the names associated with these processes are circuit partitioning, cell placement, cell routing, compaction etc. Each process depends on the other and a process at one level may not have complete information about components at a lower level and hence cannot use it in its cost function and has to make approximations.

Math for Chips

Math and Chips

Math and Chips design

Math and Chips industry

Chip Mathematics

Design flows have been characterized by a clear separation between the logical and the physical domains. More details click the left links.

New Trends in VLSI Design Cycles

  • Increased interconnect delay: interconnect not scaling at the same pace as the device.
  • Increasing interconnect area: Upto 40 % of the area devoted to interconnect.
  • Increasing number of metal layers: Upto 5 layers for microprocessors.
  • Increasing planning requirements: Physical design early on in the design cycle.
  • Automated synthesis: Logic and high-level.

Literature

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??????????????????????

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000Berlier A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms p341.pdf
000Bhatnagar ADVANCED ASIC CHIP SYNTHESIS p341.pdf
Al-Wattar Efficient Scheduling,Mapping and Resource Prediction for Dynamic Run time Operating Systems p272.pdf
Allen CMOS Analog Circuit Design-1 p477.pdf
Alsolaim DYNAMICALLY RECONFIGURABLE ARCHITECTURE FOR THIRD GENERATION MOBILE SYSTEMS p327.pdf
Baker CMOS Circuit Design Layout and Simulation 3rdEdition p1214.pdf
Banerjee Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198.pdf
Benini NETWORKS ON CHIPS TECHNOLOGY AND TOOLS p404.pdf
Blackledge DIGITAL SIGNAL PROCESSING p839.pdf
Browy A TOP-DOWN APPROACH TO IC DESIGN INTEGRATED CIRCUIT DESIGN METHODOLOGY GUIDE p369.pdf
Cai ROUTING CHANNELS IN VLSI LAYOUT p143.pdf
Cardoso ARC2005 INTERNATIONAL WORKSHOP ON APPLIED RECONFIGURABLE COMPUTING 2005 p190.pdf
Chanak NETLIST PROCESSING FOR CUSTOM VLSI VIA PATTERN MATCHING p105.pdf
Chen INNER-PRODUCT BASED SIGNAL PROCESSING ALGORITHMS AND VLSI IMPLEMENTATION p142.pdf
DICKSON Global Routing in VLSI Algorithms, Theory, and Computation p76.pdf
De Micheli Synthesis And Optimization Of Digital Circuits p586.pdf
DeHon Reconfigurable Architectures for General-Purpose Computing p368.pdf
Dittmann Methods to Exploit Reconfigurable Fabrics Making Reconfigurable Systems Mature p211.pdf
Egeblad Placement Techniques for VLSI Layout Using Sequence-Pair Legalization p240.pdf
Even Digital Logic Design A Rigorous Approach p424.pdf
Ferreira Architectural exploration methods and tools for heterogeneous 3D-IC p179.pdf
Ghongade Lecture 0 VLSI Design Introduction to the subject p455.pdf
Glesner VLSI Design of Integrated Circuits p562.pdf
Gong Synthesizing Sequential Programs onto Reconfigurable Computing Systems p237.pdf
Gotz Runtime reconfigurable rtos for reconfigurable system on chip p180.pdf
Govindarajan Algorithm for design space exploration p216.pdf
Govindarajan Algorithm for design space explorationUN p216.pdf
Guneysu CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES p213 .pdf
Harris Digital Design and Computer Architecture p561.pdf
Hauck Reconfigurable Computing The Theory and Practice of FPGA-Based Computation p945.pdf
Hendriks High Level Synthesis Performance Analysis and Code Optimization p105.pdf
Hollstein VLSI Design of Integrated Circuits Wintersemester 2006 2007 p439.pdf
John Introduction to ASICs p1179.pdf
KOONAR A RECONFIGURABLE HARDWARE IMPLEMENTATION OF GENETIC ALGORITHMS FOR VLSI CAD DESIGN p173.pdf
Kaeslin Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication p879.pdf
Kahng VLSI Physical Design From Graph Partitioning to Timing Closure p319.pdf
Kang CMOS DIGITAL INTEGRATED CIRCUITS - Analysis and Design1 p683.pdf
Koch Architectures Methods and Tools for Distributed Run-time Reconfigurable FPGA-based Systems p295.pdf
Kumar On-Chip Memory Architecture Exploration of Embedded System on Chip p203.pdf
Lamoureux Modeling and Reduction of Dynamic Power in Field-Programmable Gate Arrays p148.pdf
Lenart Design of Reconfigurable Hardware Architectures for Real-time Applications Modeling and Implementation p195.pdf
MARVASTI AN ANALYSIS OF NOCS IN FPGAS p232.pdf
Maache A Prototype Parallel Multi-FPGA Accelerator for SPICE CMOS Model Evaluation p207.pdf
Mailhot TECHNOLOGY MAPPING FOR VLSI CIRCUITS EXPLOITING BOOLEAN PROPERTIES AND OPERATIONS p146.pdf
Mano Digital Design p565.pdf
Maxfield The Design Warriors Guide to FPGAs p560.pdf
Meinel Algorithms and data stuctures in VLSI designs p279.pdf
Meyer-Baese Digital Signal Processing with FPGAs 3rd Edition p795.pdf
Mucci Software tools for embedded reconfigurable peocessors p243.pdf
Mukherjee intro-nmos-cmos VLSI design p367.pdf
NICHOLS A RECONFIGURABLE COMPUTING ARCHITECTURE FOR IMPLEMENTING ARTIFICIAL NEURAL NETWORKS ON FPGA p235.pdf
Nelson Digital Logic Circuit Analysis and Design p866.pdf
OMONDI FPGA Implementations of Neural Networks p363.pdf
OZDAL ROUTING ALGORITHMS FOR HIGH-PERFORMANCE VLSI PACKAGING p169.pdf
PANDYA A HANDEL-C IMPLEMENTATION OF THE BACK-PROPAGATION ALGORITHM ON FIELD PROGRAMMABLE GATE ARRAYS p218.pdf
Pedroni Circuit design with VHDL p376.pdf
Qu INTELLECTUAL PROPERTY PROTECTION IN VLSI DESIGNS p204.pdf
Rabaey Digital Integrated Circuits A Design Perspective p513.pdf
Rubin Using the Electric VLSI Design System p402.pdf
RubinStevenZZZ Computer Aids for VLSI Design Second Edition 1994 p443.pdf
SPARS? PRINCIPLES OF ASYNCHRONOUS CIRCUIT DESIGN – A Systems Perspective p354.pdf
Sait VLSI PHYSICAL DESIGN AUTOMATION Theory and Practice p503.pdf
Saleeba A self reconfiguring computer system p321.pdf
Sarrafzadeh An Introduction to VLSI Physical Design 1996 p350.pdf
Scheffer EDA for IC Implementation Circuit Design and Process Technology p616.pdf
SchorrSuhl Algorithms for Circuit Sizing in VLSI Design p216.pdf
Shrestha VLSI Design & Implementation of High-Throughput Turbo Decoder for Wireless Communication Systems p198.pdf
Sigdel System-Level Design Space Exploration of Reconfigurable Architectures p223.pdf
Smith Microelectronic circuits 5th p696.pdf
Starzyk Topological Analysis and Diagnosis of Analog Circuits p140.pdf
Streichert Self-Adaptive Hardware Software Reconfigurable Networks p253.pdf
Tzeng Integrated placement and routing for VLSI layout synthesis and optimization p106.pdf
WAKERLY DIGITAL DESIGN PRINCIPLES PRACTICES p795.pdf
Wang SYSTEM-ON-CHIP TEST ARCHITECTURES NANOMETER DESIGN FOR TESTABILITY p893.pdf
Wang VLSI TEST PRINCIPLES AND ARCHITECTURES p809.pdf
Weste CMOS VLSI Design A Circuits and Systems Perspective p867.pdf
Wolf Modern VLSI Design IP-Based Design p631.pdf
Ye Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits p244.pdf
Zaretsky DESIGN AND EVALUATION OF MATLAB FUNCTIONS ON FIELD PROGRAMMABLE GATE ARRAYS FPGAS p238.pdf
shin Advanced MOSFET Designs and Implications for SRAM Scaling p108.pdf

Circuit Design

Cardenas, Carlos Silva et al: Introduction to VLSI CMOS Circuits Design p87 August 18, 2006

Pedroni, Volnei A: Circuit design with VHDL, MIT Press, 2004, p376

Logic Design -> Synthesis

De Micheli, Giovanni: Synthesis And Optimization Of Digital Circuits, 2005, p586.

Liu, Bao: VLSI Interconnect Synthesis and Prediction p291 ...2003

Design Methodologies

Masselos, Konstantinos: Lecture 10 - Design methodologies and tools 2006 p95.

Aziz, Adnan: Formal methods in VLSI system design 1996 p133

Li, Jin-Fu: Chapter 1 VLSI Design Methods p37

Browy, Chris; Gullikson, Glenn and Indovina, Mark: A TOP-DOWN APPROACH TO IC DESIGN INTEGRATED CIRCUIT DESIGN METHODOLOGY GUIDE p369 2012

Srivastava, Mani: VLSI Design Methodologies p93.ppt 2001

Srivastava, Mani: VLSI Design Methodologies How are chips designed p141.ppt 2001

Physical Design

Algorithms For Vlsi Physical Design Automation.Sec p452.pdf

Almajdoub A Design Methodology for Physical Design for Testability p150.pdf

Cadence Signal and Design Integrity p56.ppt

Dilli PHYSICAL ASPECTS OF VLSI DESIGN WITH A FOCUS ON THREE-DIMENSIONAL INTEGRATED CIRCUIT APPLICATIONS p263.pdf

Frisbee An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs with a Proposal for a New MCM Routing Algorithm p51.pdf

Gao Performance driven placement and routing algorithm p157.pdf

Hu Taming the Complexity of Coordinated Place and Route p62.ppt

Kahng VLSI Physical Design From Graph Partitioning to Timing Closure p319.pdf

Khan Physical Design Methodology Best Practices NANOMETER AND RTL-DOWN CLOSURE p14

Nam Physical Design Optimization and Design For Manufacturability p108.pdf

Panda Physical design placement and routing p85.pdf

Physical design p74.pdf

Sait Introduction to VLSI Physical Design p42

Sarkar VLSI Physical design automation - introduction, partitioning and floorplanning p49.pdf

Sarrafzadeh An Introduction to VLSI Physical Design 1996 p416.pdf

Tehranipoor Physical Design Automation of VLSI Systems p20.pdf

Tzeng Integrated placement and routing p106.pdf

Simulation
SRINIVASAN, RAMKUMAR: TECHNIQUES FOR ACCELERATING MICROPROCESSOR SIMULATION p168 May 2004

Specifications
賴秉樑 Introduction to VLSI Circuits and Systems 積體電路概論 Chapter 10 System Specifications Using Verilog HDL p216 Fall 2007

Verification

Chen, Adriel: Verification of system on chip using genetic evolutionary test technique from a software applications perspective, Sept 2009, p319

Fitzpatrick, Tom: Design Verification Tutorial Building Modular, Reusable, Transaction-Level Testbenches in SystemVerilog p123 September 25, 2006


Design Contents

芯片解决方案和参考设计

CPU内核架构设计/ARM CPU core集成与优化/memory优化

多核并行处理/ASMP/SMP/多核异构计算/并行编译

GPU架构设计/游戏引擎优化

芯片系统建模（ESL）

系统带宽分析

ESL解决方案

芯片前端（综合，STA）

后端（floorplan，CTS）流程

反馈架构

设计优化

芯片量产低功耗和性能优化

外设子系统及其常用接口设计，比如USB，EMMC，SDIO，SPI，I2C，URAT

Chip VLSI IC Design Contents

product definition

design

DFT

DFM

Power(PNA)

Thermal analyses

MVRC

layout

evaluation

release

production


Design Software EDA

Chip design EDA software

Math for Software and EDA

EDA Tools for VLSI

Free/OpenSource EDA Tools for VLSI Design

5Spice

http://www.5spice.com/

5Spice – is a free analog circuit analysis and simulator with many great features which includes a user expandable library of Spice/Pspice models, save any number of analysis results, integrated graphing of simulation results, student level MOSFET IC design etc. The focus is emphasized on analog circuit analysis and design at component level. 5Spice is mainly designed for students and educators, rather than industry professionals. Latest version of 5spice is released on October 31st 2001 – v 1.65.

The Alliance Tools

http://www-asim.lip6.fr/recherche/alliance

http://www-soc.lip6.fr/

http://www-soc.lip6.fr/recherche/cian/alliance/

ftp://asim.lip6.fr/pub/alliance/distribution/latest/README.win32

The set of tools provided by Alliance lets us design and test a circuit from its specification to its layout form and many of its intermediate formats. Alliance provides a symbolic cell library that makes the design of circuits independent of the technology used in their fabrication step. The cells libraries include a standard cell library and several specific purpose cells for memory and data path logic. Many of the tools in Alliance can be used independently as command line tools. Others have a graphic user interface that requires Motif and the X11 library used in many variants of UNIX and Linux. If we provide an adequate technology file the design obtained with Alliance can be converted to CIF or GDSII format for silicon fabrication.

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Altera

Altera Cyclone? III, Stratix? III, or ArriaTM GX Development Board

Free Web Edition supports all Cyclone and MAX series devices

See Altera My First FPGA Design Tutorial p52 July 2008 for a complete design procedure using Altera's software

Beige Bag

http://www.beigebag.com/demos.htm

Beige Bag - is a demo version of the original paid version of Beige Bag circuit simulation software. Developed based on B2 Spice, this software is mixed mode, power packed, fast and easy to use. Well try the demo version before you decide to buy.

BSIM

BSIM 4 is a simulation model for SPICE3f5 and SPICE3e2. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. BSIM 4 is used for circuit simulation and CMOS technology development, and the latest version is BSIM 4.6.5, which is released in September 2009.

CircuitLogix

http://www.circuitlogix.com/student_version.php

CircuitLogix - this student version software from CircuitLogix enables you to perform analog, digital and mixed mode circuit analysis and simulation. This SPICE simulation software provides 4000 devices on its student version which is 1/3 of the pro version. This circuit building software give access to switches, linear IC and digital IC, FET, Transistors, relays, displays, signal generators, SCR’s, opto isolators, photo diodes, semiconductors, motors etc.

Circuit Simulator

http://www.softpedia.com/get/Science-CAD/Circuit-Simulator.shtml

Circuit Simulator 1.5j - is a freeware circuit simulation tool. I have not used this tool or even attempted a try. I add this as a suggestion from a user in our forum. I think this is just basic tool with very basic functions, created for starter purpose. Use at your own risk.

dreal

http://www-asim.lip6.fr/recherche/alliance

Simple layout editor which uses CIF or GDS as its native format. Companion software is Graal.

Electric

The Electric VLSI Design System is an EDA tool written by Steven M. Rubin. Electric is used to draw schematics and to do integrated circuit layout. - See more at: http://programology.com/Computer-Aided-Design-(CAD)-Programs.html#sthash.9h0evM37.dpuf

http://programology.com/Electric-Download.html

http://tinylab.in/electric-introduction-open-source-vlsi-design-tool/

Electric VLSI Design System

From HDL to layout and some extra

http://www.staticfreesoft.com/

F/LOSS EDA tools

http://timreview.ca/article/442

FreeHDL

http://freehdl.seul.org/

FreePCB

http://www.freepcb.com/

Fritzing

Fritzing is essentially an Electronic Design Automation software with a low entry barrier, suited for the needs of designers and artists. It uses the metaphor of the breadboard, so that it is easy to transfer your hardware sketch to the software. From there it is possible to create PCB layouts for turning it into a robust PCB yourself or by help of a manufacturer.

http://www.fritzing.org/

GAUT

A Free and Open Source High-Level Synthesis Tool for FPGA-Based Acceleration of Scientific Computing

gEDA

The gEDA project has produced and continues working on a full GPL'd suite and toolkit of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout. The gEDA project was started because of the lack of free EDA tools for POSIX systems with the primary purpose of advancing the state of free hardware or open source hardware. The suite is mainly being developed on the GNU/Linux platform with some development effort going into making sure the tools run on other platforms as well.

Website: git.geda-project.org
Website: pcb.geda-project.org
Website: gerbv.geda-project.org
Website: gedasymbols.org
Website: iverilog.icarus.com
Website: gtkwave.sourceforge.net
Mailing List: geda-help
Mailing List: geda-user
Download: gaf stable 1.6.2-20110115 source tarball
Download: gaf unstable 1.7.2-20111231 source tarball
Download: PCB 20110918 source tarball
Download: gerbv 2.6.0 source tarball
Download: xgsch2pcb 0.1.3 source tarball
Download: Icarus Verilog 0.9.5 source tarball
Download: gtkwave 3.3.32 source tarball

http://www.geda-project.org/

http://geda.seul.org/

http://www.gpleda.org/

GHDL

VHDL simulator

http://ghdl.free.fr/

GnuCap

http://www.gnu.org/software/gnucap/

GnuCap - is another open source project, developed as a general purpose circuit simulator. Known widely as GNU Circuit analysis package, this linux based circuit simulator performs various circuit analysis functions as dc and transient analysis, ac analysis etc. Developers have incorporated spice compatible model for MOSFET, BJT and Diode.

graal

http://www-asim.lip6.fr/recherche/alliance

Lambda based layout editor allowing conversion to CIF and GDS with appropriate technology files. Dreal is the companion software to view CIF and GDS. Part of a tool set from Alliance which is probably the best open-source software for IC design. Comes with own standard cell library. Part of Fedora Electronic Lab. The pharosc standard cells are drawn with graal.

Icarus Verilog and Free/Open Source EDA Tools

http://www.icarus.com

ftp://ftp.icarus.com/pub/eda/verilog/v0.8

IRSIM

IRSIM is a logic-level simulator for MOS transistor circuits. Initially, IRSIM was designed to read the “.sim” file and developed with MAGIC, but later the development team added the function of scheduling commands to make it have good performance as Verilog HDL simulators. The latest version of IRSIM is version 9.7.

kic

http://wrcad.com/freestuff.html

Part of open source packages released by Whiteley Research. http://wrcad.com/

KiCad

The KiCad EDA Suite project aims at creating a portable, cross-platform, Free/Libre/Open-Source EDA Suite. That is capable of schematic and printed circuit board design. The code is licensed under the terms of the GNU GPL.

http://kicad.sourceforge.net/

????????????????????????

http://www.lis.inpg.fr/realise_au_lis/kicad/

KLayout

http://www.klayout.de/

High performance layout viewer and editor

KTechLab

IDE for electronic and PIC microcontroller circuit design and simulation

lasi

http://lasihomesite.com/

LASI stands for LAyout Software for Individuals. It is designed to run on Windows, though it also runs on Linux under Crossover Office. Actively used software with frequent updates.

LayoutEditor

LogiSim

LogiSim is written in Java and intends to be an educational tool for designing and simulating digital logic circuits.

http://ozark.hendrix.edu/~burch/logisim/

LTSpice

http://www.linear.com/designtools/software/#LTspice

LTSpice – is a widely popular SPICE simulator from Linear. LTspice is a free circuit simulation tool from Linear Technology corporation. This simulation software is considered as one of the best freeware available. Highlight of LTspice is much fast simulation of switching regulators with enhanced SPICE (compared to normal SPICE simulators).LTspice gives access to over 200 op amp models, transistor models, MOSFET models etc. A high disadvantage of LTspice is its proprietary code base which is licensed by Linear Technology. Had they made it open source, LTspice could have gone places with collaborative development.

Note: LTSpice is considered as the BEST circuit simulation software available by users.

Magic

http://opencircuitdesign.com/magic/

Berkley IC design tools

VLSI layout editor, extraction, and DRC tool

MAGIC is an open source layout editor developed at UC Berkeley 3D-MAGIC is an extension to MAGIC by providing support for Multi-layer IC design

microwind3

http://www.microwind.org/

Lambda based layout editor especially adapted for interactive design with Spice. This used to be completely free, but now only a Lite version is.

MultiSim

http://www.ni.com/academic/multisimse.htm

MultiSim – is a student version circuit simulation software from National instruments. As you know, student versions always comes with limited access. Still this is a great simulation tool for beginners in electronics. MultiSim, the circuit maker software enables you to capture circuits, create layouts, analyse circuits and simulation. Highlight features include exploring breadboard in 3D before lab assignment submission, create printed circuit boards (PCB) etc. Breadboard simulation is possible with Multisim circuit simulator.

ngspice

http://ngspice.sourceforge.net/

one of the popular and widely used free, open source circuit simulator from Sourceforge. NgSpice is developed by a collective effort from its users and its code is based on 3 open source software packages:- known as:- Spice3f5 , Cider and Xspice. Ngspice is a part of gEDA project which is growing every day with suggestions from its users, development from its contributors, fixing bugs and approaching perfection. As its a collaborative project you can suggest improvement of the circuit simulator and be a part of the development team.

OptiKit

An Open Source Kit for Simulation of On-Chip Optical Components

OpenRISC Project

Oscad

http://www.oscad.in/downloads

An open source EDA tool for circuit design, simulation, analysis and PCB design

OrCAD PSpice

PECS

http://web.cecs.pdx.edu/~tymerski/

PECS - is a free power electronics circuit simulator created by Richard Tymerski. You can download the various manuals and tutorials from the website before start using the simulation tool.

Proteus

http://www.labcenter.com/products/basicsim.cfm

Proteus - Prospice is a mixed mode, Spice based simulation tool from LabCenter. They have two versions, basic and advanced. Basic version is free which supports interactive simulation only while advanced supports a range of useful functions and features like graph based analysis which includes frequency, noise, distortion, fourier parameters etc.

Qucs

Qucs is an integrated circuit simulator which means you are able to setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit. After that simulation has finished you can view the simulation results on a presentation page or window.

http://qucs.sourceforge.net/

SAVANT

VHDL analyzer, TyVIS - VHDL simulation kernel, from Clifton Labs

http://www.cliftonlabs.com/vhdl/index.html

SCLive CD

SCLive CD if your focus relies on coding with VHDL, Verilog and SystemC without the need for a complete EDA workflow. The current SCLive release version 3.0 you can download from http://sclive.wordpress.com/ and there you will find a tutorial for its integration with QEMU.

http://sclive.wordpress.com/

Solve Elec

http://www.physicsbox.com/indexsolveelec2en.html

Solve Elec - is an electrical circuit simulator (free version) which is developed for Macintosh OS and Windows. It enables users to draw and analyse circuits (both electrical and electronic) functioning in direct current or alternating current, get formulas, verify equations, get equivalent circuits etc.

Spice

SPICE (Simulation Program with Integrated Circuit Emphasis)

tclspice

http://tclspice.sourceforge.net/

TinyCAD

http://tinycad.sourceforge.net/

Tkgate

Tkgate is an event driven digital circuit simulator with a tcl/tk-based graphical editor. It is a mature project that started at Carnegie Mellon University in 1987.

http://www.tkgate.org/

Toped

http://www.toped.org.uk/

TOPED is a newer cross-platform IC layout editor, which is still under active development. It is also open source software and supports GDS and CIF formats. This editor focuses on the speed and quality of the screen output and has the features like session recovery and customizes GUI. The latest version is version 0.9.5 released in October 2009.

Micron based layout editor with extensive scripting capabilities. Under active development and part of Fedora Electronic Lab. http://fedoraproject.org/wiki/Features/FedoraElectronicLab

TopSpice

http://penzar.com/demopage.htm

TopSpice - this is a demo version circuit simulator from Penzar. This electronic simulation tool is tailored to work with Windows only and its is compatible for Windows XP/Vista/7. TopSpice is a mixed mode mixed signal digital,analog, behavioral simulation software. It offers both Pspice and Hspice compatible simulation of circuits.

Verilator

Fast simulator for synthesizable subset

http://www.veripool.org/wiki/verilator

VeriWell

http://sourceforge.net/projects/veriwell/

VLSICore

deals with VLSI design on SoC / ASIC / FPGA design flows

http://vlsi-core.blogspot.com/

Versatile Place and Route (VPR) tool

VPR is the main academic placement & routing tool

VirtualBox

the opensource virtualization software

http://www.virtualbox.org/

http://spins.fedoraproject.org/fel/#home

wol

http://www.cs.berkeley.edu/~lazzaro/chipmunk/describe/wol.html

XCircuit

XCircuit is a UNIX/X11 (and Windows, if you have an X-Server running, or Windows API, if not) program for drawing publishable-quality electrical circuit schematic diagrams and related figures, and produce circuit netlists through schematic capture. XCircuit regards circuits as inherently hierarchical, and writes both hierarchical PostScript output and hierarchical SPICE netlists. Circuit components are saved in and retrieved from libraries which are fully editable. XCircuit does not separate artistic expression from circuit drawing; it maintains flexiblity in style without compromising the power of schematic capture.

http://opencircuitdesign.com/xcircuit/

Xilinx? IISE WebPACK?

ISE? WebPACK? 设计软件是业内唯一一款功能齐全、面向 Linux、Windows XP 和 Windows 7 的免费 front-to-back FPGA 设计解决方案。

XSpice

http://users.ece.gatech.edu/~mrichard/Xspice/

XSpice - is developed as an extension to Spice 3 by Georgia Institute of Technology. It has code modelling feature which enables user to add new models.

http://www.asicworld. com

http://www.circuitstoday.com/circuit-design-and-simulation-softwares

http://www.eda.org

http://www.edautils.com/

https://fedorahosted.org/fedora-electronic-lab/

http://opencircuitdesign.com/

http://www.OpenCollector.org

http://www.opencollector.org/summary.php

http://www.OpenCores.org

http://www.semiwiki.com/forum/showwiki.php?title=Semi+Wiki:EDA+Open+Source+Tools+Wiki

http://www.tuxmaniac.com

http://ronja.twibright.com

http://www.vlsitechnology.org/html/ic_software.html

EDA Tools

There are several EDA (Electronic Design Automation) tools available for circuit synthesis, implementation, and simulation using VHDL. Some tools (place and route, for example) are ordered as part of a vendor’s design suite (e.g., Altera’s Quartus II, which allows the synthesis of VHDL code onto Altera’s CPLD/FPGA chips, or Xilinx’s ISE suite, for Xilinx’s CPLD/FPGA chips). Other tools (synthesizers, for example), besides being ordered as part of the design suites, can also be provided by specialized EDA companies (Mentor Graphics, Synopsis, Synplicity, etc.). Examples of the latter group are Leonardo Spectrum (a synthesizer from Mentor Graphics), Synplify (a synthesizer from Synplicity), and ModelSim (a simulator from Model Technology, a Mentor Graphics company).

The designs presented in the book were synthesized onto CPLD/FPGA devices (appendix A) either from Altera or Xilinx. The tools used were either ISE combined with ModelSim (for Xilinx chips), MaxPlus II combined with Advanced Synthesis Software (for Altera CPLDs), or Quartus II (also for Altera devices). Leonardo Spectrum was also used occasionally.

Logic Synthesis Tools

Logic synthesis tools take the register transfer-level HDL description and convert it to an optimized gate-level netlist

RTL-based synthesis is currently the most popular design method

Synopsys: Design-compiler, design-analyzer

Cadence: NC-VHDL

Sigasi: VHDL editing tools

Innoveda: VIEWDRAW

http://www.edaplayground.com/

The LDV system provides a simulator for the VHDL language

High-Level Synthesis (HLS) tools

HLS tools work by taking applications written in a subset of ANSI C, and translating it into a Register Transfer Level (RTL) module for Application-Specific Integrated Circuit (ASIC) or Field Programmable Gate Arrays (FPGAs) chip design.

The SPR tool is an example of a synthesis tool, or to be more precise an RTL level synthesis tool.

Xilinx Virtex-5 FPGA platform

Synopsys: Synphony C Compiler

Synfora Inc: the HLS tool called PICO

AutoESL: Catapult C

Xtensa processor extension synthesis compiler. XPRES

Icarus Verilog – Technical Details

● A Command line Verilog simulation and synthesis tool
● A Compiler, compiling source code written in Verilog (IEEE1364) into some target format.
● The currently supported targets are vvp for simulation, and xnf and fpga for synthesis
● Selection of the Verilog language generation to support in the compiler. Selects between IEEE13641995(1), IEEE13642001(2). Increases compatibility with other tools down the chain.
● The Icarus Verilog compiler supports module libraries as directories that contain Verilog source files.
● Main porting target is Linux, although it works well on many similar operating systems such as Windows, MacOS.

ftp://ftp.icarus.com/pub/eda/verilog/v0.8
ftp://icarus.com/pub/eda/verilog/snapshots

Cell Development Tools
? Schematic entry (transistor symbols)
? Analog simulation (SPICE models)
? Layout (layer definitions)
? Design Rule Checking, DRC ( design rules)
? Extraction (extraction rules and parameters)
? Electrical Rule Checking, ERC (ERC rules)
? Layout Versus Schematic, LVS ( LVS rules)

NetList Visualization Tools

Physical Design Tools

Synopsys

Cadence: ALLEGRO

Magma

Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays

View-logic

=============================

Spiffy algorithm ???

VPR ???

Locus- Route ???

GBP ???

TRACER ???

Alexander/Robins routing tool

Avant! ???
– Power full place and route tools
– Hspice simulator with automatic characterization tools

Summit ???

AMATEROUS A PARALLEL WIRE ROUTER WITHOUT DETAILED/GLOBAL FEEDBACK

The Research Institute for Discrete Mathematics of the University of Bonn

BonnTools, are widely used in industry. More than 1500 highly complex chips have been designed by BonnTools. Chip design is a very fascinating and highly important area of application of mathematics.

VLSI Floorplanning Tools

specifically Capo ???

Place and Route Tools

Versatile Place and Route (VPR) tool

VPR is the main academic placement & routing tool

non-linear congestion method implemented in Versatile Place and Route (VPR)

Placement & Routing版图设计工具软件

Cadence: Encounter, icfb, Spectre、SpectreRF, Allegro, OrCAD, Virtuoso, Composer

Encounter自动布局布线工具软件

Mentor: Calibre

Synopsys: Astro

Altium: Protel

Altium Designer 在单一设计环境中集成板级和FPGA系统设计、基于FPGA和分立处理器的嵌入式软件开发以及PCB版图设计、编辑和制造

TannerEDA工具 - 版图流程L-edit是美国Tanner公司开发的版图设计工具软件

Ansoft Designer v3.5 射频数模混合集成电路设计软件

Laker

PADS

九天EDA系统包括：版图设计工具ZeniPDT 版图对应电路的验证（LVS），版图设计规范验证（DRC）及电路规范验证（ERC） PCB版图绘制工具

Static Analysis
Synsopsys: Primetime

DFT可測性設計工具

Mentor: MBIST, TESTKOMPRESS

Synopsys: DFT COMPILER

时序验证工具

PT ??????????????

PRIMETIME ?????????????

ETS ????????????

DRC & LVS物理形式验证工具
Mentor: Calibre

Cadence: Diva, Dracula, CONFORMAL, Incisive Formal Verifier 验证工具

DRC (design rule check)
LVS (layout vs. schematic)
GDS vs. (verilog + spice module)

Simulation Tools

Mentor: Modelsim, Caliber

Cadence: Synplify, NC-Verilog, MMSIM7, Virtuoso, SPECTRE

Synopsys: HSPICE, VCS，DFT,PC

Aldec: Active-HDL

Altium: Protel

Robei芯片设计工具

http://robei.com/

若贝软件是一款全新的芯片可视化设计和仿真工具。该软件集成了先进的图形化与代码设计，同时具备Verilog编译仿真和波形分析，可以实现各种系统的设 计，仿真和测试。软件生成标准的Verilog代码，可以直接与各种EDA工具相融合。界面美观，简洁，15分钟就可以熟悉软件的操作，对比其他大型复杂 软件，可以节省很多时间来实现同样的功能。若贝通过一种结构层面上图形化设计，算法层面上代码输入的方式，不仅使设计更加直观，且内置的代码生成功能更可 以减少代码输入中的错误，实现快速设计。若贝不仅仅是一款为学生和老师准备的优秀的教学工具，也是一款为初级到中级的硬件设计工程师准备的快速开发验证工 具。目前只支持Verilog语言。

通用设计工艺库

TSMC

IBM

JAZZ

SMIC

ASIC 的EDA工具

Synopsys: PrimeTime

Cadence: NCVerilog

DesignCompiler ???

Formality ????????

VCS ???????

Virtual Platforms in System-on-Chip Design

Virtual platform tools providers

Synopsys

Carbon Design Systems

Imperas /OVP (Open Virtual Platform)

Mentor

Catapult C

MathWorks

EDA Simulator Link tool

CoFluent Studio

Encounter SoC

Design companies

ARM

Tensilica

Qualcomm

Samsung

ST Microelectronics

Freescale

Infineon Technologies

Standards

SystemC

Transaction-level modeling (TLM)

IP-XACT

FPGA 的EDA工具

免费的FPGA EDA工具

Free FPGA EDA tools

=================================================

FPGA Design Flow with Tools

Circuit

Logic optimization (SIS)

Technology map to 4-LUTs (FlowMap + Flowpack)

Pack registers and LUTs into logic clusters (VPack)

Placement (VPR)

Routing architecture

Routing (VPR, timing-driven router)

Routing with W = 1.2 Wmin (VPR, timing-driven router)

Determine critical path delay and transistor area to build FPGA routing (VPR)

==================================================

Altera

See Altera My First FPGA Design Tutorial p52 July 2008 for a complete design procedure using Altera's software

Quartus II , Maxplus II

Cyclone? III, Stratix? III, or ArriaTM GX Development Board

Free Web Edition supports all Cyclone and MAX series devices

NEC

推出了半导体设计高阶综合工具CyberWorkBench的FPGA专用版

Mentor

Modelsim, Questasim

Spiffy

The first tool specifically designed for the placement and global routing of 3DFPGAs.

Karro, John: A Spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays.

Synopsys

FPGA综合布线工具Synplify

VPH

A place and route tool for hybrid FPGA called VPH. VPH is a modified version of the VPR tool. It supports embedded blocks, memories, multipliers, carry chains and user constraints.

Versatile Place and Route (VPR) tool

VPR is the main academic placement & routing tool

Non-linear congestion method implemented in Versatile Place and Route (VPR).

Xilinx

FPGA design with Xilinx ISE 13 and prototyping boards

Xilinx? ISE WebPACK?

ISE? WebPACK? 设计软件是业内唯一一款功能齐全、面向 Linux、Windows XP 和 Windows 7 的免费 front-to-back FPGA 设计解决方案。

Xilinx ISE 13

Xilinx PicoBlaze for Spartan3 libraries and software

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

FPGA验证阶段

VPACK

VPACK netlist translation / clustering tool

The VPACK Logic Block Packer / Netlist Translator

RPack ??????????

T-VPack timing-based T-VPack ??????????

T-RPack clustering algorithm ??????????

Rmap ??????????

GASA and VPlace are highly comparable placement tools ??????????

EasyRouter; FPGA IP design framework ??????????

SPLACE/SROUTE tool ??????????

TORCH a design tool for routing channel segmentation in FPGAs ???????????

3D FPGA Software support

  • Spiffy - Simultaneous placement and global routing. Placement is recursive partition based.
  • Three-dimensional Place & Route (TPR) – Placement (recursive partition based and simulated annealing based, routing is based on PathFinder algortihm)
  • 3D MEANDER

Literature

Altera: Introduction to Simulation of VHDL Designs, May 2011, p30

Altera: Quartus II Introduction Using VHDL Design, Oct 2005, p30

Aanjhan Icarus Verilog and Free Open Source EDA Tools, 25/02/2006, p10

Breuer Fundamental CAD Algorithms p27

Digilent: Xilinx ISE WebPACK? VHDL Tutorial, February 27, 2010, p16

Hendry, D C: Software Tools for VHDL Development, August 2003 p13

Karro, John and Cohoon, James: Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays, July 6, 2001, p11

Kougianos, Elias et al: VLSI Design Through Open-Source Free Tools, 22 Dec 2010 ISED 2010 -- WES, p41

Moiseev, Konstantin and Wimer, Shmuel: Lecture 1 VLSI CAD Overview Design, Flows, Algorithms and Tools 048918 VLSI Backend CAD, March 2013, p51

Nestor, John A.: Web-Based Visualization Tools for Teaching VLSI CAD Algorithms, June 2001, p11

Ng, Shao et al: Bottom up IC design-flow Using an Analog Leaf Cell 2007 p103.

Quartus II Introduction Using VHDL Design 2005 p30

Rubin, Steven M.: Computer Aids for VLSI Design, Second Edition, 1994 p443

@@@@@@@@@@@@@@@@@@@@@@@@@@

Sherwani: VLSI Physical Design Automation, 1992 p25

Wolf, Wayne : Modern VLSI Design 3e Chapter 10 CAD systems, 2002 Prentice Hall, p32

Wong, Martin D.F.: On Simulated Annealing in EDA, 1981, p30.


Design Flow Overview

The Y-Chart

The Y-chart (first introduced by D. Gajski) illustrates a design flow for most logic chips, using design activities on the three different axes (domains). Y chart of three major domains, they are:

  • Behavioral domain
  • Structural domain
  • Geometrical layout domain

General Flow

The design flow starts from the algorithm that describes the behavior of the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning.

The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing inter- connects area and signal delays.

The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell placement & routing program.

The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use.

The Process of VLSI Design

Consists of many different representations/abstractions of the system (chip) that is being designed. Basic steps in the physical design cycle:

1. System specification

System Level Design

High level functional description (informal) of the design with size, speed, and power constraints.

2. Architecture Design and Verification/Simulation

Micro-architectural specification (informal) of the design with architecture style number of ALUs, floating point units, number and structure of pipelines, and size of caches.

The first step in evolving the design description is to describe the circuit in terms of its behavior. The description looks like a program in a high level language like C. Once the behavior level design description is ready, it is tested extensively with the help of simulation tool; it checks and confirms that all the expected functions are carried out satisfactorily. If necessary, this behavioral level routine is edited, modified, and rerun – all done manually. Finally, one has a design for the expected system- described at the behavioral level. The behavioral constructs not supported by the synthesis tools replaced by data flow and gate level constructs. To surmise, the designer has to develop synthesizable codes for his design.

Architecture / Algorithm Level Design

Digital System Level Design

Semiconductor Level Design (possibly more)

Hardware Description Languages

Register transfer level (RTL) description of the design in HDL is generated. It consists of boolean expressions and timing information.

RTL Description / Register Transfer Level Design and Simulation / Verification

RTL Simulation

4. Functional Behavioral / Design and Verification/Simulation

Functional Design and Simulation / Verification

Behavioral Simulation

The functionality of each unit and their interconnection is described by HDL. The area, power, and time of each unit is identified.

5. Logic Design and Verification/Simulation

Logical Level Design

Logic Synthesis

Logic Simulation

6. Circuit Design and Verification/Simulation

Electrical Level Design

7. Physical Design and Verification/Simulation

The circuit representation (or netlist) is converted into a geometric representation called the layout. Automated physical design is called physical synthesis.

Layout Level Design

Converts a circuit description into a geometric description. This description is used for fabrication of the chip.

Partitioning

Floorplanning

Placement

Global Placement and timing optimization

Clocktree Generation

Detailed Placement

Routing

Global Routing

Detailed Routing

Compaction

Design Rule Checking

POST LAYOUT SIMULATION

Final Checks

8. Final Verification/Simulation

Once the placement and routing are completed the performance specifications like silicon area, power consumed, path delays, can be computed. Equivalent circuit can be extracted at the component level and the performance analysis carried out. This onstitutes the final stage called “verification”. One may have to go through the placement and routing activity once again to improve performance.

9. Fabrication

Production

10. Packaging, testing, and debugging

Design with VHDL

One of the major utilities of VHDL is that it allows the synthesis of a circuit or system in a programmable device (PLD or FPGA) or in an ASIC.

  • We start the design by writing the VHDL code, which is saved in a ?le with the extension .vhd and the same name as its ENTITY’s name.
  • The ?rst step in the synthesis process is compilation. Compilation is the conversion of the high-level VHDL language, which describes the circuit at the Register Transfer Level (RTL), into a netlist at the gate level.
  • The second step is optimization, which is performed on the gate-level net-list for speed or for area. At this stage, the design can be simulated.
  • Finally, a place- and-route (?tter) software will generate the physical layout for a PLD/FPGA chip or will generate the masks for an ASIC.

芯片设计需要经过大致的几个阶段：

前期准备阶段（对于标准的理论研究、芯片实现的算法研究、计算机仿真、 FPGA 验证）

芯片设计和生产阶段（布图、布线、芯片工艺设计、芯片流片、芯片评估和测试）

器件物理

电路设计

网表提取

编译

前仿真

后仿真

版图设计

电路整理

仿真验证

专 利分析

综合

约束

静态时序分析

形式验证等

芯片验证和产品推出阶段（通过在各种类型整机上对芯片进行充分验证）

工艺技术

材料制备

自动测试

封装

组装


DESIGN METHODOLOGIES

Chip (VLSI) Design Methodologies

A circuit can be modeled differently according to the desired abstraction level (e.g., architectural, logic, geometric), view (e.g., behavioral, structural, physical) and to the modeling means being used (e.g., language, diagram, mathematical model).

Every company has its own design methodology. Methodology depends on:
?type of chip
?size of chip
?design time constraints
?cost/performance
?available tools

S-Parameter Design
  • Direct control of layout and device parameters
  • longer design time
  • but faster operation
  • more dense

RTL-Level Design

Chip Design Styles Overview

  • Custom
  • Semi-custom
    • Cell - based
      • Standard cells/Compiled cells
      • Macro-cells
    • Array based
      • Pre-diffused (Gate Arrays)
      • Pre-wired (FPGA)

Full Custom Design

Bottom Up Design [Full Custom Flow]

The bottomup design methodology is based on (mainly) manual construction of circuit building blocks at the transistor and masklayout level

●Flexibility at lower level design issues such as transistor size optimization and parasitics minimization.
●Better suited for the design of very dense, highperformance digital modules as well as analog and mixedsignal integrated circuits.

Full Custom: Block/Cell and transistor aspect ratios, shape (need not be rectangular), floorplanning can be controlled by the designer to achieve a high degree of optimization—hand tuned designs

Full Custom Design Style

 Circuit partitioned into sub-blocks.
 Blocks can be of any size/shape
 Hierarchical design
 Placement on any location is allowed
 Allows very compact designs
 Difficult automation
 High performance
 The process of automating a fullcustom design style has a much higher complexity than other restricted styles.

Semi Custom Design
[Top Down Design]

Cell - Based

Standard Cell Design

Cell-Based Design (Standard Cells)

In standard cell design, a circuit is composed of a set of logic cells. Each logic cell has the same height and variable width, and each cell contains a number of connection points, called pins. There may be equivalent pins which allow connection at multiple locations on a cell.

Standard Cell Design Style

  • Design process is somewhat simpler than full-custom design style
  • Standard cell design style takes more area than full custom.
  • Rectangular cells of same height
  • Cells arranged in rows
  • Library based design
  • In modern ASIC design, standard cell methodology is practiced with a sizeable library of cells
  • The library contains multiple implementations of the same logic function, differing in area and speed
  • Logic synthesis uses standard cell design style.
  • Channel is the space between two rows.
  • Feedthrough is the empty cells in a row.
  • Feedthroughs are assigned for the interconnections of non-adjacent cells.
  • Inherently nonhierarchical
  • Easier automation
  • Lower performance
  • Well suited for moderate size designs and medium production volume.
  • Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC).

ASIC – Standard Cell Design

Macro Cell Design

Macro-block design

Array Based

Pre-diffused (Gate Arrays)

Gate Array Design

Gate Array or Programmable Logic Array PLA Design

Circuit integration through lattice hyperterms, distributive lattices

Easier to implement

Fastest design turn around

Limited cell library selections

Reduced performance

 A simplification of Standard Cell Design Style
 Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected
 A regular lattice shaped structure
 Pre-fabricated logic
 Both vertical and Horizontal channels
 Only wiring masks need to be defined
 Rapid fabrication
 Low performance
 Easy automation
 Non-hierarchical structure
 Logic synthesis can use gate array.

Photo-lithographic masks are required only for the metal layers

 Production cycles are much shorter as metallization is a comparatively quick process
 Advantages/Disadvantages:
 The steps involved for creating any prefabricated wafer are the same
 Only the last few steps in the fabrication process will be used.
 Cheaper and easier to produce than full-custom and standard cell.
 It offers more area and less time.
 Difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the price
 Pure, logic-only gate array design is rarely implemented by circuit designers today
 FPGA is preferred.

Today gate arrays are evolving into Structured ASICs

 Structured ASICs consist of a large IP core like a CPU, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommited logic.
 This shift is largely because ASIC devices are capable of integrating large blocks of system functionality and"system on a chip" requires far more than just logic blocks.

Sea-of-Gate Design

Gate Matrix Design

Pre-wired (FPGA)

FPGA (Field Programmable Gate Array) Design

Field Programmable Gate Array (FPGA)

FPGA Design Style

 Extremely rapid prototyping
 Re-programmable
 Lowest performance
 Easy automation
 Cells and interconnects are prefabricated.
 The user simply programs the interconnects.
 Contains programmable logic blocks and interconnects
 Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions.
 FPGAs contain FFs

CPLD / SPLD / SSI Design


System Specification

VLSI System Specification

Specification and High-Level Design

PROCESS SELECTION

System modeling

The concepts in the designer’s mind are captured as a set of computational operations and data dependencies subject to constraints on timing, chip area, etc.:

  • Goals and constraints of the system
  • Functionality (what will a system do)
  • Performance figures like speed and power
  • Technology constraints like size and space (physical dimensions)
  • Fabrication technology and design techniques
賴秉樑 Introduction to VLSI Circuits and Systems 積體電路概論 Chapter 10 System Specifications Using Verilog HDL 2007 p216


Architectural / Behavioral Design

Synthesis and optimization of circuits at the architectural level describe techniques for transforming an abstract model of circuit behavior into a data path and a control unit. The data path is an interconnection of resources, whose execution times and input/output data are determined by the control unit accofding to a schedule.

Architectural synthesis means constructing the macroscopic structure of a digital circuit, starting from behavioral models that can be captured by data-flow or sequencing graphs. The outcome of architectural synthesis is both a structural view of the circuit, in particular of its data path, and a logic-level specification of its coritrol unit. The data path is an interconnection of resources (implementing arithmetic or logic functions), steering logic circuits (e.g., multiplexers and busses), that send data to the appropriate destination at the appropriate time and registers or rnemov arrays to store data.

Micro-architectural specification (informal) of the design with architecture style number of ALUs, floating point units, number and structure of pipelines, and size of caches.

The first step in evolving the design description is to describe the circuit in terms of its behavior. The description looks like a program in a high level language like C. Once the behavior level design description is ready, it is tested extensively with the help of simulation tool; it checks and confirms that all the expected functions are carried out satisfactorily. If necessary, this behavioral level routine is edited, modified, and rerun – all done manually. Finally, one has a design for the expected system- described at the behavioral level. The behavioral constructs not supported by the synthesis tools replaced by data flow and gate level constructs. To surmise, the designer has to develop synthesizable codes for his design.

Architecture / Algorithm Level Design

Digital System Level Design

Semiconductor Level Design (possibly more)

Hardware Description Languages

Register transfer level (RTL) description of the design in HDL is generated. It consists of boolean expressions and timing information.

RTL Description / Register Transfer Level Design and Simulation / Verification

RTL Simulation

Behavioral/Functional

VHDL, C

Behavioral VHDL

Verilog HDL Synthesis: Top-Down Design

Requirements Analysis

Specification

Verification

Synthesis & Optimization

System Partitioning

Gate Level Verification


Functional Design / Verification

Behavioral Representation

Functional Design.

Behavioral Design

Architecture Design

The resources that can implement the system’s operations are identified, and the operations are scheduled. As a result, the control logic and datapath interconnections are also identified.

Functional design is also called high-level synthesis. Considerations are taken for the following:

  • RISC, CISC, # of ALUs, floating point units, number and structure of pipelines, etc.
  • Functional behavior and functional units to match specification
  • Functional subunits and relationship among them

Literature

Devadas, Srini: VLSI CAD Flow: Logic Synthesis, Placement and Routing p19

RTL Design p6

Synopsys Describing Synthesizable RTL in SystemC p116


Logic Design / Synthesis / Verification

We begin the logic design by defining the top-level chip interface and block diagram. We then hierarchically decompose the units until we reach leaf cells. We specify the logic with a Hardware Description Language (HDL), which provides a higher level of abstraction than schematics or layout. This code is often called the Register Transfer Level (RTL) description.

Logic synthesis produces a gate-level netlist from an abstract specification (behavioral, RTL)

Logic synthesis fits between the register transfer level and the netlist of gates specification. It provides the automatic synthesis of netlists minimizing some objective function subject to various constraints. Example inputs to a logic synthesis system include two-level logic representation, multi-level Boolean networks, finite state machines and technology mapped circuits. Depending on the input specification (combinational versus sequential, synchronous versus asynchronous), the target implementation (two-level versus multi-level, unmapped versus mapped, ASICs versus FPGAs), the objective function (area, delay, power, testability) and the delay models used (zero-delay, unit-delay, unit-fanout delay, or library delay models), different techniques are applied to transform and optimize the original RTL description.

The high-level specification is transformed into an interconnection of gate-level boolean primitives — nand, xor, etc. The circuit components that can best realize the functions derived in functional design are assembled. Circuit delay and power consumption are considered at this step. The output description of the interconnection between different gate-level primitives is usually called a netlist.

Logic Design may involve:

  • Implementation of functional subunits using logic representation
  • Boolean expressions, finite state machines or schematics.
  • Use of standard building blocks like RAM, ROM, PLA, etc.
  • Logic design should match functional description.
  • Register Transfer Level (RTL) description of subunits.
  • RTL is expressed in VHDL or Verilog.

Register Transfer Level (micro-architecture, block)

RTL Level Design

RTL Description

rtl设计

RTL级

Gate级

Logic Simulation / Synthesis

Logic Synthesis

Logic Design

High-Level Synthesis (HLS)

Simulation

Netlist

Precomputation Logic

The basic idea is to selectively precompute the output logic values of the circuits one clock cycle before they are required, and then use the precomputed values to reduce internal switching activity in the succeeding clock cycle .

In a combinational circuit, it is also possible to identify subsets of gates which do not contribute to the computation initiated with some input stimulus. Power can thus be reduced by turning off these subsets of gates. The overhead of detecting and disabling these sub-circuits may however be large. For many circuits, this approach does not produce an appreciable decrease in power dissipation, however, power savings of up to 40% have been reported for some circuits.

Retiming

Retiming is the process of re-positioning the flip-flops in a pipelined circuit so as to either minimize the number of flip-flops or minimize the delay through the longest pipeline stage. It is noted that a flip-flop output makes at most one transition when the clock is asserted. Based on this observation, the authors then describe a circuit retiming technique targeting low power dissipation. The idea is to identify circuit nodes with high hazard activity and high load capacitance as candidates for adding a flip-flop. The technique does not produce the optimal retiming solution because the retiming of a single node can dramatically change the switching activity of many other nodes in the circuit.

Techniques

Recent developments in lattice theory, and particularly the concepts of lattice hyperterms and lattice hyperidentities give a new perspective to the optimization of logic circuits.

  • find an equivalent hypercircuit
  • combinatorial optimization and integer programming
  • reliability theory

Aboulhamid, El Mostapha: VHDL Design Flow BEHAVIORAL AND LOGIC SYNTHESIS 1997 p112

Chan, YiuHing: Physical Synthesis Methodology for High Performance Microprocessors p6 .

De Micheli, Giovanni: Synthesis And Optimization Of Digital Circuits p586 .....................16

Gupta, Sumit: Distributed Adaptive Simulated Annealing for Synthesis Design Space Exploration p12

Kutzschebauch Layout and structure aware synthesis of integrated circuits p155

Wloka, Markus G: Parallel VLSI Synthesis May 1991 p163

Wong, Catherine Grace: High-Level Synthesis and Rapid Prototyping of Asynchronous VLSI Systems May 21, 2004 p205


Circuit Design / Circuit Verification

Circuit Design

Circuit design is concerned with arranging transistors to perform a particular logic function. Given a circuit design, we can estimate the delay and power. The circuit can be represented as a schematic, or in textual form as a netlist. Common transistor level netlist formats include Verilog and SPICE. Verilog netlists are used for functional verification, while SPICE netlists have more detail necessary for delay and power simulations.

 Logic networks or descriptions are converted into electronic circuits.
 Circuit elements are designed to meet specifications.
 Transistors are sized for current capacity and delay requirements.
 Circuit simulation is used to verify the correctness and timing of each component.


Physical Design / Physical Verification

Physical design of VLSI circuits is the process of mapping structural representations of circuits into layout representation of circuits. Structural representations describe the system in terms of logic components and their interconnects. Layout representations define circuits in terms of a set of geometric objects which specify the dimensions and locations of transistors and wires on a silicon surface.

Physical design is one of the main steps in IC design where the physical properties such as the exact locations of components and wires of the circuit are determined.

Physical design includes several major stages: partitioning, floor planning, placement and routing.

Physical Design Process

  • Physical Design converts circuit description into a geometric description.
  • This description is used to manufacture a chip.
  • The input to a physical design cycle is a circuit diagram/netlist and the output is the layout of the circuit.

Required Stages:

  • Partitioning Divide the net-list into sub-sets.
  • Floorplanning
  • Pin assignment
  • Placement
  • Routing
  • Convergence
  • Compaction
  • Extraction and Verification (post-layout verification)

New Trends in Physical Design Process

Chip Level Signal Planning

  • Routing of major signals and buses must be planned from early design stages, so that the interconnect distances can be minimized.
  • Interconnects length directly impact circuit delay and layout area

OTC Routing

  • Over-the-cell (OTC) routing allows routing over blocks and active areas. Reduces the layout area

Major Challenges

  • Crosstalk
  • Power Supply Noise and Temperature

Steps of Iterative Design Process

Synthesis:

  • Synthesis derives or improves a representation at any step.
  • Behavioral synthesis, logic synthesis and layout synthesis are all examples at various steps.

Analysis:

  • Analysis ensures that the design representation matches the requirements at various steps.
  • Requirements like area, power dissipation and speed.

Verification:

  • Establishes the correctness of design at any given step.
  • Simulation at any step should match specifications.

Selection of Design Style

Selection of design styles depends on many factors:

  • Type of chip
  • High performance, Area, …
  • Volume
  • Mass production, Medium production volume, …
  • Cost
  • Company’s budget, Cost of the chip
  • Time-to-market
  • Last two are dominant.

Multi Level Framework

Multilevel Routing System

Multilevel Full-Chip Routing for the X-Based Architecture

Multilevel Full-Chip Routing with Testability and Yield Enhancement

Novel Framework for Multilevel Routing Considering Routability and Performance

novel framework for fast multilevel routing considering crosstalk and performance optimization.

integrated multilevel routing framework with embedded oscillation ring (OR) test architecture

==================================================

minimum-radius minimum-cost spanning-tree (MRMCST) heuristic for global routing

diagonal routing

the X-initiative

multilevel routers 2001 ????????

http://www.xinitiative.org/

Ho, Tsung-Yi et al: Multilevel Full-Chip Routing for the X-Based Architecture, p6, 2005 ACM 1-59593-058-2/05/0006

Ho, Tsung-Yi: et al: A Fast Crosstalk- and Performance-Driven Multilevel Routing System, p6, Aug. 2003

Li, Katherine Shu-Min et al: Multilevel Full-Chip Routing with Testability and Yield Enhancement, p45 (slide) , Sept 2005.

Lin, Shih-Ping: and Chang, Yao-Wen: A Novel Framework for Multilevel Routing Considering Routability and Performance, p 7, Nov 2002

Layout (placement and routing)

netlist layout

版图设计流程工具

Aarts, Emil H L et al: VLSI layout synthesis 1997 p26

Cagan A Survey of Computational Approaches to Three dimensional Layout Problems p33.

Chsoma Chip Layout consideration p17

CoeStephen Hardware Implementation of a Memetic Algorithm for VLSI Circuit Layout,

Cong Performance Optimization of VLSI Interconnect Layout p99.pdf

Das, Ananda Swarup et al: Detecting VLSI Layout and Connectivity Errors in a Query Window August 10{12, 2011 p6

Das, Sandip: Routing algorithms for channels, swithboxes, and MCMs in VLSI layout design Nov 2006. p137 .

de Abreu Moreira, Dilvan et al: Using Software Agents to Generate VLSI Layouts NOVEMBER/DECEMBER 1997 p7

Hong, Teen Soh and Yin, Lee Sin: Cmos Ic Layout Design: 7- Segments Counter August 19, 2013 p4

Jaja Parallel algorithm for VLSI layout 1989 p36 .

Kchsomsa Chip Layout consideration p17 .

Linhares, Alexandre: Synthesizing a predatory search strategy for VLSI layouts JULY 1999 p6

Martins, Ricardo: LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach 2012 p8

MOISEEV, KONSTANTIN, KOLODNY, AVINOAM and WIMER, SHMUEL: Power-Delay Optimization in VLSI Microprocessors by Wire Spacing .......... ACM Trans. Des. Autom. Electron. Syst. 14, 4, Article 55 (August 2009) ..........p28

Moraes, F. et al: Estimation of layout densities for CMOS digital circuits 1998 p10

Ousterhout, John K et al: Magic: A VLSI layout system Dec 1983 p105

Pan, Min and Chu, Chris: IPR: An Integrated Placement and Routing Algorithm, DAC 2007, June 4-8, 2007, San Diego, California, USA, p4

Palermo, Sam: lecture05_ee474 Layout Techniques p74.

Pedram, Massoud and Vaishnav, Hirendu: Power Optimization in VLSI Layout A Survey May 2008 p30

Yeh, Chi-Hsiang et al: Multilayer VLSI Layout for Interconnection Networks 1999 p8.

Yeh, Chi-Hsiang and Parhami, Behrooz: VLSI layouts of complete graphs and star graphs Received 18 December 1997 p7................ Information Processing Letters 68 (1998) 3945

The actual spatial layout of circuit components on the chip is determined. The objectives during this step usually include total wirelength, maximum signal propogation time (“performance”), etc. Physical design can be further divided into steps including partitioning, floorplanning, placement, and routing

Minimizing the wirelength plays an important role in physical design automation of very large scale integration(VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay have prime importance. In VLSI circuit floorplanning the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning has influence on other criteria like power, cost, clock speed etc.

===========================================

Flat Design

================================================

IPR (Integrated Placement and Routing)

Efficient placement and routing algorithms FastPlace, FastDP and FastRoute are integrated, and well-designed methods are proposed to integrate them efficiently and effectively. Experimental results show that IPR reduces overflow by 36%, global routing wirelength by 3.6%, and runtime by 36% comparing to ROOSTER, which is the previous best academic routability driven placer

FastPlace is a very efficient wirelength-driven placement algorithm. It was first proposed to handle standard cell designs and later extended to handle mixed-size designs. In general, it is a force-directed placement algorithm. It formulates the placement problem as convex quadratic programming. In order to achieve an even placement, a cell shifting technique is proposed to spread out the cells. In addition, half-perimeter wirelength (HPWL) is optimized by an iterative local refinement (ILR) technique. FastPlace can generate good placement solutions in terms of HPWL with very fast runtime.

FastDP is an efficient and effective detailed placer. It works on a legalized placement and iteratively reduces HPWL. In the main loop, global swap, vertical swap and local re-ordering techniques are applied to reduce the wirelength. For the cells in the same placeable segment, a single-segment clustering technique is proposed to find the optimal cell positions respecting their original ordering.

FastRoute is a very fast high-quality global router. Different from traditional global routers, it focuses on Steiner tree structures to resolve congestion. Congestion driven Steiner tree topology construction algorithm and edge shifting technique are proposed to construct good Steiner trees. Monotonic routing and multi-source multisink maze routing techniques are proposed to enhance the pattern routing and traditional maze routing to achieve high-quality routing solutions. Experimental results show that FastRoute generates much better global routing solutions with tens to hundreds of times speedup compared to all other state-of-the-art academic global routers.

================================================

the Sharp methodology developed by Bapat and Cohoon, a technique for the integration of placement and global routing

======================================================

Congestion

For handling connection congestion researchers have introduced annealing algorithms, multiple partition techniques, concurrent detection in top-down placement and integer linear programming (ILP).

Measuring Congestion

Congestion occurs in a physical layout when the pin density (pins per unit placement layer area) and average fanout are high in a localized area, and the wires must be as short as possible to meet the timing constraints. Automated wiring tools are used to find routes for each signal in the design. A congested design with a legal wiring assignment is prone to longer wires (with the attendant larger wire delays) and signal crosstalk (interference between two adjacent signals). A congested design with an illegal wiring assignment must be manually modified to make it legal (if possible) either by changing the wiring route or by removing a subset of the routed wires and rerunning the wiring tool or both. These problems are very expensive to address in terms of both scheduling and workforce resources.

Since the degree of wiring congestion is so central to the quality of the physical design of the chip, and the process of creating a physical layout for a chip from the netlist is so time consuming, companies need a means of estimating the congestion inherent in a given netlist before attempting the physical layout processes.

Three major factors affect congestion: the number of wiring layers available, the interconnectedness of the netlist, and the delay constraints.

Since the number of layers available in the wiring space obviously determines a critical parameter for potential congestion, various measures of the thickness of a graph may inform this problem. Graph thickness is the minimum number of planar subgraphs whose union is the original graph. Geometric thickness adds the restriction (very important in this context) that the planar subgraphs must be on the same arrangement of the vertices in the plane and have straight line segments as the edges, where geometric thickness two is called doubly linear). A critical concern about this approach is that graph thickness is in general NP hard. Although there are heuristics for approximating graph thickness, this computation complexity presents an implementation obstacle.

Furthermore, the problem actually requires something more specific: what might be described as the thickness-dependent area of a hypergraph. The number of wiring layers available is known. The question then becomes how to find a hypergraph measure that, given the number of wiring layers, returns the minimum area on the placement layer necessary to embed the hypergraph.

Since congestion is a consequence of the interconnectedness of the netlist, it also seems reasonable that various measures of graph and hypergraph connectivity might inform this problem. The most common connectivity measures, edge and vertex connectivity, are too sensitive to local phenomena to measure global congestion. More promising candidates include tree- and pathwidth and the bramble number. In general, connectivity measures need to be adapted to account for the hypergraph structure, the delays, and the computational magnitude of the problem; as always, the challenge remains bridging the gap between theory and practice.

Effectively modeling the delay constraints is as large a stumbling block in this problem as in others, and congestion measures that incorporate delay information in a meaningful way are highly desirable.

Identifying Localized Congestion

In some cases, congestion may be localized. In other words, there may be identifiable substructures (of roughly 2,000 to 200,000 pins) in the netlist in which the confluence of numbers of pins, gates, signals, and shortness of delays makes that small piece of the netlist difficult to place and route, independent of the rest of the netlist. If such substructures could be identified, they could be placed and routed separately, or their delays reassessed or even redesigned, depending on the severity of the congestion.

A typical example of such localized congestion occurs in a crossbar switch. Conceptually, this is just a bipartite graph on two sets of pins, with every pin in one set of pins communicating with every pin in the other set. The difficulty lies in the nature of the communication, which is through an intermediary set of gates and signals, typically with very short delays. This intermediary set of gates and signals may or may not be regular and may or may not be the same for each pin on the left-hand side.

While some such configurations are readily identified, having been deliberately introduced to meet specific design requirements, other such snarls of interconnections evolve insidiously as part of the design process. These latter may not become apparent until they cause serious problems during the wiring process. Thus, a means of identifying them from the netlist information prior to placement and routing would be valuable.

One possible approach to this problem would be to consider the restrictions inherent in the topology of the wiring space. For example, obstruction sets for hypergraph planarity have recently been determined. It would be very useful to find the set of hypergraph obstructions in the wiring space, since such structures would then be known to be impossible to place and wire. Even a partial list of such obstructions would be of benefit to the industry, since structures containing any of them might then be avoided even in the design stage and thus would never appear in a netlist.

Automating Small Configurations

Some configurations (substructures of a netlist known as datapath structures) are relatively easy to place and route: The fanouts may be low and uniform; the logic may permit a simple left-to-right topology; there may be no, or very few, circuits formed. In such cases, common statistical models apply and can accurately predict the congestion of the design. Unfortunately, problematic configurations, such as the crossbar switches described above, still need to be placed and routed. Complications include irregular fanouts, many circuits, high interconnectivity. There are probably minimal layouts for some regular configurations such as butterfly switches for several examples on an integer grid model). However, the industry advances so rapidly that highly specific results may be obsolete even before implementation.

As when analyzing congestion, reasonable bounds for small configurations would be valuable here — for example, being able to analyze a small configuration and determine that, irrespective of delays, it will require a footprint of area at least A on the placement layer given that there are n wiring layers. Even better would be a constructive approach, which then provides a possible layout, for graphs with one-bend edges.

The “inverse” problem of determining whether it is possible and, if so, how to fit a given hypergraph into a fixed volume is also of interest. Significant progress has. recently been made for doing something very close to this, at least in the case of three-dimensional grid drawing. However, grid-drawings permit vertices to lie on any lattice point, not just the placement layer: They permit both vertical and horizontal movement on the wiring layers; and they apply only to graphs, not general hypergraphs. Thus, more work must be done to adapt such techniques to the exact demands of the placement and routing problem.

A wide range of other graph drawing techniques have been brought to bear not only on automating small configurations, but also on other aspects of the layout process, often with considerable success. A random sample of some recent techniques might include force-directed drawing, rectangular drawing, and orthogonal grid drawing. The important considerations are: applicability to the actual wiring space, modeling the delays, realizing the areas occupied by the gates, minimizing the footprint in the layout space, computational speed, and provable optimality.

The highly-effcient congestion estimator FaDGloR

======================================================

Placement and Routing Problem

================================================

The placement is done in three phases; partitioning, chip assignment and iterative improvement

================================================

Placement heuristic

================================================

Field Programmable Multi-Chip Module (FPMCM)

================================================

Technology mapping

================================================

Channel conflict-graph

Post-layout

via duplication problem

Ford-Fulkerson Algorithm

Wang, Chien-Fu 王建富: Post-layout multiple vias insertion 在佈局後多倍鑽孔的植入 July 2004 中華民國九十三年七月 p38.

Compaction
After completion of detailed routing, the layout is functionally complete. At this stage, the layout is ready to be used to fabricate a chip. However, due to non-optimality of placement and routing algorithms, some vacant space is present in the layout. In order to minimize the cost, improve performance and yield, layouts are reduced in size by removing the vacant space without altering the functionality of the layout. This operation of layout area minimization is called layout compaction

The compaction problem is simplified by using symbols to represent primitive circuit features, such as transistors and wires. The representation of layout using symbols is called a symbolic layout. There are special languages [Eic86, LM84a, Mat85] and special graphic editors [Hil84, Hsu79] to describe symbolic layouts. To produce the actual masks, the symbolic layouts are translated into actual geometric features. Although a feature can have any geometric shape, in practice only rectangular shapes are considered.

The goal of compaction is to minimize the total layout area without violating any design rules, maintaining good layout practices and without violating designer specified constraints. The last two objectives are usually motivated by performance verification. The area can be minimized in three different ways:

By reducing the space between features: This can be performed by bringing the features as close to each other as possible. However, the spacing design rules must be met while moving features closer to each other.

By reducing the size of each feature: The size rule must be met while resizing the features.

By reshaping the features: Electrical characteristics must be preserved while reshaping the feature.

Compaction tools are sometimes used as a layout aid. That is, layout is drawn in larger than minimum area. This reduces the design time. Compaction is then used to get a close to minimum area layout.

Final Checks 版图控制

DRC (Design Rule Check),

LVS (Layout vs Schematic)

IC mask generation process

IC mask generation

automatic IC mask generation

silicon compiler

mixed integer linear programming problem

user defined stick diagram

dimensionless topological representation of IC layout

branch and bound method

longest path algorithm on acyclic graphs

symbolic layout methods

  1. the fixed grid method
  2. the relative grid method

Mask Compaction

Specials

Genetic Algorithm

A genetic algorithm for PHYSICAL VLSI-DESIGN the physical design of VLSI-chips is presented. The algorithm simultane- The design-cycle of VLSI-chips consists of dierent consecutive steps from high-level ously optimizes the placement of the synthesis (functional design) to production cells with the total routing. The physical design is the the placement the detailed routing is process of transforming a circuit description done, while the global routes are opti- into the physical layout, which describes the mized by the genetic algorithm. This position of cells and routes for the intercon- is just opposed to the usual serial approach, where the computation of the nections between them.

Genetic algorithms are an iterative approach to placement. These types of algorithms attempt to achieve better and better optimization based on the biological evolution process. The algorithm starts with an initial placement and uses genetic operators to do the optimization. Three common operators are used by genetic algorithms: crossover, mutation, and inversion. Crossover, the main genetic operator, is used to combine two current configurations to produce a new configuration. Mutation, a background operator, is used to produce spontaneous random changes in various configurations. Inversion involves taking a random segment in a solution representation and flipping it. The rates of these genetic operators can be changed, automatically improving efficiency. Each of these types of genetic operators may be used in various ways to explore the solution space in a more efficient manner.

Another favorable optimization technique for module placement is the genetic algorithm (GA). These algorithms, like SA, are very useful in large-scale combinatorial placement problems. Genetic algorithms are normally very comparable to simulated annealing in both solution quality and speed of execution. Moreover, each algorithm has its general strengths and weaknesses with specific algorithms exhibiting better results over the other kind. The advantages of genetic algorithms over simulated annealing are as follows:

1. Concurrent search mechanism. GA works with a population of solutions and searches a large number of configurations from this population as opposed to SA which works with only one configuration at a time.

2. GA can learn from past trials of searching through the solution space. SA does not have this ability.

3. GAs allow the good features of candidate solutions to remain in helping to form better solutions.

4. GA can process inferior configurations without compromising the best ones.

The disadvantages are:

1. GA may require more memory space.

2. GA must have a good starting "genetic code" representation of initial layout or poor results may occur.

3. The crossover operator, the main operator in GA, must be able to avoid conflicts in combining 2 different configurations.

4. GA are unable to perform hill-climbing that might result in escaping local minima.

Evolutionary Algorithm

Shanavas Physical Design Optimization Using Evolutionary Algorithms p7

Memetic Algorithm

Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning.MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

SA is a simple algorithm and does not need much memory, but it takes a long time to reach the desired solution. Kernighan and Lin proposed a two-way graph partitioning algorithm which has become the basis for most of the subsequent partitioning algorithms. Fiduccia and Mattheyses modified the K-L algorithm to a more efficient algorithm by suggesting moving one cell at a time and by designing a new data structure separately. As a kind of global optimization technique Genetic Algorithm (GA) which borrows the concept of generation from biological system had been used for physical design problems like circuit partitioning, floorplanning etc. This technique has been applied to several problems, most of which are graph related because the genetic metaphor can be most easily applied to these types of problems. GA requires more memory but it takes less time than SA. Lots of researchers have proposed their theories to partition circuit using GA. Here proposed was a hardware genetic algorithm by developing GA and local search processor that uses some external memory to overcome problem of local maxima/minima. They expressed the probability of selection of chromosome as function of both the best and worst chromosome while others proposed different cost functions in order to achieve multiple objectives of minimizing delay, cutsize area and power. The authors proposed two GA one based on 0-1 encoding and other based on integer encoding. Number of enhancements like crossover operator mutation or choosing different fitness functions can still be made to achieve optimal solutions. This means that theory of GA still provides opportunities for new inventions that can help in inventing new solutions for physical design problems. A memetic algorithm to solve the graph partitioning and floorplanning problem. The algorithm incorporates several genetic algorithm features namely selecting a population and crossover of the selected chromosomes to get better stable solutions. The algorithm starts by incorporating the circuit as un-weighted connected graph in which each vertex represents gate and edge represents an interconnection between two gates and thereafter applying the GA metaphor to generate a partition that is highly interconnected within but disconnected from other sub partitions while trying to minimize the number of cuts and time consumed. This work tried to hybrid two algorithms like Genetic Algorithm and Simulated Annealing for overcoming the disadvantage of one another. Such type of algorithms are called memetic algorithm. This work addresses the problem of VLSI netlist partitioning with the objective of reducing delay and then floorplanning with the objective of reducing area to minimize the wirelength.

Neural networks

Simulated annealing

One attempt at improving the SA algorithm involves exploiting the probabilistic nature of the algorithm to reduce computation time by doing cost calculations approximately instead of exactly. Another attempt at improvement is the reduction of the search space of the placement problem and preventing the overlap between modules. The placement by this algorithm is comparable to conventional SA algorithms, but the improvement is manifested in the form of reduced computation time. Other improvements to SA include a cell clustering technique to improve computation time.

The SA algorithm has also been implemented with parallel processors with capability of integrated error control. An example of the parallel processor approach is an algorithm called heuristic spanning. It's used to replace the "hightemperature" portion of simulated annealing. The "lowtemperature" portion is sped up by the section annealing technique. Each processor is assigned a separate section to optimize and communicates its move with the other processors. Parallel processors can also achieve a hierarchial simulated annealing (HSA) method. This method divides a given problem into sub-problems applying the SA method at each stage. This feature makes it possible to automatically choose suitable parameters in the cost functions at each stage of computation.

The basic advantages of simulated annealing and the advantages over other placement algorithms are:

1. Ability to jump out of local minima by accepting uphill climbs and potentially falling into a more promising downhill path.
2. Highly suitable to problems having an increasing order of magnitude on the number of modules to be placed.
3. Ability to optimize a desired set of parameters through the use of a cost function.
4. Greater control of moving through the search space by use of a SA cooling schedule.
5. Only an initial random placement needed to obtain a solution.
6. Alleviates the need for complex mathematical calculations to place a module during the solution process.
7. May be applied to existing placement solutions for even further improvement.

The disadvantages of simulated annealing are:

1. Undeterministic solution. The probabilistic nature of choosing moves causes the solution to change during every execution.
2. Optimal cost functions may be very sophisticated, especially for large scale problems.
3. Smaller scale placement problems may be less efficiently solved (i.e. require more time) with SA than with other iterative algorithms.
4. SA algorithms still require large amounts of computation time for problems of high order.
5. A good cooling schedule is needed to obtain a good solution.

================================================

Simulated Sintering (SS)

Simulated sintering is used to solve these two problems and consists of two parts, starting with a "good" initial placement to improve computation speed and the inclusion of an optimal cooling schedule to control termination criteria. The "good" initial improvement is usually obtained by a fast heuristic algorithm. The choice of the algorithm depends on the problem at hand, but the time taken by the heuristic algorithm should be less than the time taken by the general SA algorithm to achieve the same result or no improvement will take place.

The cooling schedule controls the probability of accepting an uphill move in the SA technique and gives direction to the search through the solution space. Two types of cooling 12 schedules can be used, goal-directed and extended goal-directed.Goal-directed scheduling uses the cost of a minimal solution to a problem to determine uphill acceptance. Extended goal-directed scheduling is a variation on goal-directed scheduling which allows temperature to increase or decrease. Changing the temperature during the optimization process controls the speed and direction of the search (determined by the acceptance of an uphill climb). This is what the cooling schedule is designed for. A high acceptance rate (increasing the temperature) for an uphill climb is desirable during the initial stages of the optimization process, and a low acceptance rate (decreasing the temperature) is desirable during the final stages.

The success of simulated sintering hinges on the use of a good cooling schedule and the identification of an appropriate initial temperature. If the initial temperature is too high, then the SS algorithm deteriorates to simulated annealing and no improvement is achieved. If the initial temperature is too low, it results in a non-minimal solution. Thus, what is required is the ability to relate configuration costs (time and optimization quality) to temperature values and come up with a convergence criteria (determination of best solution). One possible solution is to base it on experience, but this attempt restricts itself to certain problem types and doesn't try to find a global solution process. Three convergence criteria used in simulated annealing can be controlled by simulated sintering. These criteria are listed as follows:

1. Converge when the number of accepted configurations, expressed as a percentage of the total number of configurations generated at a particular temperature, falls below a predetermined value.

2. Converge when the cost of current best configuration remains unchanged for a number of consecutive temperature values.

3. The ability to accept uphill moves is no longer required when all configurations accepted at a given temperature value have similar cost. Consequently, the SA algorithm can terminate or converge whenever the similar cost condition is detected.

Lienig, Jens: Physical design of VLSI circuits and the applications of genetic algorithm, 1997, p17 .......... 4

Terminology

minimax search strategy

the quadrature procedure of Breuer algorithm

Place and route produces the layout from the gate-level netlist and technology files.

schematic generator

transistor level schematic

gate level schematic

gate level netlist

transistor level netlist

spice netlist

CMOS netlists

bipolar netlists

================================================

Asynchronous design vs synchronous design

Literature

ABBOUD Mathematical Methods for Physical Layout of Printed Circuit Boards: An Overview p17

Algorithms For Vlsi Physical Design Automation.Sec p452

Almajdoub, Salahuddin A.: A Design Methodology for Physical Design for Testability, July, 1996, p150

Cadence Signal and Design Integrity April 2002 p56.ppt

@@@@@@@@@@@@@@@@@@@@@@@@@@

Cai, Hong: ROUTING CHANNELS IN VLSI LAYOUT, 1989, p143..........................

Chan, Tony F. et al: Multiscale Optimization in VLSI Physical Design Automation, 2005, p67

Channel & Switchbox Routing 2006-1-11 p18 .

Chen H. et al: Estimation of Wirelength Reduction for λ-Geometry vs Manhattan Placement and Routing, April 2003, p30

Cohoon, James et al: Evolutionary Algorithms for the physical design of VLSI circuits p31.

Coudert, Olivier: LOGICAL AND PHYSICAL DESIGN A FLOW PERSPECTIVE, May 2011, p32?

Cuong, Pham Quoc: PLACEMENT AND ROUTING ALGORITHMS FOR ASYNCHRONOUS LOGIC CIRCUITS, March 24, 2008, ............. p8

Dilli, Zeynep: PHYSICAL ASPECTS OF VLSI DESIGN WITH A FOCUS ON THREE-DIMENSIONAL INTEGRATED CIRCUIT APPLICATIONS, 2007, p263

Frisbee. Charles N.: An Overview of Placement and Routing Algorithms for PCB, VLSI, and MCM Designs p51, May 1996

Fudos, Ioannis et al: Placement and Routing in Computer Aided Design of Standard Cell Arrays by Exploiting the Structure of the Interconnection Graph, Computer-Aided Design & Applications, 5(1-4), 2008, 325-337, p13

Gao, Tong: Performance driven placement and routing algorithm, 1994, p157

Garg, Bikram: Partitioning, Floor Planning, Detailed Placement and Routing Techniques for Schematic Generation of Analog Netlist, Jan 2009 ......................

Hu, Jin et al: Taming the Complexity of Coordinated Place and Route p62.ppt.

Jariwala, Devang and Lillis, John: On Interactions Between Routing and Detailed Placement, 2003, p7.

JensJens VLSI Design smd154 Physical design back-end, ppt slides, p26..

Johar, Farhana & Salleh, Shaharuddin: Placement and Routing in VLSI design Problem Using Single Row Routing Technique, p22, MATEMATIKA, 2007, Volume 23, Number 2, 99-120

Joshi L14 Physical Design-Placement-and-Routing p40?......................??????????? 9

Khan, Aurangzeb: Physical Design Methodology Best Practices NANOMETER AND RTL-DOWN CLOSURE, April 9-10, 2001, p14

Kahng, Andrew B. et al: VLSI Physical Design From Graph Partitioning to Timing Closure, Springer, 2011, p319

Lan, Sanko et al: Placement and Routing For A Field Programmable Multi-Chip Module, 1994 ACM 0-89791-653-0/94/0006 3.50 .......................

Li, Lun: CHANNEL HEIGHT ESTIMATION IN VLSI DESIGN, 2002

Nam, Gi-Joon: Physical Design Optimization and Design For Manufacturability, 2009, p108

Pan, Min and Chu, Chris: FastRoute: A Step to Integrate Global Routing into Placement, ICCAD '06, November 5-9, 2006, San Jose, CA .............p8 ...........

Panda, Subrat Kumar: Physical design placement and routing p85

Physical design, June 2011, p74

Raj, A.Benuel Sathish: OPTIMISATION OF PLACEMENT AND ROUTING PROCESS IN XILINX XC4000 FPGA WITH 14X14 CLBs USING PSO, International Journal of Emerging Technology and Advanced Engineering, ISSN 2250-2459, Volume 2, Issue 7, July 2012) 474

Reda, Sherief: Physical Design of Digital Integrated Circuits, 2006, p40.

Sait, Sadiq M. & Youssef, Habib: chapter1 Introduction to VLSI Physical Design, September 2003, p42

Sarrafzadeh, Majid and Wong, C. K.: An Introduction to VLSI Physical Design, McGraw-Hill, 1996, p416 ...............20

Sarkar, Arnab: VLSI Physical design automation - introduction, partitioning and floorplanning, May 2008, p49

Schnecke, Volker: Genetic design of VLSI layout, 1995

Schnecke, Volker and Vornberger, Oliver: A GENETIC ALGORITHM FOR VLSI PHYSICAL DESIGN AUTOMATION, 2006

Shanavas, I. Hameem and Gnanamurthy, R. K. : Physical Design Optimization Using Evolutionary Algorithms, International Journal of Computer and Electrical Engineering, Vol. 4, No. 3, June 2012

Tehranipoor, Mohammad: Physical Design Automation of VLSI Systems, 7 October 2008, p20

Tzeng, Ping-San: Integrated placement and routing for VLSI layout synthesis and optimization 1991 p106

Vygen, Jens: Combinatorial Optimization in VLSI Placement and Routing p207...June 2006

橘昌良Layout DA Physical Design


Simulation

Simulation uses mathematical models to simulate the behavior of an actual electronic device or circuit. In general, people obtain typical input vectors (stimuli), track the propagation of these input values through the circuit, and check whether the simulated outputs are identical to the intended outputs of the circuit. Once mismatches are identified, the errors need to be localized and fixed. Simulations can be carried out at different levels (e.g., system level, RT level, or gate level). Usually, one cannot afford exhaustive simulation using all the input vectors because it would be very slow (the number of input vectors is an exponential function of the number of total inputs). Thus in practice, only a subset of all the input vectors is used. As a result, how to select such a subset becomes extremely important only the most relevant vectors should be selected for the maximum simulation coverage10, which then leads to high fault coverage. However, the downside of this compromise is that some corner case design errors may remain undetected if testing vectors are not properly selected.

Simulation is also widely used to analyze the timing of the circuit, especially for analog and mixed-signal circuits. Simulation-based timing analysis is able to consider the correlation among the circuits’ inputs and avoid timing analysis hurdles due to false paths. However, the main concern of this approach is its runtime complexity, especially for large and complex digital circuits. A popular replacement is the static timing analysis (STA), which is carried out in an input-independent manner and tries to find the worst-case delay of the circuit over all possible input combinations. The computational complexity is liner in the number of edges in the circuit netlist. However, due to the static feature of STA, it is vulnerable to false paths, which the STA may treat as critical, but in reality they may never be sensitized. A series of works have been dedicated to deal with this problem.

Prelayout Simulation

BAILEY, MARY L.: Parallel Logic Simulation of VLSI Systems p40

SRINIVASAN, RAMKUMAR: TECHNIQUES FOR ACCELERATING MICROPROCESSOR SIMULATION, May 2004


Design and Silicon Verification ICFormal Verification

Ideally, verification should be carried out after each implementation step to catch any design errors. Otherwise, the errors can propagate to the lower design levels and may eventually lead to faulty manufacturing masks, which then requires a design respin and generates a large cost overhead. Verification can be carried out in several different ways, namely simulation, formal verification, emulation, and post-silicon validation.

Design verification is essential to catching the errors before manufacturing and commonly accounts for half or more of the effort devoted to a chip.

As design representations become more detailed, verification time increases. It is not practical to simulate an entire chip in a circuit-level simulator such as SPICE for a large number of cycles to prove that the layout is correct. Instead, the design is usually tested for
functionality at the architectural level with a model in a language such as C and at the logic level by simulating the HDL description. Then, the circuits are checked to ensure that they are a faithful representation of the logic and the layout is checked to ensure it is a faithful representation
of the circuits. Circuits and layout must meet timing and power specifications as well.

A testbench is used to verify that the logic is correct. The testbench instantiates the logic under test. It reads a file of inputs and expected outputs called test vectors, applies them to the module under test, and logs mismatches.

A number of techniques are available for circuit verification. If the logic is synthesized onto a cell library, the postsynthesis gate-level netlist can be expressed in an HDL again and simulated using the same test vectors. Alternatively, a transistor-level netlist can be simulated against the test vector, although this can result in tricky race conditions for sequential circuits. Powerful formal verification tools are also available to check that a circuit performs the same Boolean function as the associated logic. Exotic circuits should be simulated thoroughly to ensure that they perform the intended logic function and have adequate noise margins; circuit pitfalls are discussed throughout this book.

Layout vs. Schematic tools (LVS) check that transistors in a layout are connected in the same way as in the circuit schematic. Design rule checkers (DRC) verify that the layout satisfies design rules. Electrical rule checkers (ERC) scan for other potential problems such as noise or premature wearout.

RTL

timing analysis,

physical verification,

testability analysis,

test vector generation

FPGA based Emulation and Validation.

Resolve critical issues in signal integrity, cross-talk, power, performance, Design for test (DFT), package design and simulation

Processor subsystem design and implementation, design for manufacturability (DFM) and signal integrity (SI) techniques to eliminate any problems before you commit to silicon. Stress test, test coverage analysis, device characterization and qualification across the full range of process parameters, process tuning and yield ramp along with package, test and production support.

芯片认证相关标准及流程，如AEC-Q100等；

硬件设计语言

HDL Verilog

Verilog HDL语言

硬件验证语言

System Verilog

SystemC

验证方法学

VMM

OVM

UVM

Verification Techniques and Tools

Testing vs. Verification – Verification and Design Reuse - Functional Verification, Timing Verification, Formal Verification, Linting Tools – Simulators – Third Party Models – Waveform Viewers – Code Coverage issue – Tracking Metrics.

测试机

J750、V50等

ATPG 和测试向量

Verification Plan

Verification plan – Levels of Verification – Verification Strategies – Specification Features – Test cases – Test Benches.

Stimulus and Response

Simple Stimulus – Output Verification – Self Checking Test Benches – Complex Stimulus and Response – Prediction of Output.

Architecting Test benches

Reusable Verification Components – VHDL and Verilog Implementation – Autonomous Generation and Monitoring – Input and Output Paths – Verifying Configurable Design.

System Verilog

Data types, RTL design, Interfaces, clocking, Assertion based verification, classes, Test bench automation and constraints.

Formal Verification

Instead of simulation, formal verification strives to prove the correctness of a circuit implementation using formal methods of mathematics. Used correctly, this method can decrease the verification time as well as guarantee the correctness. However, due to the intrinsic difficulty of the problem, this proof-based method cannot scale to very large designs. There are two main techniques for formal verification, namely Model Checking and Equivalence Checking. Model checking verifies that a design satisfies certain properties. It generally requires that the designer knows what desired properties the design should have. Equivalence checking compares two implementations (one of them is known to be correct) and proves that they are functionally equivalent. For example, two Boolean functions can be compared using their ROBDD (reduced ordered binary decision diagram) representations, and two finite-state machines can be compared using their state diagrams.

Emulation and Post-silicon Validation

Emulation is to implement a prototype of the design using a PLD. Once the prototype is completed, the verification process applies input vectors to the PLD and compares its outputs with the intended outputs. This is similar to simulation in principle, but is much faster due to the significant hardware acceleration effect provided by the hardware resources in the PLD. Thus, designers can afford to operate on more input vectors for better verification results. A drawback of this approach is that for each design, designers need to spend time and effort to come up with its prototype upfront before emulation starts (system-level and behavior-level design automation can speed up this process). Post-silicon validation uses actual fabricated chips and tests them at full speed. This method is obviously the fastest but is also the most expensive, among all the verification methods.


Miscellaneous Topics

In-design signoff extraction(3D)

Antenna diode


Floorplanning

or Chip Planning

Physical design begins with a floorplan. The floorplan estimates the area of major units in the chip and defines their relative placements. The floorplan is essential to determine whether a proposed design will fit in the chip area budgeted and to estimate wiring lengths and wiring congestion. An initial floorplan should be prepared as soon as the logic is loosely defined. As usual, this process involves feedback. The floorplan will often suggest changes to the logic (and microarchitecture), which in turn changes the floorplan?

The floorplanning stage ensures that (1) every chip module is assigned a shape and a location, so as to facilitate gate placement, and (2) every pin that has an external connection is assigned a location, so that internal and external nets can be routed.

Floorplanning also decides the IO structure, aspect ratio of the design.

Floorplan models can be classified in two categories: a) slicing floorplans and b) non-slicing floorplans.

=======================================

Hierarchical Floorplanning:

  1. Bottom-up clustering
  2. Top Down Placement
  3. Floorplan Optimization

=======================================

Floorplan Sizing

=======================================

Minimum-area floorplan:

=======================================

Cluster Growth:

=======================================

Linear ordering:

=======================================

Floorplannning based on Simulated Annealing

Simulated Annealing Algorithm (SA) which combines the Local Search Algorithm with the Metropolis algorithm.

================================================

Buffer Insertion

================================================

Sliceable floorplan

================================================

Non Slicing Floorplan

================================================

Floorplanning by Mathematical Programming

integer linear programming (ILP)

Linear Programming

Mixed Integer Linear Program

================================================

Sequence-Pair Based Floorplanning/Placement

================================================

BTREE representation

simulated annealing

adaptive fast simulated annealing

Combining global and local search

Memetic Algorithm

local search

evolutionary cycle

hierarchical design technique

Genetic algorithms

constructive techniques

advanced local search

================================================

http://workbench.lafayette.edu/~nestorj/cadapplets/fp/fpIntro.html

Batra, Deepak: Analysis of Floorplanning Algorithms in VLSI Physical Designs Design Sept 2012 p10

Chen, Tung-Chieh: Modern Floorplanning Based on B-Tree and Fast Simulated Annealing p14

Deyu Chapter 7 Floorplanning Aug 2013 p122

Kahng, Andrew B. et al: VLSI Physical Design From Graph Partitioning to Timing Closure Chapter 3 Chip Planning, Sept 2011, p88

Lim, Sung Kyu: floorplanning p85

Shanavas, Hameem et al: Hybrid Algorithmical Approach for VLSI Physical Design - Floorplanning November 2009 p3

Sowmya, B , MP, Sunil: Minimization of Floorplanning Area and Wire Length Interconnection Using Particle Swarm Optimization, August 2013, p10

Sur-Kolay, Susmita: VLSI Physical Design Automation Floorplanning 2, 02/18/11, p34


Partitioning

Partitioning has been an active area of research for at least a quarter of a century. The main reason that partitioning has become a central and critical design task today is due to the enormous increase of system complexity in the past and the expected further advances of microelectronic system design and fabrication. Widely accepted powerful high-level synthesis tools allow the designers to automatically generate huge systems by just changing a few lines of code in a functional specification. Synthesis and simulation tools often cannot cope with the complexity of the entire system under development and also designers want to concentrate on critical parts of a system to speed up the design cycle.

Thus the present state of design technology often requires a partitioning of the system with fast and effective optimization. Moreover, fabrication technology makes increasingly smaller feature sizes and augmented die dimensions possible to allow a circuit for accommodating several million transistors. However, circuits are restricted in size and in the number of external connections. So the fabrication technology requires partitioning of a system into components by arranging the blocks without wasting free space. The direct implementation of large circuit will occupy large area. Hence the large circuit is to be split into small sub-circuit. This will minimize the area of the system and the complexity of the system. When they are partitioned, the connection between two modules should be minimum (or the number net cut by the partition). This is known as cut size and hence this plays a major role in Partitioning. It is a design task by applying an algorithmic method to solve difficult and complex combinatorial optimization problems like breaking a large system into pieces.

Netlist partitioning

The process of converting a netlist into the physical design of a chip is traditionally broken into three phases:

  1. floorplanning, in which the very large and “special” functional elements are assigned locations in the chip area;
  2. placement, in which the remaining functional elements are assigned locations in the chip; and
  3. wiring or routing, in which the interconnect wires are assigned locations.

Because a netlist can contain several million pins, the most natural approach is to subdivide it into more manageable portions. The basic idea is to do the placement and routing of smaller pieces separately and then make the necessary connections between these larger components. The difficulty is that after these larger components have been placed, it may be problematic to route the connecting wires, or it may not be possible to meet the delays between pins in different components.

Thus, the goal is to partition the gates in the netlist so that a minimum number of signals have gates in different parts of the partition. Furthermore, the partitions cannot be very uneven in size. Since in this context the netlist is simply a hypergraph with the gates as the vertices and the signals as the hyperedges, this is a question of hypergraph partitioning. However, even graph
bisection into bounded sets is NP hard, and for the hardness of approximation, so optimal netlist partitioning is unfeasible.

Alpert and Kahng provide a comprehensive survey of both problem formulation and solution approaches to netlist partitioning. Combinatorial approaches include max flow/min cut, labeling, and covering. An important consideration in modeling the problem is that reducing the hypergraph structure to a graph model may fail to adequately capture essential characteristics, in particular the delays. For example, if the signals are converted to cliques, Ihler, Wagner, and Wagner have shown that there is no satisfactory assignment of weights to the clique edges to model the cost of cutting the hyperedge.

However, there are graph and hypergraph partitioning algorithms such as METIS and hMETIS that show experimental success. Also, for graphs, under certain conditions such as edge density, there are polynomial time approximation algorithms for NP problems, many based on the algorithmic version of the graph regularity lemma. Analogously, an algorithmic regularity lemma for hypergraphs was given and applied to hypergraph partitioning. The challenge remains in the possibility of adapting such techniques for practical application to the partitioning problem.

Leveraging the Hierarchy

One possible approach to the netlist partitioning problem is to use information from the conceptual hierarchy that results from the netlist design process. The netlist design team provides this potential partitioning of the netlist in the form of a logical design hierarchy. This nested hierarchy partitions the design in a way that is conducive to the netlist design challenge (creating and verifying the netlist from the design specifications) although not necessarily to the physical design (layout) task. Experienced design teams with adequate resources often create a netlist with a hierarchy that has a one-to-one mapping with an excellent physical partitioning. To the degree that this is not true (due to schedule constraints or lack of designer resources, for example), the physical design team tries to create a one-to-one mapping from the logical design hierarchy to physical design partitions. Figure 3 gives a simple example of a logical hierarchy that illustrates the inclusive relationships between different modules in the hierarchy. Here, the designer has chosen to break the “DSP” unit into a “MEM” unit and a “LOGIC” unit. All of the functional elements for the DSP are specified in that section of the netlist. Note, however, that there may be many signals connecting different nodes of the hierarchy tree — for example, connecting a functional element in the CACHE with another functional element in the MEM_CTL.

During the floorplanning process, a separate physical hierarchy is created, and a mapping from the logical hierarchy to this physical hierarchy is derived. The physical hierarchy is used to group together elements from the netlist that need to be physically close together. The physical hierarchy is often a proper subset of the logical hierarchy in that the physical hierarchy is a two-level hierarchy (a root with a complete cut set of the logical hierarchy tree as children). It is generally represented as a plan view of the actual chip, similar to the rooms of a house (thus, the term “floorplan”).

Ultimately, the goal is to determine which groupings in the hierarchy tree should remain together during the floorplanning process, and which should be subdivided or regrouped in order to minimize delays and routing difficulties. Treating this as an abstract problem, one possible approach would be to improve the initial design hierarchy incrementally and iteratively by implementing “local” operations — for example, those within a given level or between parent and child nodes — to transform the design hierarchy into a usable physical partition.

=============================================

Flow-based partitioning

netlist

Min-cut Partitioning

circuit partitioning

five components of netlist layout

  1. partitioning the netlist,
  2. leveraging the hierarchy,
  3. identifying congestion,
  4. measuring congestion, and
  5. automating small configurations.

=============================================

Kernighan-Lin (KL) Algorithm

Kernighan-Lin algorithm

  • Input: Graph representation of the circuit
  • Output: Two subsets of equal sizes
  • Bisecting algorithm :
    • Initial bisection
    • Vertex pairs which gives the largest decrease in cutsize are exchanged
    • Exchanged vertices are locked
    • If no improvement is possible and some vertices are still unlocked then vertices which give smallest increase are exchanged

=============================================

Memetic approach in VLSI circuit partitioning

Memetic Algorithm

Memetic approach in VLSI circuit partitioning

A new approach Memetic Algorithm is described in this section to solve problem of circuit partitioning pertaining to VLSI.

A model to solve circuit partitioning

==============================

Simulated Evolution / Simulated Annealing

==============================

Genetic algorithm

==============================

Evolutionary time series model for partitioning using Neuro-Memetic approach

An evolutionary time-series model for partitioning a circuit is discussed using Neuro Memetic algorithm owing to its local search capability. Sample Data Set

Neuro-Memetic Model:

Neuro-memetic model makes it possible to predict the sub circuit from circuit with minimum interconnections between them.

Development of Neural Network: In the context of recognition of sub circuit with minimum interconnection, the 3-layer neural network is employed to learn the inputoutput relationship using the MA. The layers of input neuron are responsible for
inputting. The number of neurons in this output layer is determined by the size of set of desired output, with each possible output being represented by separate neuron.

================================================

Neuro–EM and neuro-k mean clustering approach for VLSI design partitioning

==================================================

Ants colony Optimization (ACO)

==================================================

Clustering approach for VLSI circuit partitioning

==================================================

Clustering followed by min- cut partitioning

==================================================

Min- Cut Partitioning

min cut for graph partitioning

==================================================

Iterative improvement min cut partitioning

The KL FM Algorithm

The Lookahead LA Algorithm

==================================================

Numerical optimization

==================================================

Probability Based Partitioner - PROP

Alpert, Charles J.and Kahng, Andrew B.: Recent directions in netlist partitioning a survey, 1995, p81

Batra, Deepak and Malik, Dhruv: PARTITIONING ALGORITHMS IN VLSI PHYSICAL DESIGNS - A REVIEW p5

Caldwell, Andrew E.; Kahng, Andrew B.; Kennings, Andrew A. and Markov, Igor L.: Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting April 1999 p6

Caldwell, Andrew E.; Kahng, Andrew B. and Markov, Igor L.: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning 2000 p16

Caldwell, Andrew E.; Kahng, Andrew B. and Markov, Igor L.: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning 2000 p21

Chan Spectral k way ratio-cut partitioning and clustering p6.pdf

Dutt, Shantanu and Deng, Wenyong: A Probability based Approach to VLSI Circuit Partitioning Sept 2006, p19

Hagen On Implementation Choices for Iterative Improvement Partitioning Algorithms p7.pdf

Johannes, FrankM.: Partitioning of VLSI Circuits and Systems 1996 p5

Sawicki, Sandro et al: 3D-Via Driven Partitioning for 3D VLSI Integrated Circuits DECEMBER 2010 p11 .

Tan Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis p22

Wu Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques p10

胡云 基于概率增益的电路划分算法 p5


Placement

Placement is the process of physically arranging electronic functions (library cell circuits, integrated circuit (I.C.) chips, module components, etc.), on a planar surface (silicon substrate, printed circuit board (PCB), multichip module (MCM))
in a desired manner. Thus, placement is a process ranging from the macrolevel (i.e. I.C. chips) to the microlevel (i.e. multichip
modules).

A placement algorithm can be defined as a procedure for physically arranging all electronic functions on a planar surface
such that minimum wiring and minimum area result. Therefore, the algorithm tries to satisfy a desired optimization. Other
optimization criteria include minimizing delay, minimizing parasitic capacitance and inductance couplings (in the case
of a PCB), and meeting thermal considerations such as the designer's heat dissipation requirements. It should be noted
that no one placement algorithm achieves a complete optimization, and the choice of a placement algorithm depends on the designer's objectives and goals. Typically, algorithms are combined or adapted to interact with one another to gain further improvement. The choice of a placement algorithm can also affect the level of circuit testing quality

Recent advances in placement algorithms include (i) high-performance wirelength-driven placement, (ii) mixed-sized placement (i.e., simultaneous placement of both cells and macros), (iii) routability-driven placement, (iv) timing- and power-driven placement, as well as (v) the integration of global placement into physical synthesis.

There are basically two main classes of placement algorithms: iterative and constructive.

Iterative placement algorithms operate by creating a very crude placement and improving it in a step-by-step fashion. Constructive placement algorithms, in complete contrast to iterative placement algorithms, try to place modules one at a time in a position that is usually not far from the final solution. The significant part of a constructive algorithm spends time calculating the position of each module and is, thus, computationally intensive.

Most algorithms available today adapt known methods to achieve the designer's goals, or they are optimized to increase
efficiency of characteristics such as computation time or better placement.

Placement algorithms can also be described as being rigor or heuristic. Rigor consists of step-by-step computations until
a solution or optimal solution is found. However, these computations can be too costly when time is a limitation.

Therefore, heuristic algorithms are implemented. Heuristic algorithms have evolved from inductive reasoning based on past
experience instead of mathematical rigor. The heuristic process is designed to capitalize on the statistical properties of "real"
circuits.

Placement methods can be classified roughly into three categories:

  1. recursive minimum cut placement,
  2. analytical placement and
  3. local search methods.
  4. Manhattan distance

====================================

Traditional placement methods can be generally divided into four categories.

Stochastic approaches

are usually based on simulated annealing. Despite good solution quality, the runtime is quite long.

Min-cut approaches

comprises recursive problem partitioning and local optimum solution. However, improper partitioning would cause unrecoverable
quality loss.

Quadratic approaches,

approximate the net length using quadratic functions which enables gradient-based minimization. By solving the system, cells are dragged away from over-filled regions with quadratic wirelength overhead. Nonetheless, the modeling accuracy remains a long-term issue.

Nonlinear approaches

refer to the algorithms using nonlinear optimization framework. Wirelength and density are modeled by smooth mathematical functions where gradient can be analytically calculated. Due to the high computation complexity, nonlinear approaches usually employ multi-level cell clustering with quality overhead introduced.

===========================================

Global ?Placement? /? Detailed Placement

global placement algorithm

Global Placement Timing Optimization

Detailed Placement

Lagrange multipliers

SIMPLIFIED PLACEMENT PROBLEM

Global Placement

Placement approaches in practice

  1. simulated annealing: start with any placement and try to improve it (mostly used in the 80s)
  2. min-cut: successive bisection, with simple exchange heuristics (mostly used in the 90s)
  3. analytical placement: minimize either linear or quadratic netlength estimate, then work towards disjointness (dominant strategy today)

====================================

Detailed placement

Detailed placement, or legalization, considers standard cells only; all others are fixed beforehand. The task is to place the standard cells legally without changing the (illegal) input placement too much. Detailed placement does not only arise as a finishing step during the overall placement flow, but also in interaction with timing optimization and clock tree insertion. These steps add, remove or resize cells and thus require another legalization of the placement that has become illegal.

Due to technology constraints cells cannot be placed with arbitrary y-coordinates. Instead, they have to be arranged in cell rows. Cells that are higher than a cell row must be fixed before detailed placement. Thus we can assume unit height and have the following problem formulation:

====================================

The standard-cell placement problem

  • min-cut placement
  • simulated annealing
  • analytical methods
  • force-directed approaches

clustering and flow-based methods

algorithm is based on the Depth First Search (DFS) strategy

============================================

macro placement

Macro placement uses minimum cost flow, branch-and-bound, and greedy techniques.

Assume that we want to place rectangular macros numbered c1; : : : ; cn, with widths w1; : : : ;wn and heights h1; : : : ; hn within an area [xmin; xmax] X [ymin; ymax]. The objective function is weighted bounding box netlength. If we fix a relation rij Œ{W; S;E;N} for each 1 =< i < j <= n, then this can be written as linear program:

====================================

Iterative Algorithms.

Many iterative-based algorithms exist for placement and typically use a simulation of a natural process to perform the
optimization. Criteria (i.e. design goals) also play an important role. The force-directed method is a common iterative
approach. The algorithm treats each module as a point mass, and the interconnecting nets as springs, of weighted force
constant. A few modules are assumed fixed and the rest are allowed to move around until they assume a minimum "energy"
configuration. The term "energy" is defined as a function of intermodule spacing and connectivity. The process of "relaxing"
the system repeats itself until the module movements become negligible. Another method similar to the preceding is called
the attractive and repulsive force method (AR method). The "scatter-and-gather" method is an example of combining
several algorithms and techniques together to accomplish floor planning of IC chips. The "scatter" phase uses the force directed method and also unconstrained cluster growth (UCG) and constrained cluster growth (CCG). CCG considers size and aspect ratio of the package as fixed, and the center of the package always coincides with the center of mass of the cluster. The"gather" phase tries to solve a geometric problem called minimal box embedding (MBE) which consists of two solution techniques: GBS (growing box scheme) and RBS (reducing box scheme). Speedup techniques called incremental transform/sorting and quadrant folding are also used.

================================================

Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization

flat nonlinear placement algorithm FFTPL

====================================

QUADRATIC ASSIGNMENT PROBLEM

quadratic placement and multisection

VLSI Placement by Quadratic Programming and Slicing Optimization

new placement method based on simultaneous quadratic programming combined with improved partitioning schemes and exhaustive slicing optimization

conjugate gradient method with incomplete Cholesky pre-conditioning

HITCHCOCK TRANSPORTATION PROBLEM

Macro placement uses minimum cost flow, branch-and-bound, and greedy techniques.

PLACEMENT LEGALIZATION PROBLEM

seaof-gates design systems

min-cut placement procedure for sea-of-gates circuits

macrocell circuit

standard cell circuits

weighted estimated wiring length

Manhattan-metric minimum spanning trees

simulated annealing

Analytical placement

netlength

linear and quadratic netlength

straight-line embeddings of planar graphs

combine algorithms for minimizing netlength with recursive partitioning

wirelength

shortest rectilinear Steiner tree connecting the pins

multisection

netlists

Linear Placement

2D Placement

Placement and Routing with Standard Cells

Placement Objective Functions

net model

bb

steiner

mst

clique

star

slack, Lagrange multipliers

minimum cost flow problem

Quadratic placement (QP)

local search

Global Placement by successive partitioning

Remove overlaps by successive quadrisection

Fractional relaxation: Hitchcock (transportation) problem

Successive shortest path algorithm

quadratic, partitioning based placement algorithm

simulated-annealing

quadratic or force-directed

min-cut

nonlinear programming

PROUD: A SEA-OF-GATES PLACEMENT ALGORITHM

GENERIC GLOBAL PLACEMENT AND FLOORPLANNING (KRAFTWERK)?

FASTPLACE: EFFICIENT ANALYTICAL PLACEMENT USING CELL SHIFTING, ITERATIVE LOCAL REFINEMENT AND A HYBRID NET MODEL

Quadratic Assignment Problem

Placement algorithms

such as Simulated Annealing

Simulated Evolution

Breuer

Cluster Growth

Advanced Genetic algorithm

approach cooperating Kernighan-Lin and Breuer

====================================

Finally, even after a designer has found a very optimal placement algorithm for their problem, the final decision will be based on one or more limiting factors. These factors may include the following:

1. Module shapes.

2. Hardware available (i.e. memory space).

3. Electromagnetic (EM) factors.

4. Thermal considerations.

5. Modification concerns.

6. Testability requirements.

7. Obstacles.

Typically, these factors may necessitate the need for a less optimal algorithm in order to satisfy some limitations. In conclusion, wisely applying a placement algorithm ultimately relies upon obtaining a solution that meets design criteria, but consideration for the "right" placement algorithm can result in a solution in less time and with lower manufacturing costs.

====================================

routing driven placement

========================================

Gordian Placement Flow

Ajami, Amir H. and Pedram, Massoud: Post-Layout Timing-Driven Cell Placement Using an Accurate Net Length Model with Movable Steiner Points 1998 p6

Areibi, Shawki and Yang, Zhen: Congestion Driven Placement for VLSI Standard Cell Design December 2003 p31.pptx

Brenner, Ulrich: Theory and Practice of VLSI Placement September 2005 p164

Chanak, Thomas Stephen: NETLIST PROCESSING FOR CUSTOM VLSI VIA PATTERN MATCHING November 1995 p105 .

Chang, Y.-W.: unit5 Placement p80

Egeblad, Jens: Placement Techniques for VLSI Layout Using Sequence-Pair Legalization, July 1st, 2003, p240

Egeblad Placement Techniques for VLSI Layout Using Sequence-Pair Legalization p240

Granacki, John and Kazi, Tauseef: An Automatic Placement Tool for Rapid Prototyping of Printed Circuit Boards November, 1993 p21

Keutzer, Kurt: The Physical Placement Problem in Integrated Circuits p33

Leiserson, Charles E and Pinter Ron Y: Optimal placement for river routing 1981 p18

Lu, Jingwei et al: FFTPL An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization, Dec 2013, p4

Prabhakar, Rachapudi et al: Optimized Routing Methods for VLSI Placement Design Dec. 2012 p5

Sait, Sadiq M. et al: Cell Assignment in Hybrid CMOS Nanodevices Architecture Using a PSOSA Hybrid Algorithm October 2013 p12

Viswanathan Placement techniques for the physical synthesis of nanometer-scale integrated circuits p160

Vorwerk, Kristofer: On the Use of Directed Moves for Placement in VLSI CAD 2009 p155


Routing

Current Status

  • All router technologies discussed in this lecture are employed
  • Current focus is on using ungridded/area-based routers to do detailed routing
  • Chip-level routing is a top concern. Performance is limited by chip-level nets
  • Timing driven routing is important
  • Safe (noise resistant/immune) routing is another important topic

================================================

In VLSI layout design, it is required to realize a specified interconnection of a set of terminals present in different modules, primarily using minimum possible area. This is known as routing problem.

Routing is also an NP complete problem that is generally separated in two phases using the divide and conquer paradigm: a global routing that balances the densities of all routing channels, and a detailed routing that assigns specific wiring segments for each connection. These two phases avoid congestion and optimize the performance of the circuit, making sure all nets are routed minimizing wirelength and capacitance on the path. By running both algorithms a complete routing solution can be created. Of course there are a number of routing algorithms that solve the problem using a mixed routing, both global and detailed routing at the same time, based on the idea that a higher integration of the two phases can prevent inaccurate estimation and the routing result will be better. The drawback of this approach is that as circuit size grows this mixed routing becomes more complex and less scalable.

========================================

The Routing Problem

Apply after placement

Input:

  • Netlist
  • Timing budget for, typically, critical nets
  • Locations of blocks and locations of pins

Output:

Geometric layouts of all nets

========================================

Objective:

Minimize the total wire length, the number of vias, or just completing all connections without increasing the chip area.

Each net meets its timing budget.

=======================================

Routing Constraints

100% routing completion + area minimization, under a set of constraints:

  • Placement constraint: usually based on fixed placement
  • Number of routing layers
  • Geometrical constraints: must satisfy design rules
  • Timing constraints (performance-driven routing): must satisfy delay constraints
  • Crosstalk?
  • Process variations?

=======================================

Types of Routing Algorithms.

Routing algorithms can be grouped into several broad categories, although there are some algorithms that are hard to classify. The first type of routing algorithms to be studied were called maze-routers, because they use maze searching techniques to find paths between two terminals.

A maze router first searches the cells that are closest to the starting terminal, and then proceeds in a breadth first manner by searching the cells adjacent to those that have already been searched. When the connecting terminals have been found, the search stops and the wire is created. The precise path depends on the order in which neighboring cells are searched. Maze routers will always find a path, if one exists, and the path found is guaranteed to be of minimum length. However, these two points apply only to an individual net at the time it is being routed. Maze routers do not guarantee that the total length of all wires will be minimized, or that a complete routing for the entire circuit will be found, even if one exists. The problem is that nets routed early tend to block cells that are needed by nets routed later. This problem has been attacked in several different ways. Some algorithms will move blocking wires aside, or remove them entirely and attempt to reroute them later. These last algorithms are usually called "rip-up" routers. Other algorithms allow the most difficult nets to be placed manually. However, the most widely used approach is to avoid the use of maze-routers altogether, or to use them to route those few nets that cannot be routed by other methods.

The channel router is an efficient alternative to the maze-router, but it is designed to work in a more restricted environment. While maze-routers place no restrictions on the size or shape of the wiring area or on the position of the terminals, channel routers assume that the wiring area (called a channel) is rectangular with fixed terminals at the top and bottom and no terminals at the right or left. In spite of this, channel routers have become the workhorse of the IC industry, so a detailed discussion of these types of routers is warranted.

A variation on the channel router is the switch-box router. A switch-box is a rectangular area with fixed terminals on all four sides (as opposed to a channel which has floating terminals on the right and left). Switchbox routing tends to be more complex than channel routing, although several good algorithms have been developed.

There are many other classes of routing algorithms, most of which are designed to solve specialized problems such as power-and-ground routing or single layer routing.

========================================

Lee-Moore router

To date, Lee-Moore routing has dominated the approaches taken for application of special-purpose parallel hardware to accelerate routing. These single instruction multiple data (SIMD) array processor architectures are designed specifically to accelerate grid-search based algorithms. One of the first uses of a multiple instruction multiple data (MIMD) computer for routing was the Wire Routing Machine developed by Hong et al. . This special-purpose architecture has 64 microprocessors configured as an 8 X 8 mesh on which a two-phase algorithm (global routing followed by detailed routing) is implemented. The global routing phase is based on Lee-Moore routing and uses an exponential channel density metric to avoid overflows. The speedup due to parallelism is reported as modest. This is due in part to the low power of the processor nodes and to the fact that the global routing phase does not make efficient use of the processors because only one net is globally routed at a time.

Other approaches intended for general-purpose parallel computers make use of algorithms (e.g., simulated annealing and channel routing) that are best suited to a few tightly connected processors, because they require large amounts of interprocessor communication to keep a global data structure up to date in order to achieve good routing quality. In contrast, our approach, which is intended for many loosely coupled processors, reduces expensive communication traffic by keeping the global information local to each processor throughout the hierarchical decomposition of the global routing step. While this approach results in a low efficiency for the global routing step, the overall algorithm achieves high efficiency and produces good-quality routing. We have not seen any other routing algorithms that both have high efficiency and produce good-quality routing running on large distributed-memory multiprocessors.

=======================================

hierarchical routing algorithm

=======================================

parallel routing algorithm

=======================================

SEGA routing algorithm

=======================================

critical nets

=======================================

simultaneous routing

=======================================

Tile Expansion Shortest Path router

=======================================

XRouter

=======================================

integer linear programming formulation

approximation algorithms for min-max resource-sharing problems

block problems and virtual layer method

Undirected partitioning formulation

Interconnect Synthesis

"net ordering"

"rip-up & re-route" techniques

wire sizing and spacing

Signal integrity

Elmore delay technique

=======================================

Mathematical design

Watanabe, Hiroyuki: IC Layout Generation and Compaction Using Mathematical Optimization, 1984, p124

Maze
Zheng, Si-Qing et al: Efficient Maze Running and Line Search Algorithms for VLSI Layout, 1993, p8

Maze routing

Lee Algorithm

The exploration phase of Lee’s algorithm is an improved version of breadth-first search.The search can be visualized as a wave propagating from the source:
· The source is labeled ‘0’ and the wave front propagates to all the unblocked vertices adjacent to the source.
· Every unblocked and unlabeled vertex adjacent to the source is marked with a label ‘1’.
· Every unblocked and unlabeled vertex adjacent to the vertices with a label ‘1’ is marked with a label ‘2’ and so on.
· This process continues until any vertex in list target is reached.
A vertex is blocked if all paths are not allowed to cross it. Otherwise, it is unblocked.
Hence the result of Lee’s algorithm is the shortest path from the source point to a destination point. This path may contain a lot of intersection points and therefore may not the best one in our criteria (as described in section 1). Thus, Lee’s algorithm is not suitable for logical layout.

Lee router

Lee Maze router

Lee-Moore router

Lee-Moore Algorithm (Maze Routing)

Improvement by rip-up and re-route

============================

Maze routing finds a path b/w source (s) and target in a planar graph
Grid graph model is used to represent block placement
Available routing areas are unblocked vertices, obstacles are blocked vertices
Finds an optimal path
Time and space complexity O(hXw)

Maze routers abstract the channel routing problem with a grid-based model. Wires are restricted to follow paths along the grid lines. Routing is accomplished by laying down wires on the grid one at a time. Obstacles are modeled as disallowed portions of the grid. Therefore, maze routing can handle arbitrary obstacles.

Basic idea -- wave propagation method(Lee, 1961)
Breadth-first search
Back-tracing after finding the shortest path
guarantee to find the shortest path

Given:

A planar rectangular grid graph.

Two points S and T on the graph.

Obstacles modeled as blocked vertices.

Problems with Maze Routing

Slow: for each net, we have to search NxN grid

Memory: total layout grid needs to be kept NxN

Objective:

Find the shortest path connecting S and T.

This technique can be used in global or detailed routing (switchbox) problems.

===========================

Algorithm

add source node S into list

costS = 0

for all nodes i on list

if i == destination D

pathcost = costD

break

for j=N,S,E,W neighbors that are not visited and not occupied

add node j to list

costj = costi+1

mark i as visited

remove node i from list

while i != S do

mark i as path

i = min cost N,S,E,W visited neighbor

===============================

THE LEE ALGORITHM FOR MAZE ROUTING

The Lee algorithm is a classical routing technique; it is the basis of many routing programs.
The one-layer version is presented.
Main points:
* the routing area is a grid of squares.
* a square available for routing is white, one that is an obstacle is black.

the goal is to connect all nets.

a two-point connection is realized by propagating
a wave front from the source terminal outwards until the target terminal is reached.
* the shortest-connection is found by backtracking from the target to the source.
* in the case of multi-terminal nets: first two terminals are connected, this connection is the target for the wave propagation from the third terminal, etc.
* a routed net is an obstacle for the next nets.

Evaluation:
* the algorithm always finds a connection if a connection exists.
* for two-terminal nets, this connection is the shortest possible; for multi-terminal nets the connection need not be the shortest possible (remember: the ‘‘minimal rectilinear Steiner tree’’ problem is NP-complete).
* it can be generalized for multiple layers: wave front expansion in three dimensions.
* its time complexity and space complexity is O(n2).
* the quality of its result strongly depends on the ordering of the nets.

Maze routing and its variations Lee, Robin, Hadlock, Soukup, Ohtsuki

Rip-up and Re-route

– H.Shin and A.Sangiovanni-Vincentelli, "Mighty: A 'rip-up and re-route' detailed router," Proc. ICCAD, 1986
– Incremental router
– Path finder
? Maze routing is used to find the minimum cost path between two pins
? Build a list of nets with the order of ascending cost
? Vertical (horizontal) wire on horizontal (vertical) layer is penalized
? Changing a layer is penalized to minimize the number of vias
– Path conformer
? After all paths have been found, implement the path according to the order
? If the path is not feasible, call path finder
? If no path is found or cost is too high, call weak modifier

Tangjittaweechai, Lalinthip et al: Parallel VLSI Detailed Routing Using General- Purpose Computing on Graphics Processing Unit, IEEE, 2012

==============================

Multilayer maze router

===============================================

Line probe routing

Line probe routers scan in the x and y directions searching for line segments from either the source or the destination. Scan lines do not project beyond obstacles, so obstacles are avoided by a subsequent probe of the line segments orthogonal to the ones from the previous pass.

Mikami&Tabuchi IFIPS Proc, Vol H47, pp 1475-1478, 1968

==============================================

Mikami+Tabuchi’s algorithm

Generate search lines from both source and target (level-0 lines)
From every point on the level-i search lines, generate perpendicular level-(I+1) search lines
Proceed until a search line from the source meet a search line from a target

Will find the path if it exists, not guaranteed to find the shortest path
Time and space complexity: O(L), where L is the number of line segments

==============================================

Hightower’s algorithm

Difference: generate search level-(i+1), search lines which are extendable beyond the obstacle.
Faster, but does not guarantee a connection

Non-Manhattan Steiner tree heuristic

Non-Manhattan Routing

Non-Manhattan routing is primarily employed on printed circuit boards (PCBs)

? Route planning using octilinear Steiner minimum trees (OSMT)
? Generalize rectilinear Steiner trees by allowing segments that extend in eight directions
? More freedom when placing Steiner points

Octilinear Steiner Tree Algorithm

Input: set of all pins P and their coordinates
Output: heuristic octilinear minimum Steiner tree OST
OST = ?
T = set of all three-pin nets of P found by Delaunay triangulation
sortedT = SORT(T,minimum octilinear distance)
for (i = 1 to |sortedT |)
subT = ROUTE(sortedT [i ] ) // route minimum tree over subT
ADD(OST,subT ) // add route to existing tree
IMPROVE(OST,subT ) // locally improve OST based on subT

? Recall that Manhattan routing is dictated by the limitations of modern semiconductor manufacturing for thin wires
? PCB routing is not subject to those limitations
? Can use shorter connections
? Non-Manhattan connections
? Diagonal (45- or 60-degree) segments in addition to horizontal and vertical segments
? Create more freedom to place Steiner points
? Octilinear Steiner Tree construction
? Algorithms are generally adapted from the Manhattan case
? Should produce results that are at least as good as the Manhattan case

Non Manhattan Steiner Tree Construction
================================

Non-minimal Routing

Non-minimal routing

  • Wormhole degrades performance while VCT has less secondary effects
  • Fault tolerance is the main motivator

Classes

  • Search-based algorithms
  • Virtual channel-based routing
  • Turn-based routing
================================

QCA routing

Track assignments for multi-terminal nets induce varying numbers of crossings, and formulates crossing minimization, heuristically, as a weighted-minimum-feedback-edge-set problem.
================================

Uniform Random Algorithm

Weighted Random Algorithm
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Adaptive Routing
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Dimension-Order Routing
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Oblivious Routing
================================

Deterministic routing
================================

parametrisized VLSI routing cell
================================

λ-Geometry Routing [Burman et al. 1991]
================================

line search technique of Hightower or Mikami

the cellular routing method of Hitchcock

the stepping aperture technique of Lass

================================

relaxed linear programming for wire routing

================================
Multilevel Full-Chip Routing with Testability and Yield Enhancement

Area Routing

? The goal of area routing is to route all nets in the design
? without global routing
? within the given layout space
? while meeting all geometric and electrical design rules
? Area routing performs the following optimizations
? minimizing the total routed length and number of vias of all nets
? minimizing the total area of wiring and the number of routing layers
? minimizing the circuit delay and ensuring an even wire density
? avoiding harmful capacitive coupling between neighboring routes
? Subject to
? technology constraints (number of routing layers, minimal wire width, etc.)
? electrical constraints (signal integrity, coupling, etc.)
? geometry constraints (preferred routing directions, wire pitch, etc.)

? Area routing: avoiding the division into global and detailed routing
? Doing everything at once, subject to design rules
? Small netlists with complicated constraints
? Analog, MCM and PCB routing
? Manhattan vs Euclidean paths
? Euclidean paths are no longer than Manhattan, usually shorter
? Unique Euclidean shortest path
? Multiple Manhattan paths
? When Euclidean shortest paths intersect, there may exist Manhattan shortest paths that do not (not vice versa)
? Net ordering is important in area routing
? Rule 1: nets with higher aspect ratio (less flexible) routed first
? Rule 2: nets surrounded by other nets (more constrained) routed first
? Rule 3: nets with more pins inside other net's bounding boxes routed first

Congestion Estimation and Removal Methods

Alpert, Charles J. and Tellez, Gustavo E.: The Importance of Routing Congestion Analysis, May 2010, p14.pdf

Large single net routing

Power (VDD) and Ground (GND) routing

Knock Knee Routing

Another, weaker restriction within 2-layer rout- ing is the knock knee routing where a 90 degree turn within the same layer is possible. Wires in dierent layers can, therefore, cross or share cor- ners (i.e. knock knees) but are not allowed to overlap for any distance.

==================================
Channel routing in knock knee mode

==================================

x-Density Routing

Formal definition – decision problem

  • Given an integer x, a set of two-terminal nets N and a grid graph G(V,E)
  • Does there exist a single bend routing for every net ni in N 1 < i < |N| such occupancy(e) ≤x for every edge e ∈E?

Polynomial time solvable - O(|N| log |N|) time

Finding the maximum subset of nets is much harder

x-Density Pattern Route Heuristic (x-DPR)

The x-DPR heuristic

  • Find a set of x-Density routable nets
    • Set should be x-Density with “large” nets
  • Pattern route the x-Density nets
  • Maze route the remaining nets
  • Rip and reroute nets
    • Do not consider the x-Density nets

Predictable Routing

Smallest-First Pattern Routing (SFPR)

1.Sort two-terminal nets based on BB (smallest to largest)

2.Pattern route x% of the smallest nets

3.Maze route remaining nets

4.Rip up and reroute phase

Do not consider the pattern routed nets

Pattern routing

Use simple patterns to connect the terminals of a net

Simplest pattern is single bend routing

  • Given a two-terminal net, single bend routes are the two distinct 1-bend routes
  • Sometimes called L-shaped routing

Parallel routing

parallel multi-threaded collision-aware global router based on Maze Routing Algorithm using a heuristic collision-prevention approach.

Parallel VLSI Detailed Routing

Parallelization of VLSI routing algorithms

prim’s algorithm

Planar routing

If all the interconnections have to be realized in a single layer (k = 1, see above) then we speak about planar routing, otherwise about multilayer (or k-layer) routing.

(General) River Routing Algorithm

General River Routing Problem

  • A special case of single-layer routing problem.
  • All terminals lie on the boundary of the region.
  • All nets are two-terminal nets.
  • There are no blocks in the region.
  • Nets must be planar.

==================================

One Layer Routing: General River-Routing

  • For clock, power, ground routing still may need to solve single-layer routing
  • Two possible paths per net along boundary
  • path is alternating sequence of horizontal and vertical segments connecting two terminals of a net
  • Consider starting terminals and ending terminals
  • Assume every path counter-clockwise around boundary
  • Create circular list of all terminals ordered counterclockwise according to position on boundary
  • Boundary-Packed Solution
  • Flip corners to minimize wire length

=============================================

General River Routing Algorithm

  • Routing in arbitrary shaped rectilinear routing regions
  • Gridless-based
  • Nets are routed one-by-one.
  • Each net is routed as close to the boundary as possible in counterclock direction.
  • Guarantees to find a solution if one exists.
  • The algorithm consists of following phases:
    • 1. Starting Terminal Assignment
    • 2. Net Ordering
    • 3. Path Searching
    • 4. Corner Minimization

=============================================

Power minimization

Power & Ground

Power and ground routing
Power and Ground Routing
– Usually on a single layer (no vias)
--> planar routing
– Usually much wider (more current)
– MOSAICO
? macrocell place and route system
? Assume power and ground rings around the chip
? Before placement, decompose power and ground nets into smaller nets
? Merge the nets after global routing
? Find power requirement
? After symbolic detailed routing, find the sub-net (power and ground) widths

Clock Networks / Clock-Tree Routing

? A clock routing instance (clock net) is represented by n+1 terminals, where s0 is designated as the source, and S = {s1,s2, … ,sn} is designated as sinks
? Let si, 0 ≤ i ≤ n, denote both a terminal and its location
? A clock routing solution consists of a set of wire segments that connect all terminals of the clock net, so that a signal generated at the source propagates to all of the sinks
? Two aspects of clock routing solution: topology and geometric embedding
? The clock-tree topology (clock tree) is a rooted binary tree G with n leaves corresponding to the set of sinks
? Internal nodes = Steiner points 7.4.1

Modern Clock Tree Synthesis

? A clock tree should have low skew, while delivering the same signal to every sequential gate
? Clock tree synthesis is performed in two steps:
(1) Initial tree construction with one of these scenarios
? Construct a regular clock tree, largely independent of sink locations
? Simultaneously determine a topology and an embedding
? Construct only the embedding, given a clock-tree topology as input
(2) Clock buffer insertion and several subsequent skew optimizations

Constructing Trees with Zero Global Skew

H-tree
? Exact zero skew due to the symmetry of the H-tree
? Used for top-level clock distribution, not for the entire clock tree
? Blockages can spoil the symmetry of an H-tree
? Non-uniform sink locations and varying sink capacitances also complicate the design of H-trees

Method of Means and Medians (MMM)
? Can deal with arbitrary locations of clock sinks
? Basic idea:
? Recursively partition the set of terminals into two subsets of equal size (median)
? Connect the center of gravity (COG) of the set to the centers of gravity of the two subsets (the mean)

Recursive Geometric Matching (RGM)

? RGM proceeds in a bottom-up fashion
? Compare to MMM, which is a top-down algorithm
? Basic idea:
? Recursively determine a minimum-cost geometric matching of n sinks
? Find a set of n / 2 line segments that match n endpoints and minimize total length (subject to the matching constraint)
? After each matching step, a balance or tapping point is found on each matching segment to preserve zero skew to the associated sinks
? The set of n / 2 tapping points then forms the input to the next matching step

Exact Zero Skew

? Adopts a bottom-up process of matching subtree roots and merging the corresponding subtrees, similar to RGM
? Two important improvements:
? Finds exact zero-skew tapping points with respect to the Elmore delay model rather than the linear delay model
? Maintains exact delay balance even when two subtrees with very different source-sink delays are matched (by wire elongation)

Deferred-Merge Embedding (DME)

? Defers the choice of merging (tapping) points for subtrees of the clock tree
? Needs a tree topology as input
? Weakness in earlier algorithms:
? Determine locations of internal nodes of the clock tree too early; once a centroid is found, it is never changed
? Basic idea:
? Two sinks in general position will have an infinite number of midpoints, creating a tilted line segment – Manhattan arc
? Manhattan arc: same minimum wirelength and exact zero skew
? Selection of embedding points for internal nodes on Manhattan arc will be delayed for as long as possible

Clock Tree Buffering in the Presence of Variation

? To address challenging skew constraints, a clock tree undergoes several optimization steps, including
? Geometric clock tree construction
? Initial clock buffer insertion
? Clock buffer sizing
? Wire sizing
? Wire snaking
? In the presence of process, voltage, and temperature variations, such optimizations require modeling the impact of variations
? Variation model encapsulates the different parameters, such as width and thickness, of each library element as well-defined random variables

? Similar to signal-net routing, except for
? Very large numbers of sinks
? The need to equalize propagation delays from the root to sinks
? Longer routes (to satisfy the equalization constraint)
? Typical algorithms determine topology first, then geometric embedding
? Clock skew
? Consider propagation delay from the root to each sink
? Skew is the maximal pairwise difference between delays (over all pairs of sinks)
? May be limited to sinks that are within distance d > 0 (local skew)
? For a specified wire delay model
? ZST: Zero-Skew Tree routing requires that skew = 0
? BST: Bounded-Skew Tree routing requires that skew < Bound

Modern Clock Tree Synthesis

? Initial clock tree construction
? Topology determination (MMM or RGM)
? DME embedding (different flavors for ZST and BST)
? Working with the Elmore delay model requires more effort than working with linear delay models
? Geometric obstacles (e.g., macros)
? May require detours
? Can be handled during DME (complicated) or during post-processing (often achieves as good results)
? Clock-tree optimization
? Buffer insertion
? Buffer sizing
? Wire sizing
? Wire snaking by small amounts
? Decreasing the impact of process variability

Literature

Bazargan EE5301-Routing p121.ppt ..................10

Borah, Manjit; Owens, Robert Michael and Irwin, Mary Jane: An edge based heuristic for Steiner routing, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 13, NO. 12, DECEMBER 1994, p6..................2

Cadence Space-based Router p4 June 2008

Cai, Hong: ROUTING CHANNELS IN VLSI LAYOUT p143 1989

Chen, Huang-Yu and Chang, Yao-Wen: CHAPTER 12 Global and detailed routing Nov 2008 p64

Cong Routing in Integrated Circuits p35.PDF

Corporaal A Scalable VLSI MIMD Routing Cell, 1991, p8.

Coudert, Olivier and Shi, C.-J. Richard: Exact Multi-Layer Topological Planar Routing p5.

DAS, Sandip: Routing algorithms for channels switchboxes and MCMs in VLSI layout design 1999 p137.

Dion, Jeremy: Fast Printed Circuit Board Routing 1988 p33.

Flaig, Charles M: VLSI mesh routing system May 1987, p31.

Friedman, Eby G.: On-Chip Interconnect The Past Present and Future, March 10, 2006, p68.

Haruyama, Shinichiro: New routing strategies for VLSI Dec 1990 p158

Hassoun, J. Qiu S. and Reda S.: Fast Accurate A Priori Routing Delay Estimation p23.. July 2010

Hentschke, Renato Fernandes: Algorithms for wire length improvement of VLSI circuits with concern to critical paths p175

Ho, Tsung-Yi 何宗易: mSIGMA A Multilevel Full-Chip Routing System Considering SIGnal-integrity and MAnufacturability p75

Kahng-routing p61.ppt

Kahng, Andrew B. et al: VLSI Physical Design From Graph Partitioning to Timing Closure Chapter 7 Specialized Routing p61, Dec 2011

R. Kastner, E. Bozogzadeh, and M. Sarrafzadeh. Predictable routing. In Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, pp. 110-113, 2000.

Kastner, Ryan; Borzorgzadeh, Elaheh and Sarrafzadeh, Majid: Predictable Routing, ICCAD, Nov 5, 2000, p17.pptx

kchoi Routing p38 Nov 1999

Li, Katherine Shu-Min et al: Multilevel Full-Chip Routing with Testability and Yield Enhancement Sept 2005, p45

Lienig, Jens: A Parallel Genetic Algorithm For Performance-Driven VLSI Routing,

Lim, Sung Kyu: Steiner Routing - ECE6133 Physical Design Automation of VLSI Systems, Jan 2008, p85.

Lim, Sung Kyu: Multi-net Routing p70, April 2009

Lu-Routing-Jan2011 p17

Mandoiu, Ion I.: Approximation Algorithms for VLSI Routing, August 2000, p101

Marek-Sadowska, Malgorzata: On Old and New Routing Problems p21

Maurer, Peter M.: AUTOMATIC ROUTING OF INTEGRATED CIRCUIT CONNECTIONS A TUTORIAL, 2002-03-29, p14

Müller, Dirk: Fast Resource Sharing in VLSI Routing, September 2009, p167.

RITCHEY, LEE W. , EDGE, SPEEDING: PCB ROUTERS AND ROUTING METHODS , DECEMBER 1999

Sayed, Moustafa A. et al: Interconnect Synthesis in High Speed Digital VLSI Routing p33 Int. J. Open Problems Compt. Math., Vol. 2, No. 3, September 2009

Schulte, Christian: Design Rules in VLSI Routing, June 2012, p86

Smith CH17 ROUTING, Aug 1998, p26

Szeszler, David: Combinatorial Algorithms in VLSI Routing 2005 p78.

Szeszler Combinatorial Algorithms in VLSI Routing p78

TEP, ALIFF BIN MOHD: POWER DISSIPATION IN VLSI WIRE ROUTING USING PARTICLE SWARM OPTIMIZATION TECHNIQUE, 7 December 2010, p196

van den Akker, Marjan et al: : Routing for analog chip design at NXP semiconductors p19 May 2011

Venkatesvaran R and Mazumder P: Routing algorithm for VLSI design 1991 p108

Wu, Di et al: Layer Assignment for Crosstalk Risk Minimization, Nov 2003, p4 .

Yoshikawa, Masaya and Otani, Kazuo: Ant Colony Optimization Routing Algorithm with Tabu Search p4

Zhang, Tianpei: Routing Issues in Nanometer-scale Integrated Circuits A PhD Dissertation September 2006 p160..............

Zhang, Yanheng: Handling the complexity of routing problem in modern VLSI design 2011 p121.


Detailed Routing or Local Routing

Detailed routing

In the physical design process for very large scale integrated (VLSI) circuits the logical structure of a circuit is transformed into its physical layout.

Because of the problem complexity, VLSI routing is usually divided into global routing and detailed routing. In the global routing stage, rough routing decisions are made based on G-Cell-to-G-Cell (e.g., global routing cell) connection on a global routing grid graph. Detailed Routing, on the other hand, realizes exact routing paths considering geometrical constraints based on the global routing solution.

Detailed routing is an important stage in the sense that it is directly related to the routing completion and design rule satisfaction. It also impacts many design metrics such as timing, manufacturability, etc.

Detailed routing is one of the tasks in this process.

  • Finds actual geometric layout of each net within assigned routing regions.
  • No layouts of two different nets intersect on the same layer.
  • Problem is solved incrementally, one region at a time in a predefined order.

A detailed router connects pins of signal nets in a rectangular region in accordance with a set of routing constraints, such as the number of layers, the minimal space between wires, minimum wire width, number of vias, crosstalk and the net length. The results of this detailed routing has a strong influence on the fabrication yield and production costs of the circuit.

Detailed routing has generally evolved out of four basic approaches: maze routing, line probe routing, left-edge routing, and greedy channel scanning. The problem is formulated as a routing area containing connection points or pins on a rectilinear (usually rectangular) region or channel. Pins can be located on any of the four sides of the region or within the region. The connection points are generally constrained to reside in certain layers to make them easier to connect to.

Even single-layer routing problems are NP-complete, which means that an optimal solution cannot be achieved in a reasonable time.

For this reason, detailed routing solutions are heuristic in nature. The factors in determining a solution’s usability are the number of terminals, net width, via restrictions, boundary shape, number of layers, and net types such as power, ground, and clock wires.

In the detailed routing problem our task is to interconnect certain given subsets (or nets) of the pins (or terminals) of these devices by wires.

To sum it up from a graph-theoretical viewpoint, the detailed routing problem consists of finding vertex-disjoint Steiner-trees (trees with a given terminal vertex set) in a 3-dimensional rectangular grid.

=============================================

Detailed Routing Stages

? Assign routing tracks
? Perform entire routing – no open connection left
? Search and repair – resolving all the physical design rules
? Perform optimizations, e.g. add redundant vias (reduce resistivity, better yield)

=============================================

Routing Considerations

  • Number of terminals (i.e. two terminal vs. multiterminal nets)
  • Net width (i.e. power and ground vs. signal nets)
  • Via restrictions (i.e. stacked vs. conventional vias)
  • Boundary type (i.e. regular vs. irregular)
  • Number of layers (i.e. two vs. three layer model)
  • Net types (i.e. critical vs. non-critical nets)

=============================================

Routing Models

  • Grid-based model
    • 1. A grid is super-imposed on the routing region.
    • 2. Wires follow paths along the grid lines.
  • Gridless model
    • 1. Any model that does not follow this `gridded' approach.

====================================================

Routing approaches

Sequential approaches
? Maze searching
? Line searching
Concurrent approaches
? Network-flow based algorithms
? Linear assignment formulation
Drawback: hard to handle larger problems

====================================================

CHARACTERIZATION

Local routing is characterized by a number of parameters (each parameter setting defines a distinct problem type):
* the number of wiring layers,
* the orientation of wire segments in a layer: horizontal, vertical, diagonal or some combination of these,
* gridded or gridless routing,
* presence or absence of obstacles in routing area,
* stretchable or fixed routing area,
* the constraints on the positions of the terminals: two parallel lines, along a rectangle, arbitrarily in an area, etc.
* terminals with a fixed or floating position.

=============================================

Channel and switchbox routing with minimized crosstalk - a parallel genetic algorithm approach

Grid-based model
  1. A grid is super-imposed on the routing region
  2. Wires follow paths along the grid lines
  3. Pitch: distance between two gridded lines
  4. Most commonly used

Line routing
Line searching

Line Routing
– D.W.Hightower, "A solution to line routing problems on the continuous plane," Proc. 6th Design Automation Workshop, 1969
– Gridless (often implemented on a grid)
– Manhattan
– Definitions
? Escape line: pair of orthogonal lines passing through a point
? Cover: Blockage of a point. Intersects with an escape line.
? Escape point: A point on an escape line that is not covered by a horizontal (vertical) cover

Algorithm
? Starting from the source and sink, generate escape lines and determine escape points until escape lines intersect

Line Search Routing Algorithm

Mikami - Tabuchi Line Search Routing Algorithm

Multi-terminal Nets: Different Routing Options

two-terminal vs. multi-terminal nets

Connecting a Multi-Terminal Net

In general, maze and line-probe routing is not suitable to multi-terminal nets

Several attempts made to extend to multi-terminal nets

  • Connect one terminal at a time
  • Use the entire connected paths as source to expand.
  • Improve the quality of the solution (remove a segment and re-connect)
  • Results are sub-optimal
  • Inherit time and memory cost of maze and line-probe algorithms

=============================================

Multi-terminal Nets: Different Routing Options

(a) Steiner Tree (14)

(b) Steiner Tree with Trunk (15)

(c) Minimum Spanning Tree (16)

(d) Chain (17)

(e) Complete Graph (42)

Over-the-block detailed router

The over-the-block detailed router used in PA_Route uses a completely different approach based on a graph. The graph represents horizontal and vertical constraints of the wires.

Single active layer routing problem

Single Row Routing
  • Single Row Routing Algorithm
    • (a) Basic Single Row Routing Algorithm
    • (b) Algorithm for Street Congestion Minimization
    • (c) Algorithm for Minimizing Doglegs
  • Basic Single Row Routing Algorithm
    • Nets are represented by intervals.
    • Nets or segments of nets above reference lines are mapped onto paths in the upper street while those below reference lines are mapped onto paths in the lower stree.

The triangular routing model

lambda routing problem

Sequential routing

Problems with Sequential Routing Algorithms

  • Net ordering:
    • we have to route net by net, but it is difficult to determine the best net ordering!
    • Difficult to predict/avoid congestion
  • What can be done:
    • Use other routers
      • channel/switchbox routers
      • hierarchical routers
    • Rip-up and re-route

Full-chip routing

full chip gridless routing

Multilevel Full-Chip Routing

Multilevel Full-Chip Routing Framework

Lin and Chang, “A novel framework for multilevel routing considering routability and performance,” ICCAD-2002 (TCAD, 2003).
Multilevel framework: coarsening followed by uncoarsening.
Coarsening (bottom-up) stage:
? Constructs the net topology based on the minimum spanning tree.
? Processes routing tiles one by one at each level, and only local nets (connections) are routed.
? Applies two-stage routing of global routing followed by detailed routing.
? Uses the L-shaped & Z-shaped pattern routing.
? Performs resource estimation after detailed routing to guide the routing at the next level.
Uncoarsening (top-down) stage
? Completes the failed nets (connections) from the coarsening stage.
? Uses a global and a detailed maze routers to refine the solution.

parallel genetic algorithm
parallel genetic algorithm for channel and switchbox routing

Branch and bound

? B.W.Kernighan, D.G.Schweikert, and G.Persky, "An optimum channel-routing algorithm for polycell layouts of integrated circuits," Proc. 10th Design Automation Workshop, 1973
? Select a leftmost net that satisfies the vertical constraint
? If the current track t is filled, compute the lower bound b
? If t+1+b >= V (V is the best solution seen so far), replace the most recently placed net by the next unplaced net s=0; t=1; V=n; place: do while track t is not full & last net is not placed
place next leftmost legal net on track t;
s=s+1; netlist(s)=net placed;
if track t is full
compute b=lower bound on tracks needed for remaining nets;
if t+b < V
t=t+1; goto place;
unplace netlist(s); goto place;
if n-th net is placed
record new solution; V=t;
unplace netlist(s); unplace netlist(s);
goto place;

Integer programming formulation called Integer Programming Based Approach

Routing Grid Models

Parallelization of VLSI routing algorithms

Info Sources

!!!!!!!!!!!!!!!!!!!!!!!

http://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/

http://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/magma_tutorial/magma_tutorial.html

http://nptel.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_II/magma_tutorial/magma_tutorial3.html

http://www.actionpacked.com/products/Routing

http://forums.arcgis.com/threads/93646-Detailed-Routing-Information

http://www.baanboard.com/baanboard/showthread.php?t=5492

http://www.computer.org/csdl/proceedings/vlsid/2012/4638/00/4638a233-abs.html

!!!!!!!!!!!!!!!!!!!!

http://www.edaboard.com/

http://www.edaboard.com/forum.php

http://www.edaboard.com/thread126141.html

!!!!!!!!!!!!!!!!!!!!!!!!

http://www.edacafe.com/

http://www10.edacafe.com/book/ASIC/CH17/CH17.php?interstitial_displayed=Yes

http://www.scai.fraunhofer.de/en/business-research-areas/optimization/project-archives/vlsi-routing.html

http://adsabs.harvard.edu/abs/2011SPIE.7974E..20M

!!!!!!!!!!!!!!!

http://www.mentor.com/

http://www.mentor.com/products/ic-manufacturing/resources/overview/self-aligned-double-patterning-sadp-friendly-detailed-routing-3b4256ab-aafb-42ca-9f9f-015d9c499c6c

http://wiki.mikrotik.com/wiki/Manual:Multicast_detailed_example

!!!!!!!!!!!!!!!!!!!!

http://www.moralfiber.org/eylon/berkeley/cs270/

http://www.necdsx.com/dsx_software_manual_out/features/direct_inward_dialing_feature/direct_inward_dialing_intercept_and_overflow.html

!!!!!!!!!!!!!!!!!!!!!!!!!

http://opencircuitdesign.com/

http://opencircuitdesign.com/qrouter/

http://www.routerforums.com/project-plans-how/44637-homemade-router-table-fence.html

!!!!!!!!!!!!!!!!!

http://iroi.seu.edu.cn/

http://iroi.seu.edu.cn/books/asics/Book2/CH17/CH17.2.htm

!!!!!!!!!!!!!!!!!!

http://www.ece.ubc.ca/~stevew/

http://www.ece.ubc.ca/~stevew/routing.html

https://kfs.ucdavis.edu/kfs-help/default.htm?turl=WordDocuments%2Fviewingroutingdetails.htm

!!!!!!!!!!!!!!!!!!!!!!

http://vlsicad.ucsd.edu/index.html

http://vlsicad.ucsd.edu/Presentations/talk/supporting.html

!!!!!!!!!!!!!!!!

http://www.informatik.uni-osnabrueck.de/

http://www.informatik.uni-osnabrueck.de/papers_html/

http://www.informatik.uni-osnabrueck.de/papers_html/galesia_95/main.html

http://www.informatik.uni-osnabrueck.de/papers_html/galesia_95/node4.html

!!!!!!!!!!!!!!!

http://vlsi.pro/

http://vlsi.pro/physical-design-flow-iv-routing/

Literature

Bazargan EE5301-Routing p121

Chang, Y W.: Unit 7 Detailed Routing, May 21, 2013???????p50?????

Chang, Y W.: Unit 7 Detailed Routing, May 21, 2013???????p99 ?????

Cho, Minsik et al: ELIAD: Efficient Lithography Aware Detailed Router with Compact PostOPC Printability Prediction p6 DAC 2008, June 8–13, 2008

Golda, Bence: Implementation of VLSI Routing Algorithms, IEEE 6th International Conference on Intelligent Engineering Systems, Opatija, 2002, p6

Kahng, Andrew B. et al: VLSI Physical Design From Graph Partitioning to Timing Closure Chapter 6 – Detailed Routing p76, Dec 2011

Lemieux, Guy G. and Brown, Stephen D.: A Detailed Routing Algorithm for Allocating Wire Segments in Field-Programmable Gate Arrays, Jan 6, 2008 ................ p12

Lienig, Jens: Channel and switchbox routing with minimized crosstalk - a parallel genetic algorithm approach p6 1997

Marwedel, Peter: Layout-Synthese Detaillierte Verdrahtung Kanalverdrahtung- p29.ppt 2008/07/09

Pan, David: VLSI Physical Design Automation, Detailed Routing (II), 2014

RECSKI, Andras: Some polynomially solvable subcases of the detailed routing problems in VLSI design, Jan 2014

Sur-Kolay, Susmita: VLSI Physical Design Automation Detailed Routing I p31, 02/18/11

Tangjittaweechai, Lalinthip et al: Parallel VLSI Detailed Routing Using General- Purpose Computing on Graphics Processing Unit p4 2012

Venkateswaran R and Mazumder P: Routing algorithm for VLSI design p108 May 2012 ...(90/91?).

Vygen, Jens: Detailed Routing, Hangzhou, March 2009 Zhang, Yanheng and Chu, Chris: RegularRoute: An Efficient Detailed Router with Regular Routing Patterns, Jan 2011 ........... p46

Zli Detailed Routing Parameter Documentation p217 January, 2007


Channel Routing

Best VLSI channel router

Best VLSI channel routing algorithm

Most used VLSI channel router

Most used VLSI channel routing algorithm

Most appropriate VLSI channel router

Most appropriate VLSI channel routing algorithm

Most efficient VLSI channel router

Most efficient VLSI channel routing algorithm

Most promising VLSI channel router

Most promising VLSI channel routing algorithm

Recently developed VLSI channel routing algorithm

Answer:

Genetic

Evolutionary

Memetic Algorithm

Topological Channel Routing Using Constraint Logic Programming

Low-Latency Virtual-Channel Routers

YACRIT: Yet Another Channel Router

Over-the-cell

Greedy router

Efficient Hybrid Approach to Channel Routing Problem

Graph based algorithm

Single phase three-layer channel routing algorithms

Multi-layer Channel Routing

Routing in the Third Dimension: From VLSI Chips to MCMs

Channel Routing for Integrated Optics

Crossing-Aware Channel Routing for Photonic Waveguides

===========================================

Since its introduction in 1971, "channel routing" has become a very popular method of routing integrated circuits. This is an effective approach since it decomposes the overall routing problem into a number of simpler problems. Typically, the wiring area is first divided into disjoint "rectangular channels." A "global router" then determines which channels each net traverses. Finally, a "channel router" computes a detail routing for each channel.

===========================================

(Burstein and Pelavin, 1983; Deutsch, 1976; Hashimoto and Stevens, 1971; Ho et. al., 1991; LaPaugh, 1980; Pal, 2000; Pal et. al., 1995; Pal et. al., 1993; Pal et. al., 1998; Reed et. al., 1985; Rivest and Fiduccia, 1982; Schaper, 1989; Szymanski, 1985; Yoshimura and Kuh, 1982)

http://www.cs.cmu.edu/~jab/pubs/propo/node19.html

http://www.vpiphotonics.com/App_LinkConf_Routing.php

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A channel is a rectangular routing region that has two open ends (left and right) and has two rows (upper and lower) of fixed points called terminals. Terminals are assumed to be aligned vertically in columns that are usually equispaced along the length of the channel. A set of terminals that need to be electrically connected together is called a net. A vertical wire segment is a wire that lies in a column, whereas a horizontal wire segments is a wire that lies in a track in a grid-based reserved layer Manhattan routing model. Tracks are
horizontal lines that are usually equispaced along the height of the channel, parallel to the two rows of (fixed) terminals.

A route for a net is a collection of horizontal and vertical wire segments spread across the different layers connecting all the terminals of the net. A legal wiring of a channel is a set of routes that satisfy all the prespecified conditions where, no two wire segments used to connect different nets overlap on the same conducting layer. A legal wiring is also called a feasible routing solution.

The Channel Routing Problem (CRP) is specified by two m-element vectors TOP and BOTTOM, and a number t; objective is to find a feasible routing solution for the channel using no more than t tracks, if it exits. Let Li (Ri) be the leftmost (rightmost) column position of net ni, then Ii=(Li,Ri) is known as its interval (or span).

We know that in Manhattan routing model we can only use horizontal wire segment and vertical wire segments to interconnect the nets. In grid-based Manhattan routing, horizontal wire segments are assigned to the different rows and vertical wire segments are assigned to the different columns. The layer with only horizontal wire segments is called horizontal layer (H) and the layer with only vertical wire segments is called vertical A Review On Channel Routing On Vlsi Physical Design www.iosrjournals.org 42 | Page layer (V). In the case of multi-layer we place the horizontal and vertical layers alternatively. The connection between the layers is done through via hole.

If the number of layer is even then there must be same number of vertical and horizontal layers. This model is called ViHi model. If the number of layers is odd then there are two possible models. First model is ViHi+1 model. In this model, first layer is horizontal layer and next vertical and next again horizontal layer and so on. Second model is Vi+1Hi model. In this model first layer is vertical layer and next horizontal and next again vertical layer and so on.

These are horizontal constraint graph (HCG), vertical constraint graph (VCG) and horizontal non-constraint graph (HNCG).

The channel routing problem must be solved heuristically, and there are heuristics that appear to work much better in practice than the left-edge algorithm. The simplest of these is doglegging. A dogleg is a vertical wire segment that connects two trunks. Doglegging allows nets to be assigned to two or more trunks, which tends to produce more compact routings, than the "pure" left-edge algorithm. Doglegs are typically used only at the net's terminal positions, because this produces only one extra via. A dogleg at any other position would produce two extra vias. Furthermore, the nets that tend to cause problems are usually those that have many terminals, thus breaking trunks at terminal positions tends to reduce the harmful effects of such nets.

Other techniques of note are the greedy channel router, the hierarchical channel router, and YACR2.

Regardless of which technique is used to route the channel, it is a simple matter to extend the algorithm so that a net can be routed out of the left or right edge, at an arbitrary position. It is also possible to extend the algorithm to route nets from the left edge to the right edge, even though the net has no terminals in the channel. The importance of these two features will be explained in the next section. It is often necessary to add a second routing step to the channel router, primarily to resolve cyclic vertical constraints. If a channel router cannot complete some nets (because of cyclic constraints) the unrouted nets can be completed using a maze router. This step is usually referred to as cleanup routing.

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Introduction to Channel Routing

? Channel routing is a special case of the routing problem.
? Apply a ‘divide-and-conquer’ strategy.
? Used in the design of custom chips as well as uniform structures such as gate-arrays and standard-cells.
? Very popular because it is efficient and simple, and guarantees 100% completion.

Channel may have exits at left and right sides, but exit positions are not fixed
? We may map exits to either lower or upper edge of a channel
? One dimensional problem

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CHANNEL ROUTING ALGORITHMS
* The channel routing problem is NP-hard.
* One heuristic is to use the left-edge algorithm while trying to satisfy the vertical constraints.
* The Lee algorithm will not perform very well if used directly (there is too much freedom initially; wrong decisions are taken, blocking
future connections). However, it can be used within an iterative algorithm or as a postprocessing step for other algorithms.
* There are many algorithms based on other heuristics.

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Terminology for Channel Routing Problems

  • Net list:
  • Terminal
  • Upper boundary
  • Lower Boundary
  • Channel
  • Dogleg
  • Branches
  • Trunks
  • tacked vias

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Approaches to Channel Routing

? Most techniques are based on the left-edge algorithm with several extensions and variations of this.
? In this algorithm tracks are processed one at a time.
? In this lecture we will present the basic Left Edge Algorithm.
? Then, the dogleg algorithm proposed by Deutch which performs splitting of nets is described.
? Finally another technique that uses merging of nets proposed by Yoshimura and Kuh is explained.
? All the above techniques aim at reducing the total number of horizontal tracks required to perform channel routing.

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Channel Routing Problem Formulation

  • Assignments of horizontal segments of nets to tracks.
  • Assignments of vertical segments to connect
    • 1. horizontal segments of the same net in different tracks, and
    • 2. the terminals of the net to horizontal segments of the net.
  • Horizontal and vertical constraints must not be violated.
    • 1. Horizontal constraints between two nets: The horizontal span of two nets overlaps each other.
      2. Vertical constraints between two nets: There exists a column such that the terminal on top of the column
      belongs to one net and the terminal on bottom of the column belongs to the other net.
  • Objective: Channel height is minimized (i.e., channel area is minimized).

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Design of Typical Channel Routers

Channel routers are classified by the number of layers they are designed to exploit and how they route wires within these layers. The latter determines if a router is grid-based and if it uses a reserved layer model. Grid-based routers place a regular grid — to which doglegs and trunks musst conform — over the channel. The wires are all the same width, the width of the largest component, usually a via. With gridless routers doglegs and trunks can occupy any location in the channel and wires can differ in width according to their electrical requirements. This increased flexibility comes at a computational cost, however. Reserved layer routers require that wires consist of a single dogleg or trunk, with doglegs and trunks assigned to different layers as specified by the router. Unreserved layer routers have no such restrictions; a dogleg or trunk can be on any layer. This allows greater flexibility in routing wires and can significantly decrease final channel height. It also makes the problem significantly more difficult. For these reasons many channel routers use a grid-based, reserved-layer model. In contrast, the technique proposed in this work is gridless and unreserved-layer.

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Channel Routing for Different Styles

? For Gate-array design, channel widths are fixed. The goal is to finish routing of all the nets.
? For Standard-cell and Full-custom design, channels are expandable. The goal is to route all nets using the minimum channel width.

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Constraints of CRP and their Significance

The channel routing problem (CRP) is the problem of computing a feasible route for the nets so that the number of tracks required (and hence the channel area) is minimized. We say that a routing solution is feasible if all the nets can be assigned without any conflict. We assume that in a feasible routing solution, the routing wires do not extend beyond the left and right ends of the channel. Therefore, in order to minimize the routing area, the horizontal wire segments of the nets need to be distributed amongst a minimum number of tracks. This process of assignment of the horizontal wire segments to tracks is guided by two important constraints, viz., the horizontal constraints and the vertical constraints.

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Graph representations:

?Vertical Constraint Graph (VCG)
?Horizontal Interval Graph (HIG)

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Benchmarks for testing new algorithms

For channel routing problems, Deutsch's examples were used extensively as benchmarks for testing new algorithms. However, it is also extremely important to test the performance of channel routing algorithms on a wider variety of difficult examples.

For channel routing problems, Deutsch's examples were used extensively as benchmarks for evaluating the performance of new algorithms, especially the so-called Deutsch's Difficult Example (DDE)

Special Channel Routing Algorithms

2 (Two) Layer Channel Routing? 1986 ...............ok

Click to learn more ...

3 (Three) Dimensional Channel Routing? 1986 ??? ok

3 (Three) layer channel routing? 1984 ................ok

Single phase three-layer channel routing algorithms

Three-Layer Channel Routing Algorithms

Several approaches:

  • – Extended Net Merge Channel Router
  • – HVH Routing from HV Solution
  • – Hybrid HVH-VHV Router

Star-Routing Algorithm

Manhattan-Diagonal Model

HVH

VHV.

4 (Four) layer channel routing? ? 1984

Asynchronous Bypass Channel Routers

Bipartite channel routing

A frequently studied special case is the bipartite channel routing when each net con- sists of two terminals { one in the Northern and one in the Southern boundary. Several authors call this case the 2-terminal channel routing problem

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Channel Routing Integrated Optics? 2013 ok

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Constraint-Graph Based channel Routing Algorithms

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Constraint logic programming channel routing 1990????? ok

Zhou, Neng-ma: A logic programming approach to channel routing, 2003-12-15, p8 ...................ok

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Crosstalk channel routing

track permutation technique for crosstalk optimization

crosstalk constraint

crosstalk minimization

integer linear programming for crosstalk minimization

Defect tolerant Channel Routing algorithm 1989

Dogleg_algorithm 1976 ok

dogleg algorithm proposed by Deutch

Click to learn more ...

Evolutionary channel routing

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Forward checking Channel Routing algorithm

Gallai’s Channel Routing Algorithm

Gamma routing

Beside these important cases it is possible that terminals are on two adjacent sides what we call gamma routing

The gamma routing problem means that all the terminals are situated at two adjacent sides, thus forming a?shape.

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Genetic Algorithm?? 1989

A genetic algorithm for constrained via minimization
Genetic Algorithm for Restrictive Channel Routing Problem
A new genetic algorithm for the channel routing problem
A genetic algorithm for channel routing in VLSI circuits
A Genetic Algorithm for Channel Routing using Inter-Cluster Mutation

General River Channel Routing Algorithm? ??????????1983

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Graph Theory based Channel Routing Algorithm?? 1993

Greedy Channel Routing 1981 ok

Rivest Fiduccia Channel Router

greedy interval packing algorithm

Ho A General Greedy Channel Routing Algorithm p8.pdf????????????????
Rivest A GREEDY CHANNEL ROUTER p7.pdf????????????????????

Gridless Channel Router/Routing????????? ?1987

Any model that does not follow this “gridded” approach

Venkataramana et al: Yield Enhanced Routing for High Performance VLSI Designs 1997 p10

HIERARCHICAL CHANNEL ROUTER?? 1983

Burstein and Pelavin
hierarchical wire routing

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Hybrid Channel Routing? 1998

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Inter-chip channel routing

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Intrac-cell channel routing

Knock-knee channel routing???????? 1987

Left edge routing algorithm 1971

left-edge algorithm with several extensions and variations
Basic Left Edge Algorithm.

Click to learn more ...

Manhattan routing model

Click to learn more ...

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MCC1 and MCC2 Channel Routing algorithms

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Memetic Channel Routing??? 2005

Varatharajan An Effective Memetic Algorithm for Solving Channel Routing Problems p5.pdf???????????
A Tutorial for competent memetic algorithms: model, taxonomy and design issues
Exact routing with search space reduction
A Graph Theoretic Approach to Minimize Total Wire Length in Channel Routing
Effective Memetic Algorithms for VLSI Design

A hybrid genetic algorithm for the channel routing problem

Multi-Layer Channel Routing?? 1986 ok

multilayer dogleg-free Manhattan model

MulCh: an algorithm for Multi channel Routing

Chameleon : another multi channel routing in the two-layer VH and three-layer HVH routing models

  • Unreserved Layer Model: Any net segment is allowed to be placed in any layer.
  • Reserved Layer Model: Certain type of segments are restricted to particular layer(s).
    • 1. Two-Layer
      • (a) HV (Horizontal-Vertical)
      • (b) VH
    • 2. Three-Layer
      • (a) VHV
      • (b) HVH

Hambrusch, Susanne E.: Channel Routing Algorithms for Overlap Models, Oct 1983, p25..........................

Khan, Ajoy Kumar et al: A Review on Channel Routing On VLSI Physical Design p8, IOSR Journal of Computer Engineering (IOSRJCE) ISSN: 2278-0661 Volume 5, Issue 1 (Sep-Oct. 2012), PP 41-48 ............................ 2

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Network-Flow Based Channel Routing Algorithm????

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Neural networks channel routing 1989

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Non rectangular channel routing 1986

Non-Manhattan Channel Router 1989

Over-the-cell channel routing??? ~ 1987

Cong, Jingsheng and Liu C.L: Over the cell channel routing p11, April 1990, IEEE Transaction on computer Aided Design, Vol 9 No 4 p408-418 .......................... 2

Cong, Jason et al: PHYSICAL MODELS AND EFFICIENT ALGORITHMS FOR OVER-THE-CELL ROUTING IN STANDARD CELL DESIGN p27 Nov 2007 ...........

Liu, Xiaolin and Tollis, Ioannis G.: Improving Over-The-Cell Channel Routing In Standard Cell Design p4, 1994 ACM 0-89791-690-5/94/0011/0606.......................

Click to learn more ...

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Overlap channel routing

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Pals' channel routing algorithm

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Pattern Channel Routers

Simulated annealing channel routing????????? 1982

Mall, R et al: Simulated Annealing-Based Channel Routing on Hypercube Computers p7 1991 ................3

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Single layers channel routing ?1993

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Single row channel routing 1989

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Sort VLSI channel router? / Channel Routing by Sorting 1991

A novel approach for the channel routing problem based on sorting is described. A router based on the bubble-sort for routing two point nets across a channel is presented. A lower and an upper bound on the channel width and an upperbound on the number of vias are given. The router is extended for handling multiterminal nets and single-sided connections. Results for multilayer channel routing are presented. The high-speed and predictable performance of these channel routing algorithms makes them valuable in assessing the difficulty of routing a particular configuration of logic blocks. This makes then suitable for use when calculating a cost metric in an iterative placement algorithm

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Steiner Tree Based channel routing Algorithms

Steiner Tree Based Algorithms

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Swap VLSI channel Router

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Through-chip channel routing

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Topological Channel Routing 1976 / 1990 / 1992 ok

Zhonghai

Click to learn more ...

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Virtual Channel Router?

Low-Latency Virtual-Channel Routers

Click to learn more ...

YACR2 Yet another channel router 1985

Symbolic Channel Router: YACR2

Symbolic Channel Router: YACR2

Features of YACR2

YACR2 uses two steps:
1. Horizontal segments are assigned to tracks such that vof(ci) is minimized for each column ci.
2. For each column ci:
(a) If vof(ci) = 0, appropriate vertical segments are placed in ci;
(b) If vof(ci) > 0: localized maze routing techniques
(Maze1, Maze2) are used to resolve the vertical constraint violations in ci.

==================================

Chameleon - the multilayer descendant of YACR2

Reed A new symbolic channel router YACR2, 1985 p12

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YACRIT : Yet Another Channel Router with Interchangeable Terminals 2007

YACRIT : Yet Another Channel Router with Interchangeable Terminals

Pal, Rajat K.: A Revisit to YACRIT Yet Another Channel Router with Interchangeable Terminals, Journal of Physical Sciences, Vol. 11, 2007, 172-184, p13

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[1] Hashimoto A. and J. Stevens, Wire Routing by Optimizing Channel Assignment within Large Apertures, Proc. of 8th ACM Design Automation Workshop, pp 155-169, 1971.
[2] Ho T.-T., S. S. Iyengar and S.-Q. Zheng, A General Greedy Channel Routing Algorithm, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 10, pp 204-211, 1991.
[3] Kobayashi H. and C. E. Drozd, Efficient Algorithms for Routing Interchangeable Terminals, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 4, pp. 204-207, 1985.
[4] Kobayashi H. and Y. P. Foo, Programmable Logic for Parallel Convolution, IEEE Intl. Conf. on Computer Design: VLSI in Computers, Port Chester, NY, pp. 700-704, 1984.
[5] LaPaugh A. S., Algorithms for Integrated Circuit Layout: An Analytic Approach, Ph.D. Thesis, Lab. for Computer Sc., Massachusetts Inst. of Tech., Cambridge, 1980.
[6] Pal R. K., Multi-Layer Channel Routing: Complexity and Algorithms, Narosa Publishing House, New Delhi (also published from CRC Press, Boca Raton, USA and Alpha Sc. Intl. Ltd., UK), 2000.
[7] Pal R. K., A. K. Datta, S. P. Pal, M. M. Das and A. Pal, A General Graph Theoretic Framework for Multi-Layer Channel Routing, Proc. of 8th VSI/IEEE Intl. Conf. on VLSI Design, pp 202-207, 1995.
[8] Pal A., D. Kundu, A. K. Datta, T. N. Mandal and R. K. Pal, Algorithms for Reducing Crosstalk in Two-Layer Channel Routing, Journal of Physical Sciences, Vol. 10, pp. 167-177, 2006.
[9] Reed J., A. Sangiovanni-Vincentelli and H. Santomauro, A New Symbolic Channel Router: YACR2, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 4, pp. 208-219, 1985.
[10] Schaper G. A., Multi-Layer Channel Routing, Ph.D. Thesis, Dept. of Computer Sc., Univ. of Central Florida, Orlando, 1989.
[11] Szymanski T. G., Dogleg Channel Routing is NP-Complete, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 4, pp 31-41, 1985.
[12] Yoshimura T. and E. S. Kuh, Efficient Algorithms for Channel Routing, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 1, pp 25-35, 1982.

Yoshimura Kuh channel routing / Net Merge Channel Router 1982

Click to learn more ...

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Chao, Heng Yi and Harper, Mary P.: A Difficult Channel Routing Generator, January 5, 1995

Chao, Heng Yi and Harper, Mary P.: An efficient lower bound algorithm for channel routing, January 26, 1995, p26

Chan, Wan S.: A new channel routing algorithm, Sept. 1982, p39

Chiluvuri, Venkat K. R. and Korent, Israel: Wire Length and Via Reduction for Yield Enhancement, SPIE Vol. 2874 / 103, 2004, p9

Cong, Jingsheng and Wong, D. F.: Generating More Compactable Channel Routing Solutions p16 ... 1988

Ho, Tai-tsung, New results on channel routing, IEEE, 1991

Jensen, Rune M. and Bryant, Randal E.: Set A* applied to channel routing, Sept 2002, p12

Jhang, Kyoung-son et al: COP a crosstalk optimizer for gridded channel routing p6 Nov 2007

Leong, H. W. and Liu, C. L.: A NEW CHANNEL ROUTING PROBLEM, 0738-I00X/83/0000/0584, IEIEE, 1983, p7

Mehlhorn, Kurt et al: Channel routing in knock knee mode: simplified algorithm and proofs, Algorithmica (1986) 1: 213-221, p9

Otten, Ralph: DESIGN AUTOMATION 5MD20 coping with hard problems, February-March 2010, p59

Rivest, Ronald .L et al: Provably good channel routing algorithms, 1980?, p7

Sahni, Sartaj and Wu, San-Yuan: Two NP-hard Interchangeable Terminal Problems, 1896?, p16

Somogyi, Kornélia Ambrus: On the Complexity of the Channel Routing Problem in the Dogleg-free Multilayer Manhattan Model, p9, Acta Polytechnica Hungarica Vol. 1, No. 2, 2004

Sulimma, Kolja and Goethe, Kunz, Wolfgang: An Exact Algorithm for Solving Difficult Detailed Routing Problems, ISPD’01, April 14, 2001, Sonoma, California,USA, ACM 1581133472

Yoeli, Uzi: A Robust Channel Router, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL IO, NO. 2. FEBRUARY 1991, p212/220 ..........p8 ?

曾奕倫: An Introduction to Channel Routing , 2008/07/11


Switchbox Routing

Switchbox Routing

? A switchbox is a generalization of a channel.
– Has terminals on all four sides.
? More difficult than channel routing problem.
– Main objective of channel routing is to minimize the channel height.
– Main objective of switchbox routing is to ensure that all the nets are routed.

Classification of algorithms:

– Greedy router
– Rip up and reroute routers
– BEAVER (based on computational geometry)

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Switchbox Routing Problem Definition

? A switchbox is a rectangular region with no inside obstructions, and with terminals lying on all four sides.
? The terminals are grouped into a collection S of disjoint sets called nets.
? To identify which terminals are to be connected, each terminal is labeled with a net identification number k, 1 ≤ k ≤ |S|.
? Formally a switchbox is defined as a region R={0, 1, · · ·,m} × {0, 1, · · · , n} where m and n are positive integers.

Each pair (i, j) in R is a grid point. The ith column is a set of grid points COL(i) = {(i, j) | j ∈ {0, 1, · · · n}}, 1 ≤ i ≤ m.
? The jth row or track is a set of points ROW(j) = {(i, j) | j ∈ {0, 1, · · ·m}}, 1 ≤ j ≤ n.
? The zeroth and mth columns are the left and right boundaries of the switchbox respectively.
? Similarly, the zeroth and nth rows are the top and bottom boundaries of the switchbox.
? The connectivity and location of each terminal is represented as LEFT(i) = k, RIGHT(i) = k, TOP(i) = k, and BOT(i) = k, depending on which side of the switchbox it lies on, where i stands for the coordinate of the terminal along the edge and k for its identification number.
? Lee-type algorithms are not suitable for solving this problem. Lee-type routers do not check ahead to avoid unnecessary blocking of other terminals.
? The goal of the switchbox router is to electrically connect the terminals in each individual net.
? Connections run horizontally or vertically along rows and columns along grid lines.
? As in previous cases, only a single wire is allowed to occupy each row and each column segment. The wires are allowed to cross.

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Jogging Strategies

The main modification to the greedy channel router of Rivest and Fiduccia is in the jogging schemes applied to accommodate the additional switchbox constraints discussed above.
The various jogging schemes are defined as follows.
(1) (JogR). For nets that have terminals on the RIGHT, this jog is performed until the net occupies a track that matches one of the right edge terminal positions.
(2) (JogT/B). For nets that only have terminals on TOP and BOT, this jog is similar to the one in the greedy channel router.
(3) (JogT/B; JogR). In this jogging scheme, first (JogT/B) is performed on every net and then a switch is made to perform (JogR) at the column where the last top and/or bottom terminals appear.

================================================

General Structure of Switchbox Algorithm

The general structure of the switchbox routing algorithm is given in Figure below:

Algorithm SwitchboxRouter
Begin
0. Determine Scan Direction;
Bring in LEFT terminals into column.
Loop for i from 1 to m ? 1 Do
1. If empty tracks exist then bring TOP(i) and BOT(i) into empty rows;
2. Join split nets as much as possible;
3a. For net with no right terminal Do Bring split nets closer by jogging;
3b. For net with right terminal Do SWJOG;
4. When close to right edge Do
Fanout to targets;
5. If Step 1 failed then increase number of rows;
Repeat Step1; update columns 1 to i;
While split nets exist Do;
6. Increase number of columns by 1;
Join split nets as much as possible;
End.

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Greedy router

Greedy routers are essentially extension of the Greedy channel router.

A Greedy switchbox router is an extension of the greedy channel router.

As opposed to a channel, which is open on the left and the right side, a switchbox is closed from all four sides. Moreover, there are terminals on the left and right boundaries of a switchbox. Thus in addition to the terminals on the upper and lower boundaries, the
presence of terminals on the left and right boundaries of the switchbox need to be considered while routing.

This is achieved by the following heuristic:
1) Bring in left terminals: The terminals on the left boundary are brought to the first column as horizontal tracks.
2) Jog to right terminals: The step in greedy channel router in which the nets are jogged to their nearest top or bottom terminal is modified for the nets that have a terminal on the right boundary. Such nets are jogged to their target rows, in addition to jogging to the next top or bottom terminal.
Jogging a net to the next top or bottom terminal is referred to as JOGt/b whereas, jogging a net to its target row is referred to as JOGr A target row of a net is a row of its terminal on the right boundary.

The nets are jogged to their target rows according to the following priority.
1. First choice is a net whose right side of the target row and the vertical track between the net and target row is empty.
2. Second choice is a net whose right side of the target row is empty. In addition, the priority is also based on how close a net can be jogged to its target row.
3. Third choice is a net that can be brought closer to its target row. Several schemes of using JOGt/b and JOGr have been suggested for a net having terminals on the right and top/bottom boundaries.

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Computational Geometry based router

 Based on a delayed layering scheme with computational geometry techniques.
 Main objectives are via and wire length minimization.
 Its an unreserved layer model routing algorithm.
 Uses a priority queue to determine the order in which nets are interconnected.
 Uses 3 methods to nd interconnections for nets:
1. Corner router
2. Line sweep router
3. Thread router

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switchbox routing in the Manhattan model

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2-D Switchbox Routing

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3-D Switchbox Routing

====================================

Rip up and Reroute routers employ some algorithm for finding routes for nets and modifying the routes to accommodate additional nets.

Rip-up and Re-route Based Router
Shin and Sangiovanni-Vincentelli proposed a switchbox router based on an incremental routing strategy.
It employs maze-running but has an additional feature of modifying alreadyrouted nets.
Some nets are even ripped-up and re-routed.
It is this feature that makes it suitable for channel and switch box routing.

====================================

simulated evolution have also been applied to switchbox routing.
====================================

Open switchbox routing

Literature

Boros, Endre et al: Unconstrained multilayer switchbox routing, July 1993, p14

Channel & Switchbox Routing Jan 2006 p18

GEREZ, SABIH H. AND HERRMANN, OTTO E.: Switchbox Routing by Stepwise Reshaping, DECEMBER 1989, p12

Hamachi, Gordon T and Ousterhout John K: Switchbox Router with obstacle avoidance Dec 1983, p20

PRANEETH Switchbox Routing Algorithm p9 April 2009

Schmiedle, Frank et al: Exact switchbox routing with search space reduction, 2000, p7

SZESZLER, DAVID: SWITCHBOX ROUTING IN THE MULTILAYER MANHATTAN MODEL, November 25, 1997, p10

Tsay, CHING-YUH: An efficient algorithm for switchbox routing August, 1983 p64 .


Global (homotopic) routing

Global Routing

Global routing defines an area for each net to which the search for actual wires in detailed routing is restricted. As global routing works on a much smaller graph, we can globally optimize the most important design objectives. Moreover, global routing has another important function: decide for each placement whether a feasible routing exists and if not, give a certificate of infeasibility.

The global router performs a coarse route to determine, for each connection, the minimum distance path through routing channels that it has to go through. If the net to be routed has more than two terminals the global router will break the net into a set of two terminal connections and route each set independently.

The global router considers for each connection multiple ways of routing it and chooses the one that passes through the least congested routing channels. By keeping track of the usage of each routing channel, congestion is avoided; and the principal objective of the global router, balancing the usage of the routing channels, is achieved. Once all connections have been coarse routed, the solution is optimized by ripping up and re-routing each connection a small number of times. After that, the final solution is passed to the detailed router.

Global routing is a design action that precedes detailed routing and follows placement.

  • Global routing decides about the distribution of netlists across the available routing channels.
  • Overall optimization goal : area minimization and observance of timing constraint.
  • Generates a ‘loose’ route for each net.
  • Assigns a list of routing regions to each net without specifying the actual layout of wires.

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Global routing is divided into 3 phases:

  • Region definition
  • Region assignment
  • Pin assignment to routing regions

=======================================================

Global Routing Formulation

Given?? (i) Placement of blocks/cells

?????????? (ii) channel capacities

Determine

Routing topology of each net

Optimize

(i) max # nets routed

(ii) min routing area

(iii) min total wirelength

Classic terminology:? In general cell design or standard cell design, we are able to move blocks or cell rows, so we can guarantee connections of all the nets (“variable-die” + channel routers).

Classic terminology:? In gate-array design, exceeding channel capacity is not allowed (“fixed-die” + area routers).

Since Tangent’s Tancell (~1986), and > 3LM processes, we use area routers for cell-based layout

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The global routing graph

The global router works on a three-dimensional grid graph which is obtained by partitioning the chip area into regions. For classical Manhattan routing this can be done by an axis-parallel grid. In any case, these regions are the vertices of the global routing graph. Adjacent regions are joined by an edge, with a capacity value indicating how many wires of unit width can join the two regions. Each routing plane has a preference direction (horizontal or vertical), and we remove edges orthogonal to this direction in the global routing graph.

For each net we consider the regions that contain at least one of its pins. These vertices of the global routing graph have to be connected by a Steiner tree. If a pin consists of shapes in more than one region, we may assign it to one of them, say the one which is closest to the center of gravity of the whole net, or by solving a group Steiner tree problem.

The quality of the global routing depends heavily on the capacities of the global routing edges. A rough estimate has to consider blockages and certain resources for nets whose pins lie in one region only. These nets are not considered in global routing. However, they may use global routing capacity. Therefore we route very short nets, which lie in one region or in two adjacent regions, first in the routing flow, i.e. before global routing. They are then viewed as blockages in global routing. Yet these nets may be rerouted later in local routing if necessary.

Routing short nets before global routing makes better capacity estimates possible, but this also requires more sophisticated algorithms than are usually used for this task. We consider a vertex-disjoint paths problem for every set of four adjacent global routing regions, illustrated in Figure 26. There is a commodity for each wiring plane, and we try to find as many paths for each commodity as possible. Each path may use the plane of its commodity in preference direction and adjacent planes in the orthogonal direction.

An upper bound on the total number of such paths can be obtained by considering each commodity independently and solving a maximum flow problem. However, this is too optimistic and too slow. Instead we compute a set of vertex-disjoint paths (i.e., a lower bound) by a very fast multicommodity flow heuristic. It is essentially an augmenting path algorithm but exploits the special structure of a grid graph. For each augmenting path it requires only O(k) constant-time bit pattern operations, where k is the number of edges orthogonal to the preferred wiring direction in the respective layer. In practice, k is less than three for most paths.

This very fast heuristic finds a number of vertex-disjoint paths in the region of 90% of the (weak) max-flow upper bound. For a complete chip with about one billion paths it needs 5 minutes of computing time whereas a complete max-flow computation with our implementation of the Goldberg-Tarjan algorithm would need more than a week.

Please note that this algorithm is used only for a better capacity estimation, i.e. for generating accurate input to the main global routing algorithm. However, this better capacity estimate yields much better global routing solutions and allows the detailed router to realize these solutions.

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Classical global routing

In its simplest version, the global routing problem amounts to packing Steiner trees in a graph with edge capacities. A fractional relaxation of this problem can be efficiently solved by an extension of methods for the multicommodity flow problem. However, the approach does not consider today’s main design objectives which are timing, signal integrity, power consumption, and manufacturing yield. Minimizing the total length of all Steiner trees is no longer important. Instead, minimizing a weighted sum of the capacitances of all Steiner trees, which is equivalent to minimizing power consumption, is an important objective. Delays on critical paths also depend on the capacitances of their nets. Wire capacitances can no longer be assumed to be proportional to the length, since coupling between neighboring wires plays an increasingly important role. Small detours of nets are often better than the densest possible packing. Spreading wires can also improve the yield.

Our global router is the first algorithm with a provable performance guarantee which takes timing, coupling, yield, and power consumption into account directly. Our algorithm extends earlier work on multicommodity flows, fractional global routing, the min-max resource sharing problem, and randomized rounding.

Let G be the global routing graph, with edge capacities u : E(G) ! R+ and lengths l : E(G) ! R+. Let N be the set of nets. For each N 2 N we have a set YN of feasible Steiner trees. The set YN may contain all delay-optimal Steiner trees of N or, in many cases, it may simply contain all possible Steiner trees for N in G. Actually, we do not need to know the set YN explicitly. The only assumption which we make is that for each N 2 N and any : E(G) ! R+ we can find a Steiner tree Y 2 YN with P e2E(Y ) (e) (almost) minimum sufficiently fast. This assumption is justified since in practical instances almost all nets have less than, say, 10 pins. We can use a dynamic programming algorithm for finding an optimum Steiner tree for small nets and a fast approximation algorithm for others. With w(N; e) 2 R+ we denote the width of net N at edge e. A straightforward integer programming formulation of the classical global routing problem is: min X N2N X e2E(G) l(e) X Y 2YN:e2E(Y ) xN;Y s.t. X N2N X Y 2YN:e2E(Y ) w(N; e)xN;Y  u(e) (e 2 E(G)) X Y 2YN xN;Y = 1 (N 2 N) xN;Y 2 f0; 1g (N 2 N; Y 2 YN)

Here the decision variable xN;Y is 1 iff the Steiner tree Y is chosen for net N. The decision whether this integer programming problem has a feasible solution is already NP-complete. Thus, we relax the problem by allowing xN;Y 2 [0; 1]. Raghavan and Thompson proposed solving the LP relaxation first, and then using randomized rounding to obtain an integral solution whose maximum capacity violation can be bounded. Although the LP relaxation has exponentially many variables, it can be solved in practice for moderate instance sizes since it has only jE(G)j+jN j many constraints. Therefore all but jE(G)j + jN j variables are zero in an optimum basic solution. However, for current complex chips with millions of nets and edges, all exact algorithms for solving the LP relaxation are far too slow.

Fortunately, there exist combinatorial fully polynomial approximation schemes, i.e. algorithms that compute a feasible solution of the LP relaxation which is within a factor of 1 +  of the optimum, and whose running time is bounded by a polynomial in jV (G)j and 1  , for any accuracy  > 0. If each net has exactly two pins, YN contains all possible paths connecting N, and w  1, the global routing problem reduces to the edgedisjoint paths problem whose fractional relaxation is the multicommodity flow problem. Shahrokhi and Matula [87] developed the first fully polynomial approximation scheme for multicommodity flows. Carden, Li and Cheng first applied this approach to global routing, while Albrecht [1] applied a modification of the approximation algorithm by Garg and K?nemann [32]. However, these approaches did not consider the above-mentioned design objectives, like timing, power, and yield.

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Standard-cell layout

  • A net connected to cells on more than two adjacent rows, global router should split the net into parts.
  • A wiring pattern : a minimum rectilinear Steiner tree.
  • vertical segment across the rows
    • use wiring layer that is not used by the cells.
    • use feedthrough cells
    • use feedthrough wires within cells.

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Rectilinear Steiner Tree

Some kind of detailed routing should be used to fix the exact position of the vertical segments of the Steiner tree.
? slightly shift the segments in order to align with feedthrough wire position.
? segments at approximately the same location can be permuted to reduce the densities in the channels.

(a) minimal length.
(b) minimal number of cell-row crossing.

Efficient Rectilinear Steiner-tree Construction

? input : a set of points P = {p1,p2,…,pn}.
? the rectilinear distance between a pair of points pi and pj is equal to |xi-xj|+|yi-yj|.
? the goal of problem is to find a minimallength tree that interconnects all points in P and makes use of new points in the plane not included in P if these points contribute to the tree-length reduction.
? the set of new points will denoted S.

Approximated algorithm
? The rectilinear Steiner tree problem is NPComplete.
? The optimal tree can be approximated by spanning tree that can be computed in polynomial time by Prim’s algorithm.
? At most a factor of 3/2 longer than the minimum Steiner tree.
? There are many heuristics inspired by this fact.

The interconnection of three points based on the minimal spanning tree (a), and the introduction of a Steiner-point after flipping and merging (b), and the final Steiner tree (c).

The iterated 1-Steiner heuristic for Steinertree construction.

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Timing Constraint

? Minimal-length Steiner tree may not be the optimal solution for a single net.
? Timing-driven (performance-driven) layout synthesis
? Very small number of critical path determines system’s operation speed.
? A long wire behaves more like a transmission line.
? The unidirectional signal flow : one source terminal to multiple sink terminals

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sequential routing

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concurrent routing

Global Routing: Concurrent Approaches

Can formulate routing problem as integer programming problem, solve simultaneously for all nets

Given

(i) Set of Steiner trees for each net
(ii) Placement of blocks/cells
(iii) Channel capacities

Determine

Select a Steiner tree for each net w/o violating channel capacities
Optimize

Min total wirelength

Simulated annealing also can be used

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Multicommodity Flow Algorithms

multi-commodity network flow problem

multi-commodity flow based algorithm

fractional multi-commodity flows

Combinatorial fully polynomial approximation schemes

Min-max resource sharing

contract regions of approximately 50x50 tracks to a single vertex

  1. compute capacities of edges between adjacent regions
  2. pack Steiner trees with respect to these edge capacities
  3. global optimization of objective functions
  4. Steiner tree yields detailed routing area for each net
  5. Detailed routing computes the detailed wires in these areas by a very fast goal-riented interval-labeling variant of Dijkstra’s algorithm (Peyer, Rautenbach, Vygen [2009])

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multi-level routing

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integer programming

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progressive Integer Linear Programming (ILP) based method
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an extremely fast and high-quality global router called FastRoute
Different from traditional approaches, we proposed a congestion-driven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestion-driven Steiner trees, we only need to apply maze routing to a small percentage of the two-pin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing.
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the stateof- the-art academic global routers Labyrinth and Chi Dispersion router
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neural network global router 1997

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applications of the network coding technique for intercon nect optimization and improving the routability of Very-large-scale integration (VLSI) designs.

Network coding generalizes the traditional routing approach by enabling the intermediate nodes to generate new signals by combining the signals received over their incoming wires.
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minimum spanning tree solutions

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hierarchical routing

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Parallel Hierarchical algorithm for Global Routing

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ripup and reroute methods
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pattern-based global routing
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Chi dispersion router

based on a linear cost function as well as a predicted congestion map
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FastRoute

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DpRouter
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Hybrid CHC (HCHC) genetic algorithm for global routing

C.Albrecht. Global routing by new approximation algorithms for multicommodity flow. In IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 20:622-631, 2001. ?????????? not downloaded yet

Brouwer, Randall J. and Banerjee, Prithviraj: PHIGURE: A PARALLEL HIERARCHICAL GLOBAL ROUTER, 1988, p4.

CHO, MINSIK et al: BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability 2009 p21.

Deza, Antoine et al: Global Routing in VLSI Design Algorithms, Theory, and Computational Practice p25 May 2011

Hamachi, Gordon T and Ousterhout John K: Magic's Obstacle Avoiding Global Router 1985 p20

Han, Yiding and Ancajas, Dean Michael: Exploring High Throughput Computing Paradigm for Global Routing 2/14/2012 p17

R. T. Hadsell and P. H. Madden. Improved global routing through congestion estimation. In Proc. ACM/IEEE Design Automation Conf., pp. 28-31, 2003.

Hu, Jiang and Sapatnekar Sachin S: A survey on multinet global routing for integrsated circuits 2000 p68

Hu, Jiang and Sapatnekar Sachin S: A Timing-constrained Algorithm for Simultaneous Global Routing of Multiple Nets 1999 p5

Jayalakshmi, G.Andal et al: A HYBRID CHC GENETIC ALGORITHM FOR MACRO CELL GLOBAL ROUTING 1994 p11

Karp, R. M. et al: Global Wiire Routing in Two-Dimensional Arrayst 1983 p7

Koh, Cheng-Kok: Manhattan or Non-Manhattan - A Study of Alternative VLSI Routing Architectures p15 APRIL1 999

Mandoiu, Ion: Recent Advances in Multicommodity Flow Algorithms for Global Routing 2003 p6.

NEMADE, NIKHIL PANDIT: APPLICATION OF NETWORK CODING FOR VERY-LARGE-SCALE INTEGRATION (VLSI) ROUTING (THESIS), May 2008, p67

M. Pan, and C. Chu, FastRoute: A step to integrate global routing into placement," Proc. of Intl. Conf. on Computer-Aided Design, pp. 464-471, 2006.......................

M. Pan, and C. Chu, FastRoute: A step to integrate global routing into placement," Proc. of Intl. Conf. on Computer-Aided Design, pp. 464-471, 2006.......................5

Saad, Mohamed et al: A provably good global routing algorithm in multilayer IC and MCM layout designs June 2008, p14

Sherwani Global Routing 1992 p40

Shojaei, Hamid et al: Planning for Local Net Congestion in Global Routing March 2013 p8

Shragowitz E and Keel, S.: A global router based on a multicommodity flow model 1985 p14

Sun, Hao and Areibi, Shawki: GLOBAL ROUTING FOR VLSI STANDARD CELLS 1999 p4

SUN, HAO: Sequential Parallel Global Routing Algorithms for VLSI Standard Cells April, 2004 p145.

Westra, Jurjen et al: Global Routing: Metrics, Benchmarks and Tools 2004 p6

Wu, Tai-Hsuan et al: GRIP: Scalable 3D Global Routing Using Integer Programming May 2009 p6.

Yang, Zhen: A Multiple-objective ILP based Global Routing Approach for VLSI ASIC Design 2009 p178

Zafrany, Samy: VLSI Routing Flow on Topological Patterns p6, Nov 21, 2013

Zafrany, Samy: VLSI Routing flow based on Topological Patterns p6 Nov 2013

Zaglyadin, Gleb: A New Approach to Multi-objective Global Routing for VLSI Layout April 2011 p19

Zhou, Hai and Wong, D. F: Global Routing with Crosstalk Constraints NOVEMBER 1999 p6


Timing Optimization

Timing Optimization / Clocktree Generation / Cycle Time and Slack Optimization for VLSI–Chips / timing(PT-SI)

timing_driven_routing

Net topology optimization and resource allocation to critical nets

Timing Optimization / Clocktree Generation / Cycle Time and Slack Optimization for VLSI–Chips / timing(PT-SI)

  1. Clocktree Generation
  2. clock tree design
  3. clock tree synthesis
  4. clock skew scheduling
  5. optimizing the clock skews
  6. clock period optimization
  7. timing, timing optimization
    1. fanout tree design
    2. gate sizing
    3. timing graph

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arrival time at input of the chip

arrival time at output of the chip

arrival time at register of the chip

=======================

netlist

a netlist is a hypergraph on the set of pins, such that each pin is in exactly two hyperedges (a gate and a signal), together with the delay information.

optimal netlist partitioning is unfeasible

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hypergraph partitioning

graph and hypergraph partitioning algorithms such as METIS and hMETIS

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graph regularity lemma

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clock schedule

optimal arrival times for clock signals

cycle time

data paths and clocktree paths.

test for negative circuits in a digraph as a subroutine

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direct combinatorial algorithm

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timing analysis

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transparent latches.

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slack balancing problem

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routing detours

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process variations

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manufacturing skew

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critical paths

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optimum slack distribution

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fixed clock arrival times

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slack on clocktree paths

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simultaneous optimization of slacks on all data paths and clocktree paths

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network optimization algorithms

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parametric shortest paths

=================================

linear programming

=================================

binary search

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the algorithm of Young, Tarjan and Orlin

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l1-metric is the right metric for wire length

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to find disjoint sets of wires for all nets ?- vertex disjoint Steiner trees

=================================

the bounding box model BB

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net models : STEINER MST CLIQUE ?STAR

Chuang, Wei-Tong: Timing and Area Optimization for VLSI Circuit and Layout May 1994 p150

Held, Stephan: Timing Closure in Chip Design, Juni 2008, p193

Khang, Andrew B. et al: Chapter 8 – Timing Closure p73

Scheffer,Lou: Timing Closure Today p104.ppt April 2002


Two-Layer Channel Routing

Channel routing in the 2–layer Manhattan model is one of the most investigated problems in detailed routing. Finding a minimum width solution was proved to be NP–hard by Szymanski.

A channel is a rectangular grid G of size (w + 2) × n consisting of horizontal tracks (numbered from 0 to w+1) and vertical columns (numbered from 1 to n), where w is the width and n is the length of the channel. Upper and lower boundary points of G (that is, points with y–coordinate 0 or w+1) are called terminals. Depending on which boundary of the channel they are situated on, terminals are called Northern or Southern.

A net is a collection of terminals. A channel routing problem is a set N = {N1, . . . ,Nt} of pairwise disjoint nets. If all the terminals of every net are northern, we speak of a single row routing problem. A channel routing problem is called bipartite if each net contains exactly two terminals, one on the northern, and one on the southern boundary.

The solution of a routing problem in the k–layer model is a set H = {H1, . . . ,Ht} of pairwise vertex disjoint subgraphs (also called wires, these are usually Steiner trees) of the k–layer rectangular grid such that Hi connects the terminals of Ni (that is, Ni ? V (Hi)) for i = 1, . . . , t. Wires can access the terminals on any layer. Edges of the wires that join adjacent vertices of two consecutive layers are called vias.

A solution of a channel routing problem is said to belong to the Manhattan model if consecutive layers contain wire segments of different directions only. That is, layers with horizontal (east–west) and vertical (north–south) wire segments alternate. (This notion is motivated by the fact that for certain technologies it is advantageous not to have long parallel wire segments on two consecutive layers). If a solution does not belong to the Manhattan model, it is said to be in the unconstrained model.

The usual formulation of the channel routing problem is to fix the number of layers and ask for the minimum width routing (either in the Manhattan, or in the unconstrained model).

2–layer Manhattan routing has always been one of the most popular and most investigated problems in VLSI routing. The first classic result in the topic of VLSI routing is probably Gallai’s linear time algorithm that solves the single row routing problem — a special case of channel routing — with optimal width in the 2–layer Manhattan model.

For every vertical line e that cuts the grid into two we define its congestion c(e): it is the number of nets that are divided into two by e (that is, the number of nets that have terminals both left to e and right to e). The maximum congestion of all vertical lines that cut the grid into two is called the density of the problem. It is straightforward that the density is a lower bound on the width of any routing (again, in the 2–layer Manhattan model).

Theorem 1 (T. Gallai 1958) The minimum width of a solution of a single row routing problem in the 2–layer Manhattan model is equal to the density of the problem. Moreover, such a minimum width routing can be found in linear time.

The proof makes use of the fact that interval graphs are perfect. A horizontal interval is associated with every net, stretching from its leftmost terminal to its rightmost terminal. The density is equal to the clique number of the corresponding interval graph. A colouring with an equal number of colours can easily be transformed into an optimal width routing.

Theorem 2 (T.G. Szymanski, 1985) It is NP–complete to decide whether a channel routing problem is solvable in the 2–layer Manhattan model with width at most k (where k is part of the input).

Despite the above theorem, there exist a few positive results concerning 2–layer Manhattan channel routing. There is a linear time algorithm to decide whether a channel routing problem is solvable in this model with a given width w. (In this result the length n of the channel is thought of as part of the input, however the width w is not. Therefore the algorithm is linear in the sense that the number of operations is c · n, where c is a superpolynomial function of w.)

A substantially different approach is adopted in that it is proved that every channel routing problem can be solved in the 2–layer Manhattan model with width at most 2d + O( t ), where d denotes the density and t denotes the number of nets. (Furthermore, the bound on the width is at most d + O( t ) if each net consists of two terminals only). However, for the routing they extend the length of the channel by introducing extra columns into the grid, the number of which can be as large as O( t ). The running time of their algorithm is linear in the area of the routing. The upper bound on the width was substantially improved to 3 2d+O( d log d)+O( t ).

If we consider 2–layer unconstrained routing then it is true that every channel routing problem is solvable in polynomial time (with a sufficiently large width). This was first proved by M. Marek–Sadowska and E. Kuh. Later A. Recski and F. Strzyzewski found a linear time algorithm.

Theorem 3 (A. Recski and F. Strzyzewski, 1990) Every channel routing problem can be solved in linear time in the 2–layer unconstrained model.

Their algorithm does not give an optimal width solution, however, the obtained width can be upper–bounded by n in the bipartite, and by 3 2n in the general case. The complexity of the naturally arising question of finding a minimum width routing is not known, but according to the widely accepted conjecture of D. S. Johnson it is NP–hard.

One of the main differences between the unconstrained and the Manhattan version of 2–layer channel routing is that, in contrast to the statement of the above Theorem, some specifications are unsolvable in the Manhattan model, even if the width can be arbitrarily large. (Here we assume that the length of the channel cannot be extended by introducing extra columns.)

A channel routing problem is dense if each terminal (that is, boundary point) on the northern and southern boundaries belongs to some net. (We always assume that each net contains at least two terminals.) A net is called trivial if it consists of two terminals which are situated in the same column.

Their algorithm does not give an optimal width solution, however, the obtained width can be upper–bounded by n in the bipartite, and by 3 2n in the general case. The complexity of the naturally arising question of finding a minimum width routing is not known, but according to the widely accepted conjecture of D. S. Johnson it is NP–hard.

One of the main differences between the unconstrained and the Manhattan version of 2–layer channel routing is that, in contrast to the statement of the above Theorem, some specifications are unsolvable in the Manhattan model, even if the width can be arbitrarily large. (Here we assume that the length of the channel cannot be extended by introducing extra columns.) In this paper we give a complete characterization of all solvable specifications and give a linear time algorithm that solves them. Furthermore, the width of the obtained routing will be upper– bounded by 3 /2n in the bipartite, and by 7 4n in the general case.

A channel routing problem is dense if each terminal (that is, boundary point) on the northern and southern boundaries belongs to some net. (We always assume that each net contains at least two terminals.) A net is called trivial if it consists of two terminals which are situated in the same column.

Theorem 4 A channel routing problem is not solvable in the 2–layer Manhattan model (with an arbitrary width) if and only if it is bipartite, dense and has at least one non–trivial net. Moreover, if a specification is solvable then it can be solved with width at most 3/ 2n in the bipartite, and 7/ 4n in the general case (where n is the length of the channel).

Proof: Throughout the proof we assume that the top and bottom layers are reserved for vertical and horizontal wire segments, respectively.

In a dense, bipartite specification the length n of the channel equals the number of nets. If a non–trivial net Ni exists, then the routing of Ni requires at least one horizontal wire segment on the bottom layer in track j. The remaining n?1 nets must also cross track j. However, the two vias at the endpoints of the horizontal wire segment belonging to Ni occupy two columns on the top layer, therefore at most n ? 2 further nets can cross track j. Hence such a specification cannot be routed.

To show the converse implication assume that a specification N = {N1, . . . ,Nt} is given. We define a directed graph Gv with vertex set N: a directed edge (Ni,Nj) (1 ≤ i, j ≤ t, i 6= j) is introduced whenever there exists a column in which Ni has a northern terminal and Nj has a southern terminal. Gv is going to be called the vertical constraint graph of N.

First assume that the specification is bipartite. In this case each vertex of Gv has both in–degree and out–degree at most one, therefore each connected component is either a directed path or a directed cycle. If each net is trivial then a trivial routing exists (with width 1). Otherwise we construct a routing by processing the components of Gv one after the other. (The routing of trivial nets can be solved by a single vertical segment on the top layer, we disregard these henceforth.) We first process directed paths, then directed cycles (otherwise the order of the components is arbitrary). Assume that the directed path P = (Ni1 ,Ni2 , . . . ,Nik ) is a component of Gv. Proceeding from North to South, we assign a separate track on the bottom layer to each net of P in the above order and route them in the most straightforward way: in the corresponding track of the bottom layer we introduce a horizontal wire segment connecting the columns of the two terminals, we switch to the top layer at both ends of this segment and connect to the two terminals. Thus we have consumed k consecutive tracks to route the nets of P. Now assume that the directed cycle C = (Ni1 ,Ni2 , . . . ,Nik ,Ni1) is a component of Gv. We choose a net of C, say Ni1 , arbitrarily; we are going to refer to the chosen net as an exceptional net. Again, proceeding from North to South we assign a track to each net of C in the above order. However, the exceptional net Ni1 receives two tracks: the topmost and the bottommost track of the altogether k+1 tracks assigned to C. Routing of the nets Ni2 , . . . ,Nik is performed in the same straightforward way as in the case of directed paths. To route Ni1 , we first find a column in which the southern terminal does not belong to any net. (Since the length n is larger than the number of nets t by the assumption of the theorem, the existence of such a column is guaranteed.) We place a vertical wire segment in this column on the top layer to connect the two tracks assigned to Ni1 . At both ends of this segment we switch to the bottom layer and introduce two horizontal wire segments in the upper and lower tracks assigned to Ni1 to reach the column of the northern and southern terminal of Ni1 , respectively. We complete the routing of Ni1 by joining the endpoints of the above horizontal segments with the two terminals using the top layer.

It is easy to verify that no conflict can occur between the routings of any two nets. Since each track of the bottom layer is assigned completely to one of the nets, no two wires intersect on this layer. Assume that both terminals of a column are occupied by a net; then these two (not necessarily distinct) nets belong to the same component of Gv. If neither of these two nets are exceptional then the track assigned to the net of the northern terminal lies one unit north to the track assigned to the net of the southern terminal, therefore the two vertical wire segments of this column are disjoint. This is true even if, say, the net of the northern terminal is exceptional since in this case this terminal is joined to the topmost of the tracks assigned to the component of its net. If the northern terminal of a column is empty, but the southern one is occupied by a net then only one vertical segment was placed in this column, thus no conflict can occur. If the southern terminal or both terminals of a column are empty then vertical segments belonging to exceptional nets may have been placed in this column. If the northern terminal is occupied by a net then this net is the endpoint of a directed path in Gv, therefore it was processed prior to all exceptional nets. Thus no two vertical segments can intersect even in such columns.

Finally, we consider the general (non–bipartite) case. The upper and lower boundaries can each be regarded as a single row routing problem. These can be solved using the algorithm of Theorem 1. This way the problem is reduced to the bipartite case: from each net that appears on both boundaries one northern and one southern terminal is chosen arbitrarily. Obviously, the thus obtained bipartite problem is not dense, hence it can be routed using the above described algorithm.

To conclude the proof, we show that the above constructed routing uses not more than 3 2n tracks in the bipartite, and not more than 7/ 4n tracks in the general case.

If the problem is bipartite then the track consumption of the routing of each non–exceptional and exceptional net is 1 and 2, respectively. Since each connected component of Gv has at least two vertices, at most half of the nets are exceptional. Hence, if t denotes the number of nets, we have w ≤ t + t /2 = 3 /2 t ≤ 3 /2n.

In the general case, denote by xi and yi the number of non–exceptional and exceptional nets containing exactly i terminals, respectively (i ≥ 2). Denote by e the number of terminals that are not occupied by any net. Thus we have

∑ i 2 i ⋅ ( x i + y i ) = 2n

The following table shows the maximum number of tracks consumed by the construction to route a net, depending on the number of terminals (correctness of the values can easily be verified).

 | 2 terminals | 3 terminals | ≥ 4 terminals
Non–exceptional nets | 1 | 2 | 3
Exceptional nets | 2 | 3 | 4

It follows that for the width w of the routing
w ≤ x2 + 2y2 + 2x3 + 3y3 + 3 ∑ i 4 x i + 4 ∑ i 4 y i (2)

holds. Furthermore, since at most half of the nets are exceptional,

∑ i x i ≥ ∑ i y i (3)

follows. From (1) and (2) we have
w ≤ 2n ? s, (4)
where
s = e + x2 + x3 + ∑ i 4 ( ( i − 3 ) x i + ( i − 4 ) yi ) . (5)

Finally, 2n ≤ 8s is easy to verify from (1), (3) and (5), which proves w ≤ 7 /4n by (4). 2

It is easy to verify that the above presented construction can be realized by a linear time algorithm. Since the two single row routing problems for the two boundaries can be solved in linear time (Theorem 1), it suffices to consider the bipartite case. The size of the input is O(n) since the problem is specified by the two sequences of terminals on the two boundaries. The vertical constraint graph Gv can be generated by a scanning of the columns, that is, in O(n) time. With the same scanning x–coordinates of the two terminals of each net can be recorded. By a scanning of the vertices of Gv starting points of the directed path components of Gv (that is, vertices with in–degree 0) can be found. Once a separate track is assigned to a net, its routing requires constant time (since only the coordinates of the endpoints of the straight wire–segments — together with the positions of the necessary vias — are to be outputted). The same holds even for exceptinal nets if a column with an empty southern terminal was previously recorded. Once a net is routed, the next one to route can also be found in constant time using the information provided by Gv. Hence the nets can be processed one–by–one, yielding a total running time of O(n).

Finally, we mention an easy corollary of the above theorem.

Corollary 5 Every channel routing problem can be solved in linear time in the 2–layer Manhattan model if it is allowed to extend the length of the channel by at most one (by introducing an extra column).

Crosstalk minimization problem

Crosstalk minimization problem for the reserved two-layer Manhattan channel routing is NP-hard, even if the channel instances are free from any vertical constraint (simplest channel instances).

heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions

There are two types of crosstalk minimization problem, namely sumcrosstalk minimization and bottleneck-crosstalk minimization.

Sum-crosstalk is the amount of total crosstalk between horizontal wire segments of the nets that are assigned to adjacent tracks. The sum-crosstalk minimization problem is to compute a feasible routing solution with a given number of tracks in which the total amount of crosstalk is minimized.

Bottleneck-crosstalk with respect to a feasible routing solution is the maximum amount of crosstalk due to overlapping between any pair of adjacent horizontal wire segments of two different nets. So the bottleneck crosstalk minimization problem of finding a feasible routing solution with a given number of tracks, such that the bottleneck-crosstalk is minimized.

==========================================

Crosstalk and High Performance Routing

As fabrication technology advances and feature size reduces, devices are placed in closer to each other, and interconnecting wire segments are assigned with narrower pitch, whereas circuits’ operations are realized at higher frequencies. As a result, electrical hazards viz., crosstalk between wire segments is evolved. Crosstalk between wire segments is proportional to the coupling capacitance, which is in turn proportional to the coupling length; the total length of overlap between wire segments of two different nets on adjacent tracks.

Crosstalk is also proportional to the frequency of operation and inversely proportional to separating distance between wires.

More crosstalk means more signal delay and reduced circuit performance. Therefore, in high performance routing it is desirable to develop channel routing algorithms that not only compute minimum area channel routing solutions but also reduce crosstalk. We define the amount of crosstalk between horizontal wire segments of two different nets assigned to two adjacent tracks in a given routing solution is proportional to the amount of overlap of their horizontal spans. If two intervals do not overlap, there is no horizontal constraint between the nets. That is, if there is an overlap of the horizontal wire segments of a pair of nets, there is a possibility of having crosstalk between them.

We measure crosstalk in terms of number of units of overlap between a pair of nets that are assigned to adjacent tracks in a feasible routing solution. We assume that the crosstalk between wire segments of two different nets assigned to two nonadjacent tracks is negligibly small, and hence can be ignored. We also assume that the amount of crosstalk between
vertical wire segments of two different nets placed in two adjacent columns to be very small, Algorithms for Reducing Crosstalk in Two-Layer Channel Routing 169 and hence can be neglected (as usually the number of columns in a channel is much more than the number of tracks required in it).

Some Definitions

Now we define a few terms and constraints involving CRP, and characterize the problem as stated below. In this paper, we allow all interconnections of nets present in a channel using two-layer Manhattan routing model, where one layer is reserved for horizontal wire segment only and the other is reserved for vertical wire segment only. Such a routing model is known as the two-layer VH routing model. In this model, the CRP is characterized by two important constraints, viz., the horizontal constraint and the vertical constraint.

These constraints are usually represented by two graphs, viz., the horizontal constraint graph (HCG) and the vertical constraint graph (VCG), respectively. The HCG is simple undirected graph. Specifically, the HCG is an interval graph and, therefore, a perfect graph. The VCG is an arbitrary directed graph that may or may not contain any cycle.

Reduced vertical constraint graph (RVCG) is another directed graph that can be formed from VCG. The local density of a column (in a channel) is the maximum number of nets passing through it. The channel density is the maximum of all the local densities in a channel. We denote channel density by dmax.

Crosstalk Minimization Problem

In CRP, usually the prime intention of a router is to compute such a solution that uses a minimum number of tracks (or minimum channel area). In addition, in high performance routing our interest is also to obtain a routing solution with less electrical hazards (i.e., crosstalk), less signal propagation delay, less power consumption, less or no hotspot formation, etc.

Crosstalk is one of the most important high performance optimization criteria in channel routing that should be reduced to get better performance in routing. In this paper we have developed algorithms for minimizing crosstalk for reserved two-layer (VH) Manhattan channel routing model. There are two types of crosstalk minimization problem, namely sumcrosstalk minimization and bottleneck-crosstalk minimization. Sum-crosstalk is the amount of total crosstalk between horizontal wire segments of the nets that are assigned to adjacent tracks. The sum-crosstalk minimization problem is to compute a feasible routing solution with a given number of tracks in which the total amount of crosstalk is minimized.

Similarly, bottleneck-crosstalk with respect to a feasible routing solution is the maximum amount of crosstalk due to overlapping between any pair of adjacent horizontal wire segments of two different nets. So the bottleneck crosstalk minimization problem of finding a feasible routing solution with a given number of tracks, such that the bottleneck-crosstalk is minimized.

Here in this paper we have developed algorithms only for sum-crosstalk minimization problem. The CRP of area minimization being an NP-hard problem; several heuristics have been proposed for routing channels in different routing models. The problem is polynomial time solvable if the channel instances are free from any vertical constraint, and 170 Achira Pal et al. there are algorithms for computing dmax-track routing solutions for such instances.

Since the problem of minimizing area for an instance of routing channel with only horizontal constraints is polynomial time solvable (using dmax tracks), we define such instances as simplest channel instances of channel routing. We define a channel specification as general, if both the constraints are present in it.

However, the crosstalk minimization problem for two-layer routing, both in case of simplest as well as general channel instances are NP-hard [6], i.e., there exists no polynomial time algorithm for crosstalk minimization in two-layer channel using the routing model under consideration. In this paper we have developed heuristic algorithms for two-layer channel routing for simplest as well as general instances of channel specifications, as stated in the following section.

Algorithms for Crosstalk Minimization

In the previous section we have mentioned that crosstalk minimization problem for twolayer channel routing is NP-hard, even if the channel instances are simplest. So, first we develop crosstalk minimization algorithm for two-layer channel routing, where instances are free from any vertical constraint. Then we extend it for two-layer routing with general channel instances. Before that let us consider a simplest channel instance of only three nets and illustrate the presence of crosstalk between nets (or intervals), when these are assigned to tracks in a two-layer VH routing model. Interestingly, the fact to be noticed that just by reassigning the nets to tracks, the amount of crosstalk is reduced to 30.77% to that of in Figure 1(a). Hence we have the following observation. Observation 1: The amount of crosstalk is mostly reduced if a net (or interval) of smaller span is sandwiched by two nets (or intervals) of larger spans, or vice versa.

This observation is the motivation in developing the first algorithm. 3.1. Algorithm track interchange (for simplest channel instances) First of all we compute a dmax-track feasible routing solution either using LEA, or MCC1, or MCC2. Then we reassign the nets trackwise so that the total amount of crosstalk is reasonably reduced. In order to do so, we define the term effective interval of nets that are assigned to a track. The effective interval (EI) of a track (for the nets assigned to it) is computed by adding the net spans of all the nets belonging to the track. Let us assume that we have an instance of the CRP with at most t nets overlapping each other. We sort the tracks according to their EI in descending order. It may happen that two or more tracks having the same effective intervals. In such cases, we sort these equal EI tracks based on their total intervals (TI) (i.e., the interval between the leftmost terminal and the rightmost terminal of the net(s) assigned to a track) in ascending order. It is done so, because, in between two tracks with same EI, the one with larger TI is sparser than that of the other Algorithms for Reducing Crosstalk in Two-Layer Channel Routing 171 track; so the track with more TI should come later in the computed sorted order (using EI).

To sort the tracks based on the criteria with primary key: EI and secondary key: TI, we may use any sorting algorithm that runs in O(n2) or lesser time. Now we trackwise rearrange the nets in a sandwiched fashion as stated below. For a set of t sorted tracks {n1, n2, …, nt}, the rearranged sequence is {n1, nt, n2, nt – 1, n3, nt – 2, …}. A more improvised rearranging sequence is {n1, nt, n3, nt – 2, …, nt – 3, n4, nt – 1, n2}. Reduction of crosstalk in both these cases is more or less same; however, the later sequence is more desirable in practice. In this paper, though we are interested only with crosstalk between nets assigned to adjacent tracks, but as a high performance optimization criterion, we should reduce crosstalk that occurs between non-adjacent tracks also; the later rearranging sequence optimizes that too.

=================================

Algorithm track interchange (for general channel instances)

Here channel instances contain vertical constraints that are represented by VCG, which is a directed graph VC=(V,A), where a net ni is represented by a vertex vi?V, and a directed edge (vi,vj)?A (or directed path from vertex vi to vertex vj in VC) represents that the net ni is to be assigned to a track above the track to which the net nj is assigned. In order to route
the nets and obtain feasible routing solutions, the vertical constraints should be maintained.

Here we cannot apply the crosstalk minimization algorithm directly, because, free rearranging the tracks may introduce undesired vertical constraint violation in the case of general channel instances. So we need to compute a group of freely interchangeable tracks (that are not vertically constrained to each other) for a given routing solution on which we can apply our algorithm Track Interchange in one iteration. This process of computing freely interchangeable tracks and their assignment to tracks in successive iterations is continued until all the nets are assigned, and may result in 172 Achira Pal et al. obtaining a reduced crosstalk routing solution of the given general channel instance. A set T={t1, t2, …, tk} of t tracks is called freely interchangeable, if there is no vertical constraints between any pair of nets (ni,nj), where nets ni and nj are assigned to two different tracks tp and tq, respectively, such that tp, tq ? T. In order to get a group of such freely interchangeable tracks, we can use a modified VCG, called RVCG, where each vertex represents a set of nets that are assigned to a track. So, the number of vertices in RVCG is same as the number of tracks needed to route the channel. If nets ni and nj are assigned to tracks tp and tq, and there is an edge (or a path) from ni to nj (i.e., nj is successor of ni) in VC, then there should be an edge from tp to tq in the RVCG. As an RVCG is computed from a given two-layer feasible routing solution, it is a directed acyclic graph (DAG) without any parallel edge between any pair of vertices. We use the terms, an RVCG vertex and a track interchangeably.

So, from the computed RVCG, we first identify the set T1 of source vertices (that are freely interchangeable), and assign them to the topmost |T1| tracks using algorithm in Section 3.1. We delete the corresponding vertices from the RVCG, and compute another set T2 of source vertices (that are freely interchangeable). We apply the same algorithm and assign them to the next |T2| tracks of the channel. This process is continued until trackwise all the nets are reassigned to tracks.

A modified version of this algorithm is greedy in nature. Here instead of considering the set of source vertices at a time (in one iteration) for their assignment to tracks, we select the source vertex in the RVCG having maximum EI among all the sources in it. We assign it to the topmost track, and modify the RVCG by deleting the selected vertex. Then in the next iteration, we select the source vertex from the modified RVCG whose assignment renders minimum crosstalk, and delete the vertex from the modified RVCG in order to start the third iteration. This process is continued until all the vertices of the RVCG are considered for their assignment to tracks in subsequent iterations.

===============================

Algorithm Net-Change

Algorithm Net-Change is basically a greedy algorithm where each net after their assignment following algorithm Track Interchange is considered one after another in some sequence. Then it is checked whether net ni with span Ii assigned to track tp is reassignable to some other track (other than tp) so that all the constraints are satisfied but crosstalk is reduced. This algorithm may result in reducing crosstalk further. In practice, we successively call algorithms Track Interchange and Net-Change in order to compute a mostly reduced crosstalk routing solution for general channel instances. The computational complexity of this algorithm is O(n2), where n is the number of nets belonging to the channel.

Terminology

Parallel bubble sorting

river routing

Mini swap model

overlap model

two-layer Manhattan routing model

reserved two-layer Manhattan channel routing

reserved two-layer (VH) Manhattan channel routing model

Literature

Gao, Shaodi and Hambrusch, Susanne E.: Two-Layer Channel Routing with Vertical Unit-Length Overlap p14, 1986

Pal, Achira et al: Algorithms for Reducing Crosstalk in Two-Layer Channel Routing, Journal of Physical Sciences, Vol. 10, 2006, 167 – 177, p11

Savage, John E: The parallel complexity of minimizing column conflicts p5, IEEE, 1992

Szeszler, David: A New Algorithm for 2–layer Manhattan Channel Routing, June 2008, p7

Wang, Deborah C: Novel routing scheme for IC layout Part I Two layer channel routing, ACM 1991, p5 ..........

Wiesel M. and Mlynski S A: TWO-DIMENSIONAL CHANNEL ROUTING AND CHANNEL INTERSECTION PROBLEMS, p7, 0420-0098/82/0000/0733500.75 ? 1982 IEEE .................................


Dogleg Algorithm

Often in order to obtain a feasible routing solution or a solution with less number of tracks, the horizontal wire segment of a net is split into two (or more) parts and assigned to different tracks. This kind of routing is known as dogleg routing (Deutsch, 1976; Pal, 2000; Szymanski, 1985). In no-dogleg routing no such splitting of horizontal wire segments is allowed, and it needs less via holes. If the route for a net is allowed to dogleg only in those columns in which it contains a terminal, then it is called a restricted dogleg route; otherwise, it is known as an unrestricted dogleg route. In this paper, we study the issues of representing the constraints present in a channel and computing reduced area channel routing solutions for two-layer no-dogleg VH channel routing only.

Dogleg Router

Deutsch, “A dogleg channel router,” 13rd DAC, 1976.

Doglegs are used to place parts of the same net on different tracks.

  • A dogleg is a vertical segment that connects two trunks located in two different tracks.
  • May lead to a reduction in channel height.

Dogleg router allows multi-terminal nets and vertical constraints.

  • Each multi-terminal net is broken into a set of 2-terminal nets.

Two parameters are used to control routing:

  • Range: Determine the # of consecutive 2-terminal subnets of the same net that can be placed on the same track.
  • Routing sequence: Specifies the starting position and the direction of routing along the channel.

Modified Left-Edge Algorithm is applied to each subnet.

Cannot handle cyclic vertical constraints.

Dogleg Router: Algorithm

? Step 1:
– If cycle exists in the VCG, return with failure.
? Step 2:
– Split each multi-terminal net into a sequence of 2-terminal nets.
? A net 2 .. 2 .. 2 will get broken as 2a .. 2a 2b .. 2b.
– HCG and VCG gets modified accordingly.
? Step 3:
– Apply the extended left-edge algorithm to the modified problem.


Left-edge routing

Left-edge routers sort wires by the boundary formed by the leftmost and rightmost pins. It orders wires one at a time using a greedy method that places segments into tracks. It fills tracks one at a time, packing segments to minimize unused space in a track. The route is complete when all wires have been assigned to a track.

  • Proposed by Hashimoto and Stevens in 1971 “Wire routing by optimizing channel assignment within large apertures,” DAC-71.
  • Regarded as the first channel routing algorithm
  • Originally used in PCB design
  • Can be applied on VLSI physical design
  • Requires building the Vertical Constraint Graph (VCG) for a channel routing problem

=================================================

The Left-Edge Algorithm (summary)

Step 1: Build the Vertical Constraint Graph (VCG) for the input channel routing problem

Step 2: Place horizontal segments (choose nets (1) that do not have ancestors in the VCG and (2) whose horizontal segments do not overlap) and update the VCG

Step 3: Repeat Step 2 until all the horizontal segments have been placed

==================================================

THE LEFT-EDGE ALGORITHM

Channel routing problems without vertical constraints can be solved efficiently by the left-edge algorithm.

Problem: given a set of segments (intervals) [ximin , ximax], put non-overlapping segments on the same track such that the number of tracks is minimal.

THE LEFT-EDGE ALGORITHM
l := ‘‘list of intervals sorted by first coordinate’’;
t := 0;
while ‘‘l is not empty’’
do f := ‘‘first element in l’’;
t := t + 1
repeat ‘‘put f on track t’’;
f := ‘‘first element in l non-over
lapping with f’’
until ‘‘no such f can be found’’;
od;

INTERVAL GRAPHS
A set of intervals defines an interval graph:
* there is a node for each interval,
* nodes corresponding to overlapping intervals are connected by an edge.

==================================================

Basic Left Edge Algorithm

? Assumptions:
– Only two-terminal nets.
– No vertical constraints.
– HV layer model.
– Doglegs are not allowed.
? Basic Steps:
– Sort the nets according to the x-coordinate of the leftmost terminal of the net.
– Route the nets one-by-one according to the order.
– For a net, scan the tracks from top to bottom, and assign it to the first track that can accommodate it.
? In the absence of vertical constraints, the algorithm produces a minimum-track solution.

Extension to Left-Edge Algorithm
– Vertical constraints may exist, but there are no directed cycles in the VCG.
– Select a net for routing if
? The x-coordinate of the leftmost terminal is the least.
? There is no edge incident on the vertex corresponding to that net in the VCG.
– After routing a net, the corresponding vertex and the incident edges are deleted from the VCG.
– Other considerations same as the basic left-edge algorithm.

===========================

Features of Basic Left-Edge Algorithm

  • Only two-terminal nets in the problem.
  • No Vertical constraint in the problem.
  • HV layer model is used.
  • Doglegs are not allowed.
  • Nets are sorted according to the x-coordinate of the leftmost terminal of the net.
  • Nets are routed one-by-one according to the order.
  • For a net, tracks are scanned from top to bottom, and the rst track that can accommodate the net is assigned to the net.
  • It produces a routing solution with minimum number of tracks.

============================

Unconstrained left-edge algorithm

ALGORITHM Unconstrained ChannelRouter
Begin
1. Sort all nets on their leftmost end positions;
2. Select the net with the lowest left position;
Place it on the lower most available track; Delete net from list;
3. Continue scanning the list and select from it nets that do not overlap with the nets assigned to this track; Assign the nets to the current track and delete from list;
4. If list = φ Then Goto 2;
5. Exit
End.

============================

Constrained left-edge algorithm

ALGORITHM Constrained ChannelRouter
Begin
1. Sort all nets on their leftmost end positions;
2. Select the next net n with the lowest left-end position;
If n has no descendants in VCG
Then Begin
Place n on the lowermost available track;
Delete n from the sorted list;
Delete n from VCG
End
Else Goto 2
EndIf
3. Continue scanning the sorted list and from it select those nets which do not overlap with nets assigned to this track and have no descendents in VCG; Remove all selected nets from the list
4. If list = φ Then Goto 2
5. Exit
End.


Manhattan routing

Manhattan routing model
  • (k) Two-layer
    • Restricted / Reserved
      • Non Overlap / Overlap
        • Manhattan routing model
Manhattan routing model

Restricted Manhattan routing model
  • safe & unsafe endpoints
  • safe & unsafe wires
Reserved Layer Manhattan routing model
Reserved layer Manhattan routing model, where only horizontal and vertical wire segments are used for interconnecting the nets, and the wire segments are assigned to the respective layers (Pal, 2000; Pal et. al., 1995; Pal et. al., 1993; Yoshimura and Kuh, 1982).

(k) Two-layer Manhattan routing model ( two-layer VH routing model)

Two-layer Manhattan routing model, where one layer is reserved for horizontal wire segment only and the other is reserved for vertical wire segment only. Such a routing model is known as the two-layer VH routing model. In this model, the CRP is characterized by two important constraints, viz., the horizontal constraint and the vertical constraint. These constraints are usually represented by two graphs, viz., the horizontal constraint graph (HCG) and the vertical constraint graph (VCG), respectively. The HCG is simple undirected graph. Specifically, the HCG is an interval graph and, therefore, a perfect graph. The VCG is an arbitrary directed graph that may or may not contain any cycle. Reduced vertical constraint graph (RVCG) is another directed graph that can be formed from VCG [8]. The local density of a column (in a channel) is the maximum number of nets passing through it. The channel density is the maximum of all the local densities in a channel.

Non Overlap Manhattan routing model
Overlap Manhattan routing model


Over-the-cell channel routing

Over The Cells (OTC) routing

Traditional channel routing algorithms have proved very successfull in reducing channel height. Any further reductions are only possible if some nets are routed “outside” the channel. Based on this observation, some researchers have proposed utilisation of over-the-cell area to obtain further reduction in the channel height. This style of routing is called over-the-cell channel routing. As more metal layers are becoming available for routing in the standard cell design style, routing over the cells becomes both practical and important.

The inclusion of both over-the-cell and channel optimisation in a single channel routing domain will provide an effective framework for area/energy optimisation. However, this will increase the burden on the routing algorithm due to the significant increase in search space. To cope with this multiobjective search problem,? evolutionary algorithms, such as Genetic Algorithms (GAs) have been employed.

we study the effect of an evolutionary over-the cell router, developed by the authors, on energy loss and area reduction in all channel areas and compare this with a traditional over-the-cell router. We show that significant reductions in energy loss are achieved by the evolutionary over-the-cell router in all the channel areas.

Over-the-cell Channel Routing

? Another extension to the classical channel routing problem is over-the-cell channel routing.
? This method is employed when there are at least two layers in the routing channel, and one routing layer over the channel.
? Certain nets can be partially or totally routed on one side over the channel using the single available layer. Then, the remaining net segments are chosen for routing.
? Therefore, a common approach to over-thecell channel routing is to divide the problem into three steps, namely, (1) routing over the channel, (2) choosing the net segments, and (3) routing within the channels.
? The third step can be accomplished easily using one of the conventional techniques discussed in Chapter 7 of the text.
? Cong and Liu showed that the first step can be formulated as the problem of finding a maximum independent set of a circle graph and can be solved optimally in quadratic time.
? In this step a row of terminals are routed on one side of the channel using a single routing layer.
? The result is that the number of hyperterminals are minimized.
? Cong and Liu called this problem multiterminal single-layer one-sided routing problem (MSOP).
? The second step is formulated as the problem of finding a minimum density spanning forest of a graph.
? An efficient heuristic which produces satisfactory results is proposed.
? A channel routing problem and its over-the-cell solution are illustrated in Figure below.

Over-The-Cell Channel Routing In Standard Cell Design

horizontally connected vertically connected (HCVC) model

two row fixed height planar routing (TFPR) problem

There are two physical models

The Horizontally connected vertically divided model (HCVD)

The horizontally connected vertically connected model (HCVC)

Liu, Xiaolin and Tollis, Ioannis G.: Improving Over-The-Cell Channel Routing In Standard Cell Design p4, 1994 ACM 0-89791-690-5/94/0011/0606.......................

Cong, Jason et al: PHYSICAL MODELS AND EFFICIENT ALGORITHMS FOR OVER-THE-CELL ROUTING IN STANDARD CELL DESIGN p27 Nov 2007 ...........

OVER THE CELL ROUTING WITH VERTICAL FLOATING PINS

Greedy Algorithm for Over-the-Cell Channel Routing

genetic algorithm for over the cell and channel area optimzation

THE EVOLUTIONARY ALGORITHM

General properties: A traditional GA-based algorithm was used for this work. The developed algorithm is based on a model developed by Goldberg. Our? investigations revealed that with a population of 500 chromosomes, the following GA characteristics are necessary for a performance which provides a ‘good’ trade off in speed and quality of solutions:

· Two point crossover and random mutation at rates of 0.6 and 0.001.

· Chromosome selection procedure using Baker’s Stochastic Universal Sampling algorithm.

· Employment of an elitist selection strategy.

The chromosome structure for a single net X is presented as [top,int,bot,id]. Where, top = top track on which net X is placed; int = internal track on which net X is placed; bot = bottom track on which net X is placed; id = the net number.

Fitness function: A key component of the GA is the fitness evaluation stage, where the quality of the different routing solutions are assessed. Beginning with a given netlist (see Figure 1), and after initialisation, the fitness function starts by identifying all multi-terminal net circuit segments for over-the cell routing, and places them on tracks over-the-cell according to horizontal constraints. Further, it proceeds to route the remaining net circuits inside the channel subject to horizontal and vertical constraints. For a given structure Y, the fitness function F(Y) can be specified as:

F(Y) = OTC(Y) + HV(Y) + VV(Y).

Where OTC, HV and VV are routing procedures and are described as follows:

Over-the-cell routing (OTC): Performs the routing of multiterminal net circuits in the over-the-cell areas, and returns their number. After this procedure only net? circuits with single pin connections at both the top and bottom will remain inside the channel area.

Horizontal violation elimination (HV): Carries out the elimination of horizontal violations, by returning the number of net circuits without such violations. It is applied to both the over-the-cell and channel areas.

Vertical violation elimination (VV): Performs the elimination of vertical violations, by returning the number of two pin (terminal) net circuits connected to the top and bottom pins inside the channel area without such violations. As there are no vertical violations in the regions over-the-cell, this procedure is not applied.

Evolutionary 3D Over?the?Cell Router

Evolutionary Constraint Satisfaction Solution for Over The Cell Channel Routing


Topological Routing

Topological Routing 1976 / 1990 / 1992

(Haruyama, Shinichiro)

topological definition

  • topological sort
  • graph colouring

topological graph
Interleaving mesh

VLSI Routing flow based on Topological Patterns

Multi-Layer Topological Planar Routing in switchboxes and channels

set covering resolution

set covering problem

two-terminal channel crossing problem

Topology-Agnostic Fault-Tolerant NoC Routing Method

Topological Channel Routing 1990 / 1992

[Cox+92, JaMa94] [ChSa93, LiTh93, Suz+95, Zhou96] Hugh98

Topological Channel Routing Using Constraint Logic Programming

a channel router designed to exploit an arbitrary number of layers

CLP (Constraint Logic Programming)

The overall problem is broken into two components: topological definition followed by physical placement. a new channel routing approach which explicitly separates the channel routing problem into two relatively independent portions: topological definition and physical placement.

Topological definition specifies the assignment of wires to layers and the mapping from a two-dimensional topological model to a set of intervals. Physical placement is the process of creating a layout from the topological relationships. It defines the sequence of doglegs and trunks composing a wire and specifies the placement of these items within the channel.

Topological definition

Topological definition is further decomposed into

  • the canonical problems of topological sort and
  • graph colouring.

The resulting computational tasks are naturally modelled as a

  • constraint-satisfaction problem and
  • solved using constraint logic programming.

=============================================

The topological definition subproblem has two components: deriving an interval representation of the wires and assigning wires to layers.

A solution to these components relies on and maintains the equivalence to the topological model and determines: (a) the number of vias, (b) the minimum possible channel height, and (c) the parameters of the physical placement subproblem.

The components of the topological definition subproblem are independent in that they can be solved in any order.

Physical placement

Multilayer Topological Planar Routing Algorithm

Iterative Peeling Algorithm

================================

Haruyama [Haru92] uses a topological model which represents terminals, vias, and crossings of nets in a topological graph.

Literature

Cong, Jingshen et al: A Provably Good Multilayer Topological Planar Routing Algorithm In IC Layout Designs p9 1992.

Cong, Jingshen et al: A Provably Good Multilayer Topological Planar Routing Algorithm In IC Layout Designs 1992 p17

Coudert, Olivier and Shi, C.-J. Richard: Exact Multi-Layer Topological Planar Routing, 1995 ??? p5

Doreau, Michel T. and Abel, Luther C.: A TOPOLOGICALLY BASED NON-MINIMUM DISTANCE ROUTING ALGORITHM p8...1976?

Flich, J.; et al. “A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms”. IEEE Transactions on Parallel and Distributed Systems, v.23(3), 2012, pp.405-425

Haruyama, Shinichiro: New routing strategies for VLSI, chapt 3, Dec 1990 p158

Haruyama, Shinichiro: Topological channel routing, IEEE Transactions on Computer-Aided Design of Integrated Circuits, 11(10):1177-1197, October 1992.

Haruyama, Shinichiro; Wong D F and Fussell Don: Topological channel routing, Proceedings of IEEE International Conference on Computer-Aided Design, pp 406-409, 1988.

Haruyama, Shinichiro; Wong D F and Fussell Don: Topological routing using geometrical information, Proceedings of IEEE International Conference on Computer-Aided Design, 1990

Hsu, Chi-Ping: . Minimum via topological routing, IEEE Transactions on Computer-Aided Design, Vol CAD2, pp 235-246, 1983.

Hughes, Andrew: A Multi-layer Channel Router Implemented using a Topological Channel Routing Model, M.Sc. thesis, Department of Computer Science, University of Saskatchewan, Saskatoon, Canada, July 1998

Hughes, Andrew; Kusalik, Anthony J. and McCrosky, Carl D.: Topological Channel Routing Using Constraint Logic Programming, p15, March 26, 2000 .......... .............. 7

$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

Marek-Sadowska, M., ‘‘An unconstrained topological via minimization’’. IEEE Trans. on Computer-Aided Design (1984) Vol. CAD-3, pp. 184-190.

Rim, C. S., T. Kashiwabara and K. Nakajima, ‘‘Exact Algorithms for Multilayer Topological Via Minimization’’. IEEE Trans. on CAD (1989) Vol. 8, pp. 1165- 1173.

Sarrafzadeh, M. and D. T. Lee, ‘‘A New Approach to Topological Via Minimization’’. IEEE Trans. Computer-Aided Design (1989) Vol. 8, pp. 890- 900.

Sarrafzadeh, M. and D. T. Lee: Topological Via Minimization Revisited, IEEE Trans. on Computers, Nov 1991, p6

Solheim, ?shild Gr?nstad: Topology Agnostic Methods for Routing, Reconfiguration and Virtualization of Interconnection Networks February 14, 2012, p183

Wachter, Eduardo et al: Topology-Agnostic Fault-Tolerant NoC Routing Method p6, 978-3-9815370-0-0/DATE13/?2013 EDAA..


Virtual Channel Router

Virtual Channel Router? 2001

?
?

Terminology

sharing Block RAMs between multiple router ports

virtual channel buffers

BRS (Block RAM Split)

BRS (Block RAM Split) router architecture

synthetic traffic patterns on mesh and torus networks

Adaptive Logic Module (ALM)

Application- Specific Integrated Circuit (ASIC) NoCs

torus network based dimension-ordered routing

VC buffers

Distributed RAMs

Block RAMs

RASoC

LiPaR?

?

Network-on-chip (NoC)

on-chip network

on-chip interconnection network

system-on-chip (SoC)

heterogeneous system-on chip

tiled heterogeneous reconfigurable SoC

?

virtual channel router

?

packet-switched on-chip network

packet switching network with virtual channel flow control

?

Central Coordination Node (CCN)

?

GPP – General-Purpose Processor

DSP – Digital Signal Processor

ASIC – Application-Specific Integrated Circuit

FPGA – Field-Programmable Gate Array

DSRC – Domain-Specific Reconfigurable

Greedy Algorithms

Adaptive routing

Cut-through routing

Wormhole routing

Wormhole routing with virtual channel flow control

?

arbitration unit

virtual channels (VCs)

source routing

multi-flit header

data flits

tail flit

?

round robin arbiter (RRA)

request/acknowledge multiplexers

Literature
?

Kavaldjiev, Nikolay , Smit, Gerard J. M. , and Jansen, Pierre G.: A Virtual Channel Router for On-chip Networks. July 9, 2004 .........p5 ..........................

Kim, John: Low-Cost Router Microarchitecture for On-Chip Networks p12, MICRO’09, December 12–16, 2009, New York, NY, USA.

Kwa, Jimmy , Aamodt, Tor M.: Small Virtual Channel Routers on FPGAs Through Block RAM Sharing, 978-1-4673-2845-6/12, 2012 IEEE ......... p9 ...................3

Mullins, Robert , West, Andrew and Moore, Simon: Low-Latency Virtual-Channel Routers for On-Chip Networks


Yoshimura-Kuh Channel Routing

Net Merge Channel Router - Yoshimura and Kuh
Yoshimura & Kuh, “Efficient algorithms for channel routing,” IEEE TCAD, Jan. 1982.

Yoshimura-Kuh Channel Routing
Yoshimura and Kuh Algorithm
merging of nets by Yoshimura and Kuh

Yoshimura and Kuh Algorithm

? Motivation: If there is a path n1-n2-n3-· · ·-nk in the vertical constraint graph, then obviously no two nets among {n1, n2, n3, · · ·, nk } can be placed on the same track.
? Therefore, if the longest path in terms of the # of nodes is k, at least k tracks are necessary.
? We now present two algorithms proposed by Yoshimura and Kuh.
– The first algorithm uses the VCG and the zone representation of HCG and attempts to minimize the longest path in the VCG. This is done by merging nodes of VCG so that the longest path length after merging is minimized.
Obviously, this merging is performed for the purpose of minimizing the channel density.
– The second algorithm proposed by Yoshimura and Kuh achieves longest path minimization through matching techniques on a bipartite graph.
? Both techniques report better results than the dogleg algorithm.
? Before describing these algorithms we first introduce the required terminology.

============================================

Definitions

? Let i and j be the nets for which,
(a) there exists no horizontal overlap in the zone representation, and
(b) there is no directed path between node i and node j in the vertical constraint graph, (i.e., net i and net j can be placed on the same horizontal track). Then, the operation “merging of net i and net j”, results in the following.
(a) It modifies the vertical constraint graph by shrinking node i and node j into a single node i · j; and,
(b) It updates the zone representation by replacing net i and net j by net i·j which occupies the consecutive zones including those of net i and net j.

==========================================

Yoshimura and Kuh Net Merge Channel Router

? Due to Yoshimura and Kuh.
? Basic idea:
– If there is a path of length p in the VCG, at least p horizontal tracks are required to route the channel.
– Try to minimize the longest path in the VCG.
– Merge nodes of VCG to achieve this goal.
? Does not allow doglegs or cycles in the VCG.
? How does it work?
– Partition the routing channel into a number of regions called “zones”.
– Nets from adjacent zones are merged.
? Merged nets are treated as a “composite net” and assigned to a single track.

Key steps of the algorithm:
a) Zone representation
b) Net merging
c) Track assignment

Step 1: Zone Representation
? Let S(i) denote the set of nets whose horizontal segments intersect column i.
? Take only those S(i) which are maximal, that is, not a proper subset of some other S(j).
? Define a zone for each of the maximal sets.
? In terms of HCG / interval graph, a zone corresponds to a maximal clique in the graph.

Step 2: Net Merging
? Let Ni and Nj be two nets for which the following conditions are satisfied:
– There is no edge between vi and vj in HCG.
– There is no directed path between vi and vj in VCG.
? Nets Ni and Nj can then be merged to form a new composite net.
– Modifies VCG by merging nodes vi and vj into a single node vi.j.
– Modifies HCG / zone representation by replacing nodes vi and vj by a net vi-j, which occupies the consecutive zones
including those of nets Ni and Nj.

The process is iterative:
– Pairs of nodes are successively merged.
– At every step of the iteration, in case of multiple choices, merge the net-pair that minimizes the length of the longest path in the VCG.
– That is, the increase in length is minimum.
? A result:
– If the original VCG has no cycles, then the updated VCG with merged nodes will not have cycles either.

Iteration 1 of the example:
– We can merge nets pairs (1,6), (3,6) or (5,6).

Step 3: Track Assignment
? Each node in the final graph is assigned a separate track.
? Actually we apply the left-edge algorithm to assign horizontal tracks to the merged nets.
– The list of nets sorted on their left edges, subject to the vertical constraint, is:
[ 4-10, 1-7, 5-6-9, 2, 3-8 ]
Track 1: Nets 4 and 10
Track 2: Nets 1 and 7
Track 3: Nets 5, 6 and 9
Track 4: Net 2
Track 5: Nets 3 and 8

=================================

An Improved Algorithm Based on Matching

? In the algorithm of the previous section it is possible that a merging of nets may block subsequent mergings.
? To avoid this type of situation as much as possible Yoshimura and Kuh introduced another algorithm.
? In this algorithm a bipartite graph Gh is constructed where a node represents a net and an edge between net a and net b indicates that nets a and b can be merged.
? A merging is expressed by a matching on the graph which is updated dynamically.

Extended Net Merge Channel Router

Limsk Yoshimura-Kuh Channel Routing p16.pdf?????????

Yoshimura, Takeshi and Kuh, Ernest: Efficient algorithm for channel routing, IEEE transaction on computer aided design of integrated circuits and systems, vol CAD-1, no.1, Jan. 1982?


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000VLSIChip
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│	├Baker CMOS Circuit Design Layout and Simulation 3rdEdition p1214.pdf
│	├Browy A TOP-DOWN APPROACH TO IC DESIGN INTEGRATED CIRCUIT DESIGN METHODOLOGY GUIDE p369.pdf
│	├Chanak NETLIST PROCESSING FOR CUSTOM VLSI VIA PATTERN MATCHING p105.pdf
│	├De Micheli Synthesis And Optimization Of Digital Circuits p586.pdf
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│	│	├Fischer Design Flow.pdf
│	│	└Traditional VLSI Design Flow Revisited p24.pdf
│	├Even Digital Logic Design A Rigorous Approach p424.pdf
│	├Ghongade Lecture 0 VLSI Design Introduction to the subject p455.pdf
│	├Glesner VLSI Design of Integrated Circuits p562.pdf
│	├Govindarajan Algorithm for design space exploration p216.pdf
│	├Govindarajan Algorithm for design space explorationUN p216.pdf
│	├Harris Digital Design and Computer Architecture p561.pdf
│	├Hendriks High Level Synthesis Performance Analysis and Code Optimization p105.pdf
│	├Hollstein VLSI Design of Integrated Circuits Wintersemester 2006 2007 p439.pdf
│	├Kaeslin Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication p879.pdf
│	├Kang CMOS DIGITAL INTEGRATED CIRCUITS - Analysis and Design p683.pdf
│	├Lai 集成电路设计方法与设计流程 p40.pdf
│	├<LowPower>
│	│	├Allam  New Methodologies for Low Power High Performance Digital VLSI Design p225.pdf
│	│	├Sivakumar Recent Trends in Low Power VLSI Design p15.pdf
│	│	└Subalakshmi Low Power VLSI Design Trends p10.pdf
│	├Mailhot TECHNOLOGY MAPPING FOR VLSI CIRCUITS EXPLOITING BOOLEAN PROPERTIES AND OPERATIONS p146.pdf
│	├Mano Digital Design p565.pdf
│	├Meinel Algorithms and data stuctures in VLSI designs p279.pdf
│	├Mukherjee Introduction to NMOS and CMOS VLSI Systems Design p367.pdf
│	├Nelson Digital Logic Circuit Analysis and Design p866.pdf
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│	│	├Etawil Convex Optimization and Utility Theory New Trends in VLSI Circuit Layout p146.pdf
│	│	├Padhy Recent trends in VLSI Design Applications.pdf
│	│	└Wang VLSI-trends.pdf
│	├Pedroni Circuit design with VHDL p376.pdf
│	├<PhysicalDesign>
│	│	├Berlier A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms p341.pdf
│	│	├Brenner Theory and Practice of VLSI Placement p164.pdf
│	│	├Cai ROUTING CHANNELS IN VLSI LAYOUT p143.pdf
│	│	├Deza Global Routing in VLSI Design Algorithms, Theory, and Computational Practice p24.pdf
│	│	├DICKSON Global Routing in VLSI Algorithms, Theory, and Computation p76.pdf
│	│	├Egeblad Placement Techniques for VLSI Layout Using Sequence-Pair Legalization p240.pdf
│	│	├Kahng VLSI Physical Design From Graph Partitioning to Timing Closure p319.pdf
│	│	├On Planar Routing of Multi-Terminal Nets in VLSI Physical Design.pdf
│	│	├OZDAL ROUTING ALGORITHMS FOR HIGH-PERFORMANCE VLSI PACKAGING p169.pdf
│	│	├Sait VLSI PHYSICAL DESIGN AUTOMATION Theory and Practice p503.pdf
│	│	├Sarrafzadeh An Introduction to VLSI Physical Design 1996 p350.pdf
│	│	└Tzeng Integrated placement and routing for VLSI layout synthesis and optimization p106.pdf
│	├Qu INTELLECTUAL PROPERTY PROTECTION IN VLSI DESIGNS p204.pdf
│	├Rabaey Digital Integrated Circuits A Design Perspective p513.pdf
│	├<read>
│	├SchorrSuhl Algorithms for Circuit Sizing in VLSI Design p216.pdf
│	├Seneys VLSI Integrated Circuits and Systems Principles and Design Methods p141.pdf
│	├shin Advanced MOSFET Designs and Implications for SRAM Scaling p108.pdf
│	├Shrestha VLSI Design & Implementation of High-Throughput Turbo Decoder for Wireless Communication Systems p198.pdf
│	├Smith Microelectronic circuits 5th p696.pdf
│	├<Tests>
│	│	└Wang VLSI TEST PRINCIPLES AND ARCHITECTURES p809.pdf
│	├WAKERLY DIGITAL DESIGN PRINCIPLES PRACTICES p795.pdf
│	├Weste CMOS VLSI Design A Circuits and Systems Perspective p867.pdf
│	└Wolf Modern VLSI Design IP-Based Design p631.pdf
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│	│	│	├Banerjee Novel Transistor Concepts Based on 2D Systems‐ Graphene and Topological Insulators p47.pdf
│	│	│	├Benfdila Graphene Material and Perspectives for Nanoelectronics p9.pdf
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│	│	│	├Chahardeh A Review on Graphene Transistors p5.pdf
│	│	│	├Cobas Graphene-Based Magnetic Tunnel Junctions p4.pdf
│	│	│	├Ferrari Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems p213.pdf
│	│	│	├GALIB Graphene grown by chemical vapor deposition on evaporated copper thin films p31.pdf
│	│	│	├Guo Graphene Doping A Review p10.pdf
│	│	│	├Han Graphene spintronics p14.pdf
│	│	│	├Jena Tunneling Transistors Based on Graphene and 2-D Crystals p18.pdf
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│	│	│	├Klekachev Graphene Transistors and Photodetectors p6.pdf
│	│	│	├Lee Graphene Nanoelectronics - From Synthesis to Device Applications p158.pdf
│	│	│	├Lemme Current Status of Graphene Transistors p11.pdf
│	│	│	├Lin Enhanced Performance in Epitaxial Graphene FETs With Optimized Channel Morphology p3.pdf
│	│	│	├Lindgren Electrochemical Functionalization of Epitaxial Graphene p55.pdf
│	│	│	├Mahmood Towards Graphene based mono-molecular electronics Structural and electrical characterization of side-gated devices p214.pdf
│	│	│	├MAJUMDAR Theory of High Field Transport in Graphene Transistor p12.pdf
│	│	│	├Miao Chemical Vapor Deposition of Graphene p20.pdf
│	│	│	├Nouchi Metal-contact effect on grapheme p11.pdf
│	│	│	├Ou Graphene Semiconductor Heterojunctions and Devices p139.pdf
│	│	│	├Parrish A Compact Model for Graphene FETs for Linear and Non-linear Circuits p4.pdf
│	│	│	├Pascal Graphene three-terminal nanojunction rectifiers p124.pdf
│	│	│	├Pembroke Chemical and Physical Graphene Modifications p196.pdf
│	│	│	├Pollard Growing Graphene via Chemical Vapor Deposition p47.pdf
│	│	│	├Ponomarenko Tunable metal–insulator transition in double-layer graphene heterostructures p11.pdf
│	│	│	├Popov Carbon nanotubes properties and application p42.pdf
│	│	│	├RAHMAN Growth of Graphene on Nickel using a Natural Carbon Source by Thermal Chemical Vapor Deposition p7.pdf
│	│	│	├Rizzi On the fabrication and characterization of high-performance graphene electronic devices p81.pdf
│	│	│	├Ruiz-Vargas SYNTHESIS, MORPHOLOGY AND PROPERTIES OF POLYCRYSTALLINE GRAPHENE MEMBRANES p134.pdf
│	│	│	├SAGAR Graphene-based Field-effect Transistors p113.pdf
│	│	│	├Schwierz Graphene Transistors p35.pdf
│	│	│	├SCIENTIFIC AMERICAN The_Next_20_Years_of_Microchips p6.pdf
│	│	│	├Sharma Graphene based field effect transistors Efforts made towards flexible electronics p12.pdf
│	│	│	├Singh Quantum Hall Effect and Electromechanics in Graphene p186.pdf
│	│	│	├Sordan Gigahertz Multi-Transistor Graphene Integrated Circuits p7.pdf
│	│	│	├Sprinkle Scalable templated growth of graphene nanoribbons on SiC p16.pdf
│	│	│	├Sreenath Compact model for switching characteristics of graphene field effect transistor p8.pdf
│	│	│	├Stander Transport measurements on graphene p-n junctions p141.pdf
│	│	│	├Suk Enhancement of the Electrical Properties of Graphene Grown by Chemical Vapor Deposition via Controlling the Effects of Polymer p6.pdf
│	│	│	├Tahy Graphene Transistors p29.pdf
│	│	│	├Tan Optimization of Chemical Vapor Deposition Grown Graphene p54.pdf
│	│	│	├Thiele Carbon Nanotubes and Graphene for Electronics Applications 2010-2020 Technologies, Players & Opportunities p228.pdf
│	│	│	├van den Berg ConceptGraphene New Electronics Concept Wafer-Scale Epitaxial Graphene p10.pdf
│	│	│	├Vargas-Bernal Carbon Nanotube- and Graphene Based Devices, Circuits and Sensors for VLSI Design p28.pdf
│	│	│	├Vaziri Fabrication and Characterization of Graphene Field Effect Transistors p48.pdf
│	│	│	├Wall Uncovering the Secrets Governing the Chemical Vapor Deposition of Graphene with Rapid Raman Imaging p4.pdf
│	│	│	├Wu Graphene Electronics Materials, Devices, and Circuits p18.pdf
│	│	│	├Wu Quantum Behavior of Graphene Transistors near the Scaling Limit p12.pdf
│	│	│	├Xia Graphene Field-Effect Transistors with High OnOff Current Ratio and Large Transport Band Gap at Room Temperature p4.pdf
│	│	│	├Yan Graphene-based flexible and stretchable thin film transistors p13.pdf
│	│	│	├Yang Graphene Barristor, a Triode Device with a Gate-Controlled Schottky Barrier p5.pdf
│	│	│	├Yang Memristive devices for computing p12.pdf
│	│	│	├Yeric Graphene for Future VLSI p59.pdf
│	│	│	└Zhao SymFET A Proposed Symmetric Graphene Tunneling Field Effect Transistor p7.pdf
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│	│	│	├IZYUMSKAYA Two-dimensional MoS2 as a new material for electronic devices p19.pdf
│	│	│	├Kim High-mobility and low-power thin-film transistors based on multilayer MoS2 crystals p7.pdf
│	│	│	├Kis Single-layer MoS2 Devices Electronics and Mechanics p31.pdf
│	│	│	├Leong Tuning the Threshold Voltage of MoS2 Field-Effect Transistors via Surface Treatment p35.pdf
│	│	│	├Ranade Work Function Engineering of Molybdenum Gate Electrodes.pdf
│	│	│	├SemiconductorToday_JuneJuly2014-Chloride-based chemical doping yields low-contact resistance molybdenum disulfide field-effect transistors.pdf
│	│	│	├Sundaram Electroluminescence in Single Layer MoS2 p6.pdf
│	│	│	├Ye Recent Advancement on the Optical Properties of Two-Dimensional Molybdenum Disulfide (MoS2) Thin Films p20.pdf
│	│	│	└Zhan Large Area Vapor Phase Growth and Characterization of MoS2 Atomic Layers on SiO2 Substrate p24.pdf
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│	│	│	├Alpha Low Noise Medium Power GaAs MESFET Chips p3.pdf
│	│	│	├AMP 9 - 10 GHz GaAs MMIC Core Chip p18.pdf
│	│	│	├Bock New Manufacturing Concepts for Ultra-Thin Silicon and Gallium Arsenide Substrates p4.pdf
│	│	│	├Brown AlGaNGaN HFETs fabricated on 100-mm GaN on silicon (111) substrates p5.pdf
│	│	│	├Crowe Integrated GaAs Diode Technology for Millimeter and Submillimeter-wave Components and Systems p6.pdf
│	│	│	├Harmon Rad-Hard Photomultiplier Chips.ppt
│	│	│	├Northrop GaAs IC Die Handling Assembly and Testing Techniques p10.pdf
│	│	│	├Siddiqui GaAs Components for 60 GHz Wireless Communication Applications p4.pdf
│	│	│	├Skyworks GaAs Schottky Flip Chip Diodes p4.pdf
│	│	│	├Upton TA 5.5 A 160,000 Transistor GaAs Microprocessor p3.pdf
│	│	│	└Wohlgemuth Digital SiGe-Chips for Data Transmission up to 85 Gbits p4.PDF
│	│	├<germanium>
│	│	│	├0000germanium.docx
│	│	│	├Bardin Silicon-Germanium Heterojunction Bipolar Transistors For Extremely Low-Noise Applications p234.pdf
│	│	│	├Brocato Silicon Germanium Design p18.pdf
│	│	│	├Guo Silicon germanium programmable circuits for gigahertz applications p7.pdf
│	│	│	├Masini A FULLY INTEGRATED SILICON-GERMANIUM X-BAND VCO p4.pdf
│	│	│	├SUN POWER METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH STRAINED SILICON AND SILICON GERMANIUM CHANNEL p104.pdf
│	│	│	└Wolf Silicon Germanium (SiGe) Bipolor Dicke Radiometer Front End Receiver Chip p170.pdf
│	│	└<indium>
│	│	  	├0000indium.docx
│	│	  	└Wohlgemuth Digital SiGe-Chips for Data Transmission up to 85 Gbits p4.PDF
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│	│	│	├0000nano_deep_submicron.docx
│	│	│	├Andrés Developing Fault Models for Nanowire Logic Circuits p25.pdf
│	│	│	├Aquilino Development of deep submicron CMOS process for fabrication of high performance 0.25 nm transistors p159.pdf
│	│	│	├Balasubramanian Nanoscale thin-body MOSFET design and applications p185.pdf
│	│	│	├Bazarjani Mixed Analog-Digital Design Considerations in Deep Submicron CMOS Technologies p183.pdf
│	│	│	├Chaudhry Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability A Review p52.pdf
│	│	│	├Chen CMOS vs. NANO p88.pdf
│	│	│	├CUI MODELING AND SIMULATION OF LONG TERM DEGRADATION AND LIFETIME OF DEEP-SUBMICRON MOS DEVICE AND CIRCUIT p157.pdf
│	│	│	├Datta ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS p127.pdf
│	│	│	├Deleonibus ELECTRONIC DEVICE ARCHITECTURES FOR THE NANO-CMOS ERA p440.pdf
│	│	│	├Deleonibus Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices p88.pdf
│	│	│	├Elgebaly Energy E±cient Design for Deep Sub-micron CMOS VLSIs p190.pdf
│	│	│	├Forzan Interconnect impact on circuit performances in Deep Sub-Micron technologies p48.pdf
│	│	│	├Gedamu Nanowires from Microchip Integrated Synthesis to Application Examples p165.pdf
│	│	│	├Ghani Challenges and Innovations in Nano‐CMOS Transistor Scaling p50.pdf
│	│	│	├Ghani Innovative Device Structures and New Materials for Scaling Nano-CMOS Logic Transistors to the Limit p51.pdf
│	│	│	├Haselman The Future of Integrated Circuits A Survey of Nano-electronics p57.pdf
│	│	│	├Hungar Integration of Ultrathin Silicon Chips p199.pdf
│	│	│	├KARAMI Deep-submicron CMOS Single Photon Detectors and Quantum Effects p121.pdf
│	│	│	├Keller Nano Field Effect Transistors as basic building blocks for sensing p208.pdf
│	│	│	├Lin Challenges for SoC Design in Very Deep Submicron Technologies p52.pdf
│	│	│	├Liu Multi-Voltage Nanoscale CMOS Circuit Techniques p247.pdf
│	│	│	├Lundstrom Understanding the Nanoscale MOSFET p64.pdf
│	│	│	├Mangan MILLIMETRE-WAVE DEVICE CHARACTERIZATION FOR NANO-CMOS IC DESIGN p109.pdf
│	│	│	├McNeill Deep Submicron CMOS and the New Era of Creativity in Analog Design p81.pdf
│	│	│	├Pamunuwa Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip p178.pdf
│	│	│	├Panigrahy STUDIES OF SHORT CHANNEL EFFECTS AND PERFORMANCE ENHANCEMENT OF NANO-MOSFET BASED ON MULTI-OBJECTIVE GENETIC ALGORITHM p103.pdf
│	│	│	├Piednoir Challenges of Deep Submicron Design p133.pdf
│	│	│	├Rabaey Ultra deep submicron p38.pdf
│	│	│	├RAKESH Overcoming the Challenges in Very Deep Submicron for area reduction, power reduction and faster design closure p62.pdf
│	│	│	├Routenberg Fabrication and Characterization of Silicon Nanowire Field Effect Sensors p165.pdf
│	│	│	├Sicard Deep-submicron CMOS circuit design Simulator in hands p737.pdf
│	│	│	├Staszewski Digital submicron CMOS frequency synthesis p319.pdf
│	│	│	├Torres Recommendations on Beyond CMOS Nanoelectronics Research p59.pdf
│	│	│	├Veendrick Deep-submicron CMOS ICs p286.pdf
│	│	│	├Wong Nano CMOS Circuit and Physical Design encrypted p408.pdf
│	│	│	├Wulff Effocient ADCs for nano-scale CMOS Technology p196.pdf
│	│	│	└Zhang Routing Issues in Nanometer-scale Integrated Circuits A PhD Dissertation okokok p160.pdf
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│	│	│	├0000photon.docx
│	│	│	├Antao QUANTUM OPTICAL COMPUTING p19.pdf
│	│	│	├Hendry Architectures and Design Automation for Photonic Networks On Chip p161.pdf
│	│	│	├Koch CHAPTER 6 INTEGRATED OPTICS p42.pdf
│	│	│	├Korthorst Photonic IC design p30.pdf
│	│	│	├Lokar Optical Computers p14.pdf
│	│	│	├McLeod Silicon integrated optics p16.pdf
│	│	│	├Murdocca Advances in Digital Optical Computing p19.pdf
│	│	│	├<plasmonics>
│	│	│	├Pleumeekers Manufacturing Progress for InP-based 500 Gbs Photonic Integrated Circuits p4.pdf
│	│	│	├Raphael Optical Computers p29.pdf
│	│	│	├Schriever Strained Silicon Photonics p20.pdf
│	│	│	└Woods Parallel and sequential optical computing p17.pdf
│	│	├<00resonant_tunnellingOK>
│	│	│	├0000resonanttunneling.docx
│	│	│	├Akkala NEGF SIMULATION OF ELECTRON TRANSPORT IN RESONANT TUNNELING AND RESONANT INTERBAND TUNNELING DIODES p98.pdf
│	│	│	├AL-Farra Nonlinear Resonant Tunneling Diode (RTD) Circuits for Microwave AD Conversion p103.pdf
│	│	│	├Cidronali Resonant Tunneling Devices physics, technology and applications p53.pdf
│	│	│	├Figueiredo Optoelectronic Properties of Resonant Tunnelling Diodes p260.pdf
│	│	│	├Jacobs Development of Resonant Tunnelling Diode Terahertz Emitter p180.pdf
│	│	│	├Laresgoiti Resonant Tunneling and Resonant Tunneling Diodes p17.pdf
│	│	│	├Lear Applications of Resonant Tunneling Diodes and Effects of a Novel Cathode Structure p162.pdf
│	│	│	├MAZUMDER Digital Circuit Applications of Resonant Tunneling Devices p23.pdf
│	│	│	├Pacha RESONANT TUNNELING DEVICE LOGIC CIRCUITS p22.pdf
│	│	│	├Raval Resonant Tunneling Device p32.pdf
│	│	│	├SUN Resonant Tunneling Diodes Models and Properties p21.pdf
│	│	│	├Waho Resonant-Tunneling Diode and its Application to Multi-GHz Analog-to-Digital Converters p6.pdf
│	│	│	└Wikipedia Resonant-tunneling diode.pdf
│	│	├<00spin>
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│	│	│	├000Abdullah Spin Current Amplification by a Geometrical Ratchet Effect p155.pdf
│	│	│	├000AMAND Spin dynamics and exchange interaction in semiconductor quantum dots p52.pdf
│	│	│	├000Andrade Spin-FET based on InGaAsInP heterostructure p51.pdf
│	│	│	├000Awschalom SPIN ELECTRONICS p168.pdf
│	│	│	├000Balestro Molecular spintronics p55.pdf
│	│	│	├000Baláz Current-induced dynamics in magnetic nanopillars p164.pdf
│	│	│	├000Bercioux Spin-dependent transport in nanostructures p119.pdf
│	│	│	├000Birk Spin Electronics in Metallic Nanoparticles p109.pdf
│	│	│	├000Bonhomme CIRCUIT MODELING OF SPINTRONIC DEVICES A SPICE IMPLEMENTATION p66.pdf
│	│	│	├000Br?uninger Tunnel barriers for spin injection into grapheme p148.pdf
│	│	│	├000Bürgler Spintronics p183.pdf
│	│	│	├000Carlegrim Development of Organic-Based Thin Film Magnets for Spintronics p67.pdf
│	│	│	├000Carva Spin-dependent transport in layered magnetic nanostructures p121.pdf
│	│	│	├000Chen ON-CHIP SPIN CONTROL IN SEMICONDUCTOR MICROAND NANO- STRUCTURES p171.pdf
│	│	│	├000CHUREEMART MODELS OF SPIN TORQUE USING SELF-CONSISTENT SOLUTIONS OF THE MAGNETISATION AND SPIN ACCUMULATION p163.pdf
│	│	│	├000Coey Chapter 14 Spin Electronics and Magnetic Recording p62.pdf
│	│	│	├000Corbetta Spin-polarized Scanning Tunneling Microscopy and Spectroscopy Study of Fe and Co Nanostructures on Cu(111) p123.pdf
│	│	│	├000Das Spintronics with quantum dots p64.pdf
│	│	│	├000Dash Nanospintronics p117.pdf
│	│	│	├000Duine Spintronics p81.pdf
│	│	│	├000Dürrenfeld Spin Torque and Spin Hall Nano-Oscillators with Single Magnetic Layers p78.pdf
│	│	│	├000Elste Quantum transport through single-molecule devices spin and vibration p126.pdf
│	│	│	├000Elzerman Semiconductor Few-Electron Quantum Dots as Spin Qubits p72.pdf
│	│	│	├000Fabian SEMICONDUCTOR SPINTRONICS p343.pdf
│	│	│	├000Fert Présent et futur de la spintronique p51.pdf
│	│	│	├000FLATTE SEMICONDUCTOR SPINTRONICS FOR QUANTUM COMPUTATION p52.pdf
│	│	│	├000Folk SPIN TRANSPORT MEASUREMENTS IN GaAs QUANTUM DOTS p76.pdf
│	│	│	├000Fragner Circuit Quantum Electrodynamics with Electrons on Helium p232.pdf
│	│	│	├000Freitas Spin Electronics from data storage to biochips Part II MRAMS, hybrid semiconductor-magnetic devices p56.pdf
│	│	│	├000Fu OPTICAL MANIPULATION OF ELECTRON SPINS BOUND TO NEUTRAL DONORS IN GAAS p127.pdf
│	│	│	├000Galperin Spintronics p74.pdf
│	│	│	├000Garello Symmetry and magnitude of spin-orbit torques in ferromagnetic heterostructures p51.pdf
│	│	│	├000Golovatski Spin torque and interactions in ferromagnetic semiconductor domain walls p124.pdf
│	│	│	├000Hachiya Spin relaxation in semiconductor nanostructures p116.pdf
│	│	│	├000Hajj Etude mathematique et numerique de modeles de transport  application a la spintronique p213.pdf
│	│	│	├000Heers Effect of spin-orbit scattering on transport properties of low-dimensional dilute alloys p211.pdf
│	│	│	├000Heers Effect of spin-orbit scattering on transport properties of low-dimensional dilute alloys p226.pdf
│	│	│	├000Hoang Phase transition and Spin transport in Complex Systems Frustrated spin systems, Molecular and Liquid Crystals p164.pdf
│	│	│	├000Huda Modeling and Design of Spin Torque Transfer Magnetoresistive Random Access Memory p120.pdf
│	│	│	├000Ingenhoven Spin dependent electronic and transport properties of unconventional conductors p122.pdf
│	│	│	├000Jansen Spin injection concept and technology p74.pdf
│	│	│	├000Jaromirska Modeling spin transfer induced oscillations in spin valve nanostructures p190.pdf
│	│	│	├000JOIBARI INTERPLAY OF CHARGE CURRENT AND SPIN IN NANOSTRUCTURES p101.pdf
│	│	│	├000Kim Electrical injection and detection of spin polarization in InSb  ferromagnet nanostructures p118.pdf
│	│	│	├000Konig Semiconductor Spintronics p81.pdf
│	│	│	├000Koo Control of Spin Precession in a Datta-Das Transistor Structure p80.pdf
│	│	│	├000Krich Electron and nuclear spins in semiconductor quantum dots p150.pdf
│	│	│	├000LeClair Fundamental aspects of spin polarized tunneling p187.pdf
│	│	│	├000Leem MAGNETIC COUPLED SPIN-TORQUE DEVICE SPIN-BASED NON-VOLATILE LOGIC DEVICE AND APPLICATIONS p180.pdf
│	│	│	├000Levy An idiosyncratic survey of spintronics p77.pdf
│	│	│	├000Lin Organic spintronic devices utilizing spin-injection, spin-tunneling and spin-dependent transport p109.pdf
│	│	│	├000Lin Spin polarization of ground state electron gas at low densities p139.pdf
│	│	│	├000Lo Electrical Detection of Spin-Dependent Transport in Silicon p193.pdf
│	│	│	├000Loh Mechanism and assessment of spin transfer torque based memory p70.pdf
│	│	│	├000Mane Spin-polarized charged particle beams in high-energy accelerators p269.pdf
│	│	│	├000Mann Determining the Spin Polarization of Heusler Compounds via Femtosecond Magnetization Dynamics p113.pdf
│	│	│	├000Meijer RASHBA SPIN-ORBIT INTERACTION IN MESOSCOPIC SYSTEMS p149.pdf
│	│	│	├000Moehlmann Spin transport in strained non-magnetic zinc blende semiconductor p130.pdf
│	│	│	├000Morenzoni Introduction to SR Muon Spin RotationRelaxation p55.pdf
│	│	│	├000Morten Coherent and Correlated Spin Transport in Nanoscale Superconductors p148.pdf
│	│	│	├000Münzenberg Spin-wave and spin-current dynamics in ultrafast demagnetization experiments p56.pdf
│	│	│	├000Münzenberg The magneto-Seebeck effect - THz Spintronics p55.pdf
│	│	│	├000Neumann Electronic spin transport and thermoelectric effects in graphene p145.pdf
│	│	│	├000NGUYEN TRANSPORT éLECTRONIQUE ET EFFETS DE SPIN DANS LES NANOSTRUCTURES DE GRAPHèNE p204.pdf
│	│	│	├000Nikonov Benchmarking Spintronic Logic Devices p63.pdf
│	│	│	├000NOSSA Nanospintronics With Molecular Magnets. Tunneling And Spin-Electric Coupling p219.pdf
│	│	│	├000O'Brien Charge degrees of freedom on the kagome lattice p76.pdf
│	│	│	├000Oshikawa Theory of Electron Spin Resonance p99.pdf
│	│	│	├000Palmer Relaxation and Dynamic Processes p118.pdf
│	│	│	├000PATHAK HALF-METALLIC CrO2 THIN FILMS FOR SPINTRONIC APPLICATIONS p112.pdf
│	│	│	├000Podnieks Theory of Single Spin Detection Using an ESR-STM Technique p174.pdf
│	│	│	├000POLI Spin transport in normal and superconducting nanowires p88.pdf
│	│	│	├000Popa Insitu studies of spin electronics properties of magnetic nanocontacts p191.pdf
│	│	│	├000Rieger Electron spin resonance p100.pdf
│	│	│	├000Rohra Exact-Exchange Kohn-Sham Spin-Current Density-Functional Theory p165.pdf
│	│	│	├000Ryan Polarised Neutron Scattering p63.pdf
│	│	│	├000Saari Electronic structure and spin polarization in Silicene nanostructures p69.pdf
│	│	│	├000Sahoo An Experimental Investigation of Spin Polarized Transport in Carbon Nanotubes p124.pdf
│	│	│	├000SAITOH Spin current coupled with charge and heat currents p88.pdf
│	│	│	├000Sanvito Ab-initio methods for spin-transport at the nanoscale p117.pdf
│	│	│	├000Sanvito Giant Magnetoresistance and Quantum Transport in Magnetic Hybrid Nanostructures p192.pdf
│	│	│	├000Sapkota Spin Dependent Transport Properties of Metallic and Semiconducting Nanostructures p139.pdf
│	│	│	├000Sato Spintronics for next generation innovative devices p79.pdf
│	│	│	├000Scharpf The spin of the neutron as a measuring probe p246.pdf
│	│	│	├000Schindler Quantum spin transport in semiconductor nanostructures p187.pdf
│	│	│	├000Sentef Linear-Response Theory of Spin Transport p90.pdf
│	│	│	├000Shiraishi Molecular Spintronics p66.pdf
│	│	│	├000Shiraishi Molecular Spintronics using Electron Molecules p63.pdf
│	│	│	├000Shylau Electron transport, interaction and spin in graphene and graphene nanoribbons p80.pdf
│	│	│	├000Sinno Polyelectrolyte-Gated Organic Field Effect Transistors – Printing and Electrical Stability p74.pdf
│	│	│	├000Skinner Electrical control of spin dynamics in spin-orbit coupled ferromagnets p139.pdf
│	│	│	├000Spielberg New Building Blocks for Molecular Spintronics p223.pdf
│	│	│	├000Studer Spin manipulation in two-dimensional electron and hole gases p115.pdf
│	│	│	├000Swaving Spin Transport and Dynamics in Antiferromagnetic Metals and Magnetic Insulators p108.pdf
│	│	│	├000Tatara Introduction to microscopic theory of spin transport p89.pdf
│	│	│	├000Toit SPIN CURRENTTHE CONTRIBUTION OF SPIN TO THE PROBABILITY CURRENT FOR NONRELATIVISTIC PARTICLES p96 .pdf
│	│	│	├000Vila From Basic Magnetic Concepts To Spin Currents p60.pdf
│	│	│	├000Wagemans Plastic Spintronics p131.pdf
│	│	│	├000Walser Spin-orbit interaction and the persistent spin helix in two-dimensional electron gases p153.pdf
│	│	│	├000Weymann Spin-Dependent Transport in Magnetic Nanostructures with Coulomb Blockade p145.pdf
│	│	│	├000Winkler Spin–Orbit Coupling Effects in Two-Dimensional Electron and Hole Systems p236.pdf
│	│	│	├000Woltersdorf SPIN-PUMPING AND TWO-MAGNON SCATTERING IN MAGNETIC MULTILAYERS p200.pdf
│	│	│	├000Wu Nano Spintronics for Data Storage p50.pdf
│	│	│	├000Yan Nonlinear Magnetic Dynamics and The Switching Phase Diagrams in Spintronic Devices p92.pdf
│	│	│	├000Yang Electronic Spin Transport in Bilayer and Single Layer Graphene p140.pdf
│	│	│	├000Yu Thermal Spin Transfer Torque and Transverse Spin Relaxation in Spin Valves p123.pdf
│	│	│	├000ZHOU Spin momentum transfer effects for spintronic device applications p91.pdf
│	│	│	├000Zuelicke Spin-dependent transport due to spin-orbit coupling p57.pdf
│	│	│	├Adur Spin Pumping in Ferromagnetic Resonance and Electrical Detection Experiments p16.pdf
│	│	│	├Amipara Nano Technology – Spintronics p5.pdf
│	│	│	├Anane From spintronics to magnons-spintronics p41.pdf
│	│	│	├Anjum Spintronics Fundamentals and Applications p9.pdf
│	│	│	├Atsarkin Nuclear magnetic relaxation and spin diffusion in the local fields of paramagnetic centers p7.pdf
│	│	│	├Awschalom Spin Dynamics in Semiconductors p41.pdf
│	│	│	├Awschalom The Diamond Age of SPIN ELECTRONICS p8.pdf
│	│	│	├BAKSALARY QUASICLASSICAL THEORY OF SPIN-VALVE MAGNETORESISTANCE ROLE OF SPIN-FLIP SCATTERING p4.pdf
│	│	│	├Bandyopadhyay Supercomputing with spin-polarized single electrons in a quantum coupled architecture p21.pdf
│	│	│	├BARLETTI QUANTUM DRIFT-DIFFUSION MODELING OF SPIN TRANSPORT IN NANOSTRUCTURES p22.pdf
│	│	│	├Bercioux Spin-orbit interactions in semiconductor nanostructures p10.pdf
│	│	│	├BERGENTI Organic spintronics p15.pdf
│	│	│	├Bishnoi Architectural Aspects in Design and Analysis of SOT-based Memories p30.pdf
│	│	│	├Bobo Recent advances in nanomagnetism and spin electronics p26.pdf
│	│	│	├Bournel Theoretical and experimental considerations on the spin field effect transistor p5.pdf
│	│	│	├Brataas Spin–orbit torques in action p3.pdf
│	│	│	├Bruno Spin-dependent transport in layered magnetic metals p30.pdf
│	│	│	├Bruno Spin-electronics a new challenge in science and technology p27.pdf
│	│	│	├Buchenberg SPINTRONICS p39.pdf
│	│	│	├Buhrman CHAPTER 4 SPIN INJECTION, SPIN TRANSPORT AND SPIN TRANSFER p10.pdf
│	│	│	├Camarero Molecular vs. inorganic spintronics the role of molecular materials and single molecules p7.pdf
│	│	│	├Chen All-electric Spin Transistors p34.pdf
│	│	│	├Chen Phonon-assisted spin current in a hybrid system with a single molecular quantum dot system applied with ac magnetic fields p8.pdf
│	│	│	├Chetan spin-electronics p14.doc
│	│	│	├Chuang All-electric all-semiconductor spin field effect transistors p18.pdf
│	│	│	├Chuang All-electric and all-semiconductor spin field effect transistors p17.pdf
│	│	│	├Cimpoesu Dynamic and temperature effects in spin-transfer switching p8.pdf
│	│	│	├Coronado MOLECULAR SPINTRONICS p28.pdf
│	│	│	├Cottet Nanospintronics with carbon nanotubes p18.pdf
│	│	│	├Crooker Electrical Spin Injection, Accumulation, and Detection in Lateral FerromagnetSemiconductor Devices p35.pdf
│	│	│	├Crouzy How spin-flip scattering influences the minigap in a S-N junction p47.pdf
│	│	│	├Culcer Spin procession and relaxation in semiconductors p24.pdf
│	│	│	├DAHL THE SPINNING ELECTRON p36.pdf
│	│	│	├Dankert Spin transport and precession in grapheme measured by nonlocal and three-terminal methods p5.pdf
│	│	│	├Dargys WHY THE SPIN-FET DOES NOTWORK p10.pdf
│	│	│	├Dash Electrical creation of spin polarization in silicon at room temperature p4.pdf
│	│	│	├Datta From Spin Physics to Spin Electronics-I p10.pdf
│	│	│	├Datta Non-volatile Spin Switch for Boolean and Non-Boolean Logic p10 .pdf
│	│	│	├Demidov Spin-current nano-oscillator based on nonlocal spin injection p5.pdf
│	│	│	├Demidov Spin-Hall nano-oscillators p24.pdf
│	│	│	├Demokritov Magnetic dynamics driven by spin current p30.pdf
│	│	│	├Dieny Spin-transfer effect and its use in spintronic components p21.pdf
│	│	│	├Duan Nanowire spin torque oscillator driven by spin orbit torques p7.pdf
│	│	│	├Dugaev Spin Currents in Magnetic Nanostructures p8.pdf
│	│	│	├Ebert New effects in spintronics derived from the symmetry of response functions p28.pdf
│	│	│	├Egues Novel spin FETs p2.pdf
│	│	│	├Emberly Molecular spintronics spin-dependent electron transport in molecular wires p14.pdf
│	│	│	├EURAMET Spintronic and spin-caloritronics in magnetic nanosystems p3.pdf
│	│	│	├Fabian classical and quantum spin devices theoretical perspectives p30.pdf
│	│	│	├Fabian Fundamental concepts of spintronics p34.pdf
│	│	│	├Falk Engineered defects in wide band-gap semiconductors for single-spin sensing and computation p39.pdf
│	│	│	├Fert Nobel Lecture Origin, development, and future of spintronics p14.pdf
│	│	│	├Fert ORIGIN, DEVELOPMENT AND FUTURE OF SPINTRONICS p11.pdf
│	│	│	├Fert THE ORIGIN, DEVELOPMENT AND FUTURE OF SPINTRONICS p22.pdf
│	│	│	├Franklin FeFET Spintronics p17.pdf
│	│	│	├Freitas Magnetoresistive sensors and applications I p45.pdf
│	│	│	├Galperin Giant Magnetoresistance and Spintronics p47.pdf
│	│	│	├Gelfond Symmetries of 4d higher-spin current interactions p16.pdf
│	│	│	├Gerretsen Spin Transfer Torque in Ferromagnetic Materials p8.pdf
│	│	│	├Getzlaff Spin-Polarized Scanning Tunneling Microscopy p48.pdf
│	│	│	├Giulini Electron Spin or “Classically Non-Describable Two-Valuedness” p28.pdf
│	│	│	├Gould Spintronics A half-time assessment p38.pdf
│	│	│	├Grillo Quantum simulation of a spin polarization device in an electron microscope p25.pdf
│	│	│	├Grundler Spintronics p5.pdf
│	│	│	├Hahn Conduction of spin currents through insulating oxides p10.pdf
│	│	│	├Hamrle Three-dimensional distribution of the spin-polarized current inside nanostructures p7.pdf
│	│	│	├Han Graphene spintronics p14.pdf
│	│	│	├Han Spin Transport and Relaxation in Graphene p41.pdf
│	│	│	├Haron Emerging Non-CMOS Nanoelectronic Devices - What Are They p6.pdf
│	│	│	├Hayashi Spin orbit torques and current induced domain wall motion in magnetic heterostructures p39.pdf
│	│	│	├Heide Spin Orbit Driven Physics at Surfaces p39.pdf
│	│	│	├Heidecker MRAM Technology Status p31.pdf
│	│	│	├Heiman Nanostructures for Spintronics p33.pdf
│	│	│	├Heinonen Spintronics in applications Hard drives, MRAM, and spin torque oscillators p36.pdf
│	│	│	├Hien SIMULATION OF CURRENT-VOLTAGE CHARACTERISTICS OF SPIN FIELD EFFECT TRANSISTOR USING NEMO-VN2 p13.pdf
│	│	│	├Idzuchi Spin transportinnon-magneticnano-structuresinducedbynon-local spin injection p25.pdf
│	│	│	├Ikeda Magnetic Tunnel Junctions for Spintronic Memories and Beyond p12.pdf
│	│	│	├Ilyasov Materials for Spintronics Magnetic and Transport Properties of Ultrathin (Monolayer Graphene)MnO(001) and MnO(001) Films p16.pdf
│	│	│	├Irvin Gigahertz Optical Spin Transceiver p8.pdf
│	│	│	├Isasa Temperature dependence of spin diffusion length and spin Hall angle in Au and Pt p13.pdf
│	│	│	├Jacquod Spin Currents in Mesoscopic Systems p33.pdf
│	│	│	├Jacquod Spin transport in mesoscopics p27.pdf
│	│	│	├Jalil Spintronics in 2DEG Systems p12.pdf
│	│	│	├Kalyani Spintronics- A Vision for Future in Electronics and Computers p7.pdf
│	│	│	├Kang An Overview of Spin-based Integrated Circuits p27.pdf
│	│	│	├KANTSER Materials and structures for semiconductor spintronics p14.pdf
│	│	│	├Kartha SPINTRONICS AND SPINTRONIC DEVICES p30.pdf
│	│	│	├Katsumoto Spin Transport p12.pdf
│	│	│	├KENT Spin-Transport and Transfer in Magnetic Nanostructures p16.pdf
│	│	│	├Kervalishvili Nanostructures, magnetic semiconductors and spintronics p6.pdf
│	│	│	├Khodas Spintronics without Magnets“spin-optics” p41.pdf
│	│	│	├Kim Gate-Control of Spin-Orbit Coupling in InAs HEMT Structures for a Spin Field-Effect Transistor p23.pdf
│	│	│	├Kim Spin-Based Computing Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor p25.pdf
│	│	│	├Konig Spin-Dependent Transport in Nanostructures p30.pdf
│	│	│	├KRISHNAN Nanomagnetism and spin electronics materials, microstructure and novel properties p23.pdf
│	│	│	├Kushwaha Spintronics Combination of Nanotechnology Superconductivity p6.pdf
│	│	│	├Lee Spintronics Spin transfer torque in magnetic nanostructures and spin pumping effect p46.pdf
│	│	│	├Lin Improvement of Spin Transfer Torque in Asymmetric Graphene Devices p8.pdf
│	│	│	├Lindelof Electron Spin in Single Wall Carbon Nanotubes p19.pdf
│	│	│	├Maekawa Concepts in Spin Electronics p4.pdf
│	│	│	├Maekawa Concepts in Spin Electronics p6.pdf
│	│	│	├Maekawa Spin Current and Spin Seebeck Effect p29.pdf
│	│	│	├Maekawa Spin current vs charge current in magnetic nanostructures p31.pdf
│	│	│	├Maekawa Spin Current.docx
│	│	│	├Mangin Spin Transfer Torque Effects in Devices with Perpendicular Anisotropy p6.pdf
│	│	│	├Manipatruni Circuit Theory for SPICE of Spintronic Integrated Circuits p14.pdf
│	│	│	├Mavropoulos Spintronics Transport and Materials p24.pdf
│	│	│	├Molnár CHAPTER 2 MATERIALS FOR SEMICONDUCTOR SPIN ELECTRONICS p8.pdf
│	│	│	├Monaico Spintronics p13.pdf
│	│	│	├Moodera Spin polarized tunneling in ferromagnetic junctions p26.pdf
│	│	│	├Moreno New magnetic materials for Spintronics p25.pdf
│	│	│	├Muller Spin transport p25.pdf
│	│	│	├Myers Spin Torque and Magnetic Tunnel Junctions p38.pdf
│	│	│	├Naber Organic spintronics p24.pdf
│	│	│	├Newman Spintronics and Nanomagnetics p20.pdf
│	│	│	├Nikolic Mesoscopics in Spintronics Quantum Interference Effects in Spin-Polarized Electron Transport p12.pdf
│	│	│	├Nitta Semiconductor Spintronics p6.pdf
│	│	│	├Niu Proper definition off spin current p16.pdf
│	│	│	├OHNO Semiconductor Spin Electronics p10.pdf
│	│	│	├Orellana Spin-polarized electrons in bilayer graphene ribbons p5.pdf
│	│	│	├Osterwalder Spin-Polarized Photoemission p26.pdf
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│	│	│	├Ralph Spin transfer torques p27.pdf
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│	│	│	├Wang From Nanoelectronics to Nano-Spintronics p8.pdf
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│	│	│	├Green From reversible to irreversible computations p9.pdf
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│	│	│	├Buxboim Current characteristics of the single-electron transistor at the degeneracy point p17.pdf
│	│	│	├Chawla Single Electron transistor- The future of transistors p6.pdf
│	│	│	├DUBEJSKY FABRICATION AND DC CHARACTERIZATION OF SINGLE ELECTRON TRANSISTORS AT LOW TEMPERATURE p148.pdf
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│	│	│	├Ionescu Hybrid CMOS Single-Electron-Transistor Device and Circuit Design p46.pdf
│	│	│	├Kastner The single electron transistor and artificial atoms p10.pdf
│	│	│	├Kim Single-Electron Logic Cells and SETFET Hybrid Integrated Circuits p7.pdf
│	│	│	├Koerting Transport properties of a superconducting single-electron transistor coupled to a nanomechanical oscillator p19.pdf
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│	│	│	├Kumar Single Electron Transistor Applications and problems p6.pdf
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│	│	│	├Park Electron Transport in Single Molecule Transistors p165.pdf
│	│	│	├Perry Digital to Analog Converter Design using Single Electron Transistors p73.pdf
│	│	│	├Pott Gate-All-Around Silicon Nanowires for Hybrid Single Electron TransistorCMOS Applications p154.pdf
│	│	│	├QuantumWise Benzene Single-Electron Transistor Tutorial p32.pdf
│	│	│	├Schon Single-Electron Tunneling p65.pdf
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│	│	  	├Langford Circuit QED — Lecture Notes p85.pdf
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│	│	  	├Martinis Design of a Superconducting Quantum Computer p44.pdf
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│	│	  	├Hamid Characterization and Fabrication of 90nm Strained Silicon PMOS using TCAD p7.pdf
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│	│	  	└Xu Effectiveness of Strain Solutions for Next-Generation MOSFETs p103.pdf
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│	│	│	│	└Wang Bio-MEMS Technologies and Applications p463.pdf
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│	│	│	│	└Wang Rapid engineering of versatile molecular logic gates using heterologous genetic transcriptional modules p4.pdf
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│	│	│	│	│	├Csuhaj-Varju Proceedings 13th International Conference on Membrane Computing CMC13 p464.pdf
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│	│	│	│	│	├Nguyen AN IMPLEMENTATION OF MEMBRANE COMPUTING USING RECONFIGURABLE HARDWARE p19.pdf
│	│	│	│	│	├Noack PRINCIPLES OF BIOLOGICAL INFORMATION PROCESSING MEMBRANE COMPUTING p33.pdf
│	│	│	│	│	├Paun A guide to membrane computing p28.pdf
│	│	│	│	│	├Paun Introduction to Membrane Computing p43.pdf
│	│	│	│	│	├Paun Membrane computing Brief introduction, recent results and applications p12.pdf
│	│	│	│	│	├Paun Membrane Computing Power, Efficiency, Applications (A Quick Introduction) p30.pdf
│	│	│	│	│	├Paun Membrane Computing Power, Efficiency, Applications (A Quick Introduction) p52.pdf
│	│	│	│	│	├Paun Membrane Computing Power, Efficiency, Applications (Introduction and Some Recent Results) p79.pdf
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│	│	│	│	│	├Yahya Membrane Computing for 2D Image Segmentation p16.pdf
│	│	│	│	│	├Yan Introduction to Membrane Computing p57.pdf
│	│	│	│	│	└Zandron A Model for Molecular Computing Membrane Systems p43.pdf
│	│	│	│	└TerAvest Bacteria-based biocomputing with Cellular Computing Circuits to sense decide signal and act p10.pdf
│	│	│	├<DNA>
│	│	│	│	├000dna.docx
│	│	│	│	├Adleman Computing with DNA p8.pdf
│	│	│	│	├AMOS DNA Computing p27.pdf
│	│	│	│	├Amos Molecular and Cellular Computing p44.pdf
│	│	│	│	├CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319.pdf
│	│	│	│	├Cavaliere Biomolecular Implementation of Computing Devices with Unbounded Memory p15.pdf
│	│	│	│	├Formanowicz DNA computing p10.pdf
│	│	│	│	├Franco Biomolecular Computing – Combinatorial Algorithms and Laboratory Experiments p189.pdf
│	│	│	│	├Fuentes Inference models in DNA COMPUTING p164.pdf
│	│	│	│	├Gariaev The DNA-wave Biocomputer p22.pdf
│	│	│	│	├Hagiya From Molecular Computing to Molecular Programming p14.pdf
│	│	│	│	├Herrmann Natural Computing Lecture 16 Molecular Computing p36.pdf
│	│	│	│	├Hoogeboom Computer In A Test Tube p57.pdf
│	│	│	│	├Hu BioComputer -The New Era p24.pdf
│	│	│	│	├Kahan Towards molecular computers that operate in a biological environment p8.pdf
│	│	│	│	├Kari DNA computing the arrival of biological mathematics p11.pdf
│	│	│	│	├Kari From Micro-soft to Bio-soft Computing with DNA p28.pdf
│	│	│	│	├Krithivasan DNA Computing p31.pdf
│	│	│	│	├Lemieux Overview of DNA chip technologyXXX p13.pdf
│	│	│	│	├MURARU DNA COMPUTING – MODELLING AND SIMULATING A MOLECULAR TURING MACHINE p14.pdf
│	│	│	│	├Ogura Photonic DNA Computing Concept and Implementing Methods p20.pdf
│	│	│	│	├O’Keefe NSC DNA Computing p32.pdf
│	│	│	│	├QIU ADVANCE THE DNA COMPUTING p75.pdf
│	│	│	│	├Rambidi Biomolecular computer roots and promises p15.pdf
│	│	│	│	├Saxena Use of DNA for Computation, Storage and Cryptography of Information p5.pdf
│	│	│	│	├TADESERA DNA Computing p22.pdf
│	│	│	│	├Véro Molecular Computation p51.pdf
│	│	│	│	├Watada DNA Computing and its Application p23.pdf
│	│	│	│	├WINFREE DNA Computing by Self-Assembly p10.pdf
│	│	│	│	├WINFREE DNA Computing by Self-Assembly p8.pdf
│	│	│	│	└wishart Molecular Computing p56.pdf
│	│	│	├<DNAzyme computing>
│	│	│	│	└Melnikov Analog Noise Reduction in Enzymatic Logic Gates p25.pdf
│	│	│	├<enzyme>
│	│	│	│	├enzyme_based_logical_circuits.docx
│	│	│	│	├Katz ENZYME-BASED LOGIC SYSTEMS FOR INFORMATION PROCESSING p56.pdf
│	│	│	│	├Katz ENZYME-BASED LOGIC SYSTEMS FOR INFORMATION PROCESSING.pdf
│	│	│	│	├Melnikov Analog Noise Reduction in Enzymatic Logic Gates p25.pdf
│	│	│	│	├Pedrosa Enzymatic Logic Gates with Noise-Reducing Sigmoid Response p11.pdf
│	│	│	│	├Pedrosa ENZYMATIC LOGIC GATES WITH NOISE-REDUCING SIGMOID RESPONSE p2.pdf
│	│	│	│	└Seelig Enzyme-Free Nucleic Acid Logic Circuits p4.pdf
│	│	│	├<Proteins>
│	│	│	└<RNA Computing>
│	│	├<chemical>
│	│	│	├000chemicalcomputing.docx
│	│	│	├Adamatzky Designing a chemical computer p3.pdf
│	│	│	├Adamatzky On some limitations of reaction-diffusion chemical computers in relation to Voronoi diagram and its inversion p11.pdf
│	│	│	├Adamatzky Programming Reaction-Diffusion Processors p14 (2).pdf
│	│	│	├Asai Towards reaction–diffusion computing devices based on minority-carrier transport in semiconductors p14.pdf
│	│	│	├Giavitto Autonomic computing,chemical computing &induction principles on spatial computing media p19.pdf
│	│	│	├Hartmann Stochastic Simulation of Reaction-Diffusion Systems p57.pdf
│	│	│	├Molnár SIMULATION OF REACTION-DIFFUSION PROCESSES IN THREE DIMENSIONS USING CUDA p30.pdf
│	│	│	├OBROVAC  Chemical Computing for Distributed Systems Algorithms and Implementation p201.pdf
│	│	│	└Yamamoto Considerations on the Evolution of Programs Based on Chemical Computing p56.pdf
│	│	├<liquid>
│	│	│	└liquid.docx
│	│	├<natural>
│	│	│	├000nature.docx
│	│	│	├Corne Selected Applications of Natural Computing p80.pdf
│	│	│	├de Castro Fundamentals of natural computing an overview p36.pdf
│	│	│	├Gupta-REMINISCENT-STUDY-OF-NATURE-INSPIRED-COMPUTATION-p9.pdf
│	│	│	├Kundra ASSORTMENT OF NATURE INSPIRED COMPUTING p8.pdf
│	│	│	├Uyar Nature-Inspired Computing p26.pdf
│	│	│	├Yao The Rise of Granular Computing p10.pdf
│	│	│	└Zomaya Handbook of Nature-Inspired and Innovative Computing p737.pdf
│	│	├<organic>
│	│	│	├000organiccomputing.docx
│	│	│	├Agarwal Organic Computing p5.pdf
│	│	│	└Schmeck Organic Computing –a Generic Approach to Controlled Self-organization in Adaptive Systems p61.pdf
│	│	├<others>
│	│	│	├Klimo Fuzzy Computer Architecture Based on Memristor Circuits_2012_p4.pdf
│	│	│	└Ozkul Comparative Study of Alternative Computing Technologies for Speed and Density p8.pdf
│	│	├<phase_transition_memory>
│	│	│	├000phasetransitionmemory.docx
│	│	│	├Agarwal Watching Nanoscale Phase Change Memory Work in Real Time via In Situ Electron Microscopy p34.pdf
│	│	│	├Burr Phase change memory technology p49.pdf
│	│	│	├Cabrera Material Engineering for Phase Change Memory p72.pdf
│	│	│	├Lai Phase Change MemoryA Memory Technology for All Applications p26.pdf
│	│	│	├Lee PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY p11.pdf
│	│	│	├Mittal A Survey of Power Management Techniques for Phase Change Memory p13.pdf
│	│	│	├Objective_Analysis_PCM BECOMES A REALITY.pdf
│	│	│	├Wong Phase Change Memory p28.pdf
│	│	│	├XIONG ULTRA-LOW POWER PHASE CHANGE MEMORY WITH CARBON NANOTUBE INTERCONNECTS p49.pdf
│	│	│	└ZILBERBERG Phase-Change Memory An Architectural Perspective p33.pdf
│	│	└<physarum>
│	│	  	├000Physarum.docx
│	│	  	├Adamatzky Physarum Chip Project Growing Computers From Slime Mould p5.pdf
│	│	  	├Adamatzky Slim moulds are like general purpose computer.pdf
│	│	  	├Baumgarten NETWORK COARSENING DYNAMICS IN A PLASMODIAL SLIME MOULD MODELLING AND EXPERIMENTS.pdf
│	│	  	├Bonifaci Physarum Can Compute Shortest Paths.pdf
│	│	  	├Douglas Slime molds.pdf
│	│	  	├Physarum-Chip-Project-Growing-Computers-from-Slime-Mould.pdf
│	│	  	├Schumann  Physarum Syllogistic L-Systems.pdf
│	│	  	├Schumann  PhysarumSoft - a Software Tool for Programming Physarum Machines and Simulating Physarum Games.pdf
│	│	  	├Schumann p-Adic Mathematics in Behavioural Models. The Case of Physarum Polycephalum.pptx
│	│	  	├Schumann Timed Transition System Models for Programming Physarum Machines p4.pdf
│	│	  	├Smith Whats Bugging You Slime Molds.pdf
│	│	  	├Stepney Programming Unconventional Computers Dynamics,Development, Self-Reference.pdf
│	│	  	├Tsuda The Phi-Bot A Robot Controlled by a Slime Mould.pdf
│	│	  	├Tsuda Towards Physarum engines.pdf
│	│	  	└Zou Algorithms and Models for Genome Biology.pdf
│	├<zzznot_chips>
│	│	├<amorphous>
│	│	│	├000Amorphous Cellular Computing.txt
│	│	│	├000AmorphousComputing.docx
│	│	│	├Abelson Amorphous Computing p20.pdf
│	│	│	├Abelson Amorphous Computing p35.pdf
│	│	│	├PRASAD AMORPHOUS COMPUTING AND SWARM INTELLIGENCE p35.pdf
│	│	│	└Streletz Amorphous Computing p55.ppt
│	│	├<artificialimmune>
│	│	│	└artificialimmune.docx
│	│	├<atom>
│	│	│	├AtomChip.docx
│	│	│	├CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319.pdf
│	│	│	└Wilzbach Single atom detection on an atom chip with integrated optics p184.pdf
│	│	├<crystallizationcomputers>
│	│	│	└crystallizationcomputers.docx
│	│	├<dynamical_systems_computing>
│	│	│	├000dynamicalsystemscomputing.docx
│	│	│	├Bournet On the computational power of dynamical systems and hybrid systems p43.pdf
│	│	│	└Verstraeten Reservoir Computing computation with dynamical systems p190.pdf
│	│	├<evolutionary>
│	│	│	└evolutionary.docx
│	│	├<gas>
│	│	│	└gas_discharge_analogue_path_finders.docx
│	│	├<genetic>
│	│	│	├000geneticcircuits.docx
│	│	│	├000Siuti Engineering genetic circuits that compute and remember p9.pdf
│	│	│	├Ang Designing Synthetic Gene Circuits for Homeostatic Regulation and Sensory Adaptation p100.pdf
│	│	│	├Jusiak Synthetic Gene Circuits p56.pdf
│	│	│	├Madsen Stochastic Analysis of Synthetic Genetic Circuits p148.pdf
│	│	│	└Myers Genetic Circuit Design p66.pdf
│	│	├<Lsystems>
│	│	│	└Lsystems.docx
│	│	├<maze>
│	│	│	└maze_solving_micro_fluidic_circuits.docx
│	│	├<parallel_computing>
│	│	│	├000ParallelComputing.docx
│	│	│	├Barbara Linear Algebraic Primitives for Parallel Computing on Large Graphs p301.pdf
│	│	│	├Bischof Parallel Computing Architectures Algorithms and Applications p830.pdf
│	│	│	├Grama Introduction to Parallel Computing Second Edition p612.pdf
│	│	│	└Parhami Introduction to Parallel Processing  Algorithms and Architectures p557.pdf
│	│	├<physiologicalcomputing>
│	│	│	└PHYSIOLOGICALCOMPUTING.docx
│	│	└<roll-away_computer_flexible_electronics>
│	├<_general>
│	│	├00000ngipc.docx
│	│	├00000ngipc_openproblems.docx
│	│	├00000others.docx
│	│	├Chang Emerging Interconnect Technologies for CMOS and beyond-CMOS Circuits p21.pdf
│	│	├Iwai Future of Silicon Integrated Circuit Technology p5.pdf
│	│	├Roy BEYOND CHARGE-BASED COMPUTING p80.pdf
│	│	├Shukla NANO, QUANTUM AND MOLECULAR COMPUTING p377.pdf
│	│	├The_Next_20_Years_of_Microchips.pdf
│	│	└Vgruev Digital Integrated Circuit Design and Architecture Chapter 1 Introduction p20.pdf
│	├<_quantum>
│	│	├0000quantum_graph_1.docx
│	│	├0000quantum_graph_2.docx
│	│	├0000quantum_intro.docx
│	│	├0000quantum_people.docx
│	│	├0000quantum_research.docx
│	│	├Aaronson The_Limits_of_Quantum_Computers p8.pdf
│	│	├Aharonov Quantum computation p77.pdf
│	│	├Barnum Quantum circuits for OR and AND of ORs p11.pdf
│	│	├Bera Efficient Universal Quantum Circuits p10.pdf
│	│	├Bishop Circuit Quantum Electrodynamics p168.pdf
│	│	├Black Quantum Computing and Communication p52.pdf
│	│	├Boncalo Simulation-Based Assessment of Quantum Circuit Reliability p33.pdf
│	│	├Boyden III Quantum Computation Theory and Implementation p181.pdf
│	│	├Breuckmann From quantum circuits to Hamiltonians analysis of a multi-time construction for QMA p75.pdf
│	│	├Burrell High Fidelity Readout of Trapped Ion Qubits p218.pdf
│	│	├CALUDE COMPUTING WITH CELLS AND ATOMS An Introduction to Quantum, DNA and Membrane Computing p319.pdf
│	│	├Charemza An Introduction to Quantum Computing p61.pdf
│	│	├Choi Minor-embedding in adiabatic quantum computation II Minor-universal graph design p10.pdf
│	│	├Choi?Minor-Embedding in Adiabatic Quantum Computation I The Parameter Setting Problem p17.pdf
│	│	├Choi?Minor-embedding in adiabatic quantum computation p47.pdf
│	│	├Chow Quantum Information Processing with Superconducting Qubits p322.pdf
│	│	├Cottet Implementation of a quantum bit in a superconducting circuit p259.pdf
│	│	├Dahl Programming with D-Wave Map Coloring Problem p12.pdf
│	│	├Devitt Quantum Information Engineering Concepts to Quantum Technologies p289.pdf
│	│	├Dribus Quantum Circuit Graphs p29.pdf
│	│	├Duce Quantum Logic Circuits for Solid-State Quantum Information Processing p175.pdf
│	│	├Duncan Types for Quantum Computing p175.pdf
│	│	├Duplantier Liouville quantum gravity as a mating of trees p211.pdf
│	│	├Eachempati Reconfigurable BDD based Quantum Circuits p7.pdf
│	│	├EMMS GRAPH EMBEDDING USING A QUASI-QUANTUM ANALOGUE OF THE HITTING TIMES OF CONTINUOUS TIME QUANTUM WALKS p24.pdf
│	│	├Franson Quantum Computing Using Single Photons and the Zeno Effect p34.pdf
│	│	├Geraci On the relation between quantum computation and classical statistical mechanics p138 .pdf
│	│	├Gkourasas Quantum vs DNA Computing p34.ppt
│	│	├Gruska QUANTUM COMPLEXITY THEORY p81.pdf
│	│	├Gruska QUANTUM COMPUTING p390.pdf
│	│	├Gruska QUANTUM COMPUTING p438.pdf
│	│	├Harris Adiabatic Quantum Optimization Processor Performance p59.pdf
│	│	├Hoyer Quantum Circuits with Unbounded Fan-out p12.pdf
│	│	├Jackson Properties of minimum spanning trees and fractional quantum Hall states p220.pdf
│	│	├Jeffery Frameworks for Quantum Algorithms p166.pdf
│	│	├Kauffman Quantum Topology and Quantum Computing p31.pdf
│	│	├Klymko Adiabatic quantum programming minor embedding with hard faults p21.pdf
│	│	├Lin Reversible and Quantum Circuit Synthesis p209.pdf
│	│	├Louis Distributed Hybrid Quantum Computing p185.pdf
│	│	├Lovett Application of quantum walks on graph structures to quantum computing p239.pdf
│	│	├Lucas Adiabatic Quantum Computing p47.pdf
│	│	├Maguire Toward a table-top quantum computer p17.pdf
│	│	├Martikainen Quantum information and computing Lecture 5 Quantum circuits continues p18.pdf
│	│	├MERMIN Quantum Computer Science An Introduction p237.pdf
│	│	├Miranowicz Methods of Quantum Information Processing p601.pdf
│	│	├Montanaro The Church-Turing thesis in a quantum world p50.pdf
│	│	├Nagaj Local Hamiltonian in quantum computation p176.pdf
│	│	├Neumann Towards a room temperature solid state quantum processor — The nitrogen-vacancy center in diamond p205.pdf
│	│	├Nielsen Quantum Computation and Quantum Information p698.pdf
│	│	├Nishimura Computational complexity of uniform quantum circuit families and quantum Turing machines p35.pdf
│	│	├O'Donnell Lecture 1 Introduction to the Quantum Circuit Model p17.pdf
│	│	├ORSZAG Logical gates and quantum processors with trapped ions and cavities p150.ppt
│	│	├Oskin Quantum Computing - Lecture Notes p57.pdf
│	│	├o’brien photonic quantum technologies p9.pdf
│	│	├Radecka - FPGA Emulation of Quantum Circuits p6.pdf
│	│	├Rodrigues Superconducting Charge Qubits p196.pdf
│	│	├Rotteler Introduction to Quantum Algorithms Part I Quantum Gates and Simons Algorithm p247.pdf
│	│	├Schroers Module F14ZD1 Quantum Computing p95.pdf
│	│	├Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures p6.pdf
│	│	├Shnirman Physics of Quantum Information p106.pdf
│	│	├Shukla NANO QUANTUM AND MOLECULAR COMPUTING Implications to High Level Design and Validation p377.pdf
│	│	├solid state quibts.pdf
│	│	├Strauch THEORY OF SUPERCONDUCTING PHASE QUBITS p371.pdf
│	│	├Underwood Quantum Walk Schemes for Universal Quantum Computation p267.pdf
│	│	├Vandersypen Liquid-State NMR Quantum Computing p11.pdf
│	│	├Walther Experimental One-Way Quantum Computing p36.pdf
│	│	├Wang Topological quantum error correction and quantum algorithm simulations p140 .pdf
│	│	├Wester Categorical Models for Quantum Computing p96.pdf
│	│	├Wolf Quantum Computing Lecture Notes p114.pdf
│	│	├Wong An Algorithm For Quantum Circuit Optimization p56.pdf
│	│	├Wunderlich Quantum Information Science with Trapped Ions p80 .pdf
│	│	├Yang Exact Synthesis of 3-qubit Quantum Circuits from Non-binary Quantum Gates Using Multiple-Valued Logic and Group Theory p21.pdf
│	│	└Zhang NMR Quantum Computing p56.pdf
│	└<_quantum physics mechanics theory>
│	  	├Bj?ork 20th Central European Workshop on Quantum Optics p205.pdf
│	  	├Chapter1 The basics of quantum mechanics p43.pdf
│	  	├Cresser Quantum Physics Notes p238.pdf
│	  	├DEUTSCH Quantum theory, the Church-Turing principle and the universal quantum computer p19.pdf
│	  	├DIRAC THE PRINCIPLES OF QUANTUM MECHANICS p322.pdf
│	  	├Fitzpatrick Quantum Mechanics p222.pdf
│	  	├GROENEWOLD ON THE PRINCIPLES OF ELEMENTARY QUANTUM MECHANICS p56.pdf
│	  	├Ji Yanjiang季燕江 量子力学讲义 p251.pdf
│	  	├Peres - Quantum Theory Concepts and Methods.pdf
│	  	├Schwartz Introduction to Quantum Field Theory p262.pdf
│	  	├Tong Quantum Field Theory p155.pdf
│	  	└Woit Quantum Theory, Groups and RepresentationsAn Introduction p585.pdf
├<special>
│	├<ams>
│	├<analog>
│	│	├Allen CMOS Analog Circuit Design-1 p477.pdf
│	│	└Starzyk Topological Analysis and Diagnosis of Analog Circuits p140.pdf
│	├<ASIC>
│	│	├000Bhatnagar ADVANCED ASIC CHIP SYNTHESIS p341.pdf
│	│	├ASIC Design Flow.pdf
│	│	└John Introduction to ASICs p1179.pdf
│	├<ASIPs>
│	│	└ASIPs.txt
│	├<asynchronous>
│	│	├Beerel Semi-Modularity and Self-Diagnostic Asynchronous Control Circuits p15.pdf
│	│	└SPARS? PRINCIPLES OF ASYNCHRONOUS CIRCUIT DESIGN – A Systems Perspective p354.pdf
│	├chip_special.docx
│	├<DSP>
│	│	├Blackledge DIGITAL SIGNAL PROCESSING p839.pdf
│	│	└Chen INNER-PRODUCT BASED SIGNAL PROCESSING ALGORITHMS AND VLSI IMPLEMENTATION p142.pdf
│	├<Embedded>
│	│	└Kumar On-Chip Memory Architecture Exploration of Embedded System on Chip p203.pdf
│	├<fpga>
│	│	├000fpga.docx
│	│	├Abbas PRINCE IP-core on Field Programmable Gate Arrays (FPGA) p9.pdf
│	│	├ALAOUI ISMAILI Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA p8.pdf
│	│	├Aloisio High-Resolution Time-to-Digital Converter in Field Programmable Gate Array p5.pdf
│	│	├Altera FPGA Run-Time Reconfiguration Two Approaches p6.pdf
│	│	├Altera FPGAs Provide Reconfigurable DSP Solutions p6.pdf
│	│	├Banerjee Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198.pdf
│	│	├BANERJEE FPGA Placement using Space Filling Curves Theory Meets Practice p21.pdf
│	│	├Bani-Hani High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard DES p12.pdf
│	│	├BUCUR PARTITIONING COMBINATIONAL CIRCUITS FOR K-LUT BASED FPGA MAPPING p10.pdf
│	│	├Chakrabarti Crypto Hardware Design for Embedded Applications p56.pdf
│	│	├Chen FPGA Design Automation A Survey p137.pdf
│	│	├Chen FPGA design automation a survey p151.pdf
│	│	├Chodowiec Very Compact FPGA Implementation of the AES Algorithm p15.pdf
│	│	├CHRISTIANSEN FPGA p19.pdf
│	│	├Coman Cryptographic Applications using FPGA Technology p7.pdf
│	│	├Coyne A FIELD PROGRAMMABLE GATE ARRAY CO-PROCESSOR FOR THE BASIC LOCAL ALIGNMENT SEARCH TOOL p4.pdf
│	│	├Dutt Efficient Incremental Rerouting for Fault Reconfiguration in Field Programmable Gate Arrays p4.pdf
│	│	├Gaikwad Active Noise Control Using Field Programmable Gate Arrays p7.pdf
│	│	├Ghosal A Compact FPGA Implementation of Triple-DES Encryption System with IP Core Generation and On-Chip Verification p6.pdf
│	│	├Ghosal Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA p5.pdf
│	│	├Good AES on FPGA from the Fastest to the Smallest p10.pdf
│	│	├Gore FPGA Implementation of Area Optimized AES for Image EncryptionDecryption Process p4.pdf
│	│	├Goslin A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance p11.pdf
│	│	├Gupta Successfully Designing FPGA-Based Systems p7.pdf
│	│	├Hauck Reconfigurable Computing The Theory and Practice of FPGA-Based Computation p945.pdf
│	│	├Hauck The Roles of FPGAs in Reprogrammable Systems p37.pdf
│	│	├Heinrich Comparison of FPGA-based Implementation Alternatives p8.pdf
│	│	├Hussain BASICS OF FIELD PROGRAMMABLE GATE ARRAYS p11.pdf
│	│	├Inoue Universal Test Complexity of Field-Programmable Gate Arrays p9.pdf
│	│	├Jang Energy- and Time-Efficient Matrix Multiplication on FPGAs p15.pdf
│	│	├J?rvinen Elliptic Curve Cryptography on FPGAs How Fast Can We Go with a Single Chip p10.pdf
│	│	├J?rvinen Elliptic curve cryptography on FPGAs How fast can we go with a single chip p87.pdf
│	│	├Karthik REMOTE FIELD-PROGRAMMABLE GATE ARRAY FPGA LAB p4.pdf
│	│	├Kean Secure Configuration of Field Programmable Gate Arrays p10.pdf
│	│	├Koh MODULE GRAPH MERGING AND PLACEMENT TO REDUCE RECONFIGURATION OVERHEADS IN PAGED FPGA DEVICES p6.pdf
│	│	├Kohli FPGA Implementation of Cryptographic Algorithms using Multi-Encryption Technique p9.pdf
│	│	├Kuon FPGA Architecture Survey and Challenges p119.pdf
│	│	├Lamoureux An Overview of Low-Power Techniques for Field-Programmable Gate Arrays p8.pdf
│	│	├Lamoureux Modeling and Reduction of Dynamic Power in Field-Programmable Gate Arrays p148.pdf
│	│	├Leong A Microcoded Elliptic Curve Processor Using FPGA Technology p10.pdf
│	│	├Levin FPGA-based Reconfigurable Computer Systems for digital image processing p6.pdf
│	│	├Li Power Modeling and Characteristics of Field Programmable Gate Arrays p13.pdf
│	│	├Lin A Low-Power Field-Programmable Gate Array Routing Fabric p14.pdf
│	│	├Maache A Prototype Parallel Multi-FPGA Accelerator for SPICE CMOS Model Evaluation p207.pdf
│	│	├MARVASTI AN ANALYSIS OF NOCS IN FPGAS p232.pdf
│	│	├MASUD FPGA ROUTING STRUCTURES A NOVEL SWITCH BLOCK AND DEPOPULATED INTERCONNECT MATRIX ARCHITECTURES p80.pdf
│	│	├Maxfield The Design Warriors Guide to FPGAs p560.pdf
│	│	├Mehta Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs p13.pdf
│	│	├MENON Field Programmable Gate Arrays in safety related instrumentation and control applications p68.pdf
│	│	├Meyer-Baese Digital Signal Processing with FPGAs 3rd Edition p795.pdf
│	│	├MILLER Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation p22.pdf
│	│	├Montone Floorplacement for Partial Reconfigurable FPGA-Based Systems p13.pdf
│	│	├Niu Rapid FPGA-based Delay Estimation for the HardwareSoftware Partitioning p8.pdf
│	│	├OMONDI FPGA Implementations of Neural Networks p363.pdf
│	│	├PANDYA A HANDEL-C IMPLEMENTATION OF THE BACK-PROPAGATION ALGORITHM ON FIELD PROGRAMMABLE GATE ARRAYS p218.pdf
│	│	├Panella A Design Workflow for Dynamically Reconfigurable Multi-FPGA Systems p7.pdf
│	│	├Peel Occam on Field-Programmable Gate Arrays - Optimising for Performance p13.pdf
│	│	├Pham Area and Power optimisation for AES encryption module implementation on FPGA p6.pdf
│	│	├POON A Detailed Power Model for Field Programmable Gate Arrays p28.pdf
│	│	├Rose Flexibility of Interconnection Structures for Field-Programmable Gate Arrays p6.pdf
│	│	├Rouvroy Compact and Effficient EncryptionDecryption Module for FPGA Implementation of the AES Rijndael p8.pdf
│	│	├Salem Field Programmable Gate Array-Based System-on-Chip for Real-Time Power Process Control p13.pdf
│	│	├Salim FPGA Implementation of Hiding Information using Cryptography p7.pdf
│	│	├SANGIOVANNI-VINCENTELLI Synthesis Methods for Field Programmable Gate Arrays p27.pdf
│	│	├Schelle Exploring FPGA Network on Chip Implementations Across Various Application and Network Loads p6.pdf
│	│	├SCHMIT Pipeline Reconfigurable FPGAs p18.pdf
│	│	├Shivaraj Design and FPGA implementation of TDEA using Light Weight Processor based multiprocessing system p4.pdf
│	│	├Shnidman On-Line Fault Detection for Bus-Based Field Programmable Gate Arrays p11.pdf
│	│	├Shylashree FPGA IMPLEMENTATIONS OF ADVANCED ENCRYPTION STANDARD A SURVEY p21.pdf
│	│	├Srinivas Implementation of FPGA in the design of Embedded Systems p78.pdf
│	│	├Stroop Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators p113.pdf
│	│	├strouce Field Programmable Gate Arrays p20.pdf
│	│	├Thamrin A Secure Field Programmable Gate Array Based System-on-Chip for Telemedicine Application p5.pdf
│	│	├Thanh Protecting FPGA-based Partially Reconfigurable Embedded Systems and IP Cores from Remote Update p7.pdf
│	│	├Trivedi FIELD PROGRAMMABLE GATE ARRAY BASED CONTROL SIGNAL GENERATOR FOR PULSED RADAR p10.pdf
│	│	├Varnavas The Use of Field Programmable Gate Arrays (FPGA) in Small Satellite Communication Systems p4.pdf
│	│	├VERMA VLSI-cell placement technique for Architecture of Field Programmable Gate Array (FPGA) design p9.pdf
│	│	├Viele APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL p185.pdf
│	│	├Wanderley Security FPGA Analysis p41.pdf
│	│	├Watteyne Les FPGA pour des applications à très hautes performances CETIC groupe de discussion sur la technologie FPGA p13.pdf
│	│	├Wilhelmsson Field Programmable Gate Arrays and Reconfigurable Computing in Automatic Control p102.pdf
│	│	├Wilton The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays p10.pdf
│	│	├Wright FIELD PROGRAMMABLE GATE ARRAY (FPGA) BASED SOFTWARE DEFINED RADIO (SDR) DESIGN p127.pdf
│	│	├Wu Introduction to FPGA p37.pdf
│	│	├Ye Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits p244.pdf
│	│	├Ye Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits p12.pdf
│	│	├Zain-ul-Abdin A Study of Design Efficiency with a High-Level Language for FPGAs p8.pdf
│	│	├Zaretsky DESIGN AND EVALUATION OF MATLAB FUNCTIONS ON FIELD PROGRAMMABLE GATE ARRAYS FPGAS p238.pdf
│	│	├Zhang A review of high-level synthesis for dynamically reconfigurable FPGAs p13.pdf
│	│	└Zhang Fast Marching Method Seismic Traveltimes with Reconfigurable Field Programmable Gate Arrays p9.pdf
│	├<hardware_software_codesign>
│	├<noc>
│	│	└Benini NETWORKS ON CHIPS TECHNOLOGY AND TOOLS p404.pdf
│	├<pipelining>
│	│	└Sharma A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices p59.pdf
│	├<reconfigurable>
│	│	├Abnous Evaluation of a Low-Power Reconfigurable DSP Architecture p6.pdf
│	│	├Aggarwal Bridging Parallel and Reconfigurable Computing with Multilevel PGAS and SHMEM p8.pdf
│	│	├Ahmad Efficient Reconfigurable Architectures for 3-D Medical Image Compression p207.pdf
│	│	├Akoglu Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing p8.PDF
│	│	├Al-Wattar Efficient Scheduling,Mapping and Resource Prediction for Dynamic Run time Operating Systems p272.pdf
│	│	├Alsolaim A DYNAMICALLY RECONFIGURABLE SYSTEM-ON-A-CHIP ARCHITECTURE FOR FUTURE MOBILE DIGITAL SIGNAL PROCESSING p4.pdf
│	│	├Alsolaim DYNAMICALLY RECONFIGURABLE ARCHITECTURE FOR THIRD GENERATION MOBILE SYSTEMS p327.pdf
│	│	├Amarnath A Self-Configurable Architecture on an Irregular Reconfigurable Fabric p93.pdf
│	│	├ANANDAN VLSI Implementation of Reconfigurable Low Power Fir Filter Architecture p9.pdf
│	│	├Andrade Software Synthesis from Dataflow Models for G and LabVIEW p5.pdf
│	│	├Andreas Mapping Framework for Heterogeneous Reconfigurable Architectures p127.pdf
│	│	├Attia CyGraph A Reconfigurable Architecture for Parallel Breadth-First Search p8.pdf
│	│	├Azarian Reconfigurable Computing Architecture Survey and introduction p5.pdf
│	│	├Babst Practical Reconfigurable Computing p42.pdf
│	│	├Banerjee Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198.pdf
│	│	├Beadle Software-Based Reconfigurable Computing Platform (AppSTARTM) for Multi-Mission Payloads in Spaceborne and Near-Space Vehicles p7.pdf
│	│	├Becker Configurable Systems-on-Chip Commercial and Academic Approaches p4.pdf
│	│	├Becker Configware and morphware going mainstream p16.pdf
│	│	├Beckett Towards a Reconfigurable Nanocomputer Platform p8.pdf
│	│	├Benkrid High Performance Reconfigurable Computing From Applications to Hardware p8.pdf
│	│	├Bhatia Reconfigurable Computing p185.pdf
│	│	├Bhatia Reconfigurable Computing p85.pdf
│	│	├Bhattacharyya Dynamic Dataflow Graphs p40.pdf
│	│	├Bhattacharyya Software Synthesis from Dataflow Graphs p49.pdf
│	│	├Bhattacharyya2001 Software Synthesis Trade-offs in Dataflow Representations of DSP Applications p26.pdf
│	│	├Bittner Colt An Experiment in Wormhole Run-Time Reconfiguration p8.pdf
│	│	├Bobda Synthesis of Dataflow Graphs for Reconfigurable Systems using Temporal Partitioning and Temporal Placement p90.pdf
│	│	├Bollman SCALABLE COMPUTING Practice and Experience p127.pdf
│	│	├Bondalapati Reconfigurable Computing Systems p12.pdf
│	│	├Borgatti A 1GOPS Reconfigurable Signal Processing IC with Embedded FPGA and 3-Port 1.2GBs Flash Memory Subsystem p10.pdf
│	│	├Boschetti A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications p6.PDF
│	│	├Boysen A development environment for configurable computing p10.pdf
│	│	├Brebner Reconfigurable Computing for High Performance Networking Applications p30.pdf
│	│	├Brenner Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures p72.pdf
│	│	├Brodie Dynamic Reconfigurable Computing p8.pdf
│	│	├Burleson DYNAMICALLY PARAMETERIZED ALGORITHMS AND ARCHITECTURES TO EXPLOIT SIGNAL VARIATIONS FOR IMPROVED PERFORMANCE AND REDUCED POWER p5.pdf
│	│	├Campi Re-Configurable Solutions for the high-volume ASSP Market p56.pdf
│	│	├Campi Run-Time Reconfigurable Processors p47.pdf
│	│	├Cardoso ARC2005 INTERNATIONAL WORKSHOP ON APPLIED RECONFIGURABLE COMPUTING 2005 p190.pdf
│	│	├Carroll Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency p11.pdf
│	│	├Chen A Reconfigurable Architecture for Load-Balanced Rendering p11.pdf
│	│	├CHEN Graph Minor Approach for Application Mapping on CGRAs p22.pdf
│	│	├Cheng Reconfigurable Computing p16.pdf
│	│	├Cheung Reconfigurable Elliptic Curve Cryptosystems on a Chip p7.pdf
│	│	├CHIU The Multi-context Reconfigurable Processing Unit for Fine-grain Computing p15.pdf
│	│	├Cho Diastolic Arrays Throughput-Driven Reconfigurable Computing p8.pdf
│	│	├Ciricescu The Reconfigurable Streaming Vector Processor (RSVPTM) p10.pdf
│	│	├Compton An Introduction to Reconfigurable Computing p9.pdf
│	│	├Compton Programming Architectures For Run-Time Reconfigurable Systems p34.pdf
│	│	├COMPTON Reconfigurable Computing A Survey of Systems and Software p40.pdf
│	│	├COMPTON1999 Reconfigurable Computing A Survey of Systems and Software p39.pdf
│	│	├Coughlan Introduction to Programmable Logic p28.ppt
│	│	├Cre? The CREC Reconfigurable Computer p15.pdf
│	│	├CURRERI Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing p19.pdf
│	│	├David DART  A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints p8.PDF
│	│	├Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166.pdf
│	│	├DeHon Reconfigurable Architectures for General-Purpose Computing p368.pdf
│	│	├DeHon Reconfigurable Computing What Why and Implications for Design Automation p6.pdf
│	│	├Delgado-Frias A MEDIUM-GRAIN RECONFIGURABLE CELL ARRAY FOR DSP p6.pdf
│	│	├Densmore Platform Based Reconfigurable Architecture Exploration via Boolean Constraints p 81.pdf
│	│	├Densmore Reconfigurable Architectures Overview and Commercial Examples p57.pdf
│	│	├Designing Debugging and Deploying Configurable Computing Machin.pdf
│	│	├Diessel Operating Systems Support for Dynamically Reconfigurable Architectures p12.pdf
│	│	├Dittmann Exploration partitioning and simulation of reconfigurable systems p8.pdf
│	│	├Dittmann Methods to Exploit Reconfigurable Fabrics Making Reconfigurable Systems Mature p211.pdf
│	│	├DORDOPULO Reconfigurable computer systems for digital image processing p6.pdf
│	│	├Drutarovsky CUSTOM FPGA CRYPTOGRAPHIC BLOCKS FOR RECONFIGURABLE EMBEDDED NIOS PROCESSOR p7.pdf
│	│	├Duarte Reconfigurable Computing A Survey of Architectures and Synthesis Tools p45.pdf
│	│	├Dubach Java Byte Code Synthesis for Reconfigurable Computing Platforms p71.pdf
│	│	├Eguro Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development p10.pdf
│	│	├Engel Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications p8.pdf
│	│	├Enzler The Current Status of Reconfigurable Computing p22.pdf
│	│	├Ernst A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF p18.pdf
│	│	├Ersfolk Scheduling Dynamic Dataflow Graphs with Model Checking p225.pdf
│	│	├ESHAGHIAN-WILNER The Systolic Reconfigurable Mesh p14.pdf
│	│	├Filho Description and Specialization of Coarse-grained Reconfigurable Architectures p182.pdf
│	│	├Fukushi Self-Reconfigurable Mesh Array System on FPGA p9.pdf
│	│	├Galuzzi Graph Theory and Application Specific Processors p7.pdf
│	│	├Ghazawi Parallel Programming of High-Performance Reconfigurable Computing Systems with Unified Parallel C p7.pdf
│	│	├Giani Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity p7.pdf
│	│	├Goldstein Reconfigurable Computing and Electronic Nanotechnology p12.pdf
│	│	├Gomez-Prado Optimizing Data Flow Graphs to Minimize Hardware Implementation p6.pdf
│	│	├Gong Synthesizing Sequential Programs onto Reconfigurable Computing Systems p237.pdf
│	│	├Gotz Runtime reconfigurable rtos for reconfigurable system on chip p180.pdf
│	│	├Govindarajan Algorithm for design space exploration p216.pdf
│	│	├Govindarajan Algorithm for design space explorationUN p216.pdf
│	│	├Gray Object-Oriented Reconfigurable Processing for Wireless Networks p5.pdf
│	│	├Grudnitsky Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures p6.PDF
│	│	├Guccione Reconfigurable Computing p22.pdf
│	│	├Guneysu CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES p213 .pdf
│	│	├Guo Programmability and Efficiency in Reconfigurable Computer Systems p7.pdf
│	│	├Halstead Compiling irregular applications for reconfigurable systems p11.pdf
│	│	├Hannig REGULAR MAPPING FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURES p4.pdf
│	│	├Harb A Reconfigurable Platform Architecture for an Automotive Multiple-Target Tracking System p5.pdf
│	│	├Hauck Reconfigurable Computing The Theory and Practice of FPGA-Based Computation p945.pdf
│	│	├Hauck The Future of Reconfigurable Systems p7.PDF
│	│	├Havinga Energy Management for Dynamically Reconfigurable Heterogeneous Mobile Systems p13.pdf
│	│	├Hendriks High Level Synthesis Performance Analysis and Code Optimization p105.pdf
│	│	├Heyne A PURE CORDIC BASED FFT FOR RECONFIGURABLE DIGITAL SIGNAL PROCESSING p4.pdf
│	│	├Hsu A 110 GOPSW 16-bit Multiplier and Reconfigurable PLA Loop in 90-nm CMOS p9.pdf
│	│	├HSU Hybrid LUT and SOP Reconfigurable Architecture p20.pdf
│	│	├Hudson Architecture-Independent Design for Run-Time Reconfigurable Custom Computing Machines p97.pdf
│	│	├Huynh An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization p23.pdf
│	│	├Ihrig Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric p30.pdf
│	│	├Iqbal Performance Oriented Design Perspectives of Run-Time Reconfigurable Computing Systems p10.pdf
│	│	├Jijina Low Power Architecture for Reconfigurable Fir Filter for SDR p5.pdf
│	│	├Jose Compiling Packet Programs to Reconfigurable Switches p14.pdf
│	│	├Kadam An Overview of Reconfigurable Hardware for Efficient Implementation of DSP p10.pdf
│	│	├Karkooti Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding p7.pdf
│	│	├Kastner Synthesis Techniques and Optimizations for Reconfigurable Systems p152.pdf
│	│	├Kastrup Seeking (the right) Problems for the Solutions of Reconfigurable Computing p6.pdf
│	│	├Kindratenko High-Performance Reconfigurable Computing Application Programming in C p33.pdf
│	│	├Kirasic Reconfigurable Processor Architectures Varieties and Representations p6.pdf
│	│	├Koch Architectures and Tools for Heterogeneous Reconfigurable Systems p2.pdf
│	│	├Koch Architectures Methods and Tools for Distributed Run-time Reconfigurable FPGA-based Systems p295.pdf
│	│	├KOONAR A RECONFIGURABLE HARDWARE IMPLEMENTATION OF GENETIC ALGORITHMS FOR VLSI CAD DESIGN p173.pdf
│	│	├Koutroumpezis Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-grain Implementations p10.pdf
│	│	├Krishnamurthy A Survey of Next-Generation Reconfigurable Architectures for Embedded Computing p32.pdf
│	│	├Kumar An Automated High-level Design Framework for Partially Reconfigurable FPGAs p6.pdf
│	│	├Lagger SELF-RECONFIGURABLE PERVASIVE PLATFORM FOR CRYPTOGRAPHIC APPLICATION p4.pdf
│	│	├Lechner The Java Environment for Reconfigurable Computing p10.pdf
│	│	├Lehn Framework for architecture-independent run-time reconfigurable applications p11.pdf
│	│	├Lenart Design of Reconfigurable Hardware Architectures for Real-time Applications Modeling and Implementation p195.pdf
│	│	├Liang SmartCell An Energy Efficient Reconfigurable Architecture for Stream Processing p130.pdf
│	│	├Lodi A VLIW Processor With Reconfigurable Instruction Set for Embedded Applications p11.pdf
│	│	├Lodi Reconfigurable Architectures p50.pdf
│	│	├Louri An Optical Data -Flow Computer p12.pdf
│	│	├Maestre A Framework for Reconfigurable Computing Task Scheduling and Context Management p16.pdf
│	│	├MANOLOPOULOS Reconfigurable Fast Fourier Transform Architecture for Orthogonal Frequency Division Multiplexing Systems p6.pdf
│	│	├Markovskiy Quasi-Static Scheduling for SCORE p115.pdf
│	│	├marlene A Low-Energy Heterogeneous Reconfigurable DSP IC p10.pdf
│	│	├Masselos SYSTEM LEVEL ARCHITECTURE EXPLORATION FOR RECONFIGURABLE SYSTEMS ON CHIP p6.pdf
│	│	├McMahon High Performance Reconfigurable Computing for Science and Engineering Applications p135.pdf
│	│	├Mehra Reconfigurable Cost Effective Design of Digital up Converter for Mobile Communication p9.pdf
│	│	├Mehra Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization p7.pdf
│	│	├MILLER Embedding-Based Placement of Processing element Networks on FPGAs for Physical Model Simulation p17.pptx
│	│	├Miramond Design Space Exploration for Dynamically Reconfigurable Architectures p7.pdf
│	│	├Mucci Software tools for embedded reconfigurable peocessors p243.pdf
│	│	├Myjak A TWO-LEVEL RECONFIGURABLE ARCHITECTURE FOR DIGITAL SIGNAL PROCESSING p7.pdf
│	│	├Mykyta Reconfigurable Computing Case Studies p24.pdf
│	│	├Najjar High-Level Language Abstraction for Reconfigurable Computing p7.pdf
│	│	├Nane IP-XACT Extensions for Reconfigurable Computing p4.pdf
│	│	├NICHOLS A RECONFIGURABLE COMPUTING ARCHITECTURE FOR IMPLEMENTING ARTIFICIAL NEURAL NETWORKS ON FPGA p235.pdf
│	│	├Niu EXPLOITING RUN-TIME RECONFIGURATION IN STENCIL COMPUTATION p8.pdf
│	│	├Noguera HWSW Codesign Techniques for Dynamically Reconfigurable Architectures p17.pdf
│	│	├Noguera Research in Reconfigurable Computing An Industrial Perspective p35.pdf
│	│	├Oh Dynamic Partial Reconfigurable FIR Filter Design p6.pdf
│	│	├Olson Programming a Pipelined Image Processor p41.pdf
│	│	├Ostadzadeh Parallelism Utilization in Embedded Reconfigurable Computing Systems A Survey of Recent Trends p11.pdf
│	│	├PANDYA A HANDEL-C IMPLEMENTATION OF THE BACK-PROPAGATION ALGORITHM ON FIELD PROGRAMMABLE GATE ARRAYS p218.pdf
│	│	├Parithy ADVANCED TOOLS IN RECONFIGURABLE COMPUTING p6.pdf
│	│	├Park Modulo Graph Embedding Mapping Applications onto Coarse Grained Reconfigurable Architectures p11.pdf
│	│	├Park Modulo Graph Embedding Mapping Applications onto CoarseGrained Reconfigurable Architectures p11.pdf
│	│	├Paulino Generation of Reconfigurable Circuits from Machine Code p125.pdf
│	│	├Pelkonen System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC p8.PDF
│	│	├Petersen An assessment of the suitability of reconfigurable systems for digital signal processing p149.pdf
│	│	├Pillement DART A Functional-Level Reconfigurable Architecture for High Energy Efficiency p13.pdf
│	│	├Pillement DART A Functional-Level Reconfigurable Architecture for High Energy Efficiency p15.pdf
│	│	├Poon An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications p9.pdf
│	│	├Popescu More exotic processor approaches p16.pdf
│	│	├Pottier AN INTEGRATED PLATFORM FOR HETEROGENEOUS RECONFIGURABLE COMPUTING p10.pdf
│	│	├Purna Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers p12.pdf
│	│	├Rabaey Reconfigurable Computing The Solution to Low Power Programmable DSP p10.pdf
│	│	├Raffin Scheduling Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture p8.pdf
│	│	├Rajagopal Reconfigurable stream processors for wireless base-stations p30.pdf
│	│	├Reda EN2911X Reconfigurable Computing Topic 00 Introduction p20.pdf
│	│	├Reda EN2911X Reconfigurable Computing Topic 03 Reconfigurable Computing Design Methodologies p93.pdf
│	│	├Reiner Coarse Grained Reconfigurable Architectures p28.pdf
│	│	├Rinker An Automated Process for Compiling Data flow Graphs into Reconfigurable Hardware p10.pdf
│	│	├Rosado A Reconfigurable Digital Signal Processing System for Eddy Currents Non-Destructive Testing p6.pdf
│	│	├Saidani Self-Reconfigurable Robots Topodynamic p5.pdf
│	│	├Saleeba A self reconfiguring computer system p321.pdf
│	│	├Sanchez Reconfigurable computing p48.pdf
│	│	├Saqib A Compact and Efficient FPGA Implementation of DES Algorithm p20.ppt
│	│	├Sarrigeorgidis Massively Parallel Wireless Reconfigurable Processor Architecture and Programming p8.PDF
│	│	├SAY A RECONFIGURABLE COMPUTING PLATFORM FOR REAL TIME EMBEDDED APPLICATIONS p154.pdf
│	│	├Say A reconfigurable computing platform for real time embedded applications p20.pdf
│	│	├Schier RECONFIGURABLE IMAGE PROCESSING ARCHITECTURE WITH SIMULINK PROTOTYPING SUPPORT p4.pdf
│	│	├Sghaier Efficient Implementations of WiMAX OFDM Functions on Reconfigurable Platforms p143.pdf
│	│	├Shafer A Development Method for Reconfigurable Hardware Systems With Real-Time Wavelet Image Compression Application p8.pdf
│	│	├Shoup Reconfigurable Systems New Tools and New Math p12.pdf
│	│	├Sigdel System-Level Design Space Exploration of Reconfigurable Architectures p223.pdf
│	│	├SILVA A Dynamic Dataflow Architecture using Partial Reconfigurable Hardware as an option for Multiple Cores p16.pdf
│	│	├Silva Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System p13.pdf
│	│	├Singh Partitioning and Mapping of Computation Structure on a Coarse-Grained Reconfigurable Architecture p121.pdf
│	│	├Singh Reconfigurable Computing A review of the technology and its architecture p7.pdf
│	│	├Sinha FIELD PROGRAMMABLE DSP ARRAYS A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFFICIENT REALIZATION OF DIGITAL SIGNAL PROCESSING FUNCTIONS p18.pdf
│	│	├Skliarova Intelligent Systems Engineering with Reconfigurable Computing p10.pdf
│	│	├Slade Reconfigurable Computing Application Frameworks p10.pdf
│	│	├Sripornprasert The AES Encryption Circuit on a Reconfigurable Hardware p4.pdf
│	│	├STALIN A STUDY ON LOW POWER RECONFIGURABLE FIR FILTERS WITH DYNAMIC CHANGE IN FILTER ORDER p8.pdf
│	│	├Steinbach UML-BASED CO-DESIGN FOR RUN-TIME RECONFIGURABLE ARCHITECTURES p15.pdf
│	│	├Stekelenburg Low Cost Fast Turnaround Reconfigurable Graph-Based Execution Units p5.pdf
│	│	├Stitt Reconfigurable Computing A Plan for Post-Moore's Law Sustainability p17.pdf
│	│	├STOJANOVIC An Overview of Selected Hybrid and Reconfigurable Architectures p25.pdf
│	│	├Streichert Self-Adaptive Hardware Software Reconfigurable Networks p253.pdf
│	│	├Sun Design of a Simulator for Mesh-based Reconˉgurable Architectures p10.pdf
│	│	├Sung Memory Efficient Software Synthesis from Dataflow Graph p20.ppt
│	│	├Sutter Coarse-Grained Reconfigurable Array Architectures p39.pdf
│	│	├Svensson Reconfigurable Architectures for Embedded Systems p183.pdf
│	│	├Synplicity Reconfigurable System-on-a-Chip p12.pdf
│	│	├TANIGUCHI Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model p20.pdf
│	│	├Teich Reconfigurable Computing Systems p4.pdf
│	│	├Templin DESIGN OF AN ADAPTABLE RUN-TIME RECONFIGURABLE SOFTWARE-DEFINED RADIO PROCESSING ARCHITECTURE p63.pdf
│	│	├Thahir Compiling for Reconfigurable Computing p25.pdf
│	│	├Tiwari Hardware Software Co-debugging for Reconfigurable Computing p81.pdf
│	│	├VANCOURT Elements of High-Performance Reconfigurable Computing p45.pdf
│	│	├Venkataramani A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture p10.pdf
│	│	├Vorbach Reconfigurable Processor Architectures for Mobile Phones p6.PDF
│	│	├Wang Loop Kernel Pipelining Mapping onto Coarse- Grained Reconfigurable Architecture for Data- Intensive Applications p9.pdf
│	│	├WANKAR RECONFIGURABLE ARCHITECTURES AND ALGORITHMS A RESEARCH SURVEY p16.pdf
│	│	├WANKAR2009 RECONFIGURABLE ARCHITECTURES AND ALGORITHMS A RESEARCH SURVEY p15.pdf
│	│	├Ward Dynamically-Reconfigurable-Computing p6.pdf
│	│	├Windh High-Level Language Tools for Reconfigurable Computing p19.pdf
│	│	├Wu Reconfigurable Architectures from Physical Implementation to Dynamic Behaviour Modelling p136.pdf
│	│	├YANG TISA Reconfigurable System for Template-Based Stream Computing p5.pdf
│	│	├Zain-ul-Abdin High-Level Programming of Coarse-Grained Reconfigurable Architectures p80.pdf
│	│	├Zhang A 1-V Heterogeneous Reconfigurable DSP IC for Wireless Baseband Digital Signal Processing p8.pdf
│	│	├ZHANG Auto-adaptive reconfigurable architecture for scalable multimedia applications p7.pdf
│	│	└ZhangXJ Module Allocation for Dynamically Reconfigurable Systems p9.pdf
│	└<soc>
│	  	├Pande SoC Design & Test p26.ppt
│	  	├socdam-notes1011.pdf
│	  	├Wakabayashi C-Based SoC Design Flow and EDA Tools An ASIC and System Vendor Perspective p16.pdf
│	  	└Wang SYSTEM-ON-CHIP TEST ARCHITECTURES NANOMETER DESIGN FOR TESTABILITY p893.pdf
├<VLSICADTools>
│	├<Altera>
│	│	├Altera  Introduction to Quartus II Software p11.pdf
│	│	├Altera  MAX+PLUS II  Getting Started p355.pdf
│	│	├Altera  MAX+PLUS II  Getting Started p380.pdf
│	│	├Altera  MAX+PLUS II  Getting Started p65.pdf
│	│	├Altera  Quartus II  Introduction Using Schematic Designs p37.pdf
│	│	├Altera Quartus II Handbook Version 9.1 Volume 1 Design and Synthesis p2454.pdf
│	│	├Altera Quartus II Handbook, Volume 1 Design & Synthesis p964.pdf
│	│	├Au MAX+PLUS II Tutorial Manual p32.pdf
│	│	├Cristian  INTRODUCTION TO “MAXPLUS II” p11.pdf
│	│	├ESL MAX+plus II 使用教學 p10.pdf
│	│	├NCKU Altera Quartus II 軟體之介紹與操作 p37.pdf
│	│	├Schindler Altera’s Max+plus II Tutorial p25.pdf
│	│	├Tietz QUARTUS AND MODELSIM QUICK START p10.pdf
│	│	├Wells Altera’s MAX+plus II and the UP 1 Educational Board A User’s Guide p59.pdf
│	│	└佟冬 MaxPlusII 使用指南 p12.pdf
│	├<ELECTRIC>
│	│	├Aluru  EXPLORING ANALOG AND DIGITAL DESIGN USING THE OPEN-SOURCE ELECTRIC VLSI DESIGN SYSTEM p90.pdf
│	│	├Harris CMOS VLSI Design Lab 1 Cell Design and Verification p18.pdf
│	│	├Harris CMOS VLSI Design Lab 1 Gate Design p18.pdf
│	│	├Harris VLSI Design with Electric p39.pdf
│	│	├Mistri IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System p7.pdf
│	│	├Rubin Electric a Multithreaded Integrated-Circuit Design System p17.pdf
│	│	├Rubin Using the Electric VLSI Design System 6.08 p402.pdf
│	│	├Rubin Using the Electric VLSI Design System 6.08_1 p402.pdf
│	│	├Rubin Using the Electric VLSI Design System 8.09 p350.pdf
│	│	├Rubin Using the Electric VLSI Design System 8.11 p362.PDF
│	│	├Rubin Using the Electric VLSI Design System 9.03 p396.pdf
│	│	├Rubin Using the Electric VLSI Design System 9.07 p400.pdf
│	│	└Teen  IC Layout Design of Decoder Using Electric VLSI Design System p7.pdf
│	├Kougianos VLSI Design Through Open-Source Free Tools p21.pdf
│	├Liu Open-Source VLSI CAD Tools A Comparative Study p6.pdf
│	├RubinSteven Computer Aids for VLSI Design Second Edition 1994 p443.pdf
│	├Scheffer EDA for IC Implementation Circuit Design and Process Technology p616.pdf
│	├Singh Evolution and Trends of VLSI Design Methodologies and CAD Tools p45.pdf
│	└VLSICADTools.txt
├vlsistudies.docx
├vlsistudies.pdf
├vlsi_list.docx
├vlsi_list.pdf
├<ZZZICBusiness>
│	├<clients>
│	│	└clients.docx
│	└<monthly_reports>
│	  	├<reports>
│	  	│	└<2017>
│	  	│	  	├WIDeR201710.docx
│	  	│	  	└WIDeR201711.docx
│	  	├<sources>
│	  	│	├abstract_Beenker.pdf
│	  	│	├<eda>
│	  	│	│	└design.docx
│	  	│	├fermilab-pub-06-343-e.pdf
│	  	│	├IJETT-V3I3P218.pdf
│	  	│	├MoSC2014_Advanced-packaging_technologies_The_implications_for_first_movers_and_fast_followers.pdf
│	  	│	├<others>
│	  	│	│	├2007-04-27中国手机芯片行业的发展趋势以及面临的问题.txt
│	  	│	│	├2016-09-13国内外对比令人震惊：国产芯片为什么这么落后.txt
│	  	│	│	├2017-03-08技术落后 中国发展半导体芯片产业任重道远.txt
│	  	│	│	├2017-11-10中国正发力发展芯片技术.txt
│	  	│	│	├2017-11-15揭秘芯片背后的技术较量.txt
│	  	│	│	└others.docx
│	  	│	├<packaging>
│	  	│	│	├ICEC IC DEVICE AND PACKAGING TECHNOLOGY TRENDS 1998 p58.PDF
│	  	│	│	└packaging.docx
│	  	│	├<research and development>
│	  	│	│	├2015-11-10芯片光学互联研究取得突破性进展.txt
│	  	│	│	├2017-07-29光子芯片技术发展现状及趋势.txt
│	  	│	│	├2017-08-21光电子集成芯片技术发展现状与趋势.txt
│	  	│	│	├2017-10-11半导体、电子设备：AI芯片行业迎来黄金发展期.txt
│	  	│	│	├2017-11-15存储器芯片有望实现零突破 跟踪研发进展.txt
│	  	│	│	├<Efinix>
│	  	│	│	│	└Efinix可编程芯片.png
│	  	│	│	└research and development.docx
│	  	│	├<technology,industry and manufacturing>
│	  	│	│	├Bhardwaj Revolution of Integrated Circuit in the Era of 2020 2013 p5.pdf
│	  	│	│	├Iwai Future of Silicon Integrated Circuit Technology 2007 p5.pdf
│	  	│	│	├McClean_IC-Insights_SEMI-TX-Outlook_Oct2013 p29.pdf
│	  	│	│	├Saraswat Trends in Integrated Circuits Technology 2010 p27.pdf
│	  	│	│	├Saraswat Trends in Integrated Circuits Technology 2010 p56.pdf
│	  	│	│	└tech.docx
│	  	│	├The Future of Integrated Circuits.ppt
│	  	│	├zzznews_chinese.docx
│	  	│	└zzznews_english.docx
│	  	└zzzinfo.txt
├<_DesignProject>
│	├<1frontend>
│	│	├01规格制定详细设计.txt
│	│	├02HDL编码.txt
│	│	├<Analog>
│	│	│	├ADT6401_6402.pdf
│	│	│	├ADT7320_ADT7420_FAQs.pdf
│	│	│	├ADT7420.pdf
│	│	│	├ADT7420_cn.pdf
│	│	│	├ADT7462-D.PDF
│	│	│	├ADT7516_7517_7519.pdf
│	│	│	├Analog ADM9240 p22.pdf
│	│	│	├EVAL-ADT7516EBZ_UG-911.pdf
│	│	│	└UG-138.pdf
│	│	├<Cypress>
│	│	│	└002-08550_MB3793-27A_Power_Voltage_Monitoring_IC_with_Watchdog_Timer.pdf
│	│	├<DallasSemiconductors>
│	│	│	└DS1780 CPU Peripheral Monitor.pdf
│	│	├<FinTek>
│	│	│	└F75373S.pdf
│	│	├<ITE>
│	│	│	├IT8783_A_V0.5_062510.pdf
│	│	│	└<iTE IT8720F芯片>
│	│	│	  	└iTE IT8720F芯片.png
│	│	├Kester HARDWARE MONITORING p15.pdf
│	│	├McCaffrey Monitoring Temperature and Fan Speed Using Ganglia and Winbond Chips p11.pdf
│	│	├<NationalSemiconductor>
│	│	│	├LM4140.pdf
│	│	│	└LM85.pdf
│	│	├<Nuvoton>
│	│	│	├DA00-NCT6627UDA1.pdf
│	│	│	├DA00-W83627UHGD.pdf
│	│	│	├NCT5605Y_Datasheet_V10.pdf
│	│	│	├NCT7904D_Datasheet_V1.45.pdf
│	│	│	├Nuvoton_NCT7511Y_Datasheet_V1_0.pdf
│	│	│	├Nuvoton_NCT7717U_Datasheet_V111.pdf
│	│	│	├Nuvoton_NCT7802Y_Datasheet_V12.pdf
│	│	│	└Nuvoton_W83795G_W83795ADG_Datasheet_V1.43.pdf
│	│	├<Onsemi>
│	│	│	├ADM1025-D.PDF
│	│	│	└Onsemi ADM1024 System Hardware Monitor with Remote Diode Thermal Sensing p30.PDF
│	│	├<SMSC>
│	│	│	└emc1133db.pdf
│	│	├<TexasInstruments>
│	│	│	├Hardware Monitoring and Fan Control.pdf
│	│	│	├lm78.pdf
│	│	│	├lm96080.pdf
│	│	│	└slva385.pdf
│	│	├<TQ-Group>
│	│	│	└TQMxE38M.UM.0101.pdf
│	│	├<USENIX>
│	│	│	└sec13-paper_imeson.pdf
│	│	├<Winbond>
│	│	│	├W83627THF.pdf
│	│	│	└Winbond W83792ADD W83792AGG HW Monitoring IC (CSB Version) p97.pdf
│	│	├两线远程IO 扩展芯片CH423.PDF
│	│	└胡访宇 微机原理与接口技术 第六章IO接口和并行接口芯片8255A p115.pdf
│	├<2backend>
│	├Chen PID Controller Project Final Report p77.pdf
│	├Ferguson VLSI Project Stopwatch Chip p30.pdf
│	├Syed High‐Speed 8‐bit Pipeline Current‐Steering DA Converter p59.pdf
│	└zzzdesignproject.txt
└<_DOCS>
      ├<chiptech>
      │	└chip_techsall.docx
      └<design>
            ├design.txt
            ├edainfo.txt
            ├<general>
            │	├benchmark_chip.docx
            │	├chip_design.docx
            │	├chip_design_physical.docx
            │	└VLSIDesign.docx
            └<routing>
                  └chip_design_routing.docx


VLSI Resources

designer.doc
designer.txt
edadevelopers.docx
edadevelopers.txt
foundry.docx
foundry.txt
others.docx
others.txt
programmers.docx
temp.txt
websites_completed.txt
websites_temp.txt
websources.docx
websources.txt
websources_all_others.txt

VLSI Designers

Math for Chip Design >>> Chip Technologies >>> Resources

World

http://www.3dlabs.com/

http://www.8x8.com/

http://www.sc.ic.ac.uk/

http://www.accel-india.com/

http://www.actel.com/

www.adeptchips.com/

www.advico.de/

http://www.adixen.com/

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www.allicstech.com

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www.ams.com

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http://www.analog-alchemy.de/

www.analogchip.com

http://www.andraka.com/

http://www.ansem.com/

www.anysilicon.com

http://www.apache-da.com/

www.apple.com

http://www.appliedmaterials.com/

http://arasan.com

www.arf-design.com

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www.arm.com

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http://www.artechinfo.com/

www.ashenden.com.au

www.ashton-systems.com

www.asic.co.za

www.asic.co.in

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www.atrenta.com

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http://www.bitmapper.com/

http://www.bluechiptechnology.co.uk/

http://www.bluespec.com/

www.broadcom.com

http://www.brooktree.com/

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http://www.butterflydsp.com/

http://www.c-cube.com/

http://www.cadence.com/

www.cadmazing.com/

www.calsoftlabs.com

http://www.carbondesignsystems.com/

www.catena.nl/

http://www.catsemi.com/

http://www.cavium.com/

http://www.cdac.in/

http://www.cdi-diodes.com/

http://www.centillium.com/

http://www.centtech.com/

http://www.ceva-dsp.com/

http://www.cg-coreel.com/

http://www.cgcoreel.com/

http://www.charteredsemi.com/

http://www.cherry-semi.com/

http://www.cherrysoft.com/

http://www.chip-architect.com/

http://www.chip-start.com/

www.chip-start.com

www.chipdesign.be

www.chipdesign.ca

www.chipdesigns.com.au

http://www.chipdesign.co.in/

www.chipenable.co.uk

http://www.chipexpress.com/

www.chiphuntdesign.com

http://www.chips.com/

www.chipslawnservice.com/

http://www.chiptestinc.com/

http://www.chipworks.com/

http://www.chrontel.com/

www.cic.org.tw/

http://www.cir-q-tech.net/

http://www.circuitsutra.com/

http://www.cirrus.com/

http://www.cirsolutions.com/

www.cisdesign.com

http://www.cmd.com/

http://www.cmrda.com/

www.cmrindia.com

http://www.cocochip-ic-design.com/

http://www.colognechip.com/

http://www.color-chip.com/

http://www.compunetix.com

www.comsoc.com/

http://www.dreamchip.de

http://www.conexant.com/

http://www.controlnetindia.com/

http://www.cortina-systems.com/

http://www.cosmiccircuits.com/

http://www.coware.com/

http://www.creativechips.com/

http://www.cranessoftware.com/

http://www.criticalblue.com/

http://www.crystal.com/

http://www.csr.com/

http://www.csn.net/ramtron/enhanced/

http://www.cswitch.com/

www.custommmic.com

www.cvs-verification.com

http://www.cvs-verification.com/

www.cypress.com

http://www.cyrix.com/

http://www.dafca.com/

http://www.dalsemi.com/

www.danicdesign.com/

www.design-reuse.com

www.designcrowd.com/

http://www.datadelay.com/

http://www.dcd.pl/

http://www.dcmds.com/

http://www.denali.com/

http://www.dgbmicro.com/

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http://www.digchip.com/

www.digi.com

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http://www.dlp.com/

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http://www.dspcsp.com/

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http://www.dspdimension.com/

http://www.e-coninfotech.com/

http://www.eag.com/mte/

http://www.easics.com/

http://www.eda.org/

https://www.edacentrum.de/

www.eag.com/

www.easics.com/

www.edaindia.com

http://www.edisonsemiconductor.com/

www.edn.com

www.eeherald.com

https://www.einfochips.com/

http://www.einfochips.com/

http://www.elantec.com/

http://www.electronic-designs.com/

www.embeddedintel.com

http://www.embeddedwireless.com/

www.emersysdesign.com/

http://www.emulex.com/

www.encoresemi.com/

www.ensilica.com/

http://www.envivio.com/

http://www.epcos.com/

www.esilicon.com/

www.essensium.com

http://www.essexcorp.com/

http://www.esterel-eda.com/

www.europractice-ic.com/

http://www.eve-team.com/

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http://lge.expo.co.kr/lge/

http://www.ezchip.com/

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www.faraday-tech.com/

www.fastrack-design.com

www.flextaskservice.com/

http://www.flipchip.com/

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www.fujitsu.com

http://www.fujitsumicro.com/

www.fujixerox.com

www.fulcrummicro.com

http://www.galileot.com/

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http://www.genesisus.com/

http://www.gennum.com/

http://www.gfmicro.com/

http://www.ghz.com/

http://www.gi.com/

http://www.gnss.com/

www.gps-world.biz

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www.greenarraychips.com

www.gfmicro.com/

http://www.graychip.com/

www.grotal.com

www.gsaglobal.org

www.guc-asic.com

www.hcltech.com

http://www.hcltech.com/

http://www.helic.com/

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www.hitachi.com

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http://www.holtek.com./

http://www.ssec.honeywell.com/

www.honeywellmicroelectronics.com

www.hp.com

www.hotfrog.in

http://www.hsmcindia.com/

www.hummingbirdscientific.com

http://www.hutsonind.com/

http://www.chips.ibm.com/

www.ibef.org

http://www.ibiden.com/

www.ibm.com

www.icdesign.co.uk

www.icdesignnews.com/

www.digidescorp.com

www.icds.nl

www.icdsn.com

www.icmaskdesign.com/

http://www.icmic.com/

http://www.icon-dapl.com/

http://www.icsense.com/

www.icsense.com

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www.lfoundry.com

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www.intel.com

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www.leuveninc.com

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www.livemint.com

www.loac-hsg-imit.de/

http://www.logicdevices.com/

http://www.logicvision.com/

http://www.lsem.com/

http://www.lsi.com/

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http://www.ltindia.com/

http://www.lucent.com/micro/

http://www.lumex.com/

www.madebydelta.com

http://www.magma-da.com/

http://www.masamb.com/

www.matricus.com

www.marvell.com

http://www.maxim-ic.com/

http://www.mcc.com/

http://www.mdstec.com/

http://www.megachips.us/

http://www.mei.co.jp/

www.mentor.com/

http://www.microchip.com/

http://www.microclock.com/

http://www.microhybrids.com/

http://www.microlinear.com/

www.micromagic.com/

www.microsemi.com

www.mightyohm.com

www.mimarchipdesign.com

www.mindcet.com

www.mindchip.net

http://www.mindtree.com/

http://www.minicircuits.com/

http://www.mips.com/

http://www.mirafra.com/

http://www.mistralsoftware.com/

http://www.mitelsemi.com/

http://www.mitydsp.com/

http://www.mnc.com/

http://www.montalvosystems.com/

www.moortec.com

http://www.moschip.com/

http://www.moselvitelic.com/

www.mosis.com

www.motorola.com

http://www.mrcy.com/

http://www.mstarsemi.com/

http://www.mti-milliren.com/

http://www.mxcom.com/

www.nangate.com

www.narlabs.org.tw

http://www.natinst.com/

http://www.national.com/

http://www.ncoretech.com/

http://www.sg.necel.com/

http://www.neomagic.com/

http://www.nepen.com/

http://www.netins.net/showcase/elab

http://www.netlogicmicro.com/

http://www.nevisnetworks.com/

www.nielit.in/

http://www.nomus.in/

http://gec.nova.com.ph/

http://www.novas.com/

http://www.novalog.com/

http://www.novellus.com/

www.nsn.com

http://www.nsc.com/

http://www.nsysinc.com/

http://www.nulifetech.com/

www.numetrics.com

www.nxp.com

http://www.okisemi.com/

http://www.onechipphotonics.com

http://www.onsemi.com/

http://www.open-silicon.com/

http://www.opti.com/

www.optimuslogic.in

http://www.orbitsemi.com/

http://www.oxfordmicrodevices.com/

http://www2.oxsemi.com/

http://pacificmicrochip.com/

http://www.pactxpp.com/

www.palmchip.com

www.perceptia.com

http://www.panasonic.com/PIC

http://www.pantronix.com/

http://www.patni.com/

http://www.pcsi.com/

http://www.perfectus.com/

http://www.perftrends.com/

http://www.semiconductors.philips.com/

www.philips.com

http://www.phylon.com/

www.pluschip.com

http://www.plxtech.com/

http://www.pmc-sierra.bc.ca/

http://pmcs.com/

http://www.posedge.com/

http://www.power-tech.com/

http://www.procsys.com/

http://www.prodesign-europe.com/

http://www.pulsecoresemi.com/

http://punechips.com/

http://www.qlc.com/

http://www.qlogic.com/

http://www.qualcorelogic.com/

www.qualcomm.cn?

www.qualcomm.com?

www.atheros.com

www.qualchiptech.com

http://www.qualitysemi.com/

http://www.quicklogic.com/

www.rachip.com

http://www.racom.com/

http://www.radisys.com/

http://www.rambus.com/

http://www.redwoodmicro.com/

http://www.rendition.com/

http://www.renesas.com/

www.rfcafe.com/

http://www.rfmd.com/

www.rivlan.com/

http://www.nb.rockwell.com/

http://www.ross.com/

http://www.s3.com/

www.s2cinc.com

www.samsung.com

http://www.samsungsemi.com/

http://www.sandisk.com/

http://www.sasken.com/

www.savantas.org/

http://www.sclindia.com/

http://www.seeq.com/

http://www.seiko-usa-ecd.com/

http://www.semi-tech-inc.com/

www.semicontaiwan.org

www.semitestcorp.com

http://www.semtech.com/

http://www.sensirion.com/

http://www.sensoryinc.com/

www.sgi.com

http://www.sharpmeg.com/

http://www.sierrasemi.com/

http://www.sigmadesigns.com/

http://www.simagic.com/

http://www.siliconinterfaces.com/

http://www.silabs.com/

www.silansys.com

www.siliconinterfaces.com

www.silicon-ip.com

http://www.siliconix.com/

www.siliconsemiconductor.net

http://www.sipex.com/

www.sispark.com.cn

http://www.slip.net/~slin

http://www.smc.com/

www.smics.com/

http://www.smos.com/

http://www.smsc.com/

http://www.sn.no/granjansen/

http://www.sni.net/ramtron

http://www.sni.net/simtek

www.socle-tech.com/

http://www.soctechnologies.com/

www.solekai.com

www.solomon-systech.com

www.sondrel.com

www.sony-lsi.co.jp

http://www.spectel.com/

http://www.spreadtrum.com/

http://www.spt.com/

http://www.ssi1.com/

http://www.sst.com/

www.st.com

http://www.statschippac.com/

http://www.stretchinc.com/

http://www.sundancedsp.com/

www.oracle.com/sun

www.swindonsilicon.co.uk

http://www.supertex.com/

http://www.sykiotech.com/

http://www.symbios.com/

http://www.symmidsemi.com/

http://www.synergysemi.com/

http://www.synfora.com/

http://www.syntaq.com/

www.systematic.nl

http://www.systemcom.hr/

http://www.tallika.com/

http://www.tataelxsi.com/

http://www.tcs.com/

http://www.tsc.tdk.com/

http://www.techaccel.com/

http://www.teccor.com/

http://www.tejasnetworks.com/

www.tekedia.com

http://www.telcom-semi.com/

http://www.telos.de/

http://www.teltone.com/

http://www.temic-semi.com/

http://www.tensilica.com/

www.teramics.com

http://www.teranetics.com/

http://www.tesbv.com/

http://www.tessolve.com/

www.tessolve.com

www.tevatrontech.com

www.tezzaron.com

http://www.tforceinc.com/

http://www.thaler.com/

https://www.thalesgroup.com

http://www.think-silicon.com

www.ti.com.cn

www.tiempo-ic.com/

http://www.toshiba.com/taec/

http://www.towersemi.com/

http://www.transwitch.com/

http://www.trid.com/

http://www.tridenttechlabs.com/

http://www.triquint.com/

http://www.tritechmicro.com/

http://www.tseng.com/

www.tsmc.com

www.truecircuits.com

http://www.veri-sure.com/

http://www.tundra.com/

www.tyndall.ie

www.uniquify.com

http://www.unitrode.com/

http://www.usar.com/

http://www.utmc.com/

http://www.v3logic.com/

http://www.vedatech.net/

http://www.vadem.com/

www.valencetech.com

http://www.velankani.com/

www.varindia.com

www.veri-sure.com

http://www.verisilicon.com/

http://www.via.com.tw/

http://www.viadesigner.com/

www.vinchip.com

http://www.vinchip.com/

http://www.viragelogic.com/

http://www.vitesse.com/

http://www.vividsemi.com/

http://www.vixs.com/

http://www.vlsi.com/

http://www.vlsiplus.com/

http://www.vlsisystemdesign.com/

http://www.vtc.com/

http://www.w9gr.com/

www.wavante.com

http://www.waveaxis.com/

http://www.wdc.com/

http://www.wdesignc.com/

http://www.weitek.com/

http://www.westcode.com/

http://www.whitemicro.com/

http://whizchip.com/

www.wipro.com

http://www.wipro.com/

http://www.wsipsd.com/

http://www.xicor.com/

http://www.xlinkusa.com/

www.xilinx.com

www.xmos.com

http://www.xtreme-eda.com/

http://www.yamahayst.com/

www.ycell.co.il/

http://www.yogitech.com/

http://www.zarlink.com/

www.zib.de

http://www.zilog.com/

http://www.zoran.com/

Taiwan

http://www.admtek.com.tw/

http://www.ali.com.tw/

http://www.amic.com.tw/

http://www.analog.com.tw/

http://www.anpec.com.tw/

http://www.aslic.com.tw/

http://www.atantech.com.tw/

http://www.atcorp.com.tw/

http://www.bsi.com.tw/

http://www.davicom8.com/

http://www.ecmos.com.tw/

http://www.emc.com.tw/

http://www.esmt.com.tw/

www.etron.com

www.etron.com.tw

http://www.eureka.com.tw/

http://www.faraday.com.tw/

www.globalunichip.com

http://www.gstc.com.tw/

www.himax.com.tw

http://www.hmc.com.tw/

http://www.holtek.com.tw/

http://www.inno.com.tw/

http://www.issi.com.tw/

http://www.ite.com.tw/

www.mediatek.com

http://www.mtk.com.tw/

http://www.myson.com.tw/

http://www.mxic.com.tw/

www.novatek.com.tw

http://www.nuvoton.com/

www.nvidia.com

www.nvidia.cn

http://www.pgc.com.tw/

www.phison.com

http://www.princeton.com.tw/

http://www.prolific.com.tw/

www.promos.com.tw

http://www.psc.com.tw/

www.psc.com.tw

www.realtek.com.tw

http://www. richtek.com

http://www.sg.com.tw/

www.sis.com.tw

http://www.siti.com.tw/

www.sitronix.com.tw

http://www.spil.com.tw/

http://www.springsoft.com.tw/

http://www.sunplus.com.tw/

http://www.syntekt.com.tw/

http://www.tmi.com.tw/

http://www.tmtech.com.tw/

http://www.topro.com.tw/

www.tsmc.com

www.umc.com

http://www.usc.com.tw/

http://www.utron.com.tw/

www.viatech.com.cn

www.viatech.com.tw

http://www.weltrend.com/

China

www.actions-semi.com

http://www.admiral-ic.com/

http://www.aisinochip.com/

www.alchip.com

www.allwinnertech.com

www.anlogic.com

www.amlogic.com.cn

www.analogix.com

www.anyka.com

www.apexonemicro.com

www.asmcs.com

www.availink.com.cn

www.aviaic.com

http://www.awinic.com.cn/

www.bcdsemi.com

http://www.bctest.com/

www.bekencorp.com

www.bmser.com

www.bpsemi.com

www.britesemi.com

www.broadstar.cn

www.bwave.cc

www.byd.com.cn

www.c2micro.com

www.capital-micro.com

http://www.capitalbio.com/

www.cellixsoft.com.cn

http://www.cellix.com.cn/

http://www.china-core.com/

http://www.china-dsp.com

http://china-super-chip.com/

www.chinabamc.com

http://www.chinachip.org.cn/

http://www.chipblooming.com

http://www.chiphomer.com/

www.chiplink-semi.com

www.chipown.com

www.chipsbank.com

www.chipsea.com

http://www.chipsvision.com.cn

http://www.chiptheme.com/

www.cidc.com.cn

www.commit.cn

www.crmicro.com

www.crpowtech.com

http://www.cystar.cn/

www.datang.com

www.dioo.com

www.dmt.com.cn

http://www.dowaytech.com/

http://www.dspsemi.com/

www.eastmicrotech.com

http://www.eda.ac.cn/

http://www.eda-china.com

http://www.enpowchip.com

www.eshine-ic.com

www.etek.com.cn

www.fangtek.com.cn

http://www.fast-china.com

http://www.fmsh.com/

www.fremontmicro.com

http://www.galaxychn.com/

http://www.gcore.com.cn/

www.gcoreinc.com

http://www.genitop.com/

http://www.giantec-semi.com/

www.giga-solution.com

www.gigadevice.com

http://www.gotopsys.com/

http://www.guoshi-ic.com/

www.haier-ic.com

http://www.hcsemitek.com/

http://www.health-digit.com/

www.hd-os.com

www.hed.com.cn

http://www.hicc.org.cn/

http://www.hicc.org.cn/About1.asp?id=18

www.hisilicon.com

www.htc.com/cn/

http://www.huajie-tech.com/

http://www.icc.sh.cn/

http://www.ichaier.com/

http://www.icinf.com/

http://www.icrd.com.cn

http://www.icubecorp.com

http://www.igreenchip.com

www.infix-ip.com

www.infotmic.com

www.infotmic.com.cn

www.innofidei.com

www.ingenic.cn

www.ipgoal.com

www.isisip.com

http://www. istecc.com

www.jadechip.com

http://www.jeteam.cn

http://www.jiemiic.com/

www.jszgled.com

http://www.jwsemi.com

www.kandit.cn

www.krosspower.com

http://www.ktmicro.com.cn/

www.leadcoretech.com

www.leadchip.com.cn

www.leaguerme.com

www.lingkes.com

http://www.loongson.cn/

www.lontiumsemi.com

www.maxictech.com

www.maxscend.com

www.memsic.com.cn

www.montage-tech.com

www.mstarsemi.com

www.mvsilicon.com

www.mxtronics.com

www.natlinear.com

www.nationalchip.com

www.nationz.com.cn

http://www.novatek.com.cn/

www.nufront.com

www.nufrontsoft.com

http://www.risecomm.com.cn/

www.nsiway.com.cn

http://www.on-bright.com/

www.optek.com.cn

www.panovasic.com

www.paradetech.com

http://www.pcbco.net/

http://www.pcbdate.cn/

www.prochip.com.cn

http://www.qualchiptech.com/

www.quinticcorp.com

www.rdamicro.com

www.reactor-micro.com

http://www.rfmc.com.cn/

www.rock-chips.com

www.ruichips.com

http://www.s2cinc.com.cn

www.seawardinc.com.cn

www.semipower.com.cn

www.senodia.com

www.sg-micro.com

http://www.shblue.com/

http://www.shhic.com/

www.shhic.com

www.si-power.com

http://www.sigmachip.com/

http://www.silan.com.cn/

http://www.sileadinc.com/

www.simplnano.com

www.sino-ic.cn

http://www.sinoic.net/

www.sinowealth.com

www.solomon-systech.com.cn

www.spreadtrum.com

http://www.statschippac.com/

www.sungine.com

http://www.sunplus.com.tw/schinese/

www.superchip.com.cn

www.superpix.com.cn

www.swid.com.cn

http://www.synochip.com/

http://www.szchip.com/

www.szcyt.com

http://www.sziccs.com/

http://www.szicpark.com/

http://www.tomeda.com.cn/

http://www.tonerchipchina.com/

http://www.trendsil.com/

www.ime.tsinghua.edu.cn

www.tsinghuaic.com?

www.ssmec.com?

www.chinaasic.com?

www.smit.com.cn

www.union-ic.com

www.unicorecomm.com

http://www.unisilicon.com/

www.uxfastic.com

www.verisilicon.com

www.vimicro.com.cn???????

www.ptsn.net.cn

http://www.wavante.com/

www.wenchangchip.com

www.wenhaochip.com

http://www.wenhaochip.com/

http://www.whicc.com/

http://www.wisectech.com.cn/

http://www.wxic.cn/

http://www.xel-tech.com/

http://www.xiaocheng.com/

http://www.xlsemi.com/

www.xptek.cn

http://www.yunchip.com

http://www.zhsic.org/

http://www.zitengic.com

EDA Developers

World

http://www.3soft.com/

http://www.acc-eda.com/

https://www.home.agilent.com/agilent/

http://www.agnisys.com/

http://www.ahl.co.uk/

http://www.aldec.com/

http://www-soc.lip6.fr/

http://www.altagroup.com/

http://www.altera.com/

http://www.altium.com/

http://www.ami.com/Products/

http://www.anagraminc.com/

http://www.analog.com/

http://www.ansoft.com/

http://www.ansys.com

http://www.antaresco.com/

http://www.aries-da.com

http://www.asicworld.com

http://www.artwork.com/

http://www.aspectdv.com/

http://www.atmel.com/

http://www.atrenta.com/

http://www.auspex.com/

http://www.avanticorp.com/

http://www.avista.com/

http://www.awrcorp.com/

http://splat.baker.com/

http://www.bdti.com/

http://www.bdtic.com/

http://www.cs.berkeley.edu/~lazzaro/chipmunk/pickup/pickup.html

http://www.bjicpark.com/

http://www.bluepearlsoftware.com

http://www.cadabratech.com/

http://www.cadence.com/

http://www.cadmigos.com/

http://www.cadsoftusa.com/

http://www.cae-plus.com/

http://calypto.com/

http://www.capilano.com/

http://www.carbondesignsystems.com/

http://www.cast-inc.com/

http://www.cctech.com/

http://www.cdac.com/

http://www.chiplab.com/

http://www.chronology.com/

http://www.ciotc.org/

http://www.compass-da.com/

http://www.comsol.com/

http://www.crosscheck.com/

http://www.data-io.com/

http://www.designacc.com/

http://www.designbychip.com/

http://www.diagonal.com/

http://www.digi.com/

http://www.techwin.org/

http://www.dadisp.com/

http://www.dspsolutions.com/

http://www.e-tools.com/

http://www.eagledes.com/

http://www.eda.ac.cn/software/software_tool/huada/

http://www.edac.org/EngDataXpress

http://www.edac.org/Escalade

http://www.edac.org/SVR/

http://www.edac.org/Syntest

https://www.einfochips.com/

http://www.emdoor.com/

http://www.encoresemi.com/

http://www.epic.com/

http://www.europractice-ic.com/

http://www.exemplar.com/

http://www.forteds.com/

http://www.freescale.com/

http://www.frequency.com/

http://www.frontline.com/

http://www.gambit.com/

www.gpleda.org

http://www.globalfoundries.com/design/

http://www.haier-ic.com/

http://www.harriseda.com/

http://www.hp.com/csocat/eda/edapages/analogy.htm

http://www.hp.com/csocat/eda/edapages/aspec.htm

http://www.hp.com/go/hpeesof

http://www.hyperception.com/

http://www.icarus.com

http://www.icmaskdesign.com/

http://www.icx.com/

http://www.ihs.com/

http://www.ikos.com/

http://www.imgtec.com/

http://ibfriedrich.com/

http://www.intellitech.com/

http://www.intellx.com/

http://www.interactiv.com/

http://www.interhdl.com/

http://www.intusoft.com/

http://www.jamestandon.com/

http://jasper-da.com/

http://www.jedatechnologies.net/

http://www.labcenter.com

http://www.latticesemi.com/

http://www.lauterbach.com

http://www.laytools.com/

http://www.layouteditor.net/

http://www.lucent.com/blda/

http://www.lvision.com/

http://www.matricus.com/

http://www.mcuos.com/

http://www.mentor.com/

http://www.metasw.com/

http://www.microcode.com/

http://www.microsemi.com/

http://www.nangate.com/

http://www.ni.com/

http://www.nec-labs.com/

http://www.nextwave.com/

http://www.nimbic.com/

http://www.numberone.com/

http://www.nuthena.com/

http://www.oaktech.com/

http://www.oasys-ds.com/

http://www.onespin-solutions.com/

http://opencircuitdesign.com/

http://www.opencollector.org

http://www.opencores.org

http://opencores.org/

http://www.optem.com/

http://www.orcad.com/

http://www.pads.com/

http://zeus.phase3.com/

http://www.picochip.com/

http://www.platform.com/

http://www.plunify.com/

http://www.powereda.com/

http://www.precedence.com/

http://www.prema.com/Design/chip-eda-tools.html

http://www.prolific.com.tw/

http://www.protel.com/

http://www.pulsonix.com/

http://www.quickturn.com/

http://www.zuken.com/

http://www.redac.co.uk/

http://www.redchipsolutions.com/

http://robei.com/

http://www.or.uni-bonn.de/

http://www.rtda.com/

http://www.rv-vlsi.com

http://www.savantage.com/

http://www.scsn.net/~kbscorp

http://www.semico.com/

http://www.ses.com/

http://www.sigasi.com/

http://www.silvaco.com/

http://www.simucad.com/

http://www.simtech.com/

http://www.solidodesign.com/

http://www.spectrum-soft.com

http://www.speed.com/

http://www.speedsim.com/

http://www.springsoftintl.com/

http://www.st.com

http://www.summit-design.com/

http://www.syncad.com/

http://www.synopsys.com/

http://www.synplicity.com/

http://www.systems.com/

http://www.tanner.com/

http://www.tannereda.com/

http://www.tdf.com/

http://www.terasic.com.cn/

http://www.tevatrontech.com/

http://www.texeda.de/

http://www.tmai.com/

http://www.topdown.com/

http://www.tuxmaniac.com

http://www.twolf.com/

http://ronja.twibright.com

http://www.unicad.com/

http://www.unikinfo.com/

http://www.or.uni-bonn.de/

http://www.veda.co.uk/

http://www.veribest.com/

http://www.veritools-web.com/

http://www.vhdl.com.au/

http://vhdl.org/vi/fmf

http://www.viewlogic.com/

http://www.vlibs.com/vlibs/

http://www.voom.net/

http://www.xilinx.com/

http://www.yokogawa.co.jp/

http://www.zycad.com/

EDA Information Portals

http://www.21ic.com/eda/

http://www.36ic.com/forum.php

http://www.36ic.com/thread-890-1-1.html

http://book.51cto.com/art/201103/246985.htm

http://chipdesignmag.com/

http://www.chipdesignmag.com/

http://chipdesignmag.com/display.php?articleId=3459

http://www.chiplayout.net/

http://www.circuitstoday.com/circuit-design-and-simulation-softwares

http://www.designnews.com/

http://www.eda-china.com/

http://www.edaboard.com/

http://www.edaboard.com/thread192274.html

http://www.edabus.com/

http://www.edabus.com/category/tech/eda

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with IP databases

http://www.edacafe.com/

http://www.edautils.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design interactive

http://www.edn.com/

http://www.edn.com/design/integrated-circuit-design

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design interactive

http://www.edn-europe.com

http://www.edn-europe.com/en/on-chip-debug-jesd204b-fpga-software-for-designs-with-fast-converters.html?cmp_id=7&news_id=10002570

http://www.ednasia.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design interactive very good site

http://www.ednchina.com/

http://www.eechina.com/

http://www.eechina.com/thread-94738-1-1.html

http://www.eet-china.com/

http://www.eetasia.com/

http://www.eettaiwan.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design projects

http://www.eeweb.com/

http://www.eeweb.com/electronics-forum

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://electronicdesign.com/

https://fedorahosted.org/fedora-electronic-lab/

http://www.fullchipdesign.com/

http://www.futurechips.org/

http://www.hotchips.org/

http://www.icdesignnews.com/

http://www.opencollector.org/summary.php

www.optimization-online.org/

http://www.semi.org.cn/

http://ic.semi.org.cn/

http://ic.semi.org.cn/channel/ic_design_eda.html

http://www.semiwiki.com/forum/showwiki.php?title=Semi+Wiki:EDA+Open+Source+Tools+Wiki

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://vlsi.pro/

http://www.vlsitechnology.org/html/ic_software.html

China

???????????????????????

http://www.saict.org/

http://www.saict.org/ptfw/12/1935.shtml

http://www.tomeda.com.cn/

Foundries

World

http://www.altissemiconductor.com/

http://www.amd.com/cn

http://www.americansemi.com/

http://www.analog.com/

http://www.asmcs.com/

http://www.austriamicrosystems.com/

http://www.atmel.com/

http://www.compoundsemi.co.uk/

http://www.cree.com/

http://www.cypress.com/

http://www.dalsa.com

http://www.darpa.mil/

http://www.dongbuhitek.com/

http://www.elume.com/

http://www.episil.com.tw/

http://www.espros.ch/

http://www.europractice-ic.com/

http://www.fairchildsemi.com/

http://www.freescale.com/

www.fujitsu.com

http://www.gcsincorp.com/

http://www.globalfoundries.com/

www.hitachi.com.cn

http://www.hmc.com.tw/

http://www.ssec.honeywell.com

IBM

http://www.lfoundry.com

http://www.ihp-microelectronics.com/

http://www.imec.be/

http://www.imflash.com/

http://www.infineon.com/

http://www.irf.com/

http://www.intel.com

http://www.jazzsemi.com/

http://www.loac-hsg-imit.de

http://www.liteon-semi.com

http://www.magnachip.com/

http://www.maximintegrated.com/

http://www.memc.com/

http://www.memscapinc.com/

http://www.memsengineering.com/

MHS Electronics

http://www.micrel.com/

https://www.microchip.com/

http://www.micron.com/

http://www.mimos.my

http://www.mirrorsemi.com

http://www.mosel.com.tw/

http://www.mosis.com/

http://www.motorola.com/

http://www.mxic.com.tw/

http://www.nanostructures.com/

www.nec.com

http://www.nxp.com/

http://www.okisemi.com/

http://www.onsemi.com/

http://www.panjit.com/

http://www.peregrine-semi.com/

http://www.pgc.com.tw/

http://www.polarfab.com/

http://www.promos.com.tw/

http://www.psc.com.tw/

http://www.rfmd.com

http://www.rohm.com/

http://www.roguevalleymicro.com

http://www.sames.co.za/

http://www.sandia.gov/mstc/services/silicon-fabrication.html

http://www.sandisk.com/

http://www.sarnoff.com/

http://www.scaleochip.com/

http://www.semefab.com/

http://www.mirrorsemi.com/

http://www.silexmicrosystems.com

http://www.silterra.com/

http://www.smics.com/

http://www.sitar.org.in/

http://www.skhynix.com/

http://www.spansion.com/

http://www.st.com/

http://www.sunycnse.com/

http://www.supertex.com/

http://www.svtc.com/

http://www.tanner.com/Labs/mems/

http://www.telefunkensemi.com

http://www.teledynedalsa.com

https://www.ti.com/

www.toshiba.com.cn

http://www.towersemi.com/

http://www.transyselectronics.com/

http://www.triquint.com/

http://www.tronics-mst.com/

http://www.trustedfoundry.com/

http://www.tsmc.com/

http://www.umc.com

http://www.usic.com.tw/

http://www.ums-gaas.com/

http://www.vis.com.tw/

http://www.winbond.com.tw/

http://www.winfoundry.com/

http://www.wsmc.com.tw/

http://www.xfab.com/

http://www.zarlink.com/

China

www.asmcs.com

www.belling.com.cn

www.cj-elec.com?

www.jcap.cn

www.founderic.com

www.hhgrace.com

www.hhgrace.com

www.hjtc.com.cn

www.huahong.com.cn/

www.ict.ac.cn

http://www.smics.com

Others

World

IC Consultants

www.asic-vlsi.com

www.chipscalereview.com

www.chipworks.com

http://www.garysmitheda.com/

www.statschippac.com

https://www.udemy.com/vlsi-academy/

Organizations - IC related

www.atip.org

www.semi.org

www.semiconductors.org

http://vlsi-india.org/

China

Web Sources of Chip

China

http://www.086ic.cn/

http://www.1-ic.com/

http://www.114ic.cn/

http://www.173ic.com/

http://kucun.21ic.com/

http://www.345ic.com/

http://www.883ic.com/

http://www.97ic.com/

http://www.b2bic.com/

http://www.buy-ic.com

http://china-chip-parts.com/

http://www.chinesechip.com/

http://www.chiplayout.net/

http://www.cpu-cn.com/

http://www.dram.com.cn/

http://www.enet.com.cn/cpu/

http://info.ec.hc360.com/list/zl_jcdl.shtml

http://www.esoic.net/

http://www.gdicw.com/

http://www.gongic.com/

http://www.ic.net.cn/

http://www.ic-trade.com/

http://www.ic137.com/

http://www.ic37.com/

http://www.ic5858.com/

http://www.ic72.com/???

http://www.ic918.com/

http://www.icbj.cn/

http://www.icbuy.com/

http://www.iccpp.com.cn/

http://www.iceach.com/

http://www.iceasy.com/

http://www.icfull.com/

http://www.icgoo.net/

http://www.icjyw.com/

http://www.icmade.com/IC/

http://www.icmai.net/

http://www.icmartonline.com/

http://www.icpdf.com/

http://www.icpop.com/

http://www.ictown.com/

http://www.jobic.cn/

http://www.laogu.com/

http://www.mianfeiic.com/

http://www.mmic.net.cn/

http://www.qic.com.cn/

http://www.qooic.com/

http://www.rightic.com/

http://www.seekchip.com/

http://www.soiseek.cn/

http://www.xinpian.net.cn/

http://www.zdor.cn/xinpian.html

World / Chip / VLSI

http://www.chipdesignmag.com/

http://www.chiportal.co.il/

http://www.coolchips.org/wp/

www.cpu-world.com

http://dsp-fpga.com/

http://www.dspguide.com/

http://www.dspguru.com/

http://www.dsprelated.com/

http://www.chinaicmart.com/

http://microcontroller.com/

https://www.semiwiki.com/

http://siliconchip.com.au/

VLSI EDA Resources

VLSI CAD Conferences

ACM/IEEE Design Automation Conference (DAC)

http://www.dac.com/

Design and Test in Europe (DATE)

European Design Automation Conference (EDAC)

IEEE Great Lakes Symposium on VLSI (GLSVLSI)

http://www.glsvlsi.org

International Conference on Computer Aided Design (ICCAD)

http://iccad.com

International Conference on Computer Design (ICCD)

http://www.iccd-conf.com/

IEEE International Symposium on Circuits and Systems (ISCAS)

http://iscas2014.org/

International Conference on Low Power Electronic Design (ISLPED)

ISPD global routing contest

http://www.sigda.org/

International Symposium on Physical Design (ISPD)

http://www.ispd.cc/

IEEE Midwest Symposium on Circuits and Systems (MSCAS)

http://ieee-cas.org/

International Conference on VLSI Design

http://vlsidesignconference.org/

http://www.vlsidesignconference.org/

http://www.socconference.com/

VLSI CAD Journals

IEEE Transactions on CAD of Circuits and Systems

Integration

Transactions on Circuits and Systems

Journal of Circuits, Systems and Computers?

Algorithmica

SIAM journal of Discrete and Applied Mathematics

IEEE Transactions on Computers

VLSI CAD Organizations

ACM SIGDA

Design Automation Technical Committee (DATC) of IEEE Computer Society


VLSI Designers

Math for Chip Design >>> Chip Technologies >>> Resources

World

http://www.3dlabs.com/

http://www.8x8.com/

http://www.sc.ic.ac.uk/

http://www.accel-india.com/

http://www.actel.com/

www.adeptchips.com/

www.advico.de/

http://www.adixen.com/

http://www.aha.com/

http://www.akm.com/

http://www.aldinc.com/

www.allicstech.com

http://www.alitech.com/

www.alphachips.com

http://www.alphatec.com/

http://www.alsc.com/

www.altera.com

http://www.amcc.com/

www.amd.com

http://www.amdlsed.com/

www.ami.com

http://www.ammostech.com/

http://www.amis.com/

http://www.amkor.com/

www.ams.com

http://www.anadigics.com/

http://www.analog.com/

http://www.analog-alchemy.de/

www.analogchip.com

http://www.andraka.com/

http://www.ansem.com/

www.anysilicon.com

http://www.apache-da.com/

www.apple.com

http://www.appliedmaterials.com/

http://arasan.com

www.arf-design.com

www.argondesign.com

http://www.aries-da.com

www.arm.com

http://www.arrivesys.com/

http://www.artechinfo.com/

www.ashenden.com.au

www.ashton-systems.com

www.asic.co.za

www.asic.co.

www.atheros.com

http://www.atmel.com/

www.atrenta.com

http://www.avagotech.com/

www.avnet-asic.com/

www.axiom-ic.com/

www.aytera.com

http://www.baegan.com/

http://www.bartronicsindia.com/

http://bayareachipdesign.com

http://www.bcdph.com/

http://www.bdti.com/

http://www.beceem.com/

http://www.bel-india.com/

http://www.bitmapper.com/

http://www.bluechiptechnology.co.uk/

http://www.bluespec.com/

www.broadcom.com

http://www.brooktree.com/

http://www.burr-brown.com/

http://www.cadence.com/

www.cadmazing.com/

www.calsoftlabs.com

http://www.carbondesignsystems.com/

www.catena.nl/

http://www.catsemi.com/

http://www.cavium.com/

http://www.cdac.in/

http://www.cdi-diodes.com/

http://www.ceva-dsp.com/

http://www.chip-start.com/

www.chipdesign.be

www.chipdesign.ca

http://www.chipexpress.com/

http://www.chipworks.com

www.cic.org.tw/

http://www.circuitsutra.com/

http://www.cirrus.com/

www.cmrindia.com

http://www.cocochip-ic-design.com/

http://www.colognechip.com/

http://www.color-chip.com/

www.comsoc.com/

http://www.dreamchip.de

http://www.conexant.com/

http://www.controlnetindia.com/

http://www.cortina-systems.com/

http://www.cosmiccircuits.com/

http://www.coware.com/

http://www.creativechips.com/

http://www.cranessoftware.com/

http://www.criticalblue.com/

http://www.crystal.com/

www.custommmic.com

www.cvs-verification.com

http://www.cvs-verification.com/

www.cypress.com

http://www.cyrix.com/

http://www.dalsemi.com/

www.danicdesign.com/

www.design-reuse.com

http://www.digchip.com/

http://www.dspace.com/

http://www.dspg.com

http://www.dspdimension.com/

http://www.eag.com/mte/

http://www.easics.com/

http://www.eda.org/

https://www.edacentrum.de/

www.edaindia.com

www.edn.com

www.eeherald.com

https://www.einfochips.com/

http://www.einfochips.com/

www.embeddedintel.com

http://www.embeddedwireless.com/

www.encoresemi.com/

www.ensilica.com/

www.esilicon.com/

www.europractice-ic.com/

http://www.eve-team.com/

http://www.exar.com/

http://www.ezchip.com/

http://www.fabtecheng.com/

http://fairlabs.com/

www.faraday-tech.com/

www.fastrack-design.com

www.flextaskservice.com/

http://www.flipchip.com/

http://www.fortiss.org

http://www.ftdichip.com/

http://www.focaltech-systems.com

http://www.fourctron.com/

www.fujitsu.com

http://www.fujitsumicro.com/

www.fujixerox.com

www.fulcrummicro.com

http://www.gctsemi.com/

http://www.gdatech.com/

http://www.genesisus.com/

http://www.gfmicro.com/

http://www.gnss.com/

http://www.gpsemi.com/

http://www.graychip.com/

www.greenarraychips.com

www.gsaglobal.org

www.guc-asic.com

http://www.helic.com/

http://www.hyd.hellosoft.com/

www.hitachi.com

http://www.halsp.hitachi.com/

http://www.holtek.com./

http://www.ssec.honeywell.com/

www.honeywellmicroelectronics.com

www.hp.com

www.hotfrog.in

http://www.hsmcindia.com/

www.hummingbirdscientific.com

http://www.hutsonind.com/

http://www.chips.ibm.com/

http://www.ibiden.com/

www.ibm.com

www.icdesignnews.com/

www.digidescorp.com

www.icds.nl

www.icdsn.com

www.icmaskdesign.com/

http://www.icmic.com/

http://www.icon-dapl.com/

http://www.icsense.com/

http://www.icst.com/

http://www.idt.com/

http://www.ikanos.com/

www.lfoundry.com

www.imgtec.com

http://www.implantaire.com/

www.imst-dsi.com

http://www.incide-semi.com/

www.infineon.com

www.intel.com

www.interradesign.com

http://www.ip-extreme.com/

www.iptestchip.com

http://www.irf.com/

http://www.isd.com/

http://www.issiusa.com/

www.itechland.com

http://www.ittiam.com/

http://www.iwavesystems.com/

http://www.ixys.com/

http://www.jedatechnologies.net/

www.keyasic.com

www.kilopass.com/

www.latticesemi.com

http://www.ligasystems.com/

http://www.logicdevices.com/

http://www.lucent.com/micro/

www.madebydelta.com

http://www.magnachip.com

http://www.mathworks.de

www.matricus.com

www.marvell.com

http://www.maxim-ic.com/

http://www.mdstec.com/

http://www.megachips.us/

www.mentor.com/

http://www.microchip.com/

http://www.microhybrids.com/

MicroLab

www.micromagic.com/

http://www.micronas.com

www.microsemi.com

www.mightyohm.com

www.mimarchipdesign.com

www.mindcet.com

http://www.minicircuits.com/

http://www.mips.com/

http://www.mirafra.com/

http://www.mitydsp.com/

www.moortec.com

http://www.moschip.com/

http://www.moselvitelic.com/

http://www.mosis.com/

www.motorola.com

http://www.mstarsemi.com/

http://www.mti-milliren.com/

www.nangate.com

www.narlabs.org.tw

http://www.ncoretech.com/

http://www.neomagic.com/

http://www.nevisnetworks.com/

http://www.ni.com/

www.nielit.in/

http://www.nomus.in/

http://www.novellus.com/

www.nxp.com

http://www.onsemi.com/

http://www.open-silicon.com/

www.optimuslogic.in

http://pacificmicrochip.com/

http://www.pactxpp.com/

www.palmchip.com

www.perceptia.com

http://www.panasonic.com/PIC

http://www.pantronix.com/

http://www.perfectus.com/

http://www.perftrends.com/

www.philips.com

www.pluschip.com

http://pmcs.com/

http://www.pmc-sierra.bc.ca/

http://www.procsys.com/

http://www.prodesign-europe.com/

http://punechips.com/

http://www.qlc.com/

http://www.qlogic.com/

www.qualcomm.cn

www.qualcomm.com?

http://www.quicklogic.com/

www.rachip.com

http://www.rambus.com/

http://www.redwoodmicro.com/

http://www.renesas.com/

www.rfcafe.com/

www.rivlan.com/

www.s2cinc.com

www.samsung.com

http://www.samsungsemi.com/

http://www.sandisk.com/

http://www.sasken.com/

http://www.sclindia.com/

http://www.seeq.com/

http://www.semi-tech-inc.com/

www.semitestcorp.com

http://www.semtech.com/

www.sgi.com

http://www.sharpmeg.com/

http://www.sigmadesigns.com/

http://www.siliconinterfaces.com/

http://www.silabs.com/

www.silansys.com

www.siliconinterfaces.com

www.silicon-ip.com

http://www.smartchipdesign.in/

http://www.soctechnologies.com/

http://www.sol-chip.com/

www.solekai.com

www.solomon-systech.com

www.sondrel.com

www.sony-lsi.co.jp

http://www.ssi1.com/

http://www.sst.com/

www.st.com

http://www.statschippac.com/

http://www.stretchinc.com/

http://www.sundancedsp.com/

http://www.supertex.com/

www.swindonsilicon.co.uk

www.systematic.nl

http://www.systemcom.hr/

http://www.tataelxsi.com/

http://www.tcs.com/

www.teramics.com

http://tes-dst.com

http://www.tessolve.com/

www.tevatrontech.com

www.tezzaron.com

https://www.thalesgroup.com

http://www.think-silicon.com

www.ti.com.cn

http://www.toshiba.com/taec/

http://www.towersemi.com/

http://www.tridenttechlabs.com/

http://www.triquint.com/

www.tsmc.com

www.truecircuits.com

www.tyndall.ie

www.uniquify.com

www.valencetech.com

http://www.validas.de/

www.varindia.com

http://www.veri-sure.com/

http://www.verisilicon.com/

http://www.viadesigner.com/

http://www.vishay.com/

http://www.vitesse.com/

http://www.vixs.com/

http://www.vlsiplus.com/

http://www.vlsisystemdesign.com/

www.wavante.com

http://www.wdesignc.com/

http://whizchip.com/

http://www.wipro.com/

www.xilinx.com

www.xmos.com

http://www.xtreme-eda.com/

www.ycell.co.il/

http://www.yogitech.com/

www.zib.de

http://www.zilog.com/

Taiwan

http://www.ali.com.tw/

http://www.amic.com.tw/

http://www.analog.com.tw/

http://www.anpec.com.tw/

http://www.ecmos.com.tw/

http://www.emc.com.tw/

http://www.esmt.com.tw/

www.etron.com

www.etron.com.tw

http://www.faraday.com.tw/

www.globalunichip.com

www.himax.com.tw

http://www.holtek.com.tw/

http://www.inno.com.tw/

http://www.issi.com.tw/

http://www.ite.com.tw/

www.mediatek.com

http://www.mtk.com.tw/

http://www.myson.com.tw/

http://www.mxic.com.tw/

www.novatek.com.tw

http://www.nuvoton.com/

www.nvidia.com

www.nvidia.cn

http://www.pgc.com.tw/

www.phison.com

http://www.princeton.com.tw/

http://www.prolific.com.tw/

www.promos.com.tw

http://www.psc.com.tw/

www.realtek.com.tw

http://www.sg.com.tw/

www.sis.com.tw

http://www.siti.com.tw/

www.sitronix.com.tw

www.socle-tech.com/

http://www.spil.com.tw/

http://www.sunplus.com.tw/

http://www.tmtech.com.tw/

www.tsmc.com

www.umc.com

http://www.via.com.tw/

www.viatech.com.cn

www.viatech.com.tw

http://www.weltrend.com/

China

www.actions-semi.com

www.alchip.com

www.allwinnertech.com

www.anlogic.com

www.amlogic.com.cn

www.analogix.com

www.anyka.com

www.availink.com.cn

www.aviaic.com

http://www.awinic.com.cn/

www.bcdsemi.com

http://www.bdtic.com/

www.bekencorp.com

www.bmser.com

www.bpsemi.com

www.britesemi.com

www.broadstar.cn

www.bwave.cc

www.byd.com.cn

www.capital-micro.com

http://www.capitalbio.com/

http://www.cellix.com.cn/

http://www.china-core.com/

www.chinaasic.com

http://www.chinachip.org.cn/

http://www.chiphomer.com/

www.chipown.com

www.chipsea.com

http://www.chipsvision.com.cn

http://www.chiptheme.com/

www.crmicro.com

www.crpowtech.com

http://www.cystar.cn/

www.datang.com

www.dioo.com

www.dmt.com.cn

http://www.dowaytech.com/

http://www.dspsemi.com/

www.eastmicrotech.com

http://www.eda.ac.cn/

http://www.eda-china.com

http://www.enpowchip.com

www.etek.com.cn

www.fangtek.com.cn

http://www.fast-china.com

http://www.fmsh.com/

www.fremontmicro.com

http://www.galaxychn.com/

http://www.gcore.com.cn/

www.gcoreinc.com

http://www.genitop.com/

http://www.giantec-semi.com/

www.giga-solution.com

www.gigadevice.com

www.haier-ic.com

http://www.hcsemitek.com/

www.hd-os.com

http://www.hicc.org.cn/

www.hisilicon.com

http://www.icc.sh.cn/

http://www.icinf.com/

http://www.icrd.com.cn

http://www.icubecorp.com

http://www.igreenchip.com

www.innofidei.com

www.ingenic.cn

www.ipgoal.com

www.jadechip.com

http://www.jiemiic.com/

www.jszgled.com

www.leadcoretech.com

www.leadchip.com.cn

www.leaguerme.com

www.lingkes.com

www.lontiumsemi.com

www.maxictech.com

www.memsic.com.cn

www.montage-tech.com

www.mstarsemi.com

www.mvsilicon.com

www.natlinear.com

www.nationalchip.com

www.nationz.com.cn

http://www.novatek.com.cn/

www.nsiway.com.cn

http://www.on-bright.com/

www.optek.com.cn

www.paradetech.com

http://www.pcbco.net/

http://www.pcbdate.cn/

www.prochip.com.cn

www.qualchiptech.com

www.quinticcorp.com

www.rdamicro.com

http://www.rfmc.com.cn/

http://www.risecomm.com.cn/

www.rock-chips.com

www.ruichips.com

http://www.s2cinc.com.cn

www.seawardinc.com.cn

www.semipower.com.cn

www.senodia.com

www.sg-micro.com

http://www.shblue.com/

http://www.shhic.com/

www.si-power.com

http://www.sigmachip.com/

http://www.silan.com.cn/

http://www.sileadinc.com/

www.sinowealth.com

http://www.smit.com.cn/

www.solomon-systech.com.cn

www.ssmec.com

http://www.statschippac.com/

http://www.sunplus.com.tw/

http://www.synochip.com/

http://www.szchip.com/

http://www.sziccs.com/

http://www.szicpark.com/

http://www.tomeda.com.cn/

http://www.tonerchipchina.com/

http://www.trendsil.com/

www.ime.tsinghua.edu.cn

www.tsinghuaic.com

www.union-ic.com

www.unicorecomm.com

http://www.unisilicon.com/

www.uxfastic.com

www.verisilicon.com

www.vimicro.com.cn

http://www.wavante.com/

www.wenchangchip.com

http://www.wenhaochip.com/

http://www.wisectech.com.cn/

http://www.wxic.cn/

http://www.xiaocheng.com/

http://www.xlsemi.com/

http://www.yunchip.com

http://www.zhsic.org/


EDA Developers

World

http://www.agnisys.com/

http://www.aldec.com/

http://www-soc.lip6.fr/

http://www.altera.com/

http://www.altium.com/

http://www.ami.com/Products/

http://www.analog.com/

http://www.ansys.com

http://www.aries-da.com

http://www.artwork.com/

http://www.atmel.com/

http://www.atrenta.com/

http://www.bdti.com/

http://www.bluepearlsoftware.com

http://www.cadence.com/

http://www.cadsoftusa.com/

http://calypto.com/

http://www.carbondesignsystems.com/

http://www.cast-inc.com/

http://www.comsol.com/

http://dataio.com/

http://www.designbychip.com/

http://designworkssolutions.com/

http://www.dadisp.com/

http://www.eda.ac.cn/software/software_tool/huada/

http://www.encoresemi.com/

http://www.freescale.com/

www.gpleda.org

http://www.icmaskdesign.com/

http://ibfriedrich.com/

http://www.intusoft.com/

http://jasper-da.com/

http://www.jedatechnologies.net/

http://www.labcenter.com

http://www.latticesemi.com/

http://www.lauterbach.com

http://www.laytools.com/

http://www.layouteditor.net/

http://www.lucent.com/blda/

http://www.matricus.com/

http://www.mentor.com/

http://www.microsemi.com/

http://www.nangate.com/

http://www.ni.com/

http://www.nec-labs.com/

http://www.nimbic.com/

http://www.numberone.com/

http://www.onespin-solutions.com/

http://opencircuitdesign.com/

http://www.opencollector.org

http://www.opencores.org

http://www.optem.com/

http://www.orcad.com/

http://www.picochip.com/

http://www.plunify.com/

http://www.prolific.com.tw/

http://www.pulsonix.com/

http://www.rtda.com/

http://www.semico.com/

http://www.sigasi.com/

http://www.silvaco.com/

http://www.simucad.com/

http://www.solidodesign.com/

http://www.syncad.com/

@@@@@@@@@@@@@@@@@@@@@@

http://www.synopsys.com/

http://www.tanner.com/

http://www.tannereda.com/

http://www.tdf.com/

http://www.terasic.com.cn/

http://www.tevatrontech.com/

http://www.texeda.de/

http://www.unicad.com/

http://www.unikinfo.com/

http://www.or.uni-bonn.de/

http://www.veritools-web.com/

http://www.voom.net/

http://www.xilinx.com/

http://www.yokogawa.co.jp/

http://www.zuken.com/

http://www.zycad.com/


EDA Information Portals

http://www.circuitstoday.com/circuit-design-and-simulation-softwares

http://www.edaboard.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with IP databases

http://www.edacafe.com/

http://www.edautils.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design interactive

http://www.edn.com/

http://www.edn.com/design/integrated-circuit-design

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design interactive

http://www.edn-europe.com

http://www.ednasia.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design interactive very good site

http://www.eetasia.com/

http://www.eettaiwan.com/

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! with design projects

http://www.eeweb.com/

http://www.eeweb.com/electronics-forum

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://electronicdesign.com/

https://fedorahosted.org/fedora-electronic-lab/

http://www.fullchipdesign.com/

http://www.futurechips.org/

www.optimization-online.org/

http://ic.semi.org.cn/

http://www.semiwiki.com/forum/showwiki.php?title=Semi+Wiki:EDA+Open+Source+Tools+Wiki

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

http://vlsi.pro/

http://www.vlsitechnology.org/html/ic_software.html

China

http://www.eda-china.com/

http://www.ednchina.com/

http://www.eechina.com/

http://www.eet-china.com/

http://www.tomeda.com.cn/


Foundries

World

http://www.altissemiconductor.com/

http://www.amd.com/cn

http://www.americansemi.com/

http://www.austriamicrosystems.com/

http://www.compoundsemi.co.uk/

http://www.cree.com/

http://www.cypress.com/

http://www.dalsa.com

http://www.darpa.mil/

http://www.dongbuhitek.com/

http://www.elume.com/

http://www.episil.com.tw/

http://www.espros.ch/

http://www.europractice-ic.com/

http://www.fairchildsemi.com/

http://www.freescale.com/

www.fujitsu.com

http://www.gcsincorp.com/

http://www.globalfoundries.com/

www.hitachi.com.cn

http://www.hmc.com.tw/

http://www.ssec.honeywell.com

IBM

http://www.lfoundry.com

http://www.ihp-microelectronics.com/

http://www.imec.be/

http://www.imflash.com/

http://www.infineon.com/

http://www.irf.com/

http://www.intel.com

http://www.jazzsemi.com/

http://www.loac-hsg-imit.de

http://www.liteon-semi.com

http://www.magnachip.com/

http://www.maximintegrated.com/

http://www.memc.com/

http://www.memscapinc.com/

http://www.memsengineering.com/

MHS Electronics

http://www.micrel.com/

https://www.microchip.com/

http://www.micron.com/

http://www.mimos.my

http://www.mirrorsemi.com

http://www.mosel.com.tw/

http://www.mosis.com/

http://www.motorola.com/

http://www.mxic.com.tw/

http://www.nanostructures.com/

www.nec.com

http://www.nxp.com/

http://www.okisemi.com/

http://www.onsemi.com/

http://www.panjit.com/

http://www.peregrine-semi.com/

http://www.pgc.com.tw/

http://www.polarfab.com/

http://www.promos.com.tw/

http://www.psc.com.tw/

http://www.rfmd.com

http://www.rohm.com/

http://www.roguevalleymicro.com

http://www.sames.co.za/

http://www.sandia.gov/mstc/services/silicon-fabrication.html

http://www.sandisk.com/

http://www.sarnoff.com/

http://www.scaleochip.com/

http://www.semefab.com/

http://www.silexmicrosystems.com

http://www.silterra.com/

http://www.smics.com/

http://www.sitar.org.in/

http://www.skhynix.com/

http://www.spansion.com/

http://www.st.com/

http://www.sunycnse.com/

http://www.supertex.com/

http://www.svtc.com/

http://www.tanner.com/Labs/mems/

http://www.telefunkensemi.com

http://www.teledynedalsa.com

https://www.ti.com/

www.toshiba.com.cn

http://www.towersemi.com/

http://www.transyselectronics.com/

http://www.triquint.com/

http://www.tronics-mst.com/

http://www.trustedfoundry.com/

http://www.tsmc.com/

http://www.umc.com

http://www.usic.com.tw/

http://www.ums-gaas.com/

http://www.vis.com.tw/

http://www.winbond.com.tw/

http://www.winfoundry.com/

http://www.wsmc.com.tw/

http://www.xfab.com/

http://www.zarlink.com/

China

http://www.asmcs.com/

www.belling.com.cn

www.cj-elec.com

www.jcap.cn

www.founderic.com

www.hhgrace.com

www.hjtc.com.cn

www.huahong.com.cn/

www.ict.ac.cn

http://www.smics.com


Others

World

IC Consultants

www.asic-vlsi.com

www.chipscalereview.com

www.chipworks.com

http://www.garysmitheda.com/

Traning

http://www.chipdesigncollege.com/

http://chipedge.com/

http://www.iivdt.com/

https://www.udemy.com/vlsi-academy/

http://www.vlsitraining.com/

Research

www.imtek.de

http://www.saict.org/

Organizations - IC related

www.atip.org

http://www.edac.org/

www.semi.org

http://www.semi.org.cn/

www.semiconductors.org

http://www.semiconkorea.org/

www.semicontaiwan.org

www.siliconsemiconductor.net

http://vlsi-india.org/

Capitals

Samsung Strategy and Innovation Center

http://www.samsung.com/us/ssic/

Samsung Catalyst Fund

Samsung Ventures America Fund

http://www.samsungventures.com/

Samsung Venture Investment Corporation

www.samsungventure.co.kr

@@@@@@@@@@@@@@@@

JCD Co., Ltd. (JCD = Japan China Development)

http://www.jcd.co.jp/

info@jcd.co.jp

Adobe Ventures

Agilent Ventures

Alcatel-Lucent Ventures

AOL Ventures

ASML Ventures

Blackberry Partners Fund

Adobe Ventures

Agilent Ventures

Alcatel-Lucent Ventures

AOL Ventures

Applied Ventures

ASML Ventures

Blackberry Partners Fund

Blue Run Ventures

Google Ventures

Hewlett Packard Corporate Ventures

Hitachi Corporate Venture Capital Fund

Hoya Ventures

IBM Venture Capital Group

iD Tech Ventures

Intel Capital

National Science Council

http://www.nsc.gov.tw

Panasonic Venture Group

Prime Technology Ventures

QinetiQ Ventures

Qualcomm Ventures

SAIC Venture Capital Corporation

SAP Vemtures

Taicom Capital

TEL Venture Capital

TI Venture Capital Program

TSMC Partners

VanEdge Venture

VentureTech Alliance

Wipro Capital

China


VLSI EDA Resources

VLSI CAD Conferences

ACM/IEEE Design Automation Conference (DAC)

http://www.dac.com/

Design and Test in Europe (DATE)

European Design Automation Conference (EDAC)

IEEE Great Lakes Symposium on VLSI (GLSVLSI)

http://www.glsvlsi.org

International Conference on Computer Aided Design (ICCAD)

http://iccad.com

International Conference on Computer Design (ICCD)

http://www.iccd-conf.com/

IEEE International Symposium on Circuits and Systems (ISCAS)

http://iscas2014.org/

International Conference on Low Power Electronic Design (ISLPED)

ISPD global routing contest

http://www.sigda.org/

International Symposium on Physical Design (ISPD)

http://www.ispd.cc/

IEEE Midwest Symposium on Circuits and Systems (MSCAS)

http://ieee-cas.org/

International Conference on VLSI Design

http://vlsidesignconference.org/

http://www.vlsidesignconference.org/

http://www.socconference.com/

VLSI CAD Journals

IEEE Transactions on CAD of Circuits and Systems

Integration

Transactions on Circuits and Systems

Journal of Circuits, Systems and Computers?

Algorithmica

SIAM journal of Discrete and Applied Mathematics

IEEE Transactions on Computers

VLSI CAD Organizations

ACM SIGDA

Design Automation Technical Committee (DATC) of IEEE Computer Society


Web Sources of Chip

China

http://www.086ic.cn/

http://www.114ic.cn/

http://www.173ic.com/

http://www.21ic.com.cn/

http://www.345ic.com/

http://www.36ic.com/

http://www.883ic.com/

http://www.97ic.com/

http://www.b2bic.com/

http://www.chinaicmart.com/

http://www.chinesechip.com/

http://www.chiplayout.net/

http://www.cpu-cn.com/

http://www.dram.com.cn/

http://www.enet.com.cn/cpu/

http://info.ec.hc360.com/list/zl_jcdl.shtml

http://www.gdicw.com/

http://www.ic.net.cn/

http://www.ic-trade.com/

http://www.ic137.com/

http://www.ic37.com/

http://www.ic5858.com/

http://www.ic72.com/???

http://www.ic918.com/

http://www.icbj.cn/

http://www.icbuy.com/

http://www.iccpp.com.cn/

http://www.iceasy.com/

http://www.icfull.com/

http://www.icgoo.net/

http://www.icjyw.com/

http://www.icmade.com/IC/

http://www.icmai.net/

http://www.icpdf.com/

http://www.icpop.com/

http://www.ictown.com/

http://www.jobic.cn/

http://www.laogu.com/

http://www.mianfeiic.com/

http://www.mmic.net.cn/

http://www.qic.com.cn/

http://www.qooic.com/

http://www.rightic.com/

http://www.seekchip.com/

http://www.xinpian.net.cn/

http://www.zdor.cn/xinpian.html

World / Chip / VLSI

http://www.chipdesignmag.com/

http://www.chiportal.co.il/

http://www.circuitstoday.com/

http://www.coolchips.org/wp/

www.cpu-world.com

http://www.designnews.com/

http://dsp-fpga.com/

http://www.dspguide.com/

http://www.dspguru.com/

http://www.dsprelated.com/

http://www.hotchips.org/

http://www.icdesignnews.com/

http://microcontroller.com/

https://www.semiwiki.com/

http://siliconchip.com.au/

http://www.vlsiencyclopedia.com/2011/12/list-of-vlsi-companies.html

http://www.vlsiguru.in/vlsi.html

http://www.vlsiip.com/


Mathematics

Math is something I can do with pen and paper. I have tried, in vain, over the last couple of years to enter into a research institution to carry out my other,mostlyphysical scientific studies, therefore, without a costly lab and a good team at hands, what I can only do is my math talents.

I arrived at mathematics mainly because without a research position in an university or institution, I am unable to conduct my researches on physical sciences such as thermodynamics, solar physics, fluiddynamics. And also because math is the basic science without a solid foundation one has no chance to carry out real world researches in any other sciences. And I am so busy that I cannot afford to maintain competences both in math and phyusical sciences. There are possibly other reasons why I finally chose math as my research area, either as hobby or as my academic career.

I have tried several areas of math, incl. functional, computation, diffrential equations, number theory, etc - see the list below - and still I am reading some books or papers on these subjects, for graph theory has something to do with all of them. Ｉ finally come to graph theory becasue VLSI is very much related to and dependent on graph theory for its development. Of course graph theory as well as VLSI has much more math to relate to.

I have tried

  • Discrete Mathematics
  • Complexity theory
  • ALGEBRA / Linear Algebra Boolean Algebra / Logic Algebra
  • Category Theory
  • Computer Algorithm / Programming
  • Information Theory
  • Probability Theory
  • (Computational) Geometry
  • COMPUTATION
  • NUMBER THEORY
  • Cryptography
  • Fractal Geometry
  • FUNTIONAL ANALYSIS
  • COMPLEX
  • Calculus
  • Differential Equations
  • ERGODIC THEORY
  • FOURIER ANALYSIS
  • INVARIANT THEORY
  • Laplace Equation
  • Math4GoogleMaps
  • Math4Music
  • Math4Programming
  • Math4SearchEngines
  • Math General

but without any publications yet, and now I am working mainly on graphy theory, combinatorics and all other math related to chip technology. See my other pages of this site.

Refer to the following files for more info:

  • algebra.htm
  • AlgebraBoolean.htm
  • AlgebraTerminology.pdf
  • Algorithm.htm
  • Combinatorics
  • CRYPTOGRAPHY.pdf
  • CRYPTOGRAPHYOldtimes.pdf
  • Calculus.htm
  • Category.htm
  • Complex.htm
  • Complexity.htm
  • Cryptography.htm
  • DifferentialEquations.htm
  • discrete_ref.htm
  • Ergodic.htm
  • Fourier.htm
  • FractalGeometry.htm
  • Functional.htm
  • Geometry.htm
  • Information.htm
  • InvariantTheory.htm
  • LaplaceEquation.htm
  • Manifold.htm
  • Math4Music.htm
  • Math4SearchEngines.htm
  • MathAnalysis.htm
  • MathGeneral.htm
  • MathematicalPhysics.htm
  • model_theory.htm
  • number.htm
  • Number_AKSOutline.pdf
  • Number_Primality.pdf
  • Number_RandomNumber.pdf
  • Number_aks.pdf
  • NumericalComputational.htm
  • NumberTheory.pdf
  • OperationsResearch.htm
  • Probability.htm
  • ProofTheory.htm
  • Topology.htm
  • VectorTensorAnalysis.htm

Literature and Study Notes

math_branches
├<Algebra>
│ ├<Category>
│ │ ├AWODEY Category Theory p328.pdf
│ │ ├Barr Category Theory p133.pdf
│ │ ├Riehl Category theory in context p258.pdf
│ │ └Streicher Introduction to CATEGORY THEORY and CATEGORICAL LOGIC p117.pdf
│ ├<InvariantTheory>
│ │ ├Draisma Invariant Theory with Applications p72.pdf
│ │ └Kraft CLASSICAL INVARIANT THEORY A Primer p129.pdf
│ ├<Linear>
│ │ ├Beezer A First Course in Linear Algebra p980.pdf
│ │ ├Byrne Applied and Computational Linear Algebra A First Course p504.pdf
│ │ ├Cherney Linear Algebra p430.pdf
│ │ ├Dawkins Linear Algebra p331.pdf
│ │ ├Finan Fundamentals of Linear Algebra p196.pdf
│ │ └Hefferon Linear Algebra p449.pdf
│ ├<Manifold>
│ │ └Petersen Manifold Theory p103.pdf
│ ├<ModelTheory>
│ │ ├Dawar Infinite and Finite Model Theory Part II p67.pdf
│ │ ├Libkin Elements of Finite Model Theory p326.pdf
│ │ └Weiss Fundamentals of Model Theory p64.pdf
│ ├<SetTheory>
│ │ ├Andre Axioms and Set Theory p459.pdf
│ │ ├Nesin Foundations of Mathematics I Set Theory p170.pdf
│ │ ├Roitman Introduction to Modern Set Theory p129.pdf
│ │ └Weiss AN INTRODUCTION TO SET THEORY p119.pdf
│ ├<UniversalAlgebra>
│ │ └Burris A Course in Universal Algebra p331.pdf
│ └Wallace Beginning and Intermediate Algebra p489.pdf
├AlgebraTerminology.docx
├<AlgorithmsZZZ>
│ └Dasgupta Algorithms p318.pdf
├<CalculusZZZ>
│ ├Chung Understanding Basic Calculus p292.pdf
│ ├LOOMIS ADVANCED CALCULUS p592.pdf
│ ├Predoi DIFFERENTIAL CALCULUS p279.pdf
│ ├Thompson Calculus Made Easy p292.pdf
│ └Thompson Calculus Made Easy1 p315.pdf
├<ComplexAnalysisZZZ>
│ ├Agarwal An Introduction to Complex Analysis p346.pdf
│ ├Beck Complex Analysis p159.pdf
│ ├Bennewitz COMPLEX ANALYSIS p116.pdf
│ ├Berg Complex Analysis p192.pdf
│ ├Marsden Basic Complex Analysis p519.pdf
│ ├Mathews Complex Analysis for Mathematics and Engineering p528.pdf
│ ├Schlag A concise course in complex analysis and Riemann surfaces p181.pdf
│ └Stein COMPLEX ANALYSIS p398.pdf
├<ComplexityTheory>
│ ├Arora Computational Complexity A Modern Approach p489.pdf
│ ├Gacs Complexity of Algorithms p242.pdf
│ ├Raghavendra Approximating NP-hard Problems Efficient Algorithms and their Limits p314.pdf
│ └Thompson A Complexity Theory for VLSI p106.pdf
├CRYPTOGRAPHY.doc
├CRYPTOGRAPHYOldtimes.doc
├<DifferentialZZZ>
│ ├Chasnov Introduction to Differential Equations p128.pdf
│ ├Miersemann Partial Differential Equations Lecture Notes p205.pdf
│ ├Shen 积分方程 p248.pdf
│ ├Terrell Notes on Differential equations p100.pdf
│ ├Tesch 常微分方程与动力系统 p246.pdf
│ ├Teschl Ordinary Differential Equations and Dynamical Systems p364.pdf
│ └Tracy Lectures on Differential Equations p175.pdf
├<ErgodicTheoryZZZ>
│ ├Dajani A Simple Introduction to Ergodic Theory p145.pdf
│ └Sarig Lecture Notes on Ergodic Theory p137.pdf
├<FourierZZZ>
│ └Gripenberg Fourier Analysis p137.pdf
├<FractalGeometryZZZ>
│ ├Falconer Fractal Geometry p155.pdf
│ └PEARSE AN INTRODUCTION TO DIMENSION THEORY AND FRACTAL GEOMETRY FRACTAL DIMENSIONS AND MEASURES p22.pdf
├<FunctionalZZZ>
│ ├Bass Functional analysis p182.pdf
│ ├Buhler FUNCTIONAL ANALYSIS p375.pdf
│ ├Cannarsa Lecture Notes on Measure Theory and Functional Analysis p216.pdf
│ ├Sunder Functional Analysis Spectral Theory p317.pdf
│ └Teschl Topics in Real and Functional Analysis p177.pdf
├<GeneralZZZ>
│ └Michelsen Funky Mathematical Physics Concepts p193.pdf
├<GeometryZZZ>
│ ├Africk Elementary College Geometry p374.pdf
│ ├Demailly Complex Analytic and Differential Geometry p455.pdf
│ ├Khudaverdian Riemannian Geometry p107.pdf
│ ├Preparata 计算几何导论 p499.pdf
│ └Vince Geometry for Computer Graphics p359.pdf
├<Information_TheoryZZZ>
│ ├Board Foundations and Trends in Communications and Information Theory p116.pdf
│ └Carter An introduction to information theory and entropy p139.pdf
├<LaplaceEquationZZZ>
│ ├Analytic Solutions to Laplace’s Equation in 2-D.pdf
│ ├Laplace equation in a rectangle, Fourier series.pdf
│ ├Laplace's equation Complex variables.pdf
│ ├LAPLACE’S EQUATION IN SPHERICAL COORDINATES.pdf
│ ├Laplace’s Equation, Analytic and Numerical Solution.pdf
│ ├Laplace’s Equation.pdf
│ ├Laplace’s Equation2.pdf
│ ├Laplace’s Equation3.pdf
│ ├Laplace’s Equation4.pdf
│ ├Numerical Solution of Laplace Equation.pdf
│ └The Planar Laplace Equation.pdf
├<MathAnalysisZZZ>
│ ├JOLY Introduction a lanalyse mathematique de la propagation d'ondes en regime harmonique p104.pdf
│ ├Rudin Principles of mathematical analysis p351.pdf
│ ├Trench INTRODUCTION TO REAL ANALYSIS p586.PDF
│ └Zakon Mathematical Analysis p365.pdf
├<MathematicalPhysicsZZZ>
│ ├Agoshkov METHODS FOR SOLVING MATHEMATICAL PHYSICS PROBLEMS p335.pdf
│ ├Avramidi Methods of Mathematical Physics0 p173.pdf
│ ├Avramidi Methods of Mathematical Physics1 p78.pdf
│ ├Govaerts Contemporary Problems in Mathematical Physics p326.pdf
│ ├KRASIL0SHCHIK Homological methods in equations of mathematical physics p149.pdf
│ ├Li 数学物理方程 p267.pdf
│ ├Marsden Lectures on Geometric Methods in Mathematical Physics p134.pdf
│ ├Meusburger Concepts and Methods of Mathematical Physics p142.pdf
│ ├Plenio Mathematical Physics Theory 2003 p133.pdf
│ ├Rybkin Math Physics Lecture Notes p270.pdf
│ ├Stone Mathematics for Physics I p459.pdf
│ ├Stone Mathematics for Physics II p455.pdf
│ └Stone Methods of Mathematical Physics I p316.pdf
├NumberTheory.doc
├<NumberXXX>
│ ├Milne Algebraic Number Theory p164.pdf
│ ├Rademacher Lectures on Analytic Number Theory p283.pdf
│ ├Raji An Introductory Course in Elementary Number Theory p171.pdf
│ ├Shoup Computational Introduction to Number Theory v2 p598.pdf
│ └Stein Elementary Number Theory Primes, Congruences, and Secrets p172.pdf
├Number_aks.docx
├Number_AKSOutline.docx
├Number_Primality.doc
├Number_RandomNumber.doc
├<NumericalZZZ>
│ ├Bastian Numerical Computation of Multiphase Flows in Porous Media p236.pdf
│ ├Benzoni-Gavage Analyse mathematique et numerique de la dynamique des fluides compressibles p114.pdf
│ ├Deturck Lectures on Numerical Analysis p125.pdf
│ ├FEM_FEPG 基于FEPG的有限元方法 p142.pdf
│ ├Feng Boundary Element Methods p501.pdf
│ ├Hoffman Computational Thermodynamics1 p217.pdf
│ ├Huang 数值计算方法及其程序设计 p445.pdf
│ ├KANE ANALYSE MATHéMATIQUE ET SIMULATION NUMéRIQUE DE MODèLES D'éCOULEMENT DE FLUIDES INCOMPRESSIBLES EN SURFACE LIBRE ET MILIEU POREUX DéFORMABLE p119.pdf
│ ├Konstantinov FOUNDATIONS OF NUMERICAL ANALYSIS p278.pdf
│ ├Krafczyk Lattice Boltzmann methods for CFD p183.pdf
│ ├Luo LBM for Two Dimensional Hdrofynamics p183.pdf
│ ├Magnus Analyse numerique 2 p205.pdf
│ ├METIER Modelisation, analyse mathematique et applications numeriques de problemes d'interaction fluid -structure instationnaires p220.pdf
│ ├Quarteroni Numerical Mathematics p669.pdf
│ ├Rung Numerische Methoden der Thermo- und Fluiddynamik p166.pdf
│ ├Scheid 全美经典数值分析第二版 p398.pdf
│ ├Scott Numerical Analysis p341.pdf
│ ├XuDH 偏微分方程数值解法 p441.pdf
│ └Young Introduction to Numerical Methods and Matlab Programming for Engineers p180.pdf
├<Probability>
│ ├Dekking A Modern Introduction to Probability and Statistics Understanding p483.pdf
│ ├Grinstead Introduction to Probability p520.pdf
│ ├Kerns Introduction to Probability and Statistics Using R p412.pdf
│ ├Montgomery Applied Statistics and Probability for Engineers p976.pdf
│ └Soong FUNDAMENTALS OF PROBABILITY AND STATISTICS FOR ENGINEERS p408.pdf
├<ProofTheoryZZZ>
│ ├Buss Lectures on Proof Theory p123.pdf
│ ├Restall proof theory and philosophy p168.pdf
│ └Tait Lectures on Proof Theory p119.pdf
├<Topology>
│ ├Dundas Differential Topology p210.pdf
│ ├Edelsbrunner COMPUTATIONAL TOPOLOGY AN INTRODUCTION p294.pdf
│ ├Guillemin DIFFERENTIAL TOPOLOGY p236.pdf
│ └Renzo Introduction to Topology p118.pdf
└<VectorTensorAnalysisXXX>
├Bowen INTRODUCTION TO VECTORS AND TENSORS p314.pdf
├Brannon Functional and Structured Tensor Analysis for Engineers p323.pdf
├Flügge Tensor Analysis and Continuum Mechanics p214.pdf
├Heinbockel Introduction to Tensor Calculus and Continuum Mechanics p373.pdf
├Marsden Manifolds, Tensor analysis, and Applications p617.pdf
├MARSDEN MATHEMATICAL FOUNDATIONS OF ELASTICITY p576.pdf
├Nelson Tensor analysis p138.pdf
├VANICEK TENSORS p101.pdf
├Yang 张量 p426.pdf
└郭日修 弹性力学与张量分析 p287.pdf

2018-01-052018-01-05


Untitled Document

C/C++ Codes for Graph Representations

C/C++ Codes for Adjacency Matrix

C/C++ Codes for Adjacency List

Java Codes for Graph Representations

Java Codes for Adjacency Matrix
https://code.snipcademy.com/tutorials/data-structures/graphs/adjacency-matrices

Java Codes for Adjacency List

https://code.snipcademy.com/tutorials/data-structures/graphs/adjacency-lists

Python Codes for Graph Representations

Python Codes for Adjacency Matrix

Python Codes for Adjacency Matrix

Python Codes for Adjacency List

Convert Adjacency List To Adjacency Matrix Python


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)
Definitions and Algorithms

Graph representation can have three parts:

  • computer representation (storage) of graphs / representing graphs in a computer
  • graph representation of the physical world
  • visualization / drawing of graphs

In this paper we talk about the first issue, computer representation (storage) of graphs.
The choice of the graph representation is situation specific. It totally depends on the type of operations to be performed and ease of use.

Computer Representation

Aim
To demonstrate how computers represent graphs.
Learning Outcomes
At the end of this section you will:
2 Know a possible way that computers represent graphs,

In a very real sense, data structures are the life blood of most network flow algorithms, and choosing among
alternative data structures can greatly influence the efficiency of an algorithm, both in practice and in theory. Consequently, it is important to have a good understanding of the various available data structures and an idea of how and when to use them.

The performance of a network algorithm depends not only on the algorithm, but also on the manner used to represent the network within a computer and the storage scheme used for maintaining and updating the intermediate results. By representing a network more cleverly and by using improved data structures, we can often improve the running time of an algorithm.

In representing a network, we typically need to store two types of information:

(1) the network topology, that is, the network's node and arc structure; and

(2) data such as costs, capacities, and supplies/demands associated with the network's nodes and arcs.

As we will see, usually the scheme we use to store the network's topology will suggest a natural way for storing the associated node and arc information.

Topics

  • space
  • time for various graph operations and algorithms

[Chu-Carroll 2007]

When you’re writing a graph-based algorithm, choosing which representation – and which variation of which representation – is one of your most important decisions. There’s no cut and dried correct answer: which representation is right is dependent on

  • what you want to do, and
  • what constraints you have.
  • How fast you need things to be;
  • how much memory you can afford to use;
  • how big your graph is; how many edges you graph will have –

all contribute to the choice of the best representation.

[Skiena2008]

Steven Skiena

http://www3.cs.stonybrook.edu/~algorith/files/graph-data-structures.shtml

  • Which algorithms will you be implementing? Certain algorithms are easier on adjacency matrices (such as all-pairs shortest path) and others on adjacency lists (such as most DFS-based algorithms). Adjacency matrices win for algorithms that repeatedly ask, ``Is (i,j) in G?'' However, most graph algorithms can be modified to eliminate such queries.
  • Will you be modifying the graph over the course of your application, and if so, how? Repeated edge insertions and (particularly) deletions argue for adjacency matrices, or perhaps for fancier versions of adjacency lists such as binary search trees. However, more likely than modifying the topology of graph is modifying the attributes of a vertex or edge of the graph, such as size, weight, or color. Attributes are best handled as extra fields in the vertex or edge records of adjacency lists.

Graph Data Structures

If |E| ≈ |V|2 the graph is dense
If |E| ≈ |V| the graph is sparse
If you know you are dealing with dense or sparsegraphs, different data structures may make sense

STINGER

http://www.cc.gatech.edu/stinger

STINGER is a scalable, high performance graph data structure

STINGER (Spatio-Temporal Interaction Networks and Graphs Extensible Representation) is a community developed, high performance, extensible data structure for dynamic graph problems [6].

STINGER [6] is a dynamic graph data structure that exposes large amounts of parallelism, supports fast
updates, and is well-suited to scale-free graphs.

[6] D. A. Bader, J. Berry, A. Amos-Binks, D. Chavarría-Miranda, C. Hastings, K. Madduri, and S. C. Poulos, “STINGER: Spatio-Temporal Interaction Networks and Graphs (STING) Extensible Representation,” Georgia Institute of Technology, Tech. Rep., 2009.

STINGER, the data structure for streaming graphs.

The data structure is based on linked lists of blocks.

The number of vertices and edges can grow over time by adding additional vertex and edge blocks.

Both vertices and edges have types.

A vertex can have edges of multiple types.

Edges incident on a given vertex are stored in a linked list of edge blocks. An edge is represented as a tuple of neighbor vertex ID, integer weight, first timestamp, and
modified timestamp.

All edges in a given block have the same edge type.

The block contains metadata such as the lowest and highest timestamps and the high-water mark of edges within the block.

Parallelism exists at many levels of the data structure.

Each vertex has its own linked list of edge blocks that is accessed from the logical vertex array (LVA). A “for all vertices” loop is parallelized over these lists. Within an edge block, the incident edges can be explored in a parallel loop. The size of the edge block, and therefore the quantity of parallel work to be done, is a user defined parameter. In our experiments, 32 edges in a block is a good selection.

The edge type array (ETA) is a secondary index that points to all edge blocks of a given type. In an algorithm such as connected components, which is edge parallel, this additional mode of access into the data structure permits all edge blocks to be explored in a parallel for loop.

The canonical graph representation

[Codish2013]

The canonical graph representation problem

The canonical graph representation problem is pertinent to a wide range of scientific applications. It is closely related to the graph isomorphism problem, as two graphs are isomorphic if and only if they have the same canonical representation.

pointer-assisted graph representation

[Park2014]

pointer-assisted graph representation

The pointer-assisted graph avoids expensive sorting, rearrangement and search operations which occupy a significant portion of graph computation.

A vertex is represented by a tuple of vertex value (e.g., vertex weight in pagerank), in-edge and out-edge pointers. An in-edge pointer points to an array of in-edge information. Each entry in the array consists of source vertex ID and edge value (e.g., edge weight in pagerank). An out-edge pointer in the vertex data points to an array of out-edge information. Each entry of the array contains destination vertex ID and edge offset (offset in the in-edge array of the destination vertex). Note that each edge has its weight
information only at a single location, in its entry of in-edge array (edge value).

Figure 5 Pointer-assisted graph representation

our proposed pointer-assisted graph representation enables us to access, with low latency, only the required data from the storage without additional expensive data re-arrangement steps.

[AHUJA1993]

Representing Undirected Networks

We can represent undirected networks using the same representations we have just described for directed networks. However, we must remember one fact: Whenever arc (i, j) belongs to an undirected network, we need to include both of the pairs (i,j) and (j, i) in the representations we have discussed. Consequently, we will store each arc (i, j) of an undirected network twice in the adjacency lists, once in the list for node i and once in the list for node j.

Some other obvious modifications are needed.

For example, in the node-arc incidence matrix representation, the column corresponding to arc (i, j) will have + 1 in both rows i and j.

The node-node adjacency matrix will have + 1 in position hij and hji ; for every arc (i, j) ∈ A. Since this matrix will be symmetric, we might as well store half of the matrix.

In the adjacency list representation, the arc (i, j) will be present in the linked lists of both nodes i and j. Consequently, whenever we update information for one arc, we must update it for the other arc as well. We can accomplish this task by storing for each arc the address of its other occurrence in an additional mate array.

The forward star representation requires this additional storage as well. Finally, observe that undirected networks do not require the reverse star representation.

=================

[AHUJA1993]

Comparison of Forward Star and Adjacency List Representations

The major advantage of the forward star representation is its space efficiency. It requires less storage than does the adjacency list representation.

In addition, it is much easier to implement in languages such as FORTRAN that have no natural provisions for using linked lists.

On the other hand, in the forward star representation these steps - add or delete arcs (as well as nodes) - require time proportional to m, which can be too time consuming.

The major advantage of adjacency list representation is its ease of implementation in languages such as Pascal or C that are able to manipulate linked lists efficiently.

Further, using an adjacency list representation, we can add or delete arcs (as well as nodes) in constant time.

comparing

[Kempe2016]

comparing

In comparing the two approaches, we should always take into account which operations we expect to
be performed more frequently. Let us compare which operations are more or less expensive in the two
implementations.

4. We can also compare the memory requirements of the two implementations.

Thus, for sparse graphs, adjacency list are much more economical with space than adjacency matrices,
whereas for dense graphs, it doesn’t really matter too much in terms of memory.

We saw above that each way of storing a graph has its own advantages and disadvantages.

If memory isn’t too big of a concern (it rarely is — computation time is the bottleneck much more often than memory nowadays), one possible approach is to store the entire graph twice internally. When a user queries whether an edge (u, v) exists, we answer it by using the adjacency matrix, while when the user queries all neighbors of a node u, we use adjacency lists.

The downside of this approach (besides using twice as much memory) is that it requires us to execute
each update to the graph twice: once on the adjacency matrix and once on the list. Thus, update operations (such as adding or removing nodes or edges) will take twice as long as before. However, this may well be worth it: for many graphs, updates are much less frequent than queries. For instance, when building a GPS, it is much rarer to have roads or intersections added to a road network than to look for routes between two locations. Similarly, in a social network, users add/remove friends much less frequently than reading their friends’ updates. In those cases, the extra investment in updates is well worth it to have faster responses in queries.

[Ullman2012]

Ullman Foundations of Computer Science CHAPTER 9 The Graph Data Model p78

Jeffrey D. Ullman

http://infolab.stanford.edu/~ullman/

http://infolab.stanford.edu/~ullman/focs.html

http://infolab.stanford.edu/~ullman/focs/ch09.pdf

Comparison of Adjacency Matrices and Adjacency Lists
We tend to prefer adjacency matrices when the graphs are dense, that is, when the
number of arcs is near the maximum possible number, wDense and hich is n2 for a graph of n
sparse graphs nodes. However, if the graph is sparse, that is, if most of the possible arcs are not
present, then the adjacency-list representation may save space. To see why, note
that an adjacency matrix for an n-node graph has n2 bits (provided we represent
TRUE and FALSE by single bits rather than integers as we have done in this section).
In a typical computer, a structure consisting of an integer and a pointer, like our
adjacency list cells, will use 32 bits to represent the integer and 32 bits to represent
the pointer, or 64 bits total. Thus, if the number of arcs is a, we need about 64a
bits for the lists, and 32n bits for the array of n headers. The adjacency list will use
less space than the adjacency matrix if 32n+64a < n2, that is, if a < n2/64 ? n/2.
If n is large, we can neglect the n/2 term and approximate the previous inequality
by a < n2/64, that is, if fewer than 1/64th of the possible arcs are actually present.
More detailed arguments favoring one or the other representation are presented
when we discuss operations on graphs. The following table summarizes the preferred
representations for various operations.
OPERATION DENSE GRAPH SPARSE GRAPH
Look up an arc Adjacency matrix Either
Find successors Either Adjacency lists
Find predecessors Adjacency matrix Either

With adjacency lists, it takes O(1) time to find the header of the adjacency
list for u. We must then traverse this list to the end if v is not there, or half the
way down the list on the average if v is present. If there are a arcs and n nodes in
the graph, then we take time O(1 + a/n) on the average to do the lookup. If a is
no more than a constant factor times n, this quantity is O(1). However, the larger
a is when compared with n, the longer it takes to tell whether an arc is present
using the adjacency list representation. In the extreme case where a is around n2,
its maximum possible value, there are around n nodes on each adjacency list. In
this case, it takes O(n) time on the average to find a given arc. Put another way,
the denser a graph is, the more we prefer the adjacency matrix to adjacency lists,
when we need to look up a given arc.
On the other hand, we often need to find all the successors of a given node
u. Using adjacency lists, we go to successors[u] and traverse the list, in average
time O(a/n), to find all the successors. If a is comparable to n, then we find all the
successors of u in O(1) time. But with adjacency matrices, we must examine the
entire row for node u, taking O(n) time no matter what a is. Thus, for graphs with
a small number of edges per node, adjacency lists are much faster than adjacency
matrices when we need to examine all the successors of a given node.
However, suppose we want to find all the predecessors of a given node v. With
an adjacency matrix, we can examine the column for v; a 1 in the row for u means
that u is a predecessor of v. This examination takes O(n) time. The adjacency-
list representation gives us no help finding predecessors. We must examine the
adjacency list for every node u, to see if that list includes v. Thus, we may examine


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)
Definitions and Algorithms

Graph representation can have three parts:

  • computer representation (storage) of graphs / representing graphs in a computer
  • graph representation of the physical world
  • visualization / drawing of graphs

In this paper we talk about the first issue, computer representation (storage) of graphs.
The choice of the graph representation is situation specific. It totally depends on the type of operations to be performed and ease of use.

Computer Representation

Aim
To demonstrate how computers represent graphs.
Learning Outcomes
At the end of this section you will:
2 Know a possible way that computers represent graphs,

In a very real sense, data structures are the life blood of most network flow algorithms, and choosing among
alternative data structures can greatly influence the efficiency of an algorithm, both in practice and in theory. Consequently, it is important to have a good understanding of the various available data structures and an idea of how and when to use them.

The performance of a network algorithm depends not only on the algorithm, but also on the manner used to represent the network within a computer and the storage scheme used for maintaining and updating the intermediate results. By representing a network more cleverly and by using improved data structures, we can often improve the running time of an algorithm.

In representing a network, we typically need to store two types of information:

(1) the network topology, that is, the network's node and arc structure; and

(2) data such as costs, capacities, and supplies/demands associated with the network's nodes and arcs.

As we will see, usually the scheme we use to store the network's topology will suggest a natural way for storing the associated node and arc information.

Topics

  • space
  • time for various graph operations and algorithms

Graph Data Structures

http://www.geeksforgeeks.org/graph-data-structure-and-algorithms/

https://www.tutorialspoint.com/data_structures_algorithms/graph_data_structure.htm

https://www.topcoder.com/community/data-science/data-science-tutorials/introduction-to-graphs-and-their-data-structures-section-1/

https://en.wikipedia.org/wiki/Graph_(abstract_data_type)

http://blog.benoitvallon.com/data-structures-in-javascript/the-graph-data-structure/

http://www3.cs.stonybrook.edu/~algorith/files/graph-data-structures.shtml

https://www.npmjs.com/package/graph-data-structure

https://medium.freecodecamp.org/a-gentle-introduction-to-data-structures-how-graphs-work-a223d9ef8837

https://en.wikibooks.org/wiki/Data_Structures/Graphs

http://www.algolist.net/Data_structures/Graph

https://github.com/monora/rgl

https://visualgo.net/es/graphds?slide=1

http://doc.sagemath.org/html/en/reference/graphs/sage/graphs/base/overview.html

https://stackoverflow.com/questions/19472530/representing-graphs-data-structure-in-python

http://www.bogotobogo.com/python/python_graph_data_structures.php

http://cba.winthrop.edu/acm/PLDS210/mst.html

https://medium.com/@JonRamer/day-84-graph-data-structures-es6-magic-3cb77ac632ba

https://www.ncbi.nlm.nih.gov/pubmed/24712884

http://www.martinbroadhurst.com/graph-data-structures.html

https://www.tensorflow.org/versions/r0.12/api_docs/python/framework/core_graph_data_structures

https://eschulte.github.io/graph/

https://xlinux.nist.gov/dads/HTML/graph.html

https://hackage.haskell.org/package/fgl

https://softwareengineering.stackexchange.com/questions/228222/graph-data-structures-and-journal-format-for-mini-ide

https://www.codediesel.com/algorithms/building-a-graph-data-structure-in-php/

https://quickgraph.codeplex.com/

https://rdrr.io/bioc/graph/

http://onlinelibrary.wiley.com/doi/10.1002/spe.4380190307/abstract

http://nptel.ac.in/courses/106102064/25

https://www.cs.auckland.ac.nz/software/AlgAnim/graph_rep.html

https://metacpan.org/release/Graph

https://www.interviewcake.com/concept/java/graph

https://www.raywenderlich.com/152046/swift-algorithm-club-graphs-adjacency-list

https://csgeek.wordpress.com/2016/02/19/applications-of-graph-data-structure/

https://www.nuget.org/packages/QuickGraph/3.3.51106

https://community.qlik.com/thread/121087

http://cs.nyu.edu/courses/fall16/CSCI-UA.0102-001/Notes/Graphs.html

https://www.manning.com/books/visualizing-graph-data

http://www.graphviz.org/content/datastruct

http://sc15.supercomputing.org/sites/all/themes/SC15images/tech_poster/tech_poster_pages/post336.html

https://webcms3.cse.unsw.edu.au/COMP9024/17s2/resources/12346

https://www.hackerearth.com/practice/algorithms/graphs/graph-representation/tutorial/

http://smallcultfollowing.com/babysteps/blog/2015/04/06/modeling-graphs-in-rust-using-vector-indices/

https://algorithm.yuanbin.me/zh-tw/basics_data_structure/graph.html

http://ubielife.com/faq-item/advanced-web-graph-data-structure/

https://www.programiz.com/dsa/graph-adjacency-list

http://wwwmayr.in.tum.de/personen/griebsch/xAnVi/plugins/in_tum_simpleHierarchicalGraph/doc/annotated.html

https://www.packtpub.com/mapt/book/application_development/9781787121041/11/ch11lvl1sec59/the-graph-data-structure

https://www8.cs.umu.se/kurser/TDBAfl/VT06/algorithms/BOOK/BOOK2/NODE61.HTM

http://www.dreamincode.net/forums/topic/377473-graph-data-structure-tutorial/

https://answers.ros.org/question/252213/how-to-create-a-graph-data-structure-using-rosmsgs/

https://forum.unity3d.com/threads/ngenerics-and-unity-graph-data-structure-usage.251535/

http://notes.lucida.me/2016/11/03/ds-graph-notes/

https://www.daniweb.com/programming/mobile-development/threads/506810/controlling-graph-data-structure-through-gui

https://meta.wikimedia.org/wiki/Graph_data_structure_extension

http://www.jenitennison.com/2007/09/02/web-2-0-project-using-atom-and-xml-with-graph-data-structures.html

https://www.naukri.com/data-analytics-or-hadoop-or-r-or-graph-data-structures-or-mahout-or-classification-or-clusteringor-mis-jobs-in-pune

http://wrap.warwick.ac.uk/17092/

The canonical graph representation

[Codish2013]

The canonical graph representation problem

The canonical graph representation problem is pertinent to a wide range of scientific applications. It is closely related to the graph isomorphism problem, as two graphs are isomorphic if and only if they have the same canonical representation.

pointer-assisted graph representation

[Park2014]

pointer-assisted graph representation

The pointer-assisted graph avoids expensive sorting, rearrangement and search operations which occupy a significant portion of graph computation.

A vertex is represented by a tuple of vertex value (e.g., vertex weight in pagerank), in-edge and out-edge pointers. An in-edge pointer points to an array of in-edge information. Each entry in the array consists of source vertex ID and edge value (e.g., edge weight in pagerank). An out-edge pointer in the vertex data points to an array of out-edge information. Each entry of the array contains destination vertex ID and edge offset (offset in the in-edge array of the destination vertex). Note that each edge has its weight
information only at a single location, in its entry of in-edge array (edge value).

Figure 5 Pointer-assisted graph representation

our proposed pointer-assisted graph representation enables us to access, with low latency, only the required data from the storage without additional expensive data re-arrangement steps.

matrix

matrix
[Cao2016]

matrix representationof the graph

[Depree2013]

[Yin2004]
[Emms2006]

Adjacency Matrix

[Abiy]

adjacency matrices

We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is n2 for a graph of n nodes.

Adjacency matrices are good for rather dense graphs.

An n-node graph can be represented by an n×n adjacencymatrix A. Ai j is 1 if (i, j) ∈ E and 0 otherwise. Edge insertion or removal and edge querieswork in constant time.

It takes time O(n) to obtain the edges entering or leaving a node. This is only efficient
for very dense graphs with m = W??n2

The storage requirement is n2 bits.

For very dense graphs, this may be better than the n+m+O(1) words required for adjacency
arrays. However, even for dense graphs, the advantage is small if additional edge information is needed.

?We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is for a graph of nodes.

adjacency matrix?

Each cell aij of an adjacency matrix contains 1, if there is an edge between i-th and j-th vertices, and 0 otherwise.

?adjacency matrix is a good solution for dense graphs, which implies having constant number of vertices.

Adjacency matrix is optimal for dense graphs, but for sparse ones it is superfluous.

Advantages.

Adjacency matrix is very convenient to work with. Add (remove) an edge can be done in O(1) time, the same time is required to check, if there is an edge between two vertices.

Also it is very simple to program

Disadvantages.

  • Adjacency matrix consumes huge amount of memory for storing big graphs. All graphs can be divided into two categories, sparse and dense graphs. Sparse ones contain not much edges (number of edges is much less, that square of number of vertices, |E| << |V|2). On the other hand, dense graphs contain number of edges comparable with square of number of vertices.
  • in many algorithms you need to know the edges, adjacent to the current vertex. To draw out such an information from the adjacency matrix you have to scan over the corresponding row, which results in O(|V|) complexity. For the algorithms like DFS or based on it, use of the adjacency matrix results in overall complexity of O(|V|2), while it can be reduced to O(|V| + |E|), when using adjacency list.
  • adjacency matrix requires huge efforts for adding/removing a vertex. In case, a graph is used for analysis only, it is not necessary, but if you want to construct fully dynamic structure, using of adjacency matrix make it quite slow for big graphs.

Adjacency Matrix

Adjacency matrix for undirected graph is always symmetric. Adjacency Matrix is also used to represent weighted graphs. If adj[i][j] = w, then there is an edge from vertex i to vertex j with weight w.

Pros: Representation is easier to implement and follow. Removing an edge takes O(1) time. Queries like whether there is an edge from vertex ‘u’ to vertex ‘v’ are efficient and can be done O(1).

Cons: Consumes more space O(V^2). Even if the graph is sparse(contains less number of edges), it consumes the same space. Adding a vertex is O(V^2) time.

Adjacency Matrix

Adjacency matrix of a digraph need not be symmetric

How much storage does the adjacency matrix require?
?? Answer: O(|V|2)
?? O(|V|) time to find vertex degree and/or vertices adjacent to a given vertex

The adjacency matrix is a dense representation
?? Usually too much storage for large graphs
?? But can be very efficient for small graphs
?? If graph is unweighted, there is an additional advantage in storage for the adjacency matrix presentation; rather than using one word of computer memory for each matrix entry, the adjacency matrix uses only one bit per entry.

[Chen2012]

adjacency matrix

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 1 Matrix: (n) (to go through a binary string of length n)

But the matrix representation of course has its own advantage: To decide if (u; v) 2 E, it only uses O(1) time

If the algorithm uses a lot of random access of edges in G, then the matrix representation may perform better.

canonical adjacency matrix

Weighted Adjacency Matrix
https://reference.wolfram.com/language/ref/WeightedAdjacencyMatrix.html

[Brisaboa2007]

WebGraph Framework, by Boldi and Vigna [6]. It is associated to the site http://webgraph.dsi.unimi.it

compressed graph representations

  • WebGraph compression method
  • Pair compression [18] on the adjacency lists

adjacency matrix of a Web graph

The adjacency matrix of a Web graph of n pages is a square matrix faijg of n ￡ n, where each row and each col- umn represents a Web page. Cell aij is 1 if there is a hy- perlink in page i towards page j, and 0 otherwise.

properties of the adjacency matrix

  • As on average there are about 15 links per Web page, this matrix is extremely sparse.
  • Due to locality of reference, many 1s are placed around the main diagonal (that is, page i has many pointers to pages nearby i).
  • Due to the copy prop- erty, similar rows are common in the matrix.
  • Finally, due to skewness of distribution, some rows and colums have many 1s, but most have very few.
  • regularity properties of the adjacency matrix of the Web graphs, such as
    • horizontal,
    • vertical, and
    • diagonal runs.

clustering of the adjacency matrix

compact tree representation of the matrix

  • compact representation of the adjacency matrix that exploits its sparseness and clustering properties.
  • The representation is designed to compress large matrix ar- eas with all 0s into very few bits.
  • the technique offers a relevant space/time tradeoff to represent Web graphs, that is, it is much faster than those that take less space, and much smaller than those that o?er faster navigation.
    Furthermore, we show that our representation allows for other queries on the graph not usually considered in com pressed graph representations.
  • very e±cient to represent large empty areas of the matrix,
  • but at the same time allows e±cient forward and backward navigation of the graph.
  • An elegant feature of our solution is that it is symmetric, in the sense that forward and backward navigation are carried out by similar means and achieve similar times.
  • We represent the whole adjacency matrix via the k2-tree using two bit arrays we call T (tree) and L (leaves):
    • T: This bit array stores all the bits of the k2-tree except those in the last level. The bits of the k2-tree are placed following a levelwise traversal of the tree. We will represent ˉrst the k2 binary values of the children of the root node, then the values of the second level, and so on.
    • L: This bit array stores the last level of the tree. Thus it represents the value of (some) original cells of the adjacency matrix.
  • We represent the adjacency matrix by a k2-ary tree, which we call k2-tree, of height h = dlogk ne. Each node contains a single bit of data: 1 for the internal nodes and 0 for the leaves, except for the last level of the tree, where all are leaves and represent some bit values of the matrix. corresponds to the root; its k2 children are represented at level 1. Each child is a node and therefore it has a value 0 or 1. All internal nodes in the tree (i.e., with value 1) have exactly k2 children, whereas leaves (with value 0 or at the last tree level) have no children.
  • Assume for simplicity that n is a power of k; we will soon remove this assumption.
  • Conceptually, we start dividing the adjacency matrix into k2 submatrices of the same size, that
    is, k rows and k columns of submatrices of size n2=k2.
  • Each of the resulting k2 submatrices will be a child of the root node and its value will be 1 i? in the cells of the submatrix there is at least one 1. A 0 child means that the submatrix has all 0s and therefore the tree decomposition ends there; thus 0s are leaves in our tree.
  • The children of a node are ordered in the tree starting with the submatrices in the ˉrst (top) row, from left to right, then the submatrices in the second row from left to right, and so on.
  • Once the level 1 of the tree, with the children of root, has been built, the method proceeds recursively for each child with value 1, until we reach submatrices full of 0s, or we reach the cells of the original adjacency matrix. In the last level of the tree, the bits of the nodes correspond
    to the matrix cell values.
  • Figure 1 illustrates a 22-tree for a 4 ￡ 4 matrix.
  • A larger k induces a shorter tree, with fewer levels, but with more children per internal node.
  • If n is not a power of k, we conceptually extend our matrix to the right and to the bottom with 0s, making it of width n0 = kdlogk ne. This does not cause a signiˉcant overhead as our technique is e±cient to handle large areas of 0s.
  • Figure 2 shows an example of the adjacency matrix of a Web graph (we use the ˉrst 11￡11 submatrix of graph CNR [6]), and how it is expanded to an n0 ￡ n0 matrix for n0 a power of k = 2 (at the left) and of k = 4 (at the right). The ˉgure also shows the trees corresponding to those k values. Notice that the last level of the tree represents cells in the original adjacency matrix, but most empty cells in the original adjacency matrix are not represented in this level because, where a large area with 0s is found, it is represented by a single 0 in a smaller level of the tree.

Navigating with a k2tree

To obtain the pages pointed by a speciˉc page p, that is, to ˉnd direct neighbors of page p, we need to ˉnd the 1s in row p of the matrix. We start at the root and travel down the tree, choosing exactly k children of each node. We start with an example and then generalize in the next section.

[Codish2013]

canonical adjacency matrix

[Cormen2014]

Adjacency matrices

For finding the neighbours of vertex v:

Adjacency Matrix: O(|V|)
You need to check the the row for v, (which has |V| columns) to find which ones are neighbours

If you represent your adjacency matrix as a hash table, you can get very good lookup times without using n^2 memory.

[Cornell2011]

adjacency matrix

Another common representation is an adjacency matrix, which is a two-dimensional array, where Ai j is non-zero when there is an edge (vi, vj) ∈ E.

[Depree2013]

Adjacency Matrix

O(n) time to find vertex degree and/or vertices adjacent to a given vertex.

Cost adjacency matrix. C(i,j) = cost of edge (i,j)

[Grama2003]

Adjacency matrices

Adjacency matrices have a value ai;j = 1 if nodes i and j share an edge; 0 otherwise. In case of a weighted graph, ai;j = wi;j, the weight of the edge.

[Huan2005]

Canonical adjacency matrix

Canonical adjacency matrix of labeled graphs
We represent each graph by an adjacency matrix M such that every diagonal entry of M is filled with the
label of the corresponding node and every off-diagonal entry is filled with the label of the corresponding
edge, or zero if there is no edge. This is slightly different from the standard adjacency matrix representation for unlabeled graphs (Cormen et al., 2001).

[Lenharth2014]

Adjacency matrix
Adjacency Matrix -- operations
Easy
?Iterate nodes
?Edges by src
?Edges by dst
?Loopup by src, dst
?Add Edge
?Delete edge
Hard
?Add node
?Delete node

Adjacency Matrix -- Costs
?Lookups: O(1)
?Iterations: array iteration
?Edge addition: O(1)
?Edge removal: O(1)
?Space: O(N^2)
–Good for dense graphs

[Sommer2010]

Adjacency matrix

For instance, a matrix wastes a lot of memory if a sparse graph is given, but it has optimal access times for any type of graph.

[stoimen2012]

Adjacency Matrix

In case of directed graph, we can use 1 for the edge (i,j) and -1 for (j,i) in case the edge is directed from i to j. For a weighted directed graph we can put the weights instead of 1s.

In case that we’re using adjacency matrix we have:

  1. Adding an edge – O(1);
  2. Deleting an edge – O(1);
  3. Answering the question “is there an edge between i and j” – O(1);
  4. Finding the successors of a given vertex – O(n);
  5. Finding (if exists) a path between two vertices – O(n2);

[suanfazu2015]

matrix
A matrix is just a simple 2 dimensional array. Assuming you have vertex ID's that can be represented as an int array like this:

int[][] adjacencyMatrix = new int[SIZE][SIZE];
// SIZE is the number of vertices in our graph
adjacencyMatrix[0][1] = 30;
// sets the weight of a vertex 0 that is adjacent to vertex 1

This is commonly used for dense graphs where index access is necessary. You can represent a un/directed and weighted structure with this.

[Wang2012]

adjacency matrix

The adjacency matrix is an n  n matrix where the non-diagonal entry aij is the weight value from vertex i to vertex j, and the diagonal entry aii can be used to count loops on single vertices. For most large-scale
graphs, the resulting matrix is typically sparse; representing it directly as a sparse matrix allows the use of existing libraries for sparse matrix operations such as cuSparse. Katz et al.11 represent the adjacency matrix as a 2D texture in GPU memory. The downside of such a representation is its waste of space.

[Zanibbi2009]

Adjacency Matrix

Checking if (u, v) is an edge takes Θ(1) time.
Identifying all edges takes Θ(n2) time.

incidence matrix

[Gotshalks2008]
[Gross2003]

[Rocca2006]

[Claude2007]

incidence matrix

Standard graph representations such as the incidence matrix require n(n? 1)/2 bits, for undirected graphs. For directed graphs the numbers are n2 .

Kirchhoff Matrix

https://reference.wolfram.com/language/ref/KirchhoffMatrix.html

Laplacian matrix
[Emms2006]

[Cao2016]

PPMI matrix

the original PPMI matrix itself is an explicit representation matrix of the graph

pointwise mutual information (PMI) matrix

positive pointwise mutual information (PPMI) matrix

matrix R representing the vertices of graph G by capturing deep structural information.

co-occurrence matrix / collections of linear sequences / via DeepWalk

DeepWalk proposed by Perozzi et al. (2014) presented an idea to transform unweighted
graphs into collections of linear sequences by a uniform sampling method known as truncated random walk.

DeepWalk (Perozzi, Al-Rfou, and Skiena 2014) is a recently proposed method to learn representations of networks. It transforms a graph structure into linear sequences by truncated random walks and processes the sequences using skip-gram with hierarchical softmax.

In their approach, sampled vertex sequences characterize the connections between vertices in a graph. This step can be understood as a process for converting a general graph structure into a large collection of linear structures.

Next, they utilized the skip-gram model proposed by Mikolov et al. (2013) to learn low-dimensional representations for vertices from such linear structures. The learned vertex representations were shown to be effective across a few tasks, outperforming several previous approaches such as spectral clustering and modularity method (Tang and Liu 2009a; 2009b; 2011; Macskassy and Provost 2003).

DeepWalk yields a co-occurrence matrix based on the sampled linear sequences.

probabilistic co-occurrence matrix

In Section 3, we describe our random surfing model that directly construct a probabilistic co-occurrence matrix from a weighted graph, which avoids the expensive sampling process.

random surfing model suitable for weighted graphs, which can directly yield a probabilistic
co-occurrence matrix. Such a matrix is similar to the cooccurrence matrix obtained by sampling linear sequences from graphs (Bullinaria and Levy 2007), but no sampling process is required in our approach.

Representing graphs with orthogonal matrices

[Emms2006]

Flat Sparse Matrix

[Slesarenko2015]

Lists

Adjacency Lists

[Abiy]

Adjacency List

hashtable with an array

hashtable with linked lists

A common way to implement a graph using an adjacency list is to use either a hashtable with an array as values or use a hashtable with linked lists as a value. Since python combines the idea of arrays and linked lists we can easily implement this representation using a dictionary with nodes as keys and a list as a value.

However if the graphs is sparse, that is if most of the possible edges are not present, then the adjacency-list representation can save space.

To see why, note that an adjacency matrix for an n node graph has n2 bits, and therefore could be packed into n2/32-bit words. The common adjacency list cell will consist of two words, one for the node and one for the pointer to the next cell. Thus, if the number of edges is a , we need about 2a words for the lists, and n words for the array of headers. The adjacency list will use less space than the adjacency matrix if

n+2a<n2/32

The following table summarizes the preferred representation for various operations:

operations | dense graph | sparse graph
lookup edge | adjacency matrix | either
find successor | either | adjacency list
find predeccessor | adjacency matrix | either

Let us assume the graph is represented by adjacency lists, so we can find all edges in O(m) time.

Adjacency lists are good if the graph changes frequently

Adjacency lists for sparse graphs should be implemented without the dummy item introduced in Sect. 3.1, because an additional item would waste considerable space.

The second solution has only one item for each undirected edge (or pair of directed edges) and makes this item a member of two adjacency lists. So, the item for an undirected edge {u,v} would be a member of lists Eu and Ev. If we want doubly linked adjacency information, the edge object for any edge {u,v} stores four pointers: two are used for the doubly linked list representing Eu, and two are used for the
doubly linked list representing Ev. Any node stores a pointer to some edge incident on it. Starting from it, all edges incident on the node can be traversed. The bottom part of Fig. 8.1 gives an example. A small complication lies in the fact that finding the other end of an edge now requires some work. Note that the edge object for an edge {u,v} stores the endpoints in no particular order. Hence, when we explore the
edges out of a node u, we must inspect both endpoints and then choose the one which is different from u. An elegant alternative is to store u⊕v in the edge object [145]. An exclusive OR with either endpoint then yields the other endpoint. Also, this representation saves space.

A common way to implement a graph using an adjacency list is to use either a hashtable with an array as values or use a hashtable with linked lists as a value. Since python combines the idea of arrays and linked lists we can easily implement this representation using a dictionary with nodes as keys and a list as a value.

However if the graphs is sparse, that is if most of the possible edges are not present, then the adjacency-list representation can save space.

adjacency list

For every vertex adjacency list stores a list of vertices, which are adjacent to current one.

It requires less amount of memory

To sum up, adjacency list is a good solution for sparse graphs and lets us changing number of vertices more efficiently, than if using an adjacent matrix. But still there are better solutions to store fully dynamic graphs.

Advantages.

Adjacent list allows us to store graph in more compact form, than adjacency matrix, but the difference decreasing as a graph becomes denser.

Next advantage is that adjacent list allows to get the list of adjacent vertices in O(1) time, which is a big advantage for some algorithms.

Disadvantages.

  • Adding/removing an edge to/from adjacent list is not so easy as for adjacency matrix. It requires, on the average, O(|E| / |V|) time, which may result in cubical complexity for dense graphs to add all edges.
  • Check, if there is an edge between two vertices can be done in O(|E| / |V|) when list of adjacent vertices is unordered or O(log2(|E| / |V|)) when it is sorted. This operation stays quite cheap.
  • Adjacent list doesn't allow us to make an efficient implementation, if dynamically change of vertices number is required. Adding new vertex can be done in O(V), but removal results in O(E) complexity.

Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to theith vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to theith vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).

Adjacency Lists

Most large interesting graphs are sparse ?? For this reason the adjacency list is often a more appropriate representation

Each adjacency list is a chain.

# of chain nodes = 2|E| (undirected graph)
# of chain nodes = |E| (digraph)

How much storage is required?
?? The degree of a vertex v = # incident edges
??Directed graphs have in-degree and out-degree
?? For directed graphs:
?? # of items in adjacency lists is Σ out-degree(v) = |E|
??takes Θ(V + E) storage (Why?)
?? For undirected graphs:
??# items in adjacency lists is Σ degree(v) = 2|E|
??also Θ(V + E) storage
?? So: Adjacency lists take O(V + E) storage

[Chen2012]

adjacency-list

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 2 List: linear in the length of Adj(u) (or equivalently, deg(u) if G is undirected, and out-deg(u) if G is directed)

To decide if (u; v) 2 E, the list representation has worst-case running time linear in the length of Adj(u) (why?).

If the input graphs are sparse and we make a lot of enumerations of edges incident to a vertex in our algorithm, then the list representation usually ts better.

[Claude2007]

adjacency lists

Re-Pair [19] to compress the adjacency lists

Standard graph representations such as the adjacency list require 2e log n bits, for undirected graphs. For directed graphs the numbers are e log n.

Cormen2014

Adjacency lists

Representing a graph with adjacency lists combines adjacency matrices with edge lists

It is true that in the general case that storage of an adjacency list is O(|V|+|E|).
This is the same as O( max( |V|, |E| ) )
Which means that you at least need to allocate space for the pointer to each vertices list.
In most practical cases |E| will larger than |V| (even for a minimally connected graph i.e. a tree, E = V-1). Which means for most practical cases the space required is simply O(|E|).

We can get to each vertex's adjacency list in constant time, because we just have to index into an array. To find out whether an edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis is present in the graph, we go to i i ii 's adjacency list in constant time and then look for j j jj in i i ii 's adjacency list. How long does that take in the worst case? The answer is Θ(d) \Theta(d) Θ(d) , where d d dd is the degree of vertex i i ii , because that's how long i i ii 's adjacency list is. The degree of vertex i i ii could be as high as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 (if i i ii is adjacent to all the other ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices) or as low as 0 (if i i ii is isolated, with no incident edges). In an undirected graph, vertex j j jj is in vertex i i ii 's adjacency list if and only if i i ii is in j j jj 's adjacency list. If the graph is weighted, then each item in each adjacency list is either a two-item array or an object, giving the vertex number and the edge weight.

How much space do adjacency lists take? We have ∣V∣ |V| ∣V∣vertical bar, V, vertical bar lists, and although each list could have as many as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices, in total the adjacency lists for an undirected graph contain 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar elements. Why 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar ? Each edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis appears exactly twice in the adjacency lists, once in i i ii 's list and once in j j jj 's list, and there are ∣E∣ |E| ∣E∣vertical bar, E, vertical bar edges. For a directed graph, the adjacency lists contain a total of ∣E∣ |E| ∣E∣vertical bar, E, vertical bar elements, one element per directed edge.

Agreed, if the list of neighbors is implemented as an array, and that array is sorted then determining membership is Θ(log(d)), using binary search.

However, if the array is unsorted, or if the list of neighbors is implemented as a linked list (both are typical implementations) then determining membership is Θ(d), as we need to look at every item in the list before deciding that something is not in the list.

In the article they mention "Vertex numbers in an adjacency list are not required to appear in any particular order", which implies the analysis is with regards to unsorted implementations.

Whether you would want to use a sorted version or not would depend on your application. You might get the sorting for free (i.e. if your method of constructing your graph leads to naturally sorted adjacency lists), or you might have to pay an additional cost in sorting the adjacency lists. Whether the cost outweighs the benefits depends on your application.

For finding the neighbours of vertex v:

Adjacency List: O(|N|)
where N is the number of neighbours of v
You need to iterate through the list for the vertex v, which has N neighbours
v could have up to V-1 neighbours, so we could also say it is O(|V|)

how is adjacency list space Θ(V + E)?

The adjacency list contains:
-1 array per vertex, for a total of V arrays (we are only considering the space for the array pointer, not the contents of the array).
-Each directed edge is contained once somewhere in the adjacency list, for a total of E edges (a bidirectional edge is just 2 directed edges, so if we are using bidirectional edges it would just be 2E ).

V+E is Θ(V + E)

[Cornell2011]

adjacency list

Directed graphs are commonly represented as an adjacency list, which comprises an array or list of vertices, where each vertex vi stores a list of all the vertices vj for which there is an edge (vi, vj) ∈ E.

In practice, many graphs are sparse in the sense that most of the possible edges between pairs of vertices do not exist, i.e. m << n2. In such cases the adjacency list is generally preferable to the adjacency matrix representation.

In that implementation, a graph is represented as a pair consisting of the number of vertices and a list of vertices. A vertex is represented as a triple of a unique integer id, an outgoing list, and an incoming list. The outgoing list is a list of pairs of destination vertex and weight. The incoming vertex list is a list of pairs of source vertex and weight. Note that as each edge is stored twice, in the incoming list of its destination and the outgoing list of its source, the weight must be consistent in the two lists.

In that implementation, an edge is a triple of a source vertex, destination vertex and weight, and is constructed on the fly as needed from the vertex out lists rather than being explicitly stored in the data structure.

[Depree2013]

Linked Adjacency Lists

Array Adjacency Lists

adjacency multilist representation

[Grama2003]

adjacency list

The adjacency list representation of a graph G = (V;E) consists of an array Adj[1::jV j] of lists. Each list Adj[v] is a list of all vertices adjacent to v.

[Gross2003]

ADJACENCY LIST REPRESENTATION

def: An adjacency list for a vertex v of a graph G is a list containing each vertex w of G
once for each edge between v and w.
def: An adjacency list representation of a graph is a table of all the adjacency lists.

[Lenharth2014]

Adjacency lists

?Nodes stored in array as pointers to linked lists
?Edges stored as linked list at src
?Fundamentally directed

Adjacency Lists – Operations
Easy
?Iterate nodes
?Edges by src
?Add Edge
?Delete edge
?Add node?
Hard
?Edges by dst
?Loopup by src, dst
–Linear seach
?Delete node

Adjacency Lists – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Linked List iteration
–Expensive due to indirection
–not cache friendly
?Edge addition: O(1)
–Except involves an allocation
?Edge removal: O(E)
?Space: O(N + E)
–Constant for E == sizeof(ptr) + sizeof(Edata) + sizeof(int)

[Wang2012]

adjacency lists

adjacency lists provide more compact storage for more widespread sparse graphs.

A basic adjacency list stores all edges in a graph.

One typical way of implementing it is using one array to store a list of neighbor nodes and another array to store the offset of the neighbor list for each node.

Merrill et al.12 use the well-known compressed sparse row (CSR) sparse matrix format to represent graphs in their BFS implementation.
The column-indices array C and row-offsets array R are equivalent to the neighbor nodes list and the offset list in the basic adjacency list de nition. This representation enables them to use parallel primitives such as pre x sum to reorganize sparse and uneven workloads into dense and uniform ones in all phases of graph processing. In the context of parallel BFS, parallel threads use pre x sum when assembling global edge frontiers from expanded neighbors and when outputting unique unvisited vertices into global vertex frontiers.

Jia et al.10 represent the graph as an edge list to better assign edges to threads in their centrality algorithm. Instead of using two unequal length arrays|an o set array and a neighbor list array|they use two even length arrays to store the vertex pair for each edge. Their edge-centric representation requires more GPU memory though, which could limit their application to larger graphs.

[Zanibbi2009]

Adjacency List

Node indexed array of lists.
Two representations of each edge.
Space proportional to m + n.
Checking if (u, v) is an edge takes O(deg(u)) time.
Identifying all edges takes Θ(m + n) time.

degree = number of neighbors of u

Linked Adjacency Lists

Linked Adjacency Lists

[Depree2013][Depree2013]

Each adjacency list is a chain.

Array Length = n
# of chain nodes = 2e (undirected graph)
# of chain nodes = e (digraph)

Array Adjacency Lists

Array Adjacency Lists

[Depree2013]

Each adjacency list is an array list.

Array Length = n
# of list elements = 2e (undirected graph)
# of list elements = e (digraph)

Adjacency lists => each list element is a pair (adjacent vertex, edge weight)

?

[Madduri2008] [Madduri2009]

adjacency lists using adjacency arrays

For representing sparse static graphs, adjacency lists implemented using cache-friendly adjacency arrays are shown to give substantial performance improvements over linkedlist and adjacency matrix representations for sparse graphs [22].

(adjacency lists using) dynamic, resizable adjacency arrays

Dynamic Arrays (Dyn-arr). We can extend the static graph representation and use dynamic, resizable adjacency arrays for processing insertions and deletions. Clearly, this would support fast insertions. For inserting a new edge hu; vi, we resize the adjacency array of u if needed, and place v at the end of the array. The count can be incremented using an atomic increment operation on modern hardware,
and so this representation supports lock-free, non-blocking insertions.

There are two potential parallel performance issues with this data structure. Edge deletions are expensive in this representation, as we may have to scan the entire adjacency list in the worst case to locate the required tuple. Note that a scan is reasonable for low-degree vertices (say, less than 10 adjacencies), given the spatial locality we have due to the contiguous adjacency representation. However,
due to the power-law degree distributions in small-world networks, we may encounter several high-degree vertices in the graph, and deletions for these vertices would necessitate O(n) additional work.

linkedlist

[Opendatastructures]

  • What type of collection should be used to store each element of [image]? One could use an array-based list, a linked-list, or even a hashtable.
  • Should there be a second adjacency list, [image], that stores, for each [image], the list of vertices, [image], such that [image]? This can greatly reduce the running-time of the [image] operation, but requires slightly more work when adding or removing edges.
  • Should the entry for the edge [image] in [image] be linked by a reference to the corresponding entry in [image]?
  • Should edges be first-class objects with their own associated data? In this way, [image] would contain lists of edges rather than lists of vertices (integers).

[Slesarenko2015]

Flat Adjacency List

[Sommer2010]

Adjacency List

Likewise, this is an ecient way to represent a graph but the access times are slower compared to a matrix (O(lg n) compared to O(1)). One way to solve this issue is to use a hash table for each node, containing all its neighbors.

[stoimen2012]

Adjacency Lists

While for an adjacency list we can have:

  1. Adding an edge – O(log(n));
  2. Deleting an edge – O(log(n));
  3. Answering the question “is there an edge between i and j” – O(log(n));
  4. Finding the successors of a given vertex – O(k), where “k” is the length of the lists containing the successors of i;
  5. Finding (if exists) a path between two vertices – O(n+m) – where m <= n;

Blelloch2012

Adjacency list

An array A of length n where each entry A[i] contains a pointer to a linked list of all the out-neighbors of vertex i. In an undirected graph with edge fu, vg the edge will appear in the adjacency list for both u and v.

[suanfazu2015]

adjacency list
This is just a simple datastructure mix, I usually implement this using a HashMap<Vertex, List<Vertex>>. Similar used can be the HashMultimap in Guava.
This approach is cool, because you have O(1) (amortized) vertex lookup and it returns me a list of all adjacent vertices to this particular vertex I demanded.

ArrayList<Vertex> list = new ArrayList<>();
list.add(new Vertex(2));
list.add(new Vertex(3));
map.put(new Vertex(1), list); // vertex 1 is adjacent to 2 and 3

This is used for representing sparse graphs, if you are applying at Google, you should know that the webgraph is sparse. You can deal with them in a more scalable way using a BigTable1.

adjacency multilist

incidence list

[Rocca2006]

Edge lists

edge list

[Gotshalks2008]

[Grama2003]

[Lenharth2014]
[Sommer2010]

[Tangwongsan2012]

Cormen2014

Edge lists

For finding the neighbours of vertex v:
Edge List: O(|E|)
If the list is unsorted you need to check every edge to see if it comes from v
For a complete graph (where every vertex is connected to all other vertices) this would be O(|V|^2)

How can you organize an edge list to make searching for a particular edge take O(lgE) time? The answer is a little tricky.

Sort the list by the 1st vertex in each edge, and then by 2nd vertex in each edge.
The list is sorted, so we can now use a binary search on it.
Our comparison is a little bit more complicated now.
[v1,v2] < [v3,v4] if (v1 < v3) OR ( (v1 === v3) AND v2 < v4 )

If we have an edge [v1,v2] we do a binary search for [v1,v2] on the list. Time O(log E)

If your edges are not directed i.e. [v1,v2] is equivalent to [v2,v1] then perform a second search on the equivalent edge [v2,v1] if your first search wasn't successful. Double O(log E) is still O(log E).

[Lenharth2014]

Edge List

?Think of Edges not Nodes as primary
?Array of Edges (src,dst,data)
–May be sorted by src or dst
?Array of Node data
?May not be able to iterate edges by node
?Easy global iteration over edges

Compressed Edge lists
?Rather than storing integer indexes or pointers, store compressed data stream
?Decompress as iterating over edges
?E.g. Delta-encoding
–Each edge is stored as the delta from the previous edge
?1,4,7,9 -> 1,3,3,2
–Use fewer bytes for each edge (variable length encoding)

[Sommer2010]

Edge List

While being a space-ecient way to store the graph, the access times of an edge list are slower than the access times of an adjacency matrix (for most edges).

vertex list

[Grama2003]

[Grama2003]

VertexList

linkedlist

[Madduri2009]

linked list

In Chap. 3, we learned how to implement dynamic sequences. We can use any of the solutions presented there to produce a dynamic graph data structure. For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

Linked lists allow constant-time insertion and deletion of edges at arbitrary positions.

In the example in Fig. 8.1, we show circularly linked lists.

vectors

vector representation
[Cao2016]

vector representation for each vertex

[Cao2016]

vector representation / vertex representations of a unweighted graph

a model for learning graph representations, which generates a low-dimensional vector representation for each vertex by capturing the graph structural information.

One of effective means towards organizing such information associated with the potentially large and complex graph is to learn the graph representations, which assign to each vertex of the graph a low-dimensional dense vector representation, encoding meaningful information conveyed by the graph.

v-graph (vector graph)

[Wang2012]

v-graph (vector graph)

Blelloch3 proposes the v-graph (vector graph) for graph data representa- tion. This representation uses segmented vectors to store graph topology. For undirected graphs, it uses a single segmented vector to store edge information. Each segment corresponds to a vertex and each element within a segment corresponds to one of the edges of that vertex. For directed graphs, it uses two segmented vectors: one for the incoming edges, and one for the outgoing edges. Each element in the outgoing edges vector is a pointer to a position in the incoming edges vector. For both directed and undirected graphs, the representation uses additional vectors to include weights and other information. A graph can be con-
verted from most other representations into the v-graph representation by creating two elements per edge (one for each end) and sorting the edges according to their vertex number. Parallel sorting algorithms such
as radix sort can be used to place all edges that belong to the same vertex in a contiguous segment. The cross-pointer array in this representation enables an O(1) step complexity of dynamic graph manipulations such as adding or deleting an edge or a vertex, which is not easily accomplished with the other representations.

Adjacency vectors

[Lenharth2014]

Adjacency vectors
?Replace Linked List with pointer to vector
–Resizable vector?
?Costs?
?Advantages?

set

adjacency set representation for unweighted graphs

associate a value with each out edge of a vertex

adjacency set representation for unweighted graphs

associate a value with each out edge of a vertex

associate each vertex with a table that maps each out-neighbor to its value

It would have type:
(eVal vertexTable) vertexTable .
The graph above would then be represented as:
G = f0 7! f1 7! 0.7, 2 7! 1.5g , 1 7! f2 7! ??2.0g , 2 7! fgg

Blelloch2012

edge set representation

The representation is similar to an edge list representation mentioned before, but it abstracts away from the particular data structure used for the set—the set could be based on a list, an array, a tree, or a hash table.

If we use the balanced-tree cost model for sets, for example, then determining if an edge is in the graph requires much less work than with an edge list— only O(log n) instead of (n) (i.e. following the list until the edge is found). The problem with edge sets, as with edge lists, is that they do not allow for an efficient way to access the neighbors of a given vertex v. Selecting the neighbors requires considering all the edges and picking out the ones that have v as an endpoint. Although with an edge set (but not an edge list) this can be done in parallel with O(logm) span, it requires (m) work even if the vertex has only a few neighbors.

array

Adjacency array
[Tangwongsan2012]

NodeArray and EdgeArray to indicate array-like data structures that can be indexed by nodes and by edges, respectively

To support easy access to the edges leaving any particular node, we can store the edges leaving any node in an array. If no additional information is stored with the edges, this array will just contain the indices of the target nodes. If the graph is static, i.e., does not change over time, we can concatenate all these little arrays into a single edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an example.edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an xample.

Adjacency array representations can be generalized to store additional information: we may store information associated with edges in separate arrays or within the edge array. If we also need incoming edges, we may use additional arrays V′ and E′ to store the reversed graph.

The memory consumption for storing a directed graph using adjacency arrays is n+m+Q(1) words.

Very often, some variant of adjacency arrays is fastest. This may be true even if the graph changes, because often there are only a few changes, or all changes happen in an initialization phase of a graph algorithm, or changes can be agglomerated into occasional rebuildings of the graph, or changes can be simulated by building several related graphs.

There are many variants of the adjacency array representation.

Information associated with nodes and edges may be stored together with these objects or in separate
arrays. A rule of thumb is that information that is frequently accessed should be stored with the nodes and edges. Rarely used data should be kept in separate arrays, because otherwise it would often be moved to the cache without being used. However, there can be other,more complicated reasons why separate arrays may be faster. For example, if both adjacency information and edge weights are read but only the
weights are changed, then separate arrays may be faster because the amount of data written back to the main memory is reduced.

Blelloch2012

Adjacency array

Similar to an adjacency list, an adjacency array keeps the neighbors of all vertices, one after another, in an array adj; and separately, keeps an array of indices that tell us where in the adj array to look for the neighbors of each vertex.

Dynamic Arrays
[Madduri2009]

Unbounded arrays

Unbounded arrays are more cache-efficient.

sequence

[8]

Edge Sequences

The edge sequence representation is good only in specialized situations.

In Chap. 3, we learned how to implement dynamic sequences. We can use any of the solutions presented there to produce a dynamic graph data structure. For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

[8]

Unordered Edge Sequences

Perhaps the simplest representation of a graph is as an unordered sequence of edges. Each edge contains a pair of node indices and, possibly, associated information such as an edge weight.Whether these node pairs represent directed or undirected edges is merely a matter of interpretation.

Sequence representation is often used for input and output.

It is easy to add edges or nodes in constant time.

However, many other operations, in particular navigation, take time theta(m), which is forbiddingly slow.

Only a few graph algorithms work well with the edge sequence representation;

most algorithms require easy access to the edges incident on any given node. In this case the ordered representations discussed in the following sections are appropriate.

This is even more compact than the 2m words needed for an edge sequence representation.

Edge arrays are a compact and efficient graph representation.

Their main disadvantage is that it is expensive to add or remove edges. For example, assume that we want to insert a new edge (u,v). Even if there is room in the edge array E to accommodate it, we still have to move the edges associated with nodes u+1 to n one position to the right, which takes time O(m).

[8]

ordered edge sequence representation

[Cao2016]

linear sequences

Although effective, the sampling method for transforming a graph structure into linear sequences has some weaknesses.

TABLE
store node or edge information in a hash table.

INCIDENCE TABLE REPRESENTATION

[Gross2003]

[Gross2003]

INCIDENCE TABLE REPRESENTATION

An incidence table for a graph has a column indexed by each edge. The entries in the column for an edge are its endpoints. If the edge is a self-loop, then the endpoint appears twice.

edge-set table / adjacency table

Blelloch2012

More efficient neighbor access. In our second representation, we aim to get more efficiency in accessing to the neighbors of a vertex. This representation, which we refer to as an adjacency table, is a table that maps every vertex to the set of its neighbors. Simply put, it is an edge-set table.

Therefore, in this representation, accessing the neighbors of a vertex v is cheap: it just requires a lookup in the table. Assuming the balanced-tree cost model for tables, this can be done in O(log n) work and span. Once the neighbor set has been pulled out, mapping a constant work function over the neighbors can be done in O(dG(v)) work and O(1) span. Looking up if an edge is in the graph requires the same work and span as with edge sets: O(log n). This is because we can first look up one side of the edge in the table and then the second side in the set that is returned. Note that an adjacency list is a special case of adjacency table where the table of vertices is represented as an array and the set of neighbors is represented as a list.

[Park2014]

tabular representation / tabular form

the edges are expressed as a tabular form as shown in Figure 1 (b) (in-edge sorted in this case). Each entry in the table contains two vertex IDs (‘in’ for destination and ‘out’ for source) connected to the
edge and edge value (edge weight in this example).

Index

VertexIndex

EdgeIndex

row

Compressed row storage

[Lenharth2014]

Compressed row storage
Compressed Sparse Row Storage
?Try to combine space efficiency of Lists with array traversal for edges
?Store Node data in an array
?Store all edges in an array (sorted by src)
?Store an array of pointers to edges
–Indexed by node id
–One pointer per node

CSR – Operations
Easy
?Iterate nodes
?Edges by src
?Add node?
Hard
?Edges by dst
?Add Edge
?Delete Edge
?Loopup by src, dst
–Linear seach
?Delete node

CSR – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Array iteration
?Space: O(2N + E)
–Constant for E == sizeof(Edata) + sizeof(int)

maps

maps
[Schwarz2012]

Rotation maps
[Elite2010]

Rules

EdgeRules

domains

touching domains
[Lovasz2009]

Polynomials

Graph Polynomials

[Trinks2012]

objects
linked-edge-objects representation

objects and pointers

[suanfazu2015]

objects and pointers / object representation

objects and pointers
These are just basic datastructures like hammar said in the other answer, in Java you would represent this with classes like edges and vertices. For example an edge connects two vertices and can either be directed or undirected and it can contain a weight. A vertex can have an ID, name etc. Mostly both of them have additional properties. So you can construct your graph with them like

Vertex a = new Vertex(1);
Vertex b = new Vertex(2);
Edge edge = new Edge(a,b, 30); // init an edge between ab and be with weight 30

This approach is commonly used for object oriented implementations, since it is more readable and convenient for object oriented users

Objects and pointers is mostly the same as adjacency list, at least for the purpose of comparing algorithms that use these representations.
Compare

struct Node {
??? Node *neighbours[];
};

with

struct Node {
??? Node *left;
??? Node *right;
};

You can easily construct the list of neighbours on-the-fly in the latter case, if it is easier to work with than named pointers.

Advantage of the object representation (incidence list) is that two adjacent vertices share the same instance of the edge. This makes it easy to manipulate with undirected edge data (length, cost, flow or even direction). However it uses extra memory for pointers.

Printable Format

Printable Format
[Joy1987]

Implicit Representations

hybrid

hybrid representation
[Madduri2009]

Dyn-arr to represent adjacencies of low-degree vertices, and Treaps for high-degree vertices.

Algorithms

LEDA also implements several more space-efficient adjacency array representations.

The Boost graph library [27, 119] emphasizes a strict separation of representation and interface. In particular, Boost graph algorithms run on any representation that realizes the Boost interface. Boost also offers its own graph representation class adjacency_list. A large number of parameters allow one to choose between variants of graphs (directed and undirected graphs and multigraphs2), types of navigation available (in-edges, out-edges, . . . ), and representations of vertex and edge sequences (arrays, linked lists, sorted sequences, . . . ). However, it should be noted that the array representation uses a separate array for the edges adjacent to each vertex.

JDSL [78] offers rich support for graphs in jdsl.graph. It has a clear separation between
interfaces, algorithms, and representation. It offers an adjacency list representation
of graphs that supports directed and undirected edges.


Untitled Document

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Algorithms

LEDA also implements several more space-efficient adjacency array representations.

The Boost graph library [27, 119] emphasizes a strict separation of representation and interface. In particular, Boost graph algorithms run on any representation that realizes the Boost interface. Boost also offers its own graph representation class adjacency_list. A large number of parameters allow one to choose between variants of graphs (directed and undirected graphs and multigraphs2), types of navigation available (in-edges, out-edges, . . . ), and representations of vertex and edge sequences (arrays, linked lists, sorted sequences, . . . ). However, it should be noted that the array representation uses a separate array for the edges adjacent to each vertex.

JDSL [78] offers rich support for graphs in jdsl.graph. It has a clear separation between
interfaces, algorithms, and representation. It offers an adjacency list representation
of graphs that supports directed and undirected edges.


Untitled Document

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array

Adjacency array
[Tangwongsan2012]

NodeArray and EdgeArray to indicate array-like data structures that can be indexed by nodes and by edges, respectively

To support easy access to the edges leaving any particular node, we can store the edges leaving any node in an array. If no additional information is stored with the edges, this array will just contain the indices of the target nodes. If the graph is static, i.e., does not change over time, we can concatenate all these little arrays into a single edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an example.edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an xample.

Adjacency array representations can be generalized to store additional information: we may store information associated with edges in separate arrays or within the edge array. If we also need incoming edges, we may use additional arrays V′ and E′ to store the reversed graph.

The memory consumption for storing a directed graph using adjacency arrays is n+m+Q(1) words.

Very often, some variant of adjacency arrays is fastest. This may be true even if the graph changes, because often there are only a few changes, or all changes happen in an initialization phase of a graph algorithm, or changes can be agglomerated into occasional rebuildings of the graph, or changes can be simulated by building several related graphs.

There are many variants of the adjacency array representation.

Information associated with nodes and edges may be stored together with these objects or in separate
arrays. A rule of thumb is that information that is frequently accessed should be stored with the nodes and edges. Rarely used data should be kept in separate arrays, because otherwise it would often be moved to the cache without being used. However, there can be other,more complicated reasons why separate arrays may be faster. For example, if both adjacency information and edge weights are read but only the
weights are changed, then separate arrays may be faster because the amount of data written back to the main memory is reduced.

Blelloch2012

Adjacency array

Similar to an adjacency list, an adjacency array keeps the neighbors of all vertices, one after another, in an array adj; and separately, keeps an array of indices that tell us where in the adj array to look for the neighbors of each vertex.

Dynamic Arrays
[Madduri2009]

Unbounded arrays

Unbounded arrays are more cache-efficient.


Untitled Document

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dictionary

[Kolter2016]

Adjacency dictionary

Pros: easy to add/remove/query edges (requires two dictionary lookups, so a ??(1) operation)
Cons: overhead of using a dictionary over array


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domains

touching domains
[Lovasz2009]


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)

hybrid

[Abu-Khzam2010a]

[Abu-Khzam2010b]

Hybrid Graph Representation ( adjacency-matrices + adjacency-lists)

In this paper, we show how a simple combination of the two representations can be used to facilitate the undo of many basic graph operations, especially deletions, thereby improving the running time of recursive backtracking (search) algorithms. Generally, every operation that can be taken back is pushed onto a stack and later popped out and performed in reverse. We refer to this action by explicit-undo. Our implicit-undo objective is achieved via a highly efficient use of a processor’s control stack only.

In addition to effective backtracking, the hybrid representation combines the advantage of constant time adjacency-queries in adjacency-matrices and the advantage of efficient neighborhood traversal in adjacency-lists. This method works well on simple unweighted graphs and may be extended to weighted graphs. Compared to the use of an adjacency list, the hybrid representation yields improved running times for vertex and edge deletion, permanent edge addition, as well as computing common neighbors.

The hybrid graph representation is best described using a simple example such as the one given in Figure 1. The adjacency list of a vertex v is stored in an array denoted by AL[v]. Accordingly, AL[v][i] holds the index of the ith vertex in the list of neighbors of v. The adjacency matrix, denoted henceforth by IM,
is used as an index table for the adjacency list as follows: the entry IM [u][v] is equal to the index of u in AL[v]. IM [u][v] is set to ?1 when the two vertices are not adjacent.

Note that AL is implemented using a two dimensional array for fast (direct) access via the indexing provided by IM. In general, we allocate enough memory to fit the neighbors of each vertex only.

In addition to IM and AL, we introduce three linear arrays: the degree vector (DEG), the vertex list (LIST), and the vertex index list (IDXLIST).

The degree vector holds the current neighborhood cardinality of each vertex.

LIST contains the list of currently active (not deleted) vertices which we use instead of the degree vector for more efficient complete graph traversals.

IDXLIST stores the index of each vertex in list.

In other words, LIST[i] is the i th vertex in the list of active vertices

IDXLIST[u] is the index of vertex u in LIST.

All data structures except for the deg vector are global and their memory is allocated at startup only. The deg vector is local to every search-tree node (i.e., every recursive call, since a copy of the vector is passed as parameter).

In the next section, we show how the above structures are dynamically updated during a search algorithm, while performing various graph modification operations. We note that some operations, like edge contraction for example, require additional bookkeeping that we briefly describe later. However, most common operations can be performed using the five data structures described above, which when combined together form the (generic) hybrid graph representation.

The hybrid data structure was designed with an eye on efficient graph modification operations during backtracking.

In addition, some basic operations like adjacency query and neighborhood traversal are also performed efficiently.

adjacency query

For example, checking if two vertices u and v are adjacent takes ??(1) time: just check whether ?1 < IM[u][v] < DEG[v].

neighborhood traversal

Graph traversal

Neighborhood search

Neighborhood search, on the other hand, runs in ??(d) time, where d is the current vertex degree.

Graph traversal is another frequent operation, often used to select a vertex or an edge having a certain property during branching algorithms. A complete graph traversal runs in ??(nc) time as opposed to ??(n), where nc is the number of currently active vertices in the graph. This is possible because of our use of
the LIST and IDXLIST vectors. In the rest of this section, we discuss how the hybrid method is used for graph modification operations.

Edge Deletion

The simplest and most frequent operation performed during the search is probably edge deletion. Maintaining the hybrid data structure in this case is straight- forward.

For deleting an edge (u, v), the degrees of u and v are decremented by one and the adjacency lists of the two vertices are adjusted respectively by placing u at the last position of AL[v] and v at the last position of AL[u] (Figure 2).

Each of these two operations consists of a single swap with the last element of the respective list, together with an adjustment of the positions in IM.

Going back to our illustrative graph G, after deleting edge (v0, v3), the modified AL, IM, and DEG vectors will be as shown in Figure 3 (changes are shown in gray).

No changes to LIST and IDXLIST are required for edge deletion since no vertices are removed from the graph.

Notice that this operation runs in ??(1) time as all the information required for switching positions in AL can be found in IM. Vertex v3 is no longer a neighbor of vertex v0 because IM[0][3] = 2 which is not less than DEG[0] = 2.

Undo Edge Deletion

Now assume we want to undo the previous operation. This can be accomplished by simply setting DEG[0] and DEG[3] back to 3. There is no need to change IM and AL back to the previous state since no specific order is required for storing vertex neighbors. Moreover, since every search-tree node maintains its own copy of the DEG vector, there are actually no actions whatsoever that need to be taken for undoing edge deletion. Thus we have an implicit-undo for edge deletion operations. This implicit undo runs in ??(1) time.

Edge Contraction

The next operation we consider is edge contraction. Contracting edge (u, v) replaces vertices u and v by a new vertex whose neighborhood is N(u) [ N(v) \ {u, v}.

To achieve our implicit-undo objective, we implement this operation using a coloring technique that requires additional bookkeeping.

Simply, vertices with the same color are treated as one single vertex obtained by contracting edges between them.

Initially, every vertex vi is assigned color ci, and every color class ci has cardinality one and degree d(ci) = d(vi).

In addition to previously discussed data structures, we use the following (see Figure 5):
– vcolor vector: holds the current color of every vertex.
– color card (cc) vector: holds the current cardinality of every color set.
– color degree (cd) vector: holds the current degree of every color set.
– color set list (csl): holds the list of vertices belonging to every color set.

Given that all operations now involve color sets, the LIST and IDXLIST do not hold vertex information anymore, but they maintain the list of active (not deleted) colors instead. If no edge contraction operations are performed, color sets would be identified by their corresponding vertices (or vice-versa).

When edge contraction is possible, the initial state of the graph G consists of all data structures previously discussed. AL, IM, CSL, LIST and IDXLIST would be globally stored (in RAM), while DEG, CD, CC and vcolor would be copied at every search-tree node.

To contract an edge, say (v3, v6), we actually assign both vertices the same color. Assuming we assign the two vertices color c3, the required modifications are shown in Figure 6 (changes shown in gray). Since we are dealing with simple graphs, any edge between two vertices belonging to the same color set is deleted and no more than one edge is allowed between a color set and another. Clearly, such an operation can be implicitly taken back as well, but is also more time and space consuming than simple vertex deletion. This technique makes it possible to implement the vertex folding operation, introduced in [8], for the parameterized vc algorithm.

Permanent Edge Addition

An edge addition performed at a search-tree node is considered permanent if no descendant search-tree node later modifies the operation (by edge or vertex deletion). In some problems, such as Cluster Editing, searching for a solution involves edge deletions as well as permanent edge additions.

Using the classical adjacency list structure, it would be impossible to incorporate edge addition without extra bookkeeping to record changes to the AL. To incorporate the permanent edge addition operation to our hybrid data structure, we make the following modifications:

(i) enough global memory is allocated to AL (i.e. n-by-n matrix where n is the size of the input graph), and

(ii) an additional degree vector (NDEG) is maintained at every search node.

The additional memory requirement guarantees storage space and the NDEG vector serves as a second degree vector. Figure 7 illustrate the required changes to the extended hybrid data structure after adding edge (v2, v6) to our original graph G.

The adjacency query still takes ??(1) time but requires an additional condition:

u and v are adjacent when ?1 <IM[u][v] < DEG[v] or ?1 < n ? 1 ? IM[u][v] < NDEG[v].

Neighborhood traversal becomes slightly more complicated but the time complexity remains unchanged. Undoing this operation only requires setting NDEG[2] and NDEG[6] back to 0 and subsequent addition of edges incident on v2 or v6 could overwrite older positions.

Vertex Deletion

In a typical computation using adjacency lists, deleting a vertex v of current degree d requires traversing the list of neighbors of v and deleting v from the list of each of its neighbors. This operation runs in ??(Δ(G)2) time.

Using our hybrid computation, deleting a vertex v runs in ??(d) time where d is the (current) degree of v. This is simply performed by running the edge deletion operation for every active neighbor of v (Figure 4). In addition, we remove v from the list of active vertices by swapping it with the last active vertex in LIST and decrementing the number of active vertices by one. The IDXLIST plays the same role as IM for deleting a vertex from LIST.

To illustrate the purpose of the list vector, suppose we need to pick a vertex with a particular property, such as one of maximum degree (which is often needed for heuristic priorities).

Consider the two operations of copying the deg vector and searching for the vertex of highest degree. Doing so would consume (n) time if the deg vector is used alone. This is reduced to ??(nc), where nc is the number of currently active vertices. To see why, note that iterating from i = 0 to nc only, DEG[LIST[i]]
returns the degree of the vertex at position i in LIST. Knowing that a great majority of search tree nodes are near the bottom of a search tree, where the graph order is almost constant, this simple strategy alone makes a substantial difference.

Undo Vertex Deletion

As in the case of edge-deletion, the undo of vertex deletion is implicit (requires no action) when separate degree vectors are maintained at every search node. This is due to the fact that edge deletion can be considered as an independent operation. The only required operation is to increment the number of active
vertices by one (if this value is stored globally) so that the LIST and IDXLIST vectors reflect the re-insertion of a vertex. Explicitly undoing a vertex deletion operation runs in ??(d) time where d is the degree of the deleted vertex (it mainly consists of incrementing the degree of each neighbor by one.)

The Vertex Cover Folding Operation

Let (G, k) be an instance of the Vertex Cover problem and let u ∈ V (G) be a degree-two vertex with neighbors v and w. If v and w are adjacent, then there is a minimum vertex cover that contains v and w (and not u). So it is safe to delete u, add v and w to the potential solution and decrement k by two. In the
case where v and w are non-adjacent, an equivalent Vertex Cover instance is obtained by contracting edges uv and uw and decrementing k by one. This latter operation is known as degree-two vertex folding [8].

As we shall see, applying the coloring technique to implement vertex folding considerably improves the runtime on certain recalcitrant instances, but slows down the computation on graphs where folding rarely occurs. In such cases, the overhead of maintaining color-sets is a drawback. Note that folding alone made it possible to obtain a worst-case running time of ??(1.285k) in [8]. Yet, our results show that excluding folding from the same algorithm is faster on a large number of instances, except for the case where is graph is regular (or nearly regular) where other reduction methods do no apply.

Table 1. Runtime comparison for different search-operations using al, am, and the hybrid graph representation. We denote by n the number of vertices in the graph, by d(v) the degree of a vertex v, and d(c) denotes the degree of a color-set c.

Operation Adjacency Matrix Adjacency List Hybrid
Adjacency Query ??(1) ??(d(v)) ??(1)
Neighborhood Traversal ??(n) ??(d(v)) ??(d(v))
Edge Deletion ??(1) ??(d(v)) ??(1)
Undo Edge Deletion ??(1) ??(1) ??(1)
Vertex Deletion ??(n) ??(d(v)2) ??(d(v))
Undo Vertex Deletion ??(d(v)) ??(d(v)) ??(1)
Edge Contraction ??(n) ??(d(v)) ??(d(c))
Undo Edge Contraction ??(d(v)) ??(d(v)) ??(1)
Edge Addition ??(1) ??(1) ??(1)
Undo Edge Addition ??(1) ??(d(v)) ??(1)

hybrid representation
[Madduri2009]

Dyn-arr to represent adjacencies of low-degree vertices, and Treaps for high-degree vertices.


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Graph Representation

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Implicit Representations


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Graph Representation

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Index

VertexIndex

EdgeIndex


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Graph Representation

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Lists

Adjacency Lists

[Abiy2016]

Adjacency List

hashtable with an array in python

hashtable with linked lists in python

A common way to implement a graph using an adjacency list is to use either a hashtable with an array as values or use a hashtable with linked lists as a value. Since python combines the idea of arrays and linked lists we can easily implement this representation using a dictionary with nodes as keys and a list as a value.

However if the graphs is sparse, that is if most of the possible edges are not present, then the adjacency-list representation can save space.

To see why, note that an adjacency matrix for an n node graph has n2 bits, and therefore could be packed into n2/32-bit words. The common adjacency list cell will consist of two words, one for the node and one for the pointer to the next cell. Thus, if the number of edges is a , we need about 2a words for the lists, and n words for the array of headers. The adjacency list will use less space than the adjacency matrix if

n+2a<n2/32

The following table summarizes the preferred representation for various operations:

operations | dense graph | sparse graph
lookup edge | adjacency matrix | either
find successor | either | adjacency list
find predeccessor | adjacency matrix | either

Let us assume the graph is represented by adjacency lists, so we can find all edges in O(m) time.

Adjacency lists are good if the graph changes frequently

Adjacency lists for sparse graphs should be implemented without the dummy item introduced in Sect. 3.1, because an additional item would waste considerable space.

The second solution has only one item for each undirected edge (or pair of directed edges) and makes this item a member of two adjacency lists. So, the item for an undirected edge {u,v} would be a member of lists Eu and Ev. If we want doubly linked adjacency information, the edge object for any edge {u,v} stores four pointers: two are used for the doubly linked list representing Eu, and two are used for the
doubly linked list representing Ev. Any node stores a pointer to some edge incident on it. Starting from it, all edges incident on the node can be traversed. The bottom part of Fig. 8.1 gives an example. A small complication lies in the fact that finding the other end of an edge now requires some work. Note that the edge object for an edge {u,v} stores the endpoints in no particular order. Hence, when we explore the
edges out of a node u, we must inspect both endpoints and then choose the one which is different from u. An elegant alternative is to store u⊕v in the edge object [145]. An exclusive OR with either endpoint then yields the other endpoint. Also, this representation saves space.

A common way to implement a graph using an adjacency list is to use either a hashtable with an array as values or use a hashtable with linked lists as a value. Since python combines the idea of arrays and linked lists we can easily implement this representation using a dictionary with nodes as keys and a list as a value.

However if the graphs is sparse, that is if most of the possible edges are not present, then the adjacency-list representation can save space.

adjacency list

For every vertex adjacency list stores a list of vertices, which are adjacent to current one.

It requires less amount of memory

To sum up, adjacency list is a good solution for sparse graphs and lets us changing number of vertices more efficiently, than if using an adjacent matrix. But still there are better solutions to store fully dynamic graphs.

Advantages.

Adjacent list allows us to store graph in more compact form, than adjacency matrix, but the difference decreasing as a graph becomes denser.

Next advantage is that adjacent list allows to get the list of adjacent vertices in O(1) time, which is a big advantage for some algorithms.

Disadvantages.

  • Adding/removing an edge to/from adjacent list is not so easy as for adjacency matrix. It requires, on the average, O(|E| / |V|) time, which may result in cubical complexity for dense graphs to add all edges.
  • Check, if there is an edge between two vertices can be done in O(|E| / |V|) when list of adjacent vertices is unordered or O(log2(|E| / |V|)) when it is sorted. This operation stays quite cheap.
  • Adjacent list doesn't allow us to make an efficient implementation, if dynamically change of vertices number is required. Adding new vertex can be done in O(V), but removal results in O(E) complexity.

Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to theith vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to theith vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).

Adjacency Lists

Most large interesting graphs are sparse ?? For this reason the adjacency list is often a more appropriate representation

Each adjacency list is a chain.

# of chain nodes = 2|E| (undirected graph)
# of chain nodes = |E| (digraph)

How much storage is required?
?? The degree of a vertex v = # incident edges
??Directed graphs have in-degree and out-degree
?? For directed graphs:
?? # of items in adjacency lists is Σ out-degree(v) = |E|
??takes Θ(V + E) storage (Why?)
?? For undirected graphs:
??# items in adjacency lists is Σ degree(v) = 2|E|
??also Θ(V + E) storage
?? So: Adjacency lists take O(V + E) storage

[AHS]

An Adjacency List

A more space-efficient way to implement a sparsely connected graph is to use an adjacency list. In an adjacency list implementation we keep a master list of all the vertices in the Graph object and then each vertex object in the graph maintains a list of the other vertices that it is connected to. In our implementation of the Vertex class we will use a dictionary rather than a list where the dictionary keys are the vertices, and the values are the weights. Figure 4 illustrates the adjacency list representation for the graph in Figure 2.

The advantage of the adjacency list implementation is that it allows us to compactly represent a sparse graph. The adjacency list also allows us to easily find all the links that are directly connected to a particular vertex.

[AHUJA1993]

Adjacency List:

page 25

The arc adjacency list A(i) of a node i is the set of arcs emanating from that node, that is, A(i) = {(i,j) ∈ A: j ∈N}.

Earlier we defined the arc adjacency list A(i) of a node i as the set of arcs emanating from that node, that is, the set of arcs (i, j) ∈ A obtained as j ranges over the nodes of the network.

The node adjacency list A(i) is the set of nodes adjacent to that node; in this case, A(i) = {j ∈ N: (i,j) ∈ A}.

Similarly, we defined the node adjacency list of a node i as the set of nodes j for which (i, j) ∈ A.

The adjacency list representation stores the node adjacency list of each node as a singly linked list (we refer the reader to Appendix A for a description of singly linked lists). A linked list is a collection of cells each containing one or more fields. The node adjacency list for node i will be a linked list having |A (i)| cells and each cell will correspond to an arc (i, j) ∈A. The cell corresponding to the arc (i, j) will have as many fields as the amount of information we wish to store. One data field will store node j. We might use two other data fields to store the arc cost ?ij and the arc capacity ??ij. Each cell will contain one additional
field, called the link, which stores a pointer to the next cell in the adjacency list. If a cell happens to be the last cell in the adjacency list, by convention we set its link to value zero.

Since we need to be able to store and access n linked lists, one for each node, we also need an array of pointers that point to the first cell in each linked list. We accomplish this objective by defining an n-dimensional array, first, whose element first(i) stores a pointer to the first cell in the adjacency list of node i. If the adjacency list of node i is empty, we set first(i) = 0. Figure 2.16 specifies the adjacency list representation of the network shown in Figure 2. 13.

In this book we sometimes assume that whenever arc (i,j) belongs to a network, so does the reverse arc (j, i). In these situations, while updating some information about arc (i, j), we typically will also need to update information about arc (j, i). Since we will store arc (i, j) in the adjacency list of node i and arc (j, i) in the adjacency list of node j, we can carry out any operation on both arcs efficiently if we know where to find the reversal (j, i) of each arc (i,j). We can access both arcs easily if we define an additional field, mate, that contains a pointer to the cell containing data for the reversal of each arc. The mate of arc (i, j) points to the cell of arc (j, i) and the mate of arc (j, i) points to the cell of arc (i, j).

Often, we shall omit the terms "arc" and "node" and simply refer to the adjacency list; in all cases it will be clear from context whether we mean arc adjacency list or node adjacency list.

We assume that arcs in the adjacency list A(i) are arranged so that the head nodes of arcs are in increasing order.

Notice that |A(i)| equals the outdegree of node i. Since the sum of all node outdegrees equals m, we immediately obtain the following property:

Property 2.1. ∑ i ∈ N | A(i) | = m.

?

[AlgoList]

Adjacency list

For every vertex adjacency list stores a list of vertices, which are adjacent to current one.

It requires less amount of memory

To sum up, adjacency list is a good solution for sparse graphs and lets us changing number of vertices more efficiently, than if using an adjacent matrix. But still there are better solutions to store fully dynamic graphs.

Advantages.

Adjacent list allows us to store graph in more compact form, than adjacency matrix, but the difference decreasing as a graph becomes denser.

Next advantage is that adjacent list allows to get the list of adjacent vertices in O(1) time, which is a big advantage for some algorithms.

Disadvantages.

  • Adding/removing an edge to/from adjacent list is not so easy as for adjacency matrix. It requires, on the average, O(|E| / |V|) time, which may result in cubical complexity for dense graphs to add all edges.
  • Check, if there is an edge between two vertices can be done in O(|E| / |V|) when list of adjacent vertices is unordered or O(log2(|E| / |V|)) when it is sorted. This operation stays quite cheap.
  • Adjacent list doesn't allow us to make an efficient implementation, if dynamically change of vertices number is required. Adding new vertex can be done in O(V), but removal results in O(E) complexity.

?

[Balkcom]

Adjacency lists

Representing a graph with adjacency lists combines adjacency matrices with edge lists. For each vertex x, store a list of the vertices adjacent to it. We typically have a Python list of n adjacency lists, one adjacency list per vertex. We can store an adjacency list with a Python list (if we don’t plan to insert or delete adjacent vertices) or a linked list (if we expect to insert or delete adjacent vertices). Here’s an adjacency-list representation of the graph from above, using Python lists:

We can get to each vertex’s adjacency list in Θ(1) time, because we just have to index into a Python list of adjacency lists. To find out whether an edge (x,?y) is present in the graph, we go to x’s adjacency list in Θ(1) time and then look for y in x’s adjacency list. How long does that take? O(d), where d is the degree of x, because that’s how long x’s adjacency list is. The degree of x could be as high as n???1 (if x is adjacent to all other n???1 vertices) or as low as 0 (if x is isolated, with no incident edges). In an undirected graph, y is in x’s adjacency list if and only if x is in y’s adjacency list. If the graph is weighted, then each item in each adjacency list is either a two-item list or a 2-tuple, giving the vertex number and the edge weight.

How much space do adjacency lists take? We have n lists, and although each list could have as many as n???1 vertices, in total the adjacency lists for an undirected graph contain 2m items. Why 2m? Each edge (x,?y) appears exactly twice in the adjacency lists, once in x’s list and once in y’s list, and there are m edges. For a directed graph, the adjacency lists contain a total of m items, one item per directed edge. For either an undirected graph or a directed graph, we say that the adjacency-list representation takes Θ(n?+?m) space; the n term comes from list of vertices, and the m term comes from all the adjacency lists together.

Adjacency lists in objects

For Lab Assignment 4, you’ll be creating several Vertex objects. Among its instance variables, each Vertex object will have one that is a reference to a Python list of Vertex objects, indicating the adjacent vertices. There will be two ways to get to a Vertex object: through the adjacency list of some other Vertex object, or through a dictionary whose keys are names of vertices and whose values are Vertex objects.

[Barnes2015]

Adjacency List

nodes stored in collection (JFC: Arraylist, TreeMap, HashMap) where each node has list of references to adjacent nodes ‘a’ is the vertex and ‘A’ is a pointer to ‘a’

[Barnwal]

Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to thei th vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).

?

[Basel2005]

Adjacency Lists

Most large interesting graphs are sparse For this reason the adjacency list is often a more appropriate representation

Each adjacency list is a chain.

# of chain nodes = 2|E| (undirected graph)
# of chain nodes = |E| (digraph)

How much storage is required?
The degree of a vertex v = # incident edges
Directed graphs have in-degree and out-degree
For directed graphs:
# of items in adjacency lists is Σ out-degree(v) = |E|
takes Θ(V + E) storage (Why?)
For undirected graphs:
# items in adjacency lists is Σ degree(v) = 2|E|
also Θ(V + E) storage
So: Adjacency lists take O(V + E) storage

[Beard]

adjacency list

This is just a simple datastructure mix, I usually implement this using a HashMap<Vertex, List<Vertex>>. Similar used can be the HashMultimap in Guava.

This approach is cool, because you have O(1) (amortized) vertex lookup and it returns me a list of all adjacent vertices to this particular vertex I demanded.

ArrayList<Vertex> list = new ArrayList<>();
list.add(new Vertex(2));
list.add(new Vertex(3));
map.put(new Vertex(1), list); // vertex 1 is adjacent to 2 and 3

This is used for representing sparse graphs, if you are applying at Google, you should know that the webgraph is sparse. You can deal with them in a more scalable way using a BigTable.

?

[Berkeley]

adjacency list

The adjacency list representation for a directed graph with n vertices and e edges is an n-element array of linked lists; the list for the kth vertex vk contains all vertices w such that (vk, w) is an edge in the graph.

[Black2015]

adjacency-list representation

(data structure)

Definition: A representation of a directed graph with n vertices using an array of n lists of vertices. List i contains vertex j if there is an edge from vertex i to vertex j. A weighted graph may be represented with a list of vertex/weight pairs. An undirected graph may be represented by having vertex j in the list for vertex i and vertex i in the list for vertex j.

Note: Suppose we have a directed graph with four vertices. Here are adjacency-matrix and adjacency-list representations. The arrow (->) means a link in a list.

    1 2 3 4
 1  1 1 1 1
 2  1 0 0 0
 3  0 1 0 1
 4  0 1 1 0

1 -> 1 -> 2 -> 3 -> 4
2 -> 1
3 -> 2 -> 4
4 -> 2 -> 3

One variant is to have an array of columns, rather than rows, with the list going "down". The adjacency-list representation is more compact for a sparse matrix.

Blelloch2012

Adjacency list

An array A of length n where each entry A[i] contains a pointer to a linked list of all the out-neighbors of vertex i. In an undirected graph with edge fu, vg the edge will appear in the adjacency list for both u and v.

[Bradfield]

adjacency list

The adjacency list is really a mapping, so in this section we also consider two possible representations in Python of the adjacency list: one an object-oriented approach with a Python dict as its underlying data type, and one just using a plain dict directly.

Ultimately though, we see the adjacency list representation using a pure map type (such as a dict in Python) as the most intuitive and flexible.

In an adjacency list implementation we keep a master collection of all the vertices in the Graph object and then each vertex object in the graph maintains a list of the other vertices that it is connected to. In our implementation of the Vertex class we will use a dictionary rather than a list as our master collection, where the dictionary keys are the vertices, and the values are the weights. The diagram below shows an adjacency list representation of the example graph we have been discussing.

The advantage of the adjacency list implementation is that it allows us to compactly represent a sparse graph. The adjacency list also allows us to easily find all the links that are directly connected to a particular vertex.

[Chen2012]

adjacency-list

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 2 List: linear in the length of Adj(u) (or equivalently, deg(u) if G is undirected, and out-deg(u) if G is directed)

To decide if (u; v) 2 E, the list representation has worst-case running time linear in the length of Adj(u) (why?).

If the input graphs are sparse and we make a lot of enumerations of edges incident to a vertex in our algorithm, then the list representation usually ts better.

[Chu-Carroll 2007]

adjacency list

A common optimization of the adjacency list is to use a data object to represent a vertex, and to use
pointers/references to vertex objects as the vertex identifiers in the adjacency list for a vertex. Depending
on the application, the adjacency lists could be either arrays, linked lists, or some other similar structure.

Using an adjacency list works much better if you have a sparse matrix – it only uses space for edges that are actually present in the graph.

It’s also often easier to associate data with vertices and edges in a good way using adjacency lists;

and it can often produce better performance in that case as well, due to good locality. (When you traverse an edge in an adjacency list using the pointer implementation described above, you’re pulling the vertex into your cache; then when you go to look at the data for the vertex, it’s hot in the cache. In an adjacency matrix, you’d use a separate table for that, which would mean fetching from a different area of memory.)

The adjacency list is often better for certain kinds of graph traversals:

if you need to walk through a graph collecting information about visited vertices, the locality properties of the adjacency list structure can have a great effect on performance.

Adjacency list implemented as pointers/references is of course a quite natural way to represent a graph, especially if you’re not interested in easily iterating through the edges. But this doesn’t work really well with functional programming, since there are no mutable references. One would somehow have to create the whole graph at once. Is something like that even possible in some functional language? What about cyclic data structures in FP in general? (Of course quick googling sorted much of this. But I’m posting anyways.;) )

Philip Sternberg August 15, 2007 A little note on the adjacency list implementation in python: for many applications, you might be better off using a set rather than a list as the member object that stores neighbors, giving O(1) lookup time.

[Claude2007]

adjacency lists

Re-Pair [19] to compress the adjacency lists

Standard graph representations such as the adjacency list require 2e log n bits, for undirected graphs. For directed graphs the numbers are e log n.

Cormen2014

Adjacency lists

Representing a graph with adjacency lists combines adjacency matrices with edge lists

It is true that in the general case that storage of an adjacency list is O(|V|+|E|).
This is the same as O( max( |V|, |E| ) )
Which means that you at least need to allocate space for the pointer to each vertices list.
In most practical cases |E| will larger than |V| (even for a minimally connected graph i.e. a tree, E = V-1). Which means for most practical cases the space required is simply O(|E|).

We can get to each vertex's adjacency list in constant time, because we just have to index into an array. To find out whether an edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis is present in the graph, we go to i i ii 's adjacency list in constant time and then look for j j jj in i i ii 's adjacency list. How long does that take in the worst case? The answer is Θ(d) \Theta(d) Θ(d) , where d d dd is the degree of vertex i i ii , because that's how long i i ii 's adjacency list is. The degree of vertex i i ii could be as high as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 (if i i ii is adjacent to all the other ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices) or as low as 0 (if i i ii is isolated, with no incident edges). In an undirected graph, vertex j j jj is in vertex i i ii 's adjacency list if and only if i i ii is in j j jj 's adjacency list. If the graph is weighted, then each item in each adjacency list is either a two-item array or an object, giving the vertex number and the edge weight.

How much space do adjacency lists take? We have ∣V∣ |V| ∣V∣vertical bar, V, vertical bar lists, and although each list could have as many as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices, in total the adjacency lists for an undirected graph contain 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar elements. Why 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar ? Each edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis appears exactly twice in the adjacency lists, once in i i ii 's list and once in j j jj 's list, and there are ∣E∣ |E| ∣E∣vertical bar, E, vertical bar edges. For a directed graph, the adjacency lists contain a total of ∣E∣ |E| ∣E∣vertical bar, E, vertical bar elements, one element per directed edge.

Agreed, if the list of neighbors is implemented as an array, and that array is sorted then determining membership is Θ(log(d)), using binary search.

However, if the array is unsorted, or if the list of neighbors is implemented as a linked list (both are typical implementations) then determining membership is Θ(d), as we need to look at every item in the list before deciding that something is not in the list.

In the article they mention "Vertex numbers in an adjacency list are not required to appear in any particular order", which implies the analysis is with regards to unsorted implementations.

Whether you would want to use a sorted version or not would depend on your application. You might get the sorting for free (i.e. if your method of constructing your graph leads to naturally sorted adjacency lists), or you might have to pay an additional cost in sorting the adjacency lists. Whether the cost outweighs the benefits depends on your application.

For finding the neighbours of vertex v:

Adjacency List: O(|N|)
where N is the number of neighbours of v
You need to iterate through the list for the vertex v, which has N neighbours
v could have up to V-1 neighbours, so we could also say it is O(|V|)

how is adjacency list space Θ(V + E)?

The adjacency list contains:
-1 array per vertex, for a total of V arrays (we are only considering the space for the array pointer, not the contents of the array).
-Each directed edge is contained once somewhere in the adjacency list, for a total of E edges (a bidirectional edge is just 2 directed edges, so if we are using bidirectional edges it would just be 2E ).

V+E is Θ(V + E)

[Cornell2011]

adjacency list

Directed graphs are commonly represented as an adjacency list, which comprises an array or list of vertices, where each vertex vi stores a list of all the vertices vj for which there is an edge (vi, vj) ∈ E.

In practice, many graphs are sparse in the sense that most of the possible edges between pairs of vertices do not exist, i.e. m << n2. In such cases the adjacency list is generally preferable to the adjacency matrix representation.

In that implementation, a graph is represented as a pair consisting of the number of vertices and a list of vertices. A vertex is represented as a triple of a unique integer id, an outgoing list, and an incoming list. The outgoing list is a list of pairs of destination vertex and weight. The incoming vertex list is a list of pairs of source vertex and weight. Note that as each edge is stored twice, in the incoming list of its destination and the outgoing list of its source, the weight must be consistent in the two lists.

In that implementation, an edge is a triple of a source vertex, destination vertex and weight, and is constructed on the fly as needed from the vertex out lists rather than being explicitly stored in the data structure.

[Deepa2014]

Adjacency Lists in Lists

We can more efficiently represent sparse graphs by using linked lists to store the neighbors adjacent to each vertex. Adjacency lists require pointers but are not frightening once you have experience with linked structures.
Adjacency lists make it harder to ask whether a given edge (i, j) is in G, since we have to search through the appropriate list to find the edge. However, it is often surprisingly easy to design graph algorithms which avoid any need for such queries. Typically, we sweep through all the edges of the graph in one pass via a breadth-first or depths-first traversal, and update the implications of the current edge as we visit it.

[Deepa2014]

Adjacency Lists in Matrices

Adjacency lists can also embedded in matrices, thus eliminating the need for pointers. We can represent a list in an array (or equivalently, a row of a matrix) by keeping a count k of how many elements there are, and packing them into the first k elements of the array. Now we can visit successive the elements from the first to last just like a list, but by incrementing an index in a loop instead of cruising through pointers.

As stated above, we will use adjacency lists in matrices as our basic data structure to represent graphs. It is not complicated to convert these routines to honest pointer based adjacency lists.

[Depree2013]

Linked Adjacency Lists

Array Adjacency Lists

adjacency multilist representation

[Dezso2010]

doubly-linked adjacency list

The example in Figure 1 uses ListDigraph, which is a doubly-linked adjacency list based directed graph implementation.

BGL implements a single adjacency list based graph class, but it can be customized with template parameters that specify the internal storage structures for nodes and arcs.

simply-linked lists

Another important digraph structure is SmartDigraph, which stores the nodes and arcs continuously in vectors and uses simply-linked lists for keeping track of the incident arcs of each node. Therefore, it has smaller memory footprint and it can be considerably faster, at the cost that nodes and arcs cannot be removed from it.

[Grama2003]

adjacency list

The adjacency list representation of a graph G = (V;E) consists of an array Adj[1::jV j] of lists. Each list Adj[v] is a list of all vertices adjacent to v.

[Gross2003]

ADJACENCY LIST REPRESENTATION

def: An adjacency list for a vertex v of a graph G is a list containing each vertex w of G
once for each edge between v and w.
def: An adjacency list representation of a graph is a table of all the adjacency lists.

[Guttag2013]

adjacency list

Another common representation is an adjacency list, which we use here. Class Digraph has two instance variables. The variable nodes is a Python list containing the names of the nodes in the Digraph. The connectivity of the nodes is represented using an adjacency list implemented as a dictionary. The variable
edges is a dictionary that maps each Node in the Digraph to a list of the children of that Node.

[Kempe2016]

adjacency lists

1. Via adjacency lists: for each node, store a list of all other nodes it is adjacent to. (This could be using
the ADT Set, the ADT List, a Linked List, or a dynamically growing array.) If the graph is directed, we would store two separate lists: one for outgoing edges and another for incoming ones. The elements of the list would be either pointers to the other nodes, or — if nodes themselves are stored in an array — integers, i.e., the indices in the array where the other node is stored.

For an adjacency list, we don’t have that information readily available. Instead, we need to go through
the list of all outgoing edges of u, and see if v is in that list. That will take (outdegree(u)), which can be much larger. (As we learn about better implementations of sets later, this becomes faster, but even then, the time will not go down to constant.)

3. Listing all outgoing/incoming edges of u is the specialty of adjacency lists. Since they explicitly store
this information, they just have to go through their Set/List, which takes time (outdegree(u)) or
(indegree(u)).

For adjacency lists, we store all incoming and all outgoing edges, which gives us a total memory
requirement of ( P v(indegree(v)+outdegree(v))). To evaluate this sum, notice that when we sum all
in-degrees, we count each edge exactly once, since it contributes 1 to the indegree of exactly one node.
So the sum of all indegrees is m, and similarly for the sum of all outdegrees. Thus, the sum above is equal to 2m, which is (m). Thus, the total storage requirement is (n + m) (since we also need to store information for all nodes).

[Kolter2016]

Adjacency list

Pros: easy to get all outgoing links from a given node, fast to add new edges (without checking for duplicates)
Cons: deleting edges or checking existing of an edge requires scan through given node’s full adjacency array

[Kudase2016]

Adjacency List

Adjacency List: This list structure extends the edge list structure by adding incidence containers to each vertex.
Here an array of linked lists is used. Array size will be equal to the number of vertices. Consider an array A[ ]. An entry A[i] represents the linked list of vertices adjacent to the ith vertex. In these, vertices are stored as objects. Each vertex further contains a list of neighboring vertices. This type of representation allows additional data of the vertices to be stored. But these additional data is stored only if edges are stored as objects that mean every vertex store its incident edges and edge stores its incident vertices.

Another representation could be maintaining two lists. First list stores indices corresponding to each vertex in the graph and each of these refer to the second list storing the index of each adjacent vertex to this one. It would be good if we associate weight of each edge with the adjacent vertex in this list. These lists of all the vertices in the graph would be useful if stored in a hash table.

It is also used to represent a weighted graph. The nodes of linked lists will be storing weights of edges. Each node has precisely as many nodes in its adjacency list as it has neighbors. Therefore, an adjacency list is a very space efficient representation of a graph. You would not store more information than actually required.

If a graph has V vertices and E edges then a graph represented using adjacency list will need –

? V+E node instances for a directed graph

? V+2E node instances for an undirected graph This is generally recommended if it efficiently represent sparse graphs.

Advantages of using adjacency list are as follows:
? Addition of a vertex and connecting new vertices with the existing ones is easier.
? Has a space complexity of O(|V|+|E|).
? It allows us to store graph in more compact form and to get the list of adjacent vertices in O(1) time which is a big benefit for some algorithms.

Disadvantages of using adjacency list are as follows:
? Queries like whether there is an edge from vertex u to vertex v are not efficient and require time complexity, O(V).
? It does not allow us to make an efficient implementation, if dynamic change of vertices number is required.

[Lenharth2014]

Adjacency lists

?Nodes stored in array as pointers to linked lists
?Edges stored as linked list at src
?Fundamentally directed

Adjacency Lists – Operations
Easy
?Iterate nodes
?Edges by src
?Add Edge
?Delete edge
?Add node?
Hard
?Edges by dst
?Loopup by src, dst
–Linear seach
?Delete node

Adjacency Lists – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Linked List iteration
–Expensive due to indirection
–not cache friendly
?Edge addition: O(1)
–Except involves an allocation
?Edge removal: O(E)
?Space: O(N + E)
–Constant for E == sizeof(ptr) + sizeof(Edata) + sizeof(int)

[Nelson]

  • Adjacency lists
    • Is (u,v) an edge? -- O(E/N) on average
    • Successors (u) -- O(E/N)
    • Predecessor (u) -- O(N+E)
    • Space -- O(N + E)
    • Best for sparse graphs (E << N^2)

[PSF2003]

PSF Python Patterns - Implementing Graphs

Adjacency list

For instance, here's a simple graph (I can't use drawings in these columns, so I write down the graph's arcs):

A -> B
A -> C
B -> C
B -> D
C -> D
D -> C
E -> F
F -> C
This graph has six nodes (A-F) and eight arcs. It can be represented by the following Python data structure:
graph = {'A': ['B', 'C'],
'B': ['C', 'D'],
'C': ['D'],
'D': ['C'],
'E': ['F'],
'F': ['C']}
This is a dictionary whose keys are the nodes of the graph. For each key, the corresponding value is a list containing the nodes that are connected by a direct arc from this node. This is about as simple as it gets (even simpler, the nodes could be represented by numbers instead of names, but names are more convenient and can easily be made to carry more information, such as city names).

[Slesarenko2015]

Flat Adjacency List

[Sommer2010]

Adjacency List

Likewise, this is an ecient way to represent a graph but the access times are slower compared to a matrix (O(lg n) compared to O(1)). One way to solve this issue is to use a hash table for each node, containing all its neighbors.

[stoimen2012]

Adjacency Lists

While for an adjacency list we can have:

  1. Adding an edge – O(log(n));
  2. Deleting an edge – O(log(n));
  3. Answering the question “is there an edge between i and j” – O(log(n));
  4. Finding the successors of a given vertex – O(k), where “k” is the length of the lists containing the successors of i;
  5. Finding (if exists) a path between two vertices – O(n+m) – where m <= n;

[suanfazu2015]

adjacency list
This is just a simple datastructure mix, I usually implement this using a HashMap<Vertex, List<Vertex>>. Similar used can be the HashMultimap in Guava.
This approach is cool, because you have O(1) (amortized) vertex lookup and it returns me a list of all adjacent vertices to this particular vertex I demanded.

ArrayList<Vertex> list = new ArrayList<>();
list.add(new Vertex(2));
list.add(new Vertex(3));
map.put(new Vertex(1), list); // vertex 1 is adjacent to 2 and 3

This is used for representing sparse graphs, if you are applying at Google, you should know that the webgraph is sparse. You can deal with them in a more scalable way using a BigTable1.

[Vallon2016]

Adjacency list

Complexity

Adjacency list | ? | ? | ?
Storage | Add Vertex | Add Edge | Query
O(|V|+|E|) | O(1) | O(1) | O(|V|)

[Wang2012]

adjacency lists

adjacency lists provide more compact storage for more widespread sparse graphs.

A basic adjacency list stores all edges in a graph.

One typical way of implementing it is using one array to store a list of neighbor nodes and another array to store the offset of the neighbor list for each node.

Merrill et al.12 use the well-known compressed sparse row (CSR) sparse matrix format to represent graphs in their BFS implementation.
The column-indices array C and row-offsets array R are equivalent to the neighbor nodes list and the offset list in the basic adjacency list de nition. This representation enables them to use parallel primitives such as pre x sum to reorganize sparse and uneven workloads into dense and uniform ones in all phases of graph processing. In the context of parallel BFS, parallel threads use pre x sum when assembling global edge frontiers from expanded neighbors and when outputting unique unvisited vertices into global vertex frontiers.

Jia et al.10 represent the graph as an edge list to better assign edges to threads in their centrality algorithm. Instead of using two unequal length arrays|an o set array and a neighbor list array|they use two even length arrays to store the vertex pair for each edge. Their edge-centric representation requires more GPU memory though, which could limit their application to larger graphs.

[Weiss2014] [Weiss2012]

Adjacency lists

Adjacency lists are the standard way to represent graphs.

There are several alternatives for maintaining the adjacency lists.

First, observe that the lists themselves can be maintained in either vectors or lists.

However, for sparse graphs, when using vectors, the programmer may need to initialize each vector with a smaller capacity than the default; otherwise, there could be significant wasted space.

Because it is important to be able to quickly obtain the list of adjacent vertices for any vertex, the two basic options are to use a map in which the keys are vertices and the values are adjacency lists, or to maintain each adjacency list as a data member of a Vertex class.

The first option is arguably simpler, but the second option can be faster, because it avoids repeated lookups in the map.

In the second scenario, if the vertex is a string (for instance, an airport name, or the name of a street intersection), then a map can be used in which the key is the vertex name and the value is a Vertex (typically a pointer to a Vertex), and each Vertex object keeps a list of (pointers to the) adjacent vertices and perhaps also the original string name.

[wikibooks]

https://en.wikibooks.org/wiki/Data_Structures/Graphs

Adjacency List Representation

The adjacency list is another common representation of a graph. There are many ways to implement this adjacency representation.

One way is to have the graph maintain a list of lists, in which the first list is a list of indices corresponding to each node in the graph. Each of these refer to another list that stores the index of each adjacent node to this one. It might also be useful to associate the weight of each link with the adjacent node in this list.

Example: An undirected graph contains four nodes 1, 2, 3 and 4. 1 is linked to 2 and 3. 2 is linked to 3. 3 is linked to 4.

1 - [2, 3]

2 - [1, 3]

3 - [1, 2, 4]

4 - [3]

It might be useful to store the list of all the nodes in the graph in a hash table. The keys then would correspond to the indices of each node and the value would be a reference to the list of adjacent node indices.

Another implementation might require that each node keep a list of its adjacent nodes.

[Zanibbi2009]

Adjacency List

Node indexed array of lists.
Two representations of each edge.
Space proportional to m + n.
Checking if (u, v) is an edge takes O(deg(u)) time.
Identifying all edges takes Θ(m + n) time.

degree = number of neighbors of u

Array Adjacency Lists

Array Adjacency Lists

[Depree2013]

Each adjacency list is an array list.

Array Length = n
# of list elements = 2e (undirected graph)
# of list elements = e (digraph)

Adjacency lists => each list element is a pair (adjacent vertex, edge weight)

[Madduri2008] [Madduri2009]

adjacency lists using adjacency arrays

For representing sparse static graphs, adjacency lists implemented using cache-friendly adjacency arrays are shown to give substantial performance improvements over linkedlist and adjacency matrix representations for sparse graphs [22].

(adjacency lists using) dynamic, resizable adjacency arrays

Dynamic Arrays (Dyn-arr). We can extend the static graph representation and use dynamic, resizable adjacency arrays for processing insertions and deletions. Clearly, this would support fast insertions. For inserting a new edge hu; vi, we resize the adjacency array of u if needed, and place v at the end of the array. The count can be incremented using an atomic increment operation on modern hardware,
and so this representation supports lock-free, non-blocking insertions.

There are two potential parallel performance issues with this data structure. Edge deletions are expensive in this representation, as we may have to scan the entire adjacency list in the worst case to locate the required tuple. Note that a scan is reasonable for low-degree vertices (say, less than 10 adjacencies), given the spatial locality we have due to the contiguous adjacency representation. However,
due to the power-law degree distributions in small-world networks, we may encounter several high-degree vertices in the graph, and deletions for these vertices would necessitate O(n) additional work.

Linked Adjacency Lists

Linked Adjacency Lists

[Depree2013][Depree2013]

Each adjacency list is a chain.

Array Length = n
# of chain nodes = 2e (undirected graph)
# of chain nodes = e (digraph)

adjacency multilist

incidence list

[Rocca2006]

Edge lists

edge list

[Gotshalks2008]

[Grama2003]

[Lenharth2014]
[Sommer2010]

[Tangwongsan2012]

[Balkcom]

Edge lists

One simple representation is just a Python list of m edges, which we call an edge list. To represent an edge, we just give the numbers of the two vertices it’s incident on. Each edge in the list is either a Python list with two vertex numbers or a tuple comprising two vertex numbers. If the edge has a weight, add a third item giving the weight.

Edge lists are simple, but if we want to find whether the graph contains a particular edge, we have to search through the edge list. If the edges appear in the edge list in no particular order, that’s a linear search through m edges. Question to think about: How can you organize an edge list to make searching for a particular edge take O(log?m) time? The answer is a little tricky.

Cormen2014

Edge lists

For finding the neighbours of vertex v:
Edge List: O(|E|)
If the list is unsorted you need to check every edge to see if it comes from v
For a complete graph (where every vertex is connected to all other vertices) this would be O(|V|^2)

How can you organize an edge list to make searching for a particular edge take O(lgE) time? The answer is a little tricky.

Sort the list by the 1st vertex in each edge, and then by 2nd vertex in each edge.
The list is sorted, so we can now use a binary search on it.
Our comparison is a little bit more complicated now.
[v1,v2] < [v3,v4] if (v1 < v3) OR ( (v1 === v3) AND v2 < v4 )

If we have an edge [v1,v2] we do a binary search for [v1,v2] on the list. Time O(log E)

If your edges are not directed i.e. [v1,v2] is equivalent to [v2,v1] then perform a second search on the equivalent edge [v2,v1] if your first search wasn't successful. Double O(log E) is still O(log E).

[Lenharth2014]

Edge List

?Think of Edges not Nodes as primary
?Array of Edges (src,dst,data)
–May be sorted by src or dst
?Array of Node data
?May not be able to iterate edges by node
?Easy global iteration over edges

Compressed Edge lists
?Rather than storing integer indexes or pointers, store compressed data stream
?Decompress as iterating over edges
?E.g. Delta-encoding
–Each edge is stored as the delta from the previous edge
?1,4,7,9 -> 1,3,3,2
–Use fewer bytes for each edge (variable length encoding)

[Sommer2010]

Edge List

While being a space-ecient way to store the graph, the access times of an edge list are slower than the access times of an adjacency matrix (for most edges).

linkedlist

[Madduri2009]

linked list

In Chap. 3, we learned how to implement dynamic sequences. We can use any of the solutions presented there to produce a dynamic graph data structure. For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

Linked lists allow constant-time insertion and deletion of edges at arbitrary positions.

In the example in Fig. 8.1, we show circularly linked lists.

linkedlist

[Opendatastructures]

  • What type of collection should be used to store each element of [image]? One could use an array-based list, a linked-list, or even a hashtable.
  • Should there be a second adjacency list, [image], that stores, for each [image], the list of vertices, [image], such that [image]? This can greatly reduce the running-time of the [image] operation, but requires slightly more work when adding or removing edges.
  • Should the entry for the edge [image] in [image] be linked by a reference to the corresponding entry in [image]?
  • Should edges be first-class objects with their own associated data? In this way, [image] would contain lists of edges rather than lists of vertices (integers).

vertex list

[Grama2003]

[Grama2003]

VertexList

Adjacency list creation from graph file

[Wagner2012]

create an internal, linked list representation of an arbitrary graph

a program that will create an internal, linked list representation of an arbitrary graph. The graph can be either directed or undirected, with vertices and edges. There can be information attached to the edges as well as to the vertices.

a Java or C program that reads data about a graph (such as the one above) and constructs an adjacency list internal representation of this graph.

The example in the diagram above is a directed graph. For an undirected graph we just use a directed edge in each direction. (The graph of capitals above is undirected.) Again in the diagram above, the vertices (nodes of the graph) are represented by an array of nodes: Node [ ] graph = new Node[5];. The edges are represented by the vertices at either end; the first vertex is the vertex in the array and the second vertex is in the linked list of vertices linked to from the first vertex. It's very important to keep clear that, even though the linked list gives vertex numbers, these all represent edges. The vertices are all those at the end of a directed or undirected edge from the first vertex. These vertices in the linked list can appear in any order.


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)

maps

maps
[Schwarz2012]

Rotation maps
[Elite2010]


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)

Matrix

matrix

matrix representationof the graph

[Abiy2016]

adjacency matrices

We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is n2 for a graph of n nodes.

The following table summarizes the preferred representation for various operations:

operations | dense graph | sparse graph
lookup edge | adjacency matrix | either
find successor | either | adjacency list
find predeccessor | adjacency matrix | either

[Balkcom]

Adjacency matrices

For a graph with n vertices, an adjacency matrix is an n?×?n matrix of 0s and 1s, where the entry in row i and column j is 1 if and only if the edge (i,?j) is in the graph. (Recall that we can represent an n?×?n matrix by a Python list of n lists, where each of the n lists is a list of n numbers.) If you want to indicate an edge weight, put it in the row i, column j entry, and reserve a special value (say, None) to indicate an absent edge. Here’s a unweighted, undirected graph and its adjacency matrix:

With an adjacency matrix, we can find out whether an edge is present in constant time, by just looking up the corresponding entry in the matrix. So what’s the disadvantage of an adjacency matrix? Two things, actually. First, it takes Θ(n2) space, even if the graph is sparse: relatively few edges. In other words, for a sparse graph, the adjacency matrix is mostly 0s, and we use lots of space to represent only a few edges. Second, if you want to find out which vertices are adjacent to a given vertex i, you have to look at all n entries in row i, taking Θ(n) time, even if only a small number of vertices are adjacent to vertex i.

For an undirected graph, the adjacency matrix is symmetric: the row i, column j entry is 1 if and only if the row j, column i entry is 1. For a directed graph, the adjacency matrix need not be symmetric.

[Beard]

matrix representations

A matrix is just a simple 2 dimensional array. Assuming you have vertex ID's that can be represented as an int array like this:

int[][] adjacencyMatrix = new int[SIZE][SIZE]; // SIZE is the number of vertices in our graph
adjacencyMatrix[0][1] = 30; // sets the weight of a vertex 0 that is adjacent to vertex 1

This is commonly used for dense graphs where index access is necessary. You can represent a un/directed and weighted structure with this.
[Cao2016]

[Depree2013]

[Yin2004]
[Emms2006]

Adjacency Matrix

[Abiy]

adjacency matrices

We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is n2 for a graph of n nodes.

Adjacency matrices are good for rather dense graphs.

An n-node graph can be represented by an n×n adjacencymatrix A. Ai j is 1 if (i, j) ∈ E and 0 otherwise. Edge insertion or removal and edge querieswork in constant time.

It takes time O(n) to obtain the edges entering or leaving a node. This is only efficient
for very dense graphs with m = W??n2

The storage requirement is n2 bits.

For very dense graphs, this may be better than the n+m+O(1) words required for adjacency
arrays. However, even for dense graphs, the advantage is small if additional edge information is needed.

We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is for a graph of nodes.

adjacency matrix

Each cell aij of an adjacency matrix contains 1, if there is an edge between i-th and j-th vertices, and 0 otherwise.

adjacency matrix is a good solution for dense graphs, which implies having constant number of vertices.

Adjacency matrix is optimal for dense graphs, but for sparse ones it is superfluous.

Advantages.

Adjacency matrix is very convenient to work with. Add (remove) an edge can be done in O(1) time, the same time is required to check, if there is an edge between two vertices.

Also it is very simple to program

Disadvantages.

  • Adjacency matrix consumes huge amount of memory for storing big graphs. All graphs can be divided into two categories, sparse and dense graphs. Sparse ones contain not much edges (number of edges is much less, that square of number of vertices, |E| << |V|2). On the other hand, dense graphs contain number of edges comparable with square of number of vertices.
  • in many algorithms you need to know the edges, adjacent to the current vertex. To draw out such an information from the adjacency matrix you have to scan over the corresponding row, which results in O(|V|) complexity. For the algorithms like DFS or based on it, use of the adjacency matrix results in overall complexity of O(|V|2), while it can be reduced to O(|V| + |E|), when using adjacency list.
  • adjacency matrix requires huge efforts for adding/removing a vertex. In case, a graph is used for analysis only, it is not necessary, but if you want to construct fully dynamic structure, using of adjacency matrix make it quite slow for big graphs.

Adjacency Matrix

Adjacency matrix for undirected graph is always symmetric. Adjacency Matrix is also used to represent weighted graphs. If adj[i][j] = w, then there is an edge from vertex i to vertex j with weight w.

Pros: Representation is easier to implement and follow. Removing an edge takes O(1) time. Queries like whether there is an edge from vertex ‘u’ to vertex ‘v’ are efficient and can be done O(1).

Cons: Consumes more space O(V^2). Even if the graph is sparse(contains less number of edges), it consumes the same space. Adding a vertex is O(V^2) time.

Adjacency Matrix

Adjacency matrix of a digraph need not be symmetric

How much storage does the adjacency matrix require?
?? Answer: O(|V|2)
?? O(|V|) time to find vertex degree and/or vertices adjacent to a given vertex

The adjacency matrix is a dense representation
?? Usually too much storage for large graphs
?? But can be very efficient for small graphs
?? If graph is unweighted, there is an additional advantage in storage for the adjacency matrix presentation; rather than using one word of computer memory for each matrix entry, the adjacency matrix uses only one bit per entry.

[AHUJA1993]

(Node-Node) Adjacency Matrix

page 33

The node-node adjacency matrix representation, or simply the adjacency matrix representation, stores the network as an n x n matrix ? = {hij}. The matrix has a row and a column corresponding to every node, and its ij th entry hij equals 1 if (i, j) ∈ A and equals 0 otherwise. Figure 2.15 specifies this representation for the network shown in Figure 2.13. If we wish to store arc costs and capacities as well as the network topology, we can store this information in two additional n x n matrices, ? and ??.

The adjacency matrix has n2 elements, only m of which are nonzero. Consequently, this representation is space efficient only if the network is sufficiently dense; for sparse networks this representation wastes considerable space.

Nevertheless, the simplicity of the adjacency representation permits us to use it to implement most network algorithms rather easily.

We can determine the cost or capacity of any arc (i, j) simply by looking up the ij th element in the matrix ? or ??.

We can obtain the arcs emanating from node i by scanning row i: If the jth element in this row has a nonzero entry, (i, j) is an arc of the network. Similarly, we can obtain the arcs entering node j by scanning columnj: If the ith element of this column has a nonzero entry, (i,j) is an arc of the network. These steps permit us to identify all the outgoing or incoming arcs of a node in time proportional to n. For dense networks we can usually afford to spend this time to identify the incoming or outgoing arcs, but for sparse networks these steps might be the bottleneck operations for an algorithm.

?

[AlgoList]

Adjacency matrix

Each cell aij of an adjacency matrix contains 1, if there is an edge between i-th and j-th vertices, and 0 otherwise.

Adjacency matrix is a good solution for dense graphs, which implies having constant number of vertices.

Adjacency matrix is optimal for dense graphs, but for sparse ones it is superfluous.

Advantages.

Adjacency matrix is very convenient to work with. Add (remove) an edge can be done in O(1) time, the same time is required to check, if there is an edge between two vertices.

Also it is very simple to program

Disadvantages.

  • Adjacency matrix consumes huge amount of memory for storing big graphs. All graphs can be divided into two categories, sparse and dense graphs. Sparse ones contain not much edges (number of edges is much less, that square of number of vertices, |E| << |V|2). On the other hand, dense graphs contain number of edges comparable with square of number of vertices.
  • in many algorithms you need to know the edges, adjacent to the current vertex. To draw out such an information from the adjacency matrix you have to scan over the corresponding row, which results in O(|V|) complexity. For the algorithms like DFS or based on it, use of the adjacency matrix results in overall complexity of O(|V|2), while it can be reduced to O(|V| + |E|), when using adjacency list.
  • adjacency matrix requires huge efforts for adding/removing a vertex. In case, a graph is used for analysis only, it is not necessary, but if you want to construct fully dynamic structure, using of adjacency matrix make it quite slow for big graphs.
?

[Barnwal]

Adjacency Matrix

Adjacency matrix for undirected graph is always symmetric. Adjacency Matrix is also used to represent weighted graphs. If adj[i][j] = w, then there is an edge from vertex i to vertex j with weight w.

Pros: Representation is easier to implement and follow. Removing an edge takes O(1) time. Queries like whether there is an edge from vertex ‘u’ to vertex ‘v’ are efficient and can be done O(1).

Cons: Consumes more space O(V^2). Even if the graph is sparse(contains less number of edges), it consumes the same space. Adding a vertex is O(V^2) time.

[Basel2005]

Adjacency Matrix

Assume V = {1, 2, …, n}
An adjacency matrix represents the graph as a n × n matrix A:
A[i, j] = 1 if edge(i, j) ∈ E (or weight of edge)
A[i, j] = 0 if edge(i, j) ? E

Adjacency matrix of an undirected graph is symmetric

Diagonal entries are zero

A(i, j) = A(j, i) for all i and j

Adjacency matrix of a digraph need not be symmetric

How much storage does the adjacency matrix require?
Answer: O(|V|2)
O(|V|) time to find vertex degree and/or vertices adjacent to a given vertex

The adjacency matrix is a dense representation
Usually too much storage for large graphs
But can be very efficient for small graphs
If graph is unweighted, there is an additional advantage in storage for the adjacency matrix presentation; rather than using one word of computer memory for each matrix entry, the adjacency matrix uses only one bit per entry.

?

[Black2015]

adjacency-matrix representation

(data structure)

Definition: A representation of a directed graph with n vertices using an n × n matrix, where the entry at (i,j) is 1 if there is an edge from vertex i to vertex j; otherwise the entry is 0. A weighted graph may be represented using the weight as the entry. An undirected graph may be represented using the same entry in both (i,j) and (j,i) or using an upper triangular matrix.

Aggregate parent (I am a part of or used in ...)
graph.

See also adjacency-list representation, dense graph.

Note: Suppose we have a directed graph with four vertices. Here are adjacency-matrix and adjacency-list representations. The arrow (->) means a link in a list.

    1 2 3 4
 1  1 1 1 1
 2  1 0 0 0
 3  0 1 0 1
 4  0 1 1 0

 1  -> 1 -> 2 -> 3 -> 4
 2  -> 1
 3  -> 2 -> 4
 4  -> 2 -> 3

The adjacency-list representation is more compact for a sparse matrix.

[Brisaboa2007]

WebGraph Framework, by Boldi and Vigna [6]. It is associated to the site http://webgraph.dsi.unimi.it

compressed graph representations

  • WebGraph compression method
  • Pair compression [18] on the adjacency lists

adjacency matrix of a Web graph

The adjacency matrix of a Web graph of n pages is a square matrix faijg of n ￡ n, where each row and each col- umn represents a Web page. Cell aij is 1 if there is a hy- perlink in page i towards page j, and 0 otherwise.

properties of the adjacency matrix

  • As on average there are about 15 links per Web page, this matrix is extremely sparse.
  • Due to locality of reference, many 1s are placed around the main diagonal (that is, page i has many pointers to pages nearby i).
  • Due to the copy prop- erty, similar rows are common in the matrix.
  • Finally, due to skewness of distribution, some rows and colums have many 1s, but most have very few.
  • regularity properties of the adjacency matrix of the Web graphs, such as
    • horizontal,
    • vertical, and
    • diagonal runs.

clustering of the adjacency matrix

compact tree representation of the matrix

  • compact representation of the adjacency matrix that exploits its sparseness and clustering properties.
  • The representation is designed to compress large matrix ar- eas with all 0s into very few bits.
  • the technique offers a relevant space/time tradeoff to represent Web graphs, that is, it is much faster than those that take less space, and much smaller than those that o?er faster navigation.
    Furthermore, we show that our representation allows for other queries on the graph not usually considered in com pressed graph representations.
  • very e±cient to represent large empty areas of the matrix,
  • but at the same time allows e±cient forward and backward navigation of the graph.
  • An elegant feature of our solution is that it is symmetric, in the sense that forward and backward navigation are carried out by similar means and achieve similar times.
  • We represent the whole adjacency matrix via the k2-tree using two bit arrays we call T (tree) and L (leaves):
    • T: This bit array stores all the bits of the k2-tree except those in the last level. The bits of the k2-tree are placed following a levelwise traversal of the tree. We will represent ˉrst the k2 binary values of the children of the root node, then the values of the second level, and so on.
    • L: This bit array stores the last level of the tree. Thus it represents the value of (some) original cells of the adjacency matrix.
  • We represent the adjacency matrix by a k2-ary tree, which we call k2-tree, of height h = dlogk ne. Each node contains a single bit of data: 1 for the internal nodes and 0 for the leaves, except for the last level of the tree, where all are leaves and represent some bit values of the matrix. corresponds to the root; its k2 children are represented at level 1. Each child is a node and therefore it has a value 0 or 1. All internal nodes in the tree (i.e., with value 1) have exactly k2 children, whereas leaves (with value 0 or at the last tree level) have no children.
  • Assume for simplicity that n is a power of k; we will soon remove this assumption.
  • Conceptually, we start dividing the adjacency matrix into k2 submatrices of the same size, that
    is, k rows and k columns of submatrices of size n2=k2.
  • Each of the resulting k2 submatrices will be a child of the root node and its value will be 1 i? in the cells of the submatrix there is at least one 1. A 0 child means that the submatrix has all 0s and therefore the tree decomposition ends there; thus 0s are leaves in our tree.
  • The children of a node are ordered in the tree starting with the submatrices in the ˉrst (top) row, from left to right, then the submatrices in the second row from left to right, and so on.
  • Once the level 1 of the tree, with the children of root, has been built, the method proceeds recursively for each child with value 1, until we reach submatrices full of 0s, or we reach the cells of the original adjacency matrix. In the last level of the tree, the bits of the nodes correspond
    to the matrix cell values.
  • Figure 1 illustrates a 22-tree for a 4 ￡ 4 matrix.
  • A larger k induces a shorter tree, with fewer levels, but with more children per internal node.
  • If n is not a power of k, we conceptually extend our matrix to the right and to the bottom with 0s, making it of width n0 = kdlogk ne. This does not cause a signiˉcant overhead as our technique is e±cient to handle large areas of 0s.
  • Figure 2 shows an example of the adjacency matrix of a Web graph (we use the ˉrst 11￡11 submatrix of graph CNR [6]), and how it is expanded to an n0 ￡ n0 matrix for n0 a power of k = 2 (at the left) and of k = 4 (at the right). The ˉgure also shows the trees corresponding to those k values. Notice that the last level of the tree represents cells in the original adjacency matrix, but most empty cells in the original adjacency matrix are not represented in this level because, where a large area with 0s is found, it is represented by a single 0 in a smaller level of the tree.

Navigating with a k2tree

To obtain the pages pointed by a speciˉc page p, that is, to ˉnd direct neighbors of page p, we need to ˉnd the 1s in row p of the matrix. We start at the root and travel down the tree, choosing exactly k children of each node. We start with an example and then generalize in the next section.

[Chen2012]

adjacency matrix

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 1 Matrix: (n) (to go through a binary string of length n)

But the matrix representation of course has its own advantage: To decide if (u; v) 2 E, it only uses O(1) time

If the algorithm uses a lot of random access of edges in G, then the matrix representation may perform better.

[Chu-Carroll 2007]

boolean adjacency matrix

The boolean adjacency matrix is very compact – you can get away with as little as N2/2 bits of storage to represent the edges in a graph.

Certain algorithms – like transitive closure – are extremely efficient in the adjacency matrix.

If you really only need to know the structure of the edges, and you don’t have other data that needs to be
associated with the edges, then an adjacency matrix can be an extremely good choice. If your matrix is moderately sized, you can often get the entire adjacency matrix into the cache at once, which has a dramatic impact on performance.

Even if you need to associate a little bit of information with an edge, that’s often easily doable using an adjacency matrix. For example, to represent a weighted graph, you can use the edge-weight as the value of the matrix entry if there is an edge. (This does require that you be able to identify a value which will absolutely never be an edge weight, to use to mark cells that are not edges. If you’re using floating point numbers for weight, then NaN is a good choice.)

On the other hand, if you have a very large matrix with very few edges, then an adjacency matrix will perform very poorly and waste an enormous amount of space. Consider a graph with 1 million vertices, and 1 million edges. That means that each vertex has, on average, two edges – but you’re using one million bits per vertex. That’s very wasteful, and dealing with a matrix of 1012 bits is not going to be particularly fast.

But if you want to know something about connectivity, or simple pathfinding in a relatively dense graph, then the adjacency matrix is usually the right choice.

I first saw the matrix representation of a graph when dealing with relations in a discrete math course.

We used them to decide certain properties, like whether a relation was reflexive, transitive and so on. Great stuff.

Adjacency matrices are also useful when doing ‘relaxation’ of edges, such as Dijkstra’s – you start with a weighted adjacency matrix, and end up with a matrix of distances from any node to any other.

[Codish2013]

canonical adjacency matrix

[Cormen2014]

Adjacency matrices

For finding the neighbours of vertex v:

Adjacency Matrix: O(|V|)
You need to check the the row for v, (which has |V| columns) to find which ones are neighbours

If you represent your adjacency matrix as a hash table, you can get very good lookup times without using n^2 memory.

[Cornell2011]

adjacency matrix

Another common representation is an adjacency matrix, which is a two-dimensional array, where Ai j is non-zero when there is an edge (vi, vj) ∈ E.

[Depree2013]

Adjacency Matrix

O(n) time to find vertex degree and/or vertices adjacent to a given vertex.

Cost adjacency matrix. C(i,j) = cost of edge (i,j)

[Grama2003]

Adjacency matrices

Adjacency matrices have a value ai;j = 1 if nodes i and j share an edge; 0 otherwise. In case of a weighted graph, ai;j = wi;j, the weight of the edge.

[Huan2005]

Canonical adjacency matrix

Canonical adjacency matrix of labeled graphs
We represent each graph by an adjacency matrix M such that every diagonal entry of M is filled with the
label of the corresponding node and every off-diagonal entry is filled with the label of the corresponding
edge, or zero if there is no edge. This is slightly different from the standard adjacency matrix representation for unlabeled graphs (Cormen et al., 2001).

[Kempe2016]

adjacency matrix

2. Via an adjacency matrix: Store an n × n matrix (two-dimensional array) A. In position A[u, v], store
whether there is an edge from u to v. (This could be a boolean value, or perhaps an integer storing the length, cost, or other information.)

What we store in position A[u, u] depends on what our graph is modeling. In some cases, it makes sense to treat it as though there were an edge from u to itself, in other cases not so much. There is no rule that forces us to choose one or the other, and we should use whatever makes our computational task easiest.

1. For adding or removing nodes, an adjacency matrix has a bit more overhead, since changing the size of a matrix involves a bunch of reallocation and copying. For many applications that a computer scientist
is called upon to solve, changes in the set of nodes tend to be a bit rarer while other processing is
happening.

2. Testing whether the edge (u, v) exists in the graph is the specialty of adjacency matrices. It only involves one lookup in a known position of a 2-dimensional array, and thus takes O(1) time.

For an adjacency matrix, we don’t have this information stored, so we have to loop through the entire
row (or column) of the node u, and find all the entires that are 1 or true. This will take (n), which
can be much worse if the degrees are pretty small.

For the adjacency matrix, we need to store an n × n array, which obviously requires (n2) memory.

[Kolter2016]

Adjacency matrix

Store the connectivity of the graph as a matrix
In virtually all cases, you will want to store this as a sparse matrix
Pros/cons depend on which sparse matrix format you use, but most operations on a static graph will but much faster using the right format

[Kudase2016]

Adjacency Matrix

Adjacency Matrix: The adjacency matrix structure augments the edge list structure with a matrix where each row and column corresponds to a vertex. It is a two dimensional matrix form where the rows represent source vertices and columns represent destination vertices. Data on edges and vertices is stored externally. Between each pair of vertices, cost of one edge is to be stored. This shows which vertices are adjacent to one another. We know that two vertices are said to be adjacent if there is an edge connecting them. For a graph of n vertices, the dimensions of adjacency matrix will be n*n.

In case of directed graph, suppose if vertex j is adjacent to vertex i then there will be an edge from i to j and vice-versa. For a given vertex i, its adjacent vertices will be determined by looking at the row entry (i, [1…n]) of the matrix. If the value is true then it indicates that there exists an edge from i to j and false indicates no edge exists.

In case of undirected graph, the matrix values will be populated with Boolean values. The values of (i, j) and (j, i) are equal which means adjacency matrix for undirected graph is always symmetric along the diagonal.

In weighted graph, the Boolean values will be the costs of the edges connecting two vertices of a graph. Generally adjacency matrix is used to represent weighted graphs. If adj[i][j] = w , then we will say that there is an edge from vertex i to vertex j with weight w (can be any positive number). There are some cases where zero can also be the possible weight of the edge, then we have to store some sentinel value for non-existent edge, which can be a negative value; since the weight of the edge is always a positive number.

An adjacency matrix requires an n2 element array so for parse graphs much of the matrix will be empty. Also, for undirected graphs half of the graph is repeated information. Hence these matrices are said to be space inefficient.

The memory use of an adjacency matrix is O(n2) where n = number of vertices.

Advantages of using adjacency matrix are as follows:
? Easy to understand, implement and convenient to work with.
? Removing an edge involves time complexity of O(1).
? Queries like whether there is an edge from vertex ?u? to vertex ?v? are efficient and require time complexity, O(1).

Disadvantages of using adjacency matrix are as follows:
? Space complexity is of the O(V2) where V = number of vertices.
? Sparse matrix has less number of edges but the space complexity is still the same.
? Adding an edge involves time complexity of O(V2).
? If the number of nodes in the graph may change, matrix representation is too inflexible (especially if we don?t know the maximal size of the graph).

This is preferred if the graph is of dense type where |E| ~ V2.

[Lee2012]

Lee Visualizing Adjacency Matrices in Python

15th November 2012

Conrad Lee

https://sociograph.blogspot.com/2012/11/visualizing-adjacency-matrices-in-python.html

[Lenharth2014]

Adjacency matrix
Adjacency Matrix -- operations
Easy
?Iterate nodes
?Edges by src
?Edges by dst
?Loopup by src, dst
?Add Edge
?Delete edge
Hard
?Add node
?Delete node

Adjacency Matrix -- Costs
?Lookups: O(1)
?Iterations: array iteration
?Edge addition: O(1)
?Edge removal: O(1)
?Space: O(N^2)
–Good for dense graphs

[Nelson]

  • Adjacency matrix
    • Is (u,v) an edge? -- O(1)
    • Successors (u) -- O(N)
    • Predecessor (u) -- O(N)
    • Space -- O(N^2) (bits) to store the matrix
    • Best for dense graphs (E ~= N^2)

[Sommer2010]

Adjacency matrix

For instance, a matrix wastes a lot of memory if a sparse graph is given, but it has optimal access times for any type of graph.

[stoimen2012]

Adjacency Matrix

In case of directed graph, we can use 1 for the edge (i,j) and -1 for (j,i) in case the edge is directed from i to j. For a weighted directed graph we can put the weights instead of 1s.

In case that we’re using adjacency matrix we have:

  1. Adding an edge – O(1);
  2. Deleting an edge – O(1);
  3. Answering the question “is there an edge between i and j” – O(1);
  4. Finding the successors of a given vertex – O(n);
  5. Finding (if exists) a path between two vertices – O(n2);

[suanfazu2015]

matrix
A matrix is just a simple 2 dimensional array. Assuming you have vertex ID's that can be represented as an int array like this:

int[][] adjacencyMatrix = new int[SIZE][SIZE];
// SIZE is the number of vertices in our graph
adjacencyMatrix[0][1] = 30;
// sets the weight of a vertex 0 that is adjacent to vertex 1

This is commonly used for dense graphs where index access is necessary. You can represent a un/directed and weighted structure with this.

[Vallon2016]

Adjacency matrix:

Data are stored in a two-dimensional matrix, in which the rows represent source vertices and columns represent destination vertices. The data on the edges and vertices must be stored externally.

Complexity

Adjacency matrix | ? | ? | ?
Storage | Add Vertex | Add Edge | Query
O(|V|^2) | O(|V|^2) | O(1) | O(1)

[Wang2012]

adjacency matrix

The adjacency matrix is an n  n matrix where the non-diagonal entry aij is the weight value from vertex i to vertex j, and the diagonal entry aii can be used to count loops on single vertices. For most large-scale
graphs, the resulting matrix is typically sparse; representing it directly as a sparse matrix allows the use of existing libraries for sparse matrix operations such as cuSparse. Katz et al.11 represent the adjacency matrix as a 2D texture in GPU memory. The downside of such a representation is its waste of space.

[Zanibbi2009]

Adjacency Matrix

Checking if (u, v) is an edge takes Θ(1) time.
Identifying all edges takes Θ(n2) time.

canonical adjacency matrix

Weighted Adjacency Matrix
https://reference.wolfram.com/language/ref/WeightedAdjacencyMatrix.html

incidence matrix

[AHUJA1993]

(Node-Arc) Incidence Matrix

The node-arc incidence matrix representation, or simply the incidence matrix representation, represents a network as the constraint matrix of the minimum cost flow problem that we discussed in Section 1.2. This representation stores the network as an n x m matrix ?? which contains one row for each node of the network and one column for each arc. The column corresponding to arc (i,j) has only two nonzero elements: It has a + 1 in the row corresponding to node i and a -I in the row corresponding to node j. Figure 2.14 gives this representation for the network shown in Figure 2.13.

The node-arc incidence matrix has a very special structure: Only 2m out of its nm entries are nonzero, all of its nonzero entries are + 1 or - 1, and each column has exactly one + 1 and one -1. Furthermore, the number of + 1 's in a row equals the outdegree of the corresponding node and the number of - 1 's in the row equals the indegree of the node.

Because the node-arc incidence matrix ?? contains so few nonzero coefficients, the incidence matrix representation of a network is not space efficient. More efficient schemes, such as those that we consider later in this section would merely keep track of the nonzero entries in the matrix. Because of its inefficiency in storing the underlying network topology, use of the node-arc incidence matrix rarely produces efficient algorithms.

This representation is important, however, because it represents the constraint matrix of the minimum cost flow problem and because the node-arc incidence matrix possesses several interesting theoretical properties.

?

[Claude2007]

incidence matrix

Standard graph representations such as the incidence matrix require n(n? 1)/2 bits, for undirected graphs. For directed graphs the numbers are n2 .

[Gotshalks2008]
[Gross2003]

[Rocca2006]

Kirchhoff Matrix

https://reference.wolfram.com/language/ref/KirchhoffMatrix.html

Laplacian matrix
[Emms2006]

[Cao2016]

PPMI matrix

the original PPMI matrix itself is an explicit representation matrix of the graph

pointwise mutual information (PMI) matrix

positive pointwise mutual information (PPMI) matrix

matrix R representing the vertices of graph G by capturing deep structural information.

co-occurrence matrix / collections of linear sequences / via DeepWalk

DeepWalk proposed by Perozzi et al. (2014) presented an idea to transform unweighted
graphs into collections of linear sequences by a uniform sampling method known as truncated random walk.

DeepWalk (Perozzi, Al-Rfou, and Skiena 2014) is a recently proposed method to learn representations of networks. It transforms a graph structure into linear sequences by truncated random walks and processes the sequences using skip-gram with hierarchical softmax.

In their approach, sampled vertex sequences characterize the connections between vertices in a graph. This step can be understood as a process for converting a general graph structure into a large collection of linear structures.

Next, they utilized the skip-gram model proposed by Mikolov et al. (2013) to learn low-dimensional representations for vertices from such linear structures. The learned vertex representations were shown to be effective across a few tasks, outperforming several previous approaches such as spectral clustering and modularity method (Tang and Liu 2009a; 2009b; 2011; Macskassy and Provost 2003).

DeepWalk yields a co-occurrence matrix based on the sampled linear sequences.

probabilistic co-occurrence matrix

In Section 3, we describe our random surfing model that directly construct a probabilistic co-occurrence matrix from a weighted graph, which avoids the expensive sampling process.

random surfing model suitable for weighted graphs, which can directly yield a probabilistic
co-occurrence matrix. Such a matrix is similar to the cooccurrence matrix obtained by sampling linear sequences from graphs (Bullinaria and Levy 2007), but no sampling process is required in our approach.

Representing graphs with orthogonal matrices

[Emms2006]

Flat Sparse Matrix

[Slesarenko2015]


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objects
linked-edge-objects representation

objects and pointers

[Beard]

objects and pointers

These are just basic data structures like hammar said in the other answer, in Java you would represent this with classes like edges and vertices. For example an edge connects two vertices and can either be directed or undirected and it can contain a weight. A vertex can have an ID, name etc. Mostly both of them have additional properties. So you can construct your graph with them like

Vertex a = new Vertex(1);
Vertex b = new Vertex(2);
Edge edge = new Edge(a,b, 30); // init an edge between ab and be with weight 30

This approach is commonly used for object oriented implementations, since it is more readable and convenient for object oriented users ;).

Objects and pointers is mostly the same as adjacency list, at least for the purpose of comparing algorithms that use these representations.

Compare

struct Node {
    Node *neighbours[];
};

with

struct Node {
    Node *left;
    Node *right;
};

You can easily construct the list of neighbours on-the-fly in the latter case, if it is easier to work with than named pointers.

Advantage of the object representation (incidence list) is that two adjacent vertices share the same instance of the edge. This makes it easy to manipulate with undirected edge data (length, cost, flow or even direction). However it uses extra memory for pointers.

[suanfazu2015]

objects and pointers / object representation

objects and pointers
These are just basic datastructures like hammar said in the other answer, in Java you would represent this with classes like edges and vertices. For example an edge connects two vertices and can either be directed or undirected and it can contain a weight. A vertex can have an ID, name etc. Mostly both of them have additional properties. So you can construct your graph with them like

Vertex a = new Vertex(1);
Vertex b = new Vertex(2);
Edge edge = new Edge(a,b, 30); // init an edge between ab and be with weight 30

This approach is commonly used for object oriented implementations, since it is more readable and convenient for object oriented users

Objects and pointers is mostly the same as adjacency list, at least for the purpose of comparing algorithms that use these representations.
Compare

struct Node {
    Node *neighbours[];
};

with

struct Node {
    Node *left;
    Node *right;
};

You can easily construct the list of neighbours on-the-fly in the latter case, if it is easier to work with than named pointers.

Advantage of the object representation (incidence list) is that two adjacent vertices share the same instance of the edge. This makes it easy to manipulate with undirected edge data (length, cost, flow or even direction). However it uses extra memory for pointers.


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Polynomials

Graph Polynomials

[Trinks2012]


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Printable Format

Printable Format
[Joy1987]


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row

Compressed row storage

[Lenharth2014]

Compressed row storage
Compressed Sparse Row Storage
?Try to combine space efficiency of Lists with array traversal for edges
?Store Node data in an array
?Store all edges in an array (sorted by src)
?Store an array of pointers to edges
–Indexed by node id
–One pointer per node

CSR – Operations
Easy
?Iterate nodes
?Edges by src
?Add node?
Hard
?Edges by dst
?Add Edge
?Delete Edge
?Loopup by src, dst
–Linear seach
?Delete node

CSR – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Array iteration
?Space: O(2N + E)
–Constant for E == sizeof(Edata) + sizeof(int)


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Rules

EdgeRules


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sequence

[8]

Edge Sequences

The edge sequence representation is good only in specialized situations.

In Chap. 3, we learned how to implement dynamic sequences. We can use any of the solutions presented there to produce a dynamic graph data structure. For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

[8]

Unordered Edge Sequences

Perhaps the simplest representation of a graph is as an unordered sequence of edges. Each edge contains a pair of node indices and, possibly, associated information such as an edge weight.Whether these node pairs represent directed or undirected edges is merely a matter of interpretation.

Sequence representation is often used for input and output.

It is easy to add edges or nodes in constant time.

However, many other operations, in particular navigation, take time theta(m), which is forbiddingly slow.

Only a few graph algorithms work well with the edge sequence representation;

most algorithms require easy access to the edges incident on any given node. In this case the ordered representations discussed in the following sections are appropriate.

This is even more compact than the 2m words needed for an edge sequence representation.

Edge arrays are a compact and efficient graph representation.

Their main disadvantage is that it is expensive to add or remove edges. For example, assume that we want to insert a new edge (u,v). Even if there is room in the edge array E to accommodate it, we still have to move the edges associated with nodes u+1 to n one position to the right, which takes time O(m).

[8]

ordered edge sequence representation

[Cao2016]

linear sequences

Although effective, the sampling method for transforming a graph structure into linear sequences has some weaknesses.


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set

adjacency set representation for unweighted graphs

associate a value with each out edge of a vertex

adjacency set representation for unweighted graphs

associate a value with each out edge of a vertex

associate each vertex with a table that maps each out-neighbor to its value

It would have type:
(eVal vertexTable) vertexTable .
The graph above would then be represented as:
G = f0 7! f1 7! 0.7, 2 7! 1.5g , 1 7! f2 7! ??2.0g , 2 7! fgg

Blelloch2012

edge set representation

The representation is similar to an edge list representation mentioned before, but it abstracts away from the particular data structure used for the set—the set could be based on a list, an array, a tree, or a hash table.

If we use the balanced-tree cost model for sets, for example, then determining if an edge is in the graph requires much less work than with an edge list— only O(log n) instead of (n) (i.e. following the list until the edge is found). The problem with edge sets, as with edge lists, is that they do not allow for an efficient way to access the neighbors of a given vertex v. Selecting the neighbors requires considering all the edges and picking out the ones that have v as an endpoint. Although with an edge set (but not an edge list) this can be done in parallel with O(logm) span, it requires (m) work even if the vertex has only a few neighbors.


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Stars

[AHUJA1993]

(Forward and Reverse) Star Representations

The forward star representation of a network is similar to the adjacency list representation in the sense that it also stores the node adjacency list of each node. But instead of maintaining these lists as linked lists, it stores them in a single array.

To develop this representation, we first associate a unique sequence number with each arc, thus defining an ordering of the arc list.

We number the arcs in a specific order: first those emanating from node 1, then those emanating from node 2, and so on.

We number the arcs emanating from the same node in an arbitrary fashion.

We then sequentially store information about each arc in the arc list. We store the tails, heads, costs, and capacities of the arcs in four arrays: tail, head, cost, and capacity. So if arc (i, j) is arc number 20, we store the tail, head, cost, and capacity data for this arc in the array positions tail(20), head(20), cost(20), and capacity(20).

We also maintain a pointer with each node i, denoted by point(i), that indicates the smallest numbered arc in the arc list that emanates from node i. [If node i has no outgoing arcs, we set point(i) equal to point(i + 1).] Therefore, the forward star representation will store the outgoing arcs of node i at positions point(i) to (point(i + 1) - 1) in the arc list. If point(i) > point(i + 1) - 1, node i has no outgoing arc. For consistency, we set point(l) = 1 and point(n + 1) = m + 1.

Figure 2. 17(a) specifies the forward star representation of the network given in Figure 2.13.

The forward star representation provides us with an efficient means for determining the set of outgoing arcs of any node.

To determine, simultaneously, the set of incoming arcs of any node efficiently, we need an additional data structure known as the reverse star representation. Starting from a forward star representation,
we can create a reverse star representation as follows. We examine the nodes i = 1 to n in order and sequentially store the heads, tails, costs, and capacities of the incoming arcs at node i. We also maintain a reverse pointer with each node i, denoted by rpoint(i), which denotes the first position in these arrays that contains information about an incoming arc at node i. [If node i has no incoming arc, we set rpoint(i) equal to rpoint(i + 1).] For sake of consistency, we set rpoint(l) = 1 and rpoint(n +.1) = m + 1. As before, we store the incoming arcs at node i at positions rpoint(i) to (rpoint(i + 1) - 1). This data structure gives us the representation shown in Figure 2.17(b).

Observe that by storing both the forward and reverse star representations, we will maintain a significant amount of duplicate information. We can avoid this duplication by storing arc numbers in the reverse star instead of the tails, heads, costs, and capacities of the arcs. As an illustration, for our example, arc (3, 2) has arc number 4 in the forward star representation and arc (1, 2) has an arc number 1. So instead of storing the tails, cos~s, and capacities of the arcs, we simply store arc numbers; and once we know the arc numbers, we can always retrieve the associated information from the forward star representation. We store arc Qumbers in an array trace of size m. Figure 2.18 gives the complete trace array of our example.

In our discussion of the adjacency list representation, we noted that sometimes while updating data for an arc (i, j), we also need to update data for its reversal (j, i). Just as we did in the adjacency list representation, we can accomplish this task by defining an array mate of size m, which stores the arc number of the reversal of an arc. For example, the forward star representation shown in Figure 2.17(a)
assigns the arc number 6 to arc (4, 5) and assigns the arc number 8 to arc (5, 4). Therefore, if we were using the mate array, we would set mate(6) = 8 and mate(8) = 6.

Storing Parallel Arcs

Both the adjacency list representation and the forward star representation data structures are capable of handling parallel arcs. If a node i has two outgoing arcs with the same head node but (possibly) different costs and capacities, the linked list of node i will contain two cells corresponding to these two arcs. Similarly, the forward star representation allows several entries with the same tail and head nodes but different costs and capacities.


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)

TABLE

edge-set table / adjacency table

Blelloch2012

More efficient neighbor access. In our second representation, we aim to get more efficiency in accessing to the neighbors of a vertex. This representation, which we refer to as an adjacency table, is a table that maps every vertex to the set of its neighbors. Simply put, it is an edge-set table.

Therefore, in this representation, accessing the neighbors of a vertex v is cheap: it just requires a lookup in the table. Assuming the balanced-tree cost model for tables, this can be done in O(log n) work and span. Once the neighbor set has been pulled out, mapping a constant work function over the neighbors can be done in O(dG(v)) work and O(1) span. Looking up if an edge is in the graph requires the same work and span as with edge sets: O(log n). This is because we can first look up one side of the edge in the table and then the second side in the set that is returned. Note that an adjacency list is a special case of adjacency table where the table of vertices is represented as an array and the set of neighbors is represented as a list.

[Deepa2014]

Table of Edges

An even simpler data structure is just to maintain an array or linked list of the edges. This is not as flexible as the other data structures at answering “who is adjacent to vertex x?” but it works just fine for certain simple procedures like Kruskal’s minimum spanning tree algorithm.

store node or edge information in a hash table.

INCIDENCE TABLE REPRESENTATION

[Gross2003]

[Gross2003]

INCIDENCE TABLE REPRESENTATION

An incidence table for a graph has a column indexed by each edge. The entries in the column for an edge are its endpoints. If the edge is a self-loop, then the endpoint appears twice.

[Park2014]

tabular representation / tabular form

the edges are expressed as a tabular form as shown in Figure 1 (b) (in-edge sorted in this case). Each entry in the table contains two vertex IDs (‘in’ for destination and ‘out’ for source) connected to the
edge and edge value (edge weight in this example).


Untitled Document

Graph Representation

(2017-07-01 -- 2018-07-01)

vectors

vector representation
[Cao2016]

vector representation for each vertex

[Cao2016]

vector representation / vertex representations of a unweighted graph

a model for learning graph representations, which generates a low-dimensional vector representation for each vertex by capturing the graph structural information.

One of effective means towards organizing such information associated with the potentially large and complex graph is to learn the graph representations, which assign to each vertex of the graph a low-dimensional dense vector representation, encoding meaningful information conveyed by the graph.

v-graph (vector graph)

[Wang2012]

v-graph (vector graph)

Blelloch3 proposes the v-graph (vector graph) for graph data representa- tion. This representation uses segmented vectors to store graph topology. For undirected graphs, it uses a single segmented vector to store edge information. Each segment corresponds to a vertex and each element within a segment corresponds to one of the edges of that vertex. For directed graphs, it uses two segmented vectors: one for the incoming edges, and one for the outgoing edges. Each element in the outgoing edges vector is a pointer to a position in the incoming edges vector. For both directed and undirected graphs, the representation uses additional vectors to include weights and other information. A graph can be con-
verted from most other representations into the v-graph representation by creating two elements per edge (one for each end) and sorting the edges according to their vertex number. Parallel sorting algorithms such as radix sort can be used to place all edges that belong to the same vertex in a contiguous segment. The cross-pointer array in this representation enables an O(1) step complexity of dynamic graph manipulations such as adding or deleting an edge or a vertex, which is not easily accomplished with the other representations.

Adjacency vectors

[Lenharth2014]

Adjacency vectors
?Replace Linked List with pointer to vector
–Resizable vector?
?Costs?
?Advantages?


GNU Scientific Library – Reference Manual: Sparse Matrices Compressed Format

Next: Sparse Matrices Conversion Between Sparse and Dense, Previous: Sparse Matrices Finding Maximum and Minimum Elements, Up: Sparse Matrices [Index]

41.11 Compressed Format

GSL supports compressed column storage (CCS) and compressed row storage (CRS) formats.

Function: gsl_spmatrix * gsl_spmatrix_ccs (const gsl_spmatrix * T)

This function creates a sparse matrix in compressed column format from the input sparse matrix T which must be in triplet format. A pointer to a newly allocated matrix is returned. The calling function should free the newly allocated matrix when it is no longer needed.

Function: gsl_spmatrix * gsl_spmatrix_crs (const gsl_spmatrix * T)

This function creates a sparse matrix in compressed row format from the input sparse matrix T which must be in triplet format. A pointer to a newly allocated matrix is returned. The calling function should free the newly allocated matrix when it is no longer needed.


Sparse Matrix Compression Formats

BCCS | Block Compressed Column Storage format
BCRS | Block Compressed Row Storage format
BND | Linpack Banded format
BSR | Block Sparse Row format
CCS | Compressed Column Storage format
COO | Coordinate format
CRS | Compressed Row Storage format
CSC | Compressed Sparse Column format
CSR | Compressed Sparse Row format
DIA | Diagonal format
DNS | Dense format
ELL | Ellpack-Itpack generalized diagonal format
JAD | Jagged Diagonal format
LNK | Linked list storage format
MSR | Modified Compressed Sparse Row format
NSK | Nonsymmetric Skyline format
SSK | Symmetric Skyline format
SSS | Symmetric Sparse Skyline format
USS | Unsymmetric Sparse Skyline format
VBR | Variable Block Row format

Example

Uncompressed Matrix

Nj
A=
11 | 12 | 13 | 14 | 0 | 0
0 | 22 | 23 | 0 | 0 | 0
0 | 0 | 33 | 34 | 35 | 36
0 | 0 | 0 | 44 | 45 | 0
0 | 0 | 0 | 0 | 0 | 56
0 | 0 | 0 | 0 | 0 | 66
Ni

Variables
i | Row index
j | Column index
k | Element index in compressed data vector
a(i,j) | Element at matrix row i, column j
Abbreviations
N | Number of elements per side of the matrix
NB | Number of elements per side of the Block
NDZ | Number of Diagonal Zeros
NNZ | Number of Non-Zeros
NNZB | Number of Non-Zero Blocks
NR | Number of blocks per side of the matrix
O | Order of magnitude

Compressed Row Storage / Compressed Sparse Row

 | i | 1 |  |  |  | 2 |  | 3 |  |  |  | 4 |  | 5 | 6 | 7 | O
Row Start Index | k | 1 |  |  |  | 5 |  | 7 |  |  |  | 11 |  | 13 | 14 | 15 | Ni+1
 | k | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 |  |
Column Index | j | 1 | 2 | 3 | 4 | 2 | 3 | 3 | 4 | 5 | 6 | 4 | 5 | 6 | 6 |  | NNZ
Data | a(i,j) | 11 | 12 | 13 | 14 | 22 | 23 | 33 | 34 | 35 | 36 | 44 | 45 | 56 | 66 |  | NNZ
Row Start Index : | 1 ≤ i ≤ Ni | : | if Data(k) = a(i,j) then RowStartIndex(i) ≤ k < RowStartIndex(i+1)
 | i = Ni+1 | : | k = NNZ+1
Order is 2*NNZ + Ni + 1 (=35)

Compressed Column Storage / Compressed Sparse Column / Harwell-Boeing Sparse Matrix

 | j | 1 | 2 |  | 3 |  |  | 4 |  |  | 5 |  | 6 |  |  | 7 | O
Column Start Index | k | 1 | 2 |  | 4 |  |  | 7 |  |  | 10 |  | 12 |  |  | 15 | Nj+1
 | k | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 |  |
Row Index | i | 1 | 1 | 2 | 1 | 2 | 3 | 1 | 3 | 4 | 3 | 4 | 3 | 5 | 6 |  | NNZ
Data | a(i,j) | 11 | 12 | 22 | 13 | 23 | 33 | 14 | 34 | 44 | 35 | 45 | 36 | 56 | 66 |  | NNZ
Column Start Index : | 1 ≤ j ≤ Nj | : | if Data(k) = a(i,j) then ColumnStartIndex(j) ≤ k < ColumnStartIndex(j+1)
 | j = Nj+1 | : | k = NNZ+1
Order is 2*NNZ + Nj + 1 (=35)

Modified Compressed Sparse Row

 | k | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | O
Index | k;j | 8 | 11 | 12 | 15 | 16 | 17 | 17 | 2 | 3 | 4 | 3 | 4 | 5 | 6 | 5 | 6 | NNZ+NDZ+1
Data | a(i,j) | 11 | 22 | 33 | 44 | 0 | 66 |  | 12 | 13 | 14 | 23 | 34 | 35 | 36 | 45 | 56 | NNZ+NDZ+1
k | Index | Data
1 ≤ k ≤ Ni | Row Start Index | a(k,k)
Ni+1 | NNZ+NDZ+1
Ni+2 ≤ k ≤ NNZ+NDZ+1 | Column Index | a(i,j), i<>j
Order is 2*NNZ + 2*NDZ + 2 (=32)

Modified Compressed Sparse Column

 | k | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | O
Index | k;i | 8 | 8 | 9 | 11 | 13 | 15 | 17 | 1 | 1 | 2 | 1 | 3 | 3 | 4 | 3 | 5 | NNZ+NDZ+1
Data | a(i,j) | 11 | 22 | 33 | 44 | 0 | 66 |  | 12 | 13 | 23 | 14 | 34 | 35 | 45 | 36 | 56 | NNZ+NDZ+1
k | Index | Data
1 ≤ k ≤ Nj | Column Start Index | a(k,k)
Nj+1 | NNZ+NDZ+1
Nj+2 ≤ k ≤ NNZ+NDZ+1 | Row Index | a(i,j), i<>j
Order is 2*NNZ + 2*NDZ + 2 (=32)

Block Compressed Row Storage / Block Sparse Row

 | i | 1 |  |  |  | 2 |  |  |  | 3 |  | 4 | O
Row Start Index | k | 1 |  |  |  | 3 |  |  |  | 5 |  | 6 | NRi+1
 | k | 1 |  | 2 |  | 3 |  | 4 |  | 5 |  |  |
Column Index | j | 1 |  | 3 |  | 3 |  | 5 |  | 5 |  |  | NNZB
Data | a(i,j) | 11 | 12 | 13 | 14 | 33 | 34 | 35 | 36 | 0 | 56 |  | NNZB*NBi*NBj
 |  | 0 | 22 | 23 | 0 | 0 | 44 | 45 | 0 | 0 | 66
NRi = Ni/NBi
Order is NNZB*NBi*NBj + NNZB + NRi + 1 (=29)


Untitled Document

Graph Representation
Literature Index

(2017-07-01 -- 2018-07-01)

Books

Efficient Graph Representations (Fields Institute Monographs, 19) Hardcover – June 1, 2003 by Jeremy P. Spinrad (Author)

https://www.amazon.com/Efficient-Representations-Fields-Institute-Monographs/dp/0821828150

[Abiy]

Abiy Graph implementation and representation.docx

Thaddeus Abiy, Christopher Williams, Josh Silverman

https://brilliant.org/profile/thaddeus-kcchug/

https://brilliant.org/profile/christopher-i6sq4v/

https://brilliant.org/profile/josh-8t4vhp/

adjacency matrices

We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is n2 for a graph of n nodes.

Adjacency List

hashtable with an array

hashtable with linked lists

A common way to implement a graph using an adjacency list is to use either a hashtable with an array as values or use a hashtable with linked lists as a value. Since python combines the idea of arrays and linked lists we can easily implement this representation using a dictionary with nodes as keys and a list as a value.

However if the graphs is sparse, that is if most of the possible edges are not present, then the adjacency-list representation can save space.

To see why, note that an adjacency matrix for an n node graph has n2 bits, and therefore could be packed into n2/32-bit words. The common adjacency list cell will consist of two words, one for the node and one for the pointer to the next cell. Thus, if the number of edges is a , we need about 2a words for the lists, and n words for the array of headers. The adjacency list will use less space than the adjacency matrix if

n+2a<n2/32

The following table summarizes the preferred representation for various operations:

operations | dense graph | sparse graph
lookup edge | adjacency matrix | either
find successor | either | adjacency list
find predeccessor | adjacency matrix | either

Let us assume the graph is represented by adjacency lists, so we can find all edges in O(m) time.

?????????????????????????????????

??????????????????????????????????

[AHUJA1993]

AHUJA Network Flows Theory, Algorithms, and Applications Ch1_3 p103

Ahuja, R.K., Magnanti, T.L. and Orlin J.B. (1993) “Network Flows”, Prentice-Hall, NJ.

32

RAVINDRA K. AHUJA

http://www.ise.ufl.edu/ahuja/

Ravindra K. Ahuja

Professor
Co-Director SCaLE Center
Industrial and Systems Engineering
University of Florida
303 Weil Hall
P.O. Box 116595
Gainesville, FL 32611-6595

ahuja@ufl.edu

President & CEO,

Optym
7600 NW 5th Place, Gainesville, FL 32607

ravindra.ahuja@optym.com
Office: (352) 334-7283, ext: 347
Cell: (352) 870-8401
Fax: (866) 805-4130

THOMAS L. MAGNANTI

http://mitsloan.mit.edu/faculty-and-research/faculty-directory/detail/?id=41181

Thomas Magnanti

  • Institute Professor
  • Professor of Operations Research

  • 32-D784
  • (617) 253-6604
  • (617) 258-8682
  • magnanti@mit.edu
  • http://web.mit/edu/engineering/deans/magnanti.html

JAMES B. ORLIN

http://jorlin.scripts.mit.edu/

http://mitsloan.mit.edu/faculty-and-research/faculty-directory/detail/?id=15027

Jim Orlin

  • E. Pennell Brooks (1917) Professor in Management
  • Professor of Operations Research

  • E62-570
  • (617) 253-6606
  • (617) 258-7579
  • jorlin@mit.edu
  • http://jorlin.scripts.mit.edu/

Contact Information
Office: E62-570
e-mail: jorlin at mit dot edu

Tel: 617-253-6606
Fax: 617-258-7579

Support Staff
Name: Tyler Morse
Tel: 617-253-2656
E-mail: tamorse@mit.edu

∑ nnv ± n n

(Node-Node) Adjacency Matrix

page 33

The node-node adjacency matrix representation, or simply the adjacency matrix representation, stores the network as an n x n matrix ? = {hij}. The matrix has a row and a column corresponding to every node, and its ij th entry hu equals 1 if (i, j) ∈ A and equals 0 otherwise. Figure 2.15 specifies this representation for the network shown in Figure 2.13. If we wish to store arc costs and capacities as well as the network topology, we can store this information in two additional n x n matrices, C and U.

The adjacency matrix has n2 elements, only m of which are nonzero. Consequently, this representation is space efficient only if the network is sufficiently dense; for sparse networks this representation wastes considerable space.

Nevertheless, the simplicity of the adjacency representation permits us to use it to implement most network algorithms rather easily.

We can determine the cost or capacity of any arc (i, j) simply by looking up the ijth element in the matrix <f6 or OU.

We can obtain the arcs emanating from node i by scanning row i: If the jth element in this row has a nonzero entry, (i, j) is an arc of the network. Similarly, we can obtain the arcs entering node j by scanning columnj: If the ith element of this column has a nonzero entry, (i,j) is an arc of the network. These steps permit us to identify all the outgoing or incoming arcs of a node in time proportional to n. For dense networks we can usually afford to spend this time to identify the incoming or outgoing arcs, but for sparse networks these steps might be the bottleneck operations for an algorithm.

(Node-Arc) Incidence Matrix

The node-arc incidence matrix representation, or simply the incidence matrix representation, represents a network as the constraint matrix of the minimum cost flow problem that we discussed in Section 1.2. This representation stores the network as an n x m matrix .N which contains one row for each node of the network and one column for each arc. The column corresponding to arc (i,j) has only two nonzero
elements: It has a + 1 in the row corresponding to node i and a -I in the row corresponding to node j. Figure 2.14 gives this representation for the network shown in Figure 2.13.

The node-arc incidence matrix has a very special structure: Only 2m out of its nm entries are nonzero, all of its nonzero entries are + 1 or - 1, and each column has exactly one + 1 and one -1. Furthermore, the number of + 1 's in a row equals the outdegree of the corresponding node and the number of - 1 's in the row equals the indegree of the node.

Because the node-arc incidence matrix .N' contains so few nonzero coefficients, the incidence matrix representation of a network is not space efficient. More efficient schemes, such as those that we consider later in this section would merely keep track of the nonzero entries in the matrix. Because of its inefficiency in storing the underlying network topology, use of the node-arc incidence matrix rarely produces efficient algorithms.

This representation is important, however, because it represents the constraint matrix of the minimum cost flow problem and because the node-arc incidence matrix possesses several interesting theoretical properties.

Adjacency List:

page 25

The arc adjacency list A(i) of a node i is the set of arcs emanating from that node, that is, A(i) = {(i,j) ∈ A: j ∈N}.

Earlier we defined the arc adjacency list A(i) of a node i as the set of arcs emanating from that node, that is, the set of arcs (i, j) ∈ A obtained as j ranges over the nodes of the network.

The node adjacency list A(i) is the set of nodes adjacent to that node; in this case, A(i) = {j ∈ N: (i,j) ∈ A}.

Similarly, we defined the node adjacency list of a node i as the set of nodes j for which (i, j) ∈ A.

=================

The adjacency list representation stores the node adjacency list of each node as a singly linked list (we refer the reader to Appendix A for a description of singly linked lists). A linked list is a collection of cells each containing one or more fields. The node adjacency list for node i will be a linked list having 1 A (i) 1 cells and each cell will correspond to an arc (i, j) EA. The cell corresponding to the arc (i, j) will have as many fields as the amount of information we wish to store. One data field will store nodej. We might use two other data fields to store the arc cost Cij and the arc capacity Uij. Each cell will contain one additional
field, called the link, which stores a pointer to the next cell in the adjacency list. If a cell happens to be the last cell in the adjacency list, by convention we set its link to value zero.

Since we need to be able to store and access n linked lists, one for each node, we also need an array of pointers that point to the first cell in each linked list. We accomplish this objective by defining an n-dimensional array, first, whose element first(i) stores a pointer to the first cell in the adjacency list of node i. If the adjacency list of node i is empty, we set first(i) = O. Figure 2.16 specifies the adjacency list
representation of the network shown in Figure 2. 13.

In this book we sometimes assume that whenever arc (i,j) belongs to a network, so does the reverse arc (j, i). In these situations, while updating some information about arc (i, j), we typically will also need to update information about arc (j, i). Since we will store arc (i, j) in the adjacency list of node i and arc (j, i) in the adjacency list of node j, we can carry out any operation on both arcs efficiently if we know where to find the reversal (j, i) of each arc (i,j). We can access both arcs easily if we define an additional field, mate, that contains a pointer to the cell containing data for the reversal of each arc. The mate of arc (i, j) points to the cell of arc (j, i) and the mate of arc (j, i) points to the cell of arc (i, j).

Often, we shall omit the terms "arc" and "node" and simply refer to the adjacency list; in all cases it will be
clear from context whether we mean arc adjacency list or node adjacency list.

We assume that arcs in the adjacency list A(i) are arranged so that the head nodes of arcs are in increasing order.

Notice that | A(i)|I equals the outdegree of node i. Since the sum of all node outdegrees equals m, we immediately obtain the following property:

Property 2.1. ∑ i ∈ N | A(i) | = m.

(Forward and Reverse) Star Representations

The forward star representation of a network is similar to the adjacency list representation in the sense that it also stores the node adjacency list of each node. But instead of maintaining these lists as linked lists, it stores them in a single array.

To develop this representation, we first associate a unique sequence number with each arc, thus defining an ordering of the arc list.

We number the arcs in a specific order: first those emanating from node 1, then those emanating from node 2, and so on.

We number the arcs emanating from the same node in an arbitrary fashion.

We then sequentially store information about each arc in the arc list. We store the tails, heads, costs, and capacities of the arcs in four arrays: tail, head, cost, and capacity. So if arc (i, j) is arc number 20, we store the tail, head, cost, and capacity data for this arc in the array positions tail(20), head(20), cost(20), and capacity(20).

We also maintain a pointer with each node i, denoted by point(i), that indicates the smallest numbered arc in the arc list that emanates from node i. [If node i has no outgoing arcs, we set point(i) equal to point(i + 1).] Therefore, the forward star representation will store the outgoing arcs of node i at positions point(i) to (point(i + 1) - 1) in the arc list. If point(i) > point(i + 1) - 1, node i has no outgoing arc. For consistency, we set point(l) = 1 and point(n + 1) = m + 1.

Figure 2. 17(a) specifies the forward star representation of the network given in Figure 2.13.

The forward star representation provides us with an efficient means for determining the set of outgoing arcs of any node.

To determine, simultaneously, the set of incoming arcs of any node efficiently, we need an additional data structure known as the reverse star representation. Starting from a forward star representation,
we can create a reverse star representation as follows. We examine the nodes i = 1 to n in order and sequentially store the heads, tails, costs, and capacities of the incoming arcs at node i. We also maintain a reverse pointer with each node i, denoted by rpoint(i), which denotes the first position in these arrays that contains information about an incoming arc at node i. [If node i has no incoming arc, we set rpoint(i) equal to rpoint(i + 1).] For sake of consistency, we set rpoint(l) = 1 and rpoint(n +.1) = m + 1. As before, we store the incoming arcs at node i at positions rpoint(i) to (rpoint(i + 1) - 1). This data structure gives us the representation shown in Figure 2.17(b).

Observe that by storing both the forward and reverse star representations, we will maintain a significant amount of duplicate information. We can avoid this duplication by storing arc numbers in the reverse star instead of the tails, heads, costs, and capacities of the arcs. As an illustration, for our example, arc (3, 2) has arc number 4 in the forward star representation and arc (1, 2) has an arc number 1. So instead of storing the tails, cos~s, and capacities of the arcs, we simply store arc numbers; and once we know the arc numbers, we can always retrieve the associated information from the forward star representation. We store arc Qumbers in an array trace of size m. Figure 2.18 gives the complete trace array of our example.

In our discussion of the adjacency list representation, we noted that sometimes while updating data for an arc (i, j), we also need to update data for its reversal (j, i). Just as we did in the adjacency list representation, we can accomplish this task by defining an array mate of size m, which stores the arc number of the reversal of an arc. For example, the forward star representation shown in Figure 2.17(a)
assigns the arc number 6 to arc (4, 5) and assigns the arc number 8 to arc (5, 4). Therefore, if we were using the mate array, we would set mate(6) = 8 and mate(8) = 6.

Storing Parallel Arcs

both the adjacency list representation and the forward star representation data structures are capable of handling parallel arcs. If a node i has two outgoing arcs with the same head node but (possibly) different costs and capacities, the linked list of node i will contain two cells corresponding to these two arcs.
Similarly, the forward star representation allows several entries with the same tail and head nodes but different costs and capacities.

Representing Undirected Networks

We can represent undirected networks using the same representations we have just described for directed networks. However, we must remember one fact: Whenever arc (i, j) belongs to an undirected network, we need to include both of the pairs (i,j) and (j, i) in the representations we have discussed. Consequently, we will store each arc (i, j) of an undirected network twice in the adjacency lists, once in the list
for node i and once in the list for node j.

Some other obvious modifications are needed.

For example, in the node-arc incidence matrix representation, the column corresponding to arc (i, j) will have + 1 in both rows i and j.

The node-node adjacency matrix will have + 1 in position hij and hj ; for every arc (i, j) E A. Since this matrix will be symmetric, we might as well store half of the matrix.

In the adjacency list representation, the arc (i, j) will be present in the linked lists of both nodes i and j. Consequently, whenever we update information for one arc, we must update it for the other arc as well. We can accomplish this task by storing for each arc the address of its other occurrence in an additional mate array.

The forward star representation requires this additional storage as well. Finally, observe that undirected
networks do not require the reverse star representation.

Comparison of Forward Star and Adjacenoy List Bepresentations

The major advantage of the forward star representation is its space efficiency. It requires less storage than does the adjacency list representation.

In addition, it is much easier to implement in languages such as FORTRAN that have no natural provisions for using linked lists.

On the other hand, in the forward star representation these steps - add or delete arcs (as well as nodes) - require time proportional to m, which can be too time consuming.

The major advantage of adjacency list representation is its ease of implementation in languages such as Pascal or C that are able to manipulate linked lists efficiently.

Further, using an adjacency list representation, we can add or delete arcs (as well as nodes) in constant time.

[algolist]

Undirected graphs representation

algolist Undirected graphs representation.docx

http://www.algolist.net/Data_structures/Graph/Internal_representation

adjacency matrix

Each cell aij of an adjacency matrix contains 1, if there is an edge between i-th and j-th vertices, and 0 otherwise.

adjacency matrix is a good solution for dense graphs, which implies having constant number of vertices.

Adjacency matrix is optimal for dense graphs, but for sparse ones it is superfluous.

Advantages.

Adjacency matrix is very convenient to work with. Add (remove) an edge can be done in O(1) time, the same time is required to check, if there is an edge between two vertices.

Also it is very simple to program

Disadvantages.

  • Adjacency matrix consumes huge amount of memory for storing big graphs. All graphs can be divided into two categories, sparse and dense graphs. Sparse ones contain not much edges (number of edges is much less, that square of number of vertices, |E| << |V|2). On the other hand, dense graphs contain number of edges comparable with square of number of vertices.
  • in many algorithms you need to know the edges, adjacent to the current vertex. To draw out such an information from the adjacency matrix you have to scan over the corresponding row, which results in O(|V|) complexity. For the algorithms like DFS or based on it, use of the adjacency matrix results in overall complexity of O(|V|2), while it can be reduced to O(|V| + |E|), when using adjacency list.
  • adjacency matrix requires huge efforts for adding/removing a vertex. In case, a graph is used for analysis only, it is not necessary, but if you want to construct fully dynamic structure, using of adjacency matrix make it quite slow for big graphs.

adjacency list

For every vertex adjacency list stores a list of vertices, which are adjacent to current one.

It requires less amount of memory

To sum up, adjacency list is a good solution for sparse graphs and lets us changing number of vertices more efficiently, than if using an adjacent matrix. But still there are better solutions to store fully dynamic graphs.

Advantages.

Adjacent list allows us to store graph in more compact form, than adjacency matrix, but the difference decreasing as a graph becomes denser.

Next advantage is that adjacent list allows to get the list of adjacent vertices in O(1) time, which is a big advantage for some algorithms.

Disadvantages.

  • Adding/removing an edge to/from adjacent list is not so easy as for adjacency matrix. It requires, on the average, O(|E| / |V|) time, which may result in cubical complexity for dense graphs to add all edges.
  • Check, if there is an edge between two vertices can be done in O(|E| / |V|) when list of adjacent vertices is unordered or O(log2(|E| / |V|)) when it is sorted. This operation stays quite cheap.
  • Adjacent list doesn't allow us to make an efficient implementation, if dynamically change of vertices number is required. Adding new vertex can be done in O(V), but removal results in O(E) complexity.

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appel An Alternate Graph Representation for the Tiger Compiler.docx

Barnwal Graph and its representations.docx

The choice of the graph representation is situation specific. It totally depends on the type of operations to be performed and ease of use.

Adjacency Matrix

Adjacency matrix for undirected graph is always symmetric. Adjacency Matrix is also used to represent weighted graphs. If adj[i][j] = w, then there is an edge from vertex i to vertex j with weight w.

Pros: Representation is easier to implement and follow. Removing an edge takes O(1) time. Queries like whether there is an edge from vertex ‘u’ to vertex ‘v’ are efficient and can be done O(1).

Cons: Consumes more space O(V^2). Even if the graph is sparse(contains less number of edges), it consumes the same space. Adding a vertex is O(V^2) time.

Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to theith vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).

Incidence Matrix

Incidence List

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Barták Graphs in Prolog.docx

Basel Elementary Graph Algorithms PART-1 p34.pdf

Adjacency Matrix

Adjacency matrix of a digraph need not be symmetric

How much storage does the adjacency matrix require?
?? Answer: O(|V|2)
?? O(|V|) time to find vertex degree and/or vertices adjacent to a given vertex

The adjacency matrix is a dense representation
?? Usually too much storage for large graphs
?? But can be very efficient for small graphs
?? If graph is unweighted, there is an additional advantage in storage for the adjacency matrix presentation; rather than using one word of computer memory for each matrix entry, the adjacency matrix uses only one bit per entry.

Adjacency Lists

Most large interesting graphs are sparse ?? For this reason the adjacency list is often a more appropriate representation

Each adjacency list is a chain.

# of chain nodes = 2|E| (undirected graph)
# of chain nodes = |E| (digraph)

How much storage is required?
?? The degree of a vertex v = # incident edges
??Directed graphs have in-degree and out-degree
?? For directed graphs:
?? # of items in adjacency lists is Σ out-degree(v) = |E|
??takes Θ(V + E) storage (Why?)
?? For undirected graphs:
??# items in adjacency lists is Σ degree(v) = 2|E|
??also Θ(V + E) storage
?? So: Adjacency lists take O(V + E) storage

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[Benoit2005]

Benoit Representing trees of higher degree p12

D. Benoit, E. Demaine, I. Munro, R. Raman, V. Raman, and S. S. Rao. Representing trees of higher
degree. Algorithmica, 43(4):275{292, 2005.

[Blelloch2012]

Blelloch Lecture 7 Graph Representations Sets and Tables p11

Guy E Blelloch

https://www.cs.cmu.edu/~guyb/

Blelloch@cs.cmu.edu

2017-08-31

Margaret Reid-Miller

https://www.cs.cmu.edu/~mrmiller/

Kanat Tangwongsan

http://www.philinelabs.net/~ktangwon/

How should we represent a graph?

Adjacency matrix

Adjacency list

An array A of length n where each entry A[i] contains a pointer to a linked list of all the out-neighbors of vertex i. In an undirected graph with edge fu, vg the edge will appear in the adjacency list for both u and v.

Adjacency array

Similar to an adjacency list, an adjacency array keeps the neighbors of all vertices, one after another, in an array adj; and separately, keeps an array of indices that tell us where in the adj array to look for the neighbors of each vertex.

Edge list

edge set representation

The representation is similar to an edge list representation mentioned before, but it abstracts away from the particular data structure used for the set—the set could be based on a list, an array, a tree, or a hash table.

If we use the balanced-tree cost model for sets, for example, then determining if an edge is in the graph requires much less work than with an edge list— only O(log n) instead of (n) (i.e. following the list until the edge is found). The problem with edge sets, as with edge lists, is that they do not allow for an efficient way to access the neighbors of a given vertex v. Selecting the neighbors requires considering all the edges and picking out the ones that have v as an endpoint. Although with an edge set (but not an edge list) this can be done in parallel with O(logm) span, it requires (m) work even if the vertex has only a few neighbors.

edge-set table / adjacency table

More efficient neighbor access. In our second representation, we aim to get more efficiency in accessing to the neighbors of a vertex. This representation, which we refer to as an adjacency table, is a table that maps every vertex to the set of its neighbors. Simply put, it is an edge-set table.

Therefore, in this representation, accessing the neighbors of a vertex v is cheap: it just requires a lookup in the table. Assuming the balanced-tree cost model for tables, this can be done in O(log n) work and span. Once the neighbor set has been pulled out, mapping a constant work function over the neighbors can be done in O(dG(v)) work and O(1) span. Looking up if an edge is in the graph requires the same work and span as with edge sets: O(log n). This is because we can first look up one side of the edge in the table and then the second side in the set that is returned. Note that an adjacency list is a special case of adjacency table where the table of vertices is represented as an array and the set of neighbors is represented as a list.

Blelloch Lecture 13 — Shortest Weighted Paths p8.pdf

2012

Guy Blelloch

adjacency set representation for unweighted graphs

associate a value with each out edge of a vertex

associate each vertex with a table that maps each out-neighbor to its value

It would have type:
(eVal vertexTable) vertexTable .
The graph above would then be represented as:
G = f0 7! f1 7! 0.7, 2 7! 1.5g , 1 7! f2 7! ??2.0g , 2 7! fgg .

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Brabec Procedural Code Representation in a Flow Graph p12.pdf

Michal Brabec

2015

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Braun FIRM A Graph-Based Intermediate Representation p8.pdf

Matthias Braun Sebastian Buchwald Andreas Zwinkau
Karlsruhe Institute of Technology (KIT)
{matthias.braun,buchwald,zwinkau}@kit.edu

?????????????????????????????

Brisaboa Compact Representation of Web Graphs with Extended Functionality p33
Nieves R. Brisaboa

[Brisaboa2007]

Brisaboa K2trees for Compact Web Graph Representation p10.pdf

4

Nieves R. Brisaboa

Nieves Rodríguez Brisaboa
Full Professor

Database Laboratory
University of A Coru?na
A Coru?na, Spain

http://lbd.udc.es/ShowResearcherInformation.do?lang=en_US&id=12

brisaboa@udc.es
brisaboa@udc.es

2017-07-16

Susana Ladra
Database Laboratory
University of A Coru?na
A Coru?na, Spain

http://lbd.udc.es/ShowResearcherInformation.do?lang=en_US&id=113

sladra@udc.es
sladra@udc.es

Gonzalo Navarro
Dept. of Computer Science
University of Chile
Santiago, Chile

https://www.dcc.uchile.cl/~gnavarro/

gnavarro@dcc.uchile.cl
gnavarro@dcc.uchile.cl

2017-07-17

WebGraph Framework, by Boldi and Vigna [6]. It is associated to the site http://webgraph.dsi.unimi.it

compressed graph representations

  • WebGraph compression method
  • Pair compression [18] on the adjacency lists

adjacency matrix of a Web graph

The adjacency matrix of a Web graph of n pages is a square matrix faijg of n ￡ n, where each row and each col- umn represents a Web page. Cell aij is 1 if there is a hy- perlink in page i towards page j, and 0 otherwise.

properties of the adjacency matrix

  • As on average there are about 15 links per Web page, this matrix is extremely sparse.
  • Due to locality of reference, many 1s are placed around the main diagonal (that is, page i has many pointers to pages nearby i).
  • Due to the copy prop- erty, similar rows are common in the matrix.
  • Finally, due to skewness of distribution, some rows and colums have many 1s, but most have very few.
  • regularity properties of the adjacency matrix of the Web graphs, such as
    • horizontal,
    • vertical, and
    • diagonal runs.

clustering of the adjacency matrix

compact tree representation of the matrix

  • compact representation of the adjacency matrix that exploits its sparseness and clustering properties.
  • The representation is designed to compress large matrix ar- eas with all 0s into very few bits.
  • the technique offers a relevant space/time tradeoff to represent Web graphs, that is, it is much faster than those that take less space, and much smaller than those that o?er faster navigation.
    Furthermore, we show that our representation allows for other queries on the graph not usually considered in com pressed graph representations.
  • very e±cient to represent large empty areas of the matrix,
  • but at the same time allows e±cient forward and backward navigation of the graph.
  • An elegant feature of our solution is that it is symmetric, in the sense that forward and backward navigation are carried out by similar means and achieve similar times.
  • We represent the whole adjacency matrix via the k2-tree using two bit arrays we call T (tree) and L (leaves):
    • T: This bit array stores all the bits of the k2-tree except those in the last level. The bits of the k2-tree are placed following a levelwise traversal of the tree. We will represent ˉrst the k2 binary values of the children of the root node, then the values of the second level, and so on.
    • L: This bit array stores the last level of the tree. Thus it represents the value of (some) original cells of the adjacency matrix.
  • We represent the adjacency matrix by a k2-ary tree, which we call k2-tree, of height h = dlogk ne. Each node contains a single bit of data: 1 for the internal nodes and 0 for the leaves, except for the last level of the tree, where all are leaves and represent some bit values of the matrix. corresponds to the root; its k2 children are represented at level 1. Each child is a node and therefore it has a value 0 or 1. All internal nodes in the tree (i.e., with value 1) have exactly k2 children, whereas leaves (with value 0 or at the last tree level) have no children.
  • Assume for simplicity that n is a power of k; we will soon remove this assumption.
  • Conceptually, we start dividing the adjacency matrix into k2 submatrices of the same size, that
    is, k rows and k columns of submatrices of size n2=k2.
  • Each of the resulting k2 submatrices will be a child of the root node and its value will be 1 i? in the cells of the submatrix there is at least one 1. A 0 child means that the submatrix has all 0s and therefore the tree decomposition ends there; thus 0s are leaves in our tree.
  • The children of a node are ordered in the tree starting with the submatrices in the ˉrst (top) row, from left to right, then the submatrices in the second row from left to right, and so on.
  • Once the level 1 of the tree, with the children of root, has been built, the method proceeds recursively for each child with value 1, until we reach submatrices full of 0s, or we reach the cells of the original adjacency matrix. In the last level of the tree, the bits of the nodes correspond
    to the matrix cell values.
  • Figure 1 illustrates a 22-tree for a 4 ￡ 4 matrix.
  • A larger k induces a shorter tree, with fewer levels, but with more children per internal node.
  • If n is not a power of k, we conceptually extend our matrix to the right and to the bottom with 0s, making it of width n0 = kdlogk ne. This does not cause a signiˉcant overhead as our technique is e±cient to handle large areas of 0s.
  • Figure 2 shows an example of the adjacency matrix of a Web graph (we use the ˉrst 11￡11 submatrix of graph CNR [6]), and how it is expanded to an n0 ￡ n0 matrix for n0 a power of k = 2 (at the left) and of k = 4 (at the right). The ˉgure also shows the trees corresponding to those k values. Notice that the last level of the tree represents cells in the original adjacency matrix, but most empty cells in the original adjacency matrix are not represented in this level because, where a large area with 0s is found, it is represented by a single 0 in a smaller level of the tree.

Navigating with a k2tree

To obtain the pages pointed by a speciˉc page p, that is, to ˉnd direct neighbors of page p, we need to ˉnd the 1s in row p of the matrix. We start at the root and travel down the tree, choosing exactly k children of each node. We start with an example and then generalize in the next section.

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btechsmartclass Graph Representations.docx

Adjacency Matrix

Incidence Matrix

Adjacency List

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Buriol Web Graph representation and compression.ppt

the Adjacency Lists

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burkardt GRAPH_REPRESENTATION.docx

adjacency matrix;

incidence matrix

Cao Deep Neural Networks for Learning Graph Representations p8.pdf

[Cao2016]

PPMI matrix

the original PPMI matrix itself is an explicit representation matrix of the graph

pointwise mutual information (PMI) matrix

positive pointwise mutual information (PPMI) matrix

matrix R representing the vertices of graph G by capturing deep structural information.

co-occurrence matrix / collections of linear sequences / via DeepWalk

DeepWalk proposed by Perozzi et al. (2014) presented an idea to transform unweighted
graphs into collections of linear sequences by a uniform sampling method known as truncated random walk.

DeepWalk (Perozzi, Al-Rfou, and Skiena 2014) is a recently proposed method to learn representations of networks. It transforms a graph structure into linear sequences by truncated random walks and processes the sequences using skip-gram with hierarchical softmax.

In their approach, sampled vertex sequences characterize the connections between vertices in a graph. This step can be understood as a process for converting a general graph structure into a large collection of linear structures.

Next, they utilized the skip-gram model proposed by Mikolov et al. (2013) to learn low-dimensional representations for vertices from such linear structures. The learned vertex representations were shown to be effective across a few tasks, outperforming several previous approaches such as spectral clustering and modularity method (Tang and Liu 2009a; 2009b; 2011; Macskassy and Provost 2003).

DeepWalk yields a co-occurrence matrix based on the sampled linear sequences.

probabilistic co-occurrence matrix

In Section 3, we describe our random surfing model that directly construct a probabilistic co-occurrence matrix from a weighted graph, which avoids the expensive sampling process.

random surfing model suitable for weighted graphs, which can directly yield a probabilistic
co-occurrence matrix. Such a matrix is similar to the cooccurrence matrix obtained by sampling linear sequences from graphs (Bullinaria and Levy 2007), but no sampling process is required in our approach.

linear sequences

Although effective, the sampling method for transforming a graph structure into linear sequences has some weaknesses.

vector representation / vertex representations of a unweighted graph

a model for learning graph representations, which generates a low-dimensional vector representation for each vertex by capturing the graph structural information.

One of effective means towards organizing such information associated with the potentially large and complex graph is to learn the graph representations, which assign to each vertex of the graph a low-dimensional dense vector representation, encoding meaningful information conveyed by the graph.

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Catherine Clustering the Graph Representation of Data p26

[Chen2012]

Chen Analysis of Algorithms I: Graph Representation and BFS p41
Xi Chen

adjacency matrix

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 1 Matrix: (n) (to go through a binary string of length n)

But the matrix representation of course has its own advantage: To decide if (u; v) 2 E, it only uses O(1) time

If the algorithm uses a lot of random access of edges in G, then the matrix representation may perform better.

adjacency-list

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 2 List: linear in the length of Adj(u) (or equivalently, deg(u) if G is undirected, and out-deg(u) if G is directed)

To decide if (u; v) 2 E, the list representation has worst-case running time linear in the length of Adj(u) (why?).

If the input graphs are sparse and we make a lot of enumerations of edges incident to a vertex in our algorithm, then the list representation usually ts better.

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Chen EAGER Define and Construct an Enhanced Graph Representation for Multiscale Vector Field Data Summarization.docx

??????????????????????????????

CLAUDE Fast and Compact Web Graph Representations p30
FRANCISCO CLAUDE

[Claude2007]

Claude A Fast and Compact Web Graph Representation p12
Francisco Claude

incidence matrix

Standard graph representations such as the incidence matrix require n(n? 1)/2 bits, for undirected graphs. For directed graphs the numbers are n2 .

adjacency lists

Re-Pair [19] to compress the adjacency lists

Standard graph representations such as the adjacency list require 2e log n bits, for undirected graphs. For directed graphs the numbers are e log n.

[Codish2013]

Codish Breaking Symmetries in Graph Representation p7.pdf

Michael Codish
Dept. of Computer Science
Ben-Gurion Univ. of the Negev
Beer-Sheva, Israel

https://www.cs.bgu.ac.il/~mcodish/

mcodish@cs.bgu.ac.il

2017-08-16

Alice Miller and Patrick Prosser
School of Computing Science
University of Glasgow
Scotland

Peter J. Stuckey
Dept. of Comp. Sci. and SE
and NICTA Victoria Laboratory
University of Melbourne, Australia

The canonical graph representation problem

The canonical graph representation problem is pertinent to a wide range of scientific applications. It is closely related to the graph isomorphism problem, as two graphs are isomorphic if and only if they have the same canonical representation.

adjacency matrix

canonical adjacency matrix

Boolean adjacency matrix

[Cormen2014]

Cormen Representing graphs.docx

Dartmouth Computer Science professors Thomas Cormen and Devin Balkcom

Thomas Cormen

http://www.cs.dartmouth.edu/~thc/

thc@cs.dartmouth.edu

2017-08-18

Devin Balkcom

http://www.cs.dartmouth.edu/~devin/

devin.balkcom@dartmouth.edu

Edge lists

For finding the neighbours of vertex v:
Edge List: O(|E|)
If the list is unsorted you need to check every edge to see if it comes from v
For a complete graph (where every vertex is connected to all other vertices) this would be O(|V|^2)

How can you organize an edge list to make searching for a particular edge take O(lgE) time? The answer is a little tricky.

Sort the list by the 1st vertex in each edge, and then by 2nd vertex in each edge.
The list is sorted, so we can now use a binary search on it.
Our comparison is a little bit more complicated now.
[v1,v2] < [v3,v4] if (v1 < v3) OR ( (v1 === v3) AND v2 < v4 )

If we have an edge [v1,v2] we do a binary search for [v1,v2] on the list. Time O(log E)

If your edges are not directed i.e. [v1,v2] is equivalent to [v2,v1] then perform a second search on the equivalent edge [v2,v1] if your first search wasn't successful. Double O(log E) is still O(log E).

Adjacency lists

Representing a graph with adjacency lists combines adjacency matrices with edge lists

It is true that in the general case that storage of an adjacency list is O(|V|+|E|).
This is the same as O( max( |V|, |E| ) )
Which means that you at least need to allocate space for the pointer to each vertices list.
In most practical cases |E| will larger than |V| (even for a minimally connected graph i.e. a tree, E = V-1). Which means for most practical cases the space required is simply O(|E|).

We can get to each vertex's adjacency list in constant time, because we just have to index into an array. To find out whether an edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis is present in the graph, we go to i i ii 's adjacency list in constant time and then look for j j jj in i i ii 's adjacency list. How long does that take in the worst case? The answer is Θ(d) \Theta(d) Θ(d) , where d d dd is the degree of vertex i i ii , because that's how long i i ii 's adjacency list is. The degree of vertex i i ii could be as high as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 (if i i ii is adjacent to all the other ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices) or as low as 0 (if i i ii is isolated, with no incident edges). In an undirected graph, vertex j j jj is in vertex i i ii 's adjacency list if and only if i i ii is in j j jj 's adjacency list. If the graph is weighted, then each item in each adjacency list is either a two-item array or an object, giving the vertex number and the edge weight.

How much space do adjacency lists take? We have ∣V∣ |V| ∣V∣vertical bar, V, vertical bar lists, and although each list could have as many as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices, in total the adjacency lists for an undirected graph contain 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar elements. Why 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar ? Each edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis appears exactly twice in the adjacency lists, once in i i ii 's list and once in j j jj 's list, and there are ∣E∣ |E| ∣E∣vertical bar, E, vertical bar edges. For a directed graph, the adjacency lists contain a total of ∣E∣ |E| ∣E∣vertical bar, E, vertical bar elements, one element per directed edge.

Agreed, if the list of neighbors is implemented as an array, and that array is sorted then determining membership is Θ(log(d)), using binary search.

However, if the array is unsorted, or if the list of neighbors is implemented as a linked list (both are typical implementations) then determining membership is Θ(d), as we need to look at every item in the list before deciding that something is not in the list.

In the article they mention "Vertex numbers in an adjacency list are not required to appear in any particular order", which implies the analysis is with regards to unsorted implementations.

Whether you would want to use a sorted version or not would depend on your application. You might get the sorting for free (i.e. if your method of constructing your graph leads to naturally sorted adjacency lists), or you might have to pay an additional cost in sorting the adjacency lists. Whether the cost outweighs the benefits depends on your application.

For finding the neighbours of vertex v:

Adjacency List: O(|N|)
where N is the number of neighbours of v
You need to iterate through the list for the vertex v, which has N neighbours
v could have up to V-1 neighbours, so we could also say it is O(|V|)

how is adjacency list space Θ(V + E)?

The adjacency list contains:
-1 array per vertex, for a total of V arrays (we are only considering the space for the array pointer, not the contents of the array).
-Each directed edge is contained once somewhere in the adjacency list, for a total of E edges (a bidirectional edge is just 2 directed edges, so if we are using bidirectional edges it would just be 2E ).

V+E is Θ(V + E)

Adjacency matrices

For finding the neighbours of vertex v:

Adjacency Matrix: O(|V|)
You need to check the the row for v, (which has |V| columns) to find which ones are neighbours

If you represent your adjacency matrix as a hash table, you can get very good lookup times without using n^2 memory.

[Cornell2011]

Cornell Lecture 21 Graph Representations and Traversals.docx

adjacency list

Directed graphs are commonly represented as an adjacency list, which comprises an array or list of vertices, where each vertex vi stores a list of all the vertices vj for which there is an edge (vi, vj) ∈ E.

In practice, many graphs are sparse in the sense that most of the possible edges between pairs of vertices do not exist, i.e. m << n2. In such cases the adjacency list is generally preferable to the adjacency matrix representation.

In that implementation, a graph is represented as a pair consisting of the number of vertices and a list of vertices. A vertex is represented as a triple of a unique integer id, an outgoing list, and an incoming list. The outgoing list is a list of pairs of destination vertex and weight. The incoming vertex list is a list of pairs of source vertex and weight. Note that as each edge is stored twice, in the incoming list of its destination and the outgoing list of its source, the weight must be consistent in the two lists.

In that implementation, an edge is a triple of a source vertex, destination vertex and weight, and is constructed on the fly as needed from the vertex out lists rather than being explicitly stored in the data structure.

adjacency matrix

Another common representation is an adjacency matrix, which is a two-dimensional array, where Ai j is non-zero when there is an edge (vi, vj) ∈ E.

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[Costantini2001] Comparing different graph representations of logic programs under the Answer Set semantics p6
Stefania Costantini
Dept. of Pure and Applied Maths.
Univ. of L’Aquila
via Vetoio, Loc. Coppito, I-67100 L’Aquila, Italy
stefcost@univaq.it

http://www.di.univaq.it/stefcost/

Stefania.Costantini@univaq.it

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D'Autilia Shaping ideal cities the graph representation of the urban utopia p17.pdf

[Depree2013]
Depree Graph Operations And Representation p34

Adjacency Matrix

O(n) time to find vertex degree and/or vertices adjacent to a given vertex.

Cost adjacency matrix. C(i,j) = cost of edge (i,j)

Adjacency Lists

    Linked Adjacency Lists

    Each adjacency list is a chain.

    Array Length = n
    # of chain nodes = 2e (undirected graph)
    # of chain nodes = e (digraph)

    Array Adjacency Lists

    Each adjacency list is an array list.

    Array Length = n
    # of list elements = 2e (undirected graph)
    # of list elements = e (digraph)

    Adjacency lists => each list element is a pair (adjacent vertex, edge weight)

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Dong Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance p67

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[Du2007]

Du Lecture 3 Graph Representation for Regular Expressions p26

Dvorak A dynamic data structure for counting subgraphs in sparse graphs p27
Zdenˇek Dvorak Vojtˇech T°uma?

Ediger STINGER: High Performance Data Structure for Streaming Graphs p5
David Ediger Rob McColl Jason Riedy David A. Bader

??????????????????????????????

[Egyhazy1983]

Egyhazy On implementing graph representation p23

Csaba Egyhazy

4

one way adjacency lists

each node consists of two fields, INFO and LINK, the INFO field contains the itentifier of the next vertex that is also adjacent to vertex vi.

adjacency multilist representation

[Elite2010]

Elite Graph Representation p27

Adjacency matrix

[Emms2006]

Emms A matrix representation of graphs and its spectrum as a graph invariant p14

4

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David Emms
Department of Computer Science
University of York, York YO10 5DD, U.K.
demms@cs.york.ac.uk

Edwin R. Hancock
Department of Computer Science
University of York, York YO10 5DD, U.K.
erh@cs.york.ac.uk

erh@cs.york.ac.uk

2017-08-19

Simone Severini
Department of Mathematics and Department of Computer Science
University of York, York YO10 5DD, U.K.
ss54@york.ac.uk

https://www.ucl.ac.uk/~ucapsse/

s.severini@ucl.ac.uk

2017-08-20

Richard C. Wilson
Department of Computer Science
University of York, York YO10 5DD, U.K.
richard.wilson@cs.york.ac.uk
Submitted: Nov 16, 2005; Accepted: Mar 16, 2006; Published: Apr 4, 2006
2000 Mathematics Subject Classi cation: 05E30, 05C60

the electronic journal of combinatorics 13 (2006), #R34

adjacency matrix

Laplacian matrix

Representing graphs with orthogonal matrices

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Figueroa Tracking soccer players using the graph representation p4
Pascual Figueroa

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http://www.geoffwyatt.com/

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Gaillarda Graph representation of synonymy and translation resources for cross-linguistic modelisation of meaning p12

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[García2014]

García Compact and Efficient Representations of Graphs p301

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Gkirtzou The Pyramid Quantized Weisfeiler-Lehman Graph Representation p17

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C. Godsil and G. Royle, Algebraic Graph Theory, Graduate Texts in Mathematics,
207, Springer-Verlag, New York, 2001.

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Gotshalks Graph Representation p12

[Gotshalks2008]

Gunnar Gotshalks

http://www.cse.yorku.ca/~gunnar/

gunnar@cse.yorku.ca

2017-08-22

adjacency matrix

In general the matrix entries can be any data representing the edge
? True / False are the minimum – an edge exists / ~exists
? Integer – 0 / 1 for False / True
? Number of parallel edges
? Airline flight number
? Time to do task (vertices represent checkpoints)
? Maximum rate of oil flow in a pipeline

incidence matrix

adjacency list

? Each vertex in an adjacency list points to its entry in the list of all vertices
? Each vertex in an adjacency list can also point to edge data

edge list

[Grama2003]

Grama Graph Algorithms p65.pdf

Ananth Grama

https://www.cs.purdue.edu/people/faculty/ayg/

https://www.cs.purdue.edu/homes/ayg/

ayg@cs.purdue.edu

Graphs can be represented by their adjacency matrix or an edge (or vertex) list.

Adjacency matrices

Adjacency matrices have a value ai;j = 1 if nodes i and j share an edge; 0 otherwise. In case of a weighted graph, ai;j = wi;j, the weight of the edge.

adjacency list

The adjacency list representation of a graph G = (V;E) consists of an array Adj[1::jV j] of lists. Each list Adj[v] is a list of all vertices adjacent to v.

edge list

vertex list

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GRAPH FILE FORMATS.pdf

M Bernard

Graph Representation.pdf

adjacency list and the adjacency matrix

Graph Representation1.pdf

[Gross2003]

Gross Section 8.3 Graph Representations and Graph Isomorphism p11

Jonathan L. Gross

http://www.cs.columbia.edu/~gross/

retired

https://www.cs.columbia.edu/2016/jonathan-gross-retires/

gross@cs.columbia.edu

2017-08-23

ADJACENCY MATRIX REPRESENTATION

INCIDENCE MATRIX REPRESENTATION

ADJACENCY LIST REPRESENTATION

def: An adjacency list for a vertex v of a graph G is a list containing each vertex w of G
once for each edge between v and w.
def: An adjacency list representation of a graph is a table of all the adjacency lists.

INCIDENCE TABLE REPRESENTATION

An incidence table for a graph has a column indexed by each edge. The entries in the column for an edge are its endpoints. If the edge is a self-loop, then the endpoint appears twice.

Hackerearth Graph Representation.docx

Adjacency Matrix

Adjacency Lists

Heap Graph representation .docx

Adjacency list

Adjacency matrix

Hedstrom Graph representation.docx

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Heissan Some Results on Graph Representations and Graph Colorings p60

adjacency lists

incidence lists

adjacency matrices

incidence matrices.

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Hernandez Compressed Representation of Web and Social Networks via Dense Subgraphs p12
Cecilia Hernandez

[Huan2005]

HUAN Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based Packing Motifs p15
JUN HUAN

Huan Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based acking Motifs p12
Jun Huan

Canonical adjacency matrix

Canonical adjacency matrix of labeled graphs
We represent each graph by an adjacency matrix M such that every diagonal entry of M is filled with the
label of the corresponding node and every off-diagonal entry is filled with the label of the corresponding
edge, or zero if there is no edge. This is slightly different from the standard adjacency matrix representation for unlabeled graphs (Cormen et al., 2001).

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[Iglesias2011]

Iglesias Graph representation of documents content and its suitability for text mining tasks p72

[Jampani2011]

Jampani Simultaneous Graph Representation Problems p94
by
Krishnam Raju Jampani

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[Joy1987]
The "Printable" Format for Describing a Graph
The structure for the textual representation of a graph is a sequence of lines, each representing a separate node in the graph, of the form:
address type usage_count annotation "name" [other fields]
where the fields are separated by blanks or tabs. The field address is an unsigned integer representing the storage location of the node. The field type is an unsigned integer representing the type of the node (integer, real, application, etc.). The field usage_count is an unsigned integer used for garbage collection purposes (reference counts, etc.), and represents the number of strong pointers to that node in the graph. The field annotation is an integer currently not assigned, but may be used in the future by particular implementations. The meaning of a program should be unchanged if all the annotations are ignored. The "name" field is a character string naming the node, usually null.

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[Kannan1989]

Kannan Implicit Representation of Graphs p11
Sampath Kannan

Sampath Kannan
Computer Science Department
University of Arizona

Moni Naor
IBM Research Division
Almaden Research center

Steven Rudich
Computer Science Department
Carnegie-Mellon University

How to represent a graph in memory is a fundamental data structuring question.

Kirsh An Implementation and Analysis of the Skip Graph Data Structure p12
Jonathan Kirsh

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K?bler Interval Graph Representation with Given Interval and Intersection Lengths p13

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[Kuhnert2016]

Kuhnert Space Efficient Algorithms for Graph Isomorphism and Representation p117

Sebastian Kuhnert

Kumar Improved Algorithms and Data Structures for Solving Graph Problems in External Memories p34

Lehmann Implementing Graph Query Languages over Compressed Data Structures: A Progress Report p5

Nicol′as Lehmann1;2 and Jorge P′erez1;2

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Lei?a A Graph-Based Higher-Order Intermediate Representation p11
Roland Lei?a

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Lenharth Graph Representations p5
Andrew Lenharth

http://www.lenharth.org/

lenharth@ices.utexas.edu

andrew@lenharth.org

2017-08-26

[Lenharth2014]
Base Structure Representations

Adjacency matrix
Adjacency Matrix -- operations
Easy
?Iterate nodes
?Edges by src
?Edges by dst
?Loopup by src, dst
?Add Edge
?Delete edge
Hard
?Add node
?Delete node

Adjacency Matrix -- Costs
?Lookups: O(1)
?Iterations: array iteration
?Edge addition: O(1)
?Edge removal: O(1)
?Space: O(N^2)
–Good for dense graphs

Adjacency lists

?Nodes stored in array as pointers to linked lists
?Edges stored as linked list at src
?Fundamentally directed

Adjacency Lists – Operations
Easy
?Iterate nodes
?Edges by src
?Add Edge
?Delete edge
?Add node?
Hard
?Edges by dst
?Loopup by src, dst
–Linear seach
?Delete node

Adjacency Lists – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Linked List iteration
–Expensive due to indirection
–not cache friendly
?Edge addition: O(1)
–Except involves an allocation
?Edge removal: O(E)
?Space: O(N + E)
–Constant for E == sizeof(ptr) + sizeof(Edata) + sizeof(int)

Edge List

?Think of Edges not Nodes as primary
?Array of Edges (src,dst,data)
–May be sorted by src or dst
?Array of Node data
?May not be able to iterate edges by node
?Easy global iteration over edges

Compressed Edge lists
?Rather than storing integer indexes or pointers, store compressed data stream
?Decompress as iterating over edges
?E.g. Delta-encoding
–Each edge is stored as the delta from the previous edge
?1,4,7,9 -> 1,3,3,2
–Use fewer bytes for each edge (variable length encoding)

Adjacency vectors
?Replace Linked List with pointer to vector
–Resizable vector?
?Costs?
?Advantages?

Compressed row storage
Compressed Sparse Row Storage
?Try to combine space efficiency of Lists with array traversal for edges
?Store Node data in an array
?Store all edges in an array (sorted by src)
?Store an array of pointers to edges
–Indexed by node id
–One pointer per node

CSR – Operations
Easy
?Iterate nodes
?Edges by src
?Add node?
Hard
?Edges by dst
?Add Edge
?Delete Edge
?Loopup by src, dst
–Linear seach
?Delete node

CSR – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Array iteration
?Space: O(2N + E)
–Constant for E == sizeof(Edata) + sizeof(int)

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[Lovasz2009]

Lovasz Geometric Representations of Graphs p213

Laszlo Lovasz
Institute of Mathematics
E?otv?os Lorand University, Budapest
e-mail: lovasz@cs.elte.hu

http://www.cs.elte.hu/~lovasz/

lovasz@cs.elte.hu

2018-08-26

1 Planar graphs and polytopes 11
2 Graphs from point sets 19
3 Harmonic functions on graphs 33
4 Rubber bands 41
5 Rigidity 63
6 Representing graphs by touching domains 73
7 Analytic functions on graphs 101
8 The Colin de Verdiμere Number 115
9 Orthogonal representations 123
10 Graph independence to linear independence 153
11 Metric embeddings 157
12 Adjacency matrix and regularity partitions 163
13 Some general issues 165

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[Madduri2008]

Madduri Compact Graph Representations and Parallel Connectivity Algorithms for Massive Dynamic Network Analysis p11

Kamesh Madduri
Computational Research Division
Lawrence Berkeley National Laboratory
Berkeley, USA 94703

http://www.cse.psu.edu/~kxm85/

madduri@cse.psu.edu

2018-08-27

David A. Bader
College of Computing
Georgia Institute of Technology
Atlanta, USA 30332

https://www.cc.gatech.edu/~bader/

Professor and Chair
School of Computational Science and Engineering
College of Computing
Georgia Institute of Technology
Atlanta, Georgia 30332
bader@cc.gatech.edu
http://www.cc.gatech.edu/
?
bader

2018-08-27

adjacency lists using adjacency arrays

For representing sparse static graphs, adjacency lists implemented using cache-friendly adjacency arrays are shown to give substantial performance improvements over linkedlist and adjacency matrix representations for sparse graphs [22].

(adjacency lists using) dynamic, resizable adjacency arrays

Dynamic Arrays (Dyn-arr). We can extend the static graph representation and use dynamic, resizable adjacency arrays for processing insertions and deletions. Clearly, this would support fast insertions. For inserting a new edge hu; vi, we resize the adjacency array of u if needed, and place v at the end of the array. The count can be incremented using an atomic increment operation on modern hardware,
and so this representation supports lock-free, non-blocking insertions.

There are two potential parallel performance issues with this data structure. Edge deletions are expensive in this representation, as we may have to scan the entire adjacency list in the worst case to locate the required tuple. Note that a scan is reasonable for low-degree vertices (say, less than 10 adjacencies), given the spatial locality we have due to the contiguous adjacency representation. However,
due to the power-law degree distributions in small-world networks, we may encounter several high-degree vertices in the graph, and deletions for these vertices would necessitate O(n) additional work.

linkedlist

adjacency matrix

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Madduri Scaling up graph algorithms on emerging multicore systems p22

[Madduri2009]

Complementing data stream algorithms, a graph or network representation is a convenient abstraction in many applications – unique data entities are represented as vertices, and the interactions between them are depicted as edges. The vertices and edges can further be typed, classified, or assigned attributes based on relational information from the heterogeneous sources.

For representing sparse static graphs, adjacency lists implemented using cache-friendly adjacency arrays are shown to give substantial performance improvements over linkedlist and adjacency matrix representations for sparse graphs [22]. For dynamic networks, we need to process insertions of vertices and edges, which may be streaming or batched.
Thus, we experiment with the performance of several candidate representations for small-world graphs and discuss the trade-offs associated with each data structure.

Dynamic Arrays (Dyn-arr). We can extend the static graph representation and use dynamic, resizable adjacency arrays for processing insertions and deletions.

A hybrid representation (Hybrid-arr-treap). To process both insertions and deletions efficiently, and also given the power-law degree distribution for small-world networks, we design a hybrid representation that uses Dyn-arr to represent adjacencies of low-degree vertices, and Treaps for high-degree vertices.

Maiya Visually Pleasing Graph Representation Using GraphDraw.docx

adjacency matrix

Manchester Graph Representation and Traversal.docx

adjacency list versus adjacency matrix

Manevich Synthesizing Concurrent Graph Data Structures: A Case Study p14
R. Manevich, R. Kaleem, and K. Pingali

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Matas The color adjacency graph of multi-coloured objects p18.pdf

J Matas

[Mehlhorn2008]

Mehlhorn Data Structures and Algorithms: The Basic Toolbox - 8 Graph Representations p8.pdf

4

Kurt Mehlhorn

https://people.mpi-inf.mpg.de/~mehlhorn/

https://people.mpi-inf.mpg.de/~mehlhorn/

https://people.mpi-inf.mpg.de/~mehlhorn/ftp/Toolbox/GraphRep.pdf

CHAPTER 9 The Graph Data Model p78

store node or edge information in a hash table.

adjacency matrix

Adjacency matrices are good for rather dense graphs.

An n-node graph can be represented by an n×n adjacencymatrix A. Ai j is 1 if (i, j) ∈ E and 0 otherwise. Edge insertion or removal and edge querieswork in constant time.

It takes time O(n) to obtain the edges entering or leaving a node. This is only efficient
for very dense graphs with m = W??n2

The storage requirement is n2 bits.

For very dense graphs, this may be better than the n+m+O(1) words required for adjacency
arrays. However, even for dense graphs, the advantage is small if additional edge information is needed.

adjacency list

Adjacency Lists – Dynamic Graphs

Adjacency lists are good if the graph changes frequently

Adjacency lists for sparse graphs should be implemented without the dummy item introduced in Sect. 3.1, because an additional item would waste considerable space.

The second solution has only one item for each undirected edge (or pair of directed edges) and makes this item a member of two adjacency lists. So, the item for an undirected edge {u,v} would be a member of lists Eu and Ev. If we want doubly linked adjacency information, the edge object for any edge {u,v} stores four pointers: two are used for the doubly linked list representing Eu, and two are used for the doubly linked list representing Ev. Any node stores a pointer to some edge incident on it. Starting from it, all edges incident on the node can be traversed. The bottom part of Fig. 8.1 gives an example. A small complication lies in the fact that finding the other end of an edge now requires some work. Note that the edge object for an edge {u,v} stores the endpoints in no particular order. Hence, when we explore the
edges out of a node u, we must inspect both endpoints and then choose the one which is different from u. An elegant alternative is to store u⊕v in the edge object [145]. An exclusive OR with either endpoint then yields the other endpoint. Also, this representation saves space.

For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

Unbounded arrays

Unbounded arrays are more cache-efficient.

linked list

Linked lists allow constant-time insertion and deletion of edges at arbitrary positions.

In the example in Fig. 8.1, we show circularly linked lists.

Edge Sequences

The edge sequence representation is good only in specialized situations.

In Chap. 3, we learned how to implement dynamic sequences. We can use any of the solutions presented there to produce a dynamic graph data structure. For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

This is even more compact than the 2m words needed for an edge sequence representation.

ordered edge sequence representation

Unordered Edge Sequences = Edge Lists ???

Perhaps the simplest representation of a graph is as an unordered sequence of edges. Each edge contains a pair of node indices and, possibly, associated information such as an edge weight.Whether these node pairs represent directed or undirected edges is merely a matter of interpretation.

Sequence representation is often used for input and output.

It is easy to add edges or nodes in constant time.

However, many other operations, in particular navigation, take time theta(m), which is forbiddingly slow.

Only a few graph algorithms work well with the edge sequence representation;

most algorithms require easy access to the edges incident on any given node. In this case the ordered representations discussed in the following sections are appropriate.

In Chap. 11, we shall see two minimum-spanning-tree algorithms: one works well with an edge sequence representation and the other needs a more sophisticated data structure.

This is even more compact than the 2m words needed for an edge sequence representation.

Edge arrays are a compact and efficient graph representation.

Their main disadvantage is that it is expensive to add or remove edges. For example, assume that we want to insert a new edge (u,v). Even if there is room in the edge array E to accommodate it, we still have to move the edges associated with nodes u+1 to n one position to the right, which takes time O(m).

Array

NodeArray

EdgeArray

information associated with nodes can be stored in arrays.

NodeArray and EdgeArray to indicate array-like data structures that can be indexed by nodes and by edges, respectively

Adjacency Arrays– Static Graphs

To support easy access to the edges leaving any particular node, we can store the edges leaving any node in an array. If no additional information is stored with the edges, this array will just contain the indices of the target nodes. If the graph is static, i.e., does not change over time, we can concatenate all these little arrays into a single edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an example.edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an xample.

Adjacency array representations can be generalized to store additional information: we may store information associated with edges in separate arrays or within the edge array. If we also need incoming edges, we may use additional arrays V′ and E′ to store the reversed graph.

The memory consumption for storing a directed graph using adjacency arrays is n+m+Q(1) words.

Edge arrays are a compact and efficient graph representation. Their main disadvantage is that it is expensive to add or remove edges. For example, assume that we want to insert a new edge (u,v). Even if there is room in the edge array E to accommodate it, we still have to move the edges associated with nodes u+1 to n one position to the right, which takes time O(m).

Very often, some variant of adjacency arrays is fastest. This may be true even if the graph changes, because often there are only a few changes, or all changes happen in an initialization phase of a graph algorithm, or changes can be agglomerated into occasional rebuildings of the graph, or changes can be simulated by building several related graphs.

There are many variants of the adjacency array representation.

Information associated with nodes and edges may be stored together with these objects or in separate arrays. A rule of thumb is that information that is frequently accessed should be stored with the nodes and edges. Rarely used data should be kept in separate arrays, because otherwise it would often be moved to the cache without being used. However, there can be other,more complicated reasons why separate arrays may be faster. For example, if both adjacency information and edge weights are read but only the weights are changed, then separate arrays may be faster because the amount of data written back to the main memory is reduced.

linked-edge-objects representation

Implicit Representations

Google Scholar

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Montes Graph Representation for Program Evolution: an Overview p32
Héctor A Montes

[Morris1998]

Morris Graph Representations.docx

John Morris , 1998

https://www.cs.auckland.ac.nz/software/AlgAnim/graph_rep.html

Adjacency Matrix

Adjacency List

Munro Dynamic Data Structures for Document Collections and Graphs p13
J. Ian Munro

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NetflixGraph

https://github.com/Netflix/netflix-graph

http://netflix.github.io/netflix-graph/

NetworkGraph Theory Graph-based representations p13

Representation (Matrix)
? Incidence Matrix
? Adjacency Matrix

Representation (List)
? Edge List
? Adjacency List (node list)

OJJ GRAPH REPRESENTATION.docx

ojjcourse@psu.edu

Adjacency Matrix

Incidence Matrix

Okie Graphs - Terminology and Representation.docx

Edward G. (Ned) Okie

Professor of Computer Science
Department of Information Technology
Radford University
Radford, Virginia 24142-6933

Office: | 219 Davis Hall
Email: | nokie@radford.edu
Phone: | 540-831-5992
Fax: | 540-831-6706

My RU Page
Current schedule
Current classes: | ITEC 320, ITEC 420
Office Hours: | MW: 10:00-10:55; TuTh 11:00-11:55; F: 2:00-2:55
Other information

2018-08-28

Adjacency list and adjacency matrix

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[Opendatastructures]

Opendatastructures 12.2 AdjacencyLists A Graph as a Collection of Lists.docx

AdjacencyLists

  • What type of collection should be used to store each element of [image]? One could use an array-based list, a linked-list, or even a hashtable.
  • Should there be a second adjacency list, [image], that stores, for each [image], the list of vertices, [image], such that [image]? This can greatly reduce the running-time of the [image] operation, but requires slightly more work when adding or removing edges.
  • Should the entry for the edge [image] in [image] be linked by a reference to the corresponding entry in [image]?
  • Should edges be first-class objects with their own associated data? In this way, [image] would contain lists of edges rather than lists of vertices (integers).

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[Pahikkala2006]

Pahikkala Graph Kernels versus Graph Representations a Case Study in Parse Ranking p8

Tapio Pahikkala

graph representations for dependency parses

We now give a brief introduction to kernels considered in this study. Formally, let X denote the input space, which can be any set, and H denote the feature space. For any mapping : X ? H, k(x, z) = h(x), (z)i is a kernel function. Following [3], we define a labeled graph representation of data points as follows. Below, Mi×j(R) denotes the set of real valued matrices of dimension i × j and [M]i,j denotes the element of matrix M in the i-th row and j-th column. Let L = {l}r, r ? N+ be an enumeration of all possible labels. Let G = (V,E, h) be a graph that consists of the set of vertices V , the set of edges E ? V × V , and a function h : V ? L that assigns a label to each vertex of a graph. We assume that the edge set of G is represented as an adjacency matrix A ? M|V |×|V |(R) whose rows and columns are indexed by the vertices V , and [A]i,j is one if the vertices vi ? V and vj ? V are connected with an edge, and zero otherwise. We also assume that the function h is represented as a label allocation matrix L ? M|L|×|V |(R) so that its element [L]i,j is one if vertex vj ? V has a label li ? L and zero otherwise.

http://forum.paradigm4.com/t/graph-representation/1564

Graph representation

I′m using the matrix of data as a representation of a Graph; I'm interested on detecting the transitives of the graph; any suggestions ?

there is book called Graph Analytics in the language of linear algebra which talks about how to compute variety of common graphs analytics using matrix operations. in particular spgemm operator in scidb should be helpful

Papadimitriou Combinatorial Algorithms & Data Structures Spring 2003 p9
Lecture 2: 1.23.03
Lecturer: Prof. Christos Papadimitriou

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[Park2014]

Park Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation p4

Eunhyuk Park

pointer-assisted graph representation

The pointer-assisted graph avoids expensive sorting, rearrangement and search operations which occupy a significant portion of graph computation.

A vertex is represented by a tuple of vertex value (e.g., vertex weight in pagerank), in-edge and out-edge pointers. An in-edge pointer points to an array of in-edge information. Each entry in the array consists of source vertex ID and edge value (e.g., edge weight in pagerank). An out-edge pointer in the vertex data points to an array of out-edge information. Each entry of the array contains destination vertex ID and edge offset (offset in the in-edge array of the destination vertex). Note that each edge has its weight
information only at a single location, in its entry of in-edge array (edge value).

Figure 5 Pointer-assisted graph representation

our proposed pointer-assisted graph representation enables us to access, with low latency, only the required data from the storage without additional expensive data re-arrangement steps.

tabular representation / tabular form

the edges are expressed as a tabular form as shown in Figure 1 (b) (in-edge sorted in this case). Each entry in the table contains two vertex IDs (‘in’ for destination and ‘out’ for source) connected to the
edge and edge value (edge weight in this example).

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Phukon The Composite Graph Model for Web Document and its Impacts on Graph Distance Measurement p8
Kaushik K. Phukon

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Piana A graph representation of basic macroeconomic scheme p27

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Picard Coinductive Graph Representation p64.pdf

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Picard Permutations in Coinductive Graph Representation p20
Celia Picard

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Pisanski Graph representation.ppt

Popov Algorithm of the Week Graphs and Their Representation.docx

https://dzone.com/users/735767/stoimen.html

Stoimen Popov

Adjacency Matrix

Adjacency Lists

Quiz — Graph representations.docx

S. Raghavan and H. Garcia-Molina. Representing Web graphs. In Proc. 19th International Conference on Data Engineering (ICDE), page 405, 2003.

Rao Graph p19

Rajwant Singh Rao

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[Rocca2006]

Rocca The giRaph package for graph representation in R p1

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Rotta Graph Representation

sanfoundry Java Program to Describe the Representation of Graph using Adjacency List .docx

Manish Bhojasia

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Sb?rlea DFGR: an Intermediate Graph Representation for Macro-Dataflow Programs p8
Alina Sb?rlea

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[Schwarz2012]

Schwarz Graph Representations and Algorithms p164
We can represent a graph Map<Node*, Vector<Node*> > as a map from nodes to the list of nodes each node is connected to.

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Schwarz Graph Representations and Algorithms p164

Keith Schwarz

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Sedziwy Effective graph representation p13

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Seibert Learning Aspect Graph Representations from View Sequences p8

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Shai Transforming Engineering Problems through Graph Representations p28

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[Shaia1998]

Shaia Graph theory representations of engineering systems and their embedded knowledge p13
Graphs as representation of engineering systems
An engineering system is usually represented as a diagram, with nodes, lines, and words or numbers which assign values to some or all nodes or lines.
Flow graph representation
Definition of the flow graph representation: A directed graph G is a flow graph representation if the value of the flow in each edge is independent of the potential difference across that edge.
Potential graph representation
Definition of a potential graph: Let G be a graph in which for every vertex there will be associated a number which represents the potential at the vertex.

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Shkotin Graph representation of context-free grammars p4
Alex Shkotin

Siek Review of Elementary Graph Theory.docx

Graph Data Structures

Jeremy Siek, Indiana University (jsiek@osl.iu.edu)

http://www.boost.org/people/jeremy_siek.htm

2017-08-29

Adjacency Matrix

Adjacency List

Edge List

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Situngkir Small World Network of Athletes Graph Representation of the World Professional Tennis Player p13

[Slesarenko2015]

Slesarenko How to select the best graph representation for a given task p18

Alexander Slesarenko
Alexander Filippov
Alexey Romanov
Yuri Zotov

Flat Sparse Matrix

Flat Adjacency List

[Sommer2010]

Sommer 8.1 Graph Representation in Memory p14
Graph Representation in Memory

Christian Sommer

There are several possibilities to represent a graph G = (V;E) in memory.

Adjacency matrix

For instance, a matrix wastes a lot of memory if a sparse graph is given, but it has optimal access times for any type of graph.

Edge List

While being a space-ecient way to store the graph, the access times of an edge list are slower than the access times of an adjacency matrix (for most edges).

Adjacency List

Likewise, this is an ecient way to represent a graph but the access times are slower compared to a matrix (O(lg n) compared to O(1)). One way to solve this issue is to use a hash table for each node, containing all its neighbors.

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Sowa Conceptual Graphs p26
John F. Sowa

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Spinrad Efficient Graph Representations

????????????????????????????????????????????????????????????

stackoverflow Comparing object graph representation to adjacency list and matrix representations.docx

jbeard4

objects and pointers

adjacency list

matrix representations

????????????????????????????????????????????????????????????

[stoimen2012]

stoimen Computer Algorithms Graphs and their Representation.docx

Stoimen Popov

http://stoimen.com/blog

Adjacency Matrix

In case of directed graph, we can use 1 for the edge (i,j) and -1 for (j,i) in case the edge is directed from i to j. For a weighted directed graph we can put the weights instead of 1s.

In case that we’re using adjacency matrix we have:

  1. Adding an edge – O(1);
  2. Deleting an edge – O(1);
  3. Answering the question “is there an edge between i and j” – O(1);
  4. Finding the successors of a given vertex – O(n);
  5. Finding (if exists) a path between two vertices – O(n2);

Adjacency Lists

While for an adjacency list we can have:

  1. Adding an edge – O(log(n));
  2. Deleting an edge – O(log(n));
  3. Answering the question “is there an edge between i and j” – O(log(n));
  4. Finding the successors of a given vertex – O(k), where “k” is the length of the lists containing the successors of i;
  5. Finding (if exists) a path between two vertices – O(n+m) – where m <= n;

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[Stratis2014]

Stratis Graph Representation of Concurrent Programs in C++ p50

Graph Visualization
Our tool is able to provide a visual representation of all the afore-mentioned graphs. More specifically, the tool exports the graphs in the dot format which is supported by the GraphViz [8] software package and then (internally) utilizes GraphViz for producing digital images in png format representing each graph.

[suanfazu2015]

suanfazu Comparing object graph representation to adjacency list and matrix representations.docx

http://suanfazu.com/t/comparing-object-graph-representation-to-adjacency-list-and-matrix-representations/6841

Steve Yegge

http://steve-yegge.blogspot.com/2008/03/get-that-job-at-google.html

objects and pointers / object representation

objects and pointers
These are just basic datastructures like hammar said in the other answer, in Java you would represent this with classes like edges and vertices. For example an edge connects two vertices and can either be directed or undirected and it can contain a weight. A vertex can have an ID, name etc. Mostly both of them have additional properties. So you can construct your graph with them like

Vertex a = new Vertex(1);
Vertex b = new Vertex(2);
Edge edge = new Edge(a,b, 30); // init an edge between ab and be with weight 30

This approach is commonly used for object oriented implementations, since it is more readable and convenient for object oriented users

Objects and pointers is mostly the same as adjacency list, at least for the purpose of comparing algorithms that use these representations.
Compare

struct Node {
    Node *neighbours[];
};

with

struct Node {
    Node *left;
    Node *right;
};

You can easily construct the list of neighbours on-the-fly in the latter case, if it is easier to work with than named pointers.

Advantage of the object representation (incidence list) is that two adjacent vertices share the same instance of the edge. This makes it easy to manipulate with undirected edge data (length, cost, flow or even direction). However it uses extra memory for pointers.

matrix
A matrix is just a simple 2 dimensional array. Assuming you have vertex ID's that can be represented as an int array like this:

int[][] adjacencyMatrix = new int[SIZE][SIZE];
// SIZE is the number of vertices in our graph
adjacencyMatrix[0][1] = 30;
// sets the weight of a vertex 0 that is adjacent to vertex 1

This is commonly used for dense graphs where index access is necessary. You can represent a un/directed and weighted structure with this.

adjacency list
This is just a simple datastructure mix, I usually implement this using a HashMap<Vertex, List<Vertex>>. Similar used can be the HashMultimap in Guava.
This approach is cool, because you have O(1) (amortized) vertex lookup and it returns me a list of all adjacent vertices to this particular vertex I demanded.

ArrayList<Vertex> list = new ArrayList<>();
list.add(new Vertex(2));
list.add(new Vertex(3));
map.put(new Vertex(1), list); // vertex 1 is adjacent to 2 and 3

This is used for representing sparse graphs, if you are applying at Google, you should know that the webgraph is sparse. You can deal with them in a more scalable way using a BigTable1.

Sumitjain Graph Representation — Adjacency Matrix and Adjacency List.docx

http://algorithms.tutorialhorizon.com/author/sumitjain/

Adjacency Matrix and Adjacency List

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Tilstra COMPARING MATRIX-BASED AND GRAPH-BASED REPRESENTATIONS FOR PRODUCT DESIGN p6
Andrew H Tilstra

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[Trinks2012]
“Graph Polynomials and Their Representations”

Trinks Graph Polynomials and Their Representations p122

The title of this dissertation is chosen to include two possible meanings of the term “representation” in connection with graph polynomials. Mainly, by “representations for graph polynomials” we mean the frameworks (ways, formalisms, concepts) used to deVne graph polynomials. Thus, we are talking about an “edge subset representation” and a “coloring representation” if a graph polynomial is deVned as a sum over edge subsets and as a sum over colorings, respectively. As the name suggests, the chromatic polynomial is originally deVned in terms of colorings and therefore by a coloring representation.
Furthermore, it seems to be possible to expand this meaning and to refer to a graph polynomial equivalent to another graph polynomial, but deVned in another framework (representation), as a “representation” of the given graph polynomial. With this meaning, a representation of the chromatic polynomial is for example the adjoint polynomial, which is deVned as a sum over partitions and can be derived from the chromatic polynomial by replacing the falling factorials in an appropriate formulation by powers, and vice versa.

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https://unacademy.in/lesson/graph-representation-using-adjacency-list/TEUBD3N2

????????????????????????????????????????????????????????????

[Wagner2012]

Wagner Graph Representation.docx

Neal R. Wagner

Neal.Wagner@gmail.com

2017-09-01

adjacency list

adjacency matrix

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Wang Handwritten Word Spotting Based on Graph Representation p13

[Wang2012]

Wang Large-Scale Graph Processing Algorithms on the GPU p16
Yangzihao Wang

adjacency matrix

The adjacency matrix is an n  n matrix where the non-diagonal entry aij is the weight value from vertex i to vertex j, and the diagonal entry aii can be used to count loops on single vertices. For most large-scale
graphs, the resulting matrix is typically sparse; representing it directly as a sparse matrix allows the use of existing libraries for sparse matrix operations such as cuSparse. Katz et al.11 represent the adjacency matrix as a 2D texture in GPU memory. The downside of such a representation is its waste of space.

adjacency lists

adjacency lists provide more compact storage for more widespread sparse graphs.

A basic adjacency list stores all edges in a graph.

One typical way of implementing it is using one array to store a list of neighbor nodes and another array to store the offset of the neighbor list for each node.

Merrill et al.12 use the well-known compressed sparse row (CSR) sparse matrix format to represent graphs in their BFS implementation.
The column-indices array C and row-offsets array R are equivalent to the neighbor nodes list and the offset list in the basic adjacency list de nition. This representation enables them to use parallel primitives such as pre x sum to reorganize sparse and uneven workloads into dense and uniform ones in all phases of graph processing. In the context of parallel BFS, parallel threads use pre x sum when assembling global edge frontiers from expanded neighbors and when outputting unique unvisited vertices into global vertex frontiers.

Jia et al.10 represent the graph as an edge list to better assign edges to threads in their centrality algorithm. Instead of using two unequal length arrays|an o set array and a neighbor list array|they use two even length arrays to store the vertex pair for each edge. Their edge-centric representation requires more GPU memory though, which could limit their application to larger graphs.

v-graph (vector graph)

Blelloch3 proposes the v-graph (vector graph) for graph data representa- tion. This representation uses segmented vectors to store graph topology. For undirected graphs, it uses a single segmented vector to store edge information. Each segment corresponds to a vertex and each element within a segment corresponds to one of the edges of that vertex. For directed graphs, it uses two segmented vectors: one for the incoming edges, and one for the outgoing edges. Each element in the outgoing edges vector is a pointer to a position in the incoming edges vector. For both directed and undirected graphs, the representation uses additional vectors to include weights and other information. A graph can be con-
verted from most other representations into the v-graph representation by creating two elements per edge (one for each end) and sorting the edges according to their vertex number. Parallel sorting algorithms such
as radix sort can be used to place all edges that belong to the same vertex in a contiguous segment. The cross-pointer array in this representation enables an O(1) step complexity of dynamic graph manipulations such as adding or deleting an edge or a vertex, which is not easily accomplished with the other representations.

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Wang Text-Enhanced Representation Learning for Knowledge Graph p7

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Wolfram Graph Construction & Representation.docx

VertexList

EdgeList

VertexIndex

EdgeIndex

AdjacencyList

IncidenceList

EdgeRules

AdjacencyMatrix

IncidenceMatrix

KirchhoffMatrix

WeightedAdjacencyMatrix

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Wu Structural Opinion Mining for Graph-based Sentiment Representation p10

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Xirouhakis an efficient graph representation p6

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[Yin2004]

Yin W-graph representations for Coxeter groups and Hecke algebras p101
If W is a Coxeter group then a W graph provides a method for constructing a matrix representation of the Hecke algebra associated with W, the degree of the representation being the number of vertices of the W-graph.

[Zanibbi2009]

Graph Representations p2

Richard Zanibbi

rxzvcs@rit.edu (Teaching/Advising), rlaz@cs.rit.edu

Adjacency Matrix

Checking if (u, v) is an edge takes Θ(1) time.
Identifying all edges takes Θ(n2) time.

Adjacency List

Node indexed array of lists.
Two representations of each edge.
Space proportional to m + n.
Checking if (u, v) is an edge takes O(deg(u)) time.
Identifying all edges takes Θ(m + n) time.

degree = number of neighbors of u
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Zhao Semantic Single Video Segmentation with Robust Graph Representation p7

Zhao Semantic Single Video Segmentation with Robust Graph Representation p7


Untitled Document

Graph Representation
Literature Index

(2017-07-01 -- 2018-07-01)

Graph Data Structure

Books

Efficient Graph Representations (Fields Institute Monographs, 19) Hardcover – June 1, 2003 by Jeremy P. Spinrad (Author)

https://www.amazon.com/Efficient-Representations-Fields-Institute-Monographs/dp/0821828150


Untitled Document

Graph Representation
Literature Index

(2017-07-01 -- 2018-07-01)

okokok

[Abiy2016]

Abiy Graph implementation and representation.docx

November 3, 2016

Thaddeus Abiy, Christopher Williams, Josh Silverman

https://brilliant.org/profile/thaddeus-kcchug/

https://brilliant.org/profile/christopher-i6sq4v/

https://brilliant.org/profile/josh-8t4vhp/

[Abiy2016]

adjacency matrices

We tend to prefer adjacency matrices when the graphs are dense, that is, when the number of edges is near the maximum possible number, which is n2 for a graph of n nodes.

[Abiy2016]

Adjacency List

hashtable with an array in python

hashtable with linked lists in python

A common way to implement a graph using an adjacency list is to use either a hashtable with an array as values or use a hashtable with linked lists as a value. Since python combines the idea of arrays and linked lists we can easily implement this representation using a dictionary with nodes as keys and a list as a value.

However if the graphs is sparse, that is if most of the possible edges are not present, then the adjacency-list representation can save space.

To see why, note that an adjacency matrix for an n node graph has n2 bits, and therefore could be packed into n2/32-bit words. The common adjacency list cell will consist of two words, one for the node and one for the pointer to the next cell. Thus, if the number of edges is a , we need about 2a words for the lists, and n words for the array of headers. The adjacency list will use less space than the adjacency matrix if

n+2a<n2/32

The following table summarizes the preferred representation for various operations:

operations | dense graph | sparse graph
lookup edge | adjacency matrix | either
find successor | either | adjacency list
find predeccessor | adjacency matrix | either

Let us assume the graph is represented by adjacency lists, so we can find all edges in O(m) time.

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[Abu-Khzam2010a]

Abu-Khzam A Hybrid Graph Representation for Exact Graph Algorithms p15

8

Faisal N. Abu-Khzam

http://www.csm.lau.edu.lb/fabukhzam/

Department of Computer Science and Mathematics
Lebanese American University, Beirut, Lebanon.

Research Interests: Exact and Parameterized Algorithms, High Performance Computing, Combinatorial Optimization, Graph Theory and Computational

faisal.abukhzam@lau.edu.lb

faisal.abukhzam@lau.edu.lb

???????????

Karim A. Jahed

Department of Computer Science and Mathematics
Lebanese American University, Beirut, Lebanon.

karim.jahed@lau.edu.lb

???????????

Amer E. Mouawad

David R. Cheriton School of Computer Science
University of Waterloo, Ontario, Canada.
aabdomou@uwaterloo.ca

[Abu-Khzam2010a]

Hybrid Graph Representation ( adjacency matrices + adjacency lists)

The hybrid data structure was designed with an eye on efficient graph modification operations during backtracking.

In this paper, we show how a simple combination of the two representations can be used to facilitate the undo of many basic graph operations, especially deletions, thereby improving the running time of recursive backtracking (search) algorithms. Generally, every operation that can be taken back is pushed onto a stack and later popped out and performed in reverse. We refer to this action by explicit-undo. Our implicit-undo objective is achieved via a highly efficient use of a processor’s control stack only.

In addition, some basic operations like adjacency query and neighborhood traversal are also performed efficiently.

In addition to effective backtracking, the hybrid representation combines the advantage of constant time adjacency-queries in adjacency-matrices and the advantage of efficient neighborhood traversal in adjacency-lists. This method works well on simple unweighted graphs and may be extended to weighted graphs. Compared to the use of an adjacency list, the hybrid representation yields improved running times for vertex and edge deletion, permanent edge addition, as well as computing common neighbors.

The hybrid graph representation is best described using a simple example such as the one given in Figure 1.

The adjacency list of a vertex v is stored in an array denoted by AL[v]. Accordingly, AL[v][i] holds the index of the ith vertex in the list of neighbors of v. The adjacency matrix (??? or rahter Index Matrix), denoted henceforth by IM, is used as an index table for the adjacency list as follows: the entry IM [u][v] is equal to the index of u in AL[v]. IM [u][v] is set to ?1 when the two vertices are not adjacent.

Considering the 8-vertex graph G = (V,E), the initial contents of AL and im are shown in Figure 1.

Note that AL is implemented using a two dimensional array for fast (direct) access via the indexing provided by IM. In general, we allocate enough memory to fit the neighbors of each vertex only.

In addition to IM and AL, we introduce three linear arrays: the degree vector (DEG), the vertex list (LIST), and the vertex index list (IDXLIST).

The degree vector (DEG) holds the current neighborhood cardinality of each vertex.

LIST contains the list of currently active (not deleted) vertices which we use instead of the degree vector for more efficient complete graph traversals.

IDXLIST stores the index of each vertex in LIST.

In other words, LIST[i] is the i th vertex in the list of active vertices

IDXLIST[u] is the index of vertex u in LIST.

All data structures except for the deg vector are global and their memory is allocated at startup only. The DEG vector is local to every search-tree node (i.e., every recursive call, since a copy of the vector is passed as parameter).

In the next section, we show how the above structures are dynamically updated during a search algorithm, while performing various graph modification operations. We note that some operations, like edge contraction for example, require additional bookkeeping that we briefly describe later. However, most common operations can be performed using the five data structures described above, which when combined together form the (generic) hybrid graph representation.

adjacency query

For example, checking if two vertices u and v are adjacent takes ??(1) time: just check whether ?1 < IM[u][v] < DEG[v].

Graph traversal.

Graph traversal is another frequent operation, often used to select a vertex or an edge having a certain property during branching algorithms. A complete graph traversal runs in ??(nc) time as opposed to ??(n), where nc is the number of currently active vertices in the graph. This is possible because of our use of
the LIST and IDXLIST vectors. In the rest of this section, we discuss how the hybrid method is used for graph modification operations.

Edge Deletion

The simplest and most frequent operation performed during the search is probably edge deletion. Maintaining the hybrid data structure in this case is straight- forward.

For deleting an edge (u, v), the degrees of u and v are decremented by one and the adjacency lists of the two vertices are adjusted respectively by placing u at the last position of AL[v] and v at the last position of AL[u] (Figure 2).

Each of these two operations consists of a single swap with the last element of the respective list, together with an adjustment of the positions in IM.

Going back to our illustrative graph G, after deleting edge (v0, v3), the modified AL, IM, and DEG vectors will be as shown in Figure 3 (changes are shown in gray).

No changes to LIST and IDXLIST are required for edge deletion since no vertices are removed from the graph.

Notice that this operation runs in ??(1) time as all the information required for switching positions in AL can be found in IM. Vertex v3 is no longer a neighbor of vertex v0 because IM[0][3] = 2 which is not less than DEG[0] = 2.

Undo Edge Deletion

Now assume we want to undo the previous operation. This can be accomplished by simply setting DEG[0] and DEG[3] back to 3. There is no need to change IM and AL back to the previous state since no specific order is required for storing vertex neighbors. Moreover, since every search-tree node maintains its own copy of the DEG vector, there are actually no actions whatsoever that need to be taken for undoing edge deletion. Thus we have an implicit-undo for edge deletion operations. This implicit undo runs in ??(1) time.

####################################

Edge Contraction

The next operation we consider is edge contraction. Contracting edge (u, v) replaces vertices u and v by a new vertex whose neighborhood is N(u) [ N(v) \ {u, v}.

To achieve our implicit-undo objective, we implement this operation using a coloring technique that requires additional bookkeeping.

Simply, vertices with the same color are treated as one single vertex obtained by contracting edges between them.

Initially, every vertex vi is assigned color ci, and every color class ci has cardinality one and degree d(ci) = d(vi).

In addition to previously discussed data structures, we use the following (see Figure 5):
– vcolor vector: holds the current color of every vertex.
– color card (cc) vector: holds the current cardinality of every color set.
– color degree (cd) vector: holds the current degree of every color set.
– color set list (csl): holds the list of vertices belonging to every color set.

Given that all operations now involve color sets, the LIST and IDXLIST do not hold vertex information anymore, but they maintain the list of active (not deleted) colors instead. If no edge contraction operations are performed, color sets would be identified by their corresponding vertices (or vice-versa).

When edge contraction is possible, the initial state of the graph G consists of all data structures previously discussed. AL, IM, CSL, LIST and IDXLIST would be globally stored (in RAM), while DEG, CD, CC and vcolor would be copied at every search-tree node.

To contract an edge, say (v3, v6), we actually assign both vertices the same color. Assuming we assign the two vertices color c3, the required modifications are shown in Figure 6 (changes shown in gray). Since we are dealing with simple graphs, any edge between two vertices belonging to the same color set is deleted and no more than one edge is allowed between a color set and another. Clearly, such an operation can be implicitly taken back as well, but is also more time and space consuming than simple vertex deletion. This technique makes it possible to implement the vertex folding operation, introduced in [8], for the parameterized vc algorithm.

Permanent Edge Addition

An edge addition performed at a search-tree node is considered permanent if no descendant search-tree node later modifies the operation (by edge or vertex deletion). In some problems, such as Cluster Editing, searching for a solution involves edge deletions as well as permanent edge additions.

Using the classical adjacency list structure, it would be impossible to incorporate edge addition without extra bookkeeping to record changes to the AL. To incorporate the permanent edge addition operation to our hybrid data structure, we make the following modifications:

(i) enough global memory is allocated to AL (i.e. n-by-n matrix where n is the size of the input graph), and

(ii) an additional degree vector (NDEG) is maintained at every search node.

The additional memory requirement guarantees storage space and the NDEG vector serves as a second degree vector. Figure 7 illustrate the required changes to the extended hybrid data structure after adding edge (v2, v6) to our original graph G.

The adjacency query still takes ??(1) time but requires an additional condition:

u and v are adjacent when ?1 <IM[u][v] < DEG[v] or ?1 < n ? 1 ? IM[u][v] < NDEG[v].

Neighborhood traversal becomes slightly more complicated but the time complexity remains unchanged. Undoing this operation only requires setting NDEG[2] and NDEG[6] back to 0 and subsequent addition of edges incident on v2 or v6 could overwrite older positions.

Vertex Deletion

In a typical computation using adjacency lists, deleting a vertex v of current degree d requires traversing the list of neighbors of v and deleting v from the list of each of its neighbors. This operation runs in ??(Δ(G)2) time.

Using our hybrid computation, deleting a vertex v runs in ??(d) time where d is the (current) degree of v. This is simply performed by running the edge deletion operation for every active neighbor of v (Figure 4). In addition, we remove v from the list of active vertices by swapping it with the last active vertex in LIST and decrementing the number of active vertices by one. The IDXLIST plays the same role as IM for deleting a vertex from LIST.

To illustrate the purpose of the list vector, suppose we need to pick a vertex with a particular property, such as one of maximum degree (which is often needed for heuristic priorities).

Consider the two operations of copying the deg vector and searching for the vertex of highest degree. Doing so would consume (n) time if the deg vector is used alone. This is reduced to ??(nc), where nc is the number of currently active vertices. To see why, note that iterating from i = 0 to nc only, DEG[LIST[i]]
returns the degree of the vertex at position i in LIST. Knowing that a great majority of search tree nodes are near the bottom of a search tree, where the graph order is almost constant, this simple strategy alone makes a substantial difference.

Undo Vertex Deletion

As in the case of edge-deletion, the undo of vertex deletion is implicit (requires no action) when separate degree vectors are maintained at every search node. This is due to the fact that edge deletion can be considered as an independent operation. The only required operation is to increment the number of active
vertices by one (if this value is stored globally) so that the LIST and IDXLIST vectors reflect the re-insertion of a vertex. Explicitly undoing a vertex deletion operation runs in ??(d) time where d is the degree of the deleted vertex (it mainly consists of incrementing the degree of each neighbor by one.)

The Vertex Cover Folding Operation

Let (G, k) be an instance of the Vertex Cover problem and let u ∈ V (G) be a degree-two vertex with neighbors v and w. If v and w are adjacent, then there is a minimum vertex cover that contains v and w (and not u). So it is safe to delete u, add v and w to the potential solution and decrement k by two. In the
case where v and w are non-adjacent, an equivalent Vertex Cover instance is obtained by contracting edges uv and uw and decrementing k by one. This latter operation is known as degree-two vertex folding [8].

As we shall see, applying the coloring technique to implement vertex folding considerably improves the runtime on certain recalcitrant instances, but slows down the computation on graphs where folding rarely occurs. In such cases, the overhead of maintaining color-sets is a drawback. Note that folding alone made it possible to obtain a worst-case running time of ??(1.285k) in [8]. Yet, our results show that excluding folding from the same algorithm is faster on a large number of instances, except for the case where is graph is regular (or nearly regular) where other reduction methods do no apply.

Table 1. Runtime comparison for different search-operations using al, am, and the hybrid graph representation. We denote by n the number of vertices in the graph, by d(v) the degree of a vertex v, and d(c) denotes the degree of a color-set c.

Operation Adjacency Matrix Adjacency List Hybrid
Adjacency Query ??(1) ??(d(v)) ??(1)
Neighborhood Traversal ??(n) ??(d(v)) ??(d(v))
Edge Deletion ??(1) ??(d(v)) ??(1)
Undo Edge Deletion ??(1) ??(1) ??(1)
Vertex Deletion ??(n) ??(d(v)2) ??(d(v))
Undo Vertex Deletion ??(d(v)) ??(d(v)) ??(1)
Edge Contraction ??(n) ??(d(v)) ??(d(c))
Undo Edge Contraction ??(d(v)) ??(d(v)) ??(1)
Edge Addition ??(1) ??(1) ??(1)
Undo Edge Addition ??(1) ??(d(v)) ??(1)

neighborhood traversal

Neighborhood search

Neighborhood search, on the other hand, runs in ??(d) time, where d is the current vertex degree

????????????????????????????????

Contents same as the previous article

[Abu-Khzam2010b]

Abu-Khzam A Hybrid Graph Representation for Recursive Backtracking Algorithms p12

A Hybrid Graph Representation for Recursive Backtracking Algorithms
(joint work with M. A. Langston, A. E. Mouawad and C. P. Nolan)
in Proceedings of the 4th International Frontiers of Algorithmics Workshop (FAW 2010), Wuhan, China, August 2010, pages 136-147.

8

F. N. Abu-Khzam
Department of Computer Science and Mathematics
Lebanese American University
Beirut, Lebanon
faisal.abukhzam@lau.edu.lb
http://www.csm.lau.edu.lb/fabukhzam

A. E. Mouawad

Department of Computer Science and Mathematics
Lebanese American University
Beirut, Lebanon
amer.mouawad@lau.edu.lb

M. A. Langston

Department of Electrical Engineering and Computer Science
University of Tennessee
Knoxville, TN 37996-3450 USA
langston@eecs.utk.edu
http://www.cs.utk.edu/~langston

C. P. Nolan

Department of Electrical Engineering and Computer Science
University of Tennessee
Knoxville, TN 37996-3450 USA
nolan@eecs.utk.edu

????????????????????????????????

[AHS]

https://sites.google.com/a/lps.k12.co.us/ahscs2p/graphs-graph-algorithms/an-adjacency-list

[AHS]

An Adjacency List

A more space-efficient way to implement a sparsely connected graph is to use an adjacency list. In an adjacency list implementation we keep a master list of all the vertices in the Graph object and then each vertex object in the graph maintains a list of the other vertices that it is connected to. In our implementation of the Vertex class we will use a dictionary rather than a list where the dictionary keys are the vertices, and the values are the weights. Figure 4 illustrates the adjacency list representation for the graph in Figure 2.

The advantage of the adjacency list implementation is that it allows us to compactly represent a sparse graph. The adjacency list also allows us to easily find all the links that are directly connected to a particular vertex.

??????????????????????????????????

[AHUJA1993]

AHUJA Network Flows Theory, Algorithms, and Applications Ch1_3 p103

Ahuja, R.K., Magnanti, T.L. and Orlin J.B. (1993) “Network Flows”, Prentice-Hall, NJ.

38

RAVINDRA K. AHUJA

http://www.ise.ufl.edu/ahuja/

Ravindra K. Ahuja

Professor
Co-Director SCaLE Center
Industrial and Systems Engineering
University of Florida
303 Weil Hall
P.O. Box 116595
Gainesville, FL 32611-6595

ahuja@ufl.edu

President & CEO,

Optym
7600 NW 5th Place, Gainesville, FL 32607

ravindra.ahuja@optym.com
Office: (352) 334-7283, ext: 347
Cell: (352) 870-8401
Fax: (866) 805-4130

THOMAS L. MAGNANTI

http://mitsloan.mit.edu/faculty-and-research/faculty-directory/detail/?id=41181

Thomas Magnanti

  • Institute Professor
  • Professor of Operations Research

  • 32-D784
  • (617) 253-6604
  • (617) 258-8682
  • magnanti@mit.edu
  • http://web.mit/edu/engineering/deans/magnanti.html

JAMES B. ORLIN

http://jorlin.scripts.mit.edu/

http://mitsloan.mit.edu/faculty-and-research/faculty-directory/detail/?id=15027

Jim Orlin

  • E. Pennell Brooks (1917) Professor in Management
  • Professor of Operations Research

  • E62-570
  • (617) 253-6606
  • (617) 258-7579
  • jorlin@mit.edu
  • http://jorlin.scripts.mit.edu/

Contact Information
Office: E62-570
e-mail: jorlin at mit dot edu

Tel: 617-253-6606
Fax: 617-258-7579

Support Staff
Name: Tyler Morse
Tel: 617-253-2656
E-mail: tamorse@mit.edu

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[AHUJA1993]

(Node-Node) Adjacency Matrix

page 33

The node-node adjacency matrix representation, or simply the adjacency matrix representation, stores the network as an n x n matrix ? = {hij}. The matrix has a row and a column corresponding to every node, and its ij th entry hij equals 1 if (i, j) ∈ A and equals 0 otherwise. Figure 2.15 specifies this representation for the network shown in Figure 2.13. If we wish to store arc costs and capacities as well as the network topology, we can store this information in two additional n x n matrices, ? and ??.

The adjacency matrix has n2 elements, only m of which are nonzero. Consequently, this representation is space efficient only if the network is sufficiently dense; for sparse networks this representation wastes considerable space.

Nevertheless, the simplicity of the adjacency representation permits us to use it to implement most network algorithms rather easily.

We can determine the cost or capacity of any arc (i, j) simply by looking up the ij th element in the matrix ? or ??.

We can obtain the arcs emanating from node i by scanning row i: If the jth element in this row has a nonzero entry, (i, j) is an arc of the network. Similarly, we can obtain the arcs entering node j by scanning columnj: If the ith element of this column has a nonzero entry, (i,j) is an arc of the network. These steps permit us to identify all the outgoing or incoming arcs of a node in time proportional to n. For dense networks we can usually afford to spend this time to identify the incoming or outgoing arcs, but for sparse networks these steps might be the bottleneck operations for an algorithm.

[AHUJA1993]

(Node-Arc) Incidence Matrix

The node-arc incidence matrix representation, or simply the incidence matrix representation, represents a network as the constraint matrix of the minimum cost flow problem that we discussed in Section 1.2. This representation stores the network as an n x m matrix ?? which contains one row for each node of the network and one column for each arc. The column corresponding to arc (i,j) has only two nonzero elements: It has a + 1 in the row corresponding to node i and a -I in the row corresponding to node j. Figure 2.14 gives this representation for the network shown in Figure 2.13.

The node-arc incidence matrix has a very special structure: Only 2m out of its nm entries are nonzero, all of its nonzero entries are + 1 or - 1, and each column has exactly one + 1 and one -1. Furthermore, the number of + 1 's in a row equals the outdegree of the corresponding node and the number of - 1 's in the row equals the indegree of the node.

Because the node-arc incidence matrix ?? contains so few nonzero coefficients, the incidence matrix representation of a network is not space efficient. More efficient schemes, such as those that we consider later in this section would merely keep track of the nonzero entries in the matrix. Because of its inefficiency in storing the underlying network topology, use of the node-arc incidence matrix rarely produces efficient algorithms.

This representation is important, however, because it represents the constraint matrix of the minimum cost flow problem and because the node-arc incidence matrix possesses several interesting theoretical properties.

[AHUJA1993]

Adjacency List:

page 25

The arc adjacency list A(i) of a node i is the set of arcs emanating from that node, that is, A(i) = {(i,j) ∈ A: j ∈N}.

Earlier we defined the arc adjacency list A(i) of a node i as the set of arcs emanating from that node, that is, the set of arcs (i, j) ∈ A obtained as j ranges over the nodes of the network.

The node adjacency list A(i) is the set of nodes adjacent to that node; in this case, A(i) = {j ∈ N: (i,j) ∈ A}.

Similarly, we defined the node adjacency list of a node i as the set of nodes j for which (i, j) ∈ A.

The adjacency list representation stores the node adjacency list of each node as a singly linked list (we refer the reader to Appendix A for a description of singly linked lists). A linked list is a collection of cells each containing one or more fields. The node adjacency list for node i will be a linked list having |A (i)| cells and each cell will correspond to an arc (i, j) ∈A. The cell corresponding to the arc (i, j) will have as many fields as the amount of information we wish to store. One data field will store node j. We might use two other data fields to store the arc cost ?ij and the arc capacity ??ij. Each cell will contain one additional
field, called the link, which stores a pointer to the next cell in the adjacency list. If a cell happens to be the last cell in the adjacency list, by convention we set its link to value zero.

Since we need to be able to store and access n linked lists, one for each node, we also need an array of pointers that point to the first cell in each linked list. We accomplish this objective by defining an n-dimensional array, first, whose element first(i) stores a pointer to the first cell in the adjacency list of node i. If the adjacency list of node i is empty, we set first(i) = 0. Figure 2.16 specifies the adjacency list representation of the network shown in Figure 2. 13.

In this book we sometimes assume that whenever arc (i,j) belongs to a network, so does the reverse arc (j, i). In these situations, while updating some information about arc (i, j), we typically will also need to update information about arc (j, i). Since we will store arc (i, j) in the adjacency list of node i and arc (j, i) in the adjacency list of node j, we can carry out any operation on both arcs efficiently if we know where to find the reversal (j, i) of each arc (i,j). We can access both arcs easily if we define an additional field, mate, that contains a pointer to the cell containing data for the reversal of each arc. The mate of arc (i, j) points to the cell of arc (j, i) and the mate of arc (j, i) points to the cell of arc (i, j).

Often, we shall omit the terms "arc" and "node" and simply refer to the adjacency list; in all cases it will be clear from context whether we mean arc adjacency list or node adjacency list.

We assume that arcs in the adjacency list A(i) are arranged so that the head nodes of arcs are in increasing order.

Notice that |A(i)| equals the outdegree of node i. Since the sum of all node outdegrees equals m, we immediately obtain the following property:

Property 2.1. ∑ i ∈ N | A(i) | = m.

[AHUJA1993]

(Forward and Reverse) Star Representations

The forward star representation of a network is similar to the adjacency list representation in the sense that it also stores the node adjacency list of each node. But instead of maintaining these lists as linked lists, it stores them in a single array.

To develop this representation, we first associate a unique sequence number with each arc, thus defining an ordering of the arc list.

We number the arcs in a specific order: first those emanating from node 1, then those emanating from node 2, and so on.

We number the arcs emanating from the same node in an arbitrary fashion.

We then sequentially store information about each arc in the arc list. We store the tails, heads, costs, and capacities of the arcs in four arrays: tail, head, cost, and capacity. So if arc (i, j) is arc number 20, we store the tail, head, cost, and capacity data for this arc in the array positions tail(20), head(20), cost(20), and capacity(20).

We also maintain a pointer with each node i, denoted by point(i), that indicates the smallest numbered arc in the arc list that emanates from node i. [If node i has no outgoing arcs, we set point(i) equal to point(i + 1).] Therefore, the forward star representation will store the outgoing arcs of node i at positions point(i) to (point(i + 1) - 1) in the arc list. If point(i) > point(i + 1) - 1, node i has no outgoing arc. For consistency, we set point(l) = 1 and point(n + 1) = m + 1.

Figure 2. 17(a) specifies the forward star representation of the network given in Figure 2.13.

The forward star representation provides us with an efficient means for determining the set of outgoing arcs of any node.

To determine, simultaneously, the set of incoming arcs of any node efficiently, we need an additional data structure known as the reverse star representation. Starting from a forward star representation,
we can create a reverse star representation as follows. We examine the nodes i = 1 to n in order and sequentially store the heads, tails, costs, and capacities of the incoming arcs at node i. We also maintain a reverse pointer with each node i, denoted by rpoint(i), which denotes the first position in these arrays that contains information about an incoming arc at node i. [If node i has no incoming arc, we set rpoint(i) equal to rpoint(i + 1).] For sake of consistency, we set rpoint(l) = 1 and rpoint(n +.1) = m + 1. As before, we store the incoming arcs at node i at positions rpoint(i) to (rpoint(i + 1) - 1). This data structure gives us the representation shown in Figure 2.17(b).

Observe that by storing both the forward and reverse star representations, we will maintain a significant amount of duplicate information. We can avoid this duplication by storing arc numbers in the reverse star instead of the tails, heads, costs, and capacities of the arcs. As an illustration, for our example, arc (3, 2) has arc number 4 in the forward star representation and arc (1, 2) has an arc number 1. So instead of storing the tails, cos~s, and capacities of the arcs, we simply store arc numbers; and once we know the arc numbers, we can always retrieve the associated information from the forward star representation. We store arc Qumbers in an array trace of size m. Figure 2.18 gives the complete trace array of our example.

In our discussion of the adjacency list representation, we noted that sometimes while updating data for an arc (i, j), we also need to update data for its reversal (j, i). Just as we did in the adjacency list representation, we can accomplish this task by defining an array mate of size m, which stores the arc number of the reversal of an arc. For example, the forward star representation shown in Figure 2.17(a)
assigns the arc number 6 to arc (4, 5) and assigns the arc number 8 to arc (5, 4). Therefore, if we were using the mate array, we would set mate(6) = 8 and mate(8) = 6.

Storing Parallel Arcs

Both the adjacency list representation and the forward star representation data structures are capable of handling parallel arcs. If a node i has two outgoing arcs with the same head node but (possibly) different costs and capacities, the linked list of node i will contain two cells corresponding to these two arcs. Similarly, the forward star representation allows several entries with the same tail and head nodes but different costs and capacities.

[AHUJA1993]

Representing Undirected Networks

We can represent undirected networks using the same representations we have just described for directed networks. However, we must remember one fact: Whenever arc (i, j) belongs to an undirected network, we need to include both of the pairs (i,j) and (j, i) in the representations we have discussed. Consequently, we will store each arc (i, j) of an undirected network twice in the adjacency lists, once in the list for node i and once in the list for node j.

Some other obvious modifications are needed.

For example, in the node-arc incidence matrix representation, the column corresponding to arc (i, j) will have + 1 in both rows i and j.

The node-node adjacency matrix will have + 1 in position hij and hji ; for every arc (i, j) ∈ A. Since this matrix will be symmetric, we might as well store half of the matrix.

In the adjacency list representation, the arc (i, j) will be present in the linked lists of both nodes i and j. Consequently, whenever we update information for one arc, we must update it for the other arc as well. We can accomplish this task by storing for each arc the address of its other occurrence in an additional mate array.

The forward star representation requires this additional storage as well. Finally, observe that undirected networks do not require the reverse star representation.

=================

[AHUJA1993]

Comparison of Forward Star and Adjacency List Representations

The major advantage of the forward star representation is its space efficiency. It requires less storage than does the adjacency list representation.

In addition, it is much easier to implement in languages such as FORTRAN that have no natural provisions for using linked lists.

On the other hand, in the forward star representation these steps - add or delete arcs (as well as nodes) - require time proportional to m, which can be too time consuming.

The major advantage of adjacency list representation is its ease of implementation in languages such as Pascal or C that are able to manipulate linked lists efficiently.

Further, using an adjacency list representation, we can add or delete arcs (as well as nodes) in constant time.

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[AlgoList]

Undirected graphs representation

AlgoList Undirected graphs representation.docx

http://www.algolist.net/Data_structures/Graph/Internal_representation

http://www.algolist.net/Data_structures/Graph

[AlgoList]

Adjacency matrix

Each cell aij of an adjacency matrix contains 1, if there is an edge between i-th and j-th vertices, and 0 otherwise.

Adjacency matrix is a good solution for dense graphs, which implies having constant number of vertices.

Adjacency matrix is optimal for dense graphs, but for sparse ones it is superfluous.

Advantages.

Adjacency matrix is very convenient to work with. Add (remove) an edge can be done in O(1) time, the same time is required to check, if there is an edge between two vertices.

Also it is very simple to program

Disadvantages.

  • Adjacency matrix consumes huge amount of memory for storing big graphs. All graphs can be divided into two categories, sparse and dense graphs. Sparse ones contain not much edges (number of edges is much less, that square of number of vertices, |E| << |V|2). On the other hand, dense graphs contain number of edges comparable with square of number of vertices.
  • in many algorithms you need to know the edges, adjacent to the current vertex. To draw out such an information from the adjacency matrix you have to scan over the corresponding row, which results in O(|V|) complexity. For the algorithms like DFS or based on it, use of the adjacency matrix results in overall complexity of O(|V|2), while it can be reduced to O(|V| + |E|), when using adjacency list.
  • adjacency matrix requires huge efforts for adding/removing a vertex. In case, a graph is used for analysis only, it is not necessary, but if you want to construct fully dynamic structure, using of adjacency matrix make it quite slow for big graphs.

[AlgoList]

Adjacency list

For every vertex adjacency list stores a list of vertices, which are adjacent to current one.

It requires less amount of memory

To sum up, adjacency list is a good solution for sparse graphs and lets us changing number of vertices more efficiently, than if using an adjacent matrix. But still there are better solutions to store fully dynamic graphs.

Advantages.

Adjacent list allows us to store graph in more compact form, than adjacency matrix, but the difference decreasing as a graph becomes denser.

Next advantage is that adjacent list allows to get the list of adjacent vertices in O(1) time, which is a big advantage for some algorithms.

Disadvantages.

  • Adding/removing an edge to/from adjacent list is not so easy as for adjacency matrix. It requires, on the average, O(|E| / |V|) time, which may result in cubical complexity for dense graphs to add all edges.
  • Check, if there is an edge between two vertices can be done in O(|E| / |V|) when list of adjacent vertices is unordered or O(log2(|E| / |V|)) when it is sorted. This operation stays quite cheap.
  • Adjacent list doesn't allow us to make an efficient implementation, if dynamically change of vertices number is required. Adding new vertex can be done in O(V), but removal results in O(E) complexity.
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[Amar2014]
Amar Majority-Inverter Graph A Novel Data-Structure and Algorithms for Efficient Logic Optimization p6

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Appel An Alternate Graph Representation for the Tiger Compiler.docx

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[Arikati1997]

Arikati Efficient computation of implicit representations of sparse graphs p16

Srinivasa R. Arikati

doubly-linked adjacency lists

G is given in the standard form of doubly-linked adjacency lists.

(Remark: Only for our EREW PRAM algorithms, we will further assume that the adjacency lists are provided with the so-called cross-links: the entry for u in the adjacency list of vertex u is provided,
in addition to its identification, with a pointer to v’s entry in the adjacency list of u. For details, see e.g. [7, 81.)

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[Atminas2014]

Atminas Implicit Representations and Factorial Properties of Graphs p28


Untitled Document

Graph Representation
Literature Index

(2017-07-01 -- 2018-07-01)

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[Balkcom]

Balkcom Project Python chapter18 Graph

http://projectpython.net/chapter00/

http://projectpython.net/chapter18/

http://www.cs.dartmouth.edu/~devin/craftypython/chapter19/

Devin Balkcom

Project Python is a free interactive book that will teach you to code in Python, using graphics, animations, and games. You’ll also learn ways to solve classical computer science problems, principles of software design, and how to analyze algorithm performance. No prior experience required; you’ll write code to draw a smiley face by the end of the first chapter.

[Balkcom]

Edge lists

One simple representation is just a Python list of m edges, which we call an edge list. To represent an edge, we just give the numbers of the two vertices it’s incident on. Each edge in the list is either a Python list with two vertex numbers or a tuple comprising two vertex numbers. If the edge has a weight, add a third item giving the weight.

Edge lists are simple, but if we want to find whether the graph contains a particular edge, we have to search through the edge list. If the edges appear in the edge list in no particular order, that’s a linear search through m edges. Question to think about: How can you organize an edge list to make searching for a particular edge take O(log?m) time? The answer is a little tricky.

[Balkcom]

Adjacency matrices

For a graph with n vertices, an adjacency matrix is an n?×?n matrix of 0s and 1s, where the entry in row i and column j is 1 if and only if the edge (i,?j) is in the graph. (Recall that we can represent an n?×?n matrix by a Python list of n lists, where each of the n lists is a list of n numbers.) If you want to indicate an edge weight, put it in the row i, column j entry, and reserve a special value (say, None) to indicate an absent edge. Here’s a unweighted, undirected graph and its adjacency matrix:

With an adjacency matrix, we can find out whether an edge is present in constant time, by just looking up the corresponding entry in the matrix. So what’s the disadvantage of an adjacency matrix? Two things, actually. First, it takes Θ(n2) space, even if the graph is sparse: relatively few edges. In other words, for a sparse graph, the adjacency matrix is mostly 0s, and we use lots of space to represent only a few edges. Second, if you want to find out which vertices are adjacent to a given vertex i, you have to look at all n entries in row i, taking Θ(n) time, even if only a small number of vertices are adjacent to vertex i.

For an undirected graph, the adjacency matrix is symmetric: the row i, column j entry is 1 if and only if the row j, column i entry is 1. For a directed graph, the adjacency matrix need not be symmetric.

[Balkcom]

Adjacency lists

Representing a graph with adjacency lists combines adjacency matrices with edge lists. For each vertex x, store a list of the vertices adjacent to it. We typically have a Python list of n adjacency lists, one adjacency list per vertex. We can store an adjacency list with a Python list (if we don’t plan to insert or delete adjacent vertices) or a linked list (if we expect to insert or delete adjacent vertices). Here’s an adjacency-list representation of the graph from above, using Python lists:

We can get to each vertex’s adjacency list in Θ(1) time, because we just have to index into a Python list of adjacency lists. To find out whether an edge (x,?y) is present in the graph, we go to x’s adjacency list in Θ(1) time and then look for y in x’s adjacency list. How long does that take? O(d), where d is the degree of x, because that’s how long x’s adjacency list is. The degree of x could be as high as n???1 (if x is adjacent to all other n???1 vertices) or as low as 0 (if x is isolated, with no incident edges). In an undirected graph, y is in x’s adjacency list if and only if x is in y’s adjacency list. If the graph is weighted, then each item in each adjacency list is either a two-item list or a 2-tuple, giving the vertex number and the edge weight.

How much space do adjacency lists take? We have n lists, and although each list could have as many as n???1 vertices, in total the adjacency lists for an undirected graph contain 2m items. Why 2m? Each edge (x,?y) appears exactly twice in the adjacency lists, once in x’s list and once in y’s list, and there are m edges. For a directed graph, the adjacency lists contain a total of m items, one item per directed edge. For either an undirected graph or a directed graph, we say that the adjacency-list representation takes Θ(n?+?m) space; the n term comes from list of vertices, and the m term comes from all the adjacency lists together.

Adjacency lists in objects

For Lab Assignment 4, you’ll be creating several Vertex objects. Among its instance variables, each Vertex object will have one that is a reference to a Python list of Vertex objects, indicating the adjacent vertices. There will be two ways to get to a Vertex object: through the adjacency list of some other Vertex object, or through a dictionary whose keys are names of vertices and whose values are Vertex objects.

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[Barnes2015]

Barnes Graphs

G. Michael Barnes

[Barnes2015]

Adjacency List

nodes stored in collection (JFC: Arraylist, TreeMap, HashMap) where each node has list of references to adjacent nodes ‘a’ is the vertex and ‘A’ is a pointer to ‘a’

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Barnett Data Structures and Algorithms p112

G:\studies\000Webit\000programming\ccpp

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[Barnwal]

Barnwal Graph and its representations.docx

Aashish Barnwal

The choice of the graph representation is situation specific. It totally depends on the type of operations to be performed and ease of use.

[Barnwal]

Adjacency Matrix

Adjacency matrix for undirected graph is always symmetric. Adjacency Matrix is also used to represent weighted graphs. If adj[i][j] = w, then there is an edge from vertex i to vertex j with weight w.

Pros: Representation is easier to implement and follow. Removing an edge takes O(1) time. Queries like whether there is an edge from vertex ‘u’ to vertex ‘v’ are efficient and can be done O(1).

Cons: Consumes more space O(V^2). Even if the graph is sparse(contains less number of edges), it consumes the same space. Adding a vertex is O(V^2) time.

[Barnwal]

Adjacency List

An array of linked lists is used. Size of the array is equal to number of vertices. Let the array be array[]. An entry array[i] represents the linked list of vertices adjacent to thei th vertex. This representation can also be used to represent a weighted graph. The weights of edges can be stored in nodes of linked lists. Following is adjacency list representation of the above graph.

Pros: Saves space O(|V|+|E|) . In the worst case, there can be C(V, 2) number of edges in a graph thus consuming O(V^2) space. Adding a vertex is easier.

Cons: Queries like whether there is an edge from vertex u to vertex v are not efficient and can be done O(V).

Incidence Matrix

Incidence List

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Barták Graphs in Prolog.docx

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[Basel2005]

Basel Elementary Graph Algorithms PART-1 p34.pdf

[Basel2005]

Adjacency Matrix

Assume V = {1, 2, …, n}
An adjacency matrix represents the graph as a n × n matrix A:
A[i, j] = 1 if edge(i, j) ∈ E (or weight of edge)
A[i, j] = 0 if edge(i, j) ? E

Adjacency matrix of an undirected graph is symmetric

Diagonal entries are zero

A(i, j) = A(j, i) for all i and j

Adjacency matrix of a digraph need not be symmetric

How much storage does the adjacency matrix require?
Answer: O(|V|2)
O(|V|) time to find vertex degree and/or vertices adjacent to a given vertex

The adjacency matrix is a dense representation
Usually too much storage for large graphs
But can be very efficient for small graphs
If graph is unweighted, there is an additional advantage in storage for the adjacency matrix presentation; rather than using one word of computer memory for each matrix entry, the adjacency matrix uses only one bit per entry.

[Basel2005]

Adjacency Lists

Most large interesting graphs are sparse For this reason the adjacency list is often a more appropriate representation

Each adjacency list is a chain.

# of chain nodes = 2|E| (undirected graph)
# of chain nodes = |E| (digraph)

How much storage is required?
The degree of a vertex v = # incident edges
Directed graphs have in-degree and out-degree
For directed graphs:
# of items in adjacency lists is Σ out-degree(v) = |E|
takes Θ(V + E) storage (Why?)
For undirected graphs:
# items in adjacency lists is Σ degree(v) = 2|E|
also Θ(V + E) storage
So: Adjacency lists take O(V + E) storage

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[Beard]

Beard Comparing object graph representation to adjacency list and matrix representations.docx

jbeard4

[Beard]

objects and pointers

Objects and pointers is mostly the same as adjacency list, at least for the purpose of comparing algorithms that use these representations.

Compare

struct Node {
    Node *neighbours[];
};

with

struct Node {
    Node *left;
    Node *right;
};

You can easily construct the list of neighbours on-the-fly in the latter case, if it is easier to work with than named pointers.

A matrix is just a simple 2 dimensional array. Assuming you have vertex ID's that can be represented as an int array like this:

int[][] adjacencyMatrix = new int[SIZE][SIZE]; // SIZE is the number of vertices in our graph
adjacencyMatrix[0][1] = 30; // sets the weight of a vertex 0 that is adjacent to vertex 1

This is commonly used for dense graphs where index access is necessary. You can represent a un/directed and weighted structure with this.

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[Benoit2005]

Benoit Representing trees of higher degree p12

D. Benoit, E. Demaine, I. Munro, R. Raman, V. Raman, and S. S. Rao. Representing trees of higher
degree. Algorithmica, 43(4):275{292, 2005.

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[Berkeley]

Berkeley — Graph representations.docx

[Berkeley]

adjacency list

The adjacency list representation for a directed graph with n vertices and e edges is an n-element array of linked lists; the list for the kth vertex vk contains all vertices w such that (vk, w) is an edge in the graph.

????????????????????????????????

BFS Scalable GPU graph traversal

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[Black2015]

Black graph

https://xlinux.nist.gov/dads/HTML/graph.html

https://xlinux.nist.gov/dads/HTML/adjacencyListRep.html

https://xlinux.nist.gov/dads/HTML/adjacencyMatrixRep.html

Paul E. Black

paul.black@nist.gov

[Black2015]

adjacency-list representation

(data structure)

Definition: A representation of a directed graph with n vertices using an array of n lists of vertices. List i contains vertex j if there is an edge from vertex i to vertex j. A weighted graph may be represented with a list of vertex/weight pairs. An undirected graph may be represented by having vertex j in the list for vertex i and vertex i in the list for vertex j.

Note: Suppose we have a directed graph with four vertices. Here are adjacency-matrix and adjacency-list representations. The arrow (->) means a link in a list.

    1 2 3 4
 1  1 1 1 1
 2  1 0 0 0
 3  0 1 0 1
 4  0 1 1 0

1 -> 1 -> 2 -> 3 -> 4
2 -> 1
3 -> 2 -> 4
4 -> 2 -> 3

One variant is to have an array of columns, rather than rows, with the list going "down". The adjacency-list representation is more compact for a sparse matrix.

[Black2015]

adjacency-matrix representation

(data structure)

Definition: A representation of a directed graph with n vertices using an n × n matrix, where the entry at (i,j) is 1 if there is an edge from vertex i to vertex j; otherwise the entry is 0. A weighted graph may be represented using the weight as the entry. An undirected graph may be represented using the same entry in both (i,j) and (j,i) or using an upper triangular matrix.

Aggregate parent (I am a part of or used in ...)
graph.

See also adjacency-list representation, dense graph.

Note: Suppose we have a directed graph with four vertices. Here are adjacency-matrix and adjacency-list representations. The arrow (->) means a link in a list.

    1 2 3 4
 1  1 1 1 1
 2  1 0 0 0
 3  0 1 0 1
 4  0 1 1 0

 1  -> 1 -> 2 -> 3 -> 4
 2  -> 1
 3  -> 2 -> 4
 4  -> 2 -> 3

The adjacency-list representation is more compact for a sparse matrix.

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[Blelloch2012]

Parallel and Sequential Data Structures and Algorithms — Lecture 7 15-210 (Spring 2012)

Blelloch Lecture 7 Graph Representations Sets and Tables p11

Guy E Blelloch

https://www.cs.cmu.edu/~guyb/

Blelloch@cs.cmu.edu

2017-08-31

Margaret Reid-Miller

https://www.cs.cmu.edu/~mrmiller/

Kanat Tangwongsan

http://www.philinelabs.net/~ktangwon/

How should we represent a graph?

[Blelloch2012]
Adjacency matrix

[Blelloch2012]
Adjacency list

An array A of length n where each entry A[i] contains a pointer to a linked list of all the out-neighbors of vertex i. In an undirected graph with edge {u, v} the edge will appear in the adjacency list for both u and v.

[Blelloch2012]
Adjacency array

Similar to an adjacency list, an adjacency array keeps the neighbors of all vertices, one after another, in an array adj; and separately, keeps an array of indices that tell us where in the adj array to look for the neighbors of each vertex.

[Blelloch2012]
Edge list

[Blelloch2012]

edge set representation

The representation is similar to an edge list representation mentioned before, but it abstracts away from the particular data structure used for the set—the set could be based on a list, an array, a tree, or a hash table.

If we use the balanced-tree cost model for sets, for example, then determining if an edge is in the graph requires much less work than with an edge list— only O(log n) instead of (n) (i.e. following the list until the edge is found). The problem with edge sets, as with edge lists, is that they do not allow for an efficient way to access the neighbors of a given vertex v. Selecting the neighbors requires considering all the edges and picking out the ones that have v as an endpoint. Although with an edge set (but not an edge list) this can be done in parallel with O(logm) span, it requires (m) work even if the vertex has only a few neighbors.

[Blelloch2012]

edge-set table / adjacency table

More efficient neighbor access. In our second representation, we aim to get more efficiency in accessing to the neighbors of a vertex. This representation, which we refer to as an adjacency table, is a table that maps every vertex to the set of its neighbors. Simply put, it is an edge-set table.

Therefore, in this representation, accessing the neighbors of a vertex v is cheap: it just requires a lookup in the table. Assuming the balanced-tree cost model for tables, this can be done in O(log n) work and span. Once the neighbor set has been pulled out, mapping a constant work function over the neighbors can be done in O(dG(v)) work and O(1) span. Looking up if an edge is in the graph requires the same work and span as with edge sets: O(log n). This is because we can first look up one side of the edge in the table and then the second side in the set that is returned. Note that an adjacency list is a special case of adjacency table where the table of vertices is represented as an array and the set of neighbors is represented as a list.

Blelloch Lecture 13 — Shortest Weighted Paths p8.pdf

2012

Guy Blelloch

adjacency set representation for unweighted graphs

associate a value with each out edge of a vertex

associate each vertex with a table that maps each out-neighbor to its value

It would have type:
(eVal vertexTable) vertexTable .
The graph above would then be represented as:
G = f0 7! f1 7! 0.7, 2 7! 1.5g , 1 7! f2 7! ??2.0g , 2 7! fgg .

Guy E. Blelloch. Vector models for data-parallel computing. MIT Press, Cambridge, MA, USA, August 1990.

????????????????????????????????

[bmckinn82011]

bmckinn8 Adjacency Matrix / Shortest Path

Posted 08 December 2011 - 07:45 PM

http://www.dreamincode.net/forums/topic/259118-adjacency-matrix-shortest-path/

Vertex

????????????????????????????????

Bockholt

https://xlinux.nist.gov/dads/HTML/adjacencyListRep.html

Bob Bockholt bbockholt@yahoo.com

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Bogner Feynman graph polynomials p35

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Bolboa

https://stackoverflow.com/questions/29464252/adjacency-matrix-in-python

Adjacency matrix in Python

????????????????????????????????

Boost Graph Library Adjacency List - develop

Boost Graph Library Adjacency Matrix - 1.51.0

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Brabec Procedural Code Representation in a Flow Graph p12.pdf

Michal Brabec

2015

????????????????????????????????

[Bradfield]

https://bradfieldcs.com/algos/graphs/representing-a-graph/

[Bradfield]

adjacency list

The adjacency list is really a mapping, so in this section we also consider two possible representations in Python of the adjacency list: one an object-oriented approach with a Python dict as its underlying data type, and one just using a plain dict directly.

Ultimately though, we see the adjacency list representation using a pure map type (such as a dict in Python) as the most intuitive and flexible.

In an adjacency list implementation we keep a master collection of all the vertices in the Graph object and then each vertex object in the graph maintains a list of the other vertices that it is connected to. In our implementation of the Vertex class we will use a dictionary rather than a list as our master collection, where the dictionary keys are the vertices, and the values are the weights. The diagram below shows an adjacency list representation of the example graph we have been discussing.

The advantage of the adjacency list implementation is that it allows us to compactly represent a sparse graph. The adjacency list also allows us to easily find all the links that are directly connected to a particular vertex.

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Braun FIRM A Graph-Based Intermediate Representation p8.pdf

Matthias Braun Sebastian Buchwald Andreas Zwinkau
Karlsruhe Institute of Technology (KIT)
{matthias.braun,buchwald,zwinkau}@kit.edu

?????????????????????????????

Brisaboa Compact Representation of Web Graphs with Extended Functionality p33
Nieves R. Brisaboa

[Brisaboa2007]

Brisaboa K2trees for Compact Web Graph Representation p10.pdf

4

Nieves R. Brisaboa

Nieves Rodríguez Brisaboa
Full Professor

Database Laboratory
University of A Coru?na
A Coru?na, Spain

http://lbd.udc.es/ShowResearcherInformation.do?lang=en_US&id=12

brisaboa@udc.es
brisaboa@udc.es

2017-07-16

Susana Ladra
Database Laboratory
University of A Coru?na
A Coru?na, Spain

http://lbd.udc.es/ShowResearcherInformation.do?lang=en_US&id=113

sladra@udc.es
sladra@udc.es

Gonzalo Navarro
Dept. of Computer Science
University of Chile
Santiago, Chile

https://www.dcc.uchile.cl/~gnavarro/

gnavarro@dcc.uchile.cl
gnavarro@dcc.uchile.cl

2017-07-17

WebGraph Framework, by Boldi and Vigna [6]. It is associated to the site http://webgraph.dsi.unimi.it

compressed graph representations

  • WebGraph compression method
  • Pair compression [18] on the adjacency lists

adjacency matrix of a Web graph

The adjacency matrix of a Web graph of n pages is a square matrix faijg of n ￡ n, where each row and each col- umn represents a Web page. Cell aij is 1 if there is a hy- perlink in page i towards page j, and 0 otherwise.

properties of the adjacency matrix

  • As on average there are about 15 links per Web page, this matrix is extremely sparse.
  • Due to locality of reference, many 1s are placed around the main diagonal (that is, page i has many pointers to pages nearby i).
  • Due to the copy prop- erty, similar rows are common in the matrix.
  • Finally, due to skewness of distribution, some rows and colums have many 1s, but most have very few.
  • regularity properties of the adjacency matrix of the Web graphs, such as
    • horizontal,
    • vertical, and
    • diagonal runs.

clustering of the adjacency matrix

compact tree representation of the matrix

  • compact representation of the adjacency matrix that exploits its sparseness and clustering properties.
  • The representation is designed to compress large matrix ar- eas with all 0s into very few bits.
  • the technique offers a relevant space/time tradeoff to represent Web graphs, that is, it is much faster than those that take less space, and much smaller than those that o?er faster navigation.
    Furthermore, we show that our representation allows for other queries on the graph not usually considered in com pressed graph representations.
  • very e±cient to represent large empty areas of the matrix,
  • but at the same time allows e±cient forward and backward navigation of the graph.
  • An elegant feature of our solution is that it is symmetric, in the sense that forward and backward navigation are carried out by similar means and achieve similar times.
  • We represent the whole adjacency matrix via the k2-tree using two bit arrays we call T (tree) and L (leaves):
    • T: This bit array stores all the bits of the k2-tree except those in the last level. The bits of the k2-tree are placed following a levelwise traversal of the tree. We will represent ˉrst the k2 binary values of the children of the root node, then the values of the second level, and so on.
    • L: This bit array stores the last level of the tree. Thus it represents the value of (some) original cells of the adjacency matrix.
  • We represent the adjacency matrix by a k2-ary tree, which we call k2-tree, of height h = dlogk ne. Each node contains a single bit of data: 1 for the internal nodes and 0 for the leaves, except for the last level of the tree, where all are leaves and represent some bit values of the matrix. corresponds to the root; its k2 children are represented at level 1. Each child is a node and therefore it has a value 0 or 1. All internal nodes in the tree (i.e., with value 1) have exactly k2 children, whereas leaves (with value 0 or at the last tree level) have no children.
  • Assume for simplicity that n is a power of k; we will soon remove this assumption.
  • Conceptually, we start dividing the adjacency matrix into k2 submatrices of the same size, that
    is, k rows and k columns of submatrices of size n2=k2.
  • Each of the resulting k2 submatrices will be a child of the root node and its value will be 1 i? in the cells of the submatrix there is at least one 1. A 0 child means that the submatrix has all 0s and therefore the tree decomposition ends there; thus 0s are leaves in our tree.
  • The children of a node are ordered in the tree starting with the submatrices in the ˉrst (top) row, from left to right, then the submatrices in the second row from left to right, and so on.
  • Once the level 1 of the tree, with the children of root, has been built, the method proceeds recursively for each child with value 1, until we reach submatrices full of 0s, or we reach the cells of the original adjacency matrix. In the last level of the tree, the bits of the nodes correspond
    to the matrix cell values.
  • Figure 1 illustrates a 22-tree for a 4 ￡ 4 matrix.
  • A larger k induces a shorter tree, with fewer levels, but with more children per internal node.
  • If n is not a power of k, we conceptually extend our matrix to the right and to the bottom with 0s, making it of width n0 = kdlogk ne. This does not cause a signiˉcant overhead as our technique is e±cient to handle large areas of 0s.
  • Figure 2 shows an example of the adjacency matrix of a Web graph (we use the ˉrst 11￡11 submatrix of graph CNR [6]), and how it is expanded to an n0 ￡ n0 matrix for n0 a power of k = 2 (at the left) and of k = 4 (at the right). The ˉgure also shows the trees corresponding to those k values. Notice that the last level of the tree represents cells in the original adjacency matrix, but most empty cells in the original adjacency matrix are not represented in this level because, where a large area with 0s is found, it is represented by a single 0 in a smaller level of the tree.

Navigating with a k2tree

To obtain the pages pointed by a speciˉc page p, that is, to ˉnd direct neighbors of page p, we need to ˉnd the 1s in row p of the matrix. We start at the root and travel down the tree, choosing exactly k children of each node. We start with an example and then generalize in the next section.

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Btechsmartclass Graph Representations.docx

Adjacency Matrix

Incidence Matrix

Adjacency List

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[Buesser2014]

Buesser New Adjacency List and Multiplicity

Beat Buesser

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Buriol Web Graph representation and compression.ppt

the Adjacency Lists

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Burkardt GRAPH_REPRESENTATION.docx

adjacency matrix;

incidence matrix


Untitled Document

Graph Representation
Literature Index

(2017-07-01 -- 2018-07-01)

????????????????????????????????

Cao Deep Neural Networks for Learning Graph Representations p8.pdf

[Cao2016]

PPMI matrix

the original PPMI matrix itself is an explicit representation matrix of the graph

pointwise mutual information (PMI) matrix

positive pointwise mutual information (PPMI) matrix

matrix R representing the vertices of graph G by capturing deep structural information.

co-occurrence matrix / collections of linear sequences / via DeepWalk

DeepWalk proposed by Perozzi et al. (2014) presented an idea to transform unweighted
graphs into collections of linear sequences by a uniform sampling method known as truncated random walk.

DeepWalk (Perozzi, Al-Rfou, and Skiena 2014) is a recently proposed method to learn representations of networks. It transforms a graph structure into linear sequences by truncated random walks and processes the sequences using skip-gram with hierarchical softmax.

In their approach, sampled vertex sequences characterize the connections between vertices in a graph. This step can be understood as a process for converting a general graph structure into a large collection of linear structures.

Next, they utilized the skip-gram model proposed by Mikolov et al. (2013) to learn low-dimensional representations for vertices from such linear structures. The learned vertex representations were shown to be effective across a few tasks, outperforming several previous approaches such as spectral clustering and modularity method (Tang and Liu 2009a; 2009b; 2011; Macskassy and Provost 2003).

DeepWalk yields a co-occurrence matrix based on the sampled linear sequences.

probabilistic co-occurrence matrix

In Section 3, we describe our random surfing model that directly construct a probabilistic co-occurrence matrix from a weighted graph, which avoids the expensive sampling process.

random surfing model suitable for weighted graphs, which can directly yield a probabilistic
co-occurrence matrix. Such a matrix is similar to the cooccurrence matrix obtained by sampling linear sequences from graphs (Bullinaria and Levy 2007), but no sampling process is required in our approach.

linear sequences

Although effective, the sampling method for transforming a graph structure into linear sequences has some weaknesses.

vector representation / vertex representations of a unweighted graph

a model for learning graph representations, which generates a low-dimensional vector representation for each vertex by capturing the graph structural information.

One of effective means towards organizing such information associated with the potentially large and complex graph is to learn the graph representations, which assign to each vertex of the graph a low-dimensional dense vector representation, encoding meaningful information conveyed by the graph.

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Catherine Clustering the Graph Representation of Data p26

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[Chen2012]

Chen Analysis of Algorithms I: Graph Representation and BFS p41
Xi Chen

adjacency matrix

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 1 Matrix: (n) (to go through a binary string of length n)

But the matrix representation of course has its own advantage: To decide if (u; v) 2 E, it only uses O(1) time

If the algorithm uses a lot of random access of edges in G, then the matrix representation may perform better.

adjacency-list

Given a vertex u 2 V, the enumeration of edges incident on (or from) u (or equivalently, the enumeration of all vertices v with (u; v) 2 E) takes time 2 List: linear in the length of Adj(u) (or equivalently, deg(u) if G is undirected, and out-deg(u) if G is directed)

To decide if (u; v) 2 E, the list representation has worst-case running time linear in the length of Adj(u) (why?).

If the input graphs are sparse and we make a lot of enumerations of edges incident to a vertex in our algorithm, then the list representation usually ts better.

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Chen EAGER Define and Construct an Enhanced Graph Representation for Multiscale Vector Field Data Summarization.docx

????????????????????????????????

[Chhabra2017]

Sahil Chhabra

Chhabra Graph implementation using STL for competitive programming | Set 2 (Weighted graph)

http://www.geeksforgeeks.org/graph-implementation-using-stl-for-competitive-programming-set-2-weighted-graph/

http://www.practice.geeksforgeeks.org/user-profile.php?user=sahil_coder

????????????????????????????????

https://www.reddit.com/r/Python/comments/5zio67/is_there_a_python_library_to_represent_a_graph/

????????????????????????????????

[Chu-Carroll 2007]

Chu-Carroll Representing Graphs Posted

http://scienceblogs.com/goodmath/2007/08/15/post-5/

Mark C. Chu-Carroll

August 15, 2007

[Chu-Carroll 2007]

When you’re writing a graph-based algorithm, choosing which representation – and which variation of which representation – is one of your most important decisions. There’s no cut and dried correct answer: which representation is right is dependent on

  • what you want to do, and
  • what constraints you have.
  • How fast you need things to be;
  • how much memory you can afford to use;
  • how big your graph is; how many edges you graph will have –

all contribute to the choice of the best representation.

[Chu-Carroll 2007]

boolean adjacency matrix

The boolean adjacency matrix is very compact – you can get away with as little as N2/2 bits of storage to represent the edges in a graph.

Certain algorithms – like transitive closure – are extremely efficient in the adjacency matrix.

If you really only need to know the structure of the edges, and you don’t have other data that needs to be
associated with the edges, then an adjacency matrix can be an extremely good choice. If your matrix is moderately sized, you can often get the entire adjacency matrix into the cache at once, which has a dramatic impact on performance.

Even if you need to associate a little bit of information with an edge, that’s often easily doable using an adjacency matrix. For example, to represent a weighted graph, you can use the edge-weight as the value of the matrix entry if there is an edge. (This does require that you be able to identify a value which will absolutely never be an edge weight, to use to mark cells that are not edges. If you’re using floating point numbers for weight, then NaN is a good choice.)

On the other hand, if you have a very large matrix with very few edges, then an adjacency matrix will perform very poorly and waste an enormous amount of space. Consider a graph with 1 million vertices, and 1 million edges. That means that each vertex has, on average, two edges – but you’re using one million bits per vertex. That’s very wasteful, and dealing with a matrix of 1012 bits is not going to be particularly fast.

But if you want to know something about connectivity, or simple pathfinding in a relatively dense graph, then the adjacency matrix is usually the right choice.

I first saw the matrix representation of a graph when dealing with relations in a discrete math course.

We used them to decide certain properties, like whether a relation was reflexive, transitive and so on. Great stuff.

Adjacency matrices are also useful when doing ‘relaxation’ of edges, such as Dijkstra’s – you start with a weighted adjacency matrix, and end up with a matrix of distances from any node to any other.

[Chu-Carroll 2007]

adjacency list

A common optimization of the adjacency list is to use a data object to represent a vertex, and to use
pointers/references to vertex objects as the vertex identifiers in the adjacency list for a vertex. Depending
on the application, the adjacency lists could be either arrays, linked lists, or some other similar structure.

Using an adjacency list works much better if you have a sparse matrix – it only uses space for edges that are actually present in the graph.

It’s also often easier to associate data with vertices and edges in a good way using adjacency lists;

and it can often produce better performance in that case as well, due to good locality. (When you traverse an edge in an adjacency list using the pointer implementation described above, you’re pulling the vertex into your cache; then when you go to look at the data for the vertex, it’s hot in the cache. In an adjacency matrix, you’d use a separate table for that, which would mean fetching from a different area of memory.)

The adjacency list is often better for certain kinds of graph traversals:

if you need to walk through a graph collecting information about visited vertices, the locality properties of the adjacency list structure can have a great effect on performance.

Adjacency list implemented as pointers/references is of course a quite natural way to represent a graph, especially if you’re not interested in easily iterating through the edges. But this doesn’t work really well with functional programming, since there are no mutable references. One would somehow have to create the whole graph at once. Is something like that even possible in some functional language? What about cyclic data structures in FP in general? (Of course quick googling sorted much of this. But I’m posting anyways.;) )

Philip Sternberg August 15, 2007 A little note on the adjacency list implementation in python: for many applications, you might be better off using a set rather than a list as the member object that stores neighbors, giving O(1) lookup time.

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[Claude2007]

Claude A Fast and Compact Web Graph Representation p12
Francisco Claude

incidence matrix

Standard graph representations such as the incidence matrix require n(n? 1)/2 bits, for undirected graphs. For directed graphs the numbers are n2 .

adjacency lists

Re-Pair [19] to compress the adjacency lists

Standard graph representations such as the adjacency list require 2e log n bits, for undirected graphs. For directed graphs the numbers are e log n.

????????????????????????????????

CLAUDE Fast and Compact Web Graph Representations p30
FRANCISCO CLAUDE

????????????????????????????????

[Codish2013]

Codish Breaking Symmetries in Graph Representation p7.pdf

Michael Codish
Dept. of Computer Science
Ben-Gurion Univ. of the Negev
Beer-Sheva, Israel

https://www.cs.bgu.ac.il/~mcodish/

mcodish@cs.bgu.ac.il

2017-08-16

Alice Miller and Patrick Prosser
School of Computing Science
University of Glasgow
Scotland

Peter J. Stuckey
Dept. of Comp. Sci. and SE
and NICTA Victoria Laboratory
University of Melbourne, Australia

The canonical graph representation problem

The canonical graph representation problem is pertinent to a wide range of scientific applications. It is closely related to the graph isomorphism problem, as two graphs are isomorphic if and only if they have the same canonical representation.

adjacency matrix

canonical adjacency matrix

Boolean adjacency matrix

????????????????????????????????

[COMPSCI 230]

COMPSCI Part 1 Graphs and Adjacency Matrices

https://www.cs.duke.edu/courses/spring17/compsci230

https://www.cs.duke.edu/courses/spring17/compsci230/homework/08/assignment.pdf

????????????????????????????????

[Cormen2014]

Cormen Representing graphs.docx

Dartmouth Computer Science professors Thomas Cormen and Devin Balkcom

Thomas Cormen

http://www.cs.dartmouth.edu/~thc/

thc@cs.dartmouth.edu

2017-08-18

Devin Balkcom

http://www.cs.dartmouth.edu/~devin/

devin.balkcom@dartmouth.edu

Edge lists

For finding the neighbours of vertex v:
Edge List: O(|E|)
If the list is unsorted you need to check every edge to see if it comes from v
For a complete graph (where every vertex is connected to all other vertices) this would be O(|V|^2)

How can you organize an edge list to make searching for a particular edge take O(lgE) time? The answer is a little tricky.

Sort the list by the 1st vertex in each edge, and then by 2nd vertex in each edge.
The list is sorted, so we can now use a binary search on it.
Our comparison is a little bit more complicated now.
[v1,v2] < [v3,v4] if (v1 < v3) OR ( (v1 === v3) AND v2 < v4 )

If we have an edge [v1,v2] we do a binary search for [v1,v2] on the list. Time O(log E)

If your edges are not directed i.e. [v1,v2] is equivalent to [v2,v1] then perform a second search on the equivalent edge [v2,v1] if your first search wasn't successful. Double O(log E) is still O(log E).

Adjacency lists

Representing a graph with adjacency lists combines adjacency matrices with edge lists

It is true that in the general case that storage of an adjacency list is O(|V|+|E|).
This is the same as O( max( |V|, |E| ) )
Which means that you at least need to allocate space for the pointer to each vertices list.
In most practical cases |E| will larger than |V| (even for a minimally connected graph i.e. a tree, E = V-1). Which means for most practical cases the space required is simply O(|E|).

We can get to each vertex's adjacency list in constant time, because we just have to index into an array. To find out whether an edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis is present in the graph, we go to i i ii 's adjacency list in constant time and then look for j j jj in i i ii 's adjacency list. How long does that take in the worst case? The answer is Θ(d) \Theta(d) Θ(d) , where d d dd is the degree of vertex i i ii , because that's how long i i ii 's adjacency list is. The degree of vertex i i ii could be as high as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 (if i i ii is adjacent to all the other ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices) or as low as 0 (if i i ii is isolated, with no incident edges). In an undirected graph, vertex j j jj is in vertex i i ii 's adjacency list if and only if i i ii is in j j jj 's adjacency list. If the graph is weighted, then each item in each adjacency list is either a two-item array or an object, giving the vertex number and the edge weight.

How much space do adjacency lists take? We have ∣V∣ |V| ∣V∣vertical bar, V, vertical bar lists, and although each list could have as many as ∣V∣?1 |V|-1 ∣V∣?1vertical bar, V, vertical bar, minus, 1 vertices, in total the adjacency lists for an undirected graph contain 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar elements. Why 2∣E∣ 2|E| 2∣E∣2, vertical bar, E, vertical bar ? Each edge (i,j) (i,j) (i,j)left parenthesis, i, comma, j, right parenthesis appears exactly twice in the adjacency lists, once in i i ii 's list and once in j j jj 's list, and there are ∣E∣ |E| ∣E∣vertical bar, E, vertical bar edges. For a directed graph, the adjacency lists contain a total of ∣E∣ |E| ∣E∣vertical bar, E, vertical bar elements, one element per directed edge.

Agreed, if the list of neighbors is implemented as an array, and that array is sorted then determining membership is Θ(log(d)), using binary search.

However, if the array is unsorted, or if the list of neighbors is implemented as a linked list (both are typical implementations) then determining membership is Θ(d), as we need to look at every item in the list before deciding that something is not in the list.

In the article they mention "Vertex numbers in an adjacency list are not required to appear in any particular order", which implies the analysis is with regards to unsorted implementations.

Whether you would want to use a sorted version or not would depend on your application. You might get the sorting for free (i.e. if your method of constructing your graph leads to naturally sorted adjacency lists), or you might have to pay an additional cost in sorting the adjacency lists. Whether the cost outweighs the benefits depends on your application.

For finding the neighbours of vertex v:

Adjacency List: O(|N|)
where N is the number of neighbours of v
You need to iterate through the list for the vertex v, which has N neighbours
v could have up to V-1 neighbours, so we could also say it is O(|V|)

how is adjacency list space Θ(V + E)?

The adjacency list contains:
-1 array per vertex, for a total of V arrays (we are only considering the space for the array pointer, not the contents of the array).
-Each directed edge is contained once somewhere in the adjacency list, for a total of E edges (a bidirectional edge is just 2 directed edges, so if we are using bidirectional edges it would just be 2E ).

V+E is Θ(V + E)

Adjacency matrices

For finding the neighbours of vertex v:

Adjacency Matrix: O(|V|)
You need to check the the row for v, (which has |V| columns) to find which ones are neighbours

If you represent your adjacency matrix as a hash table, you can get very good lookup times without using n^2 memory.

????????????????????????????????

Corn

https://brilliant.org/wiki/adjacency-matrix/

????????????????????????????????

[Cornell2011]

Cornell Lecture 21 Graph Representations and Traversals.docx

adjacency list

Directed graphs are commonly represented as an adjacency list, which comprises an array or list of vertices, where each vertex vi stores a list of all the vertices vj for which there is an edge (vi, vj) ∈ E.

In practice, many graphs are sparse in the sense that most of the possible edges between pairs of vertices do not exist, i.e. m << n2. In such cases the adjacency list is generally preferable to the adjacency matrix representation.

In that implementation, a graph is represented as a pair consisting of the number of vertices and a list of vertices. A vertex is represented as a triple of a unique integer id, an outgoing list, and an incoming list. The outgoing list is a list of pairs of destination vertex and weight. The incoming vertex list is a list of pairs of source vertex and weight. Note that as each edge is stored twice, in the incoming list of its destination and the outgoing list of its source, the weight must be consistent in the two lists.

In that implementation, an edge is a triple of a source vertex, destination vertex and weight, and is constructed on the fly as needed from the vertex out lists rather than being explicitly stored in the data structure.

adjacency matrix

Another common representation is an adjacency matrix, which is a two-dimensional array, where Ai j is non-zero when there is an edge (vi, vj) ∈ E.

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[Costantini2001] Comparing different graph representations of logic programs under the Answer Set semantics p6
Stefania Costantini
Dept. of Pure and Applied Maths.
Univ. of L’Aquila
via Vetoio, Loc. Coppito, I-67100 L’Aquila, Italy
stefcost@univaq.it

http://www.di.univaq.it/stefcost/

Stefania.Costantini@univaq.it

????????????????????????????????

CPLEX LP format

????????????????????????????????

Curtis An Implicit Representation of Chordal Comparabilty Graphs in Linear-time p14


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Daal

https://www.codementor.io/rishabhdaal/graph-algorithms-interview-questions-du1085u8l

Rishabh Daal

Teaching Assistant, Former SDE Intern at Amazon

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D'Autilia Shaping ideal cities the graph representation of the urban utopia p17.pdf

????????????????????????????????

de Greef Lecture 15 - Graph Data Structures and Traversals p37

Lilian de Greef

Adjacency Matrix Properties
? Running time to:
? Get a vertex’s out-edges:
? Get a vertex’s in-edges:
? Decide if some edge exists:
? Insert an edge:
? Delete an edge:
? Space requirements:
? Best for sparse or dense graphs?

????????????????????????????????

[Deepa2014]

Deepa Data Structure for Graphs p4

[Deepa2014]

Adjacency Lists in Lists

We can more efficiently represent sparse graphs by using linked lists to store the neighbors adjacent to each vertex. Adjacency lists require pointers but are not frightening once you have experience with linked structures.
Adjacency lists make it harder to ask whether a given edge (i, j) is in G, since we have to search through the appropriate list to find the edge. However, it is often surprisingly easy to design graph algorithms which avoid any need for such queries. Typically, we sweep through all the edges of the graph in one pass via a breadth-first or depths-first traversal, and update the implications of the current edge as we visit it.

[Deepa2014]

Adjacency Lists in Matrices

Adjacency lists can also embedded in matrices, thus eliminating the need for pointers. We can represent a list in an array (or equivalently, a row of a matrix) by keeping a count k of how many elements there are, and packing them into the first k elements of the array. Now we can visit successive the elements from the first to last just like a list, but by incrementing an index in a loop instead of cruising through pointers.

As stated above, we will use adjacency lists in matrices as our basic data structure to represent graphs. It is not complicated to convert these routines to honest pointer based adjacency lists.

[Deepa2014]

Table of Edges

An even simpler data structure is just to maintain an array or linked list of the edges. This is not as flexible as the other data structures at answering “who is adjacent to vertex x?” but it works just fine for certain simple procedures like Kruskal’s minimum spanning tree algorithm.

????????????????????????????????

[Depree2013]
Depree Graph Operations And Representation p34

Adjacency Matrix

O(n) time to find vertex degree and/or vertices adjacent to a given vertex.

Cost adjacency matrix. C(i,j) = cost of edge (i,j)

Adjacency Lists

    Linked Adjacency Lists

    Each adjacency list is a chain.

    Array Length = n
    # of chain nodes = 2e (undirected graph)
    # of chain nodes = e (digraph)

    Array Adjacency Lists

    Each adjacency list is an array list.

    Array Length = n
    # of list elements = 2e (undirected graph)
    # of list elements = e (digraph)

    Adjacency lists => each list element is a pair (adjacent vertex, edge weight)

????????????????????????????????

[Dezso2010]

Dezso LEMON – an Open Source C++ Graph Template Library1

[Dezso2010]

doubly-linked adjacency list

The example in Figure 1 uses ListDigraph, which is a doubly-linked adjacency list based directed graph implementation.

BGL implements a single adjacency list based graph class, but it can be customized with template parameters that specify the internal storage structures for nodes and arcs.

simply-linked lists

Another important digraph structure is SmartDigraph, which stores the nodes and arcs continuously in vectors and uses simply-linked lists for keeping track of the incident arcs of each node. Therefore, it has smaller memory footprint and it can be considerably faster, at the cost that nodes and arcs cannot be removed from it.

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Dong Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance p67

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[Douence2009]

Douence Lazy Composition of Representations in Java

G:\studies\000Webit\000programming\Java

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Drozdek Data Structure And Algorithms In C++ p664

G:\studies\000Webit\000programming\ccpp

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[Du2007]

Du Lecture 3 Graph Representation for Regular Expressions p26

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Dvorak A dynamic data structure for counting subgraphs in sparse graphs p27
Zdenˇek Dvorak Vojtˇech T°uma?


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August 25, 2014

Form the adjacency matrix and adjacency lists from the edges

ED

https://algocoding.wordpress.com/2014/08/25/form-the-adjacency-matrix-and-adjacency-lists-from-the-edges/

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[2012Ediger]

Ediger STINGER: High Performance Data Structure for Streaming Graphs p5

David Ediger Rob McColl Jason Riedy David A. Bader

2

http://www.cc.gatech.edu/stinger

STINGER is a scalable, high performance graph data structure

STINGER (Spatio-Temporal Interaction Networks and Graphs Extensible Representation) is a community developed, high performance, extensible data structure for dynamic graph problems [6].

STINGER [6] is a dynamic graph data structure that exposes large amounts of parallelism, supports fast
updates, and is well-suited to scale-free graphs.

[6] D. A. Bader, J. Berry, A. Amos-Binks, D. Chavarría-Miranda, C. Hastings, K. Madduri, and S. C. Poulos, “STINGER: Spatio-Temporal Interaction Networks and Graphs (STING) Extensible Representation,” Georgia Institute of Technology, Tech. Rep., 2009.

STINGER, the data structure for streaming graphs.

The data structure is based on linked lists of blocks.

The number of vertices and edges can grow over time by adding additional vertex and edge blocks.

Both vertices and edges have types.

A vertex can have edges of multiple types.

Edges incident on a given vertex are stored in a linked list of edge blocks. An edge is represented as a tuple of neighbor vertex ID, integer weight, first timestamp, and
modified timestamp.

All edges in a given block have the same edge type.

The block contains metadata such as the lowest and highest timestamps and the high-water mark of edges within the block.

Parallelism exists at many levels of the data structure.

Each vertex has its own linked list of edge blocks that is accessed from the logical vertex array (LVA). A “for all vertices” loop is parallelized over these lists. Within an edge block, the incident edges can be explored in a parallel loop. The size of the edge block, and therefore the quantity of parallel work to be done, is a user defined parameter. In our experiments, 32 edges in a block is a good selection.

The edge type array (ETA) is a secondary index that points to all edge blocks of a given type. In an algorithm such as connected components, which is edge parallel, this additional mode of access into the data structure permits all edge blocks to be explored in a parallel for loop.

???????????????????????????

[Egyhazy1983]

Egyhazy On implementing graph representation p23

Csaba Egyhazy

4

one way adjacency lists

each node consists of two fields, INFO and LINK, the INFO field contains the itentifier of the next vertex that is also adjacent to vertex vi.

adjacency multilist representation

[Elite2010]

Elite Graph Representation p27

Adjacency matrix

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[Ellis-Monaghan2007]

Ellis-Monaghan Graph Polynomials and Their Applications I The Tutte Polynomial p42

Joanna A. Ellis-Monaghan

Criel Merino

2

A graph polynomial is a graph invariant where the image lies in some polynomial ring.

????????????????????????????????

[Emms2006]

Emms A matrix representation of graphs and its spectrum as a graph invariant p14

4

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David Emms
Department of Computer Science
University of York, York YO10 5DD, U.K.
demms@cs.york.ac.uk

Edwin R. Hancock
Department of Computer Science
University of York, York YO10 5DD, U.K.
erh@cs.york.ac.uk

erh@cs.york.ac.uk

2017-08-19

Simone Severini
Department of Mathematics and Department of Computer Science
University of York, York YO10 5DD, U.K.
ss54@york.ac.uk

https://www.ucl.ac.uk/~ucapsse/

s.severini@ucl.ac.uk

2017-08-20

Richard C. Wilson
Department of Computer Science
University of York, York YO10 5DD, U.K.
richard.wilson@cs.york.ac.uk
Submitted: Nov 16, 2005; Accepted: Mar 16, 2006; Published: Apr 4, 2006
2000 Mathematics Subject Classi cation: 05E30, 05C60

the electronic journal of combinatorics 13 (2006), #R34

adjacency matrix

Laplacian matrix

Representing graphs with orthogonal matrices

????????????????????????????????

ERDOS THE REPRESENTATION OF A GRAPH BY SET INTERSECTIONS p7

????????????????????????????????

Erwig FGL/Haskell - A Functional Graph Library for Haskell

https://hackage.haskell.org/package/fgl

http://hackage.haskell.org/cgi-bin/hackage-scripts/package/fgl

http://darcs.haskell.org/packages/fgl/

http://web.engr.oregonstate.edu/~erwig/fgl/haskell

https://github.com/haskell/fgl.git

Wed Aug 9 13:06:50 UTC 2017

Author | Martin Erwig, Ivan Lazar Miljenovic
Maintainer | Ivan.Miljenovic@gmail.com


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Figueroa Tracking soccer players using the graph representation p4
Pascual Figueroa

????????????????????????????????

Fundamental Data Structures p376

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Gaillarda Graph representation of synonymy and translation resources for cross-linguistic modelisation of meaning p12

Gaillarda Graph representation of synonymy and translation resources for cross-linguistic modelisation of meaning p12

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Gansner GMap Visualizing Graphs and Clusters as Maps p8

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[García2014]

García Compact and Efficient Representations of Graphs p301

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Gavoille Shorter Implicit Representation for Planar Graphs and Bounded Treewidth Graphs p12

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geeksforgeeks Graph and its representations

http://www.geeksforgeeks.org/graph-and-its-representations/

http://www.geeksforgeeks.org/graph-data-structure-and-algorithms/

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http://www.geoffwyatt.com/

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Gkirtzou The Pyramid Quantized Weisfeiler-Lehman Graph Representation p17

????????????????????????????????

https://www.topcoder.com/community/data-science/data-science-tutorials/introduction-to-graphs-and-their-data-structures-section-1/

????????????????????????

C. Godsil and G. Royle, Algebraic Graph Theory, Graduate Texts in Mathematics,
207, Springer-Verlag, New York, 2001.

Goodrich Data Structures and Algorithms Introducing Graphs p9

????????????????????????????????

Goodrich Data Structures and Algorithms in C++ p738

G:\studies\000Webit\000programming\ccpp

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Gotshalks Graph Representation p12

[Gotshalks2008]

Gunnar Gotshalks

http://www.cse.yorku.ca/~gunnar/

gunnar@cse.yorku.ca

2017-08-22

adjacency matrix

In general the matrix entries can be any data representing the edge
? True / False are the minimum – an edge exists / ~exists
? Integer – 0 / 1 for False / True
? Number of parallel edges
? Airline flight number
? Time to do task (vertices represent checkpoints)
? Maximum rate of oil flow in a pipeline

incidence matrix

adjacency list

? Each vertex in an adjacency list points to its entry in the list of all vertices
? Each vertex in an adjacency list can also point to edge data

edge list

????????????????????????????????

[Grama2003]

Grama Graph Algorithms p65.pdf

Ananth Grama

https://www.cs.purdue.edu/people/faculty/ayg/

https://www.cs.purdue.edu/homes/ayg/

ayg@cs.purdue.edu

Graphs can be represented by their adjacency matrix or an edge (or vertex) list.

Adjacency matrices

Adjacency matrices have a value ai;j = 1 if nodes i and j share an edge; 0 otherwise. In case of a weighted graph, ai;j = wi;j, the weight of the edge.

adjacency list

The adjacency list representation of a graph G = (V;E) consists of an array Adj[1::jV j] of lists. Each list Adj[v] is a list of all vertices adjacent to v.

edge list

vertex list

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GRAPH FILE FORMATS.pdf

M Bernard

????????????????????????????????

Graph Representation.pdf

adjacency list and the adjacency matrix

????????????????????????????????

Graph Representation1.pdf

????????????????????????????????

graphviz

http://www.graphviz.org/content/datastruct

????????????????????????????????

[Gross2003]

Gross Section 8.3 Graph Representations and Graph Isomorphism p11

Jonathan L. Gross

http://www.cs.columbia.edu/~gross/

retired

https://www.cs.columbia.edu/2016/jonathan-gross-retires/

gross@cs.columbia.edu

2017-08-23

ADJACENCY MATRIX REPRESENTATION

INCIDENCE MATRIX REPRESENTATION

ADJACENCY LIST REPRESENTATION

def: An adjacency list for a vertex v of a graph G is a list containing each vertex w of G
once for each edge between v and w.
def: An adjacency list representation of a graph is a table of all the adjacency lists.

INCIDENCE TABLE REPRESENTATION

An incidence table for a graph has a column indexed by each edge. The entries in the column for an edge are its endpoints. If the edge is a self-loop, then the endpoint appears twice.

????????????????????????????????

Shubham Gupta

http://www.geeksforgeeks.org/graph-implementation-using-stl-for-competitive-programming-set-1-dfs-of-unweighted-and-undirected/

????????????????????????????????

[Guttag2013]

000Guttag Introduction to Computation and Programming using Python (rev. ed.) [Guttag 2013-08-09]

G:\studies\000Webit\000programming\Python

adjacency matrix

One common representation is an n × n adjacency matrix, where n is the number of nodes in the graph. Each cell of the matrix contains information (e.g., weights) about the edges connecting the pair of nodes <i, j>. If the edges are unweighted, each entry is True if and only if there is an edge from i to j.

[Guttag2013]

adjacency list

Another common representation is an adjacency list, which we use here. Class Digraph has two instance variables. The variable nodes is a Python list containing the names of the nodes in the Digraph. The connectivity of the nodes is represented using an adjacency list implemented as a dictionary. The variable
edges is a dictionary that maps each Node in the Digraph to a list of the children of that Node.


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https://www.hackerearth.com/practice/algorithms/graphs/graph-representation/tutorial/

Hackerearth Graph Representation.docx

Adjacency Matrix

Adjacency Lists

??????????????????????????????

Hagberg NetworkX Reference p645

Aric Hagberg, Dan Schult, Pieter Swart

????????????????????????????????

Pawan Harish and P. J. Narayanan. Accelerating large graph algorithms on the GPU using CUDA. In Proceedings of the 14th International Conference on High Performance Computing, HiPC'07, pages 197{208, Berlin, Heidelberg, December 2007. Springer-Verlag.

????????????????????????????????

Hayden

http://www.koderdojo.com/blog/depth-first-search-in-python-recursive-and-non-recursive-programming

Heap Graph representation .docx

Adjacency list

Adjacency matrix

Hedstrom Graph representation.docx

????????????????????????????

Heissan Some Results on Graph Representations and Graph Colorings p60

adjacency lists

incidence lists

adjacency matrices

incidence matrices.

???????????????????????????????

Hernandez Compressed Representation of Web and Social Networks via Dense Subgraphs p12
Cecilia Hernandez

????????????????????????????????

Hietaniemi Graph-0.9704

Jarkko Hietaniemi / Graph-0.9704

jhi@iki.fi

https://metacpan.org/release/Graph

Perl module Graph

????????????????????????????????

K Hong

Graph Data Structure

http://www.bogotobogo.com/python/python_graph_data_structures.php

[Huan2005]

HUAN Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based Packing Motifs p15
JUN HUAN

Huan Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based acking Motifs p12
Jun Huan

Canonical adjacency matrix

Canonical adjacency matrix of labeled graphs
We represent each graph by an adjacency matrix M such that every diagonal entry of M is filled with the
label of the corresponding node and every off-diagonal entry is filled with the label of the corresponding
edge, or zero if there is no edge. This is slightly different from the standard adjacency matrix representation for unlabeled graphs (Cormen et al., 2001).

????????????????????????????????

Hugue Lecture 22 Graphs Representations and BFS

www.cs.umd.edu/~meesh/351/mount/lectures/lect22-graphs-represent-BFS.pdf

Michelle M. Hugue, Ph.D.


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[Iglesias2011]

Iglesias Graph representation of documents content and its suitability for text mining tasks p72


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[Jampani2011]

Jampani Simultaneous Graph Representation Problems p94
by
Krishnam Raju Jampani

Yuntao Jia, Victor Lu, Jared Hoberock, Michael Garland, and John C. Hart. Edge v. node parallelism for graph centrality metrics. In Wen-mei W. Hwu, editor, GPU Computing Gems Jade Edition, chapter 2, pages 15{28. Morgan Kaufmann, October 2011.

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[Joy1987]
The "Printable" Format for Describing a Graph
The structure for the textual representation of a graph is a sequence of lines, each representing a separate node in the graph, of the form:
address type usage_count annotation "name" [other fields]
where the fields are separated by blanks or tabs. The field address is an unsigned integer representing the storage location of the node. The field type is an unsigned integer representing the type of the node (integer, real, application, etc.). The field usage_count is an unsigned integer used for garbage collection purposes (reference counts, etc.), and represents the number of strong pointers to that node in the graph. The field annotation is an integer currently not assigned, but may be used in the future by particular implementations. The meaning of a program should be unchanged if all the annotations are ignored. The "name" field is a character string naming the node, usually null.

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[Joyner]

Joyner Python and Coding Theory p115

000Joyner Python and Coding Theory p115

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[Kannan1989]

Kannan Implicit Representation of Graphs p11
Sampath Kannan

Sampath Kannan
Computer Science Department
University of Arizona

Moni Naor
IBM Research Division
Almaden Research center

Steven Rudich
Computer Science Department
Carnegie-Mellon University

How to represent a graph in memory is a fundamental data structuring question.

[Kapanowski2015]

Kapanowski Weighted Graph Algorithms with Python p13

Kapanowski Weighted graph algorithms with Python p26

[Kehr2014]

Kehr Genome alignment with graph data structures: a comparison

2014 Apr 9

Birte Kehr,corresponding author1,2 Kathrin Trappe,1 Manuel Holtgrewe,1 and Knut Reinert1

https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4020321/

????????????????????????????????

[Kempe2016]

G:\studies\000Webit\000programming\ccpp

000Kempe Class Notes for CSCI 104 Data Structures and Object-Oriented Design p244

[Kempe2016]

adjacency lists

1. Via adjacency lists: for each node, store a list of all other nodes it is adjacent to. (This could be using
the ADT Set, the ADT List, a Linked List, or a dynamically growing array.) If the graph is directed, we would store two separate lists: one for outgoing edges and another for incoming ones. The elements of the list would be either pointers to the other nodes, or — if nodes themselves are stored in an array — integers, i.e., the indices in the array where the other node is stored.

For an adjacency list, we don’t have that information readily available. Instead, we need to go through
the list of all outgoing edges of u, and see if v is in that list. That will take (outdegree(u)), which can be much larger. (As we learn about better implementations of sets later, this becomes faster, but even then, the time will not go down to constant.)

3. Listing all outgoing/incoming edges of u is the specialty of adjacency lists. Since they explicitly store
this information, they just have to go through their Set/List, which takes time (outdegree(u)) or
(indegree(u)).

For adjacency lists, we store all incoming and all outgoing edges, which gives us a total memory
requirement of ( P v(indegree(v)+outdegree(v))). To evaluate this sum, notice that when we sum all
in-degrees, we count each edge exactly once, since it contributes 1 to the indegree of exactly one node.
So the sum of all indegrees is m, and similarly for the sum of all outdegrees. Thus, the sum above is equal to 2m, which is (m). Thus, the total storage requirement is (n + m) (since we also need to store information for all nodes).

[Kempe2016]

adjacency matrix

2. Via an adjacency matrix: Store an n × n matrix (two-dimensional array) A. In position A[u, v], store
whether there is an edge from u to v. (This could be a boolean value, or perhaps an integer storing the length, cost, or other information.)

What we store in position A[u, u] depends on what our graph is modeling. In some cases, it makes sense to treat it as though there were an edge from u to itself, in other cases not so much. There is no rule that forces us to choose one or the other, and we should use whatever makes our computational task easiest.

1. For adding or removing nodes, an adjacency matrix has a bit more overhead, since changing the size of a matrix involves a bunch of reallocation and copying. For many applications that a computer scientist
is called upon to solve, changes in the set of nodes tend to be a bit rarer while other processing is
happening.

2. Testing whether the edge (u, v) exists in the graph is the specialty of adjacency matrices. It only involves one lookup in a known position of a 2-dimensional array, and thus takes O(1) time.

For an adjacency matrix, we don’t have this information stored, so we have to loop through the entire
row (or column) of the node u, and find all the entires that are 1 or true. This will take (n), which
can be much worse if the degrees are pretty small.

For the adjacency matrix, we need to store an n × n array, which obviously requires (n2) memory.

[Kempe2016]

comparing

In comparing the two approaches, we should always take into account which operations we expect to
be performed more frequently. Let us compare which operations are more or less expensive in the two
implementations.

4. We can also compare the memory requirements of the two implementations.

Thus, for sparse graphs, adjacency list are much more economical with space than adjacency matrices,
whereas for dense graphs, it doesn’t really matter too much in terms of memory.

We saw above that each way of storing a graph has its own advantages and disadvantages.

If memory isn’t too big of a concern (it rarely is — computation time is the bottleneck much more often than memory nowadays), one possible approach is to store the entire graph twice internally. When a user queries whether an edge (u, v) exists, we answer it by using the adjacency matrix, while when the user queries all neighbors of a node u, we use adjacency lists.

The downside of this approach (besides using twice as much memory) is that it requires us to execute
each update to the graph twice: once on the adjacency matrix and once on the list. Thus, update operations (such as adding or removing nodes or edges) will take twice as long as before. However, this may well be worth it: for many graphs, updates are much less frequent than queries. For instance, when building a GPS, it is much rarer to have roads or intersections added to a road network than to look for routes between two locations. Similarly, in a social network, users add/remove friends much less frequently than reading their friends’ updates. In those cases, the extra investment in updates is well worth it to have faster responses in queries.

????????????????????????????????

Kenrick Implementing a Graph p29

????????????????????????????????

KepnerGilbert Graph Algorithms in the Language of Linear Algebra p373

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Kirsh An Implementation and Analysis of the Skip Graph Data Structure p12
Jonathan Kirsh

????????????????????????????????

Philip Klein

http://blog.codingthematrix.com/2013/09/12/a-graphs-adjacency-matrix-and-counting-walks/

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K?bler Interval Graph Representation with Given Interval and Intersection Lengths p13

????????????????????????????????

[Kolter2016]

Kolter Graphs and Networks

J. Zico Kolter
Carnegie Mellon University
Fall 2016

Networks are the systems of interrelated objects (in the real world)
Graphs are the mathematical model for representing networks

[Kolter2016]

Adjacency list

Pros: easy to get all outgoing links from a given node, fast to add new edges (without checking for duplicates)
Cons: deleting edges or checking existing of an edge requires scan through given node’s full adjacency array

[Kolter2016]

Adjacency dictionary

Pros: easy to add/remove/query edges (requires two dictionary lookups, so a ??(1) operation)
Cons: overhead of using a dictionary over array

[Kolter2016]

Adjacency matrix

Store the connectivity of the graph as a matrix
In virtually all cases, you will want to store this as a sparse matrix
Pros/cons depend on which sparse matrix format you use, but most operations on a static graph will but much faster using the right format

KOZA COMPRESSED MULTI-ROW STORAGE FORMAT FOR SPARSE MATRICES ON GRAPHICS PROCESSING UNITS p26

????????????????????????????????????????????????????

[Kruse2000]

000Kruse Data Structures and Program Design in C++

G:\studies\000Webit\000programming\ccpp

G:\studies\000Webit\000programming\ccpp

Robert L. Kruse
Alexander J. Ryba

572

????????????????????????????????

[Kudase2016]

Kudase A Brief Study of Graph Data Structure p5

[Kudase2016]

Adjacency List

Adjacency List: This list structure extends the edge list structure by adding incidence containers to each vertex.
Here an array of linked lists is used. Array size will be equal to the number of vertices. Consider an array A[ ]. An entry A[i] represents the linked list of vertices adjacent to the ith vertex. In these, vertices are stored as objects. Each vertex further contains a list of neighboring vertices. This type of representation allows additional data of the vertices to be stored. But these additional data is stored only if edges are stored as objects that mean every vertex store its incident edges and edge stores its incident vertices.

Another representation could be maintaining two lists. First list stores indices corresponding to each vertex in the graph and each of these refer to the second list storing the index of each adjacent vertex to this one. It would be good if we associate weight of each edge with the adjacent vertex in this list. These lists of all the vertices in the graph would be useful if stored in a hash table.

It is also used to represent a weighted graph. The nodes of linked lists will be storing weights of edges. Each node has precisely as many nodes in its adjacency list as it has neighbors. Therefore, an adjacency list is a very space efficient representation of a graph. You would not store more information than actually required.

If a graph has V vertices and E edges then a graph represented using adjacency list will need –

? V+E node instances for a directed graph

? V+2E node instances for an undirected graph This is generally recommended if it efficiently represent sparse graphs.

Advantages of using adjacency list are as follows:
? Addition of a vertex and connecting new vertices with the existing ones is easier.
? Has a space complexity of O(|V|+|E|).
? It allows us to store graph in more compact form and to get the list of adjacent vertices in O(1) time which is a big benefit for some algorithms.

Disadvantages of using adjacency list are as follows:
? Queries like whether there is an edge from vertex u to vertex v are not efficient and require time complexity, O(V).
? It does not allow us to make an efficient implementation, if dynamic change of vertices number is required.

[Kudase2016]

Adjacency Matrix

Adjacency Matrix: The adjacency matrix structure augments the edge list structure with a matrix where each row and column corresponds to a vertex. It is a two dimensional matrix form where the rows represent source vertices and columns represent destination vertices. Data on edges and vertices is stored externally. Between each pair of vertices, cost of one edge is to be stored. This shows which vertices are adjacent to one another. We know that two vertices are said to be adjacent if there is an edge connecting them. For a graph of n vertices, the dimensions of adjacency matrix will be n*n.

In case of directed graph, suppose if vertex j is adjacent to vertex i then there will be an edge from i to j and vice-versa. For a given vertex i, its adjacent vertices will be determined by looking at the row entry (i, [1…n]) of the matrix. If the value is true then it indicates that there exists an edge from i to j and false indicates no edge exists.

In case of undirected graph, the matrix values will be populated with Boolean values. The values of (i, j) and (j, i) are equal which means adjacency matrix for undirected graph is always symmetric along the diagonal.

In weighted graph, the Boolean values will be the costs of the edges connecting two vertices of a graph. Generally adjacency matrix is used to represent weighted graphs. If adj[i][j] = w , then we will say that there is an edge from vertex i to vertex j with weight w (can be any positive number). There are some cases where zero can also be the possible weight of the edge, then we have to store some sentinel value for non-existent edge, which can be a negative value; since the weight of the edge is always a positive number.

An adjacency matrix requires an n2 element array so for parse graphs much of the matrix will be empty. Also, for undirected graphs half of the graph is repeated information. Hence these matrices are said to be space inefficient.

The memory use of an adjacency matrix is O(n2) where n = number of vertices.

Advantages of using adjacency matrix are as follows:
? Easy to understand, implement and convenient to work with.
? Removing an edge involves time complexity of O(1).
? Queries like whether there is an edge from vertex ?u? to vertex ?v? are efficient and require time complexity, O(1).

Disadvantages of using adjacency matrix are as follows:
? Space complexity is of the O(V2) where V = number of vertices.
? Sparse matrix has less number of edges but the space complexity is still the same.
? Adding an edge involves time complexity of O(V2).
? If the number of nodes in the graph may change, matrix representation is too inflexible (especially if we don?t know the maximal size of the graph).

This is preferred if the graph is of dense type where |E| ~ V2.

????????????????????????????????????????????????????????????

[Kuhnert2016]

Kuhnert Space Efficient Algorithms for Graph Isomorphism and Representation p117

Sebastian Kuhnert

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[Kumar1996]

Kumar Improved Algorithms and Data Structures for Solving Graph Problems in External Memories p34


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Literature Index

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L18Graphs

March 23, 2017

???????????????????????????????

[Lanum2016]

Lanum Visualizing Graph Data
Corey L. Lanum
  • November 2016
  • ISBN 9781617293078
  • 232 pages
  • printed in black & white

https://www.manning.com/books/visualizing-graph-data

[Lawlor2013]

Lawlor Introduction to Graph Algorithms p8

Richard Lawlor

????????????????????????????????

[Lee2012]

Lee Visualizing Adjacency Matrices in Python

15th November 2012

Conrad Lee

https://sociograph.blogspot.com/2012/11/visualizing-adjacency-matrices-in-python.html

Lehmann Implementing Graph Query Languages over Compressed Data Structures: A Progress Report p5

Nicol′as Lehmann1;2 and Jorge P′erez1;2

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Lei?a A Graph-Based Higher-Order Intermediate Representation p11
Roland Lei?a

?????????????????????????????????????????????????

Lenharth Graph Representations p5
Andrew Lenharth

http://www.lenharth.org/

lenharth@ices.utexas.edu

andrew@lenharth.org

2017-08-26

[Lenharth2014]
Base Structure Representations

Adjacency matrix
Adjacency Matrix -- operations
Easy
?Iterate nodes
?Edges by src
?Edges by dst
?Loopup by src, dst
?Add Edge
?Delete edge
Hard
?Add node
?Delete node

Adjacency Matrix -- Costs
?Lookups: O(1)
?Iterations: array iteration
?Edge addition: O(1)
?Edge removal: O(1)
?Space: O(N^2)
–Good for dense graphs

Adjacency lists

?Nodes stored in array as pointers to linked lists
?Edges stored as linked list at src
?Fundamentally directed

Adjacency Lists – Operations
Easy
?Iterate nodes
?Edges by src
?Add Edge
?Delete edge
?Add node?
Hard
?Edges by dst
?Loopup by src, dst
–Linear seach
?Delete node

Adjacency Lists – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Linked List iteration
–Expensive due to indirection
–not cache friendly
?Edge addition: O(1)
–Except involves an allocation
?Edge removal: O(E)
?Space: O(N + E)
–Constant for E == sizeof(ptr) + sizeof(Edata) + sizeof(int)

Edge List

?Think of Edges not Nodes as primary
?Array of Edges (src,dst,data)
–May be sorted by src or dst
?Array of Node data
?May not be able to iterate edges by node
?Easy global iteration over edges

Compressed Edge lists
?Rather than storing integer indexes or pointers, store compressed data stream
?Decompress as iterating over edges
?E.g. Delta-encoding
–Each edge is stored as the delta from the previous edge
?1,4,7,9 -> 1,3,3,2
–Use fewer bytes for each edge (variable length encoding)

Adjacency vectors
?Replace Linked List with pointer to vector
–Resizable vector?
?Costs?
?Advantages?

Compressed row storage
Compressed Sparse Row Storage
?Try to combine space efficiency of Lists with array traversal for edges
?Store Node data in an array
?Store all edges in an array (sorted by src)
?Store an array of pointers to edges
–Indexed by node id
–One pointer per node

CSR – Operations
Easy
?Iterate nodes
?Edges by src
?Add node?
Hard
?Edges by dst
?Add Edge
?Delete Edge
?Loopup by src, dst
–Linear seach
?Delete node

CSR – Costs
?Lookups: O(E)
–One node could have all edges
?Iterations: Array iteration
?Space: O(2N + E)
–Constant for E == sizeof(Edata) + sizeof(int)

????????????????????????????????

[Liang2013]

000Liang Introduction to Programming Using Python p582

G:\studies\000Webit\000programming\Python

????????????????????????????????

[Loerch2000]

Loerch An Introduction to Graph Algorithms p46

???????????????????????????????????????

[Lovasz2009]

Lovasz Geometric Representations of Graphs p213

Laszlo Lovasz
Institute of Mathematics
E?otv?os Lorand University, Budapest
e-mail: lovasz@cs.elte.hu

http://www.cs.elte.hu/~lovasz/

lovasz@cs.elte.hu

2018-08-26

1 Planar graphs and polytopes 11
2 Graphs from point sets 19
3 Harmonic functions on graphs 33
4 Rubber bands 41
5 Rigidity 63
6 Representing graphs by touching domains 73
7 Analytic functions on graphs 101
8 The Colin de Verdiμere Number 115
9 Orthogonal representations 123
10 Graph independence to linear independence 153
11 Metric embeddings 157
12 Adjacency matrix and regularity partitions 163
13 Some general issues 165

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[lucida2016]

lucida Data Structures and Algorithms Rewind: Graph

2016-11-03

http://notes.lucida.me/2016/11/03/ds-graph-notes/


Untitled Document

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Literature Index

(2017-07-01 -- 2018-07-01)

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[Madduri2008]

Madduri Compact Graph Representations and Parallel Connectivity Algorithms for Massive Dynamic Network Analysis p11

Kamesh Madduri
Computational Research Division
Lawrence Berkeley National Laboratory
Berkeley, USA 94703

http://www.cse.psu.edu/~kxm85/

madduri@cse.psu.edu

2018-08-27

David A. Bader
College of Computing
Georgia Institute of Technology
Atlanta, USA 30332

https://www.cc.gatech.edu/~bader/

Professor and Chair
School of Computational Science and Engineering
College of Computing
Georgia Institute of Technology
Atlanta, Georgia 30332
bader@cc.gatech.edu
http://www.cc.gatech.edu/
?
bader

2018-08-27

adjacency lists using adjacency arrays

For representing sparse static graphs, adjacency lists implemented using cache-friendly adjacency arrays are shown to give substantial performance improvements over linkedlist and adjacency matrix representations for sparse graphs [22].

(adjacency lists using) dynamic, resizable adjacency arrays

Dynamic Arrays (Dyn-arr). We can extend the static graph representation and use dynamic, resizable adjacency arrays for processing insertions and deletions. Clearly, this would support fast insertions. For inserting a new edge hu; vi, we resize the adjacency array of u if needed, and place v at the end of the array. The count can be incremented using an atomic increment operation on modern hardware,
and so this representation supports lock-free, non-blocking insertions.

There are two potential parallel performance issues with this data structure. Edge deletions are expensive in this representation, as we may have to scan the entire adjacency list in the worst case to locate the required tuple. Note that a scan is reasonable for low-degree vertices (say, less than 10 adjacencies), given the spatial locality we have due to the contiguous adjacency representation. However,
due to the power-law degree distributions in small-world networks, we may encounter several high-degree vertices in the graph, and deletions for these vertices would necessitate O(n) additional work.

linkedlist

adjacency matrix

??????????????????????????????????????????

Madduri Scaling up graph algorithms on emerging multicore systems p22

[Madduri2009]

Complementing data stream algorithms, a graph or network representation is a convenient abstraction in many applications – unique data entities are represented as vertices, and the interactions between them are depicted as edges. The vertices and edges can further be typed, classified, or assigned attributes based on relational information from the heterogeneous sources.

For representing sparse static graphs, adjacency lists implemented using cache-friendly adjacency arrays are shown to give substantial performance improvements over linkedlist and adjacency matrix representations for sparse graphs [22]. For dynamic networks, we need to process insertions of vertices and edges, which may be streaming or batched.
Thus, we experiment with the performance of several candidate representations for small-world graphs and discuss the trade-offs associated with each data structure.

Dynamic Arrays (Dyn-arr). We can extend the static graph representation and use dynamic, resizable adjacency arrays for processing insertions and deletions.

A hybrid representation (Hybrid-arr-treap). To process both insertions and deletions efficiently, and also given the power-law degree distribution for small-world networks, we design a hybrid representation that uses Dyn-arr to represent adjacencies of low-degree vertices, and Treaps for high-degree vertices.

Maiya Visually Pleasing Graph Representation Using GraphDraw.docx

adjacency matrix

Malik Data Structures Using C++ p945

G:\studies\000Webit\000programming\ccpp

Malik Data Structures Using C++ Second Edition p945

G:\studies\000Webit\000programming\ccpp

Manchester Graph Representation and Traversal.docx

adjacency list versus adjacency matrix

??????????????????????????????????????

Manevich Synthesizing Concurrent Graph Data Structures: A Case Study p14
R. Manevich, R. Kaleem, and K. Pingali

????????????????????????????????

Martin Graph Theory and Social Networks p148

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Matas The color adjacency graph of multi-coloured objects p18.pdf

J Matas

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[Mehlhorn2008]

Mehlhorn Data Structures and Algorithms: The Basic Toolbox - 8 Graph Representations p8.pdf

4

Kurt Mehlhorn

https://people.mpi-inf.mpg.de/~mehlhorn/

https://people.mpi-inf.mpg.de/~mehlhorn/

https://people.mpi-inf.mpg.de/~mehlhorn/ftp/Toolbox/GraphRep.pdf

CHAPTER 9 The Graph Data Model p78

store node or edge information in a hash table.

adjacency matrix

Adjacency matrices are good for rather dense graphs.

An n-node graph can be represented by an n×n adjacencymatrix A. Ai j is 1 if (i, j) ∈ E and 0 otherwise. Edge insertion or removal and edge querieswork in constant time.

It takes time O(n) to obtain the edges entering or leaving a node. This is only efficient
for very dense graphs with m = W??n2

The storage requirement is n2 bits.

For very dense graphs, this may be better than the n+m+O(1) words required for adjacency
arrays. However, even for dense graphs, the advantage is small if additional edge information is needed.

adjacency list

Adjacency Lists – Dynamic Graphs

Adjacency lists are good if the graph changes frequently

Adjacency lists for sparse graphs should be implemented without the dummy item introduced in Sect. 3.1, because an additional item would waste considerable space.

The second solution has only one item for each undirected edge (or pair of directed edges) and makes this item a member of two adjacency lists. So, the item for an undirected edge {u,v} would be a member of lists Eu and Ev. If we want doubly linked adjacency information, the edge object for any edge {u,v} stores four pointers: two are used for the doubly linked list representing Eu, and two are used for the doubly linked list representing Ev. Any node stores a pointer to some edge incident on it. Starting from it, all edges incident on the node can be traversed. The bottom part of Fig. 8.1 gives an example. A small complication lies in the fact that finding the other end of an edge now requires some work. Note that the edge object for an edge {u,v} stores the endpoints in no particular order. Hence, when we explore the
edges out of a node u, we must inspect both endpoints and then choose the one which is different from u. An elegant alternative is to store u⊕v in the edge object [145]. An exclusive OR with either endpoint then yields the other endpoint. Also, this representation saves space.

For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

Unbounded arrays

Unbounded arrays are more cache-efficient.

linked list

Linked lists allow constant-time insertion and deletion of edges at arbitrary positions.

In the example in Fig. 8.1, we show circularly linked lists.

Edge Sequences

The edge sequence representation is good only in specialized situations.

In Chap. 3, we learned how to implement dynamic sequences. We can use any of the solutions presented there to produce a dynamic graph data structure. For each node v, we represent the sequence Ev of outgoing (or incoming, or outgoing and incoming) edges by an unbounded array or by a (singly or doubly) linked list.

This is even more compact than the 2m words needed for an edge sequence representation.

ordered edge sequence representation

Unordered Edge Sequences = Edge Lists ???

Perhaps the simplest representation of a graph is as an unordered sequence of edges. Each edge contains a pair of node indices and, possibly, associated information such as an edge weight.Whether these node pairs represent directed or undirected edges is merely a matter of interpretation.

Sequence representation is often used for input and output.

It is easy to add edges or nodes in constant time.

However, many other operations, in particular navigation, take time theta(m), which is forbiddingly slow.

Only a few graph algorithms work well with the edge sequence representation;

most algorithms require easy access to the edges incident on any given node. In this case the ordered representations discussed in the following sections are appropriate.

In Chap. 11, we shall see two minimum-spanning-tree algorithms: one works well with an edge sequence representation and the other needs a more sophisticated data structure.

This is even more compact than the 2m words needed for an edge sequence representation.

Edge arrays are a compact and efficient graph representation.

Their main disadvantage is that it is expensive to add or remove edges. For example, assume that we want to insert a new edge (u,v). Even if there is room in the edge array E to accommodate it, we still have to move the edges associated with nodes u+1 to n one position to the right, which takes time O(m).

Array

NodeArray

EdgeArray

information associated with nodes can be stored in arrays.

NodeArray and EdgeArray to indicate array-like data structures that can be indexed by nodes and by edges, respectively

Adjacency Arrays– Static Graphs

To support easy access to the edges leaving any particular node, we can store the edges leaving any node in an array. If no additional information is stored with the edges, this array will just contain the indices of the target nodes. If the graph is static, i.e., does not change over time, we can concatenate all these little arrays into a single edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an example.edge array E. An additional array V stores the starting positions of the subarrays, i.e., for any node v, V[v] is the index in E of the first edge out of V. It is convenient to add a dummy entry V[n+1] with V[n+1] = m+1. The edges out of any node v are then easily accessible as E[V[v]], . . . , E[V[v+1]?1]; the dummy entry ensures that this also holds true for node n. Figure 8.1 shows an xample.

Adjacency array representations can be generalized to store additional information: we may store information associated with edges in separate arrays or within the edge array. If we also need incoming edges, we may use additional arrays V′ and E′ to store the reversed graph.

The memory consumption for storing a directed graph using adjacency arrays is n+m+Q(1) words.

Edge arrays are a compact and efficient graph representation. Their main disadvantage is that it is expensive to add or remove edges. For example, assume that we want to insert a new edge (u,v). Even if there is room in the edge array E to accommodate it, we still have to move the edges associated with nodes u+1 to n one position to the right, which takes time O(m).

Very often, some variant of adjacency arrays is fastest. This may be true even if the graph changes, because often there are only a few changes, or all changes happen in an initialization phase of a graph algorithm, or changes can be agglomerated into occasional rebuildings of the graph, or changes can be simulated by building several related graphs.

There are many variants of the adjacency array representation.

Information associated with nodes and edges may be stored together with these objects or in separate arrays. A rule of thumb is that information that is frequently accessed should be stored with the nodes and edges. Rarely used data should be kept in separate arrays, because otherwise it would often be moved to the cache without being used. However, there can be other,more complicated reasons why separate arrays may be faster. For example, if both adjacency information and edge weights are read but only the weights are changed, then separate arrays may be faster because the amount of data written back to the main memory is reduced.

linked-edge-objects representation

Implicit Representations

Google Scholar

????????????????????????????????

Meinel Algorithms and data stuctures in VLSI designs p279

G:\studies\000VLSIChip\000books

????????????????????????????????

Duane Merrill, Michael Garland, and Andrew Grimshaw. Scalable GPU graph traversal. In Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP '12, pages 117{128, New York, NY, USA, February 2012. ACM.

Mishra

https://www.thecrazyprogrammer.com/2014/03/representation-of-graphs-adjacency-matrix-and-adjacency-list.html

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Montes Graph Representation for Program Evolution: an Overview p32
Héctor A Montes

????????????????????????????????

000Moore Python and Data Structures p8

G:\studies\000Webit\000programming\Python

????????????????????????????????

000Morin Open Data Structures (in C++) p336

G:\studies\000Webit\000programming\ccpp

Morin Open Data Structures (in C++) p336

G:\studies\000Webit\000programming\ccpp

000Morin Open Data Structures (in pseudocode) p326

G:\studies\000Webit\000programming\Python

????????????????????????????????

[Morris1998]

Morris Graph Representations.docx

John Morris , 1998

https://www.cs.auckland.ac.nz/software/AlgAnim/graph_rep.html

https://www.cs.auckland.ac.nz/software/AlgAnim/graph_rep.html

Adjacency Matrix

Adjacency List

http://cba.winthrop.edu/acm/PLDS210/mst.html

Mourchid

https://uk.mathworks.com/matlabcentral/answers/217894-generate-a-weighted-graph-and-an-adjacency-matrix-from-an-image-matrix

Munro Dynamic Data Structures for Document Collections and Graphs p13
J. Ian Munro


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Literature Index

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?????????????????????????

Nanda Lecture 11 Graphs and their Adjacency Matrices p6

Randal C. Nelson

Associate Professor
Department of Computer Science
University of Rochester
Rochester, NY 14627-0226
Office: Wegmans Hall 3009
nelson@cs.rochester.edu

https://www.cs.rochester.edu/~nelson/

https://www.cs.rochester.edu/~nelson/courses/csc_173/graphs/implementation.html

Comparison of Implementations

Consider a graph G with N nodes and E edges (0 <= E <= N^2)

[Nelson]

  • Adjacency matrix
    • Is (u,v) an edge? -- O(1)
    • Successors (u) -- O(N)
    • Predecessor (u) -- O(N)
    • Space -- O(N^2) (bits) to store the matrix
    • Best for dense graphs (E ~= N^2)

[Nelson]

  • Adjacency lists
    • Is (u,v) an edge? -- O(E/N) on average
    • Successors (u) -- O(E/N)
    • Predecessor (u) -- O(N+E)
    • Space -- O(N + E)
    • Best for sparse graphs (E << N^2)

???????????????????????????????????????

NetflixGraph

https://github.com/Netflix/netflix-graph

http://netflix.github.io/netflix-graph/

NetworkGraph Theory Graph-based representations p13

Representation (Matrix)
? Incidence Matrix
? Adjacency Matrix

Representation (List)
? Edge List
? Adjacency List (node list)

http://cs.nyu.edu/courses/fall16/CSCI-UA.0102-001/Notes/Graphs.html


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Literature Index

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OJJ GRAPH REPRESENTATION.docx

ojjcourse@psu.edu

Adjacency Matrix

Incidence Matrix

Okie Graphs - Terminology and Representation.docx

Edward G. (Ned) Okie

Professor of Computer Science
Department of Information Technology
Radford University
Radford, Virginia 24142-6933

Office: | 219 Davis Hall
Email: | nokie@radford.edu
Phone: | 540-831-5992
Fax: | 540-831-6706

My RU Page
Current schedule
Current classes: | ITEC 320, ITEC 420
Office Hours: | MW: 10:00-10:55; TuTh 11:00-11:55; F: 2:00-2:55
Other information

2018-08-28

Adjacency list and adjacency matrix

Olorunnisola A Gentle Introduction to Data Structures: How Graphs Work

Michael Olorunnisola

Dec 6, 2016

https://medium.freecodecamp.org/a-gentle-introduction-to-data-structures-how-graphs-work-a223d9ef8837

????????????????????????????????

[Opendatastructures]

Opendatastructures 12.2 AdjacencyLists A Graph as a Collection of Lists.docx

AdjacencyLists

  • What type of collection should be used to store each element of [image]? One could use an array-based list, a linked-list, or even a hashtable.
  • Should there be a second adjacency list, [image], that stores, for each [image], the list of vertices, [image], such that [image]? This can greatly reduce the running-time of the [image] operation, but requires slightly more work when adding or removing edges.
  • Should the entry for the edge [image] in [image] be linked by a reference to the corresponding entry in [image]?
  • Should edges be first-class objects with their own associated data? In this way, [image] would contain lists of edges rather than lists of vertices (integers).

[ORLIN1981]

ORLIN DYNAMIC NETWORK FLOWS p115

1981


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Literature Index

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PageRank-Project

????????????????????????????????????????????????????????????

[Pahikkala2006]

Pahikkala Graph Kernels versus Graph Representations a Case Study in Parse Ranking p8

Tapio Pahikkala

graph representations for dependency parses

We now give a brief introduction to kernels considered in this study. Formally, let X denote the input space, which can be any set, and H denote the feature space. For any mapping : X ? H, k(x, z) = h(x), (z)i is a kernel function. Following [3], we define a labeled graph representation of data points as follows. Below, Mi×j(R) denotes the set of real valued matrices of dimension i × j and [M]i,j denotes the element of matrix M in the i-th row and j-th column. Let L = {l}r, r ? N+ be an enumeration of all possible labels. Let G = (V,E, h) be a graph that consists of the set of vertices V , the set of edges E ? V × V , and a function h : V ? L that assigns a label to each vertex of a graph. We assume that the edge set of G is represented as an adjacency matrix A ? M|V |×|V |(R) whose rows and columns are indexed by the vertices V , and [A]i,j is one if the vertices vi ? V and vj ? V are connected with an edge, and zero otherwise. We also assume that the function h is represented as a label allocation matrix L ? M|L|×|V |(R) so that its element [L]i,j is one if vertex vj ? V has a label li ? L and zero otherwise.

http://forum.paradigm4.com/t/graph-representation/1564

Graph representation

I′m using the matrix of data as a representation of a Graph; I'm interested on detecting the transitives of the graph; any suggestions ?

there is book called Graph Analytics in the language of linear algebra which talks about how to compute variety of common graphs analytics using matrix operations. in particular spgemm operator in scidb should be helpful

Papadimitriou Combinatorial Algorithms & Data Structures Spring 2003 p9
Lecture 2: 1.23.03
Lecturer: Prof. Christos Papadimitriou

????????????????????????????????????????????????????????????

[Park2014]

Park Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation p4

Eunhyuk Park

pointer-assisted graph representation

The pointer-assisted graph avoids expensive sorting, rearrangement and search operations which occupy a significant portion of graph computation.

A vertex is represented by a tuple of vertex value (e.g., vertex weight in pagerank), in-edge and out-edge pointers. An in-edge pointer points to an array of in-edge information. Each entry in the array consists of source vertex ID and edge value (e.g., edge weight in pagerank). An out-edge pointer in the vertex data points to an array of out-edge information. Each entry of the array contains destination vertex ID and edge offset (offset in the in-edge array of the destination vertex). Note that each edge has its weight
information only at a single location, in its entry of in-edge array (edge value).

Figure 5 Pointer-assisted graph representation

our proposed pointer-assisted graph representation enables us to access, with low latency, only the required data from the storage without additional expensive data re-arrangement steps.

tabular representation / tabular form

the edges are expressed as a tabular form as shown in Figure 1 (b) (in-edge sorted in this case). Each entry in the table contains two vertex IDs (‘in’ for destination and ‘out’ for source) connected to the
edge and edge value (edge weight in this example).

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[Park2015]

Park Basic Graph Algorithms p38

Implementing Adjacency List
? Solution 1. Using linked lists
– Too much memory/time overhead
– Using dynamic allocated memory or pointers is bad
? Solution 2. Using an array of vectors
– Easier to code, no bad memory issues
– But very slow
? Solution 3. Using arrays (!)
– Assuming the total number of edges is known
– Very fast and memory-efficient

Patty Math 639, Compressed Row Storage (CRS) Format for Sparse Matrices p24

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Pfenning Lecture 23 Notes Representing Graphs

Lecture 23 Notes
Representing Graphs
15-122: Principles of Imperative Computation (Spring 2016)
Frank Pfenning, André Platzer, Rob Simmons, Penny Anderson

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Phukon The Composite Graph Model for Web Document and its Impacts on Graph Distance Measurement p8
Kaushik K. Phukon

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Piana A graph representation of basic macroeconomic scheme p27

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Picard Coinductive Graph Representation p64.pdf

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Picard Permutations in Coinductive Graph Representation p20
Celia Picard

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Pisanski Graph representation.ppt

Popov Algorithm of the Week Graphs and Their Representation.docx

https://dzone.com/users/735767/stoimen.html

Stoimen Popov

Adjacency Matrix

Adjacency Lists

????????????????????????????????????????????????????????????

[Popov2012]

Popov Computer Algorithms Graphs and their Representation.docx

Stoimen Popov

http://stoimen.com/blog

Adjacency Matrix

In case of directed graph, we can use 1 for the edge (i,j) and -1 for (j,i) in case the edge is directed from i to j. For a weighted directed graph we can put the weights instead of 1s.

In case that we’re using adjacency matrix we have:

  1. Adding an edge – O(1);
  2. Deleting an edge – O(1);
  3. Answering the question “is there an edge between i and j” – O(1);
  4. Finding the successors of a given vertex – O(n);
  5. Finding (if exists) a path between two vertices – O(n2);

Adjacency Lists

While for an adjacency list we can have:

  1. Adding an edge – O(log(n));
  2. Deleting an edge – O(log(n));
  3. Answering the question “is there an edge between i and j” – O(log(n));
  4. Finding the successors of a given vertex – O(k), where “k” is the length of the lists containing the successors of i;
  5. Finding (if exists) a path between two vertices – O(n+m) – where m <= n;


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S. Raghavan and H. Garcia-Molina. Representing Web graphs. In Proc. 19th International Conference on Data Engineering (ICDE), page 405, 2003.

https://medium.com/@JonRamer/day-84-graph-data-structures-es6-magic-3cb77ac632ba

Rao Graph p19

Rajwant Singh Rao

ADJACENCY MATRIX REPRESENTATION

LINKED LIST REPRESENTATION

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[Rocca2006]

Rocca The giRaph package for graph representation in R p1

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Rotta Graph Representation


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http://doc.sagemath.org/html/en/reference/graphs/sage/graphs/base/overview.html

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https://www.codediesel.com/algorithms/building-a-graph-data-structure-in-php/

[Sangam2014]

Sangam Graph Theory Basics - Adjacency Matrix

December 24, 2014 / Vamsi Sangam / 38 Comments

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Sb?rlea DFGR: an Intermediate Graph Representation for Macro-Dataflow Programs p8
Alina Sb?rlea

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[Schwarz2012]

Schwarz Graph Representations and Algorithms p164
We can represent a graph Map<Node*, Vector<Node*> > as a map from nodes to the list of nodes each node is connected to.

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Schwarz Graph Representations and Algorithms p164

Keith Schwarz

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Sedziwy Effective graph representation p13

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Seibert Learning Aspect Graph Representations from View Sequences p8

Shaffer Data Structures and Algorithm Analysis Edition 3.2 (C++ Version) p613

G:\studies\000Webit\000programming\ccpp

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Shai Transforming Engineering Problems through Graph Representations p28

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[Shaia1998]

Shaia Graph theory representations of engineering systems and their embedded knowledge p13
Graphs as representation of engineering systems
An engineering system is usually represented as a diagram, with nodes, lines, and words or numbers which assign values to some or all nodes or lines.
Flow graph representation
Definition of the flow graph representation: A directed graph G is a flow graph representation if the value of the flow in each edge is independent of the potential difference across that edge.
Potential graph representation
Definition of a potential graph: Let G be a graph in which for every vertex there will be associated a number which represents the potential at the vertex.

shalom

https://blog.elishalom.com/category/python/

000Shirwaikar Data Structures Using C & Object Oriented Programming Concepts Using C++

G:\studies\000Webit\000programming\ccpp

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Shkotin Graph representation of context-free grammars p4
Alex Shkotin

Shukla

https://xlinux.nist.gov/dads/HTML/adjacencyMatrixRep.html

https://xlinux.nist.gov/dads/HTML/adjacencyListRep.html

SKS

Sandeep Kumar Shukla

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Sidere Vector Representation of Graphs Application to the Classification of Symbols and Letters p6

Siek Review of Elementary Graph Theory.docx

Graph Data Structures

Jeremy Siek, Indiana University (jsiek@osl.iu.edu)

http://www.boost.org/people/jeremy_siek.htm

2017-08-29

Adjacency Matrix

Adjacency List

Edge List

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[Singh2012]

Singh Role of Adjacency Matrix & Adjacency List in Graph Theory p5

3

[Singh2012]

Adjacency Matrix

Specifically, the adjacency matrix of a finite graph G on n vertices is the n × n matrix where the non diagonal entry aij is the number of edges from vertex i to vertex j, and the diagonal entry aii, depending on the convention, is either once or twice the number of edges (loops) from vertex i to itself.

Undirected graphs often use the former convention of counting loops twice, whereas directed graphs typically use the latter convention.

In the special case of a finite simple graph, the adjacency matrix is a (0, 1)-matrix with zeros on its diagonal.

If the graph is undirected, the adjacency matrix is symmetric.

Suppose G is a simple directed graph with m nodes, and suppose the nodes of G have been ordered and are called v1,v2…, vm. Then the adjacency matrix A = (aij) of the graph G is the m × m matrix defined as follows:
aij = { 1 if vi is adjacent to vj, i.e.; if there is an edge (vi, vj). 0 otherwise}

Such a matrix A, which contains entries of only 0 and 1, is called a Bit matrix or a Boolean matrix.

The adjacency matrix A of graph G does depend on the ordering of the nodes of G, that is, a different ordering of nodes may result in a different adjacency matrix. However, the matrices resulting from two different orderings are closely related in that one can be obtained from the other by simply interchanging rows and columns.

Suppose G is an undirected graph. Then the adjacency matrix A of G will be a symmetric matrix, i.e; one in which aij = aji for every i and j. This follows from the fact that each undirected edge [u, v] corresponds to the two directed edges (u, v) and (v, u).

The above matrix representation of a graph may be extended to multigraphs. Specifically, if G is a multigraph, then the adjacency matrix of G is the m × m matrix A = (aij) defined by setting aij, equal to the number of edges from vi to vj.

Adjacency matrix of a bipartite graph

The adjacency matrix A of a bipartite graph whose parts have r and s vertices has the form:
where B is an r × s matrix and O is an all-zero matrix. Clearly, the matrix B uniquely represents the bipartite graphs, and it is commonly called its biadjacency matrix. Formally, let G = (U, V, E) be a bipartite graph or bigraph with parts U = u1... ur and V = v1,...,vs.
An r x s 0-1 matrix B is called the biadjacency matrix if Bi,j
= 1 iff .
If G is a bipartite multigraph or weighted graph then the elements Bi,j are taken to be the number of edges between or the weight of (ui,vj) respectively.

Seidel adjacency matrix

The Seidel adjacency matrix or (0,?1,1)-adjacency matrix of a simple graph has zero on the diagonal and entry aij = ? 1 if ij is an edge and +1 if it is not. This matrix is used in studying
strongly regular graphs and two-graphs.

distance matrix

A distance matrix is like a higher-level adjacency matrix. Instead of only providing information about whether or not two vertices are connected, also tells the distances between them. This assumes the length of every edge is 1. A variation is where the length of an edge is not necessarily 1.

The sequential representation of G in memory---- i.e; the representation of G by its adjacency matrix A--- has a number of major drawbacks.

First of all, it may be difficult to insert and delete nodes in G. This is because the size of A may need to be
changed and the nodes may need to be reordered, so there may be many changes in the matrix A.

Furthermore, if the number of edges is O(m) or O(m log2 m), then the matrix A will be a sparse(will contain many zeros); hence a great deal of space will be wasted.

Adjacency list

In graph theory, an adjacency list is the representation of all edges or arcs in a graph as a list.

If the graph is undirected, every entry is a set (or multiset) of two nodes containing the two ends of the corresponding edge;

if it is directed, every entry is a tuple of two nodes, one denoting the source node and the other denoting the destination node of the corresponding arc.

Typically, adjacency lists are unordered.

Let G be a directed graph with m nodes.

Accordingly, G is usually represented in memory by a linked representation, also called an adjacency structure.

Consider the graph G in Fig. 2(a). The table in Fig. 2(b) shows each node in G followed by its adjacency list, which is its list of adjacent nodes, also called its successors or neighbors. Fig. 2(c) shows a schematic diagram of a linked representation of G in memory.

Specifically, the linked representation will contain two lists (or files), a node list NODE and an edge list EDGE, as follows:

============================

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Situngkir Small World Network of Athletes Graph Representation of the World Professional Tennis Player p13

[Skiena2008]

Steven Skiena

http://www3.cs.stonybrook.edu/~algorith/files/graph-data-structures.shtml

  • Which algorithms will you be implementing? Certain algorithms are easier on adjacency matrices (such as all-pairs shortest path) and others on adjacency lists (such as most DFS-based algorithms). Adjacency matrices win for algorithms that repeatedly ask, ``Is (i,j) in G?'' However, most graph algorithms can be modified to eliminate such queries.
  • Will you be modifying the graph over the course of your application, and if so, how? Repeated edge insertions and (particularly) deletions argue for adjacency matrices, or perhaps for fancier versions of adjacency lists such as binary search trees. However, more likely than modifying the topology of graph is modifying the attributes of a vertex or edge of the graph, such as size, weight, or color. Attributes are best handled as extra fields in the vertex or edge records of adjacency lists.

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[Slesarenko2015]

Slesarenko How to select the best graph representation for a given task p18

Alexander Slesarenko
Alexander Filippov
Alexey Romanov
Yuri Zotov

Flat Sparse Matrix

Flat Adjacency List

[Sommer2010]

Sommer 8.1 Graph Representation in Memory p14
Graph Representation in Memory

Christian Sommer

www.sommer.jp

There are several possibilities to represent a graph G = (V;E) in memory.

Adjacency matrix

For instance, a matrix wastes a lot of memory if a sparse graph is given, but it has optimal access times for any type of graph.

Edge List

While being a space-ecient way to store the graph, the access times of an edge list are slower than the access times of an adjacency matrix (for most edges).

Adjacency List

Likewise, this is an ecient way to represent a graph but the access times are slower compared to a matrix (O(lg n) compared to O(1)). One way to solve this issue is to use a hash table for each node, containing all its neighbors.

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Sowa Conceptual Graphs p26
John F. Sowa

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Spinrad Efficient Graph Representations

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[Stratis2014]

Stratis Graph Representation of Concurrent Programs in C++ p50

Graph Visualization
Our tool is able to provide a visual representation of all the afore-mentioned graphs. More specifically, the tool exports the graphs in the dot format which is supported by the GraphViz [8] software package and then (internally) utilizes GraphViz for producing digital images in png format representing each graph.

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[Suanfazu2015]

Suanfazu Comparing object graph representation to adjacency list and matrix representations.docx

http://suanfazu.com/t/comparing-object-graph-representation-to-adjacency-list-and-matrix-representations/6841

Steve Yegge

http://steve-yegge.blogspot.com/2008/03/get-that-job-at-google.html

objects and pointers / object representation

objects and pointers
These are just basic datastructures like hammar said in the other answer, in Java you would represent this with classes like edges and vertices. For example an edge connects two vertices and can either be directed or undirected and it can contain a weight. A vertex can have an ID, name etc. Mostly both of them have additional properties. So you can construct your graph with them like

Vertex a = new Vertex(1);
Vertex b = new Vertex(2);
Edge edge = new Edge(a,b, 30); // init an edge between ab and be with weight 30

This approach is commonly used for object oriented implementations, since it is more readable and convenient for object oriented users

Objects and pointers is mostly the same as adjacency list, at least for the purpose of comparing algorithms that use these representations.
Compare

struct Node {
    Node *neighbours[];
};

with

struct Node {
    Node *left;
    Node *right;
};

You can easily construct the list of neighbours on-the-fly in the latter case, if it is easier to work with than named pointers.

Advantage of the object representation (incidence list) is that two adjacent vertices share the same instance of the edge. This makes it easy to manipulate with undirected edge data (length, cost, flow or even direction). However it uses extra memory for pointers.

matrix
A matrix is just a simple 2 dimensional array. Assuming you have vertex ID's that can be represented as an int array like this:

int[][] adjacencyMatrix = new int[SIZE][SIZE];
// SIZE is the number of vertices in our graph
adjacencyMatrix[0][1] = 30;
// sets the weight of a vertex 0 that is adjacent to vertex 1

This is commonly used for dense graphs where index access is necessary. You can represent a un/directed and weighted structure with this.

adjacency list
This is just a simple datastructure mix, I usually implement this using a HashMap<Vertex, List<Vertex>>. Similar used can be the HashMultimap in Guava.
This approach is cool, because you have O(1) (amortized) vertex lookup and it returns me a list of all adjacent vertices to this particular vertex I demanded.

ArrayList<Vertex> list = new ArrayList<>();
list.add(new Vertex(2));
list.add(new Vertex(3));
map.put(new Vertex(1), list); // vertex 1 is adjacent to 2 and 3

This is used for representing sparse graphs, if you are applying at Google, you should know that the webgraph is sparse. You can deal with them in a more scalable way using a BigTable1.

Sumitjain Graph Representation — Adjacency Matrix and Adjacency List.docx

http://algorithms.tutorialhorizon.com/author/sumitjain/

Adjacency Matrix and Adjacency List


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Tangwongsan Lecture 7 — Graph Representations, Sets, and Tables p11

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Thomas Pathfinding

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Thomsen Adjacency matrix code visualizer

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Thulasiraman Handbook of Graph Theory Combinatorial Optimization and Algorithms p1217

G:\studies\00000Graph\0000general

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Tilstra COMPARING MATRIX-BASED AND GRAPH-BASED REPRESENTATIONS FOR PRODUCT DESIGN p6
Andrew H Tilstra

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[Trinks2012]
“Graph Polynomials and Their Representations”

Trinks Graph Polynomials and Their Representations p122

The title of this dissertation is chosen to include two possible meanings of the term “representation” in connection with graph polynomials. Mainly, by “representations for graph polynomials” we mean the frameworks (ways, formalisms, concepts) used to deVne graph polynomials. Thus, we are talking about an “edge subset representation” and a “coloring representation” if a graph polynomial is deVned as a sum over edge subsets and as a sum over colorings, respectively. As the name suggests, the chromatic polynomial is originally deVned in terms of colorings and therefore by a coloring representation.
Furthermore, it seems to be possible to expand this meaning and to refer to a graph polynomial equivalent to another graph polynomial, but deVned in another framework (representation), as a “representation” of the given graph polynomial. With this meaning, a representation of the chromatic polynomial is for example the adjoint polynomial, which is deVned as a sum over partitions and can be derived from the chromatic polynomial by replacing the falling factorials in an appropriate formulation by powers, and vice versa.

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[Ullman2012]

Ullman Foundations of Computer Science CHAPTER 9 The Graph Data Model p78

Jeffrey D. Ullman

http://infolab.stanford.edu/~ullman/

http://infolab.stanford.edu/~ullman/focs.html

http://infolab.stanford.edu/~ullman/focs/ch09.pdf

Comparison of Adjacency Matrices and Adjacency Lists
We tend to prefer adjacency matrices when the graphs are dense, that is, when the
number of arcs is near the maximum possible number, wDense and hich is n2 for a graph of n
sparse graphs nodes. However, if the graph is sparse, that is, if most of the possible arcs are not
present, then the adjacency-list representation may save space. To see why, note
that an adjacency matrix for an n-node graph has n2 bits (provided we represent
TRUE and FALSE by single bits rather than integers as we have done in this section).
In a typical computer, a structure consisting of an integer and a pointer, like our
adjacency list cells, will use 32 bits to represent the integer and 32 bits to represent
the pointer, or 64 bits total. Thus, if the number of arcs is a, we need about 64a
bits for the lists, and 32n bits for the array of n headers. The adjacency list will use
less space than the adjacency matrix if 32n+64a < n2, that is, if a < n2/64 ? n/2.
If n is large, we can neglect the n/2 term and approximate the previous inequality
by a < n2/64, that is, if fewer than 1/64th of the possible arcs are actually present.
More detailed arguments favoring one or the other representation are presented
when we discuss operations on graphs. The following table summarizes the preferred
representations for various operations.
OPERATION DENSE GRAPH SPARSE GRAPH
Look up an arc Adjacency matrix Either
Find successors Either Adjacency lists
Find predecessors Adjacency matrix Either

With adjacency lists, it takes O(1) time to find the header of the adjacency
list for u. We must then traverse this list to the end if v is not there, or half the
way down the list on the average if v is present. If there are a arcs and n nodes in
the graph, then we take time O(1 + a/n) on the average to do the lookup. If a is
no more than a constant factor times n, this quantity is O(1). However, the larger
a is when compared with n, the longer it takes to tell whether an arc is present
using the adjacency list representation. In the extreme case where a is around n2,
its maximum possible value, there are around n nodes on each adjacency list. In
this case, it takes O(n) time on the average to find a given arc. Put another way,
the denser a graph is, the more we prefer the adjacency matrix to adjacency lists,
when we need to look up a given arc.
On the other hand, we often need to find all the successors of a given node
u. Using adjacency lists, we go to successors[u] and traverse the list, in average
time O(a/n), to find all the successors. If a is comparable to n, then we find all the
successors of u in O(1) time. But with adjacency matrices, we must examine the
entire row for node u, taking O(n) time no matter what a is. Thus, for graphs with
a small number of edges per node, adjacency lists are much faster than adjacency
matrices when we need to examine all the successors of a given node.
However, suppose we want to find all the predecessors of a given node v. With
an adjacency matrix, we can examine the column for v; a 1 in the row for u means
that u is a predecessor of v. This examination takes O(n) time. The adjacency-
list representation gives us no help finding predecessors. We must examine the
adjacency list for every node u, to see if that list includes v. Thus, we may examine

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[Vallon2016]

http://blog.benoitvallon.com/data-structures-in-javascript/the-graph-data-structure/

benoit vallon

The Graph data structure

#data-structures series

Posted on February 15, 2016

A Graph data structure consists of a finite (and possibly mutable) set of vertices or nodes or points, together with a set of unordered pairs of these vertices for an undirected Graph or a set of ordered pairs for a directed Graph. These pairs are known as edges, arcs, or lines for an undirected Graph and as arrows, directed edges, directed arcs, or directed lines for a directed Graph. The vertices may be part of the Graph structure, or may be external entities represented by integer indices or references. From Wikipedia

[Vallon2016]

Adjacency list

Complexity

Adjacency list | ? | ? | ?
Storage | Add Vertex | Add Edge | Query
O(|V|+|E|) | O(1) | O(1) | O(|V|)

[Vallon2016]

Adjacency matrix:

Data are stored in a two-dimensional matrix, in which the rows represent source vertices and columns represent destination vertices. The data on the edges and vertices must be stored externally.

Complexity

Adjacency matrix | ? | ? | ?
Storage | Add Vertex | Add Edge | Query
O(|V|^2) | O(|V|^2) | O(1) | O(1)

https://visualgo.net/es/graphds?slide=1

ttps://artofproblemsolving.com/community/c163h1346740_usaco_training_riding_the_fences_adjacency_matrix_issues


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[Wagner2012]

Wagner Graph Representation.docx

Neal R. Wagner

Neal.Wagner@gmail.com

2017-09-01

http://www.cs.utsa.edu/~wagner/CS3343/newgraph/graphrep.html

[Wagner2012]

create an internal, linked list representation of an arbitrary graph

a program that will create an internal, linked list representation of an arbitrary graph. The graph can be either directed or undirected, with vertices and edges. There can be information attached to the edges as well as to the vertices.

a Java or C program that reads data about a graph (such as the one above) and constructs an adjacency list internal representation of this graph.

The example in the diagram above is a directed graph. For an undirected graph we just use a directed edge in each direction. (The graph of capitals above is undirected.) Again in the diagram above, the vertices (nodes of the graph) are represented by an array of nodes: Node [ ] graph = new Node[5];. The edges are represented by the vertices at either end; the first vertex is the vertex in the array and the second vertex is in the linked list of vertices linked to from the first vertex. It's very important to keep clear that, even though the linked list gives vertex numbers, these all represent edges. The vertices are all those at the end of a directed or undirected edge from the first vertex. These vertices in the linked list can appear in any order.

adjacency list

adjacency matrix

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[Wang2012]

Wang Large-Scale Graph Processing Algorithms on the GPU p16
Yangzihao Wang

4

adjacency matrix

The adjacency matrix is an n  n matrix where the non-diagonal entry aij is the weight value from vertex i to vertex j, and the diagonal entry aii can be used to count loops on single vertices. For most large-scale
graphs, the resulting matrix is typically sparse; representing it directly as a sparse matrix allows the use of existing libraries for sparse matrix operations such as cuSparse. Katz et al.11 represent the adjacency matrix as a 2D texture in GPU memory. The downside of such a representation is its waste of space.

adjacency lists

adjacency lists provide more compact storage for more widespread sparse graphs.

A basic adjacency list stores all edges in a graph.

One typical way of implementing it is using one array to store a list of neighbor nodes and another array to store the offset of the neighbor list for each node.

Merrill et al.12 use the well-known compressed sparse row (CSR) sparse matrix format to represent graphs in their BFS implementation.

The column-indices array C and row-offsets array R are equivalent to the neighbor nodes list and the offset list in the basic adjacency list de nition. This representation enables them to use parallel primitives such as pre x sum to reorganize sparse and uneven workloads into dense and uniform ones in all phases of graph processing. In the context of parallel BFS, parallel threads use pre x sum when assembling global edge frontiers from expanded neighbors and when outputting unique unvisited vertices into global vertex frontiers.

Jia et al.10 represent the graph as an edge list to better assign edges to threads in their centrality algorithm. Instead of using two unequal length arrays|an o set array and a neighbor list array|they use two even length arrays to store the vertex pair for each edge. Their edge-centric representation requires more GPU memory though, which could limit their application to larger graphs.

v-graph (vector graph)

Blelloch3 proposes the v-graph (vector graph) for graph data representa- tion. This representation uses segmented vectors to store graph topology. For undirected graphs, it uses a single segmented vector to store edge information. Each segment corresponds to a vertex and each element within a segment corresponds to one of the edges of that vertex. For directed graphs, it uses two segmented vectors: one for the incoming edges, and one for the outgoing edges. Each element in the outgoing edges vector is a pointer to a position in the incoming edges vector. For both directed and undirected graphs, the representation uses additional vectors to include weights and other information. A graph can be converted from most other representations into the v-graph representation by creating two elements per edge (one for each end) and sorting the edges according to their vertex number. Parallel sorting algorithms such as radix sort can be used to place all edges that belong to the same vertex in a contiguous segment. The cross-pointer array in this representation enables an O(1) step complexity of dynamic graph manipulations such as adding or deleting an edge or a vertex, which is not easily accomplished with the other representations.

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Weiss Data Structures and Algorithm Analysis in C 1994 p492

G:\studies\000Webit\000programming\ccpp

[Weiss2014]

000Weiss Data Structures and Algorithm Analysis in C++ p654

G:\studies\000Webit\000programming\ccpp

2014

p381

[Weiss2012]

Weiss Data structures and algorithm analysis in Java p636

G:\studies\000Webit\000programming\Java

p361

[Weiss2014] [Weiss2012]

Adjacency lists

Adjacency lists are the standard way to represent graphs.

There are several alternatives for maintaining the adjacency lists.

First, observe that the lists themselves can be maintained in either vectors or lists.

However, for sparse graphs, when using vectors, the programmer may need to initialize each vector with a smaller capacity than the default; otherwise, there could be significant wasted space.

Because it is important to be able to quickly obtain the list of adjacent vertices for any vertex, the two basic options are to use a map in which the keys are vertices and the values are adjacency lists, or to maintain each adjacency list as a data member of a Vertex class.

The first option is arguably simpler, but the second option can be faster, because it avoids repeated lookups in the map.

In the second scenario, if the vertex is a string (for instance, an airport name, or the name of a street intersection), then a map can be used in which the key is the vertex name and the value is a Vertex (typically a pointer to a Vertex), and each Vertex object keeps a list of (pointers to the) adjacent vertices and perhaps also the original string name.

????????????????????????????????

[wikibooks]

https://en.wikibooks.org/wiki/Data_Structures/Graphs

Adjacency List Representation

The adjacency list is another common representation of a graph. There are many ways to implement this adjacency representation.

One way is to have the graph maintain a list of lists, in which the first list is a list of indices corresponding to each node in the graph. Each of these refer to another list that stores the index of each adjacent node to this one. It might also be useful to associate the weight of each link with the adjacent node in this list.

Example: An undirected graph contains four nodes 1, 2, 3 and 4. 1 is linked to 2 and 3. 2 is linked to 3. 3 is linked to 4.

1 - [2, 3]

2 - [1, 3]

3 - [1, 2, 4]

4 - [3]

It might be useful to store the list of all the nodes in the graph in a hash table. The keys then would correspond to the indices of each node and the value would be a reference to the list of adjacent node indices.

Another implementation might require that each node keep a list of its adjacent nodes.

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[wikipedia]

https://en.wikipedia.org/wiki/Adjacency_list

Adjacency list

Implementation details

The graph pictured above has this adjacency list representation:
a | adjacent to | b, c
b | adjacent to | a,c
c | adjacent to | a,b

An adjacency list representation for a graph associates each vertex in the graph with the collection of its neighboring vertices or edges. There are many variations of this basic idea, differing in the details of how they implement the association between vertices and collections, in how they implement the collections, in whether they include both vertices and edges or only vertices as first class objects, and in what kinds of objects are used to represent the vertices and edges.

  • An implementation suggested by Guido van Rossum uses a hash table to associate each vertex in a graph with an array of adjacent vertices. In this representation, a vertex may be represented by any hashable object. There is no explicit representation of edges as objects.[1]
  • Cormen et al. suggest an implementation in which the vertices are represented by index numbers.[2] Their representation uses an array indexed by vertex number, in which the array cell for each vertex points to a singly linked list of the neighboring vertices of that vertex. In this representation, the nodes of the singly linked list may be interpreted as edge objects; however, they do not store the full information about each edge (they only store one of the two endpoints of the edge) and in undirected graphs there will be two different linked list nodes for each edge (one within the lists for each of the two endpoints of the edge).
  • The object oriented incidence list structure suggested by Goodrich and Tamassia has special classes of vertex objects and edge objects. Each vertex object has an instance variable pointing to a collection object that lists the neighboring edge objects. In turn, each edge object points to the two vertex objects at its endpoints.[3] This version of the adjacency list uses more memory than the version in which adjacent vertices are listed directly, but the existence of explicit edge objects allows it extra flexibility in storing additional information about edges.

Operations

The main operation performed by the adjacency list data structure is to report a list of the neighbors of a given vertex. Using any of the implementations detailed above, this can be performed in constant time per neighbor. In other words, the total time to report all of the neighbors of a vertex v is proportional to the degree of v.

It is also possible, but not as efficient, to use adjacency lists to test whether an edge exists or does not exist between two specified vertices. In an adjacency list in which the neighbors of each vertex are unsorted, testing for the existence of an edge may be performed in time proportional to the minimum degree of the two given vertices, by using a sequential search through the neighbors of this vertex. If the neighbors are represented as a sorted array, binary search may be used instead, taking time proportional to the logarithm of the degree.

Trade-offs

The main alternative to the adjacency list is the adjacency matrix, a matrix whose rows and columns are indexed by vertices and whose cells contain a Boolean value that indicates whether an edge is present between the vertices corresponding to the row and column of the cell. For a sparse graph (one in which most pairs of vertices are not connected by edges) an adjacency list is significantly more space-efficient than an adjacency matrix (stored as an array): the space usage of the adjacency list is proportional to the number of edges and vertices in the graph, while for an adjacency matrix stored in this way the space is proportional to the square of the number of vertices. However, it is possible to store adjacency matrices more space-efficiently, matching the linear space usage of an adjacency list, by using a hash table indexed by pairs of vertices rather than an array.

The other significant difference between adjacency lists and adjacency matrices is in the efficiency of the operations they perform. In an adjacency list, the neighbors of each vertex may be listed efficiently, in time proportional to the degree of the vertex. In an adjacency matrix, this operation takes time proportional to the number of vertices in the graph, which may be significantly higher than the degree. On the other hand, the adjacency matrix allows testing whether two vertices are adjacent to each other in constant time; the adjacency list is slower to support this operation.

Data structures

For use as a data structure, the main alternative to the adjacency list is the adjacency matrix. Because each entry in the adjacency matrix requires only one bit, it can be represented in a very compact way, occupying only |V |2/8 bytes of contiguous space, where |V | is the number of vertices of the graph. Besides avoiding wasted space, this compactness encourages locality of reference.

However, for a sparse graph, adjacency lists require less space, because they do not waste any space to represent edges that are not present. Using a na?ve array implementation on a 32-bit computer, an adjacency list for an undirected graph requires about 2(32/8)|E | = 8|E | bytes of space, where |E | is the number of edges of the graph.

Noting that an undirected simple graph can have at most |V |2/2 edges, allowing loops, we can let d = |E |/|V |2 denote the density of the graph. Then, 8|E | > |V |2/8 when |E |/|V |2 > 1/64, that is the adjacency list representation occupies more space than the adjacency matrix representation when d > 1/64. Thus a graph must be sparse enough to justify an adjacency list representation.

Besides the space trade-off, the different data structures also facilitate different operations. Finding all vertices adjacent to a given vertex in an adjacency list is as simple as reading the list. With an adjacency matrix, an entire row must instead be scanned, which takes O(|V |) time. Whether there is an edge between two given vertices can be determined at once with an adjacency matrix, while requiring time proportional to the minimum degree of the two vertices with the adjacency list.

https://en.wikipedia.org/wiki/Adjacency_matrix

adjacency matrix

For a simple graph with vertex set V, the adjacency matrix is a square |V|?×?|V| matrix A such that its element Aij is one when there is an edge from vertex i to vertex j, and zero when there is no edge.[1] The diagonal elements of the matrix are all zero, since edges from a vertex to itself (loops) are not allowed in simple graphs. It is also sometimes useful in algebraic graph theory to replace the nonzero elements with algebraic variables.[2]

The same concept can be extended to multigraphs and graphs with loops by storing the number of edges between each two vertices in the corresponding matrix element, and by allowing nonzero diagonal elements. Loops may be counted either once (as a single edge) or twice (as two vertex-edge incidences), as long as a consistent convention is followed. Undirected graphs often use the latter convention of counting loops twice, whereas directed graphs typically use the former convention.

Adjacency matrix of a bipartite graph

The adjacency matrix A of a bipartite graph whose two parts have r and s vertices can be written in the form

A = ( 0 r , r B B T 0 s , s ) , {\displaystyle A={\begin{pmatrix}0_{r,r}&B\\B^{T}&0_{s,s}\end{pmatrix}},}

where B is an r × s matrix, and 0r,r and 0s,s represent the r × r and s × s zero matrices. In this case, the smaller matrix B uniquely represents the graph, and the remaining parts of A can be discarded as redundant. B is sometimes called the biadjacency matrix.

Formally, let G = (U, V, E) be a bipartite graph with parts U = {u1, …, ur} and V = {v1, …, vs}. The biadjacency matrix is the r × s 0–1 matrix B in which bi,j = 1 if and only if (ui, vj) ∈ E.

If G is a bipartite multigraph or weighted graph then the elements bi,j are taken to be the number of edges between the vertices or the weight of the edge (ui, vj), respectively.

Variations

An (a, b, c)-adjacency matrix A of a simple graph has Ai,j = a if (i, j) is an edge, b if it is not, and c on the diagonal. The Seidel adjacency matrix is a (?1, 1, 0)-adjacency matrix. This matrix is used in studying strongly regular graphs and two-graphs.[3]

The distance matrix has in position (i, j) the distance between vertices vi and vj. The distance is the length of a shortest path connecting the vertices. Unless lengths of edges are explicitly provided, the length of a path is the number of edges in it. The distance matrix resembles a high power of the adjacency matrix, but instead of telling only whether or not two vertices are connected (i.e., the connection matrix, which contains boolean values), it gives the exact distance between them.

Data structures

The adjacency matrix may be used as a data structure for the representation of graphs in computer programs for manipulating graphs. The main alternative data structure, also in use for this application, is the adjacency list.[6] [7]

Because each entry in the adjacency matrix requires only one bit, it can be represented in a very compact way, occupying only |V |2/8 bytes to represent a directed graph, or (by using a packed triangular format and only storing the lower triangular part of the matrix) approximately |V |2/16 bytes to represent an undirected graph. Although slightly more succinct representations are possible, this method gets close to the information-theoretic lower bound for the minimum number of bits needed to represent all n-vertex graphs.[8] For storing graphs in text files, fewer bits per byte can be used to ensure that all bytes are text characters, for instance by using a Base64 representation.[9] Besides avoiding wasted space, this compactness encourages locality of reference. However, for a large sparse graph, adjacency lists require less storage space, because they do not waste any space to represent edges that are not present.[7] [10]

An alternative form of adjacency matrix (which, however, requires a larger amount of space) replaces the numbers in each element of the matrix with pointers to edge objects (when edges are present) or null pointers (when there is no edge).[10] It is also possible to store edge weights directly in the elements of an adjacency matrix.[7]

Besides the space tradeoff, the different data structures also facilitate different operations. Finding all vertices adjacent to a given vertex in an adjacency list is as simple as reading the list, and takes time proportional to the number of neighbors. With an adjacency matrix, an entire row must instead be scanned, which takes a larger amount of time, proportional to the number of vertices in the whole graph. On the other hand, testing whether there is an edge between two given vertices can be determined at once with an adjacency matrix, while requiring time proportional to the minimum degree of the two vertices with the adjacency list.[7] [10]

okokok

https://en.wikipedia.org/wiki/Degree_matrix

okokok

https://en.wikipedia.org/wiki/Graph_%28abstract_data_type%29

https://en.wikipedia.org/wiki/Incidence_matrix

Incidence matrix

In mathematics, an incidence matrix is a matrix that shows the relationship between two classes of objects. If the first class is X and the second is Y, the matrix has one row for each element of X and one column for each element of Y. The entry in row x and column y is 1 if x and y are related (called incident in this context) and 0 if they are not. There are variations; see below.

Undirected and directed graphs

An undirected graph.

In graph theory an undirected graph has two kinds of incidence matrices: unoriented and oriented.

The unoriented incidence matrix (or simply incidence matrix) of an undirected graph is a n × m matrix B, where n and m are the numbers of vertices and edges respectively, such that Bi,j = 1 if the vertex vi and edge ej are incident and 0 otherwise.

For example the incidence matrix of the undirected graph shown on the right is a matrix consisting of 4 rows (corresponding to the four vertices, 1-4) and 4 columns (corresponding to the four edges, e1-e4):

( 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 ) . {\displaystyle {\begin{pmatrix}1&1&1&0\\1&0&0&0\\0&1&0&1\\0&0&1&1\\\end{pmatrix}}.}

If we look at the incidence matrix, we see that the sum of each column is equal to 2. This is because each edge has a vertex connected to each end.

The incidence matrix of a directed graph is a n × m matrix B where n and m are the number of vertices and edges respectively, such that Bi,j = ?1 if the edge ej leaves vertex vi, 1 if it enters vertex vi and 0 otherwise (many authors use the opposite sign convention).

The oriented incidence matrix of an undirected graph is the incidence matrix, in the sense of directed graphs, of any orientation of the graph. That is, in the column of edge e, there is one 1 in the row corresponding to one vertex of e and one ?1 in the row corresponding to the other vertex of e, and all other rows have 0. The oriented incidence matrix is unique up to negation of any of the columns, since negating the entries of a column corresponds to reversing the orientation of an edge.

The oriented or unoriented incidence matrix of a graph G is related to the adjacency matrix of its line graph L(G) by the following theorem:

A ( L ( G ) ) = B ( G ) T B ( G ) ? 2 I m . {\displaystyle A(L(G))=B(G)^{T}B(G)-2I_{m}.}

where A(L(G)) is the adjacency matrix of the line graph of G, B(G) is the incidence matrix, and Im is the identity matrix of dimension m.

The discrete Laplacian (or Kirchhoff matrix) is obtained from the oriented incidence matrix B(G) by the formula

B ( G ) B ( G ) T . {\displaystyle B(G)B(G)^{T}.}

The integral cycle space of a graph is equal to the null space of its oriented incidence matrix, viewed as a matrix over the integers or real or complex numbers. The binary cycle space is the null space of its oriented or unoriented incidence matrix, viewed as a matrix over the two-element field.

Signed and bidirected graphs

The incidence matrix of a signed graph is a generalization of the oriented incidence matrix. It is the incidence matrix of any bidirected graph that orients the given signed graph. The column of a positive edge has a 1 in the row corresponding to one endpoint and a ?1 in the row corresponding to the other endpoint, just like an edge in an ordinary (unsigned) graph. The column of a negative edge has either a 1 or a ?1 in both rows. The line graph and Kirchhoff matrix properties generalize to signed graphs.

Multigraphs

The definitions of incidence matrix apply to graphs with loops and multiple edges. The column of an oriented incidence matrix that corresponds to a loop is all zero, unless the graph is signed and the loop is negative; then the column is all zero except for ±2 in the row of its incident vertex.

Hypergraphs

Because the edges of ordinary graphs can only have two vertices (one at each end), the column of an incidence matrix for graphs can only have two non-zero entries. By contrast, a hypergraph can have multiple vertices assigned to one edge; thus, a general matrix of non-negative integers describes a hypergraph.

Incidence structures

The incidence matrix of an incidence structure C is a p × q matrix B, where p and q are the number of points and lines respectively, such that Bi,j = 1 if the point pi and line Lj are incident and 0 otherwise. In this case the incidence matrix is also a biadjacency matrix of the Levi graph of the structure. As there is a hypergraph for every Levi graph, and vice versa, the incidence matrix of an incidence structure describes a hypergraph.

Finite geometries

An important example is a finite geometry. For instance, in a finite plane, X is the set of points and Y is the set of lines. In a finite geometry of higher dimension, X could be the set of points and Y could be the set of subspaces of dimension one less than the dimension of Y; or X could be the set of all subspaces of one dimension d and Y the set of all subspaces of another dimension e.

Block designs

Another example is a block design. Here X is a finite set of "points" and Y is a class of subsets of X, called "blocks", subject to rules that depend on the type of design. The incidence matrix is an important tool in the theory of block designs. For instance, it is used to prove the fundamental theorem of symmetric 2-designs, that the number of blocks equals the number of points.

okokok

https://en.wikipedia.org/wiki/Sparse_matrix

https://en.wikipedia.org/wiki/Sparse_matrix#Compressed_sparse_row_.28CSR.2C_CRS_or_Yale_format.29

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Wirth Algorithms and Data Structures p179
G:\studies\000Webit\000programming\ccpp

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Wolfram Graph Construction & Representation

????????????????????????????????????????????????????????????

Wolfram Graph Construction & Representation.docx

VertexList

EdgeList

VertexIndex

EdgeIndex

AdjacencyList

IncidenceList

EdgeRules

AdjacencyMatrix

IncidenceMatrix

KirchhoffMatrix

WeightedAdjacencyMatrix

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Wu Structural Opinion Mining for Graph-based Sentiment Representation p10


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Graph Representation
Literature Index

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Xirouhakis an efficient graph representation p6


Untitled Document

Graph Representation
Literature Index

(2017-07-01 -- 2018-07-01)

Shirley Young

https://shirleyisnotageek.blogspot.com/2015/08/graph-again-python-and-java-adjacency.html

https://plus.google.com/+ShirleyYutianYang

Yegge Get that job at Google

Wednesday, March 12, 2008

http://steve-yegge.blogspot.com/2008/03/get-that-job-at-google.html

Steve Yegge

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[Yin2004]

Yin W-graph representations for Coxeter groups and Hecke algebras p101
If W is a Coxeter group then a W graph provides a method for constructing a matrix representation of the Hecke algebra associated with W, the degree of the representation being the number of vertices of the W-graph.

Graph - 圖
https://algorithm.yuanbin.me/zh-tw/basics_data_structure/graph.html


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Literature Index

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[Zanibbi2009]

Graph Representations p2

Richard Zanibbi

rxzvcs@rit.edu (Teaching/Advising), rlaz@cs.rit.edu

[Zanibbi2009]

Adjacency Matrix

Checking if (u, v) is an edge takes Θ(1) time.
Identifying all edges takes Θ(n2) time.

[Zanibbi2009]

Adjacency List

Node indexed array of lists.
Two representations of each edge.
Space proportional to m + n.
Checking if (u, v) is an edge takes O(deg(u)) time.
Identifying all edges takes Θ(m + n) time.

deg(u) = number of neighbors of u

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[Zeps2012]
Zeps How to draw combinatorial map From graphs and edges to corner rotations and permutations p20

Dainis Zeps, Paulis Kikusts

Institute of Mathematics and Computer Science,
University of Latvia,
29 Rainis blvd., Riga, Latvia
dainize@mii.lu.lv
paulis@mii.lu.lv
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Zewi VECTOR REPRESENTATION OF GRAPH DOMINATION p21
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Zewi Vector Representation of Graph Domination p66
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Zhao Semantic Single Video Segmentation with Robust Graph Representation p7
Zhao Semantic Single Video Segmentation with Robust Graph Representation p7


def

Bed

Em(im)bed

Em(im)bedding

Graph Embedding Definitions

https://en.wikipedia.org/wiki/Graph_embedding

http://en.wikipedia.org/wiki/Graph_embedding

http://mathworld.wolfram.com/GraphEmbedding.html
A graph embedding is a particular drawing of a graph.
[Baingana2013a]
Consider a network represented by an undirected graph G = (V, E),
where E denotes the set of edges, and V the set of vertices with
cardinality |V| = N. Let ?ij denote the pairwise dissimilarity (edge
weight) between any two nodes i and j. Given the set {?ij} and
the prescribed embedding dimension p, the graph embedding task
amounts to finding p × 1 vectors {xi}N
i=1 so that the embedding
coordinates xi and xj satisfy kxi - xjk2 ? ?ij .
[Baingana2013b]
    Given a graph whose vertices represent entities in a system, and edges capture interactions between them,graph embedding associates each vertex with a set of coordinates in low-dimensional Euclidean space.
[Belkin2001]

The embedding maps for the data come from approximations to
a natural map that is defined on the entire manifold.

More generally, the embedding of the graph into lR!.m (m > 1) is given
by the n x m matrix Y = [Y1Y2 ... Yml where the ith row, denoted by Yl, provides
the embedding coordinates of the ith vertex.
[Brink2005]
[CHARTRAND2009]
A graph G is called a planar graph if G can be drawn in the plane without
any two of its edges crossing. Such a drawing is also called an embedding of G in
the plane.

[Conte2013]
Graph embedding methods map either explicitly or implicitly graphs into high dimensional spaces hence allowing to perform the basic mathematical computations required by various statistical pattern recognition techniques.

[Cooley2009]

In this case, we again aim to embed a graph H into a graph G, but now the order of H might be linear in n = |G| rather than fixed.

We could view the problem of finding a perfect H-packing as an embedding problem:
[Ebner2005]
There is an infinite number of different drawings of a planar graph, nevertheless they can be divided into a finite set of equivalence classes of drawings called the embeddings of a graph.
[Gibert2011]

Formally, a graph embedding is a mapping from the set of graphs to a vectorial space
Assign a feature vector to every graph
vectorial representation of the graph Gk
[He2009]
Given a graph G with m vertices, each vertex represents a data point. Let W be a a symmetric m × m matrix with
Wij having the weight of the edge joining vertices i and j. The G and W can be defined to characterize certain statistical or geometrical properties of the data set. The purpose of graph embedding is to represent each vertex of the graph as a low dimensional vector that preserves similarities between the vertex pairs, where similarity is measured by the edge weight.
[Horaud2009]
Embed the graph in a k-dimensional Euclidean space. The
embedding is given by the n  k matrix F = [f1f2 : : : fk]
where the i-th row of this matrix { f(i) { corresponds to the
Euclidean coordinates of the i-th graph node vi.
[Jouili2010]
Recently, a few works have been carried out concerning the bridging of this
gap between structural and statistical approaches. Their aim is to delineate a
mapping between graphs and real vectors, this task is called graph embedding.
[Kermarrec2011]
Consider G(V;E), an undirected graph of n = jV j nodes
representing a distributed system. Let P be the host space
and let dimP = d. A graph embedding is a mapping of the
graph vertices to positions in the host space. In other words,
each vertex gets assigned to a point in the host space.
[Kocay2003]
Given a graph G and a topological surface S , we ask whether it is possible to draw the graph on the surface without edge crossings. Such a drawing of G on the surface is called an embedding of G in S.
[Kocurova2007]

[Krug2015]
An embedding E(G) of a graph G is a cyclic order of the edges around each vertex, which describes the topology of
the graph.
[Liu2010]
As stated in [31], most conventional
algorithms for feature extraction can be unified within a framework
called graph embedding [31], and the certain purpose of
a specific algorithm is characterized by the so-called intrinsic
and penalty graphs.
[LUQMAN2012]
Definition 14: Graph Embedding (GEM)
Graph Embedding is a methodology aimed at representing a whole graph (with attributes
attached to its nodes and edges) as a point in a suitable vector space; preserving
the similarity/distance between the graphs that have been embedded i.e. the more two
graphs are considered similar, the closer should be the corresponding points in the vector
space.
[Matsubayashi2014]

We study the problem of embedding a guest graph with minimum edge-congestion into
a multidimensional grid with the same size as that of the guest graph.

The graph embedding of a guest graph into a host graph is to map (typically oneto-
one) nodes and edges of the guest graph onto nodes and paths of the host graph,
respectively, so that an edge of the guest graph is mapped onto a path connecting the
images of end-nodes of the edge. The graph embedding problem is to embed a guest graph into a host graph with certain constraints and/or optimization criteria.
[MOHAR1999]
An embedding of a connected graph G is a pair ? = (?, ?) where ? is
a rotation system and ? is a signature. Having an embedding ? of G, we say that
G is ?-embedded. If H is a subgraph of G, then the induced embedding of H (or the
restriction of ? to H) is obtained from that of G by ignoring all edges in E(G)\E(H)
and by restricting the signature to E(H).
[Newsome2003]
Graph embedding is a technique in graph theory in which
a guest graph G, is mapped into a host graph H.
[Ou1997]
Recently, the graph embedding paradigm [35] is proposed
to represent vertices of a graph in a low-dimensional vector
space while the structures (i.e. edges and other high-order
structures) of the graph can be reconstructed in the vector
space.
[Potoczak2014]
Two topological spaces are said to be homeomorphic or topologically equiva-
lent if there exists a homeomorphism between the spaces (Figure 1.5). Continuous
functions can also be used to study how one topological space sits within another
topological space. This is accomplished via a function called an embedding.

In topological graph theory, the graph is treated as a topological space which
allows for the study of embedding graphs into topological spaces. In particular,
topological graph theory is concerned with embedding graphs into compact surfaces.
In the Topological Graph chapter, some results regarding graph embeddings are
explored.

Let X and Y be topological spaces. Recall, an embedding of X in Y is a function
f : X ! Y that maps X homeomorphically to the subspace f(X) in Y .

Here it
is of interest to embed topological graphs into compact surfaces. An embedding of
a graph G into a surface S can be considered to be a picture of the graph on the
surface such that edges in f(G) only intersect in shared vertices and do not intersect
in any other way.
[Rajan2015]

Graph embedding is an important technique that maps a logical graph into a host graph, usually an interconnection network.

De nition 2.1 [2] Let G and H be nite graphs. An embedding of G into H is a pair (f; Pf ) de ned as follows:
1. f is a one-to-one map from V (G) ! V (H)
2. Pf is a one-to-one map from E(G) to fPf (u; v) : Pf (u; v) is a path in H between f(u) and f(v) for (u; v) 2 E(G)g:
For brevity, we denote the pair (f; Pf ) as f.
[Riesen2009]

The overall objective of all graph embedding
techniques is to condense the high representational power of graphs into a
computationally efficient and mathematically convenient feature vector.

From another perspective, graph embeddings can be viewed as an
extraction of descriptive numerical features from graphs.

Definition 6.1 (Graph Embedding).
[Robles-Kelly2007]
The problem of embedding relational structures onto a
Riemannian manifold for the purposes of representation
or visualisation is an important one in computer science
which arises in parameterisation of three-dimensional data
[1], multidimensional scaling (MDS) [2] and graph drawing
[3]. In general, this problem is clearly one of a combinatorial
nature which has been traditionally solved by viewing
the edge-weights for the graph as distances between
pairs of nodes. The embedding coordinates are then those
[Rodl1999]
[Saxe1980]
This report contains two Independent papers on problems concerned with graph
embedding—I.e., assignment of the vertices of a graph to points In a metric space
s u b j e c t to specified constraints.
[Shaw2011]

Formally the problem of graph embedding can be stated as follows: given a graph G = (V;E)
with n = |V| ?nodes and |E| edges, find for each node a vector yi ? Rd for i = 1; : : : ; n.
In this thesis we focus on low-dimensional embeddings where d is small.

Graph embedding algorithms place vertices at points on a surface, typically Euclidean space, and connect vertices with an arc if the vertices have an edge between them.

drawing graphs so that they have certain aesthetic qualities to embedding graphs in VLSI chip designs to minimize fabrication cost [Chung, 1997, Battista et al., 1999]

graph embedding algorithms suited for dimensionality reduction, visualization, and metric learning
[Shaw2009]
Graph embedding algorithms place nodes at points
on some surface (e.g. Euclidean space) and connect
points with an arc if the nodes have an edge between
them.
[Simonraj2012]
An embedding from G to H is defined [2] as follows.
1. f is a bijective map from V(G)  V(H)
2. f is a one to one map from E(G) to { Pf ( f(u) , f(v)) : Pf ( f(u) , f(v)) is a path in H between f(u) and f(v) }.
[Song2012]
A graph embedding can bemathematically formalized as the decomposition
[Stefano2012]
[Valveny2015]
A graph embedding is a maping from the set of graphs to a vectorial space.
[VITCC2013]
[Yan2007]

the graph embedding framework can be used as a general platform for developing new dimensionality reduction algorithms.

Graph Embedding is a general framework for dimensionality reduction (DR) With it’s linearization, kernelization, and tensorization, we have a unified view for understanding DR algorithms. GE can be used as a platform for developing new DR algorithms.

graph embedding, along with its linearization, kernelization, and tensorization, that offers a unified view for understanding and explaining many of the popular dimensionality
reduction algorithms such as the ones mentioned above.

The purpose of direct graph embedding is to represent each vertex of a graph as a low-dimensional vector that preserves similarities between the vertex pairs, where similarity is measured by a graph similarity matrix that characterizes certain statistical or geometric properties of the data set. The vector representations of the vertices can be obtained from the eigenvectors corresponding to the leading eigenvalues of the graph Laplacian matrix with certain constraints. While direct graph embedding only presents the mappings for the graph vertices in the training set, its extensions provide mappings for all samples, such asnewtest data, in the original feature space. The linearization of graph
embedding assumes that the vector representation of each vertex is linearly projected from the original feature vector representation of the graph vertex and the kernelization of graph embedding applies the kernel trick on the linear graph embedding algorithm to handle data with nonlinear distributions. Finally, in the tensorization of graph embedding,
the original vertex is encoded as a general tensor of arbitrary order and the multilinear algebra approach is applied to extend the direct graph embedding to multilinear cases based on tensor representations.

Graph embedding of G is an algorithm to find low-dimensional vector representations relationships among the vertices of G .

the graph embedding of the graph G is defined as an algorithm to find the desired low-dimensional vector representations relationships among the vertices of G that best characterize the similarity relationship between the vertex pairs in G.

In graph embedding, each algorithm can be considered as the direct graph embedding or its linear/kernel/tensor extension of a specific intrinsic graph that describes certain desired statistical or geometric properties of a data set, with constraints from scale normalization or a penalty graph that characterizes a statistical or geometric property that should be avoided. Furthermore, the graph embedding framework can be used as a general platform for developing new dimensionality reduction algorithms.
[Yang2008]

Although varieties of dimensionality reduction algorithms [2][3][6] have been proposed in pattern recognition, Yan et al. claimed that most of them, such as Principal Component Analysis (PCA) [7][14], LDA [1][12] and the recently proposed Marginal Fisher Analysis (MFA) [17], can be unified with a general formulation, called graph embedding [17].

Despite the different motivations of different algorithms for dimensionality reduction, Yan et al. [17] claimed that most of them can be explained within a unified framework,called graph embedding.
[Yu2016]
Embedding a graph G on a surface is to draw each vertex of G as a point and each edge between two
vertices as a curve connecting the points of the two vertices on the surface. Graph G is embeddable
on a surface if G can be drawn on the surface in such a way that no two edges cross.
[Yu2014]
A graph G is embedded on a surface S if it is drawn on S so that the edges are pairwise disjoint except at their common ends. The drawing of G is an embedding of G on S.
[Zhao2013]

The problem of embedding relational structures onto a manifold arises in parameterization of threedimensional data [1], multidimensional scaling (MDS)[2], graph drawing [3] and structural graph matching [4].

In the pattern analysis community, there has recently been renewed interest in using embedding methods motivated by graph theory for representation, classification, retrieval or visualisation.

Embedding methods can also be used to transform the relational-matching problem into one of point-pattern matching in a high-dimensional space. The problem is to find matches between pairs of point sets when there is noise, geometric distortion and structural corruption.

Thus, given the coordinates in <n for all the nodes in the graph-set ?? the purpose is
to find a transformation matrix F 2<nd that projects the input vectors for the nodes in the graph onto the submanifold U!i such that Y = FX belongs to a lower dimensional space <d(d 6 n) maximising the separation between classes in and the affinity within classes.
[Zhou2000]
An embedding of G on H is an injection  from V(G) to V(H), and this can be viewed as a layout of G on H.

embedding space

?

Hypergraph Embeddings

[Cooley2009]

Broadly speaking, we consider the problem of embedding a hypergraph H into a larger hypergraph G, i.e. of finding a subhypergraph of G which is isomorphic to H.


Untitled Document

Geometric Graph Theory
[Pach2013]

Geometric graphs are graphs drawn in the plane with possibly crossing straight-line edges. Here we take a narrower view: by a geometric graph we mean a graph G drawn in the plane with possibly intersecting straight-line edges.

The term “geometric graph theory” is often used to refer to a large, amorphous body of
research related to graphs defined by geometric means. We use the term geometric graph theory as a short form for “the theory of geometric and topological graphs.”
[Toth2013]

A geometric graph is G = (V;E),
V =set of points in the plane,
E =set of line segments between points in V .

Fary (1957): Every planar graph has an embedding in the plane as a geometric graph.

Geometric Graph Theory

okokok
>>> 0000Geometric Graph Theory
[Pach2013] The Beginnings of Geometric Graph Theory p20

okokok
>>> 0000Geometric Graph Theory

[Toth2013] Universality in Geometric Graph Theory p96.pdf????????????????


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?

?graph compilation?

[Alcazar2011]
SAT compilation for the landmark graph.

[Ciricescu2003]

[Kelly2006]

Our implementation uses a dataflow execution model, and includes a compiler to build dataflow graphs from XSLT source code.
This paper describes the execution model used to obtain parallelism and compose web services, as well as the compilation process used to create the dataflow graphs.
The program is first compiled into a set of static graphs, each of which corresponds to a block of code within the program, such as a function, template, or loop body.
The static graphs from which the activities are instantiated are built by the compiler from the XSLT source.
The compilation process, described in Section 5, parses the source code and builds the static graphs from which the
runtime activities are instantiated. A program is passed to the dataflow execution engine in the form of a set of static
graphs, with one marked as the initial graph. This is like the main function in C; it is instantiated first, and from
there it makes calls to other functions which get activated as described above.

graph compilation

okokok
[Alcazar2011] A SAT Compilation of the Landmark Graph p8

okokok
[Kelly2006] Compilation of XSLT into Data ow Graphs forWeb Service Composition p9


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graph construction

[Hong2000]

[Wang2012]
Given a data set X, graph construction aims in converting the data to a weighted graph G = {X,E,W} where graph nodes are the samples and W ? Rn×n is a weight matrix of edges E.

graph construction

okokok
[Hong2000] Graph Construction and Analysis as a Paradigm for Plan Recognition p6

okokok
Khoreva Classifier Based Graph Construction for Video Segmentation p10

okokok
[Kim2009] Degree-based graph construction p12

okokok
[Liu2010] Large Graph Construction for Scalable Semi-Supervised Learning p8

okokok
MIZUNO The construction of a regular graph p31

okokok
Musco Graph Construction Through Laplacian Function Optimization p32

okokok
Saito Lecture 10: Graph Construction from Given Datasets p93

[Wang2012] Fast Graph Construction Using Auction Algorithm p10


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graph creating

graph creating

Kumar Creating Graph Abstractions for the Interpretation of Combined Functional and Anatomical Medical Images p10

Posner Creating a Network Graph with Gephi p16


Untitled Document

[Baingana2013b]

[BARAHIMI2015]
The academic efforts on graph drawing are usually separated into two categories. The first category is to determine algorithms to lay out graphs with respect to some criteria such as area, volume,? number of crossings, symmetry, etc. The second category is to develop software systems that allow visualization and manipulation of graphs or implementation of layout algorithms.

Graph drawing adds geometrical properties to the graphs making it a more structured model.

[Battista1994]
A graph drawing algorithm reads as input a combinatorial description of a graph G, and produces as output a drawing of G according to a given graphic standard.

[Bridgeman2002]
The goal of a graph drawing algorithm is to assign geometry to the graph so as to produce a drawing or layout
[Chowdhury2010]

A drawing of a graph is a sort of visualization of information represented by that graph. The field in which the different aesthetic techniques of drawing graphs are vividly described is “Graph Drawing”.

In the field of graph drawing, the geometric representations of graphs generated by graph drawing algorithms are constrained by some predefined geometric or aesthetic properties.
[Baingana2013a]
[Eades2004]
A graph drawing algorithm reads as input a combinatorial description of a graph, and produces as output a visual representation of the graph. Such algorithms aim to produce drawings which are easy to read and easy to remember.
[Klau1997]

The field of Automatic Graph Drawing provides algorithms to construct geometric representations of the underlying graph structures.

An undirected graph is planar if it is embeddable in the plane, i.e., if it is possible to map its vertices to distinct points in R2 and the edges to non crossing Jordan curves connecting their endpoints. Such a mapping is called a planar geometric embedding or simply an embedding when this causes no confusion.

?
[Eades2004]
A graph drawing algorithm reads as input a combinatorial description of a graph, and produces as output a visual representation of the graph. Such algorithms aim to produce drawings which are easy to read and easy to remember.

[Eades2012]
A graph drawing is a picture of a graph. That is, a graph drawing is a mapping that assigns
? a location for each node, and
? a curve to each edge.

[El-Sayeda2011]
Graph drawing addresses the problem of finding a layout of a graph that satisfies given aesthetic and understandability objectives. The most important objective in graph drawing is minimization of the number of crossings in the drawing, as the aesthetics and readability of graph drawings depend on the number of edge crossings.

[Freeman2003]
An embedding of a graph in a surface is a drawing of the graph onto some surface so that there are no edge-crossings.

[Harel2004]
Graph drawing is a standard means for the visualization of relational information, and its ultimate usefulness depends on the readability of the resulting layout; that is, the drawing algorithm’s capability of conveying the meaning of the diagram quickly and clearly.

?
[Klau1997]

The field of Automatic Graph Drawing provides algorithms to construct geometric representations of the underlying graph structures.

An undirected graph is planar if it is embeddable in the plane, i.e., if it is possible to map its vertices to distinct points in R2 and the edges to non crossing Jordan curves connecting their endpoints. Such a mapping is called a planar geometric embedding or simply an embedding when this causes no confusion.

[Mumford2008]
For a graph to be able to serve its purpose as an information carrier it has to be visualized. Moreover, it has to be visualized such that it conveys the information in the best possible way. Graph drawing [2] is a branch of computer science that concentrates on developing algorithms for visualizing graphs. That is, graph drawers develop algorithms that produce drawings of graphs that satisfy certain aesthetic criteria. These criteria are often expressed in properties like edge complexity, number of edge crossings, angular resolution, number of edge directions, shapes of faces, graph symmetries, or the aspect ratio of a drawing. Some of these criteria are application-specific. For example, graphs that represent metro maps are usually drawn using a limited number of edge directions—see, for example, [40, 51, 54]. When drawing such a map one has to balance between drawing the map exactly as it looks in reality (which would produce a map cluttered with unnecessary details) and simplifying the map beyond recognition. Limiting the number of edge directions allows us to depict a metro map such that the map looks simple enough and is easy to follow, but still resembles the original layout of the network.

Other criteria are more general—they aim at improving the readability of any graph drawing. An example of such a criterion is the number of edge crossings of a graph. Unless crossings of a graph are part of the information conveyed by it—such as a crossing in a map representing a highway overpass—we would like to have as few crossings as possible,
because edge crossings in general make a graph cluttered and unreadable. Another example of a general criterion is edge complexity—edges with too many bends are hard to follow. Most of the graph-drawing problems have to deal with satisfying a combination of criteria. For instance, in VLSI design the drawings are required to use two perpendicular directions for their edges and have as few edge bends and edge crossings as possible.

Problems in graph drawing are often of combinatorial and/or geometric nature, hence the methods for solving these problems come from a variety of areas such as computational geometry, graph theory, and (computational) topology.

[Samaranayake2008]
Graph drawing algorithms will take these nodes and edges and represent them in an aesthetically pleasing graphical manner.

[Siebenhaller2009]
Graph drawing, as a branch of graph theory, deals with the design and implementation of automatic layout algorithms for generating readable drawings (diagrams) of graphs. Graphs are usually drawn on a plane using points or rectangles to represent vertices and lines to represent edges.

[Tamassia1994]
A natural representation of graphs is via geometric shapes placed in the plane with adjacencies determined by certain geometric properties such as visibility or distance.

[Wood2005]
graph drawing—automatic production of ‘nice’ drawings of graphs

[Zhao2013]
[Samaranayake2008]
Graph drawing algorithms will take these nodes and edges and represent them in an aesthetically pleasing graphical manner.
[Zhao2013]

graph drawing

okokok
Alshayji Force Directed Algorithm p25.ppt

4/28/2005

okokok
[BARAHIMI2015] WEB-BASED DRAWING SOFTWARE FOR GRAPHS IN 3D AND TWO LAYOUT ALGORITHMS p72
FARSHAD BARAHIMI
2015

okokok
[Battista1994] Algorithms for Drawing Graphs: an Annotated Bibliography p44
Giuseppe Di Battista

okokok
Chiba Drawing Plane Graphs Nicely p15
Norishige Chiba
1985

okokok
[Eades2012] How to Draw a Graph Revisited p191

[Bridgeman2002] Techniques and Tools for Graph Drawing p168
by Stina Bridgeman, Ph.D., Brown University,
May 2002.

okokok
[Eades2004] Straight-Line Drawing Algorithms for Hierarchical Graphs and Clustered Graphs p34
Peter Eades
November 25, 2004

okokok
Eades Symmetric Graph Drawing p28

okokok
[El-Sayeda2011] Study of Neural Network Algorithm for Straight-Line Drawings of Planar Graphs p7
Mohamed A. El-Sayeda

okokok
Feng Coherent Time-Varying Graph Drawing with Multifocus Context Interaction p12
Kun-Chuan Feng
2011

okokok
[Freeman2003] DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177
Andre Freeman
2003

okokok
FRUCHTERMAN Graph Drawing by Force-directed Placement p36
THOMAS M. J. FRUCHTERMAN
1991

Godiya Rapid Multipole Graph Drawing on the GPU p12

okokok
[Harel2004] Graph Drawing by High-Dimensional Embedding p20

okokok
Kant Algorithms for Drawing Planar Graphs p237
1993

okokok
[Klau1997] Quasi–Orthogonal Drawing of Planar Graphs p15
Gunnar W. Klau? ?Petra Mutzel

okokok
[Krug2015] New Approaches on Octilinear Graph Drawing p165
2015

okokok
M?kinen GENETIC ALGORITHMS FOR DRAWING BIPARTITE GRAPHS p15
Erkki M?kinen and Mika Sieranta
1994

okokok
[Mumford2008] Drawing Graphs for Cartographic Applications p144
2008

okokok
Radwan Hybrid GA for Straight-Line Drawings of Level Clustered Planar Graphs p7
Ahmed A. A. Radwan
2011

okokok
Ruegg Using One-Dimensional Compaction for Smaller Graph Drawings p23
Ulf Ruegg
2016

okokok
[Samaranayake2008] Force Directed Graph Drawing Algorithms for Macro Cell Placement p6
Meththa Samaranayake , Helen Ji and John Ainscough

okokok
[Siebenhaller2009] Orthogonal Graph Drawing with Constraints: Algorithms and Applications p222

okokok
Sim Automatic Graph Drawing Algorithms p16.pdf

okokok
[Tamassia1994] Graph Drawing p10
1994

okokok
[Wood2005] Drawings of Graphs in Two and Three Dimensions p53
David Wood
2005


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graph encoding

[Baingana2013b]

Graphs are a versatile tool for encoding different kinds of network data arising in a broad
class of complex systems.

the graph encodes data sampled from a low-dimensional manifold.
[Baingana2013a]

graph encoding

Chen Graph Encoding and Transitive Closure Representation p3

okokok
Dagstuhl Graph encoding: an overview p24
21 april 2009

Das Succinct Encodings of Graph Isomorphism p17
Bireswar Das

Ionicioiu Encoding graphs into quantum states: an axiomatic approach p33
Radu

Pouly A Modeling and Encoding Method for Relative Layout Generation and Optimization in Manufacturing p34
Marc

SCHIANO Structure and strategy in encoding simplified graphs p9
DIANE J.

Urbania KOGNAC: Efficient Encoding of Large Knowledge Graphs p8
Jacopo Urbania, Sourav Duttab, Sairam Gurajadab, and Gerhard Weikumb
2


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Graph Extractor??????

[Atkinson2004]
A useful analysis is the extraction of the call graph of a program. The call graph is simply a visual representation of
the calling relationships between functions or procedures. Each function is represented as a graph node.
If function a calls function b then a ! b is an edge in the graph. Thus, the call graph can be used to determine which functions are called by a particular function, as well as which functions call a particular function.

[Leskovec2008]
Generate graphs recursively

[Paulino2011]
dynamic graph discovery?????????

?
[Vallerio2007]
This work differs from related work since it is the only work to generate task graphs from C.
Our work aims to reduce both of these problems by automatically extracting task graphs from C specifications.

Graph Extractor / Graph Extraction

[Atkinson2004] Accurate Call Graph Extraction of Programs with Function Pointers Using Type Signatures p10

okokok
[Vallerio2007] Task Graph Extraction for Embedded System Synthesis p7


Untitled Document

Graph Generation

Graph Generation

Definitions

[Ashish2016]

Modular Random Task Graph generator (MRTG)

MRTG primarily generates a specified number of random isometric task graphs, where the graph nodes are tasks and the graph edges depict the communication between tasks.

Task Graphs for Free (TGFF)

Graph Generation for Scheduling Simulations (GGEN)

Random Task and Resource Graphs (RTRG)

[Coxon2013]

The use of random graph generators is mostly used for generating graphs for the testing
of algorithms[11].

The aim of the project is to research current graph generators, provide a method to generate random graphs where a user can design the `shape' of graph, and nally to provide a sample computer program that applies this algorithm.

Random graph generators are systems to generate a single or set of graphs based on some
non-deterministic rules.

In order to generate random graphs we can study Ranjan's approach to graph genera tion. Ranjan [9] describes a method of generating a random sequence of productions over a graph grammar G which can then be run to generate a single random graph.

Hickey-Cohen Generation of Hypergraphs

[Cullum2006]

CAULDRON, an attack graph generation tool developed at George Mason University

CAULDRON uses externally provided network vulnerability scan reports of a given network as well as exploit models and detailed attack scenarios to automatically generate attack graphs depicting all known combinations of vulnerabilities that could be systematically exploited by an attacker to reach an attack goal on that network [Jaj03].

AUTOMATED ATTACK GRAPH GENERATION TOOLS

  • CMU - Attack Graph Toolkit
  • MIT Lincoln Laboratory – NetSPA
  • Skybox - Skybox View

CMU - Attack Graph Toolkit
The “Attack Graph Toolkit”, created by researchers at Carnegie Mellon University,

Network Security Planning Architecture (NetSPA)

Network vulnerability scanners

[EVERETS2005]
It is this LST file which is manipulated by the tools to generate control flow graphs and provide alternate representations of the assembly programs.
The Graph Generation Tools & Library creates the Control Flow Graph representation of the assembly language program. It is used for visualization of the operation of the code, as well as manipulation of the resulting graphs in order to perform extended data mining and information retrieval from the patterns therein.
Control Flow Graph Generation is performed by the Lst2Gxl program, which reads in an assembly LST file, and converts that to an internal representation of a control flow graph, then into a GXL representation of that graph. This is performed by evaluating each instruction from the LST file, and determining the possible next instructions that could be executed based on the instruction type and the operands of that instruction. Currently this is done in a mostly-static fashion.

[Ingols2006]

We have created a new type of attack graph, themultiple-prerequisite graph, that scales nearly linearly as the size of a typical network increases.

NetSPA

It rapidly generates an attack graph showing how an attacker can maximally compromise the targeted network. The tool can model an attacker able to start from any IP address,
maximally exploiting any special “holes” in the perimeter firewalls. Our system builds multiple-prerequisite graphs, orMP graphs, which are faster to build and have greater expressive
power than our previous work’s predictive graphs [17, 18]. MP graphs are able to model portable credentials, such as passwords, which an attacker can use from anywhere to compromise a target. MP graph construction is substantially faster than all other published attack graph results of which we are aware [19, 25].

We have implemented a working prototype in Perl and C++ that is capable of automatically computing reachability from readily available source data, generating an MP graph, analyzing it, and producing the graph and recommended actions as output.

NetSPA must derive a few core pieces of knowledge to build an attack graph. For a given host, the tool must know which ports the host can reach. For each instance of a vulnerability,
the tool must know what is required to exploit it and what is gained by exploiting it.

[Jeon2015]
TeGViz, a distributed Terascale graph generation and visualization tool

【Johnsonbau】

Richard Johnsonbaugh

Martin Kalin

Department of Computer Science and Information Systems
DePaul University
Chicago, IL 60604

johnsonbaugh@depaul.edu

kalin@depaul.edu

[Kang1994]
Our approach is to develop a technique for generating the finite representation of the reachable states (called a timed reachability graph) for a real-time system by clustering a possibly infinite set of states that share reachability and timing properties
In our approach, the timed reachability graph consists nodes corresponding to reachable states and edges corresponding to transitions in a timed automaton.

[Leist2011]

Graph500 benchmark formulation

Parallel graph generation

[Miyazaki2004]

learning method for generating a representative graph of a set of graphs by constructing graph unions with merging corresponding vertices and edges.

We generate the representative graph from a set of graphs.

Therefore, we form a representative graph by making graph union.

[Namouz2014]
methods of part connection graph (part connectivity graphs) generation for input into the complexity connectivity method to estimate the assembly time of a product.
The Assembly Mate Method (AMM) uses SolidWorks (SW) assembly mate information to create the connectivity graphs needed for the complexity connectivity method.
Another method for generating the complexity graphs has been developed that uses part interference to create the complexity graphs.

?

[Nobari2011]

[Sorensen2003]

generating a graph that provides a good representation of the navigable space in a maze.

[Toma2015]

[Wardhana2011]
we propose an algorithm to automatically generate an enhanced waypoint graph which is capable of planning volumetric paths for characters with various sizes.

[Winlaw2015]

graph generators

?
[Ying2009]

Graph generation for privacy preserving social network publishing

The algorithm uses a Markov chain to generate a random graph.

Literature

Ahmad A Technique for Reachability Graph Generation for the Petri Net Models of Parallel Processes p5

APPENDIX B GRAPH GENERATION AND COMPLEXITY MEASURES p8

okokok

[Ashish2016] A Modular Approach to Random Task Graph Generation p7

[Bader2006] GTgraph: A Synthetic Graph Generator Suite p4

Bailey Automatic Generation of Graph Models for Complex Networks by Genetic Programming p8

Cordeiro Random graph generation for scheduling simulations p10

okokok

[Coxon2013] Uniform Random Generation of Graphs with Graph Grammars p50

okokok

[Cullum2006] PERFORMANCE ANALYSIS OF AUTOMATED ATTACK GRAPH GENERATION SOFTWARE p159

okokok
ESTERLE Socio-Economic Vision Graph Generation and Handover in Distributed Smart Camera Networks p24

okokok
[EVERETS2005] ASSEMBLY LANGUAGE REPRESENTATION AND GRAPH GENERATION IN A PURE FUNCTIONAL PROGRAMMING LANGUAGE p108
Kevin Everets, January 13, 2005

okokok
[Jeon2015] TeGViz: Distributed Tera-Scale Graph Generation and Visualization p4

okokok
[Kang1994] An Efficient Generation of the Timed Reachability Graph for the Analysis of Real-Time Systems p23

okokok
[Leskovec2008] Kronecker graph p37

okokok
[Namouz2014] Comparison of Graph Generation Methods for Structural Complexity Based Assembly Time Estimation p28

[Wardhana2011] Automatic Generation of Enhanced Waypoint Graph for Volumetric Path Planning p6

okokok
ESTERLE Socio-Economic Vision Graph Generation and Handover in Distributed Smart Camera Networks p24

okokok
[EVERETS2005] ASSEMBLY LANGUAGE REPRESENTATION AND GRAPH GENERATION IN A PURE FUNCTIONAL PROGRAMMING LANGUAGE p108
Kevin Everets, January 13, 2005

[EVERETS2005]
It is this LST file which is manipulated by the tools to generate control flow graphs and provide alternate representations of the assembly programs.
The Graph Generation Tools & Library creates the Control Flow Graph representation of the assembly language program. It is used for visualization of the operation of the code, as well as manipulation of the resulting graphs in order to perform extended data mining and information retrieval from the patterns therein.
Control Flow Graph Generation is performed by the Lst2Gxl program, which reads in an assembly LST file, and converts that to an internal representation of a control flow graph, then into a GXL representation of that graph. This is performed by evaluating each instruction from the LST file, and determining the possible next instructions that could be executed based on the instruction type and the operands of that instruction. Currently this is done in a mostly-static fashion.

[Jeon2015]
TeGViz, a distributed Terascale graph generation and visualization tool

[Kang1994]
Our approach is to develop a technique for generating the finite representation of the reachable states (called a timed reachability graph) for a real-time system by clustering a possibly infinite set of states that share reachability and timing properties
In our approach, the timed reachability graph consists nodes corresponding to reachable states and edges corresponding to transitions in a timed automaton.

[Namouz2014]
methods of part connection graph (part connectivity graphs) generation for input into the complexity connectivity method to estimate the assembly time of a product.
The Assembly Mate Method (AMM) uses SolidWorks (SW) assembly mate information to create the connectivity graphs needed for the complexity connectivity method.
Another method for generating the complexity graphs has been developed that uses part interference to create the complexity graphs.

?

[Wardhana2011]
we propose an algorithm to automatically generate an enhanced waypoint graph which is capable of planning volumetric paths for characters with various sizes.

?

Fernandez Minimal State Graph Generation p20

okokok

[Ingols2006] Practical Attack Graph Generation for Network Defense p10

okokok
[Jeon2015] TeGViz: Distributed Tera-Scale Graph Generation and Visualization p4

okokok

【Johnsonbau】 A Graph Generation Software Package p4

okokok
[Kang1994] An Efficient Generation of the Timed Reachability Graph for the Analysis of Real-Time Systems p23

Lampka MTBDD-based Activity-Local State Graph Generation p4

Lampka Symbolic Activity-Local State Graph Generation in the Context of Mobius p11

okokok

[Leist2011] Graph Generation on GPUs using Dynamic Memory Allocation p7

okokok
[Leskovec2008] Kronecker graph p37

Leskovec Realistic, Mathematically Tractable Graph Generation and Evolution, Using Kronecker Multiplication p12

okokok

[Miyazaki2004] Representative Graph Generation for Graph-Based Character Recognition p9

okokok
[Namouz2014] Comparison of Graph Generation Methods for Structural Complexity Based Assembly Time Estimation p28

okokok

[Nobari2011] Fast Random Graph Generation p12

Ou A Scalable Approach to Attack Graph Generation p10

Schluter Effects of Graph Generation for Unsupervised Non-Contextual Single Document Keyword Extraction p7

Ryszka GraphTool - a new System of Graph Generation p5

?????????????????????????

[Sorensen2003] Safe-Path Graph Generation for Path Planning in Urban Environments p6

okokok

[Toma2015] A Dependency Graph Generation Process for Client-side Web Applications p13

VanHorn A Random Graph Generator p6

okokok

[Wardhana2011] Automatic Generation of Enhanced Waypoint Graph for Volumetric Path Planning p6

okokok

[Winlaw2015] A Clustering Graph Generator p16

okokok

[Ying2009] Graph Generation with Prescribed Feature Constraints p12

Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15


Untitled Document

?

?

graph layouts
[Baingana2013b]
Concentric graph layouts

Diaz2000]

A linear layout or simply layout is also called linear ordering, linear arrangement, numbering, labeling and is a bijective function V -> [n] = {1,2, ... ,n}

[anoop2013]
Graph Layout Problems are a particular class of optimization problems whose goal is to find a layout of an input in such a way that a certain objective is optimized.

[Baingana2013b]
Concentric graph layouts

[Diaz2000]
A linear layout or simply layout is also called linear ordering, linear arrangement, numbering, labeling and is a bijective function V -> [n] = {1,2, ... ,n}

[Dujmovic2003]
Graph drawing addresses the problems of characterizing the existence of such drawings and layouts, as well as developing algorithmic techniques for their automatic generation.

[Fellows2008]
In a graph layout problem, we are given a graph G = (V;E) as input and asked to find a permutation : V ! f1; 2; : : : ; ng that minimizes a certain problem specific objective function of .

[SHIELDS2001]

?In general, there is a guest graph G and a host graph H.? A layout of G into H is an injective function f from the vertices of G to the vertices of H, together with a mapping Pf, which assigns to each edge [u,v] of G a path between f(u) and f(v) in H.? In a layout, internal nodes in a path from f(u) to f(v) do not include f(z), for any vertices u,v,z in G, nor any other point in a path between f(s) and f(t) for any other edge st in G.

[Sp?nemann2009]
[SHIELDS2001]

?In general, there is a guest graph G and a host graph H.? A layout of G into H is an injective function f from the vertices of G to the vertices of H, together with a mapping Pf, which assigns to each edge [u,v] of G a path between f(u) and f(v) in H.? In a layout, internal nodes in a path from f(u) to f(v) do not include f(z), for any vertices u,v,z in G, nor any other point in a path between f(s) and f(t) for any other edge st in G.

Graph layout

[anoop2013] On Some Graph Layout Problems and Solution Strategies p18

Buchsbaum Rectangular Layouts and Contact Graphs p25
Adam L. Buchsbaum

BUCHSBAUM Rectangular Layouts and Contact Graphs p29
ADAM L.

Claussen Implementing an Algorithm for Orthogonal Graph Layout p47
Ole

okokok
Diaz A survey on graph layout problems p22
[Diaz2000] A survey on graph layout problems p54
7

Dujmovic On Linear Layouts of Graphs p20
Vida

[Dujmovic2003] Track Layouts of Graphs p160
Vida

[Fellows2008] Graph Layout problems Parameterized by Vertex Cover p12
Michael R.

Leeuw Graph Layout Techniques and Multidimensional Data Analysis p31
Author(s): Jan De

okokok
[SHIELDS2001] AREA EFFICIENT LAYOUTS OF BINARY TREES ON ONE, TWO LAYERS p13
CHARLES O. SHIELDS, JR. AND I. HAL SUDBOROUGH
2

[Sp?nemann2009] On the Automatic Layout of Data Flow Diagrams p99
Miro
2009-03-19


Untitled Document

Graph mapping
[LUQMAN2012]
[Potoczak2014]
[Riesen2009]
[ARORA2006]
[Belkin2001]

[Bhatel2009]
Topology aware mapping: how to assign tasks with two-dimensional (2D) near-neighbor communication graphs, to the prevailing three-dimensional (3D) grid and torus topologies.

graph mapping

[Bhatel2009] Automated Mapping of Structured Communication Graphs onto Mesh Interconnects p17
Abhinav Bhatel


Untitled Document

Graph Modeling

?[McBride2005]
Bond graph modeling maps the flow of power through a system.

?

GRAPH MODELING

okokok
[Boonto2014] Dynamics System and Modelling: Linear Graph Modeling I p20

XXXXXXXXXX
[McBride2005] SYSTEM ANALYSIS THROUGH BOND GRAPH MODELING p325

okokok
[Mittelmann2009] Graph Modeling for Quadratic Assignment Problems Associated with the Hypercube p15

[Needham2013] Graph Modeling Dos and Donts p96

[Rowell2004] Linear Graph Modeling: State Equation Formulation p38


Untitled Document

graph realization

?

[Alfakih2006]
The Graph Realization Problem
Given an edge-weighted graph G = (V,E, ?), G is said to be realizable in Rr iff
? p1, p2, . . . , pn ? Rr such that
||pi - pj ||2 = ?ij ? (i, j) ? E.

GRAPH REALIZATION

okokok
[Alfakih2006] The Graph Realization Problem via Semi-Definite Programming p70


Untitled Document

graph visualization/Visual rendering of graphs

Graph visualization

Graph Theoretic Software & Tools
?

Keywords

graph editor
graph editing tools
graph tools
graph software

graph theory software
Graph visualization tools
?

Force-Directed Edge Bundling for Graph Visualization

Danny Holten and Prof. van Wijk

http://infosthetics.com/archives/2009/06/force_directed_edge_bundling_for_graph_visualization.html

http://selection.datavisualization.ch/

https://www.packtpub.com/books/content/visualizing-my-social-graph-d3js

http://raffy.ch/blog/2012/03/24/advanced-network-graph-visualization-with-afterglow/

http://www.scribblelive.com/blog/2013/10/03/graph-visualization-101/

https://opendata.stackexchange.com/questions/93/graph-visualization-analysis-tool/1918

https://reference.wolfram.com/language/guide/GraphVisualization.html
[Baingana2013b]
Visual rendering of graphs is a key task in the mapping of complex network data.
[Gibert2012]
[Baingana2013a]

[Baingana2013b]
Visual rendering of graphs is a key task in the mapping of complex network data.
[Gibert2012]
[Baingana2013a]

?

Battista, G.D., Eades, P., Tamassia, R., and Tollis, I.G. Graph Drawing: Algorithms for the Visualization of Graphs. Prentice Hall, 1999.

Beck A Taxonomy and Survey of Dynamic Graph Visualization p28

Author(s): Beck, Fabian; Burch, Michael; Diehl, Stephan; Weiskopf, Daniel

https://www.vis.wiwi.uni-due.de/en/research/publications/a-taxonomy-and-survey-of-dynamic-graph-visualization-13409/

A Taxonomy and Survey of Dynamic Graph Visualization
Fabian Beck

?

Graph Analysis and Visualization: Discovering Business Opportunity in Linked Data

Authors Richard Brath, David Jonker

Deore Survey on Graph-Hierarchy Visualization Techniques p5

http://www.diagrams-conference.org/2014/GraphViP

DIMACS Implementation Challenge

?

?

?

??????????????????????????

Dujmovic Track Layouts of Graphs p160

89

?

?

Férey IMMERSIVE GRAPH-BASED VISUALIZATION AND EXPLORATION OF BIOLOGICAL DATA RELATIONSHIPS p6

?????????????????????????????????????

GANSNER An open graph visualization system and its applications to software engineering p29

EMDEN R. GANSNER1 and STEPHEN C. NORTH1
1AT&T Labs - Research, Shannon Laboratory, 180 Park Avenue, Florham Park, NJ 07932, USA

1999

?

Gansner Interactive Visualization of Streaming Text Data with Dynamic Maps p25
Emden R.

Gansner Visualizing Streaming Text Data with Dynamic Graphs and Maps p12

Gansner Visualizing Streaming Text Data with Dynamic Graphs and Maps p12.pdf

dynamic graph layout

dynamic graph drawings

Dynamic Visualization

graph packing algorithm

https://gmamaladze.wordpress.com/2014/02/11/net-code-dependency-graph-visualization-using-force-field-simulation/

?

Graph Drawing Contests

Provides information about past and present contests held in conjunction with the annual Symposium on Graph Drawing.

http://www.graphdrawing.de/

?

Graph Drawing Resources

Links to research groups and software.

http://www.cs.brown.edu/people/rt/gd.html

http://graphdrawing.org/index.html

?

???????????????????????????

???????????????????????????

http://www.graphdrawing.org/

http://www.graphdrawing.org

http://graphdrawing.org/books.html

http://graphdrawing.org/

Information source for researchers, practitioners, developers, and users working on all aspects of graph visualization and representation.

?

https://experts.griffith.edu.au/publication/n733e9e596c2a0408e3113ca746681e6a

GSVR website

Ham Interactive Visualization of Small World Graphs p8
Frank van

scalable, interactive visualizations of small world graphs

spring embedder algorithm

force model

small world graphs

clustering index

force directed algorithms

GEM, a typical example of a force directed graph drawing package

LinLog force model

Graph partitioning

Information Galaxies

Information Landscapes

Graph Splatting method

r- PolyLog energy models

3-PolyLog

1-PolyLog mode

1-PolyLog (LinLog)

D. Auber, Y. Chiricota, F. Jourdan, and G. Melanc?on. Multiscale visualization of small world networks. In Proc. of IEEE Symp. on Information Visualization 2003, pages 75–81. IEEE CS Press, 2003.
Guiseppe Di Battista, Peter Eades, Roberto Tamassia, and Ioannis G. Tollis. Graph drawing : Algorithms for the visualization of graphs. Prentice Hall, 1999.
Ivan Herman, Guy Melanc?on, and M. Scott Marshall. Graph visualization and navigation in information visualization. volume 6(1), pages 24–43, 2000.
M. L. Huang and P. Eades. A fully interactive system for clustering and navigating large graphs. In S. Whitesides, editor, Proc. 6th Int. Symp. on Graph Drawing, pages 374 – 383. Springer-Verlag, 1998.
A. Noack. An energy model for visual graph clustering. In Proc. 11th Int. Symp. on Graph Drawing, pages 425–436. Springer-Verlag, 2003.
Robert van Liere and Wim de Leeuw. Graphsplatting: Visualizing graphs as continuous fields. In IEEE Transactions on Visualization and Computer Graphics, volume 9(2), pages 206–212, 2003.
J. A. Wise, J. J. Thomas, K. Pennock, and D. L. Lantrip. Visualizing the non-visual: Spatial analysis and interaction with information from text documents. In S.K. Card, J.D. Mackinlay, and B. Shneiderman, editors, Readings in Information

[Herman2000]

[Herman2000]

Herman Graph Visualization and Navigation in Information Visualization: a Survey p21.pdf

Herman Graph Visualization and Navigation in Information Visualization: a Survey p37.ppt

Herman, I., Marshall, M.S., and Melan?on G. Graph Visualisation and Navigation in Information Visualization: A Survey. IEEE Transactions on Visualization and Computer Graphics, 6, 1 (Jan-Mar 2000), 24-43.

Graph drawing

graph visualization

Information Visualization

Zoom and Pan

Focus+Context Techniques

Graph layout

3D Layout

Hyperbolic Layout

Navigation of large graphs

Reorganization of data: Clustering

Clustering

https://ics.hutton.ac.uk/wiki/index.php?title=Flapjack_Help_-_Graph_Visualization&action=edit

?????????????????????????????????????

Jarukasemratana Recent large graph visualization tools a review p17

Sorn Jarukasemratana

Tsuyoshi Murata

http://www.net.c.titech.ac.jp/murata.html

Name
Tsuyoshi Murata
Affiliation
Associate Professor, Major in Artificial Intelligence
Department of Computer Science, School of Computing
Tokyo Institute of Technology
Address
W8-59 2-12-1 Ookayama, Meguro, Tokyo, 152-8552 Japan
Room
Room E503, 5th floor, West8E building, Ookayama campus
E-mail
murata(@)c.titech.ac.jp
Lectures
Foundations of Computing (in Japanese)(for undergraduates, the first quarter)
Machine Learning(for graduates, the second quarter, English lecture)
Complex Networks(for graduates, the fourth quarter, biannual English lecture)

2013

10

AllegroMCODE

CGV - Coordinated Graph Visualization

GraphGL

Honeycomb

In Situ Framework

JavaScript InfoVis Toolkit

LGL - Large Graph Layout

Pajek

Piccolo

Prefuse

Social Cosmo Browser

The Visualization Toolkit (VTK)

Tulip

VisANT

Web Community Chart

WebGL

WiGis

World flights

DIMACS Implementation Challenge

GSVR website

UMBEL

?

References
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Michailidis, G.: Multiple step social structure analysis
with Cytoscape, in IEEE Symposium on Visual
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[ 2 ] http://www.cytoscape.org/
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down-winner-for-large-scale-graphvisualization/.
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P.L. and Ideker, T.: Cytoscape 2.8: new features for
data integration and network visualization, Bioinformatics,
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bioinformatics application for largescale
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and H¨ollerer, T.: WiGis: A Framework for Scalable
Web-Based Interactive Graph Visualizations,
in 17th International Symposium, Graph Drawing
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of large graph layouts., Technical report,
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/ ct/software/CGV/CGV.html
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CGV An interactive graph visualization system,
Computers & Graphics, Vol. 33, Issue 6 (2009),
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[10] Buchheim, C., Junger, M. and Leipert, S.: Improving
Walker’s algorithm to run in linear time,
in Proceedings of the international symposium on
graph drawing (GD), Berlin, Springer, 2002.
[11] Reingold, E.M. and Tilford J.S.: Tidier drawings
of trees, IEEE Transactions on Software Engineering,
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Wedge I.P.: clutter-free visualization of off-screen
locations, in Proceedings of the SIGCHI conference
on human factors in computing systems (CHI), New
York, ACM, 2008.
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H.: Fisheye tree views and lenses for graph
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[17] http://pajek.imfm.si/doku.php
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[19] http://tulip.labri.fr/TulipDrupal/
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framework, Graph Drawing Softwares, Mathematics
and Visualization, Mutzel, P. and J¨unger, M.
(eds.), Springer-Verlag, 2003, pp. 105–126.
[21] Moscovich, T., Chevalier, F., Henry, N.,
Pietrige, E. and Fekete, J.D.: Topology-aware navigation
in large networks, in Proceedings of the ACM
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Systems, 2009, pp. 2319–2328.
[22] http://www.piccolo2d.org/index.html
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Using Computer Games Techniques for Improving
Graph Visualization Efficiency, in IEEE-VGTC
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VisANT: an online visualization and analysis tool
for biological interaction data, BMC Bioinformatics,
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in Proceedings of the ACM Conference on Human
Factors in Computing Systems , 2005 , pp. 421–430.
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Toolkit Design for Interactive Structured Graphics,
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PhiloGL/examples/worldFlights2/
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Information and Media Technologies 8(4): 944-960 (2013)
reprinted from: Computer Software 30(2): 159-175 (2013)
? Japan Society for Software Science and Technology
960
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, Complex Systems, 2006, p. 1695.
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[40] Landesberger, T.V., Kuijper, A., Kohlhammer,
J., Wijk, J.J.V., Fekete, J.D. and Fellner, D.W.:
Visual Analysis of Large Graphs: State-of-the-Art
and Future Research Challenges, Computer Graphics
Forum, Vol. 30, Issue 6(2011), pp, 1719–1749.
[41] Tollis, I.G., Battista, G.D., Eades, P. and
Tamassia, R.: Graph Drawing: Algorithms for the
Visualization of Graphs, Prentice Hall Engineering/
Science/Mathematics, 1998.
[42] http://www.vtk.org/
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[44] Koshida, M., Hosobe, H. and Wakita, K.:
A Hierarchical Visualization Method for Large-
Scale Social Networks, Computer Software, Vol.28,
No.2(2011), pp. 202–216. (in Japanese)
[45] Itoh, M., Yoshinaga, N., Toyoda, M. and Kitsuregawa,
M.: Analysis and Visualization of Temporal
Changes in Bloggers’ Activities and Interests,
in Proceedings of IEEE Pacific Visualization Symposium
(PacificVis2012), 2012, pp. 57–64.
[46] Matsubayashi, T., Nishida, K., Hoshiide, T.
and Fujimura, K.: Graph visualization of streaming
data using HTML5 in Proceedings of 8th Neteco
Symposium, 2012. (in Japanese)
[47] Toyoda, M. and Kitsuregawa, M.: Web Community
Chart : A Tool for Navigating the Web and
Observing Its Evolution, IEICE transactions on information
and systems, Vol.E86-D, No. 6 (2003),
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[48] Adai, A.T., Date, S.V., Wieland S. and Marcotte
E.M.: LGL: creating a map of protein function
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(2004), pp. 179–190.
[49] http://www.dis.uniroma1.it/challenge9
/papers.shtml
[50] http://www.youtube.com/watch?v
=wxjU1gCRhCA
Sorn Jarukasemratana
Currently a Ph.D. student at Tokyo
Institute of Technology under the
supervision of Dr. Tsuyoshi Murata.
He graduated his master degree
from University of Tampere,
Finland with M.Sc. in User Interface Software Development.
His bachelor degree is obtained from
faculty of engineering, Chulalongkorn University,
Thailand with computer engineering major.
Tsuyoshi Murata
He is an associate professor in the
Department of Computer Science,
Graduate School of Information
Science and Engineering, Tokyo Institute
of Technology. He obtained
his doctor’s degree in Computer Science at Tokyo
Institute of Technology in 1997, on the topic of
Machine Discovery of Geometrical Theorems. At
Tokyo Institute of Technology, he conducts research
on Web mining and social network analysis

Graph Drawing Software (Mathematics and Visualization) 2004th Edition

by Michael Jünger (Editor), Petra Mutzel (Editor)

https://www.amazon.com/Graph-Drawing-Software-Mathematics-Visualization/dp/3540008810

?

?

?????????????????????????????????????

Junghans Visualization of Hyperedges in Fixed Graph Layouts p131

2008

29

Hypergraph Visualization

box-and-line visualizations

Kratochv?l GraDR Graph Drawings and Representations p44
2011

[Kumar2009]
Graph drawing and visualization represent structural information as diagrams of abstract graphs and networks

[Kumar2009] Visualization of Clustered Directed Acyclic Graphs with Node Interleaving p6
Pushpa

Kumar Visualization of Clustered Directed Acyclic Graphs with Node Interleaving p6

Graph drawing and visualization

diagrams of abstract graphs and networks

directed acyclic graphs (DAGs)

E-Spring algorithm

spring embedder model

node interleaving

Spring algorithms

Kamada-Kawai method

modified (or generalized) spring method

The family of spring algorithms includes

  • force scan (FS)
  • force transfer (FT)
  • dynamic natural length spring (DNLS)
  • orthogonal dynamic natural length spring (ODNLS)
  • A fast algorithm (FADE) for two dimensional drawing, geometric clustering and multilevel viewing of large undirected graphs

decomposition tree

heuristics

Clustering

set covering heuristics

hierarchical clustering method

clustered graph model

navigation model

visual complexit

semantic fisheye view of a clustered graph

visualization of clustered graph in dynamic environments

Generalized fisheye views

two dimensional plane drawing algorithms for clustered graphs

two dimensional plane drawings to three dimensional multilevel drawings

convex drawings

orthogonal rectangular drawings

animated drawing

Kwon A Study of Layout, Rendering, and Interaction Methods for Immersive Graph Visualization p14

2016

[Langevin2015]
[Langevin2015] Community Visualization of Graph

Community Visualization of Graph

okokok

[Langevin2015] Multi-Scale Community Visualization of Massive Graph Data p4
Scott Langevin, Member, IEEE, David Jonker, David Giesbrecht, and Michael Crouch

visual mapping of data

visual graph analytic

scalable visual graph analytics

Tile-Based Visual Analytics for Graphs

tile-based visual analytic approach

interactive graph visualizations in modern web browser

two-dimensional, multi-scale graph visualization with a familiar, webbased map interaction scheme

cluster computing

opensource cluster-computing frameworks (Apache Hadoop and Spark)

https://hadoop.apache.org/
http://spark.apache.org/

Apache Spark GraphX library

Apache Avro data tiles

multi-resolution technique

interaction design

zooming and navigation techniques

pan and zoom navigation.

hierarchical communities

distributed, recursive layout algorithm

optimal graph layouts

Hierarchical Graph Layout

distributed, recursive layout algorithm

distributed, recursive, force-directed layout algorithm

cross-plot, geospatial, time series, and force-directed graph layouts of big data

Louvain Modularity algorithm

http://aperturetiles.com/

GraphCT

D. Ediger, K. Jiang, E.J. Riedy, and D.A. Bader, “GraphCT: Multithreaded Algorithms for Massive Graph Analysis”, IEEE Transactions on Parallel & Distributed Systems, 2012.

SNAP:graph analytic tools

are taking advantage of distributed and parallel computing systems to handle node-link datasets with millions or billions of nodes.

community-based layouts for large graph visualizations:

  • HC-drawing
  • Fitted-Rectangles
    • S. Chaturvedi, Z. Ashktorab, and R. Zacharia, “Fitted Rectangles: A Visualization for Clustered Graphs”, 2013.
  • Group-in-a-Box
    • E. Rodrigues, N. Milic-Frayling, M. Smith, B. Shneiderman, and D. Hansen, "Group-in-a-Box layout for multi-faceted analysis of communities", Privacy, Security, Risk and Trust (PASSAT) and 2011 IEEE Third Inernational Conference on Social Computing (SocialCom), 2011 IEEE Third International Conference on. IEEE, 2011.
    • treemap space filling technique
  • NodeTrix
    • N. Henry, J.-D. Fekete, and M. McGuffin, “NodeTrix: a Hybrid Visualization of Social Networks”, Visualization and Computer Graphics, IEEE Transactions On 13, no. 6 (2007): 1302–1309.
    • adjacency matrices
  • Zame
    • N. Elmqvist, T-N. Do, H. Goodell, and N. Henry, “ZAME: Interactive Large-Scale Graph Visualization”, Visualization Symposium, PacificVIS'08, 2008.
    • tile-based approach
    • interactive multi-scale visualization of a graph adjacency matrix

GraphML source data

https://www.comp.leeds.ac.uk/djd/graphs/

[Marshall2001]

[Marshall2001] An Object-Oriented Design for Graph Visualization p16
Graph visualization refers to the display of a set of data that has relations between elements and to the interactive facilities that make navigation through the visual representation of that data possible.

?

http://www2.microstrategy.com/producthelp/10/WebUser/WebHelp/Lang_1033/Analyzing_data_in_graph_visualization.htm

http://www.multigesture.net/research-projects/twilight-graph-visualization/

?????????????????????????????????????

??rnberg Comparison and implementation of graph visualization algorithms using JavaFX p62

2016

GEM-2

Prefux
Prefux is a data visualization library that aims to migrate the Prefuse library to JavaFX

?

?

okokok

Razoumov Graph Visualization with Gephi p12

4/14/2016

Alex Razoumov

Graph/network visualization falls more into the information visualization category

https://www.scads.de/de/lehre/17-abschlussarbeiten/239-bachelor-s-or-master-s-thesis-leipzig-visualization-driven-graph-data-reduction

https://www3.cs.stonybrook.edu/~algorith/implement/north/implement.shtml

?

Graph Drawing and Applications for Software and Knowledge Engineers

By Kozo Sugiyama

?

https://books.google.co.jp/books?

id=H06j5GJKITIC&pg=PA38&lpg=PA38&dq=

graph+software&source=bl&ots=

Q0G-foG9FV&sig=Iyj_W0CVVQnjwjK3JGjw05wJb5M&

hl=en&sa=X&redir_esc=y#v=onepage&q=graph%20software&f=false

?

Handbook of Graph Drawing and Visualization

Roberto Tamassia

https://cs.brown.edu/~rt/gdhandbook/

October 19, 2016 by Chapman and Hall/CRC
Reference - 862 Pages - 480 B/W Illustrations
ISBN 9781138034242 - CAT# K31589

????????????????????????????????????????

okokok

[Tarawneh2011]

[Tarawneh2011] A General Introduction To Graph Visualization Techniques p14

4

Raga’ad M. Tarawneh

Computer Graphics and HCI Group
University of Kaiserslautern, Germany

tarawneh@cs.uni-kl.de

Prof. Dr. Achim Ebert

Achim Ebert

http://www.uni-kl.de/znt/organisation/znt-mitglieder/ebert/

http://www.uni-kl.de/en/znt/organisation/znt-members/ebert/

http://www-hagen.cs.uni-kl.de/?page_id=8&memberID=41

TU Kaiserslautern

Fachbereich Informatik AG Computergrafik

http://informatik.uni-kl.de/

HCI

http://hci.uni-kl.de/

Geb?ude 36, Raum 236
Tel: +49 631 / 205-3502
Fax: +49 631 / 205-3270
E-Mail: ebert[at]cs.uni-kl.de

Computer Graphics and HCI Group
University of Kaiserslautern, Germany
ebert@cs.uni-kl.de

Dear Prof. Dr. Ebert,

I am honored to have read the paper titled "A General Introduction To Graph Visualization Techniques " coauthored by you and your colleagues. I wanted to know if you have similar papers for me to read, because I have been writing a similar paper called "Graph embedding" which will also include graph visualization. I will write the graph visualization part independently, because it alone needs a lot of studies. Graph visualization is an interesting subject, and in the academia there seems some confusion about the terms, definition and scope of topic. Some see it as equal to graph drawing and some consider it as more like a graph navigation. I take the later stand, and consider graph visualization more or less like a 3-dimensional observation of the relationships among the graph components, nodes, links and so on. It might be related to virtual reality as well.

On the other hand, graph embedding is a much broader sense and it needs years of investigations to compile a comprehensive report. I have been working on that for some years already and have just found out hundreds of embedding techniques and algorithms. It may take my entire lifetime to complete that project.

At the moment I am concentrating on graph visualization and plan to finish it in a year or so. Do you have more paper for me to read? German is also OK for me, for I am capable of reading German already since 1980 and was working at German companies for a long time. Of course if you have other language paper please also don't hesitate to send me some, such as those in French and Russian, see my CV for my linguistic potentials.

I am living now in a village in China, with no access to the academia, therefore I rely completely on the Internet to gather information for peruse.

Thank you for your kind attention and your help!

Mark Chen

P.S.: to save me time in writing I write this letter in English rather than German, for writing German takes me a bit longer time.

Dr.-Ing. Patric Keller

Patric Keller

http://www-hagen.informatik.uni-kl.de/~p_keller/webpage/index.php?option=com_content&view=article&id=43%3Aexample-pages-and-menu-links&Itemid=71

Contact:

Dept. of Computer Graphics
Research Group Dependability TU Kaiserslautern
Room 427, Building 32
P.O. Box 3049
67653 Kaiserslautern, Germany

Phone: +49 (0)631 / 205 - 3367
Fax: +49 (0)631 / 205 - 3331
EMail: pkeller [at] cs [dot] uni-kl [dot] de

Software Engineering: Dependability Group
University of Kaiserslautern, Germany
pkeller@cs.uni-kl.de

navigation tools
interaction tools

The goal of graph visualization techniques is to increase the comprehension level of the data by providing intuitive, intelligible layouts as well as suitable interaction mechanisms.

In [60] a summary of popular interaction techniques is presented:

  • Selecting: giving the user the ability to highlight and process specific objects.
  • Abstracting/Elaborating: changing the level of detail of the representation scheme. This allows users to get different insights into the data.
  • Reconfiguring: giving the user the ability to change the layouts for the same representation scheme, such as sorting the graph nodes based on a specific criteria.
  • Encoding: switching between different layout methods, such as converting the node-link diagram into a sunburst layout.
  • Exploring: this is related to giving the user the ability to change the view point of the graph layout. Zooming and panning are examples of this category.
    • Geometric zooming adjusts the screen transformation and thereby allows increasing or decreasing the magnification of the displayed graph.
    • Semantic zooming means that not only the size of objects but also the displayed information may change when approaching a particular area of the graph.
    • Focus+Context Techniques
      • Overview+detail
      • Fish-eye
  • Filtering: removing unnecessary detail and displaying the remaining items in a more visible fashion. The main concept is to filter the data nodes based on their attributes in order to make the querying process easy and fast. For more examples see [5].
  • Connecting: giving users the ability to highlight the paths between relevant objects and the focus object.

References
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https://visual.ly/facebook-graph-visualization

Vogt An open source browser-based software tool for graph drawing and visualization p171

http://ksd.ai.ar.tum.de/?project=3d-graph-visualization&lang=en

UMBEL

http://visjs.org/

http://blog.visualmotive.com/2009/graph-visualization-edge-bundling/

?

http://webgraph.di.unimi.it/

?

Yang PIWI: Visually Exploring Graphs Based on Their Community Structure p14
Jing

?

http://www.yworks.com/
https://www.yworks.com/products/yed

https://www.yworks.com/products/yed

http://www.yworks.com/en/index.html

?

yFiles for Java

http://www.yworks.com/en/products_yfiles_about.htm

An extensive Java class library that provides algorithms and components for analyzing, viewing and layouting graphs, diagrams and networks.

?

?

?

?

?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?

graph databases
?
?
?
?
?
?
?
?

graph theory libraries
?

?

Annas

Java framework designed for developers and researchers in the fields of graph theory.

https://github.com/gt4j/annas

Open source graph theory Java library http://annas.gt4j.org
?

?

The Boost Graph Library (BGL)

http://www.boost.org/doc/libs/1_35_0/libs/graph/doc/index.html
?
?
GoVisual

GoVisual-API is a library of layout algorithms that can be integrated into C++, .NETor Java applications. Includes advanced layout for UML diagrams and cluster diagrams.

http://www.oreas.com/

?
?
?
?
?
?
?
?
?

?

Ref

?

University of Passau? Prof. Dr. Franz Brandenburg
http://www.fim.uni-passau.de/en/fim/faculty/chairs/theoretische-informatik/projects.html

?
?
?
?


def

topological_graph_embedding

?

topological embedding

sequential topological embedding

parallel topological embedding

?

In topological graph theory, an embedding (also spelled imbedding) of a graph G on a surface ? is a representation of G on ? in which points of ? are associated to vertices and simple arcs (homeomorphic images of [0,1]) are associated to edges in such a way that:

??? the endpoints of the arc associated to an edge e are the points associated to the end vertices of e ,
no arcs include points associated with other vertices,
two arcs never intersect at a point which is interior to either of the arcs.

Here a surface is a compact, connected 2-manifold.

Informally, an embedding of a graph into a surface is a drawing of the graph on the surface in such a way that its edges may intersect only at their endpoints. It is well known that any graph can be embedded in 3-dimensional Euclidean space R3 and planar graphs can be embedded in 2-dimensional Euclidean space R2.

Some authors define a weaker version of the definition of "graph embedding" by omitting the non-intersection condition for edges. In such contexts the stricter definition is described as "non-crossing graph embedding".

topology-specific graph embedding

?local topology preserving embedding

?


def

Topological graph theory
graph minor theory
graph structure theorem
Graph embeddings
surface embedding of graphs
spatial embeddings of graphs
embedding a graph into a book
topological embedding

Topological combinatorics

topological homeomorphism

strong embedding

Graph Diagrams

equivalent or ambient isotopic

autohomeomorphism
homeomorphism of graphs
immersions of graphs
graph drawing
draw the graph on a surface, a sphere for example, without two edges intersecting
constructing a graph embedding which they term a "palm tree".

graph diagrams
Crossing number (graph theory)

crosscap number

Genus

Planar graph

Toroidal graph

Voltage graph

fundamental group
3-space
abstract simplicial complex

Whitney complex or clique complex, with a set per clique of the graph
matching complex, with a set per matching of the graph (equivalently, the clique complex of the complement of the line graph).
chessboard complex
cell complex
1-dimensional cell complex
Topology
https://en.wikipedia.org/wiki/Topological_graph

http://research.omicsgroup.org/index.php/Topological_graph_theory

Topological graph theory

This article is about the study of graph embeddings. For graphs in the plane with crossings, see topological graph.
In mathematics topological graph theory is a branch of graph theory. It studies

  • the embedding of graphs in surfaces,
  • spatial embeddings of graphs, and
  • graphs as topological spaces.[1]
  • It also studies immersions of graphs.

Embedding a graph in a surface means that we want to draw the graph on a surface, a sphere for example, without two edges intersecting. A basic embedding problem often presented as a mathematical puzzle is the three-cottage problem.

More important applications can be found in printing electronic circuits where the aim is to print (embed) a circuit (the graph) on a circuit board (the surface) without two connections crossing each other and resulting in a short circuit.

Graphs as topological spaces

An undirected graph can be viewed as an abstract simplicial complex C with a single-element set per vertex and a two-element set per edge.[2]

The geometric realization |C| of the complex consists of a copy of the unit interval [0,1] per edge, with the endpoints of these intervals glued together at vertices.

In this view, embeddings of graphs into a surface or as subdivisions of other graphs are both instances of topological embedding,

homeomorphism of graphs is just the specialization of topological homeomorphism, the notion of a connected graph coincides with topological connectedness, and a connected graph is a tree if and only if its fundamental group is trivial.

Other simplicial complexes associated with graphs include the Whitney complex or clique complex, with a set per clique of the graph, and the matching complex, with a set per matching of the graph (equivalently, the clique complex of the complement of the line graph).

The matching complex of a complete bipartite graph is called a chessboard complex, as it can be also described as the complex of sets of nonattacking rooks on a chessboard.[3]

Example studies

John Hopcroft and Robert Tarjan [4] derived a means of testing the planarity of a graph in time linear to the number of edges. Their algorithm does this by constructing a graph embedding which they term a "palm tree". Efficient planarity testing is fundamental to graph drawing.

Fan Chung et al.[5] studied the problem of embedding a graph into a book with the graph's verticies in a line along the spine of the book. Its edges are drawn on separate pages in such a way that edges residing on the same page do not cross. This problem abstracts layout problems arising in the routing of multilayer printed circuit boards.
Graph embeddings are also used to prove structural results about graphs, via graph minor theory and the graph structure theorem.

[Ackerman2008] XXXXXXXXXXX

Ackerman On Grids in Topological Graphs p14

3

Eyal Ackerman

http://sci.haifa.ac.il/~ackerman/

ackerman@sci.haifa.ac.il

2016-10-23

A topological graph is a graph drawn in the plane with vertices represented by points and edges as arcs connecting its vertices. The arcs are allowed to cross, but they may not pass through vertices except for their endpoints.

The field uses topology to study graphs. For example, planar graphs have many special properties.

The field also uses graphs to study topology. For example, the graph theoretic proofs of the Jordan Curve Theorem, or the theory of voltage graphs depicting branched coverings of surfaces, provide an intuitively appealing and easily checked combinatorial interpretation of subtle topological concepts.

k-grid

(k, l)-grid

k-grid is an abbreviation for a (k, k)-grid

intersection graph: Given a topological graph G, the intersection graph of E(G) has the edge set of G as its vertex set, and an edge between every pair of crossing edges.

maximum independent set

maximum clique

simple topological graph: A topological graph is simple if every pair of its edges intersect at most once.

geometric graph: If the edges are drawn as straight-line segments, then the graph is geometric.

convex geometric graph
Albertson, Mike, Smith College
[Archdeacon1996]

D. Archdeacon, Topological Graph Theory. A Survey, Congr. Numerantium 115 (1996), 5-54, http://www.emba.uvm.edu/~archdeac/papers/survey.ps

Topological graph theory deals with ways to represent the geometric realization of graphs.
D. Archdeacon, Problems in Topological Graph Theory, http://www.emba.uvm.edu/~archdeac/papers/problems.ps

Bokal, Drago, University ofWaterloo

[Bonnington1991a]

Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front p18

Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front1 p18

Topological graph theory is concerned with the study of graphs imbedded in surfaces.

The principal objective of topological graph theory is to determine the surface of smallest genus such that a given graph imbeds in that surface.

combinatorial maps

(A combinatorial map is an n-regular graph endowed with proper edge colouring in n colours.)

cubic combinatorial maps

(A cubic combinatorial map is defined as a cubic graph endowed with a proper edge colouring in three colours .)

first Betti number of a surface

homology spaces

Euler characteristic

Lins ' model

combinatorialise topological graph theory

simplicial complex

orientability character

genus

cross cap number

imbedding distribution of a graph

double cover for a graph

A double cover is a family of circuits such that each edge belongs to exactly two.double cover for a graph

[Bonnington1991b]

Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228

Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole1 p228

23

Bruhn, Henning, Universitt Hamburg
Cabello, Sergio, University of Ljubljana

Chapter 5 Topological Graph Theory p32
Topological graph theory studies the ”drawing” of a graph on a surface.
Definition 5.1.3. (Embedding or Imbedding, 2-cell embedding)
An embedding of a graph in a surface is a continuous 1-1 function from a topological representation of the graph into the surface. If every region of the embedding is homeomorphic to a 2-dim open disc, then the embedding is a 2-cell embedding(????).
Chapter III Adopting Topological Graph Theory to Traffic Management Problem p18
[Childs2016]
Definition 9. We say that a graph G can be embedded on a surface S if there is a drawing
on G on S such that edges intersect only at their endpoints.

Christian, Robin, University of Waterloo

Chung, F. R. K.; Leighton, F. T.; Rosenberg, A. L. (1987). "Embedding Graphs in Books: A Layout Problem with Applications to VLSI Design". SIAM Journal on Algebraic and Discrete Methods 8 (1).
[Craft2013]

Topological Graph Theory is the study of imbeddings of graphs in various surfaces or spaces

The main problem in topological graph theory:? Given a graph G, determine the smallest? genus n so that G imbeds in Sn.

An imbedding or embedding (or proper drawing) of a graph is one in which edges do not cross.

David Craft

Debowsky, Marisa, Courant Institute
DeVos, Matt, Simon Fraser University
Ebrahimi B., Javad, Simon Fraser University
Ellingham, Mark, Vanderbilt University
Fox, Jacob, Princeton University

Jacob Fox

Department of Mathematics, Princeton, Princeton, NJ 08544.

jacobfox@math.princeton.edu

Goddyn, Luis, Simon Fraser University
J.L. Gross and T.W. Tucker, Topological graph theory, Wiley Interscience, 1987
Graph topology, from PlanetMath.

Hajiaghayi, MohammadTaghi, Carnegie Mellon University

Hopcroft, John; Tarjan, Robert E. (1974). "Efficient Planarity Testing". Journal of the ACM 21 (4): 549–568. doi:10.1145/321850.321852.

Hlineny, Petr, Masaryk University
Hutchinson, Joan, Macalester College
Kawarabayashi, Ken-ichi, National Institute of Informatics
KNILL CLASSICAL MATHEMATICAL STRUCTURES WITHIN TOPOLOGICAL GRAPH THEORY p28

OLIVER KNILL

2

Jonathan Gross

Tom Tucker

finite simple graph

geometric graphs

graphs of specific dimension d for which the unit spheres are (d - 1)-dimensional geometric graphs.

manifolds

simplex structure

cohomology group

Lefschetz fixed point theorem in the continuum

Lefschetz number of T

fixed simplices

fixed point simplices

fixed vertex or edge

automorphism of a tree

automorphism T of a triangularization of an n-dimensional sphere

orientation reversing

orientation preserving

orientation preserving automorphism of a triangularization of a 2-sphere

Kral, Daniel, Charles University

XXXXXXXXX
Bojan Mohar

(Simon Fraser University)

http://www.fmf.uni-lj.si/~mohar/

bojan.mohar@fmf.uni-lj.si

bojan.mohar@fmf.uni-lj.si

mohar@sfu.ca

2016-10-25

Norine, Serguei, Georgia Institute of Technology
Oum, Sang-il, Georgia Institute of Technology

[Pach2013]

Janos Pach

City College, CUNY and Courant Institute, NYU, New York, NY.

pach@cims.nyu.edu

Janos Pach

(Courant Institute and City College),

Topological graphs are graphs drawn in the plane with possibly crossing curvilinear edges.

If the edges are allowed to be arbitrary continuous curves connecting the vertices points), then G is called a topological graph.

Bruce Richter

(University of Waterloo),

Pelsmajer, Michael, Illinois Institute of Technology
Pikhurko, Oleg, Carnegie Mellon University
Pinchasi, Rom, Technion - Israel Institute of Technology

Robertson, G. Neil, Ohio State University
[Rooney2006]
Rooney Topological Graph Theory Lecture 15-16 Cycles of Embedded Graphs p6

Brendan Rooney

Simon Fraser University
3

Cycles of Embedded Graphs

Euler genus

additivity of graph genera

three-path property

facial walk

Induced Embeddings

Salazar, Gelasio, Universidad Autonoma de San Luis Potosi

[Sawollek2000] XXXXXXXXX

Sawollek A Survey of Embedding Problems in Topological Graph Theory

Topology Atlas Document # taic-38

Topology Atlas Invited Contributions vol. 5 issue 1 (2000) 20-26

J?rg Sawollek
Fachbereich Mathematik, Universit?t Dortmund, 44221 Dortmund, Germany
E-mail: sawollek@math.uni-dortmund.de

WWW:

http://www.mathematik.uni-dortmund.de/lsv/

Dr. J?rg Sawollek

Technische Universit?t Dortmund

http://www.tu-dortmund.de/

Fakult?t für Mathematik

http://www.mathematik.tu-dortmund.de/

Lehrstuhl LSI

http://www.mathematik.tu-dortmund.de/lsi/

Vogelpothsweg 87
44227 Dortmund

Dr.?J?rg?Sawollek

http://www.mathematik.uni-dortmund.de/de/personen/person/Joerg+Sawollek.html

http://www.mathematik.tu-dortmund.de/de/personen/person/Joerg+Sawollek.html

Raum | M 613
Telefon | (0231) 755-3088
Telefax |
E-mail | Dr.?J?rg?Sawollek

joerg.sawollek@math.tu-dortmund.de

2016-10-19

The main purpose of topological graph theory is to consider geometric realizations of a graph and its embeddings in 3-space or its embeddings or immersions in the plane or surfaces of higher genus.

A topological graph is a 1-dimensional cell complex where the 0-cells correspond to the vertices and the 1-cells correspond to the edges of an underlying abstract graph. If G is a topological graph, then a graph G in R3 is the image of an embedding of G in R3.

Two graphs G1, G2 in R3 are called equivalent or ambient isotopic if there exists an orientation preserving autohomeomorphism of R3 which maps G1 onto G2.

equivalent or ambient isotopic

autohomeomorphism

Embeddings of topological graphs in R3 can be examined via graph diagrams (see Fig. 2),

i.e., images under regular projections to an appropriate plane equipped with over-under information at double points (called crossings ).

cell complex

strong embedding

crosscap number

Graph Diagrams

automorphisms of the graph group

Shareshian, John; Wachs, Michelle L. (2004). "Torsion in the matching complex and chessboard complex". arXiv:math.CO/0409054.

Schaefer, Marcus, DePaul University
Shahrokhi, Farhad, University of North Texas
Solymosi, Jozsef, University of British Columbia
Song, Zixia, University of Central Florida

Andrew Suk

Department of Mathematics, Courant Institute of Mathematical Sciences, New York University, 251 Mercer St., New York, NY 10012.

suk@cims.nyu.edu

Szekely, Laszlo, University of South Carolina
Tardos, Gabor, Simon Fraser University

Robin Thomas

(Georgia Institute of Technology),

Carsten Thomassen

(Technical University of Denmark)

Vodopivec, Andrej, University of Ljubljana

A. T. White and L. W. Beineke, Topological Graph Theory, in: Selected Topics in Graph Theory, eds L. W. Beineke and R. J. Wilson, Academic Press, London (1978), 15-49.

Yerger, Carl, Georgia Institute of Technology

topological_graph_theory

okokok
[Ackerman2008] On Grids in Topological Graphs p14
Eyal Ackerman

okokok

[Archdeacon1995] Topological Graph Theory a Survey p67

okokok
[Bonnington1991a] Combinatorial maps and the foundations of Topological Graph Theory 01_front p18
[Bonnington1991b] Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228
1991

[Childs2016] Topological Graph Theory and Graphs of Positive Combinatorial Curvature p54

okokok
>>> 0000topological_graph_theory
[Craft2013] Topological Graph Theory

Hutchinson Some Conjectures in Chromatic Topological Graph Theory p19

????????????????
KNILL CLASSICAL MATHEMATICAL STRUCTURES WITHIN TOPOLOGICAL GRAPH THEORY p28
2014

okokok
Mohar Topological graph theory and crossing numbers p18
October 21–26, 2006

okokok
Rooney Topological Graph Theory Lecture 15-16 Cycles of Embedded Graphs p6
Burnaby, 2006

okokok

>>> 0000topological_graph_theory

[Sawollek2000] A Survey of Embedding Problems in Topological Graph Theory

Vella A FUNDAMENTALLY TOPOLOGICAL PERSPECTIVE ON GRAPH THEORY p263
2005


def

https://en.wikipedia.org/wiki/Graph_embedding

http://en.wikipedia.org/wiki/Graph_embedding

http://mathworld.wolfram.com/GraphEmbedding.html
https://en.wikipedia.org/wiki/Manifold
https://en.wikipedia.org/wiki/Graph_drawing
https://en.wikipedia.org/wiki/Geometric_graph_theory
https://en.wikipedia.org/wiki/Crossing_number_%28graph_theory%29
https://en.wikipedia.org/wiki/Embedding
https://en.wikipedia.org/wiki/Book_embedding
https://en.wikipedia.org/wiki/Thickness_%28graph_theory%29
https://en.wikipedia.org/wiki/Doubly_connected_edge_list
https://en.wikipedia.org/wiki/Regular_map_%28graph_theory%29
https://en.wikipedia.org/wiki/F%C3%A1ry%27s_theorem

Graph embedding

!!!!!!!!!!!!!!!!!!

??????????????????????

embedding (also spelled imbedding)

Also called

Graph

  • Mapping
  • Packing
  • Drawing
  • Layout
  • Visualization

graph drawing

Visual rendering of graphs

layout of a single graph

Related:

  • Encoding
  • Coupling
  • Clustering
  • Matching
  • Coloring

https://en.wikipedia.org/wiki/Graph_embedding

http://en.wikipedia.org/wiki/Graph_embedding

http://mathworld.wolfram.com/GraphEmbedding.html

https://en.wikipedia.org/wiki/Manifold

https://en.wikipedia.org/wiki/Graph_drawing

https://en.wikipedia.org/wiki/Geometric_graph_theory

https://en.wikipedia.org/wiki/Crossing_number_%28graph_theory%29

https://en.wikipedia.org/wiki/Book_embedding

https://en.wikipedia.org/wiki/Thickness_%28graph_theory%29

https://en.wikipedia.org/wiki/Doubly_connected_edge_list

https://en.wikipedia.org/wiki/Regular_map_%28graph_theory%29

https://en.wikipedia.org/wiki/F%C3%A1ry%27s_theorem

?

!!!!!!!!!!!!!!!!!!

??????????????????????

?
http://dataera.org/category/representation-models/graph-embedding/

?

?

?

Terms & Synonyms

?
Graph embedding
embedding (also spelled imbedding)

Also called

graph drawing

graph encoding

Graph layout

Graph mapping

Graph matching

Graph packing

Graph visualization
Visual rendering of graph

Related Theories

00extremal_graph_theory

00metric_graph_theory

00spectral_graph_theory

00topological_graph_theory

Graph clustering

Graph Coloring

graph coupling

graph homomorphism

graph isomorphism

Graph partition

Definitions

?

[Baingana2013] Embedding Graphs under Centrality Constraints p54

  1. …graph embedding associates each vertex with a set of coordinates in low-dimensional Euclidean space.
  2. In addition to network visualization, graph embedding algorithms compress network data and provide a way to geometrically solve some computationally hard problems.

[Bondy2008] Graph Theory 2008 p654

An embedding of a graph F in a graph G is an isomorphism between F and a subgraph of G

?

https://en.wikipedia.org/wiki/Graph_embedding
http://en.wikipedia.org/wiki/Graph_embedding
http://en.wikipedia.org/wiki/Graph_embedding
http://en.wikipedia.org/wiki/Graph_embedding

http://mathworld.wolfram.com/GraphEmbedding.html
http://mathworld.wolfram.com/GraphEmbedding.html

https://en.wikipedia.org/wiki/Manifold

https://en.wikipedia.org/wiki/Graph_drawing

https://en.wikipedia.org/wiki/Book_embedding

[Borzeshi2011]

In the literature, “graph embedding” refers interchangeably to

??? the embedding of a graph as a whole into a point in vector space, or
the embedding of its set of nodes into a set of corresponding points in vector space.
ransforming the graphs into a vector space by means of graph embedding
raph embedding, converting a graph into a point in a vector space
a graph is converted to an n-dimensional feature vector by way of a set of “prototype” graphs and a dissimilarity measure (often, a graph edit distance): the feature vector consists of the distances between the graph and each prototype.

Well-known embedding techniques include

??? Laplacian eigenmaps,
commute times,
symmetric polynomials, and
kernel principal component analysis,

amongst others

?

?

[Borzeshi2010]

graph embedding to convert the graph into a suitable feature vector.

using graph embedding for obtaining a more suitable feature set.

An alternative to the direct comparison of action graphs is offered by graph embedding: in each frame, the graph representing the actor’s shape can be converted to a finite set of distances from prototype graphs, and the distance vector
then used with conventional statistical classifiers.

With an adequate prototype set, we convert the graph to a set of distances based on the probabilistic graph edit distance (GED) of Neuhaus and Bunke [9].

Graph embedding converts a graph into an n-dimensional real vector

[CHANG2001]

Graph embedding has been used to model the problem of simulating a parallel algorithm in a parallel machine. It is a mapping M of a guest graph G onto a host graph H. The cost of an embedding is measured in terms of dilation, congestion, and expansion [1, 3, 4, 6-10, 13-15].

?

[CHEN2000]

graph embedding problem. Given a guest graph G and a host graph H, the problem is to find a mapping from each
node of G to one of H, and a mapping from each edge of G to one path in H.

[Chowdhury2010]

A drawing of a graph is a sort of visualization of information represented by that graph. The field in which the different aesthetic techniques of drawing graphs are vividly described is “Graph Drawing”.

In the field of graph drawing, the geometric representations of graphs generated by graph drawing algorithms are constrained by some predefined geometric or aesthetic properties.

?

?

===========================

?

?

?

Algorithm for embedding a graph with metric constraints

?

embedding of the graph on the surface.

?

?

embedding of the Shrikhande graph on the torus

?

?

Graph embedding in 3D grid minimizing edge length

https://mathoverflow.net/questions/158460/graph-embedding-in-3d-grid-minimizing-edge-length

Algorithm for embedding a graph with metric constraints

https://mathoverflow.net/questions/33043/algorithm-for-embedding-a-graph-with-metric-constraints

?

?
embedded graphs

2D embedding / two dimensional quantum embedding

[EMMS2007]

2D embedding / two dimensional quantum embedding
Action Respecting Embedding (ARE)

?

sparsest cut
measure concentration.
dilation
congestion.

Embedding graphs by dimensionality reduction

?

?1? one-dimensional embedding

2-Cellular Embedding

2-cell embedding

2-cell toroidal embedding

2 Two dimensional embedding,

2-dimensional embeddings
2D embeddings

3 three-dimensional embeddings

Three dimensional embedding of binary trees
3D embedding

[Bondy2008] Graph Theory 2008 p654

An embedding of a graph F in a graph G is an isomorphism between F and a subgraph of G

[Borzeshi2011]

In the literature, “graph embedding” refers interchangeably to

  • the embedding of a graph as a whole into a point in vector space, or
  • the embedding of its set of nodes into a set of corresponding points in vector space.
  • ransforming the graphs into a vector space by means of graph embedding
  • raph embedding, converting a graph into a point in a vector space
  • a graph is converted to an n-dimensional feature vector by way of a set of “prototype” graphs and a dissimilarity measure (often, a graph edit distance): the feature vector consists of the distances between the graph and each prototype.

Well-known embedding techniques include

  • Laplacian eigenmaps,
  • commute times,
  • symmetric polynomials, and
  • kernel principal component analysis,

amongst others

[Borzeshi2010]

graph embedding to convert the graph into a suitable feature vector.

using graph embedding for obtaining a more suitable feature set.

An alternative to the direct comparison of action graphs is offered by graph embedding: in each frame, the graph representing the actor’s shape can be converted to a finite set of distances from prototype graphs, and the distance vector
then used with conventional statistical classifiers.

With an adequate prototype set, we convert the graph to a set of distances based on the probabilistic graph edit distance (GED) of Neuhaus and Bunke [9].

Graph embedding converts a graph into an n-dimensional real vector

[CHANG2001]

Graph embedding has been used to model the problem of simulating a parallel algorithm in a parallel machine. It is a mapping M of a guest graph G onto a host graph H. The cost of an embedding is measured in terms of dilation, congestion, and expansion [1, 3, 4, 6-10, 13-15].

[CHEN2000]

graph embedding problem. Given a guest graph G and a host graph H, the problem is to find a mapping from each
node of G to one of H, and a mapping from each edge of G to one path in H.

[Chowdhury2010]

A drawing of a graph is a sort of visualization of information represented by that graph. The field in which the different aesthetic techniques of drawing graphs are vividly described is “Graph Drawing”.

In the field of graph drawing, the geometric representations of graphs generated by graph drawing algorithms are constrained by some predefined geometric or aesthetic properties.

===========================

Algorithm for embedding a graph with metric constraints

embedding of the graph on the surface.

embedding of the Shrikhande graph on the torus

Graph embedding in 3D grid minimizing edge length

https://mathoverflow.net/questions/158460/graph-embedding-in-3d-grid-minimizing-edge-length

Algorithm for embedding a graph with metric constraints

https://mathoverflow.net/questions/33043/algorithm-for-embedding-a-graph-with-metric-constraints
embedded graphs

2D embedding / two dimensional quantum embedding

[EMMS2007]

2D embedding / two dimensional quantum embedding
Action Respecting Embedding (ARE)

?
?
?
?


Untitled Document

Adaptive local graph embedding weighted-penalty SVM
additive-distortion embedding into low-dimensional Euclidean space.
additive-error embeddings
Attribute Statistics based Embedding

Action Respecting Embedding (ARE)

?

additive-distortion embedding into low-dimensional Euclidean space

?

additive-error embeddings

?

?

(Graph) Attribute Embedding

?
Graph Attribute Embedding

Graph Attribute Embedding

Graph Attribute Embedding

Attribute Statistics based Embedding

?


Untitled Document

barycentric embedding proofs of Tutte
book embedding

One method for doing this is to place the points on any line in space and to draw the m edges as curves each of which lies in one of m distinct halfplanes having that line as their common boundary. An embedding like this in which the edges are drawn on halfplanes is called a book embedding of the graph. This metaphor comes from imagining that each of the planes where an edge is drawn is like a page of a book. It was observed that in fact several edges may be drawn in the same "page"; the book thickness of the graph is the minimum number of halfplanes needed for such a drawing.

embedding a graph in a book with its vertices in a line along the spine of the book and its edges on the pages in such a way that edges residing on the same page do not cross.

Topological Book Embedding
book embeddings
n-book embedding
brute force embedding
?

brute force embedding

?

?

[Klymko2014]

brute force embedding
?
?

?

barycentric embedding proofs of Tutte

?

?BER Embedding

Bipartite embeddings

block-preserving embedding

book embedding

One method for doing this is to place the points on any line in space and to draw the m edges as curves each of which lies in one of m distinct halfplanes having that line as their common boundary. An embedding like this in which the edges are drawn on halfplanes is called a book embedding of the graph. This metaphor comes from imagining that each of the planes where an edge is drawn is like a page of a book. It was observed that in fact several edges may be drawn in the same "page"; the book thickness of the graph is the minimum number of halfplanes needed for such a drawing.

embedding a graph in a book with its vertices in a line along the spine of the book and its edges on the pages in such a way that edges residing on the same page do not cross.

book embeddings

minimum-page embedding

n-book embedding

?

Topological Book Embedding

Topological Book Embedding

upward topological book embedding

?

brute force embedding

?
brute force embedding

?

?

[Klymko2014]

brute force embedding

?


Untitled Document

canonical embedding

Cauchy Graph Embedding
http://techtalks.tv/talks/cauchy-graph-embedding/54317/

cellular embeddings

cellular embedding
CENTRALITY-CONSTRAINED GRAPH EMBEDDING

[Baingana2013] CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5

chordal embedding

circular embedding

circular embedding

Circular Embedding Conjecture

Circular Embedding Conjecture
clockwise embedding

Clustered Embedding

Combinatorial embedding

An embedded graph uniquely defines cyclic orders of edges incident to the same vertex. The set of all these cyclic orders is called a rotation system. Embeddings with the same rotation system are considered to be equivalent and the corresponding equivalence class of embeddings is called combinatorial embedding (as opposed to the term topological embedding, which refers to the previous definition in terms of points and curves). Sometimes, the rotation system itself is called a "combinatorial embedding"

complete-graph embedding

[Klymko2014]

complete-graph embedding
Constrained Graph Embedding
convex embedding
cross-entropy embedding
Cross-view Graph Embedding
cycle (resp. path) embedding problem.

?

canonical embedding

?
canonical embedding

Cauchy Graph Embedding

http://techtalks.tv/talks/cauchy-graph-embedding/54317/

Cauchy Graph Embedding

cellular embeddings

cellular embedding

?

?

?

?

chordal embedding

?

circular embedding

circular embedding

Circular Embedding Conjecture

Circular Embedding Conjecture

clockwise embedding

?

?

?

Clustered Embedding

Clustered Embedding

cluster preserving embedding

?

color-based embedding

Color Naming based Embedding

?

Combinatorial embedding

An embedded graph uniquely defines cyclic orders of edges incident to the same vertex. The set of all these cyclic orders is called a rotation system. Embeddings with the same rotation system are considered to be equivalent and the corresponding equivalence class of embeddings is called combinatorial embedding (as opposed to the term topological embedding, which refers to the previous definition in terms of points and curves). Sometimes, the rotation system itself is called a "combinatorial embedding"

complete-graph embedding

[Klymko2014]

complete-graph embedding

Constant Shift Embedding

Graph Embedding using Constant Shift Embedding
Graph Embedding using Constant Shift Embedding
Graph Embedding using Constant Shift Embedding

constant shift embedding

Constrained Graph Embedding

?

CENTRALITY-CONSTRAINED GRAPH EMBEDDING

centrality-constrained graph embedding

[Baingana2013] CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5

adapt MDS and LLE to the centrality-constrained graph embedding

Directionally constrained embeddings

?

convex embedding

?

cross-entropy embedding

?

Cross-view Graph Embedding

?
Cross-view Graph Embedding

cycle (resp. path) embedding problem

?

cylindrical embedding


Untitled Document

direct graph embedding
linear extension of the direct graph embedding

[Zhou, Ziheng2010]

Directed Graph Embedding

Direct map embedding
Directionally constrained embeddings
dissimilarity space embedding

Distance Preserving Graph Embedding
The distance preserving graph embedding problem is to embed the vertices of a given weighted graph onto points in d-dimensional Euclidean space for a constant d such that for each edge the distance between their corresponding endpoints is as close to the weight of the edge as possible.
Distance Preserving Graph Embedding

Distributed Social Graph Embedding

Dual embeddings

Data structure embedding

Dilation-5 embedding

direct graph embedding

linear extension of the direct graph embedding

[Zhou, Ziheng2010]

?

?

Directed Graph Embedding

?

Direct map embedding

?

?

Direct constructive embedding

?Dissimilarity based graph embedding

Dissimilarity based graph embedding

?

Distance Preserving Graph Embedding

The distance preserving graph embedding problem is to embed the vertices of a given weighted graph onto points in d-dimensional Euclidean space for a constant d such that for each edge the distance between their corresponding endpoints is as close to the weight of the edge as possible.
Distance Preserving Graph Embedding
Distance Preserving Graph Embedding

?

?

Domain-specific Embedding

Dual embeddings

?dual embedding

dynamic embedding problem

dynamic data structure
dynamization of graph algorithms

dynamic embedding problem


Untitled Document

edge-disjoint embeddings

Embeddings in Hypercubes
?

encoded embedding / unencoded embedding

?

[Lucas2012]

?

encoded embedding / unencoded embedding

?
Euclidean L-embedding

explicit graph embedding.

On the other hand, explicit graph embedding methods explicitly embed an input graph into a feature vector and thus enable the use of all the methodologies and techniques devised for vector spaces. The vectors obtained by an
explicit graph embedding method can also be employed in a standard dot product for defining an implicit graph embedding function between two graphs. An important property of explicit graph embedding is that graphs of different size and order need to be embedded into a feature vector of determined size. The selection of the axis of this feature vector requires thus a fine analysis of the analysed dataset in order to selected features representive of the set while remaining sufficiently generic to describe any input graph. We refer the interested reader to [16] for further reading on classical explicit graph embedding techniques.

Edge based embedding

?

edge-disjoint embeddings

?

embedding space

?

encoded embedding / unencoded embedding

?

[Lucas2012]

?

encoded embedding / unencoded embedding

?

?entity embeddings

?Entropic Graph Embedding

?

Euclidean embeddings

Euclidean low-distortion embeddings

explicit graph embedding

On the other hand, explicit graph embedding methods explicitly embed an input graph into a feature vector and thus enable the use of all the methodologies and techniques devised for vector spaces. The vectors obtained by an
explicit graph embedding method can also be employed in a standard dot product for defining an implicit graph embedding function between two graphs. An important property of explicit graph embedding is that graphs of different size and order need to be embedded into a feature vector of determined size. The selection of the axis of this feature vector requires thus a fine analysis of the analysed dataset in order to selected features representive of the set while remaining sufficiently generic to describe any input graph. We refer the interested reader to [16] for further reading on classical explicit graph embedding techniques.

Explicit Graph Embedding

Exponential and Gaussian Embedding

exponential embedding

extended embedding


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F′ ary embedding
Fixed Embedding
force-directed graph embedding

Force-directed graph embedding algorithms, like the Fruchterman-Reingold method
FST embedding

nite state transducer (FST)
Fuzzy Multilevel Graph Embedding (FMGE)

?

Fary embedding

?
Fary embeddings

?

Fixed Embedding

?

flat embedding

Fold Embeddings

?

force-directed graph embedding

?

Force-directed graph embedding algorithms, like the Fruchterman-Reingold method

Fruchterman-Reingold method

?

spring embedding techniques / Spring-based Graph Embedding Algorithm / spring force embedding

spring embedding

?

frequent reembedding of temporally dynamic network graphs

FST embedding

finite state transducer (FST)

?


Untitled Document

geometric embedding
Graph partitions or separators are central objects of study in the theory of Markov chains, geometric embeddings and are a natural algorithmic primitive in numerous settings, including clustering, divide and conquer approaches, PRAM emulation, VLSI layout, and packet routing in distributed networks.
Expander Flows Geometric Embeddings

ARORA Expander Flows Geometric Embeddings and Graph Partitioning p30
Graph Attribute Embedding
Grassmann graph embedding framework
Grassmann based graph embedding framework

greedy embedding
?

greedy embedding

[Klymko2014]

greedy embedding
grid embedding

?

Gaussian embedding

?

?

geometric embedding

Graph partitions or separators are central objects of study in the theory of Markov chains, geometric embeddings and are a natural algorithmic primitive in numerous settings, including clustering, divide and conquer approaches, PRAM emulation, VLSI layout, and packet routing in distributed networks.
Expander Flows Geometric Embeddings

ARORA Expander Flows Geometric Embeddings and Graph Partitioning p30

Simultaneous Geometric Graph Embedding

simultaneous geometric embedding (SGE)
Simultaneous geometric embeddings

Colored Simultaneous Geometric Embeddings

Colored Simultaneous Geometric Embeddings

global embedding

global optimal embedding

?

graph embedding in vector space (GEVS)

Graph embedding in vector space via dissimilarity mapping

?graph drawing

dynamic graph visualization

Visual rendering of graphs

embedding graphs for visualization

Concentric graph layouts
Visual rendering of graphs
graph drawing algorithms

Graph of Words Embedding

Graph probing based graph embedding methods

Graph probing based graph embedding methods

GRASP embeddings

Grassmann graph embedding framework

Grassmann based graph embedding framework

?

?

greedy embedding

?
greedy embedding

[Klymko2014]

greedy embedding

Grassmann based graph embedding framework
greedy embedding in two-dimensional hyperbolic space
greedy embedding of an infinite d-regular tree

online greedy graph embedding in the hyperbolic plane

?

grid embedding

?
grid-embedding

?Dynamic grid embedding


Untitled Document

H-tree embedding
HCLG embedding
Hierarchical Graph Embedding

H-tree embedding

?

HCLG embedding

?

Hierarchical Graph Embedding

?
hierarchical embedding problem
Hierarchical Graph Embedding

honeycomb embedding

Hyperbolic Embedding

hyperbolic-space embeddings

hypercube embeddings

Embeddings in Hypercubes

Hypergraph embedding

Hypergraph embedding and transductive inference based on the hypergraph Laplacian.

Hyperbolic Embedding

hypergraph Laplacian

Hypergraph Embeddings
[Cooley2009]

Broadly speaking, we consider the problem of embedding a hypergraph H into a larger hypergraph G, i.e. of finding a subhypergraph of G which is isomorphic to H.


Untitled Document

implicit graph embedding

The implicit graph embedding methods are based on graph kernels. A graph kernel is a function that can be thought of
as a dot product in some implicitly existing vector space. Instead of mapping graphs from graph space to vector space and then computing their dot product, the value of the kernel function is evaluated in graph space. Such an implicit
embedding satisfies all properties of a dot product. Since it does not explicitly map a graph to a point in vector space, a strict limitation of implicit graph embedding is that it does not permit all operations that could be defined on
vector spaces. Further reading on state of the art methods of graph kernels and implicit graph embedding could be found in [2].

Bunke, H., Riesen, K.: Recent advances in graph-based pattern recognition with applications in document analysis. Pattern Recognition 44(5), 1057–1067 (2011)
incremental embedding problem
I/O-Optimal Planar Embedding

isomap embedding
isometric embedding

isometric embedding

weighted isometric embeddings

Topologically Constrained Isometric Embedding
isomorphic embedding

implicit graph embedding

The implicit graph embedding methods are based on graph kernels. A graph kernel is a function that can be thought of
as a dot product in some implicitly existing vector space. Instead of mapping graphs from graph space to vector space and then computing their dot product, the value of the kernel function is evaluated in graph space. Such an implicit
embedding satisfies all properties of a dot product. Since it does not explicitly map a graph to a point in vector space, a strict limitation of implicit graph embedding is that it does not permit all operations that could be defined on
vector spaces. Further reading on state of the art methods of graph kernels and implicit graph embedding could be found in [2].

Bunke, H., Riesen, K.: Recent advances in graph-based pattern recognition with applications in document analysis. Pattern Recognition 44(5), 1057–1067 (2011)

incremental embedding of network nodes

incremental embedding problem

induced embedding

internet embedding

?

?

isomap embedding

?
Isomap
isomap embedding

?c-isomap

?

isometric embedding

isometric embedding

Canonical isometric embedding

Canonical isometric embedding

Topologically Constrained Isometric Embedding

weighted isometric embeddings

  1. weighted isometric embeddings

?

isomorphic embedding

?
isomorphic, non-isotopic embeddings


Untitled Document

Kernel Embedding

?

?Knowledge Graph Embedding


Untitled Document

l1-embeddings
Laplacian eigenmaps
least-squares embedding
Level and radial embeddings

Linear Discriminant Analysis (LDA)

3.4 Linear Extensions of Graph Embedding ................................................................. 38

[Azary2014]

Linear Extensions of Graph Embedding (LGE) methods are eigen-based linearized techniques to solve linear approximations of non-linear systems through dimensionality reduction. They include linear discriminant analysis (LDA) [70], locality preserving projections (LPP) [71], and neighborhood preserving embedding (NPE) [72].

Linear embedding
Linear Extensions of Graph Embedding (LGE)
locally linear embedding (LLE)
Lipschitz embedding
linkless embedding
An embedding of a graph into three-dimensional space in which no two of the cycles are topologically linked is called a linkless embedding. A graph has a linkless embedding if and only if it does not have one of the seven graphs of the Petersen family as a minor.
Local Discriminant Embedding (LDE)
Local Graph Embedding

locally linear embedding (LLE)

locally linear embedding algorithm of Roweis and Saul

Supervised locally linear embedding

Hessian LLE

[Azary2014]

3.3 Locally Linear Embedding ..................................................................................... 35

Locally Linear Embedding (LLE) is an unsupervised eigenvector method for dimensionality reduction that preserves the embedding of high dimensional data through maximal discrimination in the lower dimensional space.
Locality Sensitive Discriminant Analysis (LSDA)
LLR embedding
LLR embedding technique
the LLR embedding technique [20,23] to map all vertices in G into points in vector space ℜk, where k is the dimensionality of ℜk.
[20,23]

20. N. Linial, E. London, and Y. Rabinovich. The geometry of graphs and some of its algorithmic applications. Combinatorica, 15(2):215–245, 1995.

23. C. Shahabi, M. R. Kolahdouzan, and M. Sharifzadeh. A road network embedding technique for k-nearest neighbor search in moving object databases. GeoInformatica, 7(3):255–273, 2003.

[Zou, Lei et al2012]

Long-Ring Embedding
Low dimensional embedding

low-dimensional embeddings
low-distortion embeddings
low distortion embedding of the geodesic distance

L-embedding

Euclidean L-embedding

?
Euclidean L-embedding

l1-embedding

l1-embeddings

l1-embedding

?

Laplacian eigenmaps

?Laplacian eigenmaps (LEM)

Laplacian embedding

?

least-squares embedding

?

Level and radial embeddings

?
Level and radial embeddings

Level embeddings

linear extensions of graph embedding (LGE)

?

linear discriminant embedding

locally linear discriminant embedding

Linear embedding

Linear Extensions of Graph Embedding (LGE)
locally linear embedding (LLE)

linear extensions of graph embedding (LGE)

?

Lipschitz embedding

?

linkless embedding

An embedding of a graph into three-dimensional space in which no two of the cycles are topologically linked is called a linkless embedding. A graph has a linkless embedding if and only if it does not have one of the seven graphs of the Petersen family as a minor.

Local Discriminant Embedding (LDE)

?

Local Graph Embedding

?

Adaptive local graph embedding weighted-penalty SVM

?

?

Local Spline Embedding

?

locally linear embedding (LLE)

locally linear embedding (LLE)
locally linear embedding (LLE)
Locally Linear Embedding (LLE),

locally linear embedding algorithm of Roweis and Saul

locally-linear embedding (LLE) algorithm

α-SupervisedLLE (α-SLLE)

Automated Local Linear Embedding

centrality-constrained LLE problem

Enhanced SLLE

Guided Locally Linear Embedding

Hessian LLE

Hessian LLE

[Azary2014]

3.3 Locally Linear Embedding ..................................................................................... 35

Locally Linear Embedding (LLE) is an unsupervised eigenvector method for dimensionality reduction that preserves the embedding of high dimensional data through maximal discrimination in the lower dimensional space.

Iterative Locally Linear Embedding

Kernel Locally Linear Embedding (KLLE)

Kernelized Locally Linear Embeddings

?Modified Supervised Locally Linear Embedding(MSLLE)

?

Probability-based locally linear embedding

Robust Locally Linear Embedding R LLE

Robust locally linear embedding(RLLE)

Supervised locally linear embedding

Supervised locally linear embedding

supervised LLE (SLLE)

locality-preserving embedding

?

LLR embedding

LLR embedding technique
the LLR embedding technique [20,23] to map all vertices in G into points in vector space ?k, where k is the dimensionality of ?k.

[20,23]

20. N. Linial, E. London, and Y. Rabinovich. The geometry of graphs and some of its algorithmic applications. Combinatorica, 15(2):215–245, 1995.

23. C. Shahabi, M. R. Kolahdouzan, and M. Sharifzadeh. A road network embedding technique for k-nearest neighbor search in moving object databases. GeoInformatica, 7(3):255–273, 2003.

[Zou, Lei et al2012]

?

Long-Ring Embedding

?

Low dimensional embedding

?

?

low-dimensional embeddings

?nonlinear low-dimensional embeddings

?

low-distortion embeddings

low distortion embedding of the geodesic distance

Low distortion Delaunay embedding
low-dimensional nonlinear embedding
low-distortion embeddings

low-distortion embeddings
Low-distortion embeddings

low-distortion, volume-respecting, embeddings

lowest-dimensional embedding

LSMDS embedding


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Manifold embedding
Margin-based Embedding
mass-preserving embedding

Matrix-based embeddings
Maximum inter-class and marginal discriminant embedding (MIMDE)

MDS embedding

[EMMS2007]

MDS embedding
?
metric embeddings

contractive metric embedding

expansive metric embedding

optimal-distortion metric embeddings
Minimum Depth Graph Embedding
minimum volume embedding (MVE)

Minor-Embedding

topological-minor embedding
Minor-Embedding (subgraph-embedding)

maximal minor embedding

topological-minor embedding

Minor-Embedding (subgraph-embedding)
?

[Choi2008] [Choi2011]

Minor-Embedding (subgraph-embedding)

[Klymko2014]

minor embedding / subgraph embedding

?
?
?
?

maximal minor embedding
?

[Klymko2014]

maximal minor embedding
?
?
?

topological-minor embedding
?

[Choi2008] [Choi2009]

topological-minor embedding
?
?

modulo graph embedding
Modulo Graph Embedding
Multi-kernel graph embedding

MultiPlane Graph Embedding
http://sydney.edu.au/research/opportunities/opportunities/1033
multiple embedding

Multi-kernel graph embedding
http://www.ncbi.nlm.nih.gov/pubmed/23294985

Manifold embedding

?
Manifold embedding

Flexible manifold embedding

?

Margin-based Embedding

?

mass-preserving embedding

?mass-preserving embedding

Matou?sek’s embedding

?

Matrix-based embeddings

?

Matrix-Based Embedding

maximum genus embedding

?

Maximum inter-class and marginal discriminant embedding (MIMDE)

?

?m-dimensional embedding

?

MDS embedding

[EMMS2007]

MDS embedding

MDS embedding

metric embeddings

contractive metric embedding

expansive metric embedding

optimal-distortion metric embeddings

metric embeddings

contractive metric embedding

expansive metric embedding

optimal-distortion metric embeddings

?

Minimal and Maximal Graph Embeddings

Minimum Depth Graph Embedding

?
Minimum Depth Graph Embedding

?

?minimum genus embedding

Minimum Distortion Embedding

?

minimum volume embedding (MVE)

?Minimum Volume Embedding (MVE)
Minimum volume embedding (MVE)

?

Minor-Embedding

topological-minor embedding

?

Minor-Embedding (subgraph-embedding)

maximal minor embedding

topological-minor embedding
Minor-Embedding (subgraph-embedding)

[Choi2008] [Choi2011]

Minor-Embedding (subgraph-embedding)

[Klymko2014]

minor embedding / subgraph embedding

?

maximal minor embedding

[Klymko2014]

maximal minor embedding

topological-minor embedding

[Choi2008] [Choi2009]

topological-minor embedding

?

?

?

?

modulo graph embedding

Modulo Graph Embedding

More faithfulness graph embedding

?

Multi-kernel graph embedding

?

?Semi Supervised Multi Kernel (SeSMiK) Graph Embedding

?

multi-level embedding

Multi-Level Graph Embedding

?

?Fuzzy Multilevel Graph Embedding (FMGE)

?

Fuzzy Multilevel Graph Embedding

?

MultiPlane Graph Embedding

http://sydney.edu.au/research/opportunities/opportunities/1033

multiple embedding

?
Multi-kernel graph embedding
http://www.ncbi.nlm.nih.gov/pubmed/23294985

Multi-view Embedding

Transductive Multi-view Embedding

Mutual Information Embedding (MIE)


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natural embedding
neighborhood preserving embedding (NPE)
network embedding
Non-negative Graph Embedding (NGE)

natural embedding

?

near-isometric embedding

near-isometric embedding

near-optimal embedding

near-simultaneous embeddings

neighbor embedding

neighborhood preserving embedding (NPE)

?

?low-dimensional neighborhood preserving embedding

?

network embedding

?network embedding

network embeddings based on an embedded spanning tree subgraph

Virtual Network Embedding (VNE) algorithms

neural embedding

node-based embedding

node statistics based embedding of graphs

non-contracting embedding

non-isomorphic embeddings

non-linear embedding

low-dimensional nonlinear embedding

?

Non-negative Graph Embedding (NGE)

?

Nonnegative Graph Embedding
nonnegative graph embedding (NGE)

Multiplicative nonnegative graph embedding

Projective Nonnegative Graph Embedding

Robust (Semi) Nonnegative Graph Embedding

non-surface separating graph embeddings

?

online graph embedding.


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ordinal embedding

Local Ordinal Embedding

in an ordinal embedding, we must preserve the relative order between pairs of distances (which pairs are larger or smaller), and not necessarily the values of the distances themselves.
Orientable Embedding Conjecture

Orientable Embedding Conjecture

Orientable Embedding Conjecture
orthogonal embedding

optimal-distortion embedding

?

ordinal embedding

Local Ordinal Embedding

in an ordinal embedding, we must preserve the relative order between pairs of distances (which pairs are larger or smaller), and not necessarily the values of the distances themselves.

  1. ?Soft Ordinal Embedding (SOE)
    1. SOE for graph embedding problem = Local Ordinal Embedding (LOE) (LOE is one of graph embedding methods for unweighted graphs)

?
Ordinal embedding

?

Orientable Embedding Conjecture

?

Orientable Embedding Conjecture

Orientable Embedding Conjecture

?

orientable and non-orientable embeddings

?

Orientation embedding of signed graphs

http://onlinelibrary.wiley.com/doi/10.1002/jgt.3190160503/abstract

?

orthogonal embedding

?


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PCO embedding

Principal Coordinate Analysis (PCO)
planar embedding / plane embedding

Unique Plane Embeddings

straight-line plane embedding

planar embeddings

fixed planar embedding

On-line Planar Graph Embedding
plane embedding

straight-line plane embedding

[Ancona2009] Ancona A New Tool for Rectangular Dualization p12
p 4
Point Set Embedding

Point-Set Embedding

upward point-set embedding

Straight-line Point-Set Embedding

Orthogonal point-set embeddings
probabilistic tree embeddings

prototype-based graph embedding
Prototype-based embedding is certainly the simplest and fastest embedding approach
PROXIMITY-BASED GRAPH EMBEDDING

?

PCO embedding

Principal Coordinate Analysis (PCO)

PCO embedding

?

planar embedding / plane embedding

Unique Plane Embeddings

straight-line plane embedding

planar embeddings

fixed planar embedding

I/O-Optimal Planar Embedding

On-line Planar Graph Embedding

On-line Planar Graph Embedding

plane embedding

straight-line plane embedding

[Ancona2009] Ancona A New Tool for Rectangular Dualization p12
p 4

?planar embedding of a planar graph
planar straight-line embedding

?

upward planar embedding

?

Point Set Embedding

Point-Set Embedding

Orthogonal point-set embeddings

Straight-line Point-Set Embedding

upward point-set embedding

primal-dual embedding

?

?probabilistic embedding method

?

probabilistic tree embeddings

?

?

prototype-based graph embedding

Prototype-based embedding is certainly the simplest and fastest embedding approach

PROXIMITY-BASED GRAPH EMBEDDING

?

High-Order Proximity preserved Embedding

Partial Proximity Embedding

?Stochastic proximity embedding


def

Prototype-based embedding is certainly the simplest and fastest embedding approach

[Borzeshi2011] A discriminative prototype selection approach for graph embedding in human action recognition p7

transforming the graphs into a vector space by means of graph embedding

graph embedding, converting a graph into a point in a vector space

prototype-based graph embedding

“prototype” graphs

selection of a suitable set of prototypes

discriminative approach outperforms well-established class-based prototype selection methods such as center, border and random prototype selection.

a graph is converted to an n-dimensional feature vector by way of a set of “prototype” graphs and a dissimilarity measure (often, a graph edit distance): the feature vector consists of the distances between the graph and each prototype.

error-tolerant graph matching

graph edit distance (GED)

In the literature, “graph embedding” refers interchangeably to the embedding of a graph as a whole into a point
in vector space, or the embedding of its set of nodes into a set of corresponding points in vector space.

Prototype-based embedding is certainly the simplest and fastest embedding approach

embedding the graph into a feature vector by means of P-GED with the prototype set of choice

discriminative prototype selection method

3

2

[Borzeshi2010] Automatic human action recognition in videos by graph embedding p10

E. Z. Borzeshi, R. Y. D. Xu, and M. Piccardi. Automatic human action recognition in videos by graph embedding. In 16th International Conference on Image Analysis and Processing, ICIAP 2011, 2011.

graph embedding to convert the graph into a suitable feature vector.

using graph embedding for obtaining a more suitable feature set.

An alternative to the direct comparison of action graphs is offered by graph embedding: in each frame, the graph representing the actor’s shape can be converted to a finite set of distances from prototype graphs, and the distance vector
then used with conventional statistical classifiers.

With an adequate prototype set, we convert the graph to a set of distances based on the probabilistic graph edit distance (GED) of Neuhaus and Bunke [9].

Graph embedding converts a graph into an n-dimensional real vector

[Borzeshi2013] Discriminative Prototype Selection for Graph Embedding p34

[Borzeshi2012] Discriminative prototype selection methods for graph embedding p10
Cieszko Graph Based Messaging APIs – concept and implementation p8
Jouili Graph Embedding Using Constant Shift Embedding p12
Malmheden ModeGraph - A Mode-Automata Based Modelica Library for Embedded Control p86
Mu PROXIMITY-BASED GRAPH EMBEDDINGS FOR MULTI-LABEL CLASSIFICATION p11
Serratosa Graph Indexing and Retrieval based on Median Graphs p10
Torselloa Graph embedding using tree edit-union p13


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quadrangular embedding
quadrangular embedding of this graph on the torus
?

Quantum Hitting Time Embeddings of Random Graphs

[EMMS2007]

Quantum Hitting Time Embeddings of Random Graphs

?

?
?
Quasisymmetric embeddings

quadrangular embedding

quadrangular embedding of this graph on the torus

Quantum Hitting Time Embeddings of Random Graphs

[EMMS2007]

Quantum Hitting Time Embeddings of Random Graphs

?

?

Quasisymmetric embeddings

?
Quasisymmetric embeddings


Untitled Document

radial embeddings for curvilinear simultaneous embeddings of a path and an outerplanar graph
random tree embeddings for k-outerplanar graphs
Randomized Graph Embedding
Recursive Embedding

?

radial embeddings for curvilinear simultaneous embeddings of a path and an outerplanar graph

?

radial embeddings

?

random tree embeddings for k-outerplanar graphs

?

Randomized Graph Embedding

?

rectilinear embedding

?

Recursive Embedding

?
Recursive Embedding

reference node embedding

resistive distance embedding

Resistive embedding

reversible graph embeddings

?reversible graph embeddings (from a graph to points back to a graph)
reversible graph embeddings (from a graph to points back to a graph)

?

?ring embedding problem

long-ring embedding scheme
ring embedding


Untitled Document

S-tree embedding
Semi-Dynamic Graph Embedding
semi-dynamic LM language model embedding
Semi Supervised Multi Kernel (SeSMiK) Graph Embedding
Separator-Based Graph Embedding
SPHERICAL GRAPH EMBEDDING

Simultaneous Embedding

Simultaneous Geometric Embedding (SGE)

Simultaneous Geometric Graph Embeddings

Simultaneous Embedding with Fixed Edges (SEFE)

Simultaneous Embedding (SE)

Simultaneous embedding of planar graphs

Simultaneous Geometric Embedding

Geometric simultaneous embeddings

geometric simultaneous embedding of two vertex-labeled planar graphs on n vertices in the xy-plane
Spectral Distance Embedding
spectral embedding
spectral embedding
spherical embeddings
spring embedding techniques

Spring-based Graph Embedding Algorithm

spring force embedding

star embedding

structure preserving embedding (SPE)
Sub Graph Embedding
subgraph-embedding
supervised graph embedding
Surface Embeddings

straight-line embedding

straight-line plane embedding

straight-line embedding

super graph embedding
super graph embedding
We also employ graph embedding to convert Gs into the converted space ℜk super,
[Zou, Lei et al2012]
Symmetry Factored Embedding

S. T Bounded Embeddings

?

?

?

S-tree embedding

?

?

scalable embedding

scalable three-dimensional grids/tori embeddings

Scale embedding

scale embedding

self-dual embeddings

self-dual rectangular embedding

Semi definite embedding

semidefinite embedding (SDE)

Semi-Dynamic Graph Embedding

?

semi-dynamic LM language model embedding

?

seminonnegative graph embedding (RsNGE)

robust seminonnegative graph embedding (RsNGE)

?Semi-Supervised Graph Embedding

?

?

Separator-Based Graph Embedding

?Separator-Based Graph Embedding

SGE and Proximity Embedding

simultaneous embedding of planar graphs

?

?

Simultaneous Embedding

Simultaneous Embedding with Fixed Edges (SEFE)

Simultaneous Embedding (SE)

Simultaneous embedding of planar graphs

simultaneous embedding with mapping
simultaneous embedding without mapping

Colored simultaneous embedding

curvilinear simultaneous embeddings

Geometric simultaneous embeddings

geometric simultaneous embedding of two vertex-labeled planar graphs on n vertices in the xy-plane

simultaneous geometric embedding

Simultaneous Geometric Embedding
Simultaneous Geometric Embedding (SGE)
Simultaneous Geometric Graph Embeddings

?

SMACOF embedding

SMACOF embedding Scaling by Maximizing a Convex Function

Social Graph Embedding

?Distributed Social Graph Embedding

?

Distributed Social Graph Embedding

?Distributed Social Graph Embedding

?

SoCS embedding

space embeddings

?dissimilarity space embedding

?hyperbolic-space embedding

?metric space embeddings

Vector Space Embedding

Graph Classification based on Vector Space Embedding
Graph Classification based on Vector Space Embedding
Graph Classification based on Vector Space Embedding

spatial embeddings

Spectral Distance Embedding

?

spectral embedding

spectral embedding

[Baingana2013] Embedding Graphs under Centrality Constraints p54

spectral embedding

spectral hypergraph embedding technique based on the hypergraph Laplacian

?
Spectral based graph embedding
spectral embedding

Clustered Spectral Graph Embedding

?

spherical embeddings

SPHERICAL GRAPH EMBEDDING

spherical embeddings

star embedding

?

straight-line embedding

straight-line plane embedding

straight-line embedding

?
straight-line embedding

planar straight-line embedding

Plane straight-line embedding

?

structure preserving embedding (SPE)

?

[Baingana2013] Embedding Graphs under Centrality Constraints p54

structure preserving embedding algorithm

local structure preserving embedding

?
structure preserving embedding
structure preserving embedding (SPE)
Structure Preserving Embedding (SPE)
Structure Preserving Embedding (SPE) is an algorithm for embedding graphs in Euclidean space such that the embedding is low dimensional and preserves the global topological properties of the input graph.

Structured Embedding

Sub Graph Embedding

subgraph-embedding

subgraph embeddings

Sub Graph Embedding
http://alps.comp-phys.org/static/doc2.1.0/bgl_extensions/sge.html

super graph embedding

?
super graph embedding
We also employ graph embedding to convert Gs into the converted space ?k super,

[Zou, Lei et al2012]

?

supervised graph embedding

?

?

surface embedding

surface-separating embedding

?

?

?

?

?

?

?

?

Symmetry Factored Embedding

?Symmetry Factored Embedding

?


Untitled Document

Thrackle embedding

Three dimensional embedding of binary trees

Three-layer embedding

Topological embedding

In topological graph theory, an embedding (also spelled imbedding) of a graph G on a surface Σ is a representation of G on Σ in which points of Σ are associated to vertices and simple arcs (homeomorphic images of [0,1]) are associated to edges in such a way that:

  • the endpoints of the arc associated to an edge e are the points associated to the end vertices of e ,
  • no arcs include points associated with other vertices,
  • two arcs never intersect at a point which is interior to either of the arcs.

Here a surface is a compact, connected 2-manifold.

Informally, an embedding of a graph into a surface is a drawing of the graph on the surface in such a way that its edges may intersect only at their endpoints. It is well known that any graph can be embedded in 3-dimensional Euclidean space R3 and planar graphs can be embedded in 2-dimensional Euclidean space R2.

Some authors define a weaker version of the definition of "graph embedding" by omitting the non-intersection condition for edges. In such contexts the stricter definition is described as "non-crossing graph embedding".

sequential topological embedding

parallel topological embedding

?
local topology preserving embedding

?

Topology-specific graph embedding

Toroidal embeddings

toroidal embeddings of the complete graph K7 and the Petersen graph

k-regular toroidal embedding

Transductive Multi-view Embedding

Transitive embeddings
Asymmetric Transitivity Preserving Graph Embedding

http://www.kdd.org/kdd2016/subtopic/view/asymmetric-transitivity-preserving-graph-embedding/672

Tree embedding

probabilistic tree embeddings

random tree embeddings for k-outerplanar graphs

embeddings into random (dominating) trees

Tree Preserving Embedding

Triangular embedding

Trustworthy embedding

Continuity Trustworthy Graph Embedding (CTGE)

Tutte Embedding


Untitled Document

Upward embedding


Untitled Document

Variable Embedding
Variable Embedding

Variational Graph Embedding
Variational Graph Embedding
Variational Graph Embedding

Virtual Network Embedding (VNE) algorithms

Volterra embedding

Volume-respecting embedding


Untitled Document

Weighted Graph Embedding

Word embedding

Neural word embedding


Untitled Document

http://www.ebay.co.uk/itm/NEW-Mathematical-Layout-Of-A-Graph-Embedding-by-BOOK-Paperback-softback-/201194198197

Mathematical Layout Of A Graph Embedding

Publisher

LAP Lambert Academic Publishing

Date of Publication

13/03/2013

Language(s)

English

Format

Paperback / softback

ISBN-10

3659366617

ISBN-13

9783659366611

Genre

Mathematics

Publication Data

Country of Publication

United States

Imprint

LAP Lambert Academic Publishing

An important feature of an interconnection network is its ability to efficiently simulate programs written for other architectures. Such a simulation problem can be mathematically formulated as graph embedding. Graph embedding is an important technique for studying the computational capabilities of processor interconnection networks and task distributions, which is a recent focus of research in the parallel processing area. The quality of an embedding can be measured by certain cost criteria, namely dilation and wire-length (layout). Dilation is the measure for the communication time needed when simulating one network on another. The layout of a graph embedding arises from the VLSI designs, biological models that deal with cloning and visual stimuli, parallel architecture and structural engineering. In this book we give the techniques to compute the layout of a graph embedding and apply this for certain well known interconnection networks such as circulant networks, hypercubes, folded hypercubes, grid networks and generalized Petersen graphs.


Untitled Document

Abellanas, M., Garcfa, J., Hermindez, G., Noy, M., Ramos, P.: Bipartite embeddings of trees in the
plane. Discrete Appl. Math. 93(2-3), 141-148 (1999)

B. D. Acharya, S. B. Rao, and S. Arumugam, Embeddings and NP-complete
problems for graceful graphs. Labelings of Discrete Structures and Applications
(B. D. Acharya, S. Arumugam, and A. Rosa, eds.), Narosa Publishing
House, New Delhi, India (2007) 57-62.

???????????????
B. D. Acharya, S. B. Rao, and S. Arumugam, Embeddings and NP-complete
problems for graceful graphs. Labelings of Discrete Structures and Applications
(B. D. Acharya, S. Arumugam, and A. Rosa, eds.), Narosa Publishing
House, New Delhi, India (2007) 57-62.

Alam Pixel and Voxel Representations of Graphs p15
Md. Jawaherul Alam

3

in this paper, reresentation is drawing

contact representations for graphs

Pixel Representations of Graphs in 2D

Voxel Representations of Graphs in 3D

bar visibility representation

VCPGrepresentations

???????????????
[Alam,Jawaherul 2012] Alam Proportional Contact Representations of Planar Graphs p28
P8

contact representations for planar graphs

  1. representing planar graphs as contact graphs
    1. consider contact graphs with vertices represented by simple polygons in the plane with disjoint interiors, and adjacencies represented by point-contacts or side-contacts between corresponding polygons
  2. proportional contact representations for planar graphs (proportional point-contact and side-contact representations of planar graphs)
    1. In the weighted version of the problem, the input is not only a planar graph G = (V,E) but also a weight function w : V (G) → R+ that assigns a weight to each vertex. A graph G admits a proportional contact representation with the weight function w if there exists a contact representation of G, where the area of the polygon for each vertex v of G is proportional to w(v).

general planar graphs

planar 2-segment graphs,

  1. G is a 2-segment graph if it can be represented by assigning interior-disjoint line segments to vertices such that line segments share a point if and only if the corresponding vertices are adjacent, and no 3 line segments share a point
  2. maximal outer-planar graphs
  3. partial 2-trees.

A plane graph is a planar graph with a fixed embedding.

T. B. H. Albert D. Shieh, E. M. Airoldi, Tree preserving embedding, in: Proceedings of the 28th International
Conference on Machine Learning, Bellevue, WA, USA, 2011.

???????????????

okokok

[Aleardi2013] Aleardi INF562 Lecture 3 Geometric and combinatorial properties of planar graphs p92

Voronoi diagrams
planar meshes

minors

okokok

Alipanahi Guided Locally Linear Embedding p25
2011
Babak Alipanahi
David R. Cheriton School of Computer Science
http://www.psi.toronto.edu/~babak/
babak@psi.toronto.edu
sent 2016-1-22

2-dimensional embeddings
α-SupervisedLLE (α-SLLE)
Enhanced SLLE
Guided Locally Linear Embedding
Probability-based locally linear embedding
Supervised locally linear embedding

Locally linear discriminant embedding

locality-preserving embedding
low-dimensional neighborhood preserving embedding

Manifold

Kernel PCA

LLE kernel

[Ancona2009] Ancona A New Tool for Rectangular Dualization p12
p 4
straight-line plane embedding

J. Boyer, and W. Myrvold. Stop minding your P's and Q's: a simplified O(n) planar embedding algorithm . In Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms, pp. 140{146. SIAM,
Philadelphia, 1999.

Cedric Archambeau
http://www0.cs.ucl.ac.uk/staff/c.archambeau/
Honorary Senior Research Associate
Centre for Computational Statistics and Machine Learning
Department of Statistical Science and Department of Computer Science
University College London, United Kingdom
C.Archambeau@cs.ucl.ac.uk

Senior Research Scientist
Machine Learning Science
Amazon, Berlin, Germany
cedrica@amazon.com

D. Archdeacon, A Kuratowski Theorem for the projective plane, J. Graph Theory 5
(1981) 243–246.
[2] , The complexity of the graph embedding problem, in “Topics in Combinatorics
and Graph Theory,” R. Bodendiek and R. Henn (Eds.), Physica-Verlag, Heidelberg,
1990, pp. 59–64.
http://www.emba.uvm.edu/~darchdea/
dan.archdeacon@uvm.edu

okokok
Archdeacon The Pagenumber of Complete Bipartite Graphs p2

M. Arockiaraj, Paul Manuel, Indra Rajasingh and Bharati Rajan, Wirelength of 1-fault hamiltonian graphs into wheels and fans, Information Processing Letters, 111(18) (2011), 921-925.

Arockiaraj

Mathematical Layout of a Graph Embedding Paperback – March 13, 2013
by Micheal Arockiaraj (Author), Indra Rajasingh (Author)

http://www.amazon.com/Mathematical-Layout-Embedding-Micheal-Arockiaraj/dp/3659366617

Mathematical Layout of a Graph Embedding

March 13, 2013 by Micheal Arockiaraj (Author), Indra Rajasingh (Author)

Paperback: 164 pages

Publisher: LAP LAMBERT Academic Publishing (March 13, 2013)

Language: English

ISBN-10: 3659366617 ISBN-13: 978-3659366611

okokok

[ARORA2006] Expander Flows, Geometric Embeddings and Graph Partitioning p30? replied 2016-1-3

2006

okokok
ARORA Expander Flows Geometric Embeddings and Graph Partitioning p30
S. Arora, S. Rao, U. Vazirani, Expander flows, geometric embeddings and graph partitioning, J. ACM 56 (2009) article 5.
S. Arora, S. Rao, and U.V. Vazirani. Expander flows, geometric embeddings and graph partitioning. In Symposium on Theory of Computing, 2004.

SANJEEV ARORA
https://www.cs.princeton.edu/~arora/
Charles C. Fitzmorris Professor of Computer Science
Princeton University
Sanjeev Arora photo??????????

My research area is Theoretical Computer Science. Specific topics that I have worked on: Computational Complexity (see my book on this topic), Probabilistically Checkable Proofs (PCPs), computing approximate solutions to NP-hard problems, geometric embedding of metric spaces, unique games conjecture, complexity of financial derivatives, provable bounds for Machine Learning. See my group website.

Computer Science Dept,
35 Olden St
Princeton NJ 08540
609-258-3869 (but don't leave a msg; send email instead)
609-258-4562 (Ms Mitra Kelly; Admin. Assistant)
609-258-1771 (Fax)
email address image
While on sabbatical in Spring 2013 I started a travelogue that I still maintain.
arora@cs.princeton.edu

Geometric Embeddings
metric embeddings
metric space embeddings
natural embedding
near-optimal embedding
Quasisymmetric embeddings

clustering
mapping

Graph Partitioning
graph conductance

Graph partitions or separators

expansion
expander
expander flow.
edge expansion
graph expansion,

graph separators
balanced separator

Markov chains
divide and conquer approaches
Riemannian manifolds
conductance and the eigenvalue gap of the Laplacian:
Ellipsoid method

semidefinite programs
semidefinite relaxation

sparsest cut
normalized or sparsest cut

measure concentration.
dilation
congestion.

multicommodity flows

=========================
2016-1-2

Dear Prof Arora,

I am honored to have read your paper “Expander Flows Geometric Embeddings and Graph Partitioning” and several of similar papers of yours, for I happen to be interested in the graph theoretic aspects of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, spin-based computing etc). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the generation of the netlist.

I am not an established graphtheorist, rather, an independent and self taught researcher in this field. Nobody knows my work, nothing has been published out of my hands, although I have prepared hundreds of papers and dozens of books or study notes in this and many other fields.

I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, graph embedding is understood as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant and corrupt. They ignore people like me who have no decent position in their system. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Therefore I need to have contacts with the external academic circles to communicate my ideas and to know what others are doing and thinking about. I want to know if you are interested in joining this circle or not.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:
new:
https://sites.google.com/site/markchenstudio/
old:
https://sites.google.com/site/markchen0088/

==================================
2016-1-3

I wish you luck, but sorry I can't be part of your planned discussion circle. I suggest stackexchange or other online resources.

okokok
Tetsuo Asano
[Asano2007] A Linear-Space Algorithm for Distance Preserving Graph Embedding p23
Asano A Linear-Space Algorithm for Distance Preserving Graph Embedding p23
Asano A Linear-Space Algorithm for Distance Preserving Graph Embedding p23
2007
Tetsuo Asano
http://www.jaist.ac.jp/~t-asano/e-index.htm
t-asano@jaist.ac.jp

Distance Preserving Graph Embedding
global optimal embedding
isomap embedding
locally linear embedding (LLE)
low-distortion embeddings
LSMDS embedding
MDS embedding
PCO embedding
SMACOF embedding Scaling by Maximizing a Convex Function

dimensionality reduction
Multi-Dimensional Scaling (MDS)
anchored MDS
least-squares multi-dimensional scaling

Asano Linear-Space Algorithms for Distance Preserving Embedding p4

Tetsuo Asano, Prosenjit Bose, Paz Carmi, Anil Maheshwari, Chang Shu, Michiel Smid, and Stefanie Wuhrer. Linear-space algorithm for distance preserving graph embedding with applications. In Proceedings of the 19th Canadian Conference on Computational Geometry, pages
185{188, 2007.
Tetsuo Asano, Prosenjit Bose, Paz Carmi, Anil Maheshwari, Chang Shu, Michiel Smid, and Stefanie Wuhrer. Linear-space algorithm for distance preserving graph embedding with applications. In Proceedings of the 19th Canadian Conference on Computational Geometry, pages 185{188, 2007.
2007

[Auletta1992]

Auletta Embedding graphs onto the Supercube p12

okokok

[Azary2014] Grassmann Learning for Recognition and Classification p132
Sherif Azary
1-1-2014

Dr. Andreas Savakis, Professor, Department of Computer Engineering, RIT
https://www.rit.edu/kgcoe/staff/andreas-savakis
https://people.rit.edu/axseec/
axseec@rit.edu
andreas.savakis@rit.edu
2016-6-7

Dr. Nathan D. Cahill, Associate Professor, School of Mathematical Sciences, RIT

Dr. Shanchieh J. Yang, Associate Professor & Department Head, Department of Computer Engineering, RIT

Dr. Richard Zanibbi, Associate Professor, Department of Computer Science, RIT

Dr. Dhireesha Kudithipudi, Associate Professor, Department of Computer Engineering, RIT

embedding data onto Riemannian manifolds

2D embeddings
3D embedding
GRASP embeddings Grassmannian Spectral Regression
Grassmann based graph embedding framework
isometric embedding

  1. weighted isometric embeddings

Kernel Embedding
linear extensions of graph embedding (LGE)
locally linear discriminant embedding
neighbor embedding
neighborhood preserving embedding (NPE)
orthogonal embedding

3.3 Locally Linear Embedding ..................................................................................... 35

Locally Linear Embedding (LLE) is an unsupervised eigenvector method for dimensionality reduction that preserves the embedding of high dimensional data through maximal discrimination in the lower dimensional space.

3.4 Linear Extensions of Graph Embedding ................................................................. 38

Linear Extensions of Graph Embedding (LGE) methods are eigen-based linearized techniques to solve linear approximations of non-linear systems through dimensionality reduction. They include linear discriminant analysis (LDA) [70], locality preserving projections (LPP) [71], and neighborhood preserving embedding (NPE) [72].

Manifold learning
Grassmann learning
Grassmannian Sparse Representation (GSR)
Grassmann manifolds
Grassmannian Spectral Regression (GRASP)
Riemann and Grassmann manifolds
Riemannian manifold
Grassmann manifolds


Untitled Document

????????????

Mihai Badoiu, Kedar Dhamdhere, Anupam Gupta, Yuri Rabinovich, Harald Racke, R. Ravi, and Anastasios Sidiropoulos. Approximation algorithms for low-distortion embeddings into low dimensional spaces. In SODA '05: Proceedings of the sixteenth annual ACM-SIAM symposium on Discrete algorithms, pages 119{128, 2005.

Badoiu Low dimensional embedding with extra information p10

[Badoiu2007] Ordinal Embedding Approximation Algorithms and Dimensionality Reduction p11
[Badoiu2007] Ordinal Embedding Approximation Algorithms and Dimensionality Reduction p14

4

isometric embedding

low-dimensional embeddings

metric embeddings

contractive metric embedding

expansive metric embedding

optimal-distortion metric embeddings

ordinal embedding

[Badoiu2004] Low-Dimensional Embedding with Extra Information p10

Mihai Badoiu, Erik D. Demaine, Mohammad Taghi Hajiaghayi, and Piotr Indyk. Low dimensional embedding with extra information. In SCG '04: Proceedings of the twentieth annual symposium on Computational geometry, pages 320{329, 2004.

4

computational geometry

multi-dimensional scaling

additive-distortion embedding

additive-error embeddings

okokok

[Bai2004] Heat Kernels Manifolds and Graph Embedding p9
Bai Heat Kernels, Manifolds and Graph Embedding p9
Xiao Bai

class prototype

Laplacian

graph Laplacian
normalised Laplacian
Laplacian eigenmap
Laplacian matrix
Laplacian eigensystem
eigensystem
principal eigenvectors
spectral decomposition
spectral decomposition on the graph Laplacian

Gaussian form
Gaussian function of the geodesic distance between nodes

geodesic distance
geodesic distance between nodes

space
pattern space
Riemannian space
neighborhood hypersphere in the embedding space

manifold

Riemannian Manifolds
global geometry of the manifold
manifold learning theory
geodesic distance between nodes on a manifold

Clustering

pairwise clustering methods
pairwise clustering methods to the edit distance between graphs
Central clustering

Vector

graph feature vectors
Fiedler-vector
pattern vectors
embedded vector of co-ordinates
principal eigenvectors

matrix

Laplacian matrix
Laplacian matrix L = D – A
normalised Laplacian is given by ?L = D?12LD?12

eigenvalues of the Laplacian matrix
spectral decomposition of the normalised Laplacian matrix

adjacency matrix
adjacency matrix A for the graph where
A(u, v) =1 if(u, v) ∈ E0 otherwise

adjacency weight matrix
dissimilarity matrix
covariance matrix
weighted proximity matrix
diagonal degree matrix
D, whose elements are given by
D(u, u) =v∈V A(u, v)

matrix of geodesic distances

Graph

heat kernel of the graph
The heat kernel of the graph is found by exponentiating the resulting eigensystem over time.
spectral heat kernel
spectral heat kernel and its Gaussian form
heat-equation

nearest neighbor graph
topology of the graph
edit distance between graphs
path length distribution on the graph
negative squared-distance between nodes.
simplicial complex of the graph
sets of shock graphs

graph-spectra
graph genus
local connectivity

class prototype

trees

direct spectral analysis of trees
shock trees
co-spectrality of the trees

Embedding

embedding space
PCA
principal components analysis
ISOMAP
multidimensional scaling
locally linear embedding
low distortion embedding of the geodesic distance
graphs embedded in manifolds
use of heat kernels as a means of embedding graphs in a pattern space.
embed the trees in a Euclidean space using multidimensional scaling
computing distance via embedding
heat kernel can be used for the purposes of embedding graphs, and in particular trees, on a low dimensional manifold.

Dijkstra’s algorithm
Dijkstra’s algorithm is used to compute the shortest(geodesic) distances between nodes

okokok

B. Baingana, and G. B. Giannakis, “Centrality-constrained graph embedding," Proc. of the IEEE Intl. Conf. on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26 - 31, 2013.

[Baingana2013a] CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5
Baingana CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5

Brian Baingana
https://sites.google.com/site/bbaingana/research
http://www.tc.umn.edu/~baing011/
baing011@umn.edu

graph embedding approach with centrality considerations to comply with node hierarchy

graph drawing

Visual rendering of graphs

embedding graphs for visualization

Graphs encoding

graph smoothness

edge crossing

node centrality structure

block coordinate descent iterations

degree centrality

MDS
constrained multi-dimensional scaling (MDS)

Betweenness centrality

closeness

eigenvalue

KKT point

k-core decomposition

okokok
[Baingana2013b] Embedding Graphs under Centrality Constraints p54

Brian Baingana

9

A THESIS
SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL
OF THE UNIVERSITY OF MINNESOTA
BY
Brian Baingana
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF MASTER OF SCIENCE
Professor Georgios B. Giannakis, Advisor
May 2013

Georgios B. Giannakis
http://spincom.umn.edu/georgios/
ADC Chair in Wireless Telecommunications
Dept. of Electrical and Computer Engr.
University of Minnesota
200 Union Street SE
Minneapolis, MN 55455
Tel: (612) 626-7781
Fax: (612) 625-4583
georgios@umn.edu

Nikos Sidiropoulos
http://www.ece.umn.edu/~nikos/
Professor,
ADC Chair in Digital Technology
Dept. of Electrical & Computer Engineering
& Digital Technology Center
University of Minnesota
DTC office: 481 Walter Library
ECE office: 6-179 Keller Hall
Phone: +1 (612) 625 1242
Mailing address:
Dept. ECE, University of Minnesota,
200 Union St. SE, Minneapolis, MN 55455
e-mail: nikos@umn.edu

George Karypis
http://glaros.dtc.umn.edu/gkhome/index.php
karypis@cs.umn.edu

US Postal address:
4-192 EE/CS Building
200 Union Street SE
Minneapolis, MN 55455
Office locations:
CS: 4-203 EE/CS Building
DTC:???? 480 Walter Library
Phones:
CS: (612) 626-7524
DTC:???? (612) 625-8144
Fax:
CS: (612) 625-0572

  1. …graph embedding associates each vertex with a set of coordinates in low-dimensional Euclidean space.
  2. In addition to network visualization, graph embedding algorithms compress network data and provide a way to geometrically solve some computationally hard problems.

connectivity graph

Concentric graph layouts
community browsing in graphs
Visual rendering of graphs
graph drawing algorithms
graph adjacency matrix

Embedding graphs by dimensionality reduction
adapt MDS and LLE to the centrality-constrained graph embedding
spectral embedding
structure preserving embedding algorithm

Principal component analysis (PCA)

Eigenvalue
leading eigenvectors

Laplacian eigenmaps
spectral decomposition of the graph Laplacian

multi-dimensional scaling (MDS)
constrained multi-dimensional scaling (MDS)
Centrality-constrained MDS

Nonlinear manifold
manifold learning approaches

locally-linear embedding (LLE) algorithm
centrality-constrained LLE problem
Hessian LLE

block coordinate descent iterations with successive approximations
Kuhn-Tucker (KKT) point

leading component vectors

mapping of complex network data

centrality - network centrality
Degree centrality
Closeness centrality
Betweenness centrality
Markov centrality

node dissimilarity
Shared neighbors
Graph-theoretic distances

node hierarchy

closeness

betweenness

Visual analytics based approaches

unsupervised machine learning
Nonlinear manifold learning algorithms
dimensionality reduction approaches from machine learning

semidefinite program
nearest neighbor algorithm

geodesic distance (lowest sum of edge weights)

Bibliography
[3] B. Luo, R. C. Wilson, and E. R. Hancock, \Spectral embedding of graphs," Pattern
Recognition, vol. 36, pp. 2213{2230, January 2003.
[8] J. Abello, F. V. Ham, and N. Krishnan, \ASK-GraphView : A large scale graph
visualization system," IEEE Transactions on Visualization and Computer Graphics,
vol. 12, pp. 669{676, September 2006.
[11] F. V. Ham and M. Wattenberg, \Centrality based visualization of small world graphs,"
Computer Graphics Forum, vol. 27, pp. 975{982, May 2008.
[12] E. Giacomo, W. Didimo, L. Grilli, and G. Liotta, \Graph visualization techniques for
web clustering engines," IEEE Transactions on Visualization and Computer Graphics,
vol. 13, pp. 294{304, March 2007.
[14] J. Ignatowicz, \Drawing force-directed graphs using optigraph," Proceedings of DI-
MACS International Workshop, vol. 894, pp. 333{336, October 1994.
[15] A. Papakostas and I. Tollis, \Algorithms for area-efficient orthogonal drawings," Com-
putational Geometry: Theory and Applications, vol. 9, pp. 83{110, January 1998.
[19] T. Biedl and G. Kant, \A better heuristic for orthogonal graph drawings," Proceed-
ings of the Second Annual European Symposium on Algorithms, vol. 855, pp. 24{35,
September 1994.
[20] D. Tunkelang, \A numerical optimization approach to general graph drawing," PhD
Thesis, Carnegie Mellon University School of Computer Science, January 1999.
[21] T. Fruchterman, and E. Reingold, "Graph drawing by force-directed placement," Soft-
ware Practice and Experience, vol. 21, pp. 1129-1164, November 1991.
[33] T. Kamada and S. Kawai, \An algorithm for drawing general undirected graphs,"
Information Processing Letters, vol. 31, pp. 7{15, April 1989.
[36] D. De Ridder, O. Kouropteva, O. Okun, M. Pietikainen, and R. Duin, \Supervised locally
linear embedding," Artificial Neural Networks and Neural Information Processing-
ICANN/ICONIP, pp. 175{175, June 2003.
[37] H. Chang and Y. Dit-Yan, \Robust locally linear embedding," Pattern Recognition,
vol. 39, pp. 1053{1065, June 2006.
[47] B. Baingana, and G. B. Giannakis, \Centrality-constrained graph embedding," Proc.
of the IEEE Intl. Conf. on Acoustics, Speech and Signal Processing, Vancouver, Canada,
May 26 - 31, 2013. BIBLIOGRAPHY 43

H.-J. Bandelt, V. Chepoi, Decomposition and l1-embedding of weakly median graphs, Europ. J. Combin. 21 (2000), 701{714.
Hans-J?urgen Bandelt
http://www.math.uni-hamburg.de/home/bandelt/
bandelt@math.uni-hamburg.de

Okokok

Bandelt Metric graph theory and geometry a survey p30?

Bandelt Metric graph theory and geometry a survey p30
Bandelt Metric graph theory and geometry a survey p30

Canonical isometric embedding
near-isometric embedding
canonical embedding
scale embedding

l1-embedding

Battista

Graph Drawing: Algorithms for the Visualization of Graphs

Di Battista G.
http://www.dia.uniroma3.it/~compunet/www/view/person.php?id=gdb
gdb@dia.uniroma3.it

This book is designed to describe fundamental algorithmic techniques for constructing drawings of graphs. Suitable as a book or reference manual, its chapters offer an accurate, accessible reflection of the rapidly expanding field of graph drawing.

[Behzadi1999]

Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow a Java Environment for Graph Drawing p144
Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow: a Java Environment for Graph Drawing p144
Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow a Java Environment for Graph Drawing p144

Lila Behzadi
Lila Behzadi
Lila Behzadi

drawing undirected graphs

  1. force-directed placement
    1. Spring-based algorithms
  2. virtual physical models

graph-Eudidean and graphtheoretic distances between pairs of vertices, referred to as the KK algorithm

Eades algorithms
FR algorithms
GEM algorithms
Graphlet version of KK

VGJ - is a graph drawing software
Brown University's Graph Drawing Server : GDS
Tom Sawyer Software’s GRAPH LAYOUT TOOLKIT(GLT) and GRAPH EDITOR TOOLKIT(GET)

[3] G. Di Battista, P. Eades, R Tam8ssia1 and 1. G. Tollis. Algorithm for drawing graphs: An annotated bibiiography. Computational Gwmetry: Theory and Appiicatio ns, 4:235-282, 1994.
[4] G.D. Battista, P. Eades, R Tamassia, and I.G. Tollis. Gmph Dmwing Algo&hms
for the Visuolization of Cmphs. Prentice Haii, New Jersey, 1999.

[Bein2000]

Bein Three dimensional embedding of binary trees p8

__ ________ ______
__ ________ ______

[Bekos2013]
Bekos Smooth Orthogonal Layouts p21

okokok

[Belkin2001] Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering p7 2016-1-4 ???

????????????????????????

[Belkin2000] Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering p7
[Belkin2000] “Laplacian Eigenmaps and spectral techniques for embedding and clustering,” in Adv. Neural Inform. Proc. Syst. 14, 2001, pp. 585-591.

M. Belkin and P. Niyogi, "Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering," in Advances in Neural Information Processing Systems, Vancouver, British Columbia, Canada, 2002.
Mikhail Belkin
http://web.cse.ohio-state.edu/~mbelkin/
Associate Professor
Department of Computer Science and Engineering
Department of Statistics (courtesy)
Center for Cognitive Science

The Ohio State University,
Computer Science and Engineering,
2015 Neil Avenue, Dreese Labs 597.
Columbus, OH 43210 [map]
phone: 614-292-5841
email:
mbelkin@cse.ohio-state.edu

one-dimensional embedding
m-dimensional embedding

graph Laplacian

Laplace Beltrami operator on a manifold

Laplacian operator in providing an optimal embedding

Laplacian Eigenmap algorithm

==========================
2016-1-4

Dear Prof Belkin,

I am honored to have read your paper “Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering” and several of similar papers of yours, for I happen to be interested in the graph theoretic aspects of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, spin-based computing etc). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the generation of the netlist.

I am not an established graphtheorist, rather, an independent and self taught researcher in this field. Nobody knows my work, nothing has been published out of my hands, although I have prepared hundreds of papers and dozens of books or study notes in this and many other fields.

I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, graph embedding is understood as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant and corrupt. They ignore people like me who have no decent position in their system. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Therefore I need to have contacts with the external academic circles to communicate my ideas and to know what others are doing and thinking about. I want to know if you are interested in joining this circle or not.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:
new:
https://sites.google.com/site/markchenstudio/
old:
https://sites.google.com/site/markchen0088/

okokok
Berchenko Graph Embedding through Random Walk for Shortest Paths Problems p14

okokok

[Berchenko2009] Graph Embedding through Random Walk for Shortest Paths Problems p14

probabilistic technique of embedding graphs in Zd, the d-dimensional integer lattice, in order to find the shortest paths and shortest distances between pairs of nodes

prof.dr. M.T. de Berg
faculteit Wiskunde & Informatics
Technische Universiteit Eindhoven
https://www.tue.nl/universiteit/faculteiten/wiskunde-informatica/de-faculteit/medewerkers/detail/ep/e/d/ep-uid/20022349/
m.t.d.berg@tue.nl
http://www.cs.uu.nl/staff/markdb.html
http://www.win.tue.nl/~mdberg/
m.t.d.berg@tue.nl

Bhatel Automated Mapping of Structured Communication Graphs onto Mesh Interconnects p17

[Bhatel2009] Automated Mapping of Structured Communication Graphs onto Mesh Interconnects p17

mapping 2D object graphs to 2D and 3D processor graphs

topology aware mapping

[11] S. N. Bhatt, F. T. Leighton, A framework for solvingVLSI graph layout problems,
J. Comput. Syst. Sci. 28 (1984) 300–343.

S. N. Bhatt, F. R. K. Chung, F. T. Leighton, A. L. Rosenberg, Efficient embeddings
of trees in hypercubes, SIAM J. Comput. 21 (1992) 151–162.

Biedl Bounds for Orthogonal 3-D Graph Drawing p17
https://cs.uwaterloo.ca/~biedl/
biedl@uwaterloo.ca

[Biedl1999] Bounds for Orthogonal 3-D Graph Drawing p17

how the volume depends on the maximum number of bends permitted per edge

V=f(B)

V - the volume of the bounding box in 3-D orthogonal grid drawings for graphs of arbitrary degree

B -the maximum number of bends permitted per edge in 3-D orthogonal grid drawings for graphs of arbitrary degree

Any simple graph G on n vertices is a subgraph of the complete graph Kn.

Thus, a drawing of Kn immediately provides a drawing for G by deleting irrelevant edges.

Consequently, upper bounds for Kn yield upper bounds for all other simple graphs on n vertices.

Furthermore, no simple graph on n vertices can yield larger lower bounds than Kn.

embedding a graph in a rectangular grid

4

D. Bienstock and C. L. Monma. On the complexity of embedding planar graphs
to minimize certain distance measures. Algorithmica, 5(1):93–109, 1990. 357
http://ieor.columbia.edu/daniel-bienstock-0
dano@ieor.columbia.edu
http://www.columbia.edu/~dano/
dano@columbia.edu

T. Blasius, S. G. Kobourov, and I. Rutter. Simultaneous embedding of
planar graphs. In Handbook of Graph Drawing and Visualization. Chapman
and Hall/CRC, 2013. arXiv:http://arxiv.org/abs/1204.5853.

[Blasius2013.] Simultaneous Embedding of Planar Graphs p34

graph drawing

layout of a single graph

simultaneous graph drawing

layout of multiple related graphs

drawing a series of graphs that share all, or parts of the same vertex set

The graphs may represent different relations between the same set of objects

the graphs may be the result of a single relation that changes through time.

In simultaneous graph embedding, vertices are placed in the exact same locations in all the graphs, while the layout of the edges may differ.

Simultaneous Geometric Embedding (SGE)

Simultaneous Embedding with Fixed Edges (SEFE)

Simultaneous Embedding (SE)

7

[Bondy2008] Graph Theory 2008 p654
J.A. Bondy

One of the dramatic developments over the past thirty years has been the creation of the theory of graph minors by G. N. Robertson and P. D. Seymour. In a long series of deep papers, they have revolutionized graph theory by introducing an original and incisive way of viewing graphical structure. Developed to attack a celebrated conjecture of K. Wagner, their theory gives increased prominence to embeddings of graphs in surfaces.

A graph which can be drawn in the plane in such a way that edges meet only at points corresponding to their common ends is called a planar graph, and such a drawing is called a planar embedding of the graph.

Such a drawing is called an embedding of the graph on the surface.

embedding of the Shrikhande graph on the torus

An embedding of a graph F in a graph G is an isomorphism between F and a subgraph of G

The Circular Embedding Conjecture

This suggests one natural approach to the Cycle Double Cover Conjecture: find a suitable embedding of the graph on some surface, an embedding in which each face is bounded by a cycle; the facial cycles then form a cycle double cover.

the toroidal embeddings of the complete graph K7 and the Petersen graph

Unique Plane Embeddings

The Orientable Embedding Conjecture

planar embedding

A thrackle is a graph embedded in the plane in such a way that any two edges intersect exactly once (possibly at an end). Such an embedding is called a thrackle embedding

We note that the same proof serves to show that every simple 3-connected planar graph admits a convex embedding, that is, a planar embedding all of whose faces are bounded by convex polygons.

A straight-line embedding of G is an embedding of G in the plane in which each edge is a straight-line segment.

An embedding ?Gof a graph G on a surface Σ is a cellular embedding if each of the arcwise-connected regions of Σ \ ?G is homeomorphic to the open disc.

Dual embeddings

circular embedding

The Orientable Embedding Conjecture

quadrangular embedding of this graph on the torus

[Bondy2008] Graph theory 2008 p666

Bonningtong Graphs embedded in the plane with finitely many accumulation points p13

http://www.bonnington.org/research.html
paul.bonnington@monash.edu

Silvano Bordignon
http://homes.stat.unipd.it/silvanobordignon/

2016-5-11

Karsten Borgwardt
https://www.bsse.ethz.ch/mlcb/karsten/profile-karsten.html
Karsten Borgwardt
Main content
Karsten Borgwardt
ETH Zurich
Dep. Biosysteme
Prof. Dr. Karsten M. Borgwardt
BSB G 4
Mattenstrasse 26
4058 Basel
Switzerland
karsten.borgwardt@bsse.ethz.ch
K. Borgwardt. Graph Kernels. PhD thesis, Ludwig-Maximilians-University
Munich, 2007.

K. Borgwardt, C. Ong, S. Sch¨onauer, S. Vishwanathan, A. Smola, and H.-
P. Kriegel. Protein function prediction via graph kernels. Bioinformatics,
21(1):47–56, 2005.

K. Borgwardt and H.-P. Kriegel. Shortest-path kernels on graphs. In Proc.
5th Int. Conference on Data Mining, pages 74–81, 2005.

?

[Borzeshi2011] A discriminative prototype selection approach for graph embedding in human action recognition p7

[Borzeshi2011] A discriminative prototype selection approach for graph embedding in human action recognition p7

Borzeshi A discriminative prototype selection approach for graph embedding in human action recognition p7

http://www.uts.edu.au/staff/ehsan.zareborzeshi
Ehsan.ZareBorzeshi@uts.edu.au

?

transforming the graphs into a vector space by means of graph embedding

graph embedding, converting a graph into a point in a vector space

prototype-based graph embedding

“prototype” graphs

selection of a suitable set of prototypes

discriminative approach outperforms well-established class-based prototype selection methods such as center, border and random prototype selection.

a graph is converted to an n-dimensional feature vector by way of a set of “prototype” graphs and a dissimilarity measure (often, a graph edit distance): the feature vector consists of the distances between the graph and each prototype.

error-tolerant graph matching

graph edit distance (GED)

In the literature, “graph embedding” refers interchangeably to the embedding of a graph as a whole into a point in vector space, or the embedding of its set of nodes into a set of corresponding points in vector space.

Prototype-based embedding is certainly the simplest and fastest embedding approach

embedding the graph into a feature vector by means of P-GED with the prototype set of choice

discriminative prototype selection method

3

prototype-based graph embedding
“prototype” graphs

Laplacian eigenmaps
Commute times
symmetric polynomials
kernel principal component analysis, amongst others

graph edit distance
probabilistic graph edit distance (P-GED)
graph domain
attributed graph
graph matching

transforming the graphs into a vector space by means of graph embedding

graph embedding, converting a graph into a point in a vector space

prototype-based graph embedding

“prototype” graphs

selection of a suitable set of prototypes

discriminative approach outperforms well-established class-based prototype selection methods such as center, border and random prototype selection.

a graph is converted to an n-dimensional feature vector by way of a set of “prototype” graphs and a dissimilarity measure (often, a graph edit distance): the feature vector consists of the distances between the graph and each prototype.

error-tolerant graph matching

graph edit distance (GED)

In the literature, “graph embedding” refers interchangeably to the embedding of a graph as a whole into a point
in vector space, or the embedding of its set of nodes into a set of corresponding points in vector space.

Prototype-based embedding is certainly the simplest and fastest embedding approach

embedding the graph into a feature vector by means of P-GED with the prototype set of choice

discriminative prototype selection method

3

[1] M. Belkin and P. Niyogi. Laplacian Eigenmaps for Dimensionality Reduction and Data Representation. Neural Computation, 15(6):1373–1396, June 2003. 2

[2] J. Blackburn and E. Ribeiro. Human motion recognition using isomap and dynamic time warping. In Proceedings of the 2nd conference on Human motion: understanding, modeling, capture and animation, pages 285–298, Berlin, Heidelberg, 2007. Springer-Verlag.

[3] E. Z. Borzeshi, R. Y. D. Xu, and M. Piccardi. Automatic human action recognition in videos by graph embedding. In 16th International Conference on Image Analysis and Processing, ICIAP 2011, 2011. 4

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[6] P. Dollar, V. Rabaud, G. Cottrell, and S. Belongie. Behavior recognition via sparse spatio-temporal features. In Visual Surveillance and Performance Evaluation of Tracking and Surveillance, 2005. 2nd Joint IEEE International Workshop on, pages 65–72. IEEE, 2006.

[7] D. Emms, R. Wilson, and E. Hancock. Graph embedding using quantum commute times. Graph-Based Representations in Pattern Recognition, pages 371– 382, 2007.

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[9] K. Guo, P. Ishwar, and J. Konrad. Action Recognition Using Sparse Representation on Covariance Manifolds of Optical Flow.

[10] G. Hjaltason and H. Samet. Properties of embedding methods for similarity searching in metric spaces. IEEE Transactions on Pattern Analysis and machine intelligence, pages 530–549, 2003.

[11] I. Laptev. On space-time interest points. International Journal of Computer Vision, 64(2):107–123, 2005. 1

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[14] M. Neuhaus and H. Bunke. A probabilistic approach to learning costs for graph edit distance. In Pattern Recognition, 2004. ICPR 2004. Proceedings of the 17th International Conference on, volume 3, pages 389–393. IEEE, 2004. 2

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[17] E. Pekalska and R. Duin. The dissimilarity representation for pattern recognition: foundations and applications. World Scientific Pub Co Inc, 2005. 1, 2, 3

[18] H. Qiu and E. Hancock. Clustering and embedding using commute times. IEEE Transactions on Pattern Analysis and Machine Intelligence, 29(11):1873– 1890, 2007. 2

[19] A. Quattoni, S. Wang, L. p Morency, M. Collins, T. Darrell, and M. Csail. Hidden-state conditional random fields. In IEEE Transactions on Pattern Analysis and Machine Intelligence, 2007. 1

[20] L. Rabiner. A tutorial on hidden Markov models and selected applications in speech recognition. Proceedings of the IEEE, 77(2):257–286, 1989. 3, 5

[21] K. Rieck and P. Laskov. Linear-Time Computation of Similarity Measures for Sequential Data. Journal of Machine Learning Research, 9:23–48, Jan. 2007. 2

[22] K. Riesen, M. Neuhaus, and H. Bunke. Graph embedding in vector spaces by means of prototype selection. In Proceedings of the 6th IAPR-TC-15 international conference on Graph-based representations in pattern recognition, pages 383–393. Springer-Verlag, 2007. 1, 2, 3, 4

[23] M. Rodriguez, J. Ahmed, and M. Shah. Action mach a spatio-temporal maximum average correlation height filter for action recognition. In Computer Vision and Pattern Recognition, 2008. CVPR 2008. IEEE Conference on, pages 1–8. IEEE, 2008. 1, 3

[24] C. Rother, V. Kolmogorov, and A. Blake. Grabcut: Interactive foreground extraction using iterated graph cuts. ACM Transactions on Graphics, 23:309–314, 2004. 6

[25] B. Scholkopf, A. Smola, and K.-R. Muller. Nonlinear Component Analysis as a Kernel Eigenvalue Problem. Neural Comp., 10(5):1299–1319, July 1998. 2

[26] C. Schuldt, I. Laptev, and B. Caputo. Recognizing human actions: a local SVM approach. In Pattern Recognition, 2004. ICPR 2004. Proceedings of the 17th International Conference on, volume 3, 2004. 1, 3, 4, 5

[27] Q. Shi, L.Wang, L. Cheng, and A. Smola. Discriminative human action segmentation and recognition using semi-markov model. In Computer Vision and Pattern Recognition, 2008. CVPR 2008. IEEE Conference on, 2008. 5

[28] S. Singh, S. Velastin, and H. Ragheb. Muhavi: A multicamera human action video dataset for the evaluation of action recognition methods. In Advanced Video and Signal Based Surveillance (AVSS), 2010 Seventh IEEE International Conference on, pages 48– 55. IEEE, 2010. 1, 3

[29] C. Sutton and A. McCallum. 1 an introduction to conditional random fields for relational learning. Introduction to statistical relational learning, page 93, 2007. 5

[30] A. Vedaldi and B. Fulkerson. VLFeat: An open and portable library of computer vision algorithms, 2008. 3

[31] R. Wilson, E. Hancock, and B. Luo. Pattern vectors from algebraic graph theory. IEEE Transactions on Pattern Analysis and Machine Intelligence, pages 1112–1124, 2005. 1, 2

[32] J. Yamato, J. Ohya, and K. Ishii. Recognizing human action in time-sequential images using hidden Markov model. In Computer Vision and Pattern Recognition, 1992. Proceedings CVPR ’92., 1992 IEEE Computer Society Conference on, pages 379–385, 1992. 1

?

[1], [18], [25].
[17] [31] [22] [7]

[1] M. Belkin and P. Niyogi. Laplacian Eigenmaps for Dimensionality Reduction and Data Representation.
Neural Computation, 15(6):1373–1396, June 2003. 2
[7] D. Emms, R. Wilson, and E. Hancock. Graph embedding using quantum commute times. Graph-Based Representations in Pattern Recognition, pages 371–382, 2007. 1
[17] E. Pekalska and R. Duin. The dissimilarity representation for pattern recognition: foundations and applications. World Scientific Pub Co Inc, 2005. 1, 2, 3
[18] H. Qiu and E. Hancock. Clustering and embedding using commute times. IEEE Transactions on Pattern Analysis and Machine Intelligence, 29(11):1873– 1890, 2007. 2
[22] K. Riesen, M. Neuhaus, and H. Bunke. Graph embedding in vector spaces by means of prototype selection. In Proceedings of the 6th IAPR-TC-15 international conference on Graph-based representations in pattern recognition, pages 383–393. Springer-Verlag, 2007. 1,2, 3, 4
[25] B. Scholkopf, A. Smola, and K.-R. Muller. Nonlinear Component Analysis as a Kernel Eigenvalue Problem. Neural Comp., 10(5):1299–1319, July 1998. 2
[31] R. Wilson, E. Hancock, and B. Luo. Pattern vectors from algebraic graph theory. IEEE Transactions
on Pattern Analysis and Machine Intelligence, pages 1112–1124, 2005. 1, 2

[Borzeshi2010] Automatic human action recognition in videos by graph embedding p10
[Borzeshi2010] Automatic human action recognition in videos by graph embedding p10
[Borzeshi2010] Automatic human action recognition in videos by graph embedding p10

E. Z. Borzeshi, R. Y. D. Xu, and M. Piccardi. Automatic human action recognition in videos by graph embedding. In 16th International Conference on Image Analysis and Processing, ICIAP 2011, 2011.

graph embedding to convert the graph into a suitable feature vector.

using graph embedding for obtaining a more suitable feature set.

An alternative to the direct comparison of action graphs is offered by graph embedding: in each frame, the graph representing the actor’s shape can be converted to a finite set of distances from prototype graphs, and the distance vector
then used with conventional statistical classifiers.

With an adequate prototype set, we convert the graph to a set of distances based on the probabilistic graph edit distance (GED) of Neuhaus and Bunke [9].

Graph embedding converts a graph into an n-dimensional real vector

E. Z. Borzeshi, R. Y. D. Xu, and M. Piccardi. Automatic human action recognition in videos by graph embedding. In 16th International Conference on Image Analysis and Processing, ICIAP 2011, 2011.

graph embedding to convert the graph into a suitable feature vector.

using graph embedding for obtaining a more suitable feature set.

An alternative to the direct comparison of action graphs is offered by graph embedding: in each frame, the graph representing the actor’s shape can be converted to a finite set of distances from prototype graphs, and the distance vector
then used with conventional statistical classifiers.

With an adequate prototype set, we convert the graph to a set of distances based on the probabilistic graph edit distance (GED) of Neuhaus and Bunke [9].

Graph embedding converts a graph into an n-dimensional real vector

[Borzeshi2012] Discriminative prototype selection methods for graph embedding p10
Borzeshi Discriminative prototype selection methods for graph embedding p10
Borzeshi Discriminative prototype selection methods for graph embedding p10

?

[Borzeshi2013] Discriminative Prototype Selection for Graph Embedding p34

[Borzeshi2013] Discriminative Prototype Selection for Graph Embedding p34

[Borzeshi2013] Discriminative Prototype Selection for Graph Embedding p34

Borzeshi Discriminative Prototype Selection for Graph Embedding p34

Prosenjit Bose
http://jitbose.ca/
jit@scs.carleton.ca

Bose, P.: On embedding an outer-planar graph in a point set. Comput. Geom.: Theory Appl. 23(3),
303-312 (2002)

P. Bose, On Embedding an OuterPlanar Graph in a Point Set. Computational
Geometry: Theory and Applications, 23(3):303–312, 2002.

[277] J. Bourgain. On Lipschitz embedding of finite metric spaces in Hilbert
spaces. Israel Journal of Mathematics, 52(1-2):46–52, 1985.
https://www.math.ias.edu/people/faculty/bourgain
bourgain@math.ias.edu

M. Bowling, A. Ghodsi, and D. Wilkinson. Action respecting embedding. ACM Interna-
tional Conference Proceeding Series, 119:65{72, 2005.

okokok
Brand A unifying theorem for spectral embedding and clustering p8

Matthew Brand

low-dimensional nonlinear embedding
lowest-dimensional embedding
mass-preserving embedding
nonlinear low-dimensional embeddings
spherical embeddings

[Brand2004[ Spectral Soluction of Large-Scale Extrinsic Camera Clibration as a Graph Embedding Problem p14

[Brand2002] [Brand2002]
Brand Spectral Soluction of Large-Scale Extrinsic Camera Clibration as a Graph Embedding Problem p14

barycentric embedding proofs of Tutte
Directionally constrained embeddings
least-squares embedding
locally linear embedding algorithm of Roweis and Saul
mass-preserving embedding
nonlinear embedding
spectral embedding methods
spherical embeddings

7

okokok

Brandes Colored Simultaneous Geometric Embeddings and Universal Pointsets p24
Ulrik Brandes
http://algo.uni-konstanz.de/members/brandes/
Ulrik.Brandes@uni-konstanz.de
7

Bipartite embeddings

extended embedding

Fary embeddings

Simultaneous geometric embeddings
Colored Simultaneous Geometric Embeddings

near-simultaneous embeddings

upward planar embedding

Simultaneous embedding
simultaneous embedding with mapping
simultaneous embedding without mapping
Colored simultaneous embedding

straight-line embedding
planar straight-line embedding

upward embedding

Brass, P., Cenek, E., Duncan, CA., Efrat, A., Erten, C, Ismailescu, D., Kobourov, S.G., Lubiw, A.,
Mitchell, J.S.B.: On simultaneous graph embedding. Comput. Geom.: Theory Appl. 36(2), 117-130
(2007)

P. Brass, E. Cenek, C. A. Duncan, A. Efrat, C. Erten, D. Ismailescu, S. G.
Kobourov, A. Lubiw, and J. S. B. Mitchell. On simultaneous graph embedding.
In 8th Workshop on Algorithms and Data Structures, pages 243–255, 2003.

Peter Brass, Eowyn Cenek, Christian A. Duncan, Alon Efrat, Cesim Erten, Dan
Ismailescu, Stephen G. Kobourov, Anna Lubiw, and Joseph S. B. Mitchell. On
simultaneous planar graph embeddings. In Workshop on Algorithms and Data
Structures, volume 2748 of Lecture Notes in Computer Science, pages 243–255.
Springer-Verlag, 2003.
http://www-cs.engr.ccny.cuny.edu/~peter/
peter@cs.ccny.cuny.edu

okokok
Breniuc FLEXIBLE PLATFORMS FOR TEACHING EMBEDDED SYSTEMS p23

Brink Spherical parameterization methods for 3d surfaces p152

[Brink2005] Spherical parameterization methods for 3d surfaces p152

Willie Brink
http://dip.sun.ac.za/~wbrink/
wbrink@sun.ac.za
21
31

GC (Great Circle) embedding
Tutte embedding
Spherical Tutte embedding
Sping embedding
Transformed embedding
TP embedding

Dean Brock
https://csci.unca.edu/faces/faculty/brock
brock@unca.edu

Dr. Thierry Brouard
http://www.univ-tours.fr/m-brouard-thierry-856.kjsp
thierry.brouard@univ-tours.fr

[Bruckdorfer2012] On the Characterization of Plane Bus Graphs p11
http://www-pr.informatik.uni-tuebingen.de/?site=mitarbeiter/tillbruckdorfer/index
bruckdor@informatik.uni-tuebingen.de

planar embedding

fixed planar embedding

plane embedding

Bus graphs are being used for the visualization of hyperedges

Prof. Dr. Luc Brun
evaluators Ecole Nationale Superieur d'Ingenieurs de Caen
Universite de Caen, Basse-Normandie
https://brunl01.users.greyc.fr/
luc.brun@ensicaen.fr

Tom Brylawski

2016-5-3
Horst Bunke
http://www.fki.inf.unibe.ch/staff/prof.-dr.-horst-bunke
bunke@iam.unibe.ch

H. Bunke, P.J. Dickinson, M. Kraetzl, and W.D. Wallis. A Graph-Theoretic Approach to Enterprise Network Dynamics, volume 24 of Progress in Computer Science and Applied Logic (PCS). Birkh¨auser, 2007.

[Bunke2008] Applied Pattern Recognition p246

Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81
Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81

Bunke Bridging the Gap between Structural and Statistical Pattern Recognition p41
Bunke Bridging the Gap between Structural and Statistical Pattern Recognition p41

H. Bunke and K. Riesen. Graph classification based on dissimilarity space embedding.
In IAPR International Workshop, SSPR & SPR 2008, LNCS 5342, pages
996–1007, 2008.

Bunke GRAPH CLASSIFICATION BASED ON DISSIMILARITY SPACE EMBEDDING p66

Bunke

http://www.igi-global.com/chapter/graph-embedding-using-dissimilarities-applications/77554

Graph Embedding Using Dissimilarities with Applications in Classification

Horst Bunke

(University of Bern, Switzerland) and Kaspar Riesen (University of Bern, Switzerland) Copyright ? 2013. 18 pages.

(1) H. Bunke and K. Riesen. On dissimilarity embedding of graphs in
vector spaces. To appear in book Handbook of Pattern Recognition and
Computer Vision.
(12) H. Bunke and K. Riesen. Recent developments in graph classification
and clustering using graph embedding kernels. In A. Juan-Ciscar
and G. Sanchez-Albaladejo, editors, Pattern Recognition in Information
Systems, pages 3—13, 2008.

(14) H. Bunke and K. Riesen. Graph classification based on dissimilarity
space embedding. In N. da Vitoria Lobo et al., editor, Structural,
Syntactic, and Statistical Pattern Recognition, LNCS 5342, pages 996–
1008, 2008.

?

R. Busa-Fekete and A. Kocsor. Locally linear embedding and its variant for feature extraction.
http://homepages.uni-paderborn.de/busarobi/
busarobi@upb.de

Busa-Fekete Locally Linear Embedding and its Variants for Feature Extraction p6

Modified Supervised Locally Linear Embedding(MSLLE)
Kernel Locally Linear Embedding (KLLE)
Kernelized Locally Linear Embeddings


Untitled Document

Cabello Algorithms for embedded graphs p93

[Cabello2012] Algorithms for embedded graphs p93

Cabello Algorithms for embedded graphs p93
Sergio Cabello
http://www.fmf.uni-lj.si/~cabello/
sergio.cabello@fmf.uni-lj.si

2-cell embedding

[Cabello2009] Algorithms for graphs embedded on surfaces p7

cellular embeddings

CABELLO FINDING CYCLES WITH TOPOLOGICAL PROPERTIES IN EMBEDDED GRAPHS p15

4. J. Cappos, A. Estrella-Balderrama, J. J. Fowler, and S. G. Kobourov. Simultaneous
graph embedding with bends and circular arcs. Technical Report TR06-02,
University of Arizona, 2006.

???????????????????/

?[Cappos2006] Simultaneous Graph Embedding with Bends and Circular Arcs p12

okokok
okokok
[Cappos2006] Simultaneous Graph Embedding with Bends and Circular Arcs p12
Cappos Simultaneous Graph Embedding with Bends and Circular Arcs p12
Cappos Simultaneous Graph Embedding with Bends and Circular Arcs p12
Simultaneous Graph Embedding with Bends and Circular Arcs?

3

Justin Cappos
http://engineering.nyu.edu/people/justin-cappos
http://isis.poly.edu/~jcappos/

jcappos@nyu.edu

Dear Prof Cappos,

I am honored to have read your 2006 paper “Simultaneous Graph Embedding with Bends and Circular Arcs” coauthored with Alejandro Estrella-Balderrama, Joseph Fowler and Stephen Kobourov, for I happen to be interested in the graph theoretic issues of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, DNA computing and a bunch of other novice IC techs). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the netlist is generated.

I am not an established who’s who, rather, a newcomer in this field. Nobody except myself know my work, nothing has been published out of my hands. But I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, out of my studies of quantum circuits, graph embedding is defined as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding stuff. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant. They ignore people like me who have no decent position in the Academia. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Perhaps someday when I think I have found something, I may go out and meet someone to talk about my findings. So I would like you to give some help to clarify what is really meant the term of graph embedding.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:? https://sites.google.com/site/markchen0088/

dynamic graph visualization

simultaneous embedding of graphs
simultaneous embedding of planar graphs
Geometric simultaneous embeddings
curvilinear simultaneous embeddings
geometric simultaneous embedding of two vertex-labeled planar graphs on n vertices in the xy-plane
Level and radial embeddings
Level embeddings
radial embeddings
planarity embedding algorithm for level planar graphs

level graphs
level planar graphs
n-level planar graph
outerplanar graph

star-shaped levels
level planarity
graph and geometric thickness

graph layout algorithms

1. C. Bachmaier, F. J. Brandenburg, and M. Forster. Radial level planarity testing
and embedding in linear time. J. Graph Algorithms Appl., 9(1):53–97, 2005.
2. P. Bose. On embedding an outer-planar graph in a point set. CGTA: Computational
Geometry: Theory and Applications, 23(3):303–312, 2002.
3. P. Brass, E. Cenek, C. A. Duncan, A. Efrat, C. Erten, D. Ismailescu, S. G.
Kobourov, A. Lubiw, and J. S. B. Mitchell. On simultaneous graph embedding.
In 8th Workshop on Algorithms and Data Structures, pages 243–255, 2003.
4. J. Cappos, A. Estrella-Balderrama, J. J. Fowler, and S. G. Kobourov. Simultaneous
graph embedding with bends and circular arcs. Technical Report TR06-02,
University of Arizona, 2006.
5. G. Di Battista and E. Nardelli. Hierarchies and planarity theory. IEEE Trans.
Systems Man Cybernet., 18(6):1035–1046 (1989), 1988.
6. P. Eades, Q. Feng, X. Lin, and H. Nagamochi. Straight-line drawing algorithms
for hierarchical graphs and clustered graphs. Algorithmica, 44(1):1–32, 2006.
7. C. Erten and S. G. Kobourov. Simultaneous embedding of planar graphs with few
bends. In 12th Symposium on Graph Drawing (GD), pages 195–205, 2004.
8. A. Estrella-Balderrama, J. J. Fowler, and S. G. Kobourov. Characterization of
unlabeled level planar trees. Manuscript accepted by 14th Symposium on Graph
Drawing, 2006.
9. S. Felsner, G. Liotta, and S. Wismath. Straight-line drawings on restricted integer
grids in two and three dimensions. Journal of Graph Algorithms and Applications,
7(4):363–398, 2003.
10. M. Geyer, M. Kaufmann, and I. Vrto. Two trees which are self-intersecting when
drawn simultaneously. In 13th Symposium on Graph Drawing, pages 201–210, 2005.
11. M. J¨unger and S. Leipert. Level planar embedding in linear time. J. Graph
Algorithms Appl., 6(1):67–113, 2002.

okokok

Cardinal The Complexity of Simultaneous Geometric Graph Embedding p14? 2016-1-3? ???

Cardinal The Complexity of Simultaneous Geometric Graph Embedding p71

Jean Cardinal
http://www.ulb.ac.be/di/algo/jcardin/
Algorithms Research Group
Computer Science Dept., CP 212
Université Libre de Bruxelles
B-1050 Brussels, Belgium
p: +32-2-650 56 08
f: +32-2-650 56 09
jcardin@ulb.ac.be

May 28, 2015

Plane straight-line embedding
simultaneous geometric embedding

2015-11-21

Today I continue to read? this paper:

Cardinal The Complexity of Simultaneous Geometric Graph Embedding p14

?after finished this one:

Cardinal The Complexity of Simultaneous Geometric Graph Embedding p71

?by

Jean Cardinal

and

Vincent Kusters

written on

May 28, 2015

=========================

2016-1-3

Dear Prof Cardinal,

I am honored to have read your presentation slide “The Complexity of Simultaneous Geometric Graph Embedding” and several of similar papers of yours, for I happen to be interested in the graph theoretic aspects of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, spin-based computing etc). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the generation of the netlist.

I am not an established graphtheorist, rather, an independent and self taught researcher in this field. Nobody knows my work, nothing has been published out of my hands, although I have prepared hundreds of papers and dozens of books or study notes in this and many other fields.

I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, graph embedding is understood as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant and corrupt. They ignore people like me who have no decent position in their system. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Therefore I need to have contacts with the external academic circles to communicate my ideas and to know what others are doing and thinking about. I want to know if you are interested in joining this circle or not.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:
new:
https://sites.google.com/site/markchenstudio/
old:
https://sites.google.com/site/markchen0088/

Paz Carmi
https://www.cs.bgu.ac.il/~carmip/
carmip@cs.bgu.ac.il

Okokok
[CHANG2001] Graph Embedding Aspect of IEH Graphs

CHANG Graph Embedding Aspect of IEH Graphs
HUNG-YI CHANG AND RONG-JAYE CHEN
Hypercube
generalized hypercubes
Hypercube graphs
generalized hypercube graph
incrementally extensible hypercube (IEH) graph
incomplete hypercube (IH)
spanning subgraph
complete binary tree
torus
meshes
interconnection networks
Supercubes
Graph embedding has been used to model the problem of simulating a parallel algorithm in a parallel machine.
Mapping
guest graph G
host graph H.
The cost of an embedding is measured in terms of dilation, congestion, and expansion
dilation
expansion
congestion

hypercube

Hypercube graphs

incrementally extensible hypercube (IEH) graph

incomplete hypercube (IH)

spanning subgraph of IEH

graph embedding

complete binary tree

meshes

generalized hypercubes

complete graphs

Supercubes

Chapter 1 Drawing Planar Graphs p8

Chang Robust Locally Linear Embedding p10
Robust locally linear embedding(RLLE)

Chang Robust Locally Linear Embedding p25

H. Chang and Y. Dit-Yan, \Robust locally linear embedding," Pattern Recognition,
vol. 39, pp. 1053{1065, June 2006.

[Charikar2005]
Charikar Directed Metrics and Directed Graph Partitioning Problems p11
Moses Charikar
http://www.cs.princeton.edu/~moses/
Moses@cs.princeton.edu

Charikar Spectral Embedding of k-Cliques Graph Partitioning and k-Means p27

Resistive embedding
resistive distance embedding

okokok
[CHARTRAND2009] Chromatic Graph Theory p498??

CHARTRAND Chromatic Graph Theory p498
CHARTRAND Chromatic Graph Theory p498
GARY CHARTRAND
http://homepages.wmich.edu/~zhang/gary.html
chartrand@wmich.edu

Chekuri Embedding -Outerplanar Graphs into l1 p10
http://chekuri.cs.illinois.edu/
Chekuri@illinois.edu

[Chekuri2002] Embedding k-Outerplanar Graphs into l1 p10

shortest-path metric

k-outerplanar graph

probability distribution over tree metrics with constant distortion

weighted kn planar grids.

sparsest cut

multicommodity network

treewidth- 2 graph

probabilistic tree embeddings

random tree embeddings for k-outerplanar graphs

embedding finite metric spaces into l1

Low distortion embeddings

l1-embeddings

maxflow-mincut ratio in a multicommodity flow network

divide-and-conquer algorithms

embeddings into random (dominating) trees

embeddability

unit-weighted expander graphs

metric embeddings

series-parallel graphs

buy-atbulk problem

group Steiner problem

Halin graphs

Chen, T., Yang, Q., and Tang, X. (2007). Directed graph embedding.
In International Joint Conference on Artificial Intelligence, pages 2707–2712.

T.Chen,Q.Yang,X.Tang,Directedgraphembedding,in:InternationalJoint
Conference onArtificialIntelligence,2007,pp.2707–2712.

CHEN A Long-Ring Embedding Scheme in the Faulty Star Graph p10

[CHEN2000] A Long-Ring Embedding Scheme in the Faulty Star Graph p10

star graph interconnection network

hypercube network

ring embedding problem

long-ring embedding scheme

Cayley graphs

concatenation tree

[Chen2005] Directed Graph Embedding p6

Embedding the data of directed graphs to vector spaces

F.R.K. Chunr;, F.T. Leir;hton, A.L. Rosenberr; (1984):
Embeddinr; r;raphs in books: A layout problem with applications to VLSI design.
Submitted for publication. See also 5th lnternotionol Conference on Theorv ond Applicotion? of Groph?.

[Chepoi2007] Constant approximation algorithms for embedding graph metrics into trees and outerplanar graphs p14

chepoi@lif.univ-mrs.fr

Chepoi Constant approximation algorithms for embedding graph metrics into trees and outerplanar graphs p24

Chepoi Constant approximation algorithms for embedding graph metrics into trees and outerplanar graphs p27
α-embeddings
Low-distortion embeddings
Ordinal embedding
internet embedding

Constant approximation algorithms for embedding graph metrics into trees and outerplanar graphs1
V. Chepoi1

[CHIBA1985] A Linear Algorithm for Embedding Planar Graphs Using PO-Trees p23

CHIBA A Linear Algorithm for Embedding Planar Graphs Using PO-Trees p23
embedding (or drawing) a planar graph in the plane [3].

N. Chiba, T. Nishizeki, S. Abe, T. Ozawa, A linear algorithm for embedding planar
graphs using PQ-trees, J. Comput. System Sci. 30 (1985) 54–76.

N. Chiba, T. Nishizeki, S. Abe, and T. Ozawa, A linear algorithm for embedding planar
graphs using PQ-trees, J. Comput. System Sci. 1985., 54]76.

okokok
[Chimani2007]

okokok
Chimani Algorithms for the Hypergraph and the Minor Crossing Number Problems
crossing minimization
Hypergraph Crossing Number
Minor Crossing Number
tree-based hypergraph crossing number

okokok

Chowdhury Point-Set Embeddings of Planar Graphs with Fewer Bends p67
[Chowdhury2010] Point-Set Embeddings of Planar Graphs with Fewer Bends p67

Md. Emran Chowdhury

http://www.csc.lsu.edu/~emran/
emran@csc.lsu.edu

Point-Set Embedding

  1. Orthogonal point-set embeddings
  2. Straight-line Point-Set Embedding
  3. upward point-set embedding

Topological Book Embedding

  1. upward topological book embedding

A drawing of a graph is a sort of visualization of information represented by that graph. The field in which the different aesthetic techniques of drawing graphs are vividly described is “Graph Drawing”.

In the field of graph drawing, the geometric representations of graphs generated by graph drawing algorithms are constrained by some predefined geometric or aesthetic properties.

FAN R. K. CHUNG

F.R.K. Chunr;, F.T. Leir;hton, A.L. Rosenberr; (1984): Embeddinr; r;raphs in books: A
layout problem with applications to VLSI design. Submitted for publication. See also
5th lnternotionol Conference on Theorv ond Applicotion? of Groph?.

?
Cieszko Graph Based Messaging APIs – concept and implementation p8

[Civril2003] SDE Graph Drawing Using Spectral Distance Embedding p12

Prof. Daniela Cocchi

[Connie2014] A Grassmann graph embedding framework for gait analysis

http://asp.eurasipjournals.com/content/2014/1/15

Tee Connie1, Michael Kah Ong Goh1 and Andrew Beng Jin Teoh2*

D. Conte, P. Foggia, C. Sansone, and M. Vento. Thirty years of graph
matching in pattern recognition. Int. Journal of Pattern Recognition and
Artificial Intelligence, 18(3):265–298, 2004.

????????????????

okokok
[Conte2013]

okokok
[Conte2013] A Comparison of Explicit and Implicit Graph Embedding Methods for Pattern Recognition p11
Graph embedding methods map either explicitly or implicitly graphs into high dimensional spaces hence allowing to perform the basic mathematical computations required by various statistical pattern recognition techniques.

The graph embedding methods are formally categorized as

implicit graph embedding

The implicit graph embedding methods are based on graph kernels. A graph kernel is a function that can be thought of
as a dot product in some implicitly existing vector space. Instead of mapping graphs from graph space to vector space and then computing their dot product, the value of the kernel function is evaluated in graph space. Such an implicit
embedding satisfies all properties of a dot product. Since it does not explicitly map a graph to a point in vector space, a strict limitation of implicit graph embedding is that it does not permit all operations that could be defined on
vector spaces. Further reading on state of the art methods of graph kernels and implicit graph embedding could be found in [2].

Bunke, H., Riesen, K.: Recent advances in graph-based pattern recognition with applications in document analysis. Pattern Recognition 44(5), 1057–1067 (2011)

explicit graph embedding.

On the other hand, explicit graph embedding methods explicitly embed an input graph into a feature vector and thus enable the use of all the methodologies and techniques devised for vector spaces. The vectors obtained by an
explicit graph embedding method can also be employed in a standard dot product for defining an implicit graph embedding function between two graphs. An important property of explicit graph embedding is that graphs of different size and order need to be embedded into a feature vector of determined size. The selection of the axis of this feature vector requires thus a fine analysis of the analysed dataset in order to selected features representive of the set while remaining sufficiently generic to describe any input graph. We refer the interested reader to [16] for further reading on classical explicit graph embedding techniques.

Fuzzy Multilevel Graph Embedding (FMGE)

Attribute Statistics based Embedding

Graph Kernels Methods
Laplacian Graph Kernel
graph edit distance between two graphs
gram matrix
regularization operator
Graph Laplacian kernel
implicit embedding
explicit embedding
Treelet kernel
Topological Embedding
vectorial signature of the graphs
non-isomorphic graphs network
The vectorial representation of a graph topology
Fuzzy Multilevel Graph Embedding method (FMGE)
Attribute Statistics based Embedding

References
1. Brun, L., Conte, D., Foggia, P., Vento, M.: A graph-kernel method for reidentification.
In: Kamel, M., Campilho, A.C. (eds.) ICIAR (1). LNCS, vol. 6753,
pp. 173–182. Springer (2011)
GbR2013, 011, v3 (final): ’A Comparison of...’ 9
10
2. Bunke, H., Riesen, K.: Recent advances in graph-based pattern recognition with
applications in document analysis. Pattern Recognition 44(5), 1057–1067 (2011)
3. Chung, F.R.K.: Spectral Graph Theory (CBMS Regional Conference Series in
Mathematics, No. 92). American Mathematical Society (February 1997)
4. Ga¨uz′ere, B., Brun, L., Villemin, D.: Graph kernels based on relevant patterns
and cycle information for chemoinformatics. In: Proceedings of ICPR 2012. pp.
1775–1778. IAPR, IEEE (November 2012)
5. Ga¨uz′ere, B., Brun, L., Villemin, D.: Two new graphs kernels in chemoinformatics.
Pattern Recognition Letters 33(15), 2038 – 2047 (2012)
6. Gazre, B., Hasegawa, M., Brun, L., Tabbone, S.: Implicit and explicit graph embedding:
Comparison of both approaches on chemoinformatics applications. In: Gimelfarb,
G., Hancock, E., Imiya, A., Kuijper, A., Kudo, M., Omachi, S., Windeatt,
T., Yamada, K. (eds.) Structural, Syntactic, and Statistical Pattern Recognition,
LNCS, vol. 7626, pp. 510–518. Springer Berlin Heidelberg (2012)
7. Gibert, J., Valveny, E., Bunke, H.: Graph embedding in vector spaces by node
attribute statistics. Pattern Recognition 45(9), 3072–3083 (2012)
8. Gibert, J., Valveny, E., Bunke, H., Forn′es, A.: On the correlation of graph edit
distance and l 1 distance in the attribute statistics embedding space. In: Gimel’farb,
G.L., Hancock, E.R., Imiya, A., Kuijper, A., Kudo, M., Omachi, S., Windeatt, T.,
Yamada, K. (eds.) SSPR/SPR. LNCS, vol. 7626, pp. 135–143. Springer (2012)
9. Jaromczyk, J., Toussaint, G.: Relative neighborhood graphs and their relatives. In
Proceedings of the IEEE (1992)
10. Jouili, S., Tabbone, S.: Graph embedding using constant shift embedding. In: Proceedings
of the 20th International conference on Recognizing patterns in signals,
speech, images, and videos. pp. 83–92. ICPR’10, Springer-Verlag, Berlin, Heidelberg
(2010), http://dl.acm.org/citation.cfm?id=1939170.1939183
11. Luqman,M.M., Ramel, J.Y., Llados, J.: Improving FuzzyMultilevel Graph Embedding
through Feature Selection Technique. In: Structural, Syntactic, and Statistical
Pattern Recognition. vol. 7626, pp. 243–253 (2012)
12. Luqman, M.M., Ramel, J.Y., Llad′os, J., Brouard, T.: Fuzzy multilevel graph embedding.
Pattern Recognition 46(2), 551–565 (2013)
13. Neuhaus, M., Bunke, H.: Bridging the Gap Between Graph Edit Distance and Kernel
Machines. World Scientific Publishing Co., Inc., River Edge, NJ, USA (2007)
14. Riesen, K., Bunke, H.: Iam graph database repository for graph based pattern
recognition and machine learning. In: da Vitoria Lobo, N., Kasparis, T., Roli,
F., Kwok, J.T.Y., Georgiopoulos, M., Anagnostopoulos, G.C., Loog, M. (eds.)
SSPR/SPR. LNCS, vol. 5342, pp. 287–297. Springer (2008)
15. Riesen, K., Bunke, H.: Approximate graph edit distance computation by means of
bipartite graph matching. Image Vision Computing 27(7), 950–959 (2009)
16. Riesen, K., Bunke, H.: Graph classification based on vector space embedding.
IJPRAI 23(6), 1053–1081 (2009)
17. Sidere, N., H′eroux, P., Ramel, J.Y.: Vector representation of graphs: Application to
the classification of symbols and letters. In: ICDAR. pp. 681–685. IEEE Computer
Society (2009)
18. Smola, A.J., Kondor, R.I.: Kernels and regularization on graphs. In: XV Annual
Conference on Learning Theory. pp. 144–158 (2003)
19. Steinke, F., Schlkopf, B.: Kernels, regularization and differential equations. Pattern
Recognition 41(11), 3271 – 3286 (2008)
20. Toivonen, H., Srinivasan, A., King, R., Kramer, S., Helma, C.: Statistical evaluation
of the predictive toxicology challenge 2000–2001. Bioinformatics 19(10), 1183–1193
(2003)

D. Cook and L. Holder, editors. Mining Graph Data. Wiley-Interscience,
2007.

[Cooley2009] EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf sent ????????????????????
Cooley EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf ..........

77

OLIVER JOSEF NIKOLAUS COOLEY

A thesis submitted to
The University of Birmingham
for the degree of
DOCTOR OF PHILOSOPHY
School of Mathematics
The University of Birmingham
October 2009

https://online.tugraz.at/tug_online/visitenkarte.show_vcard?pPersonenId=B2E1240C2AB5C679&pPersonenGruppe=3
https://online.tugraz.at/tug_online/webnav.navigate_to?corg=7307&cperson_nr=92359

Herr?????? Cooley, Oliver Josef Nikolaus, PhD

Cooley, Oliver Josef Nikolaus; PhD
E-Mail??? cooley@tugraz.at

Telefon? TU Graz????? +43 (316) 873 - 5362

Postadresse 5020 Institut für Optimierung und Diskrete Mathematik (Math B)
8010 Graz, Steyrergasse 30/II

Dear Prof Cooley,

I am honored to have read your 2009 PhD thesis “EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS”, several times and now I am rereading it again, for I happen to be interested in the graph theoretic aspects of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, spin-based computing etc). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the netlist is generated.

I am not an established graphtheorist, rather, a newcomer in this field. Nobody knows my work, nothing has been published out of my hands, although I have prepared hundreds of papers and dozens of books or study notes. But I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, graph embedding is understood as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant and corrupt. They ignore people like me who have no decent position in the their system. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Therefore I need to have contacts with the external academic circles to communicate my ideas and to know what others are doing and thinking about. I want to know if you are interested in joining this circle or not.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:
new:
https://sites.google.com/site/markchenstudio/
old:
https://sites.google.com/site/markchen0088/

Deryk Osthus
http://web.mat.bham.ac.uk/D.Osthus/index.html

graph embedding

Graph Packings
H-packing in G
perfect graph packing
perfect H-packing in G
almost perfect packing
almost perfect H-packing in G

extremal graph
spanning subgraphs.
graph and hypergraph Ramsey numbers

Hypergraph Embeddings
Broadly speaking, we consider the problem of embedding a hypergraph H into a larger hypergraph G, i.e. of finding a subhypergraph of G which is isomorphic to H.

Turan’s Theorem
Erdos-Stone-Simonovits Theorem

p 40

[18] O. Cooley, N. Fountoulakis, D. K¨uhn, D. Osthus, Embeddings and Ramsey numbers of sparse k-uniform hypergraphs, Combinatorica 29 (2009), 263–297.

[7] B. Bollobas, S. Eldridge, Packing of graphs and applications to computational complexity, J. Combin. Theory B 25 (1978), 105-124.

Mark Crovella

okokok
Culler Planar Graphs

Andrej Cvetkovski

Cvetkovski Hyperbolic Embedding and Routing for Dynamic Graphs p7

okokok
Cvetkovski Hyperbolic Embedding and Routing for Dynamic Graphs
Hyperbolic Embedding
online graph embedding.
online greedy graph embedding in the hyperbolic plane
global embedding
incremental embedding of network nodes
network embeddings based on an embedded spanning tree subgraph.
frequent reembedding of temporally dynamic network graphs
network embedding
greedy embedding in two-dimensional hyperbolic space
greedy embedding of an infinite d-regular tree

Dynamic Graphs
network connectivity graphs
dynamic multihop packet-switching communication networks
hyperbolic plane
hyperbolic distance
hyperbolic bisector
hyperbolic hyperplane

Cygan Tight Lower Bounds on Graph Embedding Problems p23
Marek
Low-distortion embeddings
Minimum Distortion Embedding
non-contracting embedding
optimal-distortion embedding


Untitled Document

Da Lozzo The Importance of Being Proper p39

Dahl Covariance selection for non-chordal graphs via chordal embedding p22

[Dean2007] Unit Rectangle Visibility Graphs p24

plane embedding

bar visibility graphs (BVGs)

unit bar visibility graphs (UBVGs)

rectangle visibility graphs (RVGs)

unit rectangle visibility graph (URVG)

okokok
Debowsky Hypergraphs and their planar embeddings p35

Dell Graph Embedding and Extensions: A General Framework for Dimensionality Reduction p21

DeMillo Combinatorial graph embedding p87

11

DeMillo

http://oai.dtic.mil/oai/oai?verb=getRecord&metadataPrefix=html&identifier=ADA081247

Accession Number :

ADA081247

Title :

Combinatorial Graph Embedding.

Descriptive Note :

Final rept.,

Corporate Author :

GEORGIA INST OF TECH ATLANTA SCHOOL OF INFORMATION AND COMPUTER SCIENCE

Personal Author(s) :

DeMillo,R A ; Eisenstat,S C ; Lipton,R J

PDF Url : ADA081247

Report Date : Jan 1980

Pagination or Media Count : 85

Abstract :

Let G, G' be directed graphs. A combinatorial embedding of G into G' is an identification of each x ∈G an element of V(G) with a set of vertices S a subset of V(G') such that each S is bounded in size by a constant independent of V(G) and each arc in G is carried into a directed path of length bounded by a constant independent of V(G). This concept has formed the basis for a number of theoretical studies and the papers collected here are representative of - with one major exception - the state-of-the-art with regard to graph embedding.

S. T Bounded Embeddings
Data structure embedding

M. Fatih Demirci

DiBattista Algorithms for Drawing Graphs an Annotated Bibliography p44

Sven Dickinson

Danny Dolev

Dolev PLANAR EMBEDDING OF PLANAR GRAPHS p15

W. Didimo and G. Liotta. Computing orthogonal drawings in a variable embedding
setting. In Algorithms and Computation (Proc. ISAAC ’98), volume 1533 of Lecture
Notes Comput. Sci., pages 79–88. Springer-Verlag, 1998. 358

Dongarra Graph Algorithms in the Language of Linear Algebra p372

D. Donoho and C. Grimes. Hessian eigenmaps: Locally linear embedding
techniques for high-dimensional data. Proc. of National Academy of Science,
100 (10):5591{5596, 2003.

okokok
Dornheim Graph Embedding with Topological Cycle-Constraints

Dornheim Planar Graphs with Topological Constraints p40

Robert P.W. Duin

Dujmovic Three-Dimensional Drawings p34

Duncan Drawing with Fat Edges p16

Duncan Planar Drawings of Higher-Genus Graphs p16

Duncan Planar Drawings of Higher-Genus Graphs p26


Untitled Document

Peter Eades

Ebbers-Baumann Embedding Point Sets into Plane Graphs of Small Dilation p12

Ebbers-Baumann Embedding Point Sets into Plane Graphs of Small Dilation p12

okokok
Ebeling Placement and Routing Tools for the Triptych FPGA p22
Ebeling Placement and Routing Tools for the Triptych FPGA p22
December, 1995

[Ebner2005] Optimal Crossing Minimization using Integer Linear Programming p87

okokok
Embedded Subgraph Isomorphism and Related Problems
Graph isomorphism
subgraph isomorphism
maximum common subgraph
circular ordering
combinatorial embedding.
embedded graph
embedded subgraph isomorphism
triconnected planar graphs

D. Emms, R. C. Wilson, and E. R. Hancock. Graph embedding using quantum
commute times. In IAPR International Workshop GbRPR, LNCS 4538.

prof. dr. D. Eppstein
(University of California, Irvine)

Erten, C, Kobourov, S.G.: Simultaneous embedding of planar graphs with few bends. J. Graph Algorithms
Appl. 9(3), 347-364 (200S)
C. Erten and S. G. Kobourov. Simultaneous embedding of planar graphs with few
bends. In 12th Symposium on Graph Drawing (GD), pages 195–205, 2004.

Cesim Erten and Stephen G. Kobourov. Simultaneous embedding of planar graphs
with few bends. In J. Pach, editor, 12th Int. Symp. on Graph Drawing, volume
3383 of Lecture Notes in Computer Science, pages 195–205. Springer-Verlag, 2005.

Erten Simultaneous Embedding of a Planar Graph and its Dual on the Grid o17

Erten Simultaneous Embedding of a Planar Graph and its Dual on the Grid p17

primal-dual embedding

A. Estrella-Balderrama, E. Gassner, M. Junger, M. Percan, M. Schaefer,
and M. Schulz. Simultaneous geometric graph embeddings. In Proc. 16th
International Symposium on Graph Drawing (GD2008), pages 280{290.
Springer, 2008. doi:10.1007/978-3-540-77537-9_28.

Alejandro Estrella-Balderrama

okokok
Estrella-Balderrama Simultaneous Geometric Graph Embeddings
Alejandro Estrella-Balderrama


Untitled Document

Fahnenschreiber On the Suitability of Connectivity-Extended Local Embedding for Drawing Multivariate Graphs p8

Fan Optimal Path Embedding in Crossed Cubes p11

Fang Graph Embedding Framework for Link Prediction and Vertex Behavior Modeling in Temporal Social Networks p7

Fang sLLE: Spherical Locally Linear Embedding with Applications to Tomography p8

Dr. Miquel Ferrer
Hydrometeorological Innovative Solutions, S.L.
Barcelona

2016-5-13

Miquel Ferrer
miquel.ferrer@upc.edu

Adre?a Resistència Materials i Est.A l'Eng.
EDIFICI H (ETSEIB)
PLANTA -1 PORTA 13.31
AVDA. DIAGONAL, 647
08028 BARCELONA
SPAIN
Telèfon 93 4010861
Producció científica: futur.upc.edu/MiquelFerrerBallester?????
Càrrecs ????? Secretari/a de Departament
Adam Schenker

Ferrer, M., Valveny, E., Serratosa, F., Riesen, K., Bunke, H.: An approximate
algorithm for median graph computation using graph embedding. In: Proceedings
of 19th ICPR, pp. 287–297 (2008)

Ferrer, M., Valveny, E., Serratosa, F., Riesen, K., and Bunke, H.
(2008). An approximate algorithm for median graph computation using graph embedding.
In International Conference on Pattern Recognition, pages 1–4. Ieee.

Ferrer, M., Valveny, E., Serratosa, F., Riesen, K., and Bunke, H.
(2010). Generalized median graph computation by means of graph embedding in vector
spaces. Pattern Recognition, 43(4):1642–1655.

okokok
Ferrer A Recursive Embedding Approach to Median Graph Computation
Ferrer A Recursive Embedding Approach to Median Graph Computation p11
Ferrer A Recursive Embedding Approach to Median Graph Computation p11

Recursive Embedding

Ferrer Theory and algorithms on the median graph p174

(8) M. Ferrer, E. Valveny, F. Serratosa, K Riesen, and H. Bunke. An
approximate algorithm for median graph computation using graph embedding.
In Proc. 19th Int. Conf. on Pattern Recognition. IEEE,
2008.

?

Foggia, P. and Vento, M. (2010). Graph Embedding for Pattern
Recognition. In ¨Unay, D., C? ataltepe, Z., and Aksoy, S., editors, Recognizing Patterns in
Signals, Speech, Images and Videos, volume 6388 of Lecture Notes in Computer Science,
pages 75–82. Springer.

P.Foggia,M.Vento,Graphembeddingforpatternrecognition,in:D. U¨ nay, Z.
C- ataltepe, S.Aksoy(Eds.),RecognizingPatternsinSignals,Speech,Images
and Videos,LectureNotesinComputerScience,vol.6388,Springer,2010,
pp. 75–82.

M. Formann, F.Wagner, The VLSI layout problemin various embeddingmodels,
in: Proc. 16th InternationalWorkshop on Graph-Theoretic Concepts in Computer
Science, volume 484 of Lecture Notes in Computer Science, Springer, 1991, pp.
130–139.

okokok
Fomin An Exact Algorithm for Minimum Distortion Embedding

Formam Drawing Graphs in the Plane with High Resolution p10

Nikolaos Fountoulakis

J. Joseph Fowler
J. Joseph Fowler

Fowler, J.1., Jtinger, M., Kobourov, S.G., Schulz, M.: Characterizations of restricted pairs of planar
graphs allowing simultaneous embedding with fixed edges. In: 34th International Workshop on GraphTheoretic
Concepts in Computer Science, WG 2008. LNCS, vol. 5344, pp. 146-158. Springer, Berlin
(2008)

Robert Franzosa

Frati, F.: Embedding graphs simultaneously with fixed edges. In: 14th Symposium on Graph Drawing,
GD 2006. LNCS, vol. 4372, pp. 108-113. Springer, Berlin (2007)

Fabrizio Frati. Embedding graphs simultaneously with fixed edges. In M. Kaufmann
and D. Wagner, editors, 14th Int. Symp. on Graph Drawing, volume 4372 of
Lecture Notes in Computer Science, pages 108–113. Springer-Verlag, 2007.

de Fraysseix, H., Pach, J., Pollack, R.: Small sets supporting Fary embeddings of planar graphs. In:
Proceedings of the 20th Annual ACM Symposium on Theory of Computing, STOC 1988, pp. 426-
433 (1988)

Fu Transductive Multi-view Embedding for Zero-Shot Recognition and Annotation p16

Furedi Embedding of Graphs in Two Irregular Graphs p11


Untitled Document

A. Gagarin, W. Kocay, and D. Neilson, “Embeddings of small graphs
on the torus”, Cubo 5 (2003), no. 2, to appear.

Andrei Gagarin

okokok
Gagarin Embedding Graphs Containing K5-Subdivisions
Gagarin Embedding Graphs Containing K5-Subdivisions p17
non-isomorphic embeddings
cylindrical embedding
Torus Embedding

okokok
Gagarin Embeddings of Small Graphs on the Torus
Gagarin Embeddings of Small Graphs on the Torus p19

isomorphic, non-isotopic embeddings
orientable and non-orientable embeddings
2-cell toroidal embedding
self-dual embeddings
dual embedding
toroidal embeddings
k-regular toroidal embedding
transitive embeddings
self-dual rectangular embedding
triangular embedding
honeycomb embedding

Gagarin

Graph embedding algorithms

https://dl.acm.org/citation.cfm?id=1023441

Advisers: William L. Kocay

Authors: Andrei Gagarin

Publication: · Doctoral Dissertation

Graph embedding algorithms

The University of Manitoba (Canada)

?2003 ISBN:0-612-89560-2

Gamper

http://alps.comp-phys.org/static/doc2.1.0/bgl_extensions/sge.html

Sub Graph Embedding

Lukas Gamper

Gamper Temporal and Spatial Databases Chapter 9: An Introduction to Spatial Databases p33

okokok
Gao Graph Embedding Based Semi-Supervised Discriminative Tracker

Elisabeth Gassne

Gassner Simultaneous Geometric Graph Embeddings p12

Elisabeth Gassner, Michael J¨unger, Merijam Percan, Marcus Schaefer, and Michael
Schulz. Simultaneous graph embeddings with fixed edges. In F. V. Fomin, editor,
32nd Int. Workshop on Graph-Theoretical Concepts in Computer Science, volume
4271 of Lecture Notes in Computer Science, pages 325–335. Springer-Verlag, 2006.

E. Gassner, M. Junger, M. Percan, M. Schaefer, and M. Schulz. Simultaneous
graph embeddings with fixed edges. In Proc. 32nd International Workshop
on Graph-Theoretic Concepts in Computer Science (WG2006), pages
325{335. Springer, Springer, 2006. doi:10.1007/978-3-540-77537-9_28.

Gazre, B., Hasegawa, M., Brun, L., Tabbone, S.:

Implicit and explicit graph embedding: Comparison of both approaches on chemoinformatics applications.

In: Gimelfarb, G., Hancock, E., Imiya, A., Kuijper, A., Kudo, M., Omachi, S., Windeatt, T., Yamada, K. (eds.) Structural, Syntactic, and Statistical Pattern Recognition, LNCS, vol. 7626, pp. 510–518. Springer Berlin Heidelberg (2012)

Georgiou CSC2414- Metric Embeddings Lecture 1 A brief introduction to metric embeddings examples and motivation p9

okokok
Ghawalby Graph Embedding sing the Edge-based Wave Kernel p40

Georgios B. Giannakis
Professor Georgios Giannakis
http://spincom.umn.edu/georgios

Ali Ghodsi
https://www.cs.berkeley.edu/~alig/
Department of Statistics and Actuarial Science
University of Waterloo
Waterloo, ON, Canada, N2L 3G1
aghodsib@math.uwaterloo.ca
alig@cs.berkeley.edu
sent 2016-1-22

Emilio Di Giacomo and Giuseppe Liotta. A note on simultaneous embedding of
planar graphs. In 21st European Workshop on Comp.Geometry, pages 207–210,
2005.

Okokok

okokok
okokok
[Gibert2011] Graph Embedding in Vector Spaces p66
Gibert Graph Embedding in Vector Spaces p66
Gibert Graph Embedding in Vector Spaces p66
Gibert Graph Embedding in Vector Spaces p66

Jaume Gibert, Ernest Valveny
Computer Vision Center,
Universitat Autonoma de Barcelona,
Barcelona, Spain

Jaume Gibert
http://dag.cvc.uab.es/dag/?page_id=2961

Ernest Valveny
http://dag.cvc.uab.es/dag/?page_id=2979
http://dag.cvc.uab.es/dag/?page_id=371

Horst Bunke – retired
Institute of Computer Science and Applied Mathematics,
University of Bern,
Bern, Switzerland
http://www.iam.unibe.ch/fki/staff/prof.-dr.-horst-bunke
bunke@iam.unibe.ch

GbR'2011 Mini-tutorial
May 18th, 2011 GbR'2011 Mini-tutorial on Graph Embeddings 1/23
ICPR'2010 Graph Embedding Contest for a general framework

Graph kernels
Graph kernels are an implicit way of defining a graph embedding
Graph kernels are an implicit way of defining a graph embedding
Spectral Embedding of Graphs
Spectral Embedding of Graphs
Spectral Embedding of Graphs
Graph Embedding using Constant Shift Embedding
Graph Embedding using Constant Shift Embedding
Graph Embedding using Constant Shift Embedding
Graph Classification based on Vector Space Embedding
Graph Classification based on Vector Space Embedding
Graph Classification based on Vector Space Embedding

Formally, a graph embedding is a mapping from the set of graphs to a vectorial space
Assign a feature vector to every graph
vectorial representation of the graph Gk
We do not want to draw a graph in the 2D plane.

Graph Characterization via Ihara Coefficients
MDS on the dissimilarity matrix of a set of graphs
Pattern Vectors from Algebraic Graph Theory

The eigenvalues
The eigenvectors
eigenmode index

Adjacency matrix
spectral decomposition of the adjacency matrix
Inter-mode adjacency matrix
modal matrix
truncated modal matrix
eigen-modes of the truncated modal matrix
Eigen-mode volume (volume of the eigenmode)
feature vector for Gk

Substructure finding methods
Spectral methods
Dissimilarity Representation

Graph embedding in vector spaces by node attribute statistics.
Gibert, J., Valveny, E., Bunke, H.:
Pattern Recognition 45(9), 3072–3083 (2012)

Gibert, J., Valveny, E., Bunke, H., Forn′es, A.: On the correlation of graph edit distance and l 1 distance in the attribute statistics embedding space. In: Gimel’farb, G.L., Hancock, E.R., Imiya, A., Kuijper, A., Kudo, M., Omachi, S., Windeatt, T., Yamada, K. (eds.) SSPR/SPR. LNCS, vol. 7626, pp. 135–143. Springer (2012)

[Gibert2012] Vector Space Embedding of Graphs via Statistics of Labelling Information p162
Gibert Vector Space Embedding of Graphs via Statistics of Labelling Information p162
Gibert Vector Space Embedding of Graphs via Statistics of Labelling Information1 p162

A dissertation submitted by Jaume Gibert
Domingo at Universitat Autonoma de Barcelona
to full the degree of Doctor en Informatica.
Bellaterra, June 2012

graph clustering

graph visualization

graph embeddings

Graph Matching
Error-tolerant Graph Matching
inexact graph matching

graph isomorphism
subgraph isomorphism

largest common subgraph of two graphs
minimum common subgraph of two graphs
minimum common supergraph of two graphs
maximum common subgraph of two graphs

Graph Edit Distance

graph kernels

  1. diffusion kernels
  2. dissimilarity-based kernels
  3. convolution kernels
  4. substructure finding kernels

independent component analysis

F. Giordano, G. Liotta, T. Mchedlidze, and A. Symvonis, Computing
Upward Topological Book Embeddings of Upward Planar Digraphs. In
International Symposium on Algorithms and Computation (ISAAC 2007),
53
volume 4835 of Lecture Notes in Computer Science, pp. 172–183. Springer,
2007.

F. Giordano, G. Liotta, and S. H. Whitesides, Embeddability Problems
for Upward Planar Digraphs. In the 16th International Symposium
on Graph Drawing (GD 2008), volume 5417 of Lecture Notes in Computer
Science, pp. 242–253. Springer, 2009.

William Goodwin

Goodwin Imbedding Problems in Graph Theory p27
1973
7

[7] D. Gordon, Efficient embeddings of binary trees in VLSI arrays, IEEE Trans.
Comput. C-36 (1987) 1009–1018.

GraDR Graph Drawings and Representations p44

R.L. Graham, Isometric embeddings of graphs, in Selected Topics in Graph Theory, vol. 3,
L.W. Beineke, R.L. Wilson (eds.), Academic Press, London, 1988, pp. 133{150.

R.L. Graham, P.M. Winkler, On isometric embeddings of graphs, Trans. Amer. Math. Soc.
288 (1985), 527{536.

Graham Isometric embeddings of graphs p18

Graham Isometric graph embeddings p18

R.L. Graham, P.M. Winkler, On isometric embeddings of graphs, Trans. Amer. Math. Soc.
288 (1985), 527{536.

graphpad

http://www.graphpad.com/guides/prism/6/user-guide/index.htm?using_showing_results_on_a_graph.htm

okokok
Graphs Embedded on Surfaces

?????????????????????????????????????????????????

okokok

Grilli Automated Local Linear Embedding with an application to microarray data p92
Grilli Automated Local Linear Embedding with an application to microarray data p92

Elisa Grilli
Elisa Grilli

Patrick J.F. Groenen

XIX ciclo
Anno Accademico 2005/2006

20

Sammon's Mapping (SM)
Curvilinear Component Analysis (CCA)
Curvilinear Distance Analysis (CDA)
Generative Topographic Mapping (GTM)
Self-Organizing Map (SOM)

  1. Visualization Induced Self-Organizing Map (ViSOM)

supervised LLE (SLLE)

Robust Locally Linear Embedding R LLE

c-isomap

okokok
okokok
Gu Efficient Algorithm for Embedding Hypergraphs in a Cycle
Gu Efficient Algorithm for Embedding Hypergraphs in a Cycle
Qian-Ping Gu and Yong Wang
Clockwise embedding

Qian-Ping Gu and Yong Wang
Clockwise embedding

okokok
Gu Graph Drawing p25

okokok
Gu Graph Drawing p25
David Gu
Mathematics Science Center
Tsinghua University 2010
Embedding Planar Graph
Embedding a planar graph (genus 0) onto the sphere
Embedding Genus One
Embedding Genus Two
Graph Drawing
Ribbon graph of the graph G
dual graph
3-connected graph

Groenen Multidimensional Scaling p14

Stephen Guattery and Gary L.
Miller. Graph embeddings and laplacian eigenvalues.
SIAM Journal on Matrix Analysis and Applications,
21(3):703–723, 2000.

okokok
Guattery Graph Embedding Techniques for Bounding Condition Numbers of Incomplete Factor Preconditioners

Guattery Graph Embedding Techniques for Bounding Condition Numbers of Incomplete Factor Preconditioners p13

Gupta Optimal Three-Dimensional Layouts of Complete Binary Trees p14

Gupta Sequential and Parallel Algorithms for Embedding Problems on Classes of Partial kTrees p37

Haddock

http://hackage.haskell.org/package/gbu-0.1/docs/Data-Graph-Embedding.html

https://hackage.haskell.org/package/gbu-0.1/docs/Data-Graph-Embedding.html

Data.Graph.Embedding

Haddock

http://hackage.haskell.org/package/gbu-0.1/docs/Data-Graph-Embedding.html

https://hackage.haskell.org/package/gbu-0.1/docs/Data-Graph-Embedding.html

Data.Graph.Embedding


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Prof. Dr. Edwin R. Hancock
committee Computer Science Department
University of York
Edwin R. Hancockb

okokok
Harandi Graph Embedding Discriminant Analysis on Grassmannian Manifolds for Improved Image Set Matching

M. T. Harandi, C. Sanderson, S. Shirazi and B. C. Lovell, "Graph Embedding Discriminant
Analysis on Grassmannian Manifolds for Improved Image Set Matching," in IEEE CVPR,
2011.

D. Harel, Y. Koren, Graph drawing by high-dimensional embedding, Graph Algorithms and Applications 8
(2004) 195{214.

Harel Graph Drawing by High-Dimensional Embedding p20

Harel Graph Drawing by High-Dimensional Embedding p20

David Harel

Harris Embedding Planar Graphs on the Grid p30

okokok
[He2009] Graph Embedding with Constraints p6
He Graph Embedding with Constraints2

He Graph Embedding with Constraints p6

He Neighborhood Preserving Embedding p6

X. He, D. Cai, S. Yan and H.-J. Zhang, "Neighborhood Preserving Embedding," in IEEE ICCV, 2005.

Kye Hedlund

000Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134
Lenwood Scott Heath
A dissertation submitted to the faculty of the University of North
Carolina at Chapel Hill in partial fulfillment of the requirements
for the degree of Doctor of Philosophy in the Department of
Computer Science.
Chapel Hill
1985

V. Heun, E. W. Mayr, Embedding graphs with bounded treewidth into their optimal
hypercubes, J. Algorithms 43 (2002) 17–50.
[13] V. Heun, E. W. Mayr, Efficient embeddings into hypercube-like topologies, The
Computer Journal 46 (2003) 632–644.

Higham Fitting a Geometric Graph to a Protein-Protein Interaction Network p7

?[278] G. Hjaltason and H. Samet. Properties of embedding methods for similarity
searching in metric spaces. IEEE Transactions on Pattern Analysis and
Machine Intelligence, 25(5):530–549, 2003.

Michael HimsoIt

Seok-Hee Hong

Hong

http://sydney.edu.au/research/opportunities/opportunities/1033

MultiPlane Graph Embedding (2.5D Graph Embeddability)

Contact Research Expert

Summary The mathematics of embeddings of graphs in three dimensions with constraints using a set of 2D planes, called MultiPlane or 2.5D representation.

Professor Seok-Hee Hong

Radu Horaud

[Horaud2009] A Short Tutorial on Graph Laplacians, Laplacian Embedding, and Spectral Clustering p43

okokok
Horaud A Short Tutorial on Graph Laplacians Laplacian Embedding and Spectral Clustering p43
vector spaces
manifolds
spectral clustering: graph partitionning
spectral matching : ?graph matching..

Manifold embedding
Laplacian embedding
Euclidean L-embedding

Hori Generic object recognition using graph embedding into a vector space p6
Hori Generic object recognition using graph embedding into a vector space p6

Hornung Hierarchical Volumetric Multi-view Stereo Reconstruction of Manifold Surfaces based on Dual Graph Embedding p8

okokok
Hong MultiPlane Graph Embedding (2.5D Graph Embeddability)

?[280] G. Hristescu and M. Farach-Colton. Cluster-preserving embedding of proteins.
Technical report, Rutgers University, 1999.

okokok
Huang Cross-view Graph Embedding
Huang Cross-view Graph Embedding p12

Cross-view Graph Embedding


Untitled Document

2016-5-5
Xiaoyi Jiang
http://cvpr.uni-muenster.de/organisation/jiang.html
Head of Group
Prof. Dr. Xiaoyi Jiang
Prof. Dr. Xiaoyi Jiang Phone: +49 251 8333759
Fax: +49 251 8333755
xjiang@uni-muenster.de
xjiang@uni-muenster.de
University of Münster
Department of Computer Science
Einsteinstrasse 62
D-48149 Münster

Jiang Algorithms for Testing and Embedding Planar Graphs p24

Salim Jouili

[Jouili2010] Graph Embedding Using Constant Shift Embedding p12

Jouili Graph Embedding Using Constant Shift Embedding p12
Jouili, S., Tabbone, S.:
Graph embedding using constant shift embedding.
In: Proceedings of the 20th International conference on Recognizing patterns in signals, speech, images, and videos. pp. 83–92. ICPR’10, Springer-Verlag, Berlin, Heidelberg (2010), http://dl.acm.org/citation.cfm?id=1939170.1939183
S. Jouili and S. Tabbone. Graph embedding using constant shift embedding. In D. ?Unay, Z. Cataltepe, and S. Aksoy, editors, Proceeding of the 20th International Conference on Pattern Recognition, volume 6388 of Lecture Notes in Computer Science,
pages 83{92. Springer, 2010.

constant shift embedding

M. J¨unger and P. Mutzel. Maximum planar subgraphs and nice embeddings:
Practical layout tools. Algorithmica, 16(1):33–59, 1996. 357

Michael Junger

?

okokok
Juvan An algorithm for embedding graphs in the torus
Martin Juvan? and Bojan Mohar?

M. Juvan, J. Marinˇcek, B. Mohar, Elimination of local bridges, Math. Slovaca 47
(1997) 85–92.
[18] , , , Obstructions for simple embeddings, submitted.
[19] , , , Embedding a graph into the torus in linear time, submitted.
[20] M. Juvan, B. Mohar, Extending 2-restricted partial embeddings of graphs, submitted.

M. Juvan, J. Marinˇcek, and B. Mohar, “Embedding graphs in the torus
in linear time”, Integer programming and combinatorial optimization
(Copenhagen, 1995), Lecture Notes in Comput. Sci., 920, Springer,
Berlin, 360-363.


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Abraham Kandel

A. Kandel, H. Bunke, and M. Last, editors. Applied Graph Theory in Computer
Vision and Pattern Recognition, volume 52 of Studies in Computational
Intelligence. Springer, 2007.

Kaouane From algorithm graph specifications to automatic synthesis of FPGA circuits p11

okokok
Karam Graph-Embedding for Speaker Recognition

George Karypis

Prof. George Karypis

M. Kaufmann and R.Wiese, Embedding Vertices at Points: Few Bends
Suffice for planar graphs. Journal of Graph Algorithms and Applications,
6(1):115–129, 2002.

Anne-Marie Kermarrec

okokok

[Kermarrec2011] Distributed Social Graph Embedding p6
Kermarrec Distributed Social Graph Embedding
Kermarrec Distributed Social Graph Embedding

Kermarrec

http://labs.yahoo.com/publication/distributed-social-graph-embedding/

Distributed Social Graph Embedding

inShare Author:

Anne-Marie Kermarrec ; Vincent Leroy ; Gilles Tr Publication Date: 2011

Distributed Social Graph Embedding
SoCS embedding

Yakov Keselman

Keselman Many-to-Many Graph Matching via Metric Embedding p8

okokok
Keselman Many-to-Many Graph Matching via Metric Embedding

Matou?sek’s embedding

Kessels Embedding planar graphs using PQ trees p55

Kim Three-dimensional orthogonal graph drawing with direction constrained edges p88

Klein Planar embedded graphs p14

Robert D. Kleinberg
Jon M. Kleinberg

Kleinberg Isomorphism and Embedding Problems for Infinite Limits of Scale-Free Graphs p10

okokok
Kleinberg Isomorphism and Embedding Problems for Infinite Limits of Scale-Free Graphs

subgraph embeddings

Andrew Knightly

Stephen G. Kobourov
William Kocay

Kocay Drawing on the Torus p19.pdf

Stephen G. Kobourov

Kocay Drawing on the Torus p19.pdf

[Kocay2003] Graph embedding algorithms
https://dl.acm.org/citation.cfm?id=1023441

Graph embedding algorithms
Advisers: ??? William L. Kocay ?????
Authors: ????? Andrei Gagarin ?
Publication:
· Doctoral Dissertation
Graph embedding algorithms
The University of Manitoba (Canada) ?2003
ISBN:0-612-89560-2

[Kocurova2007] Analysis of algorithms for computing the crossing number p119

Kong An Iterative Locally Linear Embedding Algorithm p8

okokok
Kong An Iterative Locally Linear Embedding Algorithm

Iterative Locally Linear Embedding

Yehuda Koren

Olga Kouropteva

dr. M. van Kreveld
(Utrecht University)

O. Kayo Kouropteva. Locally linear embedding algorithm. Extensions and
applications. PhD thesis, Faculty of technology, Department of electrical
and information engineering, University of Oulu, 2006.

okokok
Kriegel Hierarchical Graph Embedding for Efficient Query Processing in Very Large Traffic Networks

Daniela Kühn 2016-1-1 ???
http://web.mat.bham.ac.uk/D.Kuehn/
Daniela Kühn
Daniela Kuhn

??? Preprints and Publications
Teaching
Grants
Short CV
Combinatorics research seminar
Combinatorics, Probability and Algorithms @ Bham

?????? picture Daniela Kuhn ??????

Postal address:
School of Mathematics
Birmingham University
Edgbaston
Birmingham B15 2TT
UK

Office:
Watson Building, Room 303
Campus map

Contact details:
Telephone: ? ??+44? 121?? 4146601
Fax: ???? ??+44? 121?? 4143389
Email:?? ????? d.kuhn@bham.ac.uk

okokok

Kuhn AN ORE-TYPE THEOREM FOR PERFECT PACKINGS IN GRAPHS p23

Kuhn Embedding and Ramsey numbers of sparse k uniform hypergraphs p24

Kuhn Embedding cycles of given length in oriented graphs p8

Kuhn Embedding large subgraphs into dense graphs p28

Kuhn OPTIMAL PACKINGS OF HAMILTON CYCLES IN GRAPHS OF HIGH MINIMUM DEGREE p23

Kuhn PERFECT PACKINGS WITH COMPLETE GRAPHS MINUS AN EDGE p15

2016-1-1

Dear Prof Kuhn,

I am honored to have read your paper “Embedding large subgraphs into dense graphs” and several of similar papers of yours, for I happen to be interested in the graph theoretic aspects of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, spin-based computing etc). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the generation of the netlist.

I am not an established graphtheorist, rather, an independent and self taught researcher in this field. Nobody knows my work, nothing has been published out of my hands, although I have prepared hundreds of papers and dozens of books or study notes in this and many other fields.

I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, graph embedding is understood as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant and corrupt. They ignore people like me who have no decent position in their system. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Therefore I need to have contacts with the external academic circles to communicate my ideas and to know what others are doing and thinking about. I want to know if you are interested in joining this circle or not.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:
new:
https://sites.google.com/site/markchenstudio/
old:
https://sites.google.com/site/markchen0088/

KURAMOCHI Finding Frequent Patterns in a Large Sparse Graph p29

Vincent Kusters

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Kwak Enumeration of graph embedding


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JOHN LAPINSKAS
Mark Last
John Aldo Lee
FRANK THOMSON LEIGHTON
Tom Leighton
Vincent Leroy

Lee, G. and Madabhushi, A. (2010). Semi-Supervised Graph
Embedding Scheme with Active Learning (SSGEAL): Classifying High Dimensional
Biomedical Data. In Pattern Recognition in Bioinformatics, volume 6282 of Lecture
Notes in Computer Science, pages 207–218. Springer.
G.Lee,A.Madabhushi,Semi-supervisedgraphembeddingschemewith
active learning(SSGEAL):classifyinghighdimensionalbiomedicaldata,in:
Pattern RecognitioninBioinformatics,LectureNotesinComputerScience,
vol. 6282,Springer,2010,pp.207–218.

Dr. Josep Llados

Lane Geometric Embedding for Learning Combinatorial Structures p3

lau

http://www.euro-math-soc.eu/review/java-library-graph-algorithms-and-optimization-cd

A Java Library of Graph Algorithms and Optimization + CD

leda

https://www.tu-chemnitz.de/mathematik/discrete/manuals/leda/plane_graph_alg.html

Algorithms for Planar Graphs ( plane_graph_alg )

LEDA

http://webdocs.cs.ualberta.ca/~graphics/software/LEDA/doc/graph_draw.html

Graph Drawing Algorithms ( graph_draw )

Lee Locally Linear Embedding versus Isotop p8

Lee Locally Linear Embedding versus Isotop p8

Leppanen Emb edding and Emulation Results for Static Mesh of Optical Buses p15

okokok
Li Approximation Algorithms for Embedding a Weighted Directed Hypergraph on a Mixed Cycle

okokok
Li Approximation Algorithms for Embedding a Weighted Directed Hypergraph on a Mixed Cycle

Li Discriminant Locally Linear Embedding With High-Order Tensor Data p11

okok
Li Robust Object Tracking with Boosted Discriminative Model via Graph Embedding p7
okok
Li Robust Object Tracking with Boosted Discriminative Model via Graph Embedding p7

graph embedding problem

unified graph-based constraint embedding framework

Volterra kernels approximation
Volterra embedding

binary classification problem
log-Riemannian transformation
discriminative model
object subspace learning problem

Li Weak Greedy Routing over Graph Embedding for Wireless Sensor Networks p6
i Weak Greedy Routing over Graph Embedding for Wireless Sensor Networks p6

LIAO

http://www.kzyjc.net:8080/EN/abstract/abstract13006.shtml

Adaptive local graph embedding weighted-penalty SVM

LIAO Jian1,2, ZHOU Shao-lei1, SHI Xian-jun1

1. Department of Control Engineering，Naval Aeronautical and Astronautical University，Yantai 264001，China；

2. Unit 91550 of PLA，Dalian 116000，China．

Linial The geometry of graphs and some of its algorithmic applications p26

Lipman Symmetry Factored Embedding And Distance p12

Lipman Symmetry Factored Embedding And Distance p12
Yaron

Symmetry Factored Embedding

[Liu2010] Projective Nonnegative Graph Embedding p11
okok
Liu Projective Nonnegative Graph Embedding

Joseph Liu
Profesor Joseph Liu

Projective Nonnegative Graph Embedding
Multiplicative nonnegative graph embedding
Nonnegative Graph Embedding

Livingston

https://web.eecs.umich.edu/~qstout/abs/hypembed.html

Embeddings in Hypercubes

Marilynn Livingston Dept. of Computer Science, Southern Illinois University at Edwardsville

Quentin F. Stout Computer Science and Engineering, University of Michigan

2016-5-9

Marcus Liwicki
http://www.dfki.de/~liwicki/
apl.-Prof. Dr. habil. Marcus Liwicki
Vertretungsprofessor
Multimedia Analysis and Data Mining group
TU Kaiserslautern - University of Kaiserslautern
liwicki@dfki.uni-kl.de
Phone +49 (0) 631 20575 1200
Fax +49 (0) 631 20575 1020
Room 3.19
Trippstadter Str. 122
D-67663 Kaiserslautern, Germany

Dr. Ernest Valveny Llobet
Dept. Ciencies de la Computacio & Centre de Visio per Computador
Universitat Autonoma de Barcelona

Jeome E. Los
Los Embedding Groups of Graph Automorphisms in Surfaces p20

?[51] B. Luo, R. Wilson, and E. Hancock. Spectral embedding of graphs. Pattern
Recognition, 36(10):2213–2223, 2003.

B. Luo, R. C. Wilson, and E. R. Hancock, \Spectral embedding of graphs," Pattern
Recognition, vol. 36, pp. 2213{2230, January 2003.

okokok
Luo Cauchy Graph Embedding
Luo Cauchy Graph Embedding p8
Luo Non-negative Laplacian Embedding p10

Luo

http://techtalks.tv/talks/cauchy-graph-embedding/54317/

Cauchy Graph Embedding

Dijun Luo; Chris Ding; Feiping Nie; Heng Huang

Cauchy Graph Embedding
Local Spline Embedding
Gaussian embedding
local topology preserving embedding
Exponential and Gaussian Embedding
exponential embedding
Flexible manifold embedding

B. Luo, R. C. Wilson, and E. R. Hancock. Spectral embedding of graphs. Pattern
Recognition, 36(10):2213–2230, 2003.

Luo, B., Wilson, R., and Hancock, E. (2003). Spectral embedding of
graphs. Pattern Recognition, 36(10):2213–2230.

Luo Non-negative Laplacian Embedding p10

Dijun

Luqman, M., Llad′os, J., Ramel, J.-Y., and Brouard, T. (2010a). A Fuzzy-Interval Based Approach for Explicit Graph Embedding. In Recognizing Patterns in Signals, Speech, Images and Videos, volume 6388, pages 93–98.

Luqman Fuzzy Graph Embedding p23

Luqman Fuzzy multilevel graph embedding p15

Luqman, M.M., Ramel, J.Y., Llad′os, J., Brouard, T.:

Fuzzy multilevel graph embedding.

Pattern Recognition 46(2), 551–565 (2013)

Okokok

[LUQMAN2012] Fuzzy Multilevel Graph Embedding for Recognition Indexing and Retrieval of Graphic Document Images p186
LUQMAN Fuzzy Multilevel Graph Embedding for Recognition Indexing and Retrieval of Graphic Document Images p186
LUQMAN Fuzzy Multilevel Graph Embedding for Recognition Indexing and Retrieval of Graphic Document Images p186
Muhammad Muzzamil LUQMAN
02 mars 2012

?

Graph probing based graph embedding methods

Spectral based graph embedding

Dissimilarity based graph embedding

Explicit Graph Embedding
Fuzzy Multilevel Graph Embedding

graph matching
exact graph matching
error-tolerant graph matching
Boolean graph matching

Graph retrieval
subgraph spotting
graph repository

adjacency matrices
Laplacian matrices
eigen-decomposition
eigenvalues of the adjacency matrix or Laplacian matrix
eigenvectors of the adjacency matrix or Laplacian matrix.
leading eigenvectors of the adjacency matrix
eigenspaces of adjacency matrices
eigenmode

Luqman Improving Fuzzy Multilevel Graph Embedding through Feature Selection Technique
Luqman Improving Fuzzy Multilevel Graph Embedding through Feature Selection Technique

Luqman,M.M., Ramel, J.Y., Llados, J.: Improving FuzzyMultilevel Graph Embedding through Feature Selection Technique. In: Structural, Syntactic, and Statistical Pattern Recognition. vol. 7626, pp. 243–253 (2012)

Luqman, M. M., Ramel, J.-Y., Llados, J., and Brouard, T. (2011b). Subgraph Spotting through Explicit Graph Embedding : An Application to Content Spotting in Graphic Document Images. In Eleventh International Conference on Document Analysis and Recognition (ICDAR), pages 870–874.

Luqman, M. M., Brouard, T., Ramel, J.-Y., and Llados, J. (2010c). Vers une approche floue d encapsulation de graphes : application `a la reconnaissance de symboles. In Colloque International Francophone sur l’Ecrit et le Document, pages
169–184.


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Madabhushi Graph Embedding to Improve Supervised Classification and Novel Class Detection: Application to Prostate Cancer

P. Mahe, N. Ueda, and T. Akutsu. Graph kernels for molecular structures
– activity relationship analysis with support vector machines. Journal of
Chemical Information and Modeling, 45(4):939–951, 2005.

Anil Maheshwari

13. Paul Manuel, Indra Rajasingh, Bharati Rajan and Helda Mercy, Exact Wirelength of Hypercubes on a Grid, Journal of Discrete Applied Mathematics, 157, (2009), 1486-1495.
14. Paul Manuel, Indra Rajasingh, Bharati Rajan and Helda Mercy, Exact Wirelength of Hypercube Layout on k-Cube Necklace, The Journal of Combinatorial Mathematics and Combinatorial Computation, 67, (2008), 67-76.
15. Paul Manuel, MostafaI.Abd-El-Barr, Indra Rajasingh and Bharati Rajan, An Efficient Representation of Benes Networks and its Applications, Journal of Discrete Algorithms, 6 (1), (2008), 11-19.
16. Paul Manuel, Indra Rajasingh, Bharati Rajan and Helda Mercy, Exact Wirelength of Hypercube and Enhanced Hypercube Layout on Regular Caterpillars, International Journal of Mathematics and Computer Science, 2 (2), (2007), 137-146.
9. Paul Manuel, M. Arockiaraj, Indra Rajasingh and Bharati Rajan, Embedding hypercubes into cylinders, snakes and caterpillars for minimizing wirelength, Discrete Applied Mathematics, 159, (2011), 2109–2116.

Prof. Antonio Marques

Akira Matsubayashi
[Matsubayashi2014] Separator-Based Graph Embedding into Multidimensional Grids with Small Edge-Congestion p30

Separator-Based Graph Embedding

[8] A. Matsubayashi, S. Ueno, Small congestion embedding of graphs into hypercubes,
Networks 33 (1999) 71–77.

Maymounkov Greedy Embeddings, Trees, and Euclidean vs. Lobachevsky Geometry p20

[MS09] T. Mchedlidze and A. Symvonis, Crossing-Optimal Acyclic Hamiltonian
Path Completion and Its Application to Upward Topological Book
Embeddings. InWorkshop on Algorithms and Computation (WALCOM
2009), volume 5431 of Lecture Notes in Computer Science, pp. 250–261.
Springer, 2009.

[MS10] T. Mchedlidze and A. Symvonis, On ?-Constrained Upward Topological
Book Embeddings, In17th International Symposium on Graph Drawing
(GD 2009), volume 5849 of Lecture Notes in Computer Science, pp. 411–
412. Springer, 2010.

Mu PROXIMITY-BASED GRAPH EMBEDDINGS FOR MULTI-LABEL CLASSIFICATION p11

Marina Meila
Marion Merklein

Andy Minaian

Andy Minaian

[Miy06] M. Miyaguchi, Topological book embedding of bipartite graphs.
InProceedings of IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, volume 89-A(5), pages 1223–
1226, 2006.

BOJAN MOHAR

[MOHAR1999] A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21
MOHAR A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21
MOHAR A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21
MOHAR A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21
B. Mohar, “A linear time algorithm for embedding graphs in an arbitrary surface”, SIAM J. Discrete Math. 12 (1999), no. 1, 6–26 (electronic).

3

induced embedding

Mohar Embedding graphs in an arbitrary surface in linear time p6

Prof. Angela Montanari

Moran Two-Page Book Embedding of Trees under Vertex-Neighborhood Constraints p11

BOOK EMBEDDING

Mousazadeh Embedding and function extension on directed graph p13

D.J. MUDER (1985), Book embeddings ofregular complete bipartite graphs, Typescript, The MITRE Corp.

Muhammad

Rashid Bin Muhammad

http://www.personal.kent.edu/~rmuhamma/GraphTheory/graphTheory.htm

http://www.personal.kent.edu/~rmuhamma/GraphTheory/MyGraphTheory/embedding.htm

okokok
Mumford Drawing Graphs for Cartographic Applications p144

Mumford Drawing Graphs for Cartographic Applications p144
Elena Mumford
2008

Murata VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair p7

Thomas Musch

P. Mutzel and R. Weiskircher. Optimizing over all combinatorial embeddings of a
planar graph. In IPCO: 7th Integer Programming and Combinatorial Optimization
Conference, volume 1610 of Lecture Notes Comput. Sci. Springer-Verlag, 1999. 357

Mutzel The Thickness of Graphs: A Survey p18

n-book embedding

Myrvolda

http://www.sciencedirect.com/science/article/pii/S0022000010000863

Errors in graph embedding algorithms

Wendy Myrvolda, 1, , E-mail the corresponding author,

William Kocayb, , 1, , E-mail the corresponding author


Untitled Document

Alaa A. Najim

Najim More faithfulness graph embedding p9

More faithfulness graph embedding
Continuity Trustworthy Graph Embedding (CTGE)
trustworthy embedding
Tree preserving embedding
Stochastic proximity embedding

Daniel Neilson

Michel Neuhaus
M. Neuhaus and H. Bunke. A graph matching based approach to fingerprint
classification using directional variance. In T. Kanade, A. Jain, and
N.K. Ratha, editors, Proc. 5th Int. Conference on Audio- and Video-Based
Biometric Person Authentication, LNCS 3546, pages 191–200. Springer,
2005.

M. Neuhaus and H. Bunke. Bridging the Gap Between Graph Edit Distance
and Kernel Machines. World Scientific, 2007.

[Newsome2003] GEM: Graph EMbedding for Routing and DataCentric Storage in Sensor Networks Without Geographic Information p13
James

NG Embedding Pyramids into 3D Meshes p12

Nguyen Gene Function Prediction via Discriminative Graph Embedding p2

Nikfarjam New Relations between Thickness and Outer Thickness of a Graph and its Arboricity p12

plane embedding

Nishana S S

okokok ?????????????/
[Nishana2013] Graph Embedding and Dimensionality Reduction - A Survey
Nishana Graph Embedding and Dimensionality Reduction - A Survey p6

Nishana S S et al., International Journal of Computer Science & Engineering Technology (IJCSET)
ISSN : 2229-3345 Vol. 4 No. 01 Jan 2013.

okokok
Nishana Graph Embedding and Dimensionality Reduction - A Survey
Nishana S S
Dept. Computer Science & Engineering
SCT College of Engineering
Trivandrum,India
nishanalilu@gmail.com
Subu Surendran
Associate Professor, Dept. Computer Science & Engineering
SCT College of Engineering
Trivandrum,India
subusurendran@gmail.com

Spectral graph theory

principal component analysis (PCA) have been applied to many graph embedding and dimensionality reduction tasks
underling manifold is a linear subspace
Multidimensional scaling (MDS)

locally linear embedding (LLE)
Minimum volume embedding (MVE)
Laplacian eigenmaps (LEM)
Isomap
semidefinite embedding (SDE)
structure preserving embedding
structure preserving embedding (SPE)
Structure Preserving Embedding (SPE) is an algorithm for embedding graphs in Euclidean space such that the embedding is low dimensional and preserves the global topological properties of the input graph.

k-nearest neighbor graph
pattern-space
covariance matrix.
graph-spectral decomposition methods
eigenvalues and eigenvectors of the adjacency matrix
Laplacian matrix
connectivity algorithms
k-Nearest Neighbor algorithm
bmatching or maximum weight spanning tree

linear and non linear dimensionality reduction techniques

[1] W.N. Anderson and T.D. Morley. Eigen values of the Laplacian of a graph. Linear and Multilinear Algebra, 18:141–145, 1985
[2] T. Cox and M. Cox. Multidimensional scaling. Chapman & Hall, London, UK, 1994.
[3] M. Belkin and P. Niyogi. Laplacian eigenmaps for dimensionality reduction and data representation. Neural Computation, 15(6), 2002.
[4] A. Ng, M. Jordan, and Y. Weiss. On spectral clustering: Analysis and an algorithm. In Neural Information Processing Systems 14, 2001.
[5] S. Roweis and L. Saul. Nonlinear dimensionality reduction by locally linear embedding. Science, 290(5500), 2000.
[6] L. Vandenberghe and S. Boyd. Semidefinite programming. SIAM Review, 38(1):49–95, 1996.
[7] K. Q. Weinberger, F. Sha, and L. K. Saul. Learning a kernel matrix for nonlinear dimensionality reduction. In Proceedings of the Twenty First International Conference on Machine Learning (ICML-04), pages 839–846, Banff, Canada, 2004.
[8] Blake Shaw &Tony Jebara,(2009).Structure Preserving Embedding Proceedings of the 26 th International Conference on Machine Learning.
[9] Shaw, B., & Jebara, T. (2007). Minimum volume embedding. Proc. of the 11th International Conference on Articial Intelligence and Statistics.
[10] Chung, F. R. K. (1997). Spectral graph theory. American Mathematical Society.
[11] Bin Luo, Richard C. Wilson, Edwin R. Hancock; Spectral embedding of graphs , Pattern Recognition Society. Published by Elsevier Science Ltd.2003.
[12] M. Balasubramanian and E.L. Schwartz. The Isomap algorithm and topological stability. Science, 295(5552):7, 2002.
[13] Arora, S., Rao, S., & Vazirani, U. (2004). Expanderows, geometric embeddings and graph partitioning. Symposium on Theory of Computing.
[14] Burer, S., & Monteiro, R. D. C. (2003). A nonlinear programming algorithm for solving semidefinite programs via low-rank factorization. Mathematical Programming (series B), 95(2), 329{357}.

Nishana Structure Preserving Embedding Based Face Recognition p7

Nishizeki

The book Planar Graphs: Theory and Applications by T. Nishizeki and N. Chiba (Dover Press) has a discussion both of planarity testing and embedding algorithms.

Zbigniew H. Nitecki

Partha Niyogi

Norouzitallab Heuristic Algorithms for Geometric Embedding of Complete Binary Trees onto a Point-set p5

okokok
Nurvitadhi GraphGen: Compiling Graph Algorithms for Accelerator Platforms p23


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Professor Jean-Marc Ogier

Oleg Okun

Deryk Osthus

[Ou1997] Asymmetric Transitivity Preserving Graph Embedding p10
Mingdong

Asymmetric Transitivity Preserving Graph Embedding
High-Order Proximity preserved Embedding
Neural word embedding
Partial Proximity Embedding
scalable embedding


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Pach Embedding planar graphs at fixed vertex locations p12

J. Pach, P. Gritzmann,B. Mohar, and R. Pollack, Embedding a
[PW98] J. Pach and R. Wenger, Embedding Planar Graphs at Fixed Vertex
Locations. In the 6th International Symposium on Graph Drawing (GD
1998), volume 1547 of Lecture Notes in Computer Science, pp. 263–274.
Springer, 1998.Planar Triangulation with Vertices at Specified Points. American Mathematical
Monthly, 98 (1991), pp. 165–166.

Pang

http://eprints.aston.ac.uk/25093/

Pang, Yanwei and Yuan, Yuan (2010).

Outlier-resisting graph embedding.

Neurocomputing, 73 (4-6), pp. 968-974.

Papakonstantinopoulou The Geometry of Graphs and its Algorithmic Applications p44

oko
Patrignani complexity results for three-dimensional orthogonal graph drawing p34

Patrignani Planarity Testing and Embedding p42

Pavlou Tutte Embedding:How to Draw a Graph p29

okokok
Pendavingh Graph minors and embeddings
Rudi Pendavingh

Merijam Percan

Dominique C. Perrault-Joncas
okokok
Perrault-Joncas Directed Graph Embedding: an Algorithm based on Continuous Limits of Laplacian-type Operators

Perrault-Joncas Directed Graph Embedding: an Algorithm based on Continuous Limits of Laplacian-type Operators p9

Perrault-joncas

http://machinelearning.wustl.edu/mlpapers/papers/NIPS2011_0611

Directed Graph Embedding: an Algorithm based on Continuous Limits of Laplacian-type Operators

Authors: Dominique C. Perrault-joncas and Marina Meila

Directed Graph Embedding

Matti Pietikainen

Diana Piguet

Maurizio Pizzonia

Pizzonia Minimum Depth Graph Embedding p12

Pizzonia Minimum Depth Graph Embedding p12

Minimum Depth Graph Embedding
block-preserving embedding
Dynamic grid embedding

David Plaisted

okokok
[Potoczak2014] Survey of Graph Embeddings into Compact Surfaces p117.pdf

Sophia N. Potoczak
8-2014

non-surface separating graph embeddings

topological graph theory is concerned with embedding graphs into compact surfaces.

Ch. Pris?acaru, P. Soltan, V. Chepoi, On embeddings of planar graphs into hypercubes, Proc.
Moldavian Academy of Sci., Math. 1 (1990), 43{50 (Russian).


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H. Qiu and E. Hancock. Clustering and embedding using commute times. IEEE Transactions on Pattern Analysis and Machine Intelligence, 29(11):1873– 1890, 2007. 2

H. Qiu and E. Hancock. Clustering and embedding using commute times. IEEE Transactions on Pattern Analysis and Machine Intelligence, 29(11):1873– 1890, 2007.


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Francois - Rabelais

Y. Rabinovich and R. Raz. Lower bounds on the
distortion of embedding finite metric spaces in graphs.
Discrete & Computational Geometry, 19(1):79–94,
1998.

[Rajan2015] Embeddings Between Hypercubes and Hypertrees p13
R. Sundara Rajan 1 Paul Manuel 2 Indra Rajasingh 3

17. Indra Rajasingh, Paul Manuel, Jasintha Quadras and Albert William, Embedding of Cycles and Wheels into Arbitrary Trees, Networks, (2004), 173-176.
18. Indra Rajasingh, Jasintha Quadras and Paul Manuel, Embedding of Generalized Wheels into Arbitrary Trees, Electronic notes in Discrete Mathematics, (2003), 1-3.

Indra Rajasingh, Paul Manuel, Bharati Rajan and M. Arockiaraj, Wirelength of hypercubes into certain trees, Discrete Applied Mathematics (Elsevier Publication), 10.1016/j.dam.2011.12.007.
2. Indra Rajasingh, Bharati Rajan and R. Sundara Rajan, On embedding of special classes of circulant networks, hypercubes and generalized Petersen graphs, International Journal of Computer Mathematics, in press.
3. Indra Rajasingh, Paul Manuel, M. Arockiaraj and Bharati Rajan, Embedding of circulant networks, Journal of Combinatorial Optimization (Springer Publication), DOI 10.1007/s10878-011-9443-x
4. Indra Rajasingh, Bharati Rajan and R. Sundara Rajan, Embedding of Hypercubes into Necklace, Windmill and Snake Graphs, Information Processing Letters, 112, (2012), 509–515.
5. Indra Rajasingh, M. Arockiaraj, Bharati Rajan and Paul Manuel, Minimum wirelength of hypercubes into n-dimensional grid networks, Information Processing Letters, 112, (2012), 583–586.
6. Indra Rajasingh, M. Arockiaraj, Bharati Rajan and Paul Manuel, Circular wirelength of generalized Petersen graphs, Journal of Interconnection Networks, 12 (4), (2011), 319–335.
7. Indra Rajasinghand M. Arockiaraj, Linear wirelength of folded hypercubes, Mathematics in Computer Science (Springer Publication), 5, (2011), 101-111.
10. Indra Rajasingh, Bharati Rajan and R. Sundara Rajan, Combinotorial properties in Circulant Networks, IAENG International Journal of Applied Mathematics, 41 (4), (2011), 352-356.
11. Indra Rajasingh, Bharati Rajan, R. SundaraRajan and Paul Manuel, Embedding in Fat Trees, Journal of Combinatorial Mathematics and Combinatorial Computation, 79, (2011), 139-146.
12. Indra Rajasingh, Bharati Rajan and R.Sundara Rajan, On Embedding of m-sequential k-ary Trees into Hypercubes, Applied Mathematics, 1 (6), (2010), 499-503.

Prof. Ketan Rajawat

L. Ralaivola, S.J. Swamidass, H Saigo, and P. Baldi. Graph kernels for
chemical informatics. Neural Networks, 18(8):1093–1110, 2005.

okokok
Ramamurthy Learning Dictionaries with Graph Embedding Constraints for Image Classification

Dr. Jean-Yves Ramel

okokok

Ramel Graph Embedding Probem p37

embeds each input graph into a numeric feature vector

Map each graph to a feature vector

implicit graph embedding function

Graph kernels

k(x, x') = <?(x), ?(x')>

?: mapping two objects x and x' into feature space H.

Explicit Graph Embedding
? Graph probing based methods
? Spectral based graph embedding

Carla Rampichini

Raveaux Graph Embedding Problem p37

Romain Raveaux

okokok

Raveaux Graph Embedding Probem p37
Graph kernels
Implicit Graph Embedding
(NP-complex) ?
Common local subtrees kernels
Common (label) walk kernels
Direct Graph Product
Explicit Graph Embedding
? Graph probing based methods
? Spectral based graph embedding

Renz Hierarchical Graph Embedding for Efficient Query Processing in Very Large Traffic Networks p30

Hierarchical Graph Embedding
flat embedding
multi-level embedding
reference node embedding
Multi-Level Graph Embedding

okokok
Richiardi Vector space embedding of undirected graphs with fixed-cardinality vertex sequences for classification

?
Richiardi Vector space embedding of undirected graphs with fixed-cardinality vertex sequences for classification p4

Arne Rick

Dick de Ridder

D. d. Ridder and R. P. Duin,
"Locally Linear Embedding for Classification," in Pattern Recognition Group, The Netherlands, 2002.

Ridder Supervised locally linear embedding p8

(16) K. Riesen, M. Neuhaus, and H. Bunke. Bipartite graph matching for computing the edit distance of graphs. In F. Escolano and M. Vento, editors, Proc. 6th Int. Workshop on Graph Based Representations in
Pattern Recognition, LNCS 4538, pages 1–12, 2007.

okokok

[Riesen2009] Classification and Clustering of Vector Space Embedded Graphs p344
Oktober 2009

2016-5-1
Kaspar Riesen
http://www.fhnw.ch/personen/kaspar-riesen
Dr. Kaspar Riesen
Hochschule für Wirtschaft
Institut für Wirtschaftsinformatik
Riggenbachstrasse 16, 4600 Olten
kaspar.riesen@fhnw.ch

Swiss National Science Foundation
http://www.snf.ch/
international@snf.ch
personal@snf.ch
com@snf.ch
cosi@snf.ch

graph matching
Graph Isomorphism
Subgraph Isomorphism
Mapping
graph mapping
graph clustering

vector space embeddings of graphs
Graph Embedding Using Dissimilarities
Lipschitz Embeddings
dissimilarity embeddings for graphs

Topological descriptors, for instance, aim at a vectorial summary of the graph’s topology.

The Wiener index [264], defined as the sum over all shortest paths in a graph, is a prominent example of such a descriptor.

6.1.1 Graph Embedding Techniques
From another perspective, graph embeddings can be viewed as an extraction of descriptive numerical features from graphs. P135

SparseMap

(19) K. Riesen and H. Bunke. Classifier ensembles for vector space embedding of graphs. In M. Haindl, J. Kittler, and F. Roli, editors, Proc. 7th Int. Workshop on Multiple Classifier Systems, LNCS 4472, pages
220–230, 2007.

(5) K. Riesen and H. Bunke. Cluster ensembles based on vector space embeddings of graphs. In J. A. Benediktsson, J. Kittler, and F. Roli, editors, Proc. 8th International Workshop on Multiple Classifier Systems, LNCS 5519, pages 211–221, 2009.
[315] K. Riesen and H. Bunke. Cluster ensembles based on vector space embeddings of graphs. In J.A. Benediktsson, J. Kittler, and F. Roli, editors, Proc. 8th Int. Workshop on Multiple Classifier Systems, LNCS 5519, pages September 8, 2009 10:42 Dissertation Riesen - 9in x 6in main 211–221, 2009.

(4) K. Riesen and H. Bunke. Dissimilarity based vector space embedding of graphs using prototype reduction schemes. In P. Perner, editor, Proc. 6th International Conference on Machine Learning and Data Mining in Pattern, LNCS 5632, pages 617–631, 2009.

?(3) K. Riesen, S. Fankhauser, and H. Bunke. Efficient Suboptimal Graph Isomorphism. In A. Torsello, F. Escolano, and L. Brun, editors, Proc. 7th Int. Workshop on Graph Based Representations in Pattern Recognition, LNCS 5534, pages 124–133, 2009.

(2) K. Riesen, X. Jiang, and H. Bunke. Exact and inexact graph matching – methodology and applications. To appear in book Managing and Mining Graph Data.

(1) K. Riesen and H. Bunke. Feature ranking algorithms for improving classification of vector space embedded graphs. In X. Jiang and N. Petkov, editors, Proc. 13th International Conference on Computer
Analysis of Images and Patterns, LNCS 5702, pages 377–384, 2009.

[Riesen and Bunke, 2010a] Riesen, K. and Bunke, H. (2010a). Graph Classification and Clustering Based on Vector Space Embedding. World Scienti c.
Riesen, K. and Bunke, H. (2010b). Graph Classification And Clustering Based On Vector Space Embedding. World Scientific Publishing Co., Inc.

Riesen, K. and Bunke, H. (2009). Graph classification based on vector space embedding. International Journal of Pattern Recognition and Artificial Intelligence, 23(6):1053–1081.
Riesen, K., Bunke, H.: Graph classification based on vector space embedding. IJPRAI 23(6), 1053–1081 (2009)

[279] K. Riesen and H. Bunke. Graph classification by means of Lipschitz embedding. Accepted for publication in IEEE Transactions on Systems, Man, and Cybernetics (Part B).
(4) K. Riesen and H. Bunke. Graph classification by means of Lipschitz embedding. Accepted for publication in IEEE Transactions on Systems, Man, and Cybernetics (Part B).

Riesen, K., Neuhaus, M., and Bunke, H. (2007). Graph embedding in vector spaces by means of prototype selection. In International Conference on Graphbased Representations in Pattern Recognition, pages 383–393. Springer-Verlag.
[304] K. Riesen, M. Neuhaus, and H. Bunke. Graph embedding in vector spaces by means of prototype selection. In F. Escolano andM. Vento, editors, Proc. 6th Int. Workshop on Graph Based Representations in Pattern Recognition, LNCS 4538, pages 383–393, 2007.
K. Riesen, M. Neuhaus, and H. Bunke.
Graph embedding in vector spaces by means of prototype selection. In Proceedings of the 6th IAPR-TC-15 international conference on Graph-based representations in pattern recognition, pages 383–393. Springer-Verlag, 2007. 1, 2, 3, 4

(2) K. Riesen, V. Frinken, and H. Bunke. Improving graph classification by isomap. In A. Torsello, F. Escolano, and L. Brun, editors, Proc. 7th Int. Workshop on Graph Based Representations in Pattern Recognition, LNCS 5534, pages 205–214, 2009.

(6) K. Riesen and H. Bunke. Kernel k-means clustering applied to vector space embeddings of graphs. In L. Prevost, S. Marinai, and F. Schwenker, editors, Proc. 3rd IAPR Workshop Artificial Neural Networks in Pattern Recognition, LNAI 5064, pages 24–35. Springer, 2008.
[309] K. Riesen and H. Bunke. Kernel k-means clustering applied to vector space embeddings of graphs. In L. Prevost, S. Marinai, and F. Schwenker, editors, Proc. 3rd IAPR Workshop Artificial Neural Networks in Pattern Recognition, LNAI 5064, pages 24–35. Springer, 2008.

?(11) K. Riesen and H. Bunke. Non-linear transformations of vector space embedded graphs. In A. Juan-Ciscar and G. Sanchez-Albaladejo, editors, Pattern Recognition in Information Systems, pages 173–186, 2008.

?(10) K. Riesen and H. Bunke. On Lipschitz embeddings of graphs. In I. Lovrek, R.J. Howlett, and L.C. Jain, editors, Proc. 12th International Conference, Knowledge-Based Intelligent Information and Engineering Systems, Part I, LNAI 5177, pages 131–140. Springer, 2008.

?(18) K. Riesen and H. Bunke. Structural classifier ensembles for vector space embedded graphs. In In Proc. 20th Int. Joint Conf. on Neural Networks, pages 1500–1505, 2007.

[Robles-Kelly and Hancock, 2007] Robles-Kelly, A. and Hancock, E. (2007). A Riemannian
approach to graph embedding. Pattern Recognition, 40(3):1042–1056.

A. Robles-Kelly and E. R. Hancock. A riemannian approach to graph embedding.
Pattern Recognition, 40(3):1042–1056, 2007.

Antonio Robles-Kelly

okokok
[Robles-Kelly2007] A Riemannian approach to graph embedding
Robles-Kelly A Riemannian approach to graph embedding p15

[Rodl1999] Hypergraph packing and graph embedding p18
Rodl Hypergraph packing and graph embedding??

okokok
Rodl Hypergraph packing and graph embedding p18
1999

http://journals.cambridge.org/article_S0963548399003879

Hypergraph Packing and Graph Embedding

V. R?DL a1 1 , A. RUCINSKI a2 2 and A. TARAZ a3 3
a1 Emory University, Atlanta, GA, USA (e-mail: rodl@mathcs.emory.edu)
a2 A. Mickiewicz University, Poznan, Poland (e-mail: rucinski@math.amu.edu.pl)
a3 Humboldt University, Berlin, Germany (e-mail: taraz@informatik.hu-berlin.de)

Rosenberg AL : On embedding graphs in grids . IBM Watson Research Center Tech.
Rep. RC 7559 (#2668), 1979 .
A. L. Rosenberg, Graph embeddings 1988: recent breakthroughs, new directions, VLSI algorithms and architectures (Corfu, 1988), Lecture Notes in Computer Science, Springer, New York, 319(1988) 160 - 169.

Arnold Rosenberg
ARNOLD L. ROSENBERG

Rosman Topologically Constrained Isometric Embedding p6

Roth Simpler projective plane embedding p21

M. R¨ottger, U.-P. Schroeder, Embedding 2-dimensional grids into optimal hypercubes
with edge-congestion 1 or 2, Parallel Process. Lett. 8 (1998) 231–242.

Sam T. Roweis

Ruzzo WL, Snyder L : Minimum edge length planar embeddings of trees . CMU Conf
on VLSI Systems and Computations, 1981 .


Untitled Document

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Saito Graph Embedding on Spheres and its Application to Visualization of Information Diffusion Data p8
2012
embedding methods:

multi-dimensional scaling [15],

cross entropy embedding [16].
spectral embedding [2],
spring force embedding [4]
Spherical embedding [11, 3]
power iteration

R. Sarkar. Low distortion Delaunay embedding of
trees in hyperbolic plane. In Proc. 19th International
Symposium on Graph Drawing, pp. 355–366, 2012.

Swami Sarvottamananda

okokok
Sarvottamananda Planar Graphs, Planarity Testing and Embedding p151
Sarvottamananda Planar Graphs, Planarity Testing and Embedding p151
Swami Sarvottamananda
Ramakrishna Mission Vivekananda University
BESU-IGGA, March 2013

SPQR-trees
maximal planar graph
biconnected or 2-connected graph

74

Lawrence K. Saul

Saul An Introduction to Locally Linear Embedding p13

L. K. Saul and S. T. Roweis,

"An Introduction to Locally Linear Embedding,"

2001. [Online]. Available: https://www.cs.nyu.edu/~roweis/lle/papers/lleintro.pdf. [Accessed 4 February 2012].

principal component analysis (PCA)
multidimensional scaling (MDS)

B. Le Saux and H. Bunke. Feature selection for graph-based image classifiers.
In J. Marques, N. Perez de Blanca, and P. Pina, editors, Proc. 2nd
Iberian Conference on Pattern Recognition and Image Analysis, Part II,
LNCS 3523, pages 147–154. Springer, 2005.

James B. Saxe

[Saxe1980] Two papers on graph embedding problems p41

Saxe Two papers on graph embedding problems p41

Marcus Schaefer

A. Schenker, H. Bunke, M. Last, and A. Kandel. Graph-Theoretic Techniques
for Web Content Mining. World Scientific, 2005.

A. Schenker, M. Last, H. Bunke, and A. Kandel. Classification of web documents using graph matching. Int. Journal of Pattern Recognition and
Artificial Intelligence, 18(3):475–496, 2004.

Prof. Ioannis Schizas

okokok
Schnyder Embedding Planar Graphs on the Grid

W. Schnyder. Embedding planar graphs on the grid. In Proceedings of the 1st
ACM-SIAM Symposium on Discrete Algorithms (SODA), pages 138{148, 1990.

Schuon Truly Incremental Locally Linear Embedding p5

Michael Schulz

Sensen

http://www2.cs.uni-paderborn.de/fachbereich/AG/monien/RESEARCH/EMBED/

Norbert Sensen

Serratosa Graph Indexing and Retrieval based on Median Graphs p10

Shahabi A road network embedding technique for k-nearest neighbor search in moving object databases p19

SHARMA 3D Shape Registration Using Spectral Graph Embedding and Probabilistic Matching p39

Y. Shavitt and T. Tankel. Hyperbolic embedding of
internet graph for distance estimation and overlay
construction. ACM Trans. on Networking,
16(1):25–36, 2008.

okokok

[Shaw2011] Graph Embedding and Nonlinear Dimensionality Reduction p108?

Shaw Graph Embedding and Nonlinear Dimensionality Reduction p108

Shaw Graph Embedding and Nonlinear Dimensionality Reduction p108
Blake Shaw
PhD thesis, COLUMBIA UNIVERSITY, 2011
37

Blake Shaw
http://metablake.com/b/home.html
contact@metablake.com

A. Ghodsi
https://www.cs.berkeley.edu/~alig/
alig@cs.berkeley.edu

T. Jebara
http://www1.cs.columbia.edu/~jebara/papers.html
jebara@cs.columbia.edu

Action Respecting Embedding (ARE)
Action Respecting Embedding (ARE)
Locally linear embedding
locally linear embedding (LLE)
low-dimensional embeddings
low-dimensional embedding
Minimum volume embedding (MVE)
minimum volume embedding (MVE)
spectral embedding
spectral embedding
spring embedding techniques
Spring embedding techniques
structure preserving embedding (SPE)
structure preserving embedding (SPE)
weighted graph embedding

Laplacian eigenmaps
Laplacian eigenmaps
Eigendecomposition
eigen-decomposition
singular value decompositions (SVD)
spectral methods
spectral
decomposition

spectral fidelity
spectral fidelity measures how much of the variance of the original data is preserved by the embedding

Formally the problem of graph embedding can be stated as follows: given a graph G = (V;E)
with n = |V| ?nodes and |E| edges, find for each node a vector yi ∈ Rd for i = 1; : : : ; n.
In this thesis we focus on low-dimensional embeddings where d is small.

Graph embedding algorithms place vertices at points on a surface, typically Euclidean space, and connect vertices with an arc if the vertices have an edge between them.

drawing graphs so that they have certain aesthetic qualities to embedding graphs in VLSI chip designs to minimize fabrication cost [Chung, 1997, Battista et al., 1999]

graph embedding algorithms suited for dimensionality reduction, visualization, and metric learning

graph drawing is to minimize edge crossings

hyperspheres

semidefinite programing
sequential SDP

Maximum variance unfolding (MVU)
Colored MVU

eigenspectrum.

principal component analysis (PCA)
kernel PCA
kernel matrix to be used with kPCA

Multidimensional Scaling (MDS)

singular value decomposition

Isomap

Manifold
linear manifold
natural manifold
minimum volume manifold

kernel matrix
Gram matrix or kernel matrix
positive semidefinite kernel matrix
mercer kernel
sparse connectivity matrix

saddle-point optimization

metric learning algorithms
unsupervised metric learning algorithms
Structure Preserving Metric Learning SPML

Mahalanobis distance metric
geodesic distances

class impostors,
graph impostors
graph topology

convex hull of matrices

B. Shaw and T. Jebara. Minimum volume embedding. In Marina Meila and Xiaotong Shen, editors, Proc. of the 11th International Conference on Artificial Intelligence and Statistics, volume 2 of JMLR: W&CP, pages 460{467, March 2007.

B. Shaw and T. Jebara. Minimum Volume Embedding (MVE) Matlab Code. http://www.metablake.com/mve
2008.

[Shaw2009] Structure Preserving Embedding
Shaw Structure Preserving Embedding p8

okokok
Shaw Structure Preserving Embedding

Structure Preserving Embedding (SPE)
Locally Linear Embedding (LLE),
Maximum Variance Unfolding (MVU)
Minimum Volume Embedding (MVE)
spectral embedding
reversible graph embeddings (from a graph to points back to a graph)
spring embedding

Euclidean space
global topological properties
input graph
Topology
connectivity algorithm
k-nearest neighbors
semidefinite program
low-rank kernel matrix
linear inequalities
Laplacian eigenmaps.
dimensionality reduction algorithms
graph's binary connectivity

hyperplanes

singular value decomposition (SVD)
principal component analysis (PCA)
d eigenvectors of A
largest eigenvalues

Mobius Ladder Graph
adjacency matrix

positive semi-definite kernel matrix

connectivity algorithm ( k-nearest neighbors, b-matching, or maximum weight spanning tree)
kernel K
convex optimization
semidefinite programming

Multidimensional scaling
Nonlinear manifold learning algorithms
binary connectivity
manifold learning techniques

connectivity matrix A
kernel matrix K
k-nearest neighbors
epsilon-balls
maximum weight spanning trees
maximum weight generalized matching

Nearest Neighbor Graphs
k-nearest neighbor algorithm (knn)
Maximum weight subgraph
maximum weight spanning tree

dimensionality reduction

Shaw Visualizing Graphs with Structure Preserving Embedding p6

Shaw Visualizing Graphs with Structure Preserving Embedding p6
2008
Blake Shaw
Department of Computer Science
Columbia University
New York, NY 10027
blake@cs.columbia.edu
Tony Jebara
Department of Computer Science
Columbia University
New York, NY 10027
jebara@cs.columbia.edu

Structure Preserving Embedding (SPE)
spectral embedding
spring embedding

okokok
Shi Supervised Graph Embedding for Polarimetric SAR Image Classification

Shieh Tree Preserving Embedding p6

Shieh Tree Preserving Embedding p8

Shirazi CLUSTERING ON GRASSMANN MANIFOLDS VIA KERNEL EMBEDDING WITH APPLICATION TO ACTION ANALYSIS p4

Ali Shokoufandeh

Shokoufandeh Embedding and Spectrum of Graphs p91

okokok
Shokoufandeh Embedding and Spectrum of Graphs p91
isometric embedding
Non-embedability

Approximation Algorithms
Geometry of Graphs and Graphs Encoding the Geometry

Algebraic graph Theory (the study of matrices associated with a graph).
Algorithmic Graph Theory
Spectral Graph Theory

S.V. Shpectorov, On scale embeddings of graphs into hypercubes, Europ. J. Combin. 14
(1993), 117{130.

Chang Shu

Sid`ere, N. (2012). Contribution aux m′ethodes de reconnaissance structurelle
de formes : approche `a base de projections de graphes. PhD thesis, Universit′e Fran?cois-
Rabelais de Tours, France.

Sid`ere, N., H′eroux, P., and Ramel, J.-Y. (2009a). Embedding labeled
graphs into occurence matrix. In 8th International Workshop on Graphics Recognition,
pages 44–50.

Nikos Sidiropoulos
Prof. Nikos Sidiropoulos

[Simonraj2012] Embedding of Poly Honeycomb Networks and the Metric dimension of Star of David Network p18

Simonraj Embedding of Poly Honeycomb Networks and the Metric dimension of Star of David Network p18

Michiel Smid

[Song2012] Clustered Embedding of Massive Social Networks p12

Song Clustered Embedding of Massive Social Networks p12
Clustered Embedding
Clustered Spectral Graph Embedding
SGE and Proximity Embedding

dr. B. Speckmann
faculteit Wiskunde & Informatics
Technische Universiteit Eindhoven

Spielman Spectral Graph Theory and its Applications p75

Don Stanat

Domenico De Stefano

[Stefano2012] Graph embedding via dissimilarity mapping for network comparison p4

okokok
Stefano Graph embedding via dissimilarity mapping for network comparison

graph embedding in vector space (GEVS)
Graph embedding in vector space via dissimilarity mapping

dissimilarity representation framework
graph edit distance
dimensionality reduction of the embedding
graph matching
inexact graph isomorphism between two graphs
Pattern Recognition (PR)
dissimilarity mapping approach
Erdos-Renyi Random Graph distribution
Exponential Random Graphs Distributions

References
1. Bunke, H., Irniger, C., Neuhaus, M.: Graph Matching: Challenges and Potential Solutions.
In: Roli, F., Vitulano, S. (eds.) ICIAP 2005, lncs vol.3617, pp. 1-10. Springer, Berlin (2005)
2. Conte, D., Foggia, P., Sansone, C., Vento, M.: Thirty years of graph matching in pattern
recognition. Int. J. Pattern Recognit. Artif. Intell. 18, 265298 (2004)
3. Doreian, P., Batagelj, V. and Ferligoj, A.: Generalized Blockmodeling. Cambridge University
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4. Pekalska, E., and Duin, R.P.W.: The Dissimilarity Representation for Pattern Recognition,
Foundations and Applications, World Scientific, Singapore (2005)
5. Valveny, E., Ferrer, M.: Application of Graph Embedding to Solve Graph Matching Problems.
In: CIFED 2008 (2008)

Stephenson Discrete Conformality and Graph Embedding p96

SUDAKOV A RANDOMIZED EMBEDDING ALGORITHM FOR TREES p26

Subu Surendran

Subhash Suri

okokok
Sudakov Nearly optimal embeddings of trees p36
Benny Sudakov

Szalkai Graph Theoretical Analysis Reveals: Women's Brains are Better Connected than Men's p23


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Prof. Dr. Salvatore-Antoine Tabbone
Laboratoire lorrain de recherche en informatique et ses applications
Universite de Nancy
Salvatore-Antoine TABBONE
Salvatore Tabbone

Tahir Shock Graph for Representation and Modeling of Posture p9

Tahmasbi Orthogonal thickness of graphs p4

R. Tamassia, A dynamic data structure for planar graph embedding, in ‘‘Automata,
Languages and Programming roc. 15th ICALP.’’ T. Lepisto and A. Salomaa, Eds..,
Lecture Notes in Computer Science, Vol. 317, pp. 576]590, Springer-Verlag, BerlinrNew
York, 1988.

R. Tamassia. On embedding a graph in the grid with the minimum number of
bends. SIAM J. Comput., 16(3):421–444, 1987. 357

R. Tomassia, On-line planar graph embedding, J. Algorithms 21 (2)
(1996) 201–239.

Roberto Tamassia

Tamassia On-line Planar Graph Embedding p39

Tamassia On-line Planar Graph Embedding p39
JOURNAL OF ALGORITHMS 21, 201- 239 (1996).ARTICLE NO. 0044
Received May 5, 1989
Roberto Tamassia
Department of Computer Science, Brown Uni¨ersity, Pro¨idence,
Rhode Island 02912-1910

planar embedding of a planar graph
On-line Planar Graph Embedding
hierarchical embedding problem
incremental embedding problem
dynamic embedding problem

dynamic data structure
dynamization of graph algorithms

spherical st-orientation
bipolar orientations and cylindric orientations of planar graphs

cut vertex
2-connected if it has no cutvertices, and 1-connected otherwise.

p 11

Tao Learning and Mining with Visual Data on the Web p272

Terada Local Ordinal Embedding p13
Date 2014-01-30
Yoshikazu Terada, Ulrike von Luxburg
Yoshikazu Terada
terada@sigmath.es.osaka-u.ac.jp

graph embedding (graph drawing) becomes a special case of ordinal embedding.
ordinal embedding problem

  1. Soft Ordinal Embedding (SOE)
    1. SOE for graph embedding problem = Local Ordinal Embedding (LOE) (LOE is one of graph embedding methods for unweighted graphs)

Tierny ·Enhancing 3D Mesh Topological Skeletons with Discrete Contour Constrictions p14

Tiwari

http://www.ncbi.nlm.nih.gov/pubmed/23294985

Abstract Send to: Med Image Anal. 2013 Feb;17(2):219-35. doi: 10.1016/j.media.2012.10.004. Epub 2012 Dec 13.

Multi-kernel graph embedding for detection, Gleason grading of prostate cancer via MRI/MRS.

Tiwari P1, Kurhanewicz J, Madabhushi A. Author information

1Department of Biomedical Engineering, Case Western Reserve University, 10900 Euclid Avenue Cleveland, OH 44106-7207, United States. pallavi.tiwari@case.edu

okokok
Tiwari Semi Supervised Multi Kernel (SeSMiK) Graph Embedding

Topplot

http://www.findbestopensource.com/product/topplot

Topplot - Spatial Graph Embedding Plotter and Analyzer

Topplot

http://www.findbestopensource.com/product/topplot

Topplot - Spatial Graph Embedding Plotter and Analyzer

Torselloa Graph embedding using tree edit-union p13

A. Torsello and E. R. Hancock. Graph embedding using tree edit-union. Pattern
Recognition, 40(5):1393–1405, 2007.

Gilles Trédan

ANDREW TREGLOWN

Howard Trickey

Tseng Human actionrecognitionbasedongraph-embedded spatio-temporalsubspace p7


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Uehara The graph isomorphism problem on geometric graphs p10


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okokok

Vadapalli Fault Tolerant Ring Embedding in Tetravalent Cayley Network Graphs p12
Premkumar Vadapalli and Pradip K Srimani

okokok
Valveny Application of Graph Embedding to solve Graph Matching Problems
Valveny Application of Graph Embedding to solve Graph Matching Problems p7
Ernest Valveny

Valveny, E., Ferrer, M.: Application of Graph Embedding to Solve Graph Matching Problems.
In: CIFED 2008 (2008)

okokok

[Valveny2015] Vector Space Embedding of Graphs via Statistics of Labelling Information p14

Varini ISOLLE Locally Linear Embedding with Geodesic Distance p12

UMESH VAZIRANI
UC Berkeley

Michel van de Velden

Kevin Verbeek

Verbeek Metric Embedding, Hyperbolic Space, and Social Networks p10

Verbeek Metric Embedding, Hyperbolic Space, and Social Networks p10

hyperbolic-space embedding
Low distortion Delaunay embedding

Michel Verleysen

Maurizio Vichi

Vinícius Complexity dichotomy on partial grid recognition p10

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[VITCC2013] Graph Embedding


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Wan Local Graph Embedding Based on Maximum Margin Criterion (LGE/MMC) for Face Recognition

Wang Knowledge Graph and Text Jointly Embedding p11

okokokl
Wang Knowledge Graph Embedding by Translating on Hyperplanes

Wang

Zhen Wang, Jianwen Zhang, Jianlin Feng, and Zheng Chen July 2014

http://research.microsoft.com/apps/pubs/default.aspx?id=225161

Knowledge Graph Embedding by Translating on Hyperplanes

Wang Knowledge Graph Embedding by Translating on Hyperplanes p9

entity embeddings
word embedding

Wang Local Linear Embedding Algorithm with Adaptively Determining Neighborhood p8

Wang Loop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architecture for Data-Intensive Applications p9

Wei Graph Embedding Based Feature Selection p5

Robert Weigel

Asia Weiss
Asia Weiss
http://weiss.info.yorku.ca/
Professor????
Department of Mathematics and Statistics
Faculty of Science
York University Toronto, Ontario. M3J 1P3

Telephone: 416- 736-2100 x 33966
Fax: 416-736-5757
weiss@mathstat.yorku.ca
http://www.birs.ca/
http://weiss.info.yorku.ca/

Benjamin Weiss

prof. dr. J.J. van Wijk
(Technische Universiteit Eindhoven)

E. Wilkeit, Isometric embedding in Hamming graphs, J. Combin. Th. Ser. B 50 (1990),
179{197.

okokok
Wilkinson Multidimensional Scaling p30

S. G.Williamson, Embedding graphs in the plane — algorithmic aspects, Ann. Discrete
Math. 6 (1980) 349–384.

P.M. Winkler, Isometric embedding in the product of complete graphs, Discr. Appl. Math.
7 (1984), 221{225.

Wilson Network Characterisation and Similarity p93

Wilson Similarities Distances and Manifold Learning p80

Winterbach A crossing number lower bound via algorithmic graph{to{graph embedding p4
Winterbach A crossing number lower bound via algorithmic graph–to–graph embedding1 p4

Wismath Straight line drawings of graphs in three dimensions p11

Ernst Wit

Wood Bounded Degree Book Embeddings and Three-Dimensional Orthogonal Graph Drawing p16

Wright bumbleBEE and Hornet An Apian Progress Report p23

Wu Dimension Reduction and Low-dimensional Embedding p26

Wu Graph Embedding (GE) Marginal Fisher Analysis (MFA)

Stefanie Wuhrer

Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230


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Xiao From One Point to A Manifold: Knowledge Graph Embedding For Precise Link Prediction p7
Han Xiao

Gaussian embedding
Knowledge Graph Embedding
manifold-based embedding principle
probabilistic embedding method
Structured Embedding

[268] B. Xiao, A. Torsello, and E. Hancock. Isotree: Tree clustering via metric
embedding. Neurocomputing, 71:2029–2036, 2008.

okokok
XIONG Boosting Graph Embedding with Application to Facial Expression Recognition

R. Xu and D. Wunsch. Survey of graph clustering algorithms. IEEE Transactions
on Neural Networks, 16(3):645–678, 2005.

Xu Efficient Geometric Algorithms and Applications p117

XU Ship radiated noise feature extraction using multiple kernel graph embedding and auditory model p30

XU Survey on path and cycle embedding in some networks


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Yan

http://www.hindawi.com/journals/ijdsn/2014/607943/

A Graph Embedding Method Based on Sparse Representation for Wireless Sensor Network Localization

Xiaoyong Yan,1,2,3 Aiguo Song,1,2 and Hao Yan4

???????????????????

okokokok
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[Yan2007] Graph Embedding and Extensions A General Framework for Dimensionality Reduction
Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction
Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p12
Yan Graph Embedding and Extensions: A General Framework for Dimensionality Reduction p12
S. Yan et al., “Graph embedding and extensions: a general framework for dimensionality reduction,” TPAMI, 29(1), 40-51, 2007.
S. Yan et al., “Graph embedding and extensions: a general framework for dimensionality reduction,” TPAMI, 29(1), 40-51, 2007.

3

Yan Graph Embedding and Extensions: A General Framework for Dimensionality Reduction p21

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Yan Graph Embedding and Extensions:? A General Framework for Dimensionality Reduction p54.ppt
Yan Graph Embedding and Extensions: A General Framework for Dimensionality Reduction p54.ppt
Yan Graph Embedding and Extensions: A General Framework for Dimensionality Reduction p54

LPP
preserves local relationships in the data set, and uncovers its essential manifold structure

Tensor based algorithms
2DPCA, 2DLDA, DATER

okokok
[Yang2008] Non-Negative Graph Embedding
Yang Non-Negative Graph Embedding p8
J. Yang, S. Yan, Y. Fu, X. Li, and T. Huang. Non-Negative Graph Embedding. IEEE Conf. on Computer Vision and Pattern Recognition, 2008.

Linear Discriminant Analysis (LDA)
Marginal Fisher Analysis (MFA)

Yang Variational Graph Embedding for Globally and Locally Consistent Feature Extraction p16
Yang Variational Graph Embedding for Globally and Locally Consistent Feature Extraction p16

Variational Graph Embedding
Mutual Information Embedding (MIE)
BER Embedding

You General Solution for Supervised Graph Embedding p8

[Yu2016] A Practical Algorithm for Embedding Graphs on Torus p18
Jiahua Yu

embedding extension

[Yu2014] A Practical Torus Embedding Algorithm and Its Implementation p84
Jiahua Yu

Yu Topology Mapping for Blue GeneL Supercomputer p13
hypercube embeddings
scalable three-dimensional grids/tori embeddings
grid-embedding
ring embedding
Fold Embeddings
Matrix-Based Embedding
Dilation-5 embedding
torus embedding

Yuan VIDEO ACTION RECOGNITION WITH SPATIO-TEMPORAL GRAPH EMBEDDING AND SPLINE MODELING p4

Yuan VIDEO ACTION RECOGNITION WITH SPATIO-TEMPORAL GRAPH EMBEDDING AND SPLINE MODELING p4


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Zeh IO-Optimal Planar Embedding Using Graph Separators

okokok
Zhang Robust Non-negative Graph Embedding: Towards Noisy Data, Unreliable Graphs, and Noisy Labels

Zhang Robust (Semi) Nonnegative Graph Embedding p17

Robust (Semi) Nonnegative Graph Embedding
nonnegative graph embedding (NGE)
robust seminonnegative graph embedding (RsNGE)

okokok

[Zhao2013] Graph Attribute Embedding via Riemannian Submersion Learning p32
Zhao Graph Attribute Embedding via Riemannian Submersion Learning p33

Graph Attribute Embedding

ISOMAP
locally linear embedding, which is a variant of PCA
Laplacian eigenmap / Laplacian matrix
Spectral methods

okokok
Zhao Graph embedding discriminant analysis for face recognition

Prof. Hao Zhu

[Zhou2000] Bounding the bandwidths for graphs p12
Sanming Zhou

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Zhou Learning with Hypergraphs Clustering Classification and Embedding
machine learning problem settings
spectral clustering
hypergraph embedding
transductive classification on the basis of the spectral hypergraph clustering approach
kernel matrix
spectral graph techniques
normalized cut approach
real-valued relaxation of the hypergraph normalized cut criterion
eigendecomposition of a positive semidefinite matrix
Laplacian for simple graphs
hypergraph Laplacian.
Hypergraph embedding and transductive inference based on the hypergraph Laplacian.
propagating label distributions on hypergraphs
hypergraph normalized cut
random walk
spectral hypergraph embedding technique based on the hypergraph Laplacian
transductive inference on hypergraphs

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Zhou Lipreading: A Graph Embedding Approach

distance metric
the graph embedding
dimensionality reduction
heat kernel
penalty graph
linear extension of the direct graph embedding
Laplacian matrices

[8] M. Belkin, and P. Niyogi, “Laplacian Eigenmaps and spectral techniques for embedding and clustering,” in Adv. Neural Inform. Proc. Syst. 14, 2001, pp. 585-591.

[Zhou, Ziheng2010]

Lipreading: A Graph Embedding Approach

Zhou Z, Zhao G & Pietik?inen M,?? Proc. 20th International Conference on Pattern Recognition (ICPR 2010), Istanbul, Turkey, pp523-526.

graph embedding framework [7]

[7] S. Yan et al., “Graph embedding and extensions: a general framework for dimensionality reduction,” TPAMI, 29(1), 40-51, 2007.

[8] M. Belkin, and P. Niyogi, “Laplacian Eigenmaps and spectral techniques for embedding and clustering,” in Adv. Neural Inform. Proc. Syst. 14, 2001, pp. 585-591.

Ziegler

Joachim Ziegler

http://www.leda-tutorial.org/en/discussion/ch05s02s06.html

5.2.6. Planarly embedded graphs, maps, and faces

P. Zienicke, Embeddings of treelike graphs into 2-dimensional meshes, in: Proc.
16th InternationalWorkshop on Graph-Theoretic Concepts in Computer Science,
volume 484 of Lecture Notes in Computer Science, Springer, 1991, pp. 182–192.

2016-5-7
Matthias Zwicker
http://cgg.unibe.ch/staff/matthias-zwicker
Prof. Dr. Matthias Zwicker
Matthias Zwicker
Position: ????? Head of Research Group
Office: 213
Phone: +41 31 631 3301
zwicker@iam.unibe.ch

Zou Answering Pattern Match Queries in Large Graph Databases Via Graph Embedding p25
Answering Pattern Match Queries in Large Graph Databases Via Graph Embedding p25
2009
[Zou, Lei et al2012]

The VLDB Journal, February 2012, Volume 21, Issue 1, pp 97-120.
http://www.icst.pku.edu.cn/intro/leizou/cn/papers/distancejoinVLDBJ-final2012.pdf
Lei Zou · Lei Chen · M. Tamer ¨Ozsu · Dongyan Zhao

Zou Graph Embedding and Extensions A General Framework for Dimensionality Reduction p21


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?

Embedding Algorithms
?
?
?
?
?
?
?
?
?
?

drop-down embedding scheme
?

[Klymko2014]

drop-down embedding scheme

?

Fallback embedding algorithm

[Klymko2014]

Fallback embedding algorithm
?
?
?
?

fault-tolerant embedding algorithms

[Klymko2014]

fault-tolerant embedding algorithms
?
?
?
?
?
?

Embedding Algorithms

?

drop-down embedding scheme

?

[Klymko2014]

drop-down embedding scheme

?

Fallback embedding algorithm

[Klymko2014]

Fallback embedding algorithm

fault-tolerant embedding algorithms

[Klymko2014]

fault-tolerant embedding algorithms


def

Graph Embedding - Algorithms and Methods

Dijkstra’s algorithm to perform graph embedding.
[Zou, Lei et al2012]
isomap
least-squares multi-dimensional scaling (LSMDS)
Multi-Dimensional Scaling (MDS)

?

Graph Embedding - Algorithms and Methods

?

Curvilinear Component Analysis (CCA)

Curvilinear Distance Analysis (CDA)

?

dimensionality reduction

?

Dijkstra’s algorithm to perform graph embedding

[Zou, Lei et al2012]

?divide and conquer approaches

?

Eades algorithms

eigen-decomposition

eigenvalues of the adjacency matrix or Laplacian matrix
eigenvectors of the adjacency matrix or Laplacian matrix.
leading eigenvectors of the adjacency matrix
eigenspaces of adjacency matrices
eigenmode

Ellipsoid method

FR algorithms

Gaussian form

Gaussian function of the geodesic distance between nodes

geodesic distance

geodesic distance between nodes

GEM algorithms

geodesic distance (lowest sum of edge weights)

?Graph kernels

Graph kernels
Graph kernels are an implicit way of defining a graph embedding
Graph kernels are an implicit way of defining a graph embedding

graph kernels

  1. diffusion kernels
  2. dissimilarity-based kernels
  3. convolution kernels
  4. substructure finding kernels

heat kernel

?independent component analysis

?

isomap

?
isomap

?

KDA is the kernel extension of LDA

kernel trick

KK algorithm

graph-Eudidean and graphtheoretic distances between pairs of vertices, referred to as the KK algorithm

Graphlet version of KK

Laplacian eigenmaps

spectral decomposition of the graph Laplacian

Laplacian

graph Laplacian
normalised Laplacian
Laplacian eigenmap
Laplacian matrix
Laplacian eigensystem
eigensystem
principal eigenvectors
spectral decomposition
spectral decomposition on the graph Laplacian

Linear Discriminant Analysis (LDA)

Linear Discriminant Analysis (LDA)

?

3.4 Linear Extensions of Graph Embedding ................................................................. 38

[Azary2014]

Linear Extensions of Graph Embedding (LGE) methods are eigen-based linearized techniques to solve linear approximations of non-linear systems through dimensionality reduction. They include linear discriminant analysis (LDA) [70], locality preserving projections (LPP) [71], and neighborhood preserving embedding (NPE) [72].

LLP

LPP Locality Preserving Projections (LPP)

preserves local relationships in the data set, and uncovers its essential manifold structure

?

Locality Sensitive Discriminant Analysis (LSDA)

?

machine learning

?
dimensionality reduction approaches from machine learning

Nonlinear manifold learning algorithms
unsupervised machine learning

?unsupervised machine learning
Nonlinear manifold learning algorithms
dimensionality reduction approaches from machine learning

Marginal Fisher Analysis (MFA)

Kernel MFA, and Tensor MFA

Maximum Variance Unfolding (MVU)

Maximum Variance Unfolding (MVU)

?

Multi-Dimensional Scaling (MDS)

?

anchored MDS

Centrality-constrained MDS

constrained multi-dimensional scaling (MDS)

?least-squares multi-dimensional scaling (LSMDS)

?least-squares multi-dimensional scaling

nearest neighbor algorithm

nearest neighbor algorithm

Principal component analysis (PCA)

KPCA

Sammon's Mapping (SM)

Self-Organizing Map (SOM)

Visualization Induced Self-Organizing Map (ViSOM)

semidefinite program

?
semidefinite program

SparseMap

?

Tensor based algorithms

2DLDA
2DLDA is the second-order tensorization of LDA

2DPCA

DATER
DATER is the tensorization of LDA in arbitrary order

?

?Topographic Mapping (GTM)

Generative Topographic Mapping (GTM)

?Visual analytics based approaches

?

Graph Embedding - its Relations with other Graph Theoretic Topics

graph database

[Zou, Lei et al2012]

supergraph
[Zou, Lei et al2012]

?

Graph Embedding - its Relations with other Graph Theoretic Topics

Graph

heat kernel of the graph
The heat kernel of the graph is found by exponentiating the resulting eigensystem over time.
spectral heat kernel
spectral heat kernel and its Gaussian form
heat-equation

connectivity graph

community browsing in graphs
graph adjacency matrix
adjacency matrices
Laplacian matrices

nearest neighbor graph
topology of the graph
edit distance between graphs
path length distribution on the graph
negative squared-distance between nodes.
simplicial complex of the graph
sets of shock graphs

graph-spectra
graph genus
local connectivity

class prototype

centrality - network centrality
Degree centrality
Closeness centrality
Betweenness centrality
Markov centrality

node dissimilarity
Shared neighbors
Graph-theoretic distances

node hierarchy

closeness

betweenness

trees

direct spectral analysis of trees
shock trees
co-spectrality of the trees

?

graph clustering

?pairwise clustering methods
pairwise clustering methods to the edit distance between graphs
Central clustering

?

?graph conductance

?

graph database

[Zou, Lei et al2012]

Graph Edit Distance

Graphs encoding

graph expansion

graph impostors

graph isomorphism

subgraph isomorphism

A subgraph isomorphism indicates whether a graph is contained as a subgraph of a larger graph.

Graph Matching

Error-tolerant Graph Matching

inexact graph matching

Graph Matching
Error-tolerant Graph Matching
inexact graph matching

graph matching
exact graph matching
error-tolerant graph matching
Boolean graph matching

Graph Partitioning

graph repository

Graph retrieval

graph separators

graph smoothness

meshes

planar meshes

minors

?

Riemannian manifolds

subgraph spotting

supergraph

[Zou, Lei et al2012]

Other Technologies

Expander Flows

expander flow.
edge expansion

manifold

Riemannian Manifolds
global geometry of the manifold
manifold learning theory
geodesic distance between nodes on a manifold

Markov chains

matrix

Laplacian matrix
Laplacian matrix L = D – A
normalised Laplacian is given by ?L = D?12LD?12

eigenvalues of the Laplacian matrix
spectral decomposition of the normalised Laplacian matrix

adjacency matrix
adjacency matrix A for the graph where
A(u, v) =1 if(u, v) ∈ E0 otherwise

adjacency weight matrix
dissimilarity matrix
covariance matrix
weighted proximity matrix
diagonal degree matrix
D, whose elements are given by
D(u, u) =v∈V A(u, v)

matrix of geodesic distances

multicommodity flows

space

pattern space
Riemannian space
neighborhood hypersphere in the embedding space

topology aware mapping

spectral clustering

Vector

graph feature vectors
Fiedler-vector
pattern vectors
embedded vector of co-ordinates
principal eigenvectors

Voronoi diagrams

?


def

Applications & Usefulness
[Baingana2013b]

In addition to network visualization, graph embedding algorithms compress network data and provide a way to geometrically solve some computationally hard problems.
[LUQMAN2012]

Graph embedding is a natural outcome of parallel advancements in structural and
statistical pattern recognition. It o?ers a straightforward solution, by employing the
representational power of symbolic data structures and the computational superiority of
feature vectors [Bunke et al., 2005]. It acts as a bridge between structural and statistical
approaches [Bunke et al., 2001, Roth et al., 2003], and allows a pattern recognition
method to benefit from computational efficiency of state-of-the-art statistical models and
tools [Chen et al., 2007] along-with the convenience and representational power of classical
symbolic representations. This permits the last three decades of research on graph
based structural representations in various domains [Conte et al., 2004], to benefit from
the state-of-the-art machine learning models and tools. Graph embedding has its application
to the whole variety of domains which are entertained by pattern recognition
and where the use of a relational data structure is mandatory for performing high level
tasks. Apart from reusing the computational efficient methods for vector spaces, another
important motivation behind graph embedding methods is to solve the computationally
hard problems geometrically [Shaw and Jebara, 2009]. The pattern recognition
research community acknowledges the emerging importance of graph embedding methods
[Foggia and Vento, 2010] for realizing the classical idea of using the structural and statistical
methods together. We refer the interested reader to [Lee and Madabhushi, 2010] for
further reading on the applications of graph embedding.

Graph embedding is an interesting solution for addressing the computational limitations
of structural pattern recognition and in particular for addressing the problem of
graph isomorphism which belongs to the class of NP-complete problems.
[Zhao2013]
relational matching

object categorisation

shape classification-Shape Categorisation and Matching


def

Graph Embedding for VLSI Design

graph embedding for VLSI design

XXXXXXXXXX
https://dl.acm.org/citation.cfm?id=37142

okokok
https://www.amazon.com/Mathematical-Layout-Embedding-Micheal-Arockiaraj/dp/3659366617

okokok
https://archive.org/details/VLSI_Physical_Design_From_Graph_Partitioning

_to_Timing_Closure

okokok
http://www.eng.auburn.edu/~baskiyar/

okokok
ftp://ftp.cs.brown.edu/pub/techreports/93/cs93-01.ps.Z

okokok
https://www.cse.cuhk.edu.hk/v7/en/ce/coursedsc.html

okokok
http://www.design-reuse.com/articles/18275/

application-models-bandwidth-aware-core-graphs.html

okokok
http://www.ijnc.org/index.php/ijnc/article/view/122

okokok
https://mathoverflow.net/questions/228248/

building-an-orthogonal-embedding-for-a-4-planar-graph

okokok
https://www.ncbi.nlm.nih.gov/pmc/articles/PMC2858671/

okokok
https://www.omicsgroup.org/
http://research.omicsgroup.org/index.php/Topological_graph_theory

okokok
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.112.8322

okokok
https://www.researchgate.net/publication/

242601680_Embedding_Graphs_in_Books_A_Layout_Problem

_with_Applications_to_VLSI_Design

okokok
http://robertdick.org/publications/

okokok
http://www.sciencedirect.com/science/article/pii/S0012365X97001313

okokok
http://www.scientific.net/AMM.345.355

okokok
http://epubs.siam.org/doi/abs/10.1137/0608002?journalCode=sjamdu

okokok
http://engineering.siu.edu/elec/faculty-staff/faculty/kagaris.php

okokok
https://sydney.edu.au/research/opportunities/opportunities/1033

XXXXXXXXX
http://www.tandfonline.com/doi/abs/

10.1080/00207168808803629?journalCode=gcom20

okokok
http://www3.math.tu-berlin.de/coga/research/vlsi/

XXXXXXXXXXXXXX
http://www.iss.tu-darmstadt.de/staff/klaus/publications/fdl02.pdf

okokok
http://sce.uhcl.edu/bettayeb/publication.html

okokok
ftp://ftp.informatik.uni-freiburg.de/documents/reports/report202/report00202.ps.gz

XXXXXXXXXXX
https://www8.cs.umu.se/kurser/TDBA77/VT06/algorithms/

BOOK/BOOK3/NODE132.HTM

XXXXXXXXXXXX
http://web.uvic.ca/calendar2016-05/grad/programs/csc/index.html

okokok
http://www.cems.uvm.edu/TopologicalGraphTheoryProblems/pagenum.htm

okokok
http://www.worldscientific.com/worldscibooks/10.1142/6143

XXXXXXXXXXXX
[Ahn, Minwook 2006] Ahn A Spatial Mapping Algorithm for Heterogeneous Coarse- Grained Reconfigurable Architectures p6

okokok
[Alexander1994] Alexander An architecture independent approach to FPGA

routing based on multiweighted graphs p6
1994

okokok

Archdeacon Graphs on Grids area and volume tradeoffs in circuit layouts p40

[Banerjee2009] Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198

grid embedding

p27
Gopalakrishnan et al. in their work on Convex Assigned Placement for Regular ICs (CAPRI) [Gopalakrishnan 2006], have proposed an architecture aware analytical placement using graph embedding and metric geometry [Matousek 2002] that models the relationship between performance and the routing grid. The placement problem is modeled as an embedding of a graph representing the netlist into a metric space that is representative of the FPGA architecture. An analytic metric of distance that models delays along the FPGA routing grid has been developed. They use a metric space that accurately captures the delays on the FPGA chip, rather than the Manhattan space. Then the netlist is embedded into the defined metric space using matrix projections [Golub 1983] which produces an illegal placement with overlapping CLBs. The placement is legalized using a online bipartite matching [Gopalakrishnan 2006] formulation. Finally, a low-temperature simulated annealing step is performed to improve the solution further.

P86
On the theoretical front, the FPGA placement problem can be modeled as a graph embedding problem on a two dimensional grid that minimizes a cost resembling the wirelength [Even 2000, Vempala 1998]. The model is formally defined in Section 5.3. The best known approximation ratios for the graph embedding problem are polylogarithmic [Even 2000, Feige 2007, Rao 1998].

P87

Moreover, the theory developed thus far is tuned for VLSI place ment modeled as graph embedding.

Section 5.3 defines the FPGA placement problem as a graph embedding problem.

We first extend the existing graph embedding approximation algorithms [Feige 2007, Even 2000] to hypergraphs in order to prove an O(d ? log n log log n) bound for 1D (i.e., linear arrangement), and an O(d log n log log n) bound for the 2D case.

P88
These works mainly formulate the VLSI layout problem as embedding a graph in a d-dimensional grid.

P89

For d = 1, the graph embedding problem is basically the graph optimal linear arrangement (GOLA)
problem, which is known to be NP-hard [Garey 1979]. Most of these works deal with laying out a graph on a grid optimizing a cost, which in a way resembles an estimate of the total wirelength. But, a more accurate model of a circuit represented as netlists of CLBs, is a hypergraph.

Problem 5.2 (Graph Placement on Grid (GPG):) Given an undirected graph G = (V,E), the problem is to find an embedding of G in a two dimensional grid, or equivalently, a one-to-one mapping, h of G to a subgraph containing |V | vertices of the two dimensional grid, such that the cost function ? (i;j)?E d(h(i), h(j)) is minimized. Here d(x, y) is the number of grid edges in the shortest path between x and y along the grid.

Problem 5.4 (Hypergraph Placement on Grid (HPG):) Given a hypergraph H = (V, S), the problem is to find an embedding of H in a two dimensional grid, or equivalently, a one-to-one mapping, h of H to a subgraph containing |V | vertices of the two dimensional grid, such that the cost function
HPWL = ?k i=1 (bbx(i) + bby(i))
is minimized. Here, bbx(i) is the x span of net i, bby(i) is the y span of net i, and bbx(i) + bby(i) is termed as the half-perimeter bounding box of net i.

p91
Theory: Graph embedding problem

p95

Lemma 5.3 [Sagan 1994, Even 2000] In a 2D embedding using space filling curve, each net spanning a length ri in the linear arrangement has a perimeter bounded by C' ·?ri where C' is a positive constant.

Next, we derive the approximation ratio of our algorithm for the grid embedding of hypergraph.

p105

First we extended the theoretical results for graph optimal linear arrangement (GOLA) and graph embedding on grid (GPG) to optimal linear arrangement (HOLA) and embedding (HPG) for hypergraphs respectively.

[BANERJEE2008] FPGA Placement using Space Filling Curves Theory Meets Practice p21

VLSI placement modeled as graph embedding

embedding a graph in a d-dimensional mesh.

grid embedding

3

[BANERJEE2008]
BANERJEE FPGA Placement using Space Filling Curves Theory Meets Practice p21

VLSI placement modeled as graph embedding

embedding a graph in a d-dimensional mesh.

3

[Banerjee2009] Fast Placement and Floorplanning Methods in Modern Reconfigurable FPGAs okokok p198

Bokal Minor-monotone crossing number p6
Drago Bokal1, Ga^sper Fijav^z2? and Bojan Mohar3?

Britt Embedding Logical Qubits into the D-Wave Hardware Graph
okokok
Britt Embedding Logical Qubits into the D-Wave Hardware Graph.pptx
[Britt2014] Embedding Logical Qubits into the D-Wave Hardware Graph

Britt Embedding Logical Qubits into the D-Wave Hardware Graph p30.pdf
Britt Embedding Logical Qubits into the D-Wave Hardware Graph p30

Keith Britt

keithbritt@utk.edu

February 26th, 2014

=========================================

Embedding

okokok

Chen FPGA Design Automation: A Survey p137

2.2.3 Embedding-based approach
In this section, we briefly introduce one recent FPGA placement algorithm based on graph embedding and metric geometry, named convex assigned placement for regular ICs (CAPRI) [96].
CAPRI views the placement task as an embedding of a graph representing the netlist into a chosen metric space.
CAPRI then embeds the netlist graph into this metric space based on the binary quadratic assignment formulation (which is NP-hard), and solved the problem with a heuristic technique based on matrix projections followed by online bipartite graph matching.

4.3 Placement-Driven Duplication
The algorithm then embeds the replication tree by adapting the dynamic programming procedure for S-tree embedding [102] to consider both timing and wirelength. Placement legalization is invoked
after embedding.

P. Gopalakrishnan, X. Li, and L. Pileggi. Architecture-aware FPGA placement using metric embedding. In IEEE/ACM Design Automation Conference, pages 460–465, 2006.

???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????

ZZZZZZZZZZ

[Chen2006] FPGA Design Automation: A Survey p151

Deming Chen, Jason Cong, and Peichan Pan

S-tree embedding

2.2.3 Embedding-based approach

In this section, we briefly introduce one recent FPGA placement algorithm based on graph embedding and metric geometry, named convex assigned placement for regular ICs (CAPRI) [95].

P. Gopalakrishnan, X. Li, and L. Pileggi. Architecture-aware FPGA placement using metric embedding. In IEEE/ACM Design Automation Conference, pages 460–465, 2006.

CAPRI views the placement task as an embedding of a graph representing the netlist into a chosen metric space. It first defines an analytic metric of “distance” in terms of the total delay through switches on the FPGA routing architecture, and then uses it to construct a metric space that captures FPGA performance. CAPRI then embeds the netlist graph into this metric space based on the binary quadratic assignment formulation (which is NP-hard), and solved the problem with a heuristic technique based on matrix projections followed by online bipartite graph matching. The resulting solution is a legal initial placement, which tries to minimize delays on driver–sink connections and is thus “good” from a global timing perspective. Subsequently, CAPRI applies local optimization using an existing low-temperature simulated-annealing in VPR for local optimization to improve specific critical paths and routability.

4.3 Placement-Driven Duplication

The algorithm then embeds the replication tree by adapting the dynamic programming procedure for S-tree embedding [101] to consider both timing and wirelength. Placement legalization is invoked after embedding. The legalization procedure is the same as the previous algorithm except for the fact that both timing and wirelength are considered. A delay reduction of over 14% was observed on a set of benchmark designs, about twice the improvement from the approach based on local monotonicity removal.

Chen Integrated Circuit White Space Redistribution for Temperature Optimization p6

[Choi 2010] Graph Embedding implemented on DW-1 via Chimera graph retains NP-hardness

[Choi2008] Minor-Embedding in Adiabatic Quantum Computation I The Parameter Setting Problem p17

Choi, Vicky. Minor-Embedding in Adiabatic Quantum Computation: I. The Parameter Setting Problem. Quantum Information Processing, 7, pp 193 – 209, 2008. arXiv:0804.4884v1 [quant-ph].

Choi, Vicky.? Minor-Embedding in Adiabatic Quantum Computation: I. The Parameter Setting Problem. Quantum Information Processing, 7, pp 193 – 209, 2008. arXiv:0804.4884v1 [quant-ph].
Choi, Vicky. Minor-Embedding in Adiabatic Quantum Computation: I. The Parameter Setting Problem. Quantum Information Processing, 7, pp 193 – 209, 2008. arXiv:0804.4884v1 [quant-ph].

Minor-Embedding

topological-minor embedding

subgraph-embedding

NP-hard

quadratic unconstrained binary optimization (QUBO) problem on a graph

adiabatic quantum computer

Ising spin-1/2 Hamiltonian

reduction through minor-embedding of G in the quantum hardware graph U

The embedding problem is to find a minor-embedding Gemb of a graph G in U, which is a subgraph of U such that G can be obtained from Gemb by contracting edges.

The parameter setting problem is to determine the corresponding parameters, qubit biases and coupler strengths, of the embedded Ising Hamiltonian.

In this paper, we focus on the parameter setting problem.

The notion of embedding here follows naturally from physicists’ intuition that each logical qubit (corresponding to a vertex in the input graph) is mapped to a subtree of physical qubits (corresponding to vertices in the hardware graph) that are ferromagnetically coupled such that each subtree of physical qubits acts like a single logical qubit.

Informally, a minor embedding Gemb of a graph G in the hardware graph U is a subgraph of U such that Gemb is an “expansion” of G by replacing each vertex of G with a (connected) subtree of U, or equivalently, G can be obtained from Gemb by contracting edges (same color in Figure 2). In graph theory, G is called a (graph) minor of U (see for
example [12]). The minor-embedding will be formally defined in Section 3. (Remark: The embedding in [17, 18] is a special case of minor-embedding, known as topological-minor embedding.)

By reduction through minor-embedding, we mean that one can reduce the original Ising Hamiltonian on the input graph G to the embedded Ising Hamiltonian Hemb on its minor-embedding Gemb, i.e., the solution to the embedded Ising Hamiltonian gives rise to the solution to the original Ising Hamiltonian.

The embedding problem is to find a minor-embedding Gemb of a graph G in U.

Definition 3.1. Let U be a fixed hardware graph. Given G, the minor-embedding of G is defined by
? : G -? U
such that

each vertex in V(G) is mapped to a connected subtree Ti of U;

there exists a map ? : V(G) × V(G) -? V(U) such that for each ij ? E(G), there are corresponding i(i,j) ? V(Ti) and j(j,i) ? V(Tj) with i(i,j)j(j,i) ? E(U).

Given G, if ? exists, we say that G is embeddable in U. In graph theory, G is called a minor of U. When ? is clear from the context, we denote the minor-embedding ?(G) of G by Gemb.

Equivalently, one can think of a minor G of U as a graph that can be obtained from a subgraph of U by contracting edges. See Figure 2 for an example.

In particular, there are two special cases of minor-embedding:

Subgraph-embedding: Each Ti consists of a single vertex in U. That is, G is isomorphic to Gemb (a subgraph of U).

Topological-minor-embedding: Each Ti is a chain (or path) of vertices in U.

References
[1] D. Aharonov, W. van Dam, J. Kempe, Z. Landau, S. Lloyd, and O. Regev. Adiabatic quantum computation is equaivalent to standard quantum computation. Proc. 45th FOCS, pages 42–51, 2004.
[2] M. H. S. Amin and V. Choi. Work in progress. 2008.
[3] M. H. S. Amin, P. J. Love, and C. J. S. Truncik. Thermally assisted adiabatic quantum computation. Physical
Review Letters, 100:060503, 2008.
[4] M. H. S. Amin, C. J. S. Truncik, and D. V. Averin. The role of single qubit decoherence time in adiabatic
quantum computation. arXiv.org:0803.1196.
[5] B. S. Baker. Approximation algorithms for NP-complete problems on planar graphs. J. ACM, 41(1):153– 180, 1994.
[6] N. Bansal, S. Bravyi, and B. M. Terhal. A classical approximation scheme for the ground-state energy of Ising spin hamiltonians on planar graphs. quant-ph/0705.1115.
[7] F. Barahona. On the computational complexity of Ising spin glass models. J. Phys. A: Math. Gen., pages 15: 3241–3253, 1982.
[8] E. Boros and P. Hammer. Pseudo-boolean optimization. Discrete Appl. Math., (123):155–225, 2002.
[9] E. Boros, P. L. Hammer, and G. Tavares. Preprocessing of quadratic unconstrained binary optimization. Technical Report RRR 10-2006, RUTCOR Research Report., 2006.
[10] S. Bravyi, D. P. DiVincenzo, D. Loss, and B. M. Terhal. Simulation of many-body hamiltonians using
perturbation theory with bounded-strength interactions. arXiv.org:0803.2686.
[11] A. Childs, E. Farhi, and J. Preskill. Robustness of adiabatic quantum computation. Physical Review A, 65, 2002.
[12] R. Diestel. Graph Theory. Springer-Verlag, Heidelberg, 2005.
[13] L. F. Thomson. Introduction to parallel algorithms and architectures: arrays, trees, hypercubes. 1992.
[14] E. Farhi, J. Goldstone, S. Gutmann, J. Lapan, A. Lundgren, and D. Preda. A quantum adiabatic evolution
algorithm applied to random instances of an np-complete problem. Science, 292(5516):472–476, 2001.
[15] E. Farhi, J. Goldstone, S. Gutmann, and M. Sipser. Quantum computation by adiabatic evolution. quantph/ 0001106, 2000.
[16] L. M. Ioannou and M. Mosca. Limitations of some simple adiabatic quantum algorithms. quantph/ 0702241, 2007.
[17] W. M. Kaminsky and S. Lloyd. Scalable architecture for adiabatic quantum computing of NP-hard problems.
In A. J. Leggett, B. Ruggiero, and P. Silvestrini, editors, Quantum Computing and Quantum Bits in Mesoscopic Systems, 2004.
[18] W. M. Kaminsky, S. Lloyd, and T. P. Orlando. Scalable superconducting architecture for adiabatic quantum
computation. arXiv.org:quant-ph/0403090, 2004.
[19] J. Kempe, A. Kitaev, and O. Regev. The complexity of the local hamiltonian problem. SIAM JOURNAL
OF COMPUTING, 35:1070, 2006.
[20] J. M. Kleinberg and R. Rubinfeld. Short paths in expander graphs. In IEEE Symposium on Foundations of
Computer Science, pages 86–95, 1996.
[21] R. Oliveira and B.M. Terhal. The complexity of quantum spin systems on a two-dimensional square lattice.
quant-ph/0504050.
[22] B. W. Reichardt. The quantum adiabatic optimization algorithm and local minima. In STOC ’04: Proceedings
of the thirty-sixth annual ACM symposium on Theory of computing, pages 502–510, New York, NY, USA, 2004. ACM.
[23] N. Robertson and P. D. Seymour. Graph minors. xiii: the disjoint paths problem. J. Comb. Theory Ser. B, 63(1):65–110, 1995.
[24] W. van Dam, M. Mosca, and U. Vazirani. How powerful is adiabatic quantum computation? Proc. 42nd FOCS, pages 279–287, 2001.
[25] W. van Dam and U. Vazirani. Limits on quantum adiabatic optimization. Unpublished, 2001.

4

[Choi2011] Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design p10

Choi, Vicky. Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design. Quantum Information Processing: Volume 10, Issue 3 (2011), Page 343. arXiv:1001.3116v2 [quant-ph].
Choi, Vicky.? Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design. Quantum Information Processing: Volume 10, Issue 3 (2011), Page 343. arXiv:1001.3116v2 [quant-ph].
Choi, Vicky. Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design. Quantum Information Processing: Volume 10, Issue 3 (2011), Page 343. arXiv:1001.3116v2 [quant-ph].

The strength of the ferromagnetic couplings grows with the degree of the embedded graph (Choi 2008)
In principle, an N-complete graph can be embedded in the geometry implemented by Dwave using N2 vertices (Choi 2010)
Choi Minor-embedding in adiabatic quantum computation II Minor-universal graph design p10

[Choi2009] Minor-embedding in adiabatic quantum computation p47

topological-minor-embedding

minor-embedding in adiabatic quantum optimization

A minor-embedding of a graph G in a quantum hardware graph U is a subgraph of U such that G can be obtained from it by contracting edges.

optimal complete-graph-minor hardware graph

Given a family F of graphs, a (host) graph U is called F-minor-universal if for each graph G in F, U contains a minor-embedding of G.

The problem for designing a F-minor-universal hardware graph Usparse in which F consists of a family of sparse graphs (e.g., bounded degree graphs) is open.

Minor-Embedding in AQC

References
1. D. Aharonov, W. van Dam, J. Kempe, Z. Landau, S. Lloyd, and O. Regev. Adiabatic quantum computation is equivalent to standard quantum computation. Proc. 45th FOCS, 42–51, 2004.
2. N. Alon and M. Capalbo. Optimal universal graphs with deterministic embedding. Proc. 19th SODA, 2008.
3. H.L. Bodlaender. A partial k-arboretum of graphs with bounded treewidth. Theoretical Computer Science, 209, 1–45, 1998.
4. E. Boros and P. Hammer. Pseudo-boolean optimization. Discrete Appl. Math., (123):155– 225, 2002.
5. E. Boros, P. L. Hammer, and G. Tavares. Preprocessing of quadratic unconstrained binary optimization. Technical Report RRR 10-2006, RUTCOR Research Report., 2006.
6. V. Choi. Minor-embedding in adiabatic quantum computation: I. The parameter setting problem. Quantum Inf. Processing., 7, 193–209, 2008. Available at arXiv:quantph/ 0804.4884.
7. V. Choi. Systems, Devices and Methods For Analog Processing, US Patent Application US2009/0121215, May 14, 2009.
8. R. Diestel. Graph Theory. Springer-Verlag, Heidelberg, 2005.
9. D-Wave Systems Inc. 100-4401 Still Creek Dr., Burnaby, V5C 6G9, BC, Canada. http://www.dwavesys.com/
10. E. Farhi, J. Goldstone, S. Gutmann, and M. Sipser. Quantum computation by adiabatic evolution. arXiv:quant-ph/0001106, 2000.
11. E. Farhi, J. Goldstone, S. Gutmann, J. Lapan, A. Lundgren, and D. Preda. A quantum adiabatic evolution algorithm applied to random instances of an NP-complete problem. Science, 292(5516), 472–476, 2001.
12. R. Harris and J. Johansson and A. J. Berkley and M. W. Johnson and T. Lanting and S. Han et al.. Experimental Demonstration of a Robust and Scalable Flux Qubit. arXiv:quantph/ 0909.4321, 2009.
13. W.M. Kaminsky and S. Lloyd. Scalable architecture for adiabatic quantum computing of NP-hard problems. Quantum Computing and Quantum Bits in Mesoscopic Systems, 2004.
14. W.M. Kaminsky, S. Lloyd, and T.P. Orlando. Scalable superconducting architecture for adiabatic quantum computation. arXiv.org:quant-ph/0403090, 2004.
15. J.M. Kleinberg and R. Rubinfeld. Short paths in expander graphs. Proc. 37th FOCS, 1996. 16. I.L. Markov and Y. Shi. Simulating quantum computation by contracting tensor networks SIAM Journal on Computing, 38, 2008.
17. N. Robertson and P.D. Seymour. Graph minors. xiii: the disjoint paths problem. J. Comb. Theory Ser. B, 63(1), 65–110, 1995.
18. G. Rose, P. Bunyk, M.D. Coury, W. Macready, V. Choi. Systems, Devices, and Methods For Interconnected Processor Topology, US Patent Application US2008/0176750, July 24, 2008.
19. L.F. Thomson. Introduction to parallel algorithms and architectures: arrays, trees, hypercubes. Morgan Kaufmann, San Mateo, California, 1992.

CHUNG EMBEDDING GRAPHS IN BOOKS: A LAYOUT PROBLEM WITH APPLICATIONS TO VLSI DESIGN p26

[CHUNG1987] EMBEDDING GRAPHS IN BOOKS: A LAYOUT PROBLEM WITH APPLICATIONS TO VLSI DESIGN p26

book embeddings

12

[Dahl2013] Programming with D-Wave: Map Coloring Problem p12

E. D. Dahl, D-Wave Systems
November 2013

CONTACT
Corporate Headquarters
3033 Beta Avenue
Burnaby, British Columbia V5G 4M9
Canada
Tel. 604-630-1428
US Office
2650 E. Bay Shore Road
Palo Alto, CA
Email: info@dwavesys.com
www.dwavesys.com

6

D-Wave system

D-Wave quantum computer

logical qubits and couplers

physical qubits and couplers

quantum machine instruction (QMI)

map coloring problem

logical to physical mapping

unary encoding

direct embedding

unit cell embedding

Each logical qubit corresponds (via an embedding) to one or more connected physical qubits, which we call a chain. To implement a coupler between logical qubits, it is enough to find a physical coupler connecting some physical qubit in the chain for the first logical qubit to another physical qubit in the chain for the second logical qubit.

De Micheli Synthesis And Optimization Of Digital Circuits p586
De Micheli Synthesis And Optimization Of Digital Circuits p586

embedding

p358

CHAPTER 8 Multiple-Level Combinational Logic Optimization

8.4 THE BOOLEAN MODEL

8.4.1 Don't care Conditions and Their Computation
Generally speaking, don't care conditions are related to the embedding of a Boolean funtion in an environment.

9.1 INTRODUCTION

9.2 SEQUENTIAL CIRCUIT OPTIMIZATION USING STATE-BASED MODELS

9.2.1 State Minimization

p431

CHAPTER 9 SEQUENTIAL LOGIC OPTIMIZATION

9.2 SEQUENTIAL CIRCUIT OPTIMIZATION USING STATE-BASED MODELS

9.2.2 State Encoding

The state encoding (or assignment) problem consists of determining the binary representation of the states of a finite-state machine

The encoding problem is modeled by a complete edge-weighted graph, where the vertices are in one-to-one correspondence with the states. The weights denote the desired code proximity of state pairs and are determined by scanning systematically all state pairs.

State encoding is determined by embedding this graph in a Boolean space of appropriate dimensions. Since graph embedding is an intractable problem, heuristic algorithms are used to determine an encoding where pairwise code distance correlates reasonably well with the weight (the higher the weight, the lower the distance).

p460

CHAPTER 9 SEQUENTIAL LOGIC OPTIMIZATION

9.3 SEQUENTIAL CIRCUIT OPTLMIZATION USING NETWORK MODELS

9.3.3 Don't Care Conditions in Synchronous Networks

EXPLICIT DON'T CARE CONDITIONS IN SYNCHRONOUS NETWORKS. External don't care conditions of synchronous logic networks are related to the embedding of the network in the environment, as in the combinational case.

p467

CHAPTER 9 SEQUENTIAL LOGIC OPTIMIZATION

9.3 SEQUENTIAL CIRCUIT OPTLMIZATION USING NETWORK MODELS

9.3.3 Don't Care Conditions in Synchronous Networks

The first step is equating the terminal behavior of the original network and of the network embedding the local replacement.

Deotare Optimization of Latency of Temporal Key Integrity Protocol (TKIP) Using Graph Theory and Hardware Software Co-Design p8

EMMS GRAPH EMBEDDING USING A QUASI-QUANTUM ANALOGUE OF THE HITTING TIMES OF CONTINUOUS TIME QUANTUM WALKS p24
EMMS GRAPH EMBEDDING USING A QUASI-QUANTUM ANALOGUE OF THE HITTING TIMES OF CONTINUOUS TIME QUANTUM WALKS p24

[EMMS2007] GRAPH EMBEDDING USING A QUASI-QUANTUM ANALOGUE OF THE HITTING TIMES OF CONTINUOUS TIME QUANTUM WALKS p24

D. Emms, R. Wilson, and E. Hancock. Graph embedding using quantum commute times. Graph-Based Representations in Pattern Recognition, pages 371– 382, 2007. 1

D. Emms, R. Wilson, and E. Hancock.

Graph embedding using quantum commute times.
D. Emms, R. Wilson, and E. Hancock. Graph embedding using quantum commute times. Graph-Based Representations in Pattern Recognition, pages 371– 382, 2007.

D. Emms, R. Wilson, and E. Hancock. Graph embedding using quantum commute times. Graph-Based Representations in Pattern Recognition, pages 371– 382, 2007. 1

Graph-Based Representations in Pattern Recognition, pages 371– 382, 2007.

Quantum Hitting Time Embeddings of Random Graphs

MDS embedding

2D embedding

two dimensional quantum embedding

References
1. D. Aharonov, A. Ambainis, J. Kempe, and U. Vazirani. Quantum walks on graphs. In STOC '01:
Proc ACM Theory of computing, pages 50{59. ACM Press, 2001.
2. A. Ambainis, E. Bach, A. Nayak, A. Vishwanath, and J. Watrous. One-dimensional quantum
walks. In Proc. 33th STOC, pages 60{69, New York, NY, 2001. ACM.
3. K. Borgwardt, S. Schnauer, S. Vishwanathan, A. Smola, and H. Kriegel. Protein function predic-
tion via graph kernels. Bioinformatics, 21, June 2005.
4. S. Brin and L. Page. The anatomy of a large-scale hypertextual Web search engine. Computer
Networks and ISDN Systems, 30(1{7):107{117, 1998.
5. A. Childs, E. Farhi, and S. Gutmann. An example of the di?erence between quantum and classical
random walks. Quantum Information Processing, 1:35, 2002.
6. A. M. Childs, R. Cleve, E. Deotto, E. Farhi, S. Gutmann, and D. A. Spielman. Exponential
algorithmic speedup by a quantum walk. In STOC '03: Proc. 35th ACM symposium on TOC,
pages 59{68, New York, NY, USA, 2003. ACM Press.
7. F. Chung and S.-T. Yau. Discrete green's functions. J. Comb. Theory Ser. A, 91(1-2):191{214,
2000.
8. F. DePiero and J. Carlin. Structural matching via optimal basis graphs. In ICPR '06, pages
449{452, 2006.
9. P. Doyle and J. Snell. Random Walks and Electrical Networks. Mathematical Association of
America, Washington, 1984.
10. P.C. Richter F. Magniez, A. Nayak and M. Santha. On the hitting times of quantum versus
random walks. arXiv:0808.0084v1 [quant-ph], 2008.
11. E. Farhi and S. Gutmann. Quantum computation and decision trees. Phys. Rev. A, 58:915{928,
1998.
12. L. Grover. A fast quantum mechanical algorithm for database search. In Proc. 28th Annual ACM
Symposium on the Theory of Computation, pages 212{219, New York, NY, 1996. ACM Press, New
York.
13. F. B. Hildebrand. Introduction to numerical analysis. McGraw-Hill, New York, 2nd edition, 1973.
14. J. Kempe. Quantum random walks|an introductory overview. Contemporary Physics, 44(4):307{
327, 2003.
15. J. Kempe. Quantum random walks hit exponentially faster. In Proc. of 7th Intern. Workshop on
Randomization and Approximation Techniques in Comp. Sc. (RANDOM'03), pages 354{69, 2003.
16. H. Krovi and T.A. Brun. Hitting time for quantum walks on a hypercube. Phys. Rev. A, 73:032341,
24 Graph Embedding using Quantum Hitting Time
2006.
17. L. Lov?asz. Combinatorics, Paul Erd?os is Eighty, volume 2, chapter Random Walks on Graphs: A
Survey, pages 353{398. J?anos Bolyai Mathematical Society, Budapest, 1996.
18. B. Luo, R. C. Wilson, and E. Hancock. Spectral embedding of graphs. Pattern Recognition,
36(10):2213{2230, 2003.
19. H. Krovi M. Varbanov and T.A. Brun. Hitting time for the continuous time quantum walks.
arXiv:0803.3446v1 [quant-ph], 2008.
20. M. Meila and J. Shi. A random walks view of spectral segmentation. In AI and STATISTICS
(AISTATS) 2001, 2001.
21. A. Nayak and A. Vishwanath. Quantum walk on the line, 2000.
22. M. Neuhaus and H. Bunke. A random walk kernel derived from graph edit distance. In SSPR,
pages 191{199, 2006.
23. H. Qiu and E. Hancock. Robust multi-body motion tracking using commute time clustering. In
Proc ECCV, pages 160{173, 2006.
24. H. Qiu and E.R. Hancock. Clustering and embedding using commute times. IEEE Transactions
on Pattern Analysis and Machine Intelligence, 29(11):1873{1890, 2007.
25. A. Robles-Kelly and E. R. Hancock. String edit distance, random walks and graph matching.
International Journal of Pattern Recognition and Artiˉcial Intelligence, 18(3):315{327, 2004.
26. A. Robles-Kelly and E. R. Hancock. Graph edit distance from spectral seriation. IEEE Transac-
tions on Pattern Analysis and Machine Intelligence, 27(3):365{378, 2005.
27. T. Rudolph. Constructing physically intuitive graph invariants, 2002.
28. L. Sarti, M. Maggini, and M. Gori. Exact and approximate graph matching using random walks.
IEEE Trans. Pattern Anal. Mach. Intell., 27(7):1100{1111, 2005.
29. N. Shenvi, J. Kempe, and K. B. Whaley. A quantum random walk search algorithm. Phys. Rev.
A, 67(5), 2003.
30. S. Shiau, R. Joynt, and S. N. Coppersmith. Physically-motivated dynamical algorithms for the
graph isomorphism problem, 2005.
31. P. W. Shor. Polynomial-time algorithms for prime factorization and discrete logarithms on a
quantum computer. SIAM J. Comput., 26:1484{1509, 1997.
32. A. Sinclair. Algorithms for random generation and counting: a Markov chain approach. Birkhauser
Verlag, Boston, 1993.
33. Mario Szegedy. Quantum speed-up of markov chain based algorithms. pages 32{41, 2004.
34. A. Webb. Statistical Pattern Recognition, 2nd Ed. John Wiley & Sons, Chichester, England, 2002.
35. T. Yamasaki, H. Kobayashi, and H Imai. Analysis of the absorbing times of quantum walks. Phys.
Rev. A.
36. X. Zhu, Z. Ghahramani, and J. La?erty. Semi-supervised learning using gaussian ˉelds and
harmonic functions. ICML, pages 1561{1566, 2003.

Fischbach 3D Physical Design: Challenges and Solutions p6

Here, a netlist hypergraph is embedded into the layout area.

okokok
Fr?hlich Parallel Genetic Algorithm for Optimizing Run-time Reconfigurable Circuits p4

Gnanaolivu Mapping loops onto Coarse-Grained Reconfigurable Architectures using Particle Swarm Optimization p7

Gnanaolivu Mapping loops onto Coarse-Grained Reconfigurable Architectures using Particle Swarm Optimization p7

embedding of Data Flow Graph (DFG) on Routing Resource Graph (RRG)

graph embedding technique using an affinity graph heuristic and skewed scheduling space

Coarse-Grained Reconfigurable Architectures

Particle Swarm Optimization

Modulo Scheduling

Loop level parallelism

Mapping

The mapping algorithm MCHPSO maps each node of the DFG to a node of the RRG and each edge of the DFG to a path in the RRG.

Modulo Constrained Hybrid Particle Swarm Optimization

[14] H. Park, K. Fan, M. Kudlur, and S. Mahlke, “Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures,” in CASES ?06: Proceedings of the 2006 international conference on Compilers, architecture, pp. 136- 146, ACM Press, 2006.

Gokhale Automatic Allo cation of Arrays to Memories in FPGA Pro cessors With Multiple Memory Banks

Grotschel The Steiner Tree Packing Problem in VLSI Design p21

Grotschel The Steiner Tree Packing Problem in VLSI Design p21

Grotschel The Steiner Tree Packing Problem in VLSI Design p21

10

routing in VLSI design

switchbox routing knock-knee routing

Manhattan routing

Steiner tree packing problem

packing of Steiner trees in certain graphs

integer programming formulations

cutting plane algorithms

integer programming formulation of the Steiner tree packing problem and describe several classes of valid and facet-defining inequalities for the associated Steiner tree packing polyhedron.

okokokok
Hartenstein Enabling Technologies for Reconfigurable Computing Part 4 FPGAs: recent developments p95

??????????
Havinga Rattlesnake -- a Single Chip High-Performance ATM Switch p10
Paul J.M. Havinga, Gerard J.M. Smit
5

Htncu DYPP - A VLS! Supercomputer Architecture Supporting Two.Level Fault Tolerance Program Graph InJection and Data Levitation Concepts p6

Huelsbergen A Representation for Dynamic Graphs in Reconfigurable Hardware and its Application to Fundamental Graph Algorithms p11

Kahng Border Length Minimization in DNA Array Design p17

Kautz graph / Kautz digraph
Kautz K(d,k) graph (with degree d and diameter k)

In the network a switching element maps onto a node of the graph, and a link maps onto an edge of the graph.

Embedding of graphs: Kautz graphs embed standard computation graphs such as: a ring and a d-ary tree. This
property can be used to implement multicast and broadcast efficiently.

okokok
Klymko, C., Sullivan, B., Humble, T.? Adiabatic quantum programming: minor embedding with hard faults.? Quantum Information Processing: Volume 13, Issue 3 (2014), pp 709- 729. arXiv:1210.8395v2 [quant-ph].

Klymko, C., Sullivan, B., Humble, T.

Adiabatic quantum programming: minor embedding with hard faults.

Quantum Information Processing: Volume 13, Issue 3 (2014), pp 709- 729. arXiv:1210.8395v2 [quant-ph].

Klymko, C., Sullivan, B., Humble, T.

Adiabatic quantum programming: minor embedding with hard faults.

Quantum Information Processing: Volume 13, Issue 3 (2014), pp 709- 729. arXiv:1210.8395v2 [quant-ph].

[Klymko2013] Adiabatic quantum programming: minor embedding with hard faults p21

Klymko, C., Sullivan, B., Humble, T. Adiabatic quantum programming: minor embedding with hard faults. Quantum Information Processing: Volume 13, Issue 3 (2014), pp 709 – 729. arXiv:1210.8395v2 [quant-ph].

Klymko, C., Sullivan, B., Humble, T. Adiabatic quantum programming: minor embedding with hard faults. Quantum Information Processing: Volume 13, Issue 3 (2014), pp 709- 729. arXiv:1210.8395v2 [quant-ph].

Quantum Inf Process
DOI 10.1007/s11128-013-0683-9

Christine Klymko

Blair D. Sullivan

Travis S. Humble

Received: 8 November 2012 / Accepted: 4 November 2013 ? Springer Science+Business Media New York 2013

C. Klymko

Department of Mathematics and Computer Science, Emory University, 400 Dowman Drive, Atlanta, GA 30322, USA

cklymko@emory.edu

T. S. Humble

Oak Ridge National Laboratory, Quantum Computing Institute, 1 Bethel Valley Road, Oak Ridge, TN 37831, USA

humblets@ornl.gov

B. D. Sullivan

Department of Computer Science, North Carolina State University, Raleigh, NC 27695, USA

blair_sullivan@ncsu.edu

===================================

14

the embedding algorithm must handle a variety of target graphs

subgraph embedding

A subgraph embedding of P into F is a mapping f : VP ? VF such that:
1. each vertex in VP is mapped to a unique vertex in VF .
2. if (u, v) ? EP, then ( f (u), f (v)) ? EF .

minor embedding

A minor embedding of P in F is defined by a mapping ? : VP ? VF such that:
1. each vertex v in VP is mapped to the vertex set of a connected subtree Tv of F.
2. if (u, v) ? EP, then there exist iu, iv ? VF such that iu ? Tu, iv ? Tv, and (iu, iv) ? EF .
If such a mapping ? exists, then P is minor-embeddable in F or P is a minor of F, written P ?m F.

Equivalently, P is minor-embeddable in F if P can be obtained from F by a series of edge deletions and contractions

Minor embedding uses explicit information about the logical fabric as well as the problem to generate
the implementation of the AQO algorithm.

an arbitrary input graph can be minor-embedded within one type of highly regular fabric, a square lattice of K4,4s, complete bipartite graphs with eight vertices.

algorithms for minor embedding into additional logical fabrics, namely, square lattices of Kc,c with c ? 1.

hardware graph for minor embedding a large clique, Kn, in a limited number of qubits

maximal minor embedding

a brute force embedding via graph isomorphism in maximal minors

every subgraph embedding is also a minor embedding (since f (v) is a single node subtree of F).

graph minor

================================

naive embedding approaches

optimal embedding

explicit embedding

brute force embedding

greedy embedding

complete-graph embedding

embedding of a complete graph in F (hardware graphs)

Fallback embedding algorithm

fault-tolerant embedding algorithms

drop-down embedding scheme

“smart” embedding scheme

===============================

graph embeddability

tree decomposition

a combinatorial way of measuring how “tree-like” a graph is

tree decomposition of the hardware graph

Given a graph G = (V, E) let T = (I, D) be a tree, and V = {Vi }i?I be a family of vertex sets (also called bags) with Vi ? V indexed by the elements of I . The pair (T, V) forms a tree decomposition of G if the following hold:
1. V = ?i?I Vi .
2. if (u, v) ? E, then there exists i ? I such that {u, v} ? Vi .
3. for i1, i2, i3 ? I , if i3 lies on the path in T between i1 and i2, then Vi1 ? Vi2 ? Vi3 .
Equivalently, for any vertex v ? V, {i : v ? Vi } forms a connected subtree of T .

The width of a tree decomposition (T, V) is given by maxi?I {|Vi| - 1}.

treewidth

The treewidth ?(G) of a graph G is the minimum width over all tree decompositions of G.

graphs of bounded treewidth

treewidth for hardware graphs

Treewidth of the hardware graph

===========================

Adiabatic quantum programming

adiabatic quantum optimization algorithm

Adiabatic quantum optimization (AQO) applies the principles of quantum computing to solve unconstrained optimization problems.

The AQO algorithm is based on the reduction of an unconstrained optimization problem to a quantum logical Hamiltonian that is diagonal in the computational basis.

programming the AQO algorithm requires embedding P in the graph F representing the logical fabric.

P is an n-by-n symmetric real-valued matrix.

quadratic unconstrained binary optimization (QUBO) problem

Programming adiabatic quantum computing hardware to solve a specific problem requires embedding a problem graph P = (VP, EP) representing the QUBO problem (elements of VP correspond to QUBO variables and EP = {(i, j )| Pi, j = 0}) into a hardware graph F = (VF , EF ) whose vertices representing the qubits and edges are determined by couplings in the logical fabric. In some cases, this can be done in a one-to-one manner through subgraph embedding.

========================

(quantum) hardware graphs

unit-cell

The building blocks of this graph are 8-qubit unit cells whose internal couplings form K4,4

cells consist of 2c qubits forming a Kc,c

Unit cells are tiled together with each qubit on the left half of a K4,4 connected to its image in the cells directly above and below, and each qubit on the right half of the K4,4 connected to its image in the cells directly to the left and right. Note that due to the way the qubits are physically connected [19], when there is a failure, it will be the failure of a qubit and not an individual coupler. In terms of the hardware graph, this means vertices (and all their adjacent edges) will fail, not individual edges.

and are attached to form an m × m grid in the same manner as described above.

hardware fabric

logical fabric (hardware)

Hamiltonian

hard faults

Hard faults refer to defects in the logical fabric that compromise its regularity.

minor embedding that use heuristics to adapt to random faults in the logical fabric (hardware).

References
1. Adler, I., et al.: Faster parameterized algorithms for minor containment. Theor. Comput. Sci. 412, 7018–7028 (2011)
2. Altshuler, B., Karvi, H., Roland, J.: Anderson localization makes adiabatic quantum optimization fail. Proc. Natl. Acad. Sci. USA 108, E19–E20 (2011) 123 Adiabatic quantum programming
3. Amir, E.: Approximation algorithms for treewidth. Algorithmica 56, 448–479 (2010)
4. Bian, Z., Chudak, F., Macready, W.G., Clark, L., Gaitan, F.: Experimental determination of Ramsey numbers. Phys. Rev. Lett. 111, 130505 (2013)
5. Bodlaender, H.L.: A tourist guide through treewidth. Acta Cybern. 11, 1–23 (1993)
6. Bodlaender, H.L.: A linear-time algorithm for finding tree decompositions of small treewidth. SIAM J. Comput. 25, 1035–1317 (1996)
7. Bodlaender, H.L., Koster, A.M.C.A.: Treewidth Computations II. Lower Bounds, Technical Report UU-CS-2010-022. Department of Information and Computing Sciences, Utrecht University (2010)
8. Boros, E., Hammer, P.L.: Pseudo-boolean optimization. Discret. Appl. Math. 123, 155–225 (2002)
9. Choi, V.: Minor-embedding in adiabatic quantum computation: I. The parameter setting problem. Quantum Inf. Process. 7, 193–209 (2008)
10. Choi,V.: Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design. Quantum Inf. Process. 10, 343–353 (2011)
11. Dickson, N.G., Amin, M.H.S.: Does adiabatic quantum optimization fail for NP-complete problems? Phys. Rev. Lett. 106, 050502 (2011)
12. Dickson, N.G., Amin, M.H.S.: Algorithmic approach to adiabatic quantum optimization. Phys. Rev. A 85, 032303 (2012)
13. Diestel, R.: Graph Theory. Springer, Heidelberg (2005)

14. D-Wave Systems Inc., 100–4401 Still Creek Drive, Burnaby V5C 6G9, BC, Canada.

http://www. dwavesys.com/

15. Farhi, E., Goldstone, J., Gutmann, S., Sipser, M.: Quantum computation by adiabatic evolution, arxiv:quant-ph/0001106 (2000)
16. Farhi, E., et al.: A quantum adiabatic evolution algorithm applied to random instances of an NPcomplete
problem. Science 292, 472–476 (2001)

17. Fomin, F.V., Thilikos, D.M.: Dominating sets and local treewidth. LNCS 2832, 221–229 (2003)

Fomi Dominating sets and local treewidth p10

treewidth of a planar graph

dominating set of size d

fixed parameter algorithms on planar graphs

minor closed graph families

domination-treewidth

local treewidth

d-dominating set D of a graph G

3

18. Gaitan, F., Clark, L.: Ramsey numbers and adiabatic quantum computing. Phys. Rev. Lett. 108, 010501
(2012)
19. Harris, R., et al.: Experimental investigation of an eight qubit unit cell in a superconducting optimization processor. Phys. Rev. B 82, 024511–024526 (2010)
20. Kleinberg, J., Rubinfeld, R.: Short paths in expander graphs. In: Proceedings of the 37th Annual Symposium on Foundations of Computer Science, pp. 86–95 (1996)
21. Neven, H., Rose, G., Macready, W.G.: Image recognition with an adiabatic quantum computer I. Mapping to quadratic unconstrained binary optimization, arXiv:0804.4457v1 [quant-ph] (2008)
22. Perdomo-Ortiz, A., Dickson, N., Drew-Brook, M., Rose, G., Aspuru-Guzik, A.: Finding low-energy conformations of lattice protein models by quantum annealing. Sci. Rep. 2, 571 (2012)
23. Pudenz, K.L., Lidar, D.A.: Quantum adiabatic machine learning. Quantum Inf. Process. 12, 2027–2070 (2012)
24. Robertson, N., Seymour, P.D.: Graph minors. XIII: the disjoint paths problem. J. Comb. Theory Ser. B 63, 65–110 (1995)
25. Xiong, L., Dinneen, M.J.: The Feasibility and Use of a Minor Containment Algorithm, Computer Science Technical Reports 171, University of Auckland (2000)

Xiong The Feasibility and Use of a Minor Containment Algorithm p25

minor containment problem

Lucas Adiabatic Quantum Computing

Lucas Adiabatic Quantum Computing p47.pdf

[Lucas2012] Adiabatic Quantum Computing p47.pdf

encoded embedding

unencoded embedding

Malmheden ModeGraph - A Mode-Automata Based Modelica Library for Embedded Control p86

MARVASTI AN ANALYSIS OF NOCS IN FPGAS p232

Okokokokoko important?

MILLER Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation p22

kokok
MILLER Embedding-Based Placement of Processing element Networks on FPGAs for Physical Model Simulation p17
okokok
[MILLER2013] Embedding-Based Placement of Processing element Networks on FPGAs for Physical Model Simulation p17
Okokokokoko important

MILLER Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation p22

The second phase maps the structured virtual PE graph onto physical PE regions on an FPGA
using graph embedding theory
Compared to previous work on physical model implementation on FPGAs, embedding increases clock frequency by 25% on average (for applicable topologies), whereas simulated annealing increases frequency by 13% on average.
The embedding approach typically produces a circuit whose frequency is limited by the FPGA clock instead of routing.
Fig. 1. Two-phase approach of mapping physical model equations onto a structured graph of virtual PEs,
and mapping virtual PEs onto a FPGA utilizing graph embedding techniques.
Our work leverages graph theoretic techniques to embed the topology of a physical model onto a two-dimensional (2D) mesh of PEs on an FPGA.
The second phase defines physical PE regions on the FPGA, onto which virtual PEs may be mapped,
and then finds the actual placement using a graph embedding algorithm or simulated annealing. In Figure 1, a graph embedding algorithm maps a binary tree to a 2D grid by placing the root in a physical PE region in middle of the grid and expanding child subtrees outward.

5.2. Graph Embedding–Based Placement
Physical models that exhibit common structures are able to take advantage of graph embedding techniques during physical placement. Graph embedding is the process of mapping a guest graph of architecture g onto a host graph of a different architecture h.

The graph embedding problem relates to the general mapping problem, where computational tasks must be placed onto a host architecture such that communication between PEs is minimized [Berman and Snyder 1987].

topology-specific graph embedding

Graph embedding: Map guest graph to host graph, minim. max wire length

H-tree embedding

Linear embedding

Direct map embedding

okokok
Newsome GEM: Graph EMbedding for Routing and DataCentric Storage in Sensor Networks Without Geographic Information

Newsome GEM: Graph EMbedding for Routing and Data- Centric Storage in Sensor Networks Without Geographic Information p14

Ostadzadeh Parallelism Utilization in Embedded Reconfigurable Computing Systems A Survey of Recent Trends p11

Ostadzadeh Parallelism Utilization in Embedded Reconfigurable Computing Systems A Survey of Recent Trends p11

?ZSARA? FPGA IMPLEMENTATION OF GRAPH CUT METHOD FOR REAL TIME STEREO MATCHING p87

Parhami Introduction to Parallel Processing? Algorithms and Architectures p557

Park Modulo Graph Embedding: Mapping Applications onto Coarse Grained Reconfigurable Architectures??

Park Modulo Graph Embedding: Mapping Applications onto Coarse Grained Reconfigurable Architectures

modulo graph embedding

Park Modulo Graph Embedding: Mapping Applications onto Coarse Grained Reconfigurable Architectures
Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott Mahlke
Advanced Computer Architecture Laboratory
University of Michigan
Ann Arbor, MI 48109
{parkhc, fank, kvman, mahlke}@umich.edu

CASES’06, October 23–25, 2006, Seoul, Korea.
Copyright 2006 ACM 1595935436/
06/0010 ...$5.00.
P4

Graph Embedding for Coarse Grained Reconfigurable Architectures

modulo graph embedding.
graph embedding is used to draw graphs onto a target space
mapping
embedded computing
Coarse-grained reconfigurable architectures (CGRAs)

Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures?? okokok

okokok

Shafaei Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures
Alireza Shafaei, Mehdi Saeedi, and Massoud Pedram
Department of Electrical Engineering
University of Southern California
Los Angeles, CA 90089
fshafaeib,msaeedi,pedramg@usc.edu
Sept 2013

complete graph
connectivity graph
interaction graph
mapping problem is a standard graph embedding problem with connectivity and interaction graphs as the host and guest graphs, respectively.
(weighted) hypergraph
embedding a weighted undirected interaction graph

binary welded tree

okokok
Sim Automatic Graph Drawing Algorithms p16

Susan Sim

convex embedding

Many fields in computer science, such as software engineering, electronic circuit design and database design, have found it useful represent data as graphs, with vertices denoting elements and edges denoting relations between them.

Computer hardware and microchips are now sufficiently complex that they are designed using CAD tools. It is then the responsibility of the tool to create a layout of the logical gates and the connections between them on microchips and circuit boards. This layout should be a grid drawing. An orthogonal drawing is one in which an edge is a chain of
horizontal and vertical segments. A grid drawing is an orthogonal drawing in which all the vertices and bends of edges have integer coordinates. (Di Battista, et al., 1994)

Souri 3D ICs Interconnect Performance Modeling and Analysis p123

Souri Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications p8

Stroop Enhancing GNU Radio for Run-Time Assembly of FPGA-Based Accelerators p113

Szeszler Combinatorial Algorithms in VLSI Routing p78

Thompson A Complexity Theory for VLSI

Thompson A Complexity Theory for VLSI p106

three-layer embedding

planar embeddings

Thompson A Complexity Theory for VLSI p106
August1980
graph embedding

4. Upper bounds
4.3 VLSI implementations of the FF1’ 85
4.3.4 Area bounds for the shuffle-exchange graph

Chapter 1
~nt rod uct~on
communication graph

Chapter 1

1.4 Related work
graph embedding
partitioning the graph

Ch3pter 2
The VLSI mod& of cornputat~on
communication graph
admissible communication graph

2.1 Lower bounds
shuffle-exchange graph

THOMPSON Fourier Transforms in VLSI p11

THOMPSON Fourier Transforms in VLSI p11

okokok
Tyagi Energy Complexity of Optical Computations p22

2 Models
Thompson's 2 D VLSI model [Tho79]: In Thompson's 2 D VLSI model a computation is abstracted as a communication graph, which is very much like a flow graph with the primitives being some basic operators that are realizable as electrical devices. A chip layout can be viewed as a convex embedding of the communication graph in a multilayered Cartesian grid.

Wilton Memory/Logic Interconnect Flexibility in FPGAs with Large Emb edded Memory Arrays

YAMADA ON THREE-DIMENSIONAL LAYOUT OF DE BRUIJN NETWORKS p4

Yamada ON THREE-DIMENSIONAL LAYOUT OF PYRAMID NETWORKS p6

Yoon Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm p19

Yoon I2CRF Incremental Interconnect Customization for Embedded Reconfigurable Fabrics p6

Yu Embedding with Autoencoder Regularization p16

Yu Topology Mapping for Blue Gene/L Supercomputer p13

Yu Topology Mapping for Blue Gene/L Supercomputer p13

grid-embedding

Matrix-based embeddings

Zhang On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems p14

network embedding

Ziener Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs p325


Untitled Document

Research and Writing Project for Graph Embedding

This project is evolved out of my graph theoretic research plan for VLSI – Very Large Scale Integration – design, particularly the latest IC technologies.

For my part of researches as far as graph theory is concerned, I will concentrate on the graph embedding problem because it was of my interest in quantum circuits where a certain circuit was composed of socalled Chimera graph and it was their embedding into a larger graph that makes the quantum circuit operable – see the D – Wave quantum computer for details.?

This idea is also of use to general graph theoretic research for VLSI design, particularly the latest IC technologies such as the spin based circuits, the nano IC technologies etc, just to name a few, and graph embedding is the very starting point of IC design. How well a circuit is embedded into a graph will greatly affect the subsequent design quality and efficiency and hence is very important to the overall IC development progress.

I have, as a result of intensive investigation over the last year or so, discovered a great number (over 250+ types) of embedding technologies and algorithms, and I am very willing to complete my research with a comprehensive review and some of my own insights. That will eventually lead to a huge volume of research results with perhaps thousands of pages of introductory contents of the graph embedding theory, algorithms and systems, and this will also take tremendous efforts in time and studies.

Graph embedding is related also to
Graph Clustering
Graph Coloring
Graph Coupling
Graph Drawing
Graph Encoding
Graph Isomorphism
Graph Layout
Graph Mapping
Graph Matching
Graph Packing
Graph Partitioning
Graph Visualization
Extremal graph theory
Metric graph theory
Spectral graph theory
Topological graph theory

to some degree (some might be synnonyms).


Untitled Document

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Embedding Characters
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Embedding Limits
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[Britt2014]
D-Wave Embedding Limits

D-Wave Embedding Limits

  • Logical Qubit is Not the Same as a Physical Qubit
  • Can Always Embed N Logical Qubits onto N2 Physical Qubits
  • This is Not a Tight Upper-bound, Even for Complete Graph
  • Choi’s Triad Technique Able to Embed on 128-Qubit Processor
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Graph Embedding

Graph E(i)mbedding

0doc_graph_embedding
├<1graph_embedding_definition>
│ └graph_embedding_definition.htm
├<2graph_embedding_synonym>
│ ├graph_embedding_synonym_definition.htm
│ ├graph_embedding_synonym_ref.htm
│ └graph_generation.htm
├<3graph_embedding_types>
│ ├<EmbeddingAlgorithms>
│ │ └EmbeddingAlgorithms.htm
│ ├<EmbeddingCharacters>
│ │ └EmbeddingCharacters.htm
│ ├<EmbeddingTechniquesSoftwareTools>
│ │ └EmbeddingTechniquesSoftwareTools.htm
│ ├graph_embedding_types_00others.htm
│ ├graph_embedding_types_a.htm
│ ├graph_embedding_types_b.htm
│ ├graph_embedding_types_c.htm
│ ├graph_embedding_types_d.htm
│ ├graph_embedding_types_e.htm
│ ├graph_embedding_types_f.htm
│ ├graph_embedding_types_g.htm
│ ├graph_embedding_types_h.htm
│ ├graph_embedding_types_i.htm
│ ├graph_embedding_types_j.htm
│ ├graph_embedding_types_k.htm
│ ├graph_embedding_types_l.htm
│ ├graph_embedding_types_m.htm
│ ├graph_embedding_types_n.htm
│ ├graph_embedding_types_o.htm
│ ├graph_embedding_types_p.htm
│ ├graph_embedding_types_q.htm
│ ├graph_embedding_types_r.htm
│ ├graph_embedding_types_s.htm
│ ├graph_embedding_types_t.htm
│ ├graph_embedding_types_u.htm
│ ├graph_embedding_types_v.htm
│ ├graph_embedding_types_w.htm
│ ├graph_embedding_types_x.htm
│ ├graph_embedding_types_y.htm
│ └graph_embedding_types_z.htm
├<4graph_embedding_types_specials>
│ ├graph_editingtools.htm
│ ├graph_embedding_prototype.htm
│ ├graph_matching.htm
│ ├graph_packing.htm
│ ├<topological_graph_embedding>
│ │ └topological_graph_embedding.htm
│ └<topological_graph_theory>
│ └topological_graph_theory.htm
├<5graph_embedding_algotechothers>
│ └graph_embedding_algotechothers.htm
├<6graph_embedding_algotechothers_specials>
│ └graph_laplacian.htm
├<7graph_embedding_applications>
│ └graph_embedding_applications.htm
├<8graph_embedding_applications_vlsi>
│ ├graph_embedding_vlsi.htm
│ └graph_embedding_vlsi_researchplan.htm
├<9graph_embedding_references>
│ ├graph_embedding_ref_00others.htm
│ ├graph_embedding_ref_a.htm
│ ├graph_embedding_ref_b.htm
│ ├graph_embedding_ref_c.htm
│ ├graph_embedding_ref_d.htm
│ ├graph_embedding_ref_e.htm
│ ├graph_embedding_ref_f.htm
│ ├graph_embedding_ref_g.htm
│ ├graph_embedding_ref_h.htm
│ ├graph_embedding_ref_i.htm
│ ├graph_embedding_ref_j.htm
│ ├graph_embedding_ref_k.htm
│ ├graph_embedding_ref_l.htm
│ ├graph_embedding_ref_m.htm
│ ├graph_embedding_ref_n.htm
│ ├graph_embedding_ref_o.htm
│ ├graph_embedding_ref_p.htm
│ ├graph_embedding_ref_q.htm
│ ├graph_embedding_ref_r.htm
│ ├graph_embedding_ref_s.htm
│ ├graph_embedding_ref_t.htm
│ ├graph_embedding_ref_u.htm
│ ├graph_embedding_ref_v.htm
│ ├graph_embedding_ref_w.htm
│ ├graph_embedding_ref_x.htm
│ ├graph_embedding_ref_y.htm
│ └graph_embedding_ref_z.htm
├graph_embedding.htm
└sample.htm

The document depository:

0000graph_embedding
├<0graph embedding>
│ ├000Baingana Embedding Graphs under Centrality Constraints p54.pdf
│ ├000Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow a Java Environment for Graph Drawing p144.pdf
│ ├000Cardinal The Complexity of Simultaneous Geometric Graph Embedding p71.pdf
│ ├000Chowdhury Point-Set Embeddings of Planar Graphs with Fewer Bends p67.pdf
│ ├000Cooley EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf
│ ├000Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│ ├000Gibert Graph Embedding in Vector Spaces p66.pdf
│ ├000Gibert Vector Space Embedding of Graphs via Statistics of Labelling Information p162.pdf
│ ├000Grilli Automated Local Linear Embedding with an application to microarray data p92.pdf
│ ├000Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134.pdf
│ ├000LUQMAN Fuzzy Multilevel Graph Embedding for Recognition Indexing and Retrieval of Graphic Document Images p186.pdf
│ ├000Potoczak Survey of Graph Embeddings into Compact Surfaces p117.pdf
│ ├000Riesen Classification and Clustering of Vector Space Embedded Graphs p344.pdf
│ ├000Shaw Graph Embedding and Nonlinear Dimensionality Reduction p108.pdf
│ ├Alipanahi Guided Locally Linear Embedding p25.pdf
│ ├Archdeacon The Pagenumber of Complete Bipartite Graphs p2.docx
│ ├ARORA Expander Flows, Geometric Embeddings and Graph Partitioning p30.pdf
│ ├Asano A Linear-Space Algorithm for Distance Preserving Graph Embedding p23.pdf
│ ├Azary Grassmann Learning for Recognition and Classification p132.pdf
│ ├Bai Heat Kernels, Manifolds and Graph Embedding p9.pdf
│ ├Baingana CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5.pdf
│ ├Bandelt Metric graph theory and geometry a survey p30.pdf
│ ├Belkin Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering p7.pdf
│ ├Brand A unifying theorem for spectral embedding and clustering p8.pdf
│ ├Brandes Colored Simultaneous Geometric Embeddings and Universal Pointsets p24.pdf
│ ├Brink Spherical parameterization methods for 3d surfaces p152.pdf
│ ├Britt Embedding Logical Qubits into the D-Wave Hardware Graph p30.pptx
│ ├Bunke Applied Pattern Recognition p246.pdf
│ ├Busa-Fekete Locally Linear Embedding and its Variants for Feature Extraction p6.pdf
│ ├Cabello Algorithms for embedded graphs p93.pdf
│ ├Cappos Simultaneous Graph Embedding with Bends and Circular Arcs p12.pdf
│ ├Cardinal The Complexity of Simultaneous Geometric Graph Embedding p14.pdf
│ ├Chang Robust Locally Linear Embedding p10.pdf
│ ├Chang Robust Locally Linear Embedding p25.pdf
│ ├Charikar Spectral Embedding of k-Cliques Graph Partitioning and k-Means p27.pdf
│ ├CHARTRAND Chromatic Graph Theory p498.pdf
│ ├Chepoi Constant approximation algorithms for embedding graph metrics into trees and outerplanar graphs p27.pdf
│ ├CHUNG EMBEDDING GRAPHS IN BOOKS A LAYOUT PROBLEM WITH APPLICATIONS TO VLSI DESIGN p26.pdf
│ ├Conte A Comparison of Explicit and Implicit Graph Embedding Methods for Pattern Recognition p11.pdf
│ ├Cvetkovski Hyperbolic Embedding and Routing for Dynamic Graphs p7.pdf
│ ├Cygan Tight Lower Bounds on Graph Embedding Problems p23.pdf
│ ├Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166.pdf
│ ├Dell Graph Embedding and Extensions A General Framework for Dimensionality Reduction p21.ppt
│ ├DeMillo Combinatorial graph embedding p87.pdf
│ ├Dolev PLANAR EMBEDDING OF PLANAR GRAPHS p15.pdf
│ ├Ebner Optimal Crossing Minimization using Integer Linear Programming p87.pdf
│ ├Erten Simultaneous Embedding of a Planar Graph and its Dual on the Grid o17.pdf
│ ├Ferrer A Recursive Embedding Approach to Median Graph Computation p11.pdf
│ ├Gagarin Embedding Graphs Containing K5-Subdivisions p17.pdf
│ ├Gagarin Embeddings of Small Graphs on the Torus p19.pdf
│ ├Gassner Simultaneous Geometric Graph Embeddings p12.pdf
│ ├Goodwin Imbedding Problems in Graph Theory p27.pdf
│ ├Graham Isometric graph embeddings p18.pdf
│ ├Groenen Multidimensional Scaling p14.pdf
│ ├He Graph Embedding with Constraints p6.pdf
│ ├He2009 Graph Embedding with Constraints p6.pdf
│ ├Hong MultiPlane Graph Embedding (2.5D Graph Embeddability).docx
│ ├Horaud A Short Tutorial on Graph Laplacians, Laplacian Embedding, and Spectral Clustering p43.pdf
│ ├Huang Cross-view Graph Embedding p12.pdf
│ ├Jameson An Address Event Representation (AER) Multicast Router for Colour Vision p200.pdf
│ ├Jouili Graph Embedding Using Constant Shift Embedding p12.pdf
│ ├Kermarrec Distributed Social Graph Embedding p6.pdf
│ ├Keselman Many-to-Many Graph Matching via Metric Embedding p8.pdf
│ ├Kleinberg Isomorphism and Embedding Problems for Infinite Limits of Scale-Free Graphs p10.pdf
│ ├Kocurova2007 Analysis of algorithms for computing the crossing number p119.pdf
│ ├Kong An Iterative Locally Linear Embedding Algorithm p8.pdf
│ ├Krug New Approaches on Octilinear Graph Drawing p165.pdf
│ ├Kuhn Embedding and Ramsey numbers of sparse k uniform hypergraphs p24.pdf
│ ├Kuhn Embedding cycles of given length in oriented graphs p8.pdf
│ ├Kuhn Embedding large subgraphs into dense graphs p28.pdf
│ ├Lee Locally Linear Embedding versus Isotop p8.pdf
│ ├Lipman Symmetry Factored Embedding And Distance p12.pdf
│ ├Liu Projective Nonnegative Graph Embedding p11.PDF
│ ├Los Embedding Groups of Graph Automorphisms in Surfaces p20.pdf
│ ├Luo Cauchy Graph Embedding p8.pdf
│ ├Luo Non-negative Laplacian Embedding p10.pdf
│ ├Luqman Fuzzy multilevel graph embedding p15.pdf
│ ├Matsubayashi Separator-Based Graph Embedding into Multidimensional Grids with Small Edge-Congestion p30.pdf
│ ├MOHAR A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21.pdf
│ ├Najim More faithfulness graph embedding p9.pdf
│ ├Newsome GEM Graph EMbedding for Routing and DataCentric Storage in Sensor Networks Without Geographic Information p13.pdf
│ ├Nishana Graph Embedding and Dimensionality Reduction - A Survey p6.pdf
│ ├Ou Asymmetric Transitivity Preserving Graph Embedding p10.pdf
│ ├Perrault-Joncas Directed Graph Embedding an Algorithm based on Continuous Limits of Laplacian-type Operators p9.pdf
│ ├Pizzonia Minimum Depth Graph Embedding p12.pdf
│ ├Potoczak Survey of Graph Embeddings into Compact Surfaces p117.pdf
│ ├Rajan Embeddings Between Hypercubes and Hypertrees p13.pdf
│ ├Raveaux Graph Embedding Problem p37.pdf
│ ├Renz Hierarchical Graph Embedding for Efficient Query Processing in Very Large Traffic Networks p30.pdf
│ ├Ridder Supervised locally linear embedding p8.pdf
│ ├Robles-Kelly A Riemannian approach to graph embedding p15.pdf
│ ├Rodl Hypergraph packing and graph embedding p18.pdf
│ ├Sarvottamananda Planar Graphs Planarity Testing and Embedding p151.pdf
│ ├Sarvottamananda Planar Graphs, Planarity Testing and Embedding p151.pdf
│ ├Saul An Introduction to Locally Linear Embedding p13.pdf
│ ├Saxe Two papers on graph embedding problems p41.pdf
│ ├Shaw Structure Preserving Embedding p8.pdf
│ ├Shaw Visualizing Graphs with Structure Preserving Embedding p6.pdf
│ ├Simonraj Embedding of Poly Honeycomb Networks and the Metric dimension of Star of David Network p18.pdf
│ ├Song Clustered Embedding of Massive Social Networks p12.pdf
│ ├Stefano Graph embedding via dissimilarity mapping for network comparison p4.pdf
│ ├submission_14.pdf
│ ├Sudakov Nearly optimal embeddings of trees p36.pdf
│ ├Tamassia On-line Planar Graph Embedding p39.pdf
│ ├Vadapalli Fault Tolerant Ring Embedding in Tetravalent Cayley Network Graphs p12.pdf
│ ├Valveny Vector Space Embedding of Graphs via Statistics of Labelling Information p14.pptx
│ ├Verbeek Metric Embedding, Hyperbolic Space, and Social Networks p10.pdf
│ ├VITCC Graph Embedding.pdf
│ ├Wang Knowledge Graph Embedding by Translating on Hyperplanes p9.pdf
│ ├Wilkinson Multidimensional Scaling p30.pdf
│ ├Xiao From One Point to A Manifold Knowledge Graph Embedding For Precise Link Prediction p7.pdf
│ ├Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p12.pdf
│ ├Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p54.ppt
│ ├Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction1 p12.pdf
│ ├Yang Non-Negative Graph Embedding p8.pdf
│ ├Yang Variational Graph Embedding for Globally and Locally Consistent Feature Extraction p16.pdf
│ ├Yeh VLSI layouts of complete graphs and star graphs p7.pdf
│ ├Yu A Practical Algorithm for Embedding Graphs on Torus p18.pdf
│ ├Yu2014 A Practical Torus Embedding Algorithm and Its Implementation p84.pdf
│ ├Zhang Robust (Semi) Nonnegative Graph Embedding p17.pdf
│ ├Zhao Graph Attribute Embedding via Riemannian Submersion Learning p32.pdf
│ └Zhou Bounding the bandwidths for graphs p12.pdf
├<community browsing in graph>
├<Geometric Graph Theory>
│ ├0000Geometric Graph Theory.txt
│ ├Pach The Beginnings of Geometric Graph Theory p20.pdf
│ └Toth Universality in Geometric Graph Theory p96.pdf
├<graph abstractionsZZZ>
├<graph buildingZZZ>
├<graph compilation>
│ ├Alcazar A SAT Compilation of the Landmark Graph p8.pdf
│ └Kelly Compilation of XSLT into Data ow Graphs forWeb Service Composition p9.pdf
├<graph construction>
│ ├Hong Graph Construction and Analysis as a Paradigm for Plan Recognition p6.pdf
│ ├Khoreva Classifier Based Graph Construction for Video Segmentation p10.pdf
│ ├Kim Degree-based graph construction p12.PDF
│ ├Liu Large Graph Construction for Scalable Semi-Supervised Learning p8.pdf
│ ├MIZUNO The construction of a regular graph p31.pdf
│ ├Musco Graph Construction Through Laplacian Function Optimization p32.pdf
│ ├Saito Lecture 10 Graph Construction from Given Datasets p93.pdf
│ └Wang Fast Graph Construction Using Auction Algorithm p10.pdf
├<graph creating>
│ ├Kumar Creating Graph Abstractions for the Interpretation of Combined Functional and Anatomical Medical Images p10.pdf
│ └Posner Creating a Network Graph with Gephi p16.pdf
├<GRAPH DIAGRAMS>
├<graph drawing>
│ ├000graph_drawing.txt
│ ├000Mumford Drawing Graphs for Cartographic Applications p144.pdf
│ ├Alshayji Force Directed Algorithm p25.ppt
│ ├BARAHIMI WEB-BASED DRAWING SOFTWARE FOR GRAPHS IN 3D AND TWO LAYOUT ALGORITHMS p72.pdf
│ ├Battista Algorithms for Drawing Graphs an Annotated Bibliography p44.pdf
│ ├Bridgeman Techniques and Tools for Graph Drawing p168.pdf
│ ├Chiba Drawing Plane Graphs Nicely p15.pdf
│ ├Eades How to Draw a Graph Revisited p191.pdf
│ ├Eades Straight-Line Drawing Algorithms for Hierarchical Graphs and Clustered Graphs p34.pdf
│ ├Eades Symmetric Graph Drawing p28.pdf
│ ├El-Sayeda Study of Neural Network Algorithm for Straight-Line Drawings of Planar Graphs p7.pdf
│ ├Feng Coherent Time-Varying Graph Drawing with Multifocus Context Interaction p12.pdf
│ ├Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│ ├FRUCHTERMAN Graph Drawing by Force-directed Placement p36.pdf
│ ├Godiya Rapid Multipole Graph Drawing on the GPU p12.pdf
│ ├Harel Graph Drawing by High-Dimensional Embedding p20.pdf
│ ├Kant Algorithms for Drawing Planar Graphs p237.pdf
│ ├Klau Quasi–Orthogonal Drawing of Planar Graphs p15.pdf
│ ├Krug New Approaches on Octilinear Graph Drawing p165.pdf
│ ├M?kinen GENETIC ALGORITHMS FOR DRAWING BIPARTITE GRAPHS p15.pdf
│ ├Radwan Hybrid GA for Straight-Line Drawings of Level Clustered Planar Graphs p7.pdf
│ ├Ruegg Using One-Dimensional Compaction for Smaller Graph Drawings p23.pdf
│ ├Samaranayake Force Directed Graph Drawing Algorithms for Macro Cell Placement p6.pdf
│ ├Siebenhaller Orthogonal Graph Drawing with Constraints Algorithms and Applications p222.pdf
│ ├Sim Automatic Graph Drawing Algorithms p16.pdf
│ ├Tamassia Graph Drawing p10.pdf
│ └Wood Drawings of Graphs in Two and Three Dimensions p53.pdf
├<graph edintingZZZ>
│ ├Graphviz and Dynagraph – Static and.pdf
│ ├snoopy-pnnl-web.pdf
│ ├TALE A Tool for Approximate Large Graph.pdf
│ └Tools for Large Graph Mining.pdf
├<graph encoding>
│ ├Chen Graph Encoding and Transitive Closure Representation p3.pdf
│ ├Dagstuhl Graph encoding an overview p24.pdf
│ ├Das Succinct Encodings of Graph Isomorphism p17.pdf
│ ├Ionicioiu Encoding graphs into quantum states an axiomatic approach p33.pdf
│ ├Pouly A Modeling and Encoding Method for Relative Layout Generation and Optimization in Manufacturing p34.pdf
│ ├SCHIANO Structure and strategy in encoding simplified graphs p9.pdf
│ └Urbania KOGNAC Efficient Encoding of Large Knowledge Graphs p8.pdf
├<Graph Extractor>
│ ├Atkinson Accurate Call Graph Extraction of Programs with Function Pointers Using Type Signatures p10.pdf
│ └Vallerio Task Graph Extraction for Embedded System Synthesis p7.pdf
├<Graph Generation>
│ ├Ahmad A Technique for Reachability Graph Generation for the Petri Net Models of Parallel Processes p5.pdf
│ ├APPENDIX B GRAPH GENERATION AND COMPLEXITY MEASURES p8 .pdf
│ ├Ashish A Modular Approach to Random Task Graph Generation p7.pdf
│ ├Bader GTgraph A Synthetic Graph Generator Suite p4.pdf
│ ├Bailey Automatic Generation of Graph Models for Complex Networks by Genetic Programming p8.pdf
│ ├Cordeiro Random graph generation for scheduling simulations p10.pdf
│ ├Coxon Uniform Random Generation of Graphs with Graph Grammars p50.pdf
│ ├Cullum PERFORMANCE ANALYSIS OF AUTOMATED ATTACK GRAPH GENERATION SOFTWARE p159.pdf
│ ├dick98mar.pdf
│ ├ESTERLE Socio-Economic Vision Graph Generation and Handover in Distributed Smart Camera Networks p24.pdf
│ ├EVERETS ASSEMBLY LANGUAGE REPRESENTATION AND GRAPH GENERATION IN A PURE FUNCTIONAL PROGRAMMING LANGUAGE p108.pdf
│ ├Fernandez Minimal State Graph Generation p20.pdf
│ ├Ingols Practical Attack Graph Generation for Network Defense p10.pdf
│ ├Jeon TeGViz Distributed Tera-Scale Graph Generation and Visualization p4.pdf
│ ├Johnsonbau A Graph Generation Software Package p4.pdf
│ ├Kang An Efficient Generation of the Timed Reachability Graph for the Analysis of Real-Time Systems p23.pdf
│ ├Lampka MTBDD-based Activity-Local State Graph Generation p4.pdf
│ ├Lampka Symbolic Activity-Local State Graph Generation in the Context of Mobius p11.pdf
│ ├Leist Graph Generation on GPUs using Dynamic Memory Allocation p7.pdf
│ ├Leskovec Kronecker graph p37.pdf
│ ├Leskovec Realistic, Mathematically Tractable Graph Generation and Evolution, Using Kronecker Multiplication p12.pdf
│ ├Miyazaki Representative Graph Generation for Graph-Based Character Recognition p9.pdf
│ ├Namouz Comparison of Graph Generation Methods for Structural Complexity Based Assembly Time Estimation p28.pdf
│ ├Nobari Fast Random Graph Generation p12.pdf
│ ├Nobari Fast Random Graph Generation1 p12.pdf
│ ├Ou A Scalable Approach to Attack Graph Generation p10.pdf
│ ├Ryszka GraphTool - a new System of Graph Generation p5.pdf
│ ├Schluter Effects of Graph Generation for Unsupervised Non-Contextual Single Document Keyword Extraction p7.pdf
│ ├Sorensen Safe-Path Graph Generation for Path Planning in Urban Environments p6.pdf
│ ├Toma A Dependency Graph Generation Process for Client-side Web Applications p13.pdf
│ ├VanHorn A Random Graph Generator p6.PDF
│ ├Wardhana Automatic Generation of Enhanced Waypoint Graph for Volumetric Path Planning p6.pdf
│ ├Winlaw A Clustering Graph Generator p16.pdf
│ ├Ying Graph Generation with Prescribed Feature Constraints p12.pdf
│ └Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf
├<graph immersionsXXX>
├<Graph layout>
│ ├anoop On Some Graph Layout Problems and Solution Strategies p18.pdf
│ ├Buchsbaum Rectangular Layouts and Contact Graphs p25.pdf
│ ├BUCHSBAUM Rectangular Layouts and Contact Graphs p29.pdf
│ ├Claussen Implementing an Algorithm for Orthogonal Graph Layout p47.pdf
│ ├Diaz A survey on graph layout problems p22.pdf
│ ├Diaz A survey on graph layout problems p54.pdf
│ ├Dujmovic On Linear Layouts of Graphs p20.pdf
│ ├Dujmovic Track Layouts of Graphs p160.pdf
│ ├Fellows Graph Layout problems Parameterized by Vertex Cover p12.pdf
│ ├Leeuw Graph Layout Techniques and Multidimensional Data Analysis p31.pdf
│ ├SHIELDS AREA EFFICIENT LAYOUTS OF BINARY TREES ON ONE, TWO LAYERS p13.doc
│ └Sp?nemann On the Automatic Layout of Data Flow Diagrams p99.pdf
├<graph making>
│ ├Circle_graphs.pdf
│ └sudakov-making-bipartite.pdf
├<graph mapping>
│ └Bhatel Automated Mapping of Structured Communication Graphs onto Mesh Interconnects p17.pdf
├<graph matching>
│ ├000graph_matching.txt
│ ├Adamczewski Discrete Tabu Search for Graph Matching p9.pdf
│ ├Andrews Parallel Algorithms for Maximum Matching in Complements of Interval Graphs and Related Problems p31.pdf
│ ├Bunke Graph Matching Theoretical Foundations, Algorithms, and Applications p7.pdf
│ ├Carroll Matching RDF Graphs p17.pdf
│ └Duchenne A Tensor-Based Algorithm for High-Order Graph Matching p8.pdf
├<GRAPH MODELING>
│ ├Boonto Dynamics System and Modelling Linear Graph Modeling I p20.pdf
│ ├McBride SYSTEM ANALYSIS THROUGH BOND GRAPH MODELING p325.pdf
│ ├Mittelmann Graph Modeling for Quadratic Assignment Problems Associated with the Hypercube p15.pdf
│ ├Needham Graph Modeling Dos and Donts p96.pdf
│ └Rowell Linear Graph Modeling State Equation Formulation p38.pdf
├<graph packing>
│ ├Caro Packing GraphsThe packing problem solved p7.pdf
│ ├Deg-Seq-Packing-long.pdf
│ ├Goodman A Genetic Algorithm Approach to Compaction, Bin Packing, and Nesting Problems p73.pdf
│ ├Grotschel The Steiner Tree Packing Problem in VLSI Design p21.pdf
│ ├Iwaniec Algorithms for Packing Soft Blocks of Vlsi Systems p6.pdf
│ ├Jeong A branch-and-price algorithm for the Steiner tree packing problem p21.pdf
│ ├Kuhn AN ORE-TYPE THEOREM FOR PERFECT PACKINGS IN GRAPHS p23.pdf
│ ├Kuhn OPTIMAL PACKINGS OF HAMILTON CYCLES IN GRAPHS OF HIGH MINIMUM DEGREE p23.pdf
│ ├Kuhn PERFECT PACKINGS WITH COMPLETE GRAPHS MINUS AN EDGE p15.pdf
│ ├Lau An Approximate Max-Steiner-Tree-Packing Min-Steiner-Cut Theorem p10.pdf
│ ├Martin Packing Paths and Steiner Trees Routing of Electronic Circuits p20.pdf
│ ├Pantel Graph Packing Problems p86.pdf
│ ├Sausen Models for the Steiner Tree Packing Problem p85.pdf
│ └Srinivasan New Approaches to Covering and Packing Problems p10.pdf
├<Graph ProcessingXXX>
├<GRAPH REALIZATION>
│ └Alfakih The Graph Realization Problem via Semi-Definite Programming p70.pdf
├<GRAPH REPRESENTATION>
│ ├8 Graph Representations.pdf
│ ├Basel Elementary Graph Algorithms PART-1 p34.pdf
│ ├Cao Deep Neural Networks for Learning Graph Representations p8.pdf
│ ├Depree Graph Operations And Representation p34.pdf
│ ├Elite Graph Representation p27.pdf
│ ├Gotshalks Graph Representation p12.pdf
│ ├Grama Graph Algorithms p65.pdf
│ ├Gross Section 8.3 Graph Representations and Graph Isomorphism p11.pdf
│ ├Iglesias Graph representation of documents content and its suitability for text mining tasks p72.pdf
│ ├Joy A Standard for a Graph Representation for Functional Programs p8.pdf
│ ├Kobler Interval graph representation with given interval and intersection lengths p10.pdf
│ ├Lenharth Graph Representations p5.pdf
│ ├Lovasz Geometric Representations of Graphs p213.pdf
│ ├Madduri Compact Graph Representations and Parallel Connectivity Algorithms for Massive Dynamic Network Analysis p11.pdf
│ ├Pahikkala Graph Kernels versus Graph Representations a Case Study in Parse Ranking p8.pdf
│ ├Schwarz Graph Representations and Algorithms p164.pdf
│ ├Shaia Graph theory representations of engineering systems and their embedded knowledge p13.pdf
│ ├Sommer 8.1 Graph Representation in Memory p14.pdf
│ ├Stratis Graph Representation of Concurrent Programs in Cpp p50.pdf
│ ├Tangwongsan Lecture 7 Graph Representations Sets and Tables p11.pdf
│ ├Trinks Graph Polynomials and Their Representations p122.pdf
│ └Yin W-graph representations for Coxeter groups and Hecke algebras p101.pdf
├<graph sampling>
├<graph transformZZZ>
├<Graph visualization>
│ ├Dujmovic Track Layouts of Graphs p160.pdf
│ ├Gansner Interactive Visualization of Streaming Text Data with Dynamic Maps p25.pdf
│ ├Gansner Visualizing Streaming Text Data with Dynamic Graphs and Maps p12.pdf
│ ├Ham Interactive Visualization of Small World Graphs p8.pdf
│ ├Herman Graph Visualization and Navigation in Information Visualization a Survey p21.pdf
│ ├Herman Graph Visualization and Navigation in Information Visualization a Survey p37.ppt
│ ├Kratochv?l GraDR Graph Drawings and Representations p44.pdf
│ ├Kumar Visualization of Clustered Directed Acyclic Graphs with Node Interleaving p6.pdf
│ ├Langevin Multi-Scale Community Visualization of Massive Graph Data p4.pdf
│ ├Marshall An Object-Oriented Design for Graph Visualization p16.pdf
│ ├Tarawneh A General Introduction To Graph Visualization Techniques p14.pdf
│ ├Vogt An open source browser-based software tool for graph drawing and visualization p171.pdf
│ └Yang PIWI Visually Exploring Graphs Based on Their Community Structure p14.pdf
├<temp>
│ ├Ada On Bus Graph Realizability p4.pdf
│ ├Alon Optimal Universal Graphs with Deterministic Embedding p9.pdf
│ ├Bilski Optimum embedding of complete graphs in books p8.pdf
│ ├Brass On Simultaneous Planar Graph Embeddings p12.pdf
│ ├Chen Directed Graph Embedding p6.pdf
│ ├Cygan Tight Lower Bounds on Graph Embedding Problems p23.pdf
│ ├Dolev On Linear Area Embedding of Planar Graphs p24.pdf
│ ├DUNCAN The Geometric Thickness of Low Degree Graphs p12.pdf
│ ├Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134.pdf
│ ├McClintock Extremal Graph Theory for Book-Embeddings p64.pdf
│ ├Overbay Genetic Algorithms and Book Embeddings A Dual Layered Approach p8.pdf
│ ├Seventh Cologne-Twente Workshop on Graphs and Combinatorial Optimization p204.pdf
│ ├Tamassia On-line Planar Graph Embedding p39.pdf
│ ├Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf
│ └Ye Entropic Graph Embedding via Multivariate Degree Distributions p11.pdf
├<topological_graph_embedding>
└<topological_graph_theory>
├000Topological graph theory.txt
├Ackerman On Grids in Topological Graphs p14.pdf
├Archdeacon Topological Graph Theory a Survey p67.pdf
├Archdeacon Topological Graph Theory a Survey p67.txt
├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front p18.pdf
├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front333 p18.pdf
├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228.pdf
├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228jjj.pdf
├Chapter 5 Topological Graph Theory p32.pdf
├Chapter III Adopting Topological Graph Theory to Traffic Management Problem p18.pdf
├Childs Topological Graph Theory and Graphs of Positive Combinatorial Curvature p54.pdf
├Craft Topological Graph Theory.pptx
├Hutchinson Some Conjectures in Chromatic Topological Graph Theory p19.pdf
├KNILL CLASSICAL MATHEMATICAL STRUCTURES WITHIN TOPOLOGICAL GRAPH THEORY p28.pdf
├Mohar Topological graph theory and crossing numbers p18.pdf
├Rooney Topological Graph Theory Lecture 15-16 Cycles of Embedded Graphs p6.pdf
├Sawollek A Survey of Embedding Problems in Topological Graph Theory.docx
├Topological graph theory.docx
└Vella A FUNDAMENTALLY TOPOLOGICAL PERSPECTIVE ON GRAPH THEORY p263.pdf


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Graph Laplacian

Anand The Shannon and the Von Neumann entropy of random networks with heterogeneous expected degree p10

graph Laplacian
Laplacian of a graph
(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Hu Spectral Descriptors for Graph Matching p15

Graph Laplacian?????????????????
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Graph Laplacian

Anand The Shannon and the Von Neumann entropy of random networks with heterogeneous expected degree p10

graph Laplacian
Laplacian of a graph
(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

(de) Beaudrap Interpreting the von Neumann entropy of graph Laplacians, and coentropic graphs p7

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Hu Spectral Descriptors for Graph Matching p15

Graph Laplacian?????????????????
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

laplacian of graph

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

laplacian of a graph

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

laplacian matrices of graphs

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Laplace operators on graphs


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Embedding Techniques
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Choi’s Triad Technique

[Britt2014]

Choi’s Triad Technique Able to Embed on 128-Qubit Processor
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Incremental construction

[Britt2014]
http://arxiv.org/pdf/1001.3116v2.pdf
http://arxiv.org/pdf/1001.3116v2.pdf
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?

Choi Minor-embedding in adiabatic quantum computation II Minor-universal graph design p10

Dahl Programming with D-Wave Map Coloring Problem p12
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Embedding Characters

Embedding Limits

[Britt2014]
D-Wave Embedding Limits

D-Wave Embedding Limits

??? Logical Qubit is Not the Same as a Physical Qubit
Can Always Embed N Logical Qubits onto N2 Physical Qubits
This is Not a Tight Upper-bound, Even for Complete Graph
Choi’s Triad Technique Able to Embed on 128-Qubit Processor

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Applications

Health

How the Traveling Salesman Problem can help streamline kidney transplants

http://theweek.com/articles/532710/how-traveling-salesman-problem-help-streamline-kidney-transplants

Nathan Collins
(Christopher Furlong/Getty Images)
January 26, 2015

The growing list of people in need of a new kidney might get a little shorter, thanks to an unlikely source: that old, formidable puzzle in mathematics known as The Traveling Salesman Problem. That puzzle, and the methods used to solve it, have inspired an algorithm that can help pinpoint better matches, researchers report.

Kidney transplants, first performed in the 1950s, depend on either a living relative or the very recently deceased. Getting a kidney from a living donor is the better of the two options, but tracking down a viable donor among one's friends and relatives isn't always possible. Some simply don't want to donate, or maybe aren't healthy enough for the surgery. Others may be willing and able, but antibodies in their blood don't match the patient's well enough — a strong indicator a recipient's immune system will reject the donated kidney.

To solve that problem, doctors began looking for transplant cycles and chains. The latter begins with a living person donating a kidney to another, often a stranger. A friend or relative connected to that recipient then donates to another stranger, and the process continues. (A cycle is just a chain that ends with a recipient connected to the first donor.)? There are now registries set up specifically to facilitate cycles and chains, but actually finding the best chains — those that seek out the most compatible donor-recipient matches, while taking into account factors like how sick someone is or how long they've waited for a new kidney — remains a challenging technical problem.

Researchers from a variety of disciplines have been grappling with this challenge for a while, but haven't had much luck in finding any particularly great solutions. To seek a better one, Ross Anderson, a recent graduate of MIT's Operations Research Center, led a team that zeroed in on the Traveling Salesman Problem as inspiration. The classic problem is for a salesperson to find the shortest route that visits each city on a list just once — not quite the kidney exchange problem. But another version, the prize-collecting traveling salesman problem, is closer. In that version, the salesperson doesn't have to make it to each city, but there's a reward for each city he or she does get to.

That, Anderson and company reasoned, was a lot like the kidney transplant chain problem, in that one wants to find the longest possible chain of kidney patient-donor pairs without the impractical requirement that everyone who needs a kidney gets one on the first go. From there, the team adapted a known algorithm for solving the PC-TSP to the kidney exchange problem, able to obtain the longest possible transplant chains in real data from two kidney exchange programs, something previous approaches had been unable to do reliably, using just a desktop personal computer.

Along with another method the team developed, the new algorithm is already in use in kidney exchange programs, "including Methodist Specialty and Transplant Hospital in San Antonio, Texas, and the Northwestern University Medical Center in Chicago," the authors write.

Finding long chains in kidney exchange using the traveling salesman problem

http://www.pnas.org/content/112/3/663.abstract?sid=d3996b20-0902-4b1c-a7ff-6da32719a9fd


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commbinatorial optimization for delivery of goods

automatic planning and scheduling

vehicle routing and order scheduling

dynamic scheduling

distributed planning and scheduling management techniques

transportation logistics

transportation scheduling

Constraint Satisfaction for Scheduling

operations research

automating and optimizing their dispatching process

The Pick up and Delivery Problem With Time Windows (PDPTW)

The PDPTW problem consists of computing the optimal set of routes for a fleet of vehicles in order to satisfy a collection of transportation orders while satisfying the time windows at client locations.
The goal of the PDPTW is to provide feasible schedules, which satisfy the time window constraints, for each vehicle in order to deliver to a set of customers with known demands on minimum-cost vehicle routes.
Bolhaar Strategic decisions in truck routing for a retail chain p90

??????????????????????

[Caric2008]

Caric Vehnicle Routing Problem p152

Tonci Caric and Hrvoje Gold

45
?atay AN ANT COLONY OPTIMIZATION APPROACH FOR THE CAPACITATED VEHICLE ROUTING PROBLEM WITH SIMULTANEOUS DELIVERY AND PICK-UP p8
Cracknell Simulating and Optimising a Delivery Network of Autonomous Courier Agents p151

[DAVULIS2010]

DAVULIS MODELLING AND OPTIMIZATION OF TRANSPORTATION COSTS p12

ISSN 1822-8011 (print)
ISSN 1822-8038 (online)
INTELEKTIN? EKONOMIKA
INTELLECTUAL ECONOMICS
2010, No. 1(7), p. 18–29
MODELLING AND OPTIMIZATION OF TRANSPORTATION COSTS
Gediminas DAVULIS
Mykolas Romeris University
Ateities str. 20, LT-08303 Vilnius, Lithuania
E-mail: geddav@mruni.lt
Linas ?AD?IUS
Mykolas Romeris University
Ateities str. 20, LT-08303 Vilnius, Lithuania
E-mail: linassad@mruni.lt

[Dekker2012]

Dekker Operations Research for green logistics – An overview of aspects, issues, contributions and challenges p9

European Journal of Operational Research 219 (2012) 671–679
Rommert Dekker
Eitzen A Multi-Objective Two-Echelon Vehicle Routing Problem. An Urban Goods Movement Approach for Smart City Logistics p10

[Gambardellaa2003]
Gambardellaa Ant Colony Optimization for vehicle routing in advanced logistics systems p6
Luca Maria Gambardellaa

Grotschel Lectures on Combinatorial Optimization Modelling Transportation Problems p4

Prof. Dr. Martin Grotschel / Luis M. Torres
Gschwind Contributions to Exact Approaches in Combinatorial Optimization p171
Gruler A Simulation-Optimization Approach for the Two- Echelon Location Routing Problem Arising in the Creation of Urban Consolidation Centres p10

[Kindervater1995]

Kindervater Vehicle Routing 2 Handling Side Constraints p21

G.A.P. Kindervater
Erasmus University
P.O. Box 1738, 3000 DR Rotterdam
The Netherlands
M.W.P. Savelsbergh
School of Industrial and Systems Engineering
Georgia Institute of Technology
Atlanta, GA 30332-0205
U.S.A

strategic, tactical and operational planning

effective and efficient distribution management

physical distribution management

traveling salesman problem (TSP)

vehicle routing and scheduling problems

routing of vehicles

vehicle routing problem (VRP)

scheduling of vehicles

pickup and delivery problem (PDP)

dial-a-ride problem (DARP)

=============================

k-exchange algorithms

  • edge-exchange algorithms
    • edge-exchange neighborhoods for a single route and
    • edge-exchange neighborhoods for multiple routes

=============================

variants of local search, such as

  • simulated annealing and
  • tabu search

=============================

multiple routes structure

=============================

side constraints, such as

  • precedence relations between vertices,
  • collections or deliveries at vertices, and
  • time windows at vertices

=============================

parallel computations
Leech DELIVERING THE GOODS p31

[Lu2016]
Lu Ant Colony Optimization Solutions for Logistic Route Planning with Pick-up and Delivery p6
Eric Hsueh-Chan Lu*, Ya-Wen Yang and Zeal Li-Tse Su
Department of Geomatics, National Cheng Kung University
No.1, University Rd., Tainan City 701, Taiwan (R.O.C.)
*Correspondence: luhc@mail.ncku.edu.tw; v47244724@gmail.com; zeal0820@gmail.com

[Neagu2006]

Neagu Solving Distributed Delivery Problems with Agent-Based Technologies and Constraint Satisfaction Techniques p2

Nicoleta Neagu, Klaus Dorer, Monique Calisti
Whitestein Technologies AG.
Pestalozzistrasse 24
8032 Zurich, Switzerland
nne,kdo,mca@whitestein.com

PDPTW problem - The Pick up and Delivery Problem With Time Windows (PDPTW)

agent based system designed to solve the PDPTW problem using constraint satisfaction techniques

multi-agent technologies

Multi-Agent Systems for the Pick up and Delivery Problem (PDP)

Pellonpera Ant colony optimization and the vehicle routing problem p57

[Putri2017]

Putri OPTIMIZATION OF VEHICLE ROUTING PROBLEM WITH TIMES WINDOWS, TOCHASTIC DEMAND AND CONSTRAINED CAPACITY (VRPTW-SDCC) USING CROSS ENTROPY p4

Sci.Int.(Lahore),29(3),489-492,2017 ISSN: 1013-5316; CODEN: SINTE 8 489 May-June

Pusparani Asri Sugiyarto Putri, Iwan Aang Soenandi, Budi Marpaung
Department of Industrial Engineering, Krida Wacana Christian University, Jakarta, Indonesia

[Ropke2006]

Ropke A unified heuristic for a large class of Vehicle Routing Problems with Backhauls p36

Sbihi Combinatorial optimization and Green Logistics p19

Veinott Lectures in Supply-Chain Optimization p261


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Contests

8th DIMACS Implementation Challenge: The Traveling Salesman Problem

http://dimacs.rutgers.edu/Challenges/TSP/

http://dimacs.rutgers.edu/Challenges/TSP/about.html

http://dimacs.rutgers.edu/Challenges/TSP/download.html


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Introduction

http://heuristicswiki.wikispaces.com/Travelling+salesman+problem

http://mortada.net/the-traveling-tesla-salesman.html

http://www.mathworks.com/help/optim/ug/travelling-salesman-problem.html

https://www8.cs.umu.se/kurser/TDBAfl/VT06/algorithms/BOOK/BOOK3/NODE93.HTM

http://solutions.wolterskluwer.com/blog/2015/01/traveling-salesman-problem/

http://scitation.aip.org/content/aip/magazine/physicstoday/news/news-picks/virtulgooprovidessolutionstotrvelingslesmnproblem-a-news-pick-post

http://www.programming-algorithms.net/article/48915/Travelling-salesman

http://www.psychicorigami.com/2007/04/17/tackling-the-travelling-salesman-problem-part-one/

http://www.sciencebuzz.org/topics/optimum-outcomes-can-you-solve-traveling-salesman-problem

https://tech.zalando.com/blog/defeating-the-travelling-salesman-problem-for-warehouse-logistics/

http://content.iospress.com/articles/journal-of-intelligent-and-fuzzy-systems/ifs1394

http://www.wired.com/2013/01/traveling-salesman-problem/

https://developers.google.com/optimization/routing/tsp?hl=en+&cd=39&hl=en&ct=clnk&gl=usclnk&gl%3Dus

https://www.seas.gwu.edu/~simhaweb/champalg/tsp/tsp.html

http://www.personal.kent.edu/~rmuhamma/Algorithms/MyAlgorithms/AproxAlgor/TSP/tsp.htm

http://www.nomachetejuggling.com/2012/09/14/traveling-salesman-the-most-misunderstood-problem/

http://ai-depot.com/Articles/51/TSP.html
https://www.quora.com/Computational-Complexity-Theory/Is-the-traveling-salesman-problem-solvable

https://www.periscopedata.com/blog/postgres-recursive-cte.html

http://c2.com/cgi/wiki?TravelingSalesmanProblem

https://plus.maths.org/content/travelling-salesman+&cd=30&hl=en&ct=clnk&gl=us

https://plus.maths.org/content/travelling-salesman

https://en.wikipedia.org/wiki/Travelling_salesman_problem

http://www.oberlin.edu/math/faculty/bosch/tspart-page.html
http://www.obitko.com/tutorials/genetic-algorithms/tsp-example.php

http://www.rational-action.com/tag/traveling-salesman-problem/

http://www.tnooz.com/article/aerospike-airline-availability-database/

http://xlinux.nist.gov/dads/HTML/travelingSalesman.html

http://www.cut-the-knot.org/Curriculum/Combinatorics/TSP.shtml

https://www.cs.arizona.edu/icon/oddsends/travels/travels.htm

http://www.cedarville.edu/personal/JAS/i2m_jas/travsale.htm

http://study.com/academy/lesson/the-traveling-salesman-problem-in-computation.html

https://people.inf.ethz.ch/gonnet/papers/MAScoring/node6.html

http://mathforum.org/library/drmath/view/52267.html

http://kottke.org/13/09/the-unhappy-traveling-salesman-problem

http://judge.u-aizu.ac.jp/onlinejudge/description.jsp?id=DPL_2_A

http://jgap.sourceforge.net/doc/salesman/TravellingSalesman.html

http://flowingdata.com/2014/10/01/a-simulation-of-the-traveling-salesman-problem/

https://developers.google.com/optimization/routing/tsp?hl=en

http://delphiforfun.org/programs/traveling_salesman.htm

https://researchspace.auckland.ac.nz/handle/2292/20766

http://lemon.cs.elte.hu/pub/doc/1.3.1/a00618.html

https://www.kidscodecs.com/traveling-salesman-problem/

https://www-m9.ma.tum.de/games/tsp-game/index_en.html

http://sites.cgu.edu/percusa/research/tsp/

http://paal.mimuw.edu.pl/docs/twoopt.html

http://jov.arvojournals.org/article.aspx?articleid=2135427

http://deepblue.lib.umich.edu/handle/2027.42/45818

http://www.encyclopedia.com/doc/1O11-travelingsalesmanproblem.html

https://math.uc.edu/~brycw/probab/books/smplbook/node16.html

https://homepages.rpi.edu/~mitchj/handouts/lp/node6.html

http://www.nirarebakun.com/graph/enotsp.html

Sales and Chips

http://www.ams.org/samplings/feature-column/fcarc-tsp

Computing The Really Optimal Tour Across The USA On The Cloud With Python

http://www.math.uwaterloo.ca/tsp/usa50/road.html
http://www.citylab.com/tech/2014/09/an-app-that-solves-the-famed-traveling-salesman-problem/380409/

https://www.ibm.com/developerworks/community/blogs/jfp/entry/computing_the_really_optimal_tour_acrosss_the_usa_on_the_cloud_with_python?lang=en

The Ultimate American Road Trip

http://www.optaplanner.org/blog/2015/03/20/3BugsInTheUltimateAmericanRoadTrip.html

Computing the optimal road trip across the U.S.

http://www.randalolson.com/2015/03/08/computing-the-optimal-road-trip-across-the-u-s/

http://nbviewer.ipython.org/github/rhiever/Data-Analysis-and-Machine-Learning-Projects/blob/master/optimal-road-trip/Computing%20the%20optimal%20road%20trip%20across%20the%20U.S..ipynb

Solving TSP with Python, NEOS, Concorde, and CPLEX

https://www.ibm.com/developerworks/community/blogs/jfp/resource/tsp_nb.html?lang=en

NP-hardness

It is NPhard [Garey & Johnson, 1979]
the TSP is an NP-hard problem (Garey & Johnson, 1979)

proven NP-hard by Karp in 1972

TSP is known as a classical NP-complete problem, which has extremely large search spaces and is very difficult to solve (Louis & Gong, 2000).


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Libraries ?

TSPLIB

TSPLIB – benchmark library for TSP

TSPLIB (Reinelt (1991a, 1991b))

TSPLIB is a library of sample instances for the TSP (and related problems) from various sources and of various types.

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/sop/
http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/vrp/
http://www.iwr.uni-heidelberg.de/groups/comopt/software/TSPLIB95/atsp/
http://www.iwr.uni-heidelberg.de/groups/comopt/software/TSPLIB95/hcp/
http://www.iwr.uni-heidelberg.de/groups/comopt/software/TSPLIB95/tsp/
http://www.iwr.uni-heidelberg.de/groups/comopt/software/TSPLIB95/XML-TSPLIB/instances/
http://www.iwr.uni-heidelberg.de/groups/comopt/software/TSPLIB95/XML-TSPLIB/Sample/

Address

??? Gerhard Reinelt
Universit?t Heidelberg
Institut für Informatik
Im Neuenheimer Feld 368
D - 69120 Heidelberg
Germany
tel: ++49/6221/54-5749
fax: ++49/6221/54-5750
e-mail: Gerhard.Reinelt{at}informatik.uni-heidelberg.de


Untitled Document

Literature

Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

bee colony optimization

DNA computing

electromagnetism-like optimization

Evolutionary computation

neural networks

time adaptive self-organizing maps

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42

covering salesman problem (CSP)

Flying Sidekick Traveling Salesman Problem

TSP with Drone (TSP-D)

truck and trailer routing problem (TTRP)

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

Angel A dynasearch neighborhood for the bicriteria traveling salesman problem p4

bicriteria traveling salesman problem

Dynasearch neighborhood

ANGINIOL Self-Organizing Feature Maps and the Travelling Salesman Problem p5

Euclidean Travelling Salesman Problem

self-organizing feature maps

elastic net method

tea-trade model

Antosiewicz Choice of best possible metaheuristic algorithm for the travelling salesman problem with limited computational time: quality, uncertainty and speed p10

3

harmony search
quantum annealing
tabu search

greedy 2-opt interchange algorithm

Applegate, D.L., Bixby, R.E., Chvatal, V., Cook, W.J.: The Traveling Salesman Problem - A Computational Study, Princeton Series in Applied Mathematics, 2006
http://www.amazon.com/Traveling-Salesman-Problem-Computational-Mathematics/dp/0691129932/
http://www.amazon.com/The-Traveling-Salesman-Problem-Computational/dp/0691129932
http://www.amazon.ca/The-Traveling-Salesman-Problem-Computational/dp/0691129932
http://www.akademika.no/traveling-salesman-problem/william-j-cook/david-l-applegate/robert-e-bixby/9780691129938

appel An Alternate Graph Representation for the Tiger Compiler

ASCHEUER Solving the Asymmetric Travelling Salesman Problem with Time Windows by Branch-and-Cut p35

Asymmetric Travelling Salesman Problem with Time Windows(ATSP-TW)

Branch-and-Cut

Balas Linear Time Dynamic-Programming Algorithms for New Classes of Restricted TSPs A Computational Study p33

Restricted TSPs

TSPs with time windows (TSPTW)

Traveling Salesman Problem with Target Times

Linear Time Dynamic-Programming Algorithms

Local Search

Bar-Yehuda On Approximating A Geometric Prize-Collecting Traveling Salesman Problem With Time Windows p12

Geometric Prize-Collecting Traveling Salesman Problem with Time Windows

Prize-Collecting Traveling Salesman Problem with time-windows

Bartal The Traveling Salesman Problem Low-dimensionality Implies a Polynomial Time Approximation Scheme p10

Bartal The Traveling Salesman Problem Low-dimensionality Implies a Polynomial Time Approximation Scheme p10

Bassetto The Single-Double Balanced Traveling Salesman Problem p16

period traveling salesman problem

Period TSP (PTSP)

Single-Double Balanced Traveling Salesman Problem

Basu Tabu Search Implementation on Traveling Salesman Problem and Its Variations: A Literature Survey p11

American Journal of Operations Research, 2012, 2, 163-173
http://dx.doi.org/10.4236/ajor.2012.22019 Published Online June 2012 (http://www.SciRP.org/journal/ajor)

Vehicle Routing Problem

approximate methods

heuristics

metaheuristic

  • Tabu search
  • local search
  • simulated annealing
  • genetic algorithms

Biron The Traveling Salesman Problem: Deceptivley Easy to State Notoriously Hard to Solve p31

Blelloch Lecture 13 — Shortest Weighted Paths p8

Brabec Procedural Code Representation in a Flow Graph p12

Braun FIRM A Graph-Based Intermediate Representation p8

Brezina Solving the Travelling Salesman Problem Using the Ant Colony Optimization p5

evolutionary techniques

met heuristics

ant colony optimization

Brisaboa K2trees for Compact Web Graph Representation p10

Bryant Genetic Algorithms and the Traveling Salesman Problem p34

Kylie Bryant
Arthur Benjamin, Advisor
Second Reader: (Lisette de Pillis)
December 2000
Department of Mathematics

The traveling salesman problem is NP-hard

Genetic algorithms are an evolutionary technique

  1. crossover operators
  2. mutation operators
  3. operators that use heuristic information of the graph
  4. operators that use a matrix representation of the graph

btechsmartclass Graph Representations

Budinich A Neural Network for the Travelling Salesman Problem with a Well Behaved Energy Function p8
Salesman Problem with a Well Behaved
Energy Function
Marco Budinich and Barbara Rosario
Dipartimento di Fisica & INFN, Via Valerio 2, 34127 Trieste, Italy

Neural Network
Self Organizing Feature Map (SOFM)

Buriol Web Graph representation and compression

burkardt GRAPH_REPRESENTATION

Cela The x-and-y-axes travelling salesman problem p3
x-and-y-axes travelling salesman problem

CERNY Thermodynamical Approach to the Traveling Salesman Problem: An Efficient Simulation Algorithm I p11
Thermodynamical Approach

Chen EAGER Define and Construct an Enhanced Graph Representation for Multiscale Vector Field Data Summarization

Codish Breaking Symmetries in Graph Representation p7

Costantini Comparing different graph representations of logic programs under the Answer Set semantics p6

Bill Cook of Georgia Tech
“In Pursuit of the Traveling Salesman” Mathematics at the Limits of Computation
http://mat.tepper.cmu.edu/blog/?p=1603
http://www.amazon.com/Pursuit-Traveling-Salesman-Mathematics-Computation/dp/0691163529/

Cormen Representing graphs

cornell Lecture 21 Graph Representations and Traversals

Dantzig Solution of a Large-Scale Traveling-Salesman Problem p22
cutting-plane method

D'Autilia Shaping ideal cities: the graph representation of the urban utopia p17

Demez Combinatorial Optimization: Solution Methods of Traveling Salesman Problem p87
BRANCH AND BOUND ALGORITHM

Dong Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance p67

Dorigo Ant colonies for the traveling salesman problem p10
TR/IRIDIA/1996-3
Université Libre de Bruxelles
Belgium
Marco Dorigo
IRIDIA, Université Libre de Bruxelles, Avenue Franklin Roosevelt 50, CP 194/6, 1050
Bruxelles, Belgium
mdorigo@ulb.ac.be, http://iridia.ulb.ac.be/dorigo/dorigo.html
Luca Maria Gambardella
IDSIA, Corso Elvezia 36, 6900 Lugano, Switzerland
luca@idsia.ch, http://www.idsia.ch/~luca

Dornberger Solving Optimization Problems by Metaheu-ristics Using the Open Opal Framework - Integration of Travelling Salesman Problem and Selected Solvers p20

???????????????????

Dumitrescu The Traveling Salesman Problem with Pickup and Delivery Polyhedral Results and a Branch-and-Cut Algorithm p31

3
Traveling Salesman Problem with Pickup and Delivery
Polyhedral Results
Branch-and-Cut Algorithm

Precedence-Constrained TSP

TSP with backhauls

Du Lecture 3 Graph Representation for Regular Expressions p26

Easton Solving the Traveling Tournament Problem A Combined Integer Programming and Constraint Programming Approach p10
Combined Integer Programming and Constraint Programming Approach

Egyhazy On implementing graph representation p23

Gaillarda Graph representation of synonymy and translation resources for cross-linguistic modelisation of meaning p12

Gharan A Randomized Rounding Approach to the Traveling Salesman Problem p65
Randomized Rounding Approach

Gkirtzou The Pyramid Quantized Weisfeiler-Lehman Graph Representation p17

Goldengorin How To Make a Greedy Heuristic for the Asymmetric Traveling
Salesman Problem Competitive p16

okokok
Greco Travelling Salesman Problem p212
2008

Symmetric Circulant Traveling Salesman Problem

2-opt
3-opt
ACS (Ant Colony System)
ACS (Ant Colony System)-3-opt
ant-cycle
ant-density models
ant-quantity
Ant Systems
Artificial Immune Systems (AIS)
Bee Colony Optimization
branch and bound
COA (Chaotic Optimization Algorithm)
Civilization and Society (CS) algorithm
cutting planes
Discrete particle swarm optimization algorithm
DNA Computing
Electromagnetism-like Mechanisms (EM)
Evolutionary Computation
Evolutionary programming
Evolutionary strategies
GI3 (Generalized Initilialization, Insertion, and Improvement)
genetic algorithm
immune genetic algorithm (IGA)
Genetic Local Search (GLS)
genetic programming
greedy principles
I3 heuristic farthest-insertion, nearest-insertion, and cheapest-insertion heuristics
Intelligent Water Drops algorithm
Inver-over operator
K-OPT
Markov chain
mDPSO hybrid DPSO algorithm with both local search improvement heuristics
Mimetic Algorithm (MA) or Lamarckian Evolutionary Algorithm
nearest neighbour
mrOXGA Silberholz & Golden genetic algorithm
NEH heuristic
Neural Networks
Recurrent Neural Network
Transiently Chaotic Neural Networks
Particle Swarm Optimization
Priority-Based GLS (PB-GLS)
Random key genetic algorithm (RKGA)
Shuffled Frog Leaping (SFL)
Simulated Annealing
spanning tree
tabu search
Time Adaptive Self-Organizing Maps
transposition expression

GUTIN THE TRAVELING SALESMAN PROBLEM AND ITS VARIATIONS p40
EXPONENTIAL NEIGHBORHOODS
DOMINATION ANALYSIS

G. Gutin (Editor), A.P. Punnen (Editor)
The Traveling Salesman Problem and Its Variations (Combinatorial Optimization) Paperback – May 18, 2007
by G. Gutin (Editor), A.P. Punnen (Editor)

http://www.amazon.com/Traveling-Salesman-Variations-Combinatorial-Optimization/dp/0387444599
http://www.realgroovy.co.nz/Product/3596309/Traveling_Salesman_Problem_and_Its_Variations

hackerearth Graph Representation

Hahsler TSP – Infrastructure for the Traveling Salesperson Problem p21

Haque Improving the Solution of Traveling Salesman Problem Using Genetic, Memetic Algorithm and Edge assembly Crossover p4

Heap Graph representation

Hedstrom Graph representation

Heissan Some Results on Graph Representations and Graph Colorings p60

Helvig The moving-target traveling salesman problem p22
moving-target traveling salesman problem

Hidane Nonlinear Multilayered Representation of Graph-Signals p25

Hoffman Traveling salesman problem p9

Isaacs Algorithms for the Traveling Salesman Problem with Neighborhoods Involving a Dubins Vehicle p6

Ji The Traveling Salesman and the Quadratic Assignment Problems: Integration Modeling and Genetic Algorithm p8
Ping Ji* William Ho

genetic algorithm (GA)

Johnson The Traveling Salesman Problem A Case Study in Local Optimization p103

Double Minimum Spanning Tree
local search
Nearest Insertion
Nearest Addition
successive augmentation heuristics
tour construction heuristic
four tour construction heuristics

  1. Nearest Neighbor
  2. Greedy
  3. Clarke-Wright / Clarke-Wright savings heuristic
  4. Christofides / Christofides heuristic

Jones Computation of the Travelling Salesman Problem by a Shrinking Blob p27
Shrinking Blob Method

JONES THE TRAVELING SALESMAN PROBLEM AND HARMONIC ANALYSIS p9
HARMONIC ANALYSIS

Jozefowiez Multi-objective Meta-heuristics for the Traveling Salesman Problem with Profits p19
Multi-objective Meta-heuristics

okokok
Junger THE TRAVELING SALESMAN PROBLEM p117
1994

bottleneck traveling salesman problem
graphical traveling salesman problem
multisalesmen problem
rural postman problem

proven NP-hard by Karp in 1972

branch and bound
branch and cut
Construction heuristics
Geometric heuristics
Heuristics
Insertion heuristics
Lagrangean relaxation
Lin-Kernighan type methods
linear programming
Nearest neighbor heuristics
polyhedral cutting plane methods
simulated annealing

TSPLIB (Reinelt (1991a, 1991b))

Kannan Implicit Representation of Graphs p11

Kanda Using Meta-learning to Classify Traveling Salesman Problems p6

Kang Benchmarking Algorithms for Dynamic Travelling Salesman Problems p6
Dynamic Travelling Salesman Problems
Benchmarking Algorithms

K?bler Interval graph representation with given interval and intersection lengths p11

K?bler Interval Graph Representation with Given Interval and Intersection Lengths p13

Kumar Assignment and Travelling Salesman Problems with Coefficients as LR Fuzzy Parameters p16

Laporte The Traveling Salesman Problem An overview of exact and approximate algorithms p17

E. L. Lawler (Author), Jan Karel Lenstra (Author), A. H. G. Rinnooy Kan (Author)
The Traveling Salesman Problem: A Guided Tour of Combinatorial Optimization 1st Edition
by E. L. Lawler (Author), Jan Karel Lenstra (Author), A. H. G. Rinnooy Kan (Author),

http://www.amazon.com/The-Traveling-Salesman-Problem-Combinatorial/dp/0471904139
http://www.amazon.com/The-Traveling-Salesman-Problem-Combinatorial/dp/0471904139

http://www.amazon.co.uk/Traveling-Salesman-Problem-Combinatorial-Optimization/dp/0471904139

Letchford Compact Formulations of the Steiner Traveling Salesman Problem and Related Problems p28
Steiner Traveling Salesman Problem

Letchford Mathematical Programming Approaches to the Traveling Salesman Problem p12
Polyhedral Theory

Li Ant Colony Optimization for the Traveling Salesman Problem Based on Ants with Memory p6
Lokar Traveling salesman problem p6.doc

Lust The Multiobjective Traveling Salesman Problem: A Survey and a New Approach p24
Multiobjective Traveling Salesman Problem

Madduri Scaling up graph algorithms on emerging multicore systems p22

Maiya Visually Pleasing Graph Representation Using GraphDraw

manchester Graph Representation and Traversal

Mandziuk Solving the Travelling Salesman Problem with a Hopfield - type neural network p18
Hopfield - type neural network

okokok
Maredia History, Analysis, and Implementation of Traveling Salesman Problem(TSP) and Related Problems p47
Anne Maredia
Spring 2010

Matas The color adjacencyf graph p18

okokok
Mattsson The Asymmetric Traveling Salesman Problem p64

Monnot Approximation algorithms for the traveling salesman problem p22

Montemanni The robust traveling salesman problem with interval data p21

Nilsson Heuristics for the Traveling Salesman Problem p6

Morris Graph Representations

Network/Graph Theory Graph-based representations p13

nokie Graphs - Terminology and Representation

ojj GRAPH REPRESENTATION

opendatastructures 12.2 AdjacencyLists A Graph as a Collection of Lists

Pacha-Sucharzewski Analysis of the Travelling Salesman Problem and an Application of Heuristic Techniques for Finding a New Solution p7

PAPADIMITRIOU ON THE APPROXIMABILITY OF THE TRAVELING SALESMAN PROBLEM p20

Park Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation p4

Pathak Travelling Salesman Problem Using Bee Colony With SPV p5

Piana A graph representation of basic macroeconomic scheme p27

Picard Coinductive Graph Representation p64

Pisanski Graph representation

Pizlo Traveling Salesman Problem: A Foveating Pyramid Model p9

Popov Algorithm of the Week Graphs and Their Representation

okokok
Potvin The Traveling Salesman Problem A Neural Network Perspective p60

CCAO heuristic
GENIUS heuristic
iterated Lin-Kernighan heuristic

Quiz — Graph representations

Rasmussen TSP in Spreadsheets – a Guided Tour p23

Renaud AN EFFICIENT COMPOSITE HEURISTIC FOR THE SYMMETRIC GENERALIZED TRAVELING SALESMAN PROBLEM p23

okokok
Rostoker Travelling Salesman Problems p56

Rothe Two solvable cases of the Traveling Salesman Problem p60

N-line Traveling Salesman Problem

Rotta Graph Representation

Sadiq The Traveling Salesman Problem: Optimizing Delivery Routes Using Genetic Algorithms p6
2
Multiple Traveling Salesman Problem (mTSP)
SAS
greedy algorithm

sanfoundry Java Program to Describe the Representation of Graph using Adjacency List

Sb?rlea DFGR: an Intermediate Graph Representation for Macro-Dataflow Programs p8

Schneider Searching for backbones - an efficient parallel algorithm for the traveling salesman problem p16

symmetric TSP
asymmetric TSP

Simulated Annealing

Ensemble Based Simulated Annealing

Threshold Accepting

Ensemble Based Threshold Accepting

Great Deluge Algorithm

Record to Record Travel

lin-2-opt

lin-3-opt

lin-n-opts

Schneider The time-dependent traveling salesman problem p5
time-dependent traveling salesman problem

Sedziwy Effective graph representation p13

Seibert Learning Aspect Graph Representations from View Sequences p8

Siek Review of Elementary Graph Theory

Situngkir Small World Network of Athletes Graph Representation of the World Professional Tennis Player p13

Shai Transforming Engineering Problems through Graph Representations p28

Slesarenko How to select the best graph representation for a given task p18

stackoverflow Comparing object graph representation to adjacency list and matrix representations

?tencek Traveling salesman problem p53

stoimen Computer Algorithms Graphs and their Representation

Stratis Graph Representation of Concurrent Programs in C++ p50

suanfazu Comparing object graph representation to adjacency list and matrix representations

suanfazu Comparing object graph representation to adjacency list and matrix representations1

tutorialhorizon Graph Representation — Adjacency Matrix and Adjacency List

wagner Graph Representation

Wang Handwritten Word Spotting Based on Graph Representation p13

WANG SIGMA-DELTA QUANTIZATION ERRORS AND THE TRAVELING
SALESMAN PROBLEM p21

Euclidean TSP

Wang Text-Enhanced Representation Learning for Knowledge Graph p7

wolfram Graph Construction & Representation

Wu Structural Opinion Mining for Graph-based Sentiment Representation p10

Yatsenko Fast Exact Method for Solving the Travelling Salesman Problem p4

Zhao Semantic Single Video Segmentation with Robust Graph Representation p7


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People

Peter Meyer

The Travelling Salesman Problem

http://www.hermetic.ch/misc/ts3/ts3demo.htm

Neil Simonetti's Traveling Salesman Problem Page

http://www.andrew.cmu.edu/user/neils/tsp/


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Software and Online Tools

branch&cut framework ABACUS

Concorde Solver

http://www.math.uwaterloo.ca/tsp/concorde.html
http://www.math.uwaterloo.ca/tsp/usa50/index.html

http://neos.mcs.anl.gov/neos/solvers/co:concorde/TSP.html

http://www.math.uwaterloo.ca/tsp/concorde/DOC/index.html

CPLEX

MIP solver

NEOS

www.neos-server.org

https://www.ibm.com/developerworks/community/blogs/jfp/entry/computing_the_really_optimal_tour_acrosss_the_usa_on_the_cloud_with_python?lang=en

http://wid.wisc.edu/featured-science/optimizing-the-world-one-problem-at-a-time/

OptaPlanner

http://www.optaplanner.org/

QSopt

SaaS solver

SAS

SAS Global Forum 2012

SAS and all other SAS Institute Inc. product or service names are registered trademarks or trademarks of SAS Institute Inc. in the USA and other countries. ? indicates USA registration.
https://sites.google.com/site/travelingsalesmansas/


Untitled Document

A* algorithm

https://stackoverflow.com/questions/4453477/using-a-to-solve-travelling-salesman

Ant Colony

Ant Systems

http://www.techrepublic.com/resource-library/whitepapers/the-one-commodity-traveling-salesman-problem-with-selective-pickup-and-delivery-an-ant-colony-approach/

http://www.codeproject.com/Articles/644067/Applying-Ant-Colony-Optimization-Algorithms-to-Sol

http://www.emerginginvestigators.org/tag/traveling-salesman-problem/

http://benthamopen.com/ABSTRACT/TOAUTOCJ-7-1329

Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

Dorigo Ant colonies for the traveling salesman problem p10
TR/IRIDIA/1996-3
Université Libre de Bruxelles
Belgium
Marco Dorigo
IRIDIA, Université Libre de Bruxelles, Avenue Franklin Roosevelt 50, CP 194/6, 1050
Bruxelles, Belgium
mdorigo@ulb.ac.be, http://iridia.ulb.ac.be/dorigo/dorigo.html
Luca Maria Gambardella
IDSIA, Corso Elvezia 36, 6900 Lugano, Switzerland
luca@idsia.ch, http://www.idsia.ch/~luca

ACS (Ant Colony System)

ACS (Ant Colony System)-3-opt

ant-cycle

ant-density models

ant-quantity

Artificial immune systems

Greco Travelling Salesman Problem p212
Artificial Immune Systems (AIS)


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Bacterial Foraging Optimization Algorithm (BFOA)

Bacterial Foraging Optimization Algorithm (BFOA)

Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

Bees

Bee Colony Optimization

Birds, Bees, and Traveling Salesmen: What Humans Can Learn About How To Get Around

http://www.slate.com/articles/health_and_science/the_efficient_planet/2012/11/birds_bees_and_traveling_salesmen_animals_solved_a_wildly_complex_mathematical.html

Bees' tiny brains beat computers, study finds

http://www.theguardian.com/world/2010/oct/24/bees-route-finding-problems

BEE COLONY OPTIMIZATION WITH LOCAL SEARCH FOR TRAVELING SALESMAN PROBLEM

Read More: http://www.worldscientific.com/doi/abs/10.1142/S0218213010000200?src=recsys&

http://www.worldscientific.com/doi/abs/10.1142/S0218213010000200?src=recsys&

http://www.themarysue.com/bees-havent-solved-traveling-salesman-problem/

http://www.dresden-science-calendar.de/calendar/en/event/9851

Benchmarking Algorithms

Kang Benchmarking Algorithms for Dynamic Travelling Salesman Problems p6

bio-inspired heuristic techniques

Biogeography migration algorithm for traveling salesman problem

http://www.emeraldinsight.com/doi/abs/10.1108/17563781111160002

biological computing / bacterial computer

Three City Traveling Salesman Problem Solved by Bacteria! { 2009 07 26 }

http://mat.tepper.cmu.edu/blog/?p=777

branch and bound

branch and bound

Branch-and-Cut Algorithm

branch and cut

Dumitrescu The Traveling Salesman Problem with Pickup and Delivery Polyhedral Results and a Branch-and-Cut Algorithm p31
Polyhedral Results

Brute Force Solution of Traveling Salesman Problem

https://people.sc.fsu.edu/~jburkardt/m_src/tsp_brute/tsp_brute.html

http://www.stat.ucla.edu/~david.zes/TSP.html

bumblebee foraging


Untitled Document

CCAO heuristic

Cells take on traveling salesman problem

Cells take on traveling salesman problem

https://www.sciencenews.org/search?st=article%20cells%20take%20traveling%20salesman%20problem%20&cd=202&hl=en&ct=clnk&gl=us

https://www.sciencenews.org/article/cells-take-traveling-salesman-problem

Forget GPS. With no fancy maps or even brains, immune system cells can solve a simple version of the traveling salesman problem, a computational conundrum that has vexed mathematicians for decades.

The new research, which simulates how a type of white blood cell seeks and destroys infectious particles, shows how living things — be they cells, sharks or bees — successfully find a...

Chained Lin-Kernighan (CLK-ABCC)

COA (Chaotic Optimization Algorithm)

Christofides heuristic

http://en.wikipedia.org/wiki/Christofides_algorithm

Civilization and Society (CS) algorithm

cluster first-route second principle

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

Combined Integer Programming and Constraint Programming Approach

Easton Solving the Traveling Tournament Problem A Combined Integer Programming and Constraint Programming Approach p10

Construction heuristics

nearest neighbor heuristic
cheapest insertion criterion it will be called the CI heuristic

cutting-plane method

Dantzig Solution of a Large-Scale Traveling-Salesman Problem p22

cutting planes


Untitled Document

Decomposition heuristics

node selection and tour construction heuristics
subsets ordering and tour construction heuristics = ST algorithm

Dijsktra's algorithm

Dijsktra's algorithm applied to travelling salesman problem

http://cs.stackexchange.com/questions/1749/dijsktras-algorithm-applied-to-travelling-salesman-problem

Discrete particle swarm optimization algorithm

DNA Computing

http://legacy.jyi.org/volumes/volume8/issue2/features/srivastava.html
DNA Computing

Adleman utilized the incredible storage capacity of DNA to implement a brute-force algorithm for the directed Hamiltonian Path Problem (HPP)

DOMINATION ANALYSIS

GUTIN THE TRAVELING SALESMAN PROBLEM AND ITS VARIATIONS p40
EXPONENTIAL NEIGHBORHOODS

Double Minimum Spanning Tree

Dynamic Programming

https://www.andrew.cmu.edu/user/neils/tsp/

Dynasearch

Angel A dynasearch neighborhood for the bicriteria traveling salesman problem p4

Dynasearch
bicriteria traveling salesman problem


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elastic net method

elastic network approaches

Electromagnetism

Electromagnetism-like Mechanisms (EM)

electromagnetism-like optimization

Evolutionary Computing Algorithms

Evolutionary Computation
Evolutionary programming
Evolutionary strategies

evolution strategies

EXPONENTIAL NEIGHBORHOODS

GUTIN THE TRAVELING SALESMAN PROBLEM AND ITS VARIATIONS p40


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Foveating Pyramid Model


Untitled Document

GI3 (Generalized Initilialization, Insertion, and Improvement)

genetic algorithms

genetic algorithm

http://en.wikipedia.org/wiki/Genetic_algorithm

Traveling Salesman Problem Using Genetic Algorithms
http://www.lalena.com/ai/tsp/

http://www.theprojectspot.com/tutorial-post/solving-traveling-salesman-problem-using-google-maps-and-genetic-algorithms/9

http://www.ig.fpms.ac.be/node/504

http://www.hindawi.com/journals/tswj/2014/178621/

Bryant Genetic Algorithms and the Traveling Salesman Problem p34
Kylie Bryant
Arthur Benjamin, Advisor
Second Reader: (Lisette de Pillis)
December 2000
Department of Mathematics

The traveling salesman problem is NP-hard

Genetic algorithms are an evolutionary technique

  1. crossover operators
  2. mutation operators
  3. operators that use heuristic information of the graph
  4. operators that use a matrix representation of the graph

15

Ji The Traveling Salesman and the Quadratic Assignment Problems: Integration Modeling and Genetic Algorithm p8
Ping Ji* William Ho

genetic algorithm (GA)

immune genetic algorithm (IGA)

Niche Pseudo-Parallel Genetic Algorithms

for Path Optimization of Autonomous Mobile Robot - A Specific Application of TSP

Genetic Local Search

Genetic Algorithms

genetic programming

GENIUS heuristic

Geometric heuristics

GI3 (Generalized Initialization, Insertion and Improvement)

goo

Fantastic Programmable Goo Solves Difficult Math Problems

A new way of looking at a classic math problem.
By Francie Diep Posted March 26, 2013

http://www.popsci.com/science/article/2013-03/fantastic-goo-solves-traveling-salesman-problem

http://www.technologyreview.com/view/512821/shrinking-blob-computes-traveling-salesman-solutions/

Gravitational Search Algorithm (GSA)

Gravitational Search Algorithm (GSA)

Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

Great Deluge Algorithm

greedy 2-opt interchange algorithm

greedy algorithm

Greedy Heuristics

greedy principles


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HARMONIC ANALYSIS

JONES THE TRAVELING SALESMAN PROBLEM AND HARMONIC ANALYSIS p9

harmony search

Antosiewicz Choice of best possible metaheuristic algorithm for the travelling salesman problem with limited computational time: quality, uncertainty and speed p10

harmony search
quantum annealing
tabu search

Held–Karp algorithm called Bellman–Held–Karp algorithm

https://en.wikipedia.org/wiki/Held%E2%80%93Karp_algorithm

Heuristics

Sorting Heuristics

Nearest Feasible Neighbor Heuristics
Insertion Heuristic 1
Insertion Heuristic 2
Or-Exchange-Heuristic
Arc-Reversal Heuristic
Swap Heuristic
Arc-Reinsertion Heuristic
Node-Reinsertion Heuristic
Two-Node-exchange Heuristic

LP–exploitation heuristic

I3 heuristic farthest-insertion, nearest-insertion, and cheapest-insertion heuristics

ILS Algorithms


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Insertion Heuristics

Insertion heuristics

Intelligent Water Drops (IWD)

Intelligent Water Drops algorithm

Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

Intelligent water drops

Greco Travelling Salesman Problem p212

Inver-over operator

Iterated Helsgaun (ILK-H)

iterated Lin-Kernighan heuristic


Untitled Document

k-approximation heuristic algorithm

K-OPT

Kohonen Neuronal Networks

http://www.patol.com/java/TSP/


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Lagrangean relaxation

Large-Step Markov Chains (LSMC)

lin-2-opt

lin-3-opt

lin-n-opts

Lin-Kernighan heuristic

Lin-Kernighan type methods

http://www.akira.ruc.dk/~keld/research/LKH/

linear programming

Linear Time Dynamic-Programming Algorithms

Balas Linear Time Dynamic-Programming Algorithms for New Classes of Restricted TSPs A Computational Study p33

living [9] and virtual [29] slime mould based approaches

local search


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Markov chain

Memetic Algorithm (MA-MF)

Mimetic Algorithm (MA) or Lamarckian Evolutionary Algorithm

mixed integer programming formulation for the TSP with Drone (TSP-D)

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

mDPSO hybrid DPSO algorithm with both local search improvement heuristics

mrOXGA Silberholz & Golden genetic algorithm

Multi-objective Meta-heuristics

Jozefowiez Multi-objective Meta-heuristics for the Traveling Salesman Problem with Profits p19


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Nearest Addition

Nearest Insertion

Nearest Neighbor Heuristics

Nearest neighbor heuristics

nearest neighbour

http://www.sanfoundry.com/java-program-implement-traveling-salesman-problem-using-nearest-neighbour-algorithm/

NEH heuristic

Neural Network

Neural Networks
Recurrent Neural Network
Transiently Chaotic Neural Networks

Budinich A Neural Network for the Travelling p8
Salesman Problem with a Well Behaved
Energy Function
Marco Budinich and Barbara Rosario
Dipartimento di Fisica & INFN, Via Valerio 2, 34127 Trieste, Italy

Self Organizing Feature Map (SOFM)

Neural Network / Self Organizing Feature Map (SOFM)

Budinich A Neural Network for the Travelling p8
Salesman Problem with a Well Behaved
Energy Function
Marco Budinich and Barbara Rosario
Dipartimento di Fisica & INFN, Via Valerio 2, 34127 Trieste, Italy

Neural Network
Self Organizing Feature Map (SOFM)


Untitled Document

Optical Solution

https://www.osapublishing.org/oe/abstract.cfm?uri=oe-15-16-10473


Untitled Document

2-opt

3-opt

3/2-approximation algorithm for Metric TSP


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Particle Swarm Optimization(PSO)

Particle Swarm Optimization

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

Modified Discrete Particle Swarm Optimization Algorithm for the Generalized Traveling Salesman Problem

Polyhedral Results

polyhedral cutting plane methods

Dumitrescu The Traveling Salesman Problem with Pickup and Delivery Polyhedral Results and a Branch-and-Cut Algorithm p31

Polyhedral Theory

Letchford Mathematical Programming Approaches to the Traveling Salesman Problem p12

Population-Based Optimization Algorithms for Solving the Travelling Salesman Problem

Priority-Based GLS (PB-GLS)

PyGMO

https://esa.github.io/pygmo/tutorials/tsp.html


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quantum annealing

Antosiewicz Choice of best possible metaheuristic algorithm for the travelling salesman problem with limited computational time: quality, uncertainty and speed p10

harmony search
quantum annealing
tabu search

quantum annealing


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Random key genetic algorithm (RKGA)

Randomized Rounding Approach

Gharan A Randomized Rounding Approach to the Traveling Salesman Problem p65

Record to Record Travel

Recurrent Neural Network

Greco Travelling Salesman Problem p212

River Formation Dynamics (RFD)

Ant Colony Optimization (ACO)
Bacterial Foraging Optimization Algorithm (BFOA)
Gravitational Search Algorithm (GSA)
Intelligent Water Drops (IWD)
Particle Swarm Optimization(PSO)
River Formation Dynamics (RFD)

River Formation Dynamics (RFD)

route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)


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Sanjeev Arora algorithm

self-organizing feature maps

ANGINIOL Self-Organizing Feature Maps and the Travelling Salesman Problem p5

self-organizing feature maps

Budinich A Neural Network for the Travelling p8
Salesman Problem with a Well Behaved
Energy Function
Marco Budinich and Barbara Rosario
Dipartimento di Fisica & INFN, Via Valerio 2, 34127 Trieste, Italy

Self Organizing Feature Map (SOFM)

Shrinking Blob Method

Jones Computation of the Travelling Salesman Problem by a Shrinking Blob p27

Shuffled Frog Leaping (SFL)

Simplified Bi-directional Associative Memory (sBAM)

https://www.lap-publishing.com/catalog/details/store/gb/book/978-3-8383-8370-5/sbam-in-solving-traveling-salesman-problem+&cd=306&hl=en&ct=clnk&gl=us

https://www.lap-publishing.com/catalog/details/store/gb/book/978-3-8383-8370-5/sbam-in-solving-traveling-salesman-problem

Simulated Annealing

http://en.wikipedia.org/wiki/Simulated_annealing

Simulated Annealing

Simulated Annealing

Ensemble Based Simulated Annealing

The Traveling Salesman with Simulated Annealing, R, and Shiny

http://genius.com/4061755/Atodd-the-traveling-salesman-with-simulated-annealing-r-and-shiny/Traveling-salesman-problem
http://toddwschneider.com/posts/traveling-salesman-with-simulated-annealing-r-and-shiny

spanning tree

STOCHASTIC LOCAL SEARCH

successive augmentation heuristics


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tabu search

Antosiewicz Choice of best possible metaheuristic algorithm for the travelling salesman problem with limited computational time: quality, uncertainty and speed p10
tabu search
tabu search

harmony search

quantum annealing

tea-trade model

Thermodynamical Approach

CERNY Thermodynamical Approach to the Traveling Salesman Problem: An Efficient Simulation Algorithm I p11

Threshold Accepting

Ensemble Based Threshold Accepting

Time Adaptive Self-Organizing Maps

time adaptive self-organizing maps

Time Windows by Branch-and-Cut

ASCHEUER Solving the Asymmetric Travelling Salesman Problem with Time Windows by Branch-and-Cut p35

Time Windows by Branch-and-Cut

Tour construction algorithms

tour construction heuristic

four tour construction heuristics

  1. Nearest Neighbor
  2. Greedy
  3. Clarke-Wright / Clarke-Wright savings heuristic
  4. Christofides / Christofides heuristic

Transiently Chaotic Neural Networks

Greco Travelling Salesman Problem p212

transposition expression


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Attractive Traveling Salesman Problem

http://opus.bath.ac.uk/41190/

Asymmetric traveling salesman problem (ATSP)

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/

asymmetric TSP

Given a set of n nodes and distances for each pair of nodes, find a roundtrip of minimal total length visiting each node exactly once. In this case, the distance from node i to node j and the distance from node j to node i may be different.

http://dimacs.rutgers.edu/Challenges/TSP/atsp.html

https://www.aaai.org/Library/JAIR/Vol21/jair21-014.php

https://www.ii.uni.wroc.pl/en/node/361

Asymmetric Travelling Salesman Problem with Time Windows(ATSP-TW)


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bicriteria traveling salesman problem

Angel A dynasearch neighborhood for the bicriteria traveling salesman problem p4

Dynasearch
bicriteria traveling salesman problem

bottleneck traveling salesman problem


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Close-Enough Traveling Salesman Problem

was introduced by William Mennell. Benchmark data can be found at www.minlp.org.
http://www.minlp.org/library/problem/index.php?i=65&lib=MINLP

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/

clustered traveling salesman problem

http://utdallas.influuent.utsystem.edu/en/publications/approximation-algorithms-with-bounded-performance-guarantees-for-the-clustered-traveling-salesman-problem%285bdea61e-08b0-4f14-981c-3fabfd03c889%29.html

constrained traveling salesman problem

http://www.findanexpert.unimelb.edu.au/display/publication1721

cardinality constrained covering traveling salesman problem

Patterson, R., & Rolland, E. (2003). The cardinality constrained covering traveling salesman problem. Computers & Operations Research, 30, 97–116. Elsevier.

covering salesman problem (CSP)

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

covering salesman problem (CSP)
Flying Sidekick Traveling Salesman Problem
TSP with Drone (TSP-D)

truck and trailer routing problem (TTRP)

convex-hull-and-line traveling salesman problem

http://scholar.uwindsor.ca/odettepub/10/


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Dynamic Travelling Salesman Problems

Kang Benchmarking Algorithms for Dynamic Travelling Salesman Problems p6
Benchmarking Algorithms


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Euclidean TSP problem

Euclidean TSP

http://sarielhp.org/research/CG/applets/tsp/TspAlg.html


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Flying Sidekick Traveling Salesman Problem

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

covering salesman problem (CSP)
Flying Sidekick Traveling Salesman Problem
TSP with Drone (TSP-D)

truck and trailer routing problem (TTRP)


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Generalized TSP

Geometric Prize-Collecting Traveling Salesman Problem with Time Windows

Bar-Yehuda On Approximating A Geometric Prize-Collecting Traveling Salesman Problem With Time Windows p12

graphical traveling salesman problem


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maximum benefit travelling salesman problem (MBTSP)

metric TSP

the cost function verifies the triangular inequality

moving-target traveling salesman problem

Helvig The moving-target traveling salesman problem p22

Multiobjective Traveling Salesman Problem

Lust The Multiobjective Traveling Salesman Problem: A Survey and a New Approach p24

multi-objective-multi period traveling salesman problem

http://eprints.utm.my/41926/

Multiple Traveling Salesman Problem (mTSP)

http://www.neos-guide.org/content/multiple-traveling-salesman-problem-mtsp

multisalesmen problem


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N-line Traveling Salesman Problem


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2-period balanced traveling salesman problem

http://econpapers.repec.org/paper/vnmwpaper/154.htm


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Parallel Traveling Salesman Problem

https://www.shodor.org/cserd/Resources/Models/TravelingSalesman/

period traveling salesman problem

Bassetto The Single-Double Balanced Traveling Salesman Problem p16
Single-Double Balanced Traveling Salesman Problem

period traveling salesman problem

Period TSP (PTSP)

Prize-Collecting Traveling Salesman Problem with time-windows

Probabilistic Traveling Salesman Problem

http://www.optimization-online.org/DB_HTML/2015/06/4953.html

http://dev.heuristiclab.com/trac.fcgi/ticket/2221


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Quota Traveling Salesman Problem

http://www.aracneeditrice.it/aracneweb/index.php/pubblicazione.html?item=9788879996921


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Restricted TSP

https://www.andrew.cmu.edu/user/neils/tsp/

rural postman problem


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Single-Double Balanced Traveling Salesman Problem

Bassetto The Single-Double Balanced Traveling Salesman Problem p16

Single-Double Balanced Traveling Salesman Problem

site-disordered traveling salesman problem

https://iopscience.iop.org/article/10.1088/1751-8113/40/46/002/meta;jsessionid=D8C47D0308D2418BD0A04F6CF21EC7F6.c1

Steiner Traveling Salesman Problem

Letchford Compact Formulations of the Steiner Traveling Salesman Problem and Related Problems p28

Symmetric Circulant Traveling Salesman Problem

Greco Travelling Salesman Problem p212

SYMMETRIC GENERALIZED TRAVELING SALESMAN PROBLEM

Symmetric traveling salesman problem (TSP)

symmetric TSP

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/

Given a set of n nodes and distances for each pair of nodes, find a roundtrip of minimal total length visiting each node exactly once. The distance from node i to node j is the same as from node j to node i.

Sequential ordering problem (SOP)

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/

This problem is an asymmetric traveling salesman problem with additional constraints. Given a set of n nodes and distances for each pair of nodes, find a Hamiltonian path from node 1 to node n of minimal length which takes given precedence constraints into account. Each precedence constraint requires that some node i has to be visited before some other node j.

Most recent optimum solutions and best bounds have been found by L. Gouveia and M. Ruthmair. The respective report is available as GR2014.pdf

Some further optimum solutions and comments by A.A. Cire and W.-J. van Hoeve can be found in the paper Multivalued Decision Diagrams for Sequencing Problems.


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time-dependent traveling salesman problem

Schneider The time-dependent traveling salesman problem p5

time-dependent traveling salesman problem

traveling salesman problem (TSP) with Drone (TSP-D)

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

covering salesman problem (CSP)
Flying Sidekick Traveling Salesman Problem
TSP with Drone (TSP-D)

truck and trailer routing problem (TTRP)

traveling salesman problem with few inner points

http://www.wbs.ac.uk/research/explore/by/vladimir-deineko/the-traveling-salesman-problem-with/4F7CFC92-8771-4202-8A5E-B4F3478BF6BB/

TSP with multiple visits is referred to as TSPM

traveling salesman problem (TSP) with Neighborhoods

is another generalization. Test instances can be found at cse.cs.ovgu.de
https://cse.cs.ovgu.de/cse/robotics/tspn/

http://comopt.ifi.uni-heidelberg.de/software/TSPLIB95/

Traveling Salesman Problem with Pickup and Delivery (TSPPD)

http://orbit.dtu.dk/en/publications/the-traveling-salesman-problem-with-pickup-and-delivery-polyhedral-results-and-a-branchandcut-algorithm(a66bfb2d-449e-4b32-a4d2-6cfb89225201).html

Traveling Salesman Problem with Pickup and Delivery

Dumitrescu The Traveling Salesman Problem with Pickup and Delivery Polyhedral Results and a Branch-and-Cut Algorithm p31
Branch-and-Cut Algorithm
Polyhedral Results

Traveling Salesman Problem with Profits

Traveling Salesman Problem with Target Times

TSPs with time windows (TSPTW)

traveling salesman sub-tour problem

covering salesman problem
maximal covering tour problem
median tour problem
multiobjective vending problem
orienteering problem
prize collecting traveling salesman problem
time-constrained traveling salesman problem
traveling purchaser problem
traveling salesman problem with non-visiting penalties

can be viewed as particular cases of the traveling salesman sub-tour problem.

Traveling Tournament Problem

http://mat.gsia.cmu.edu/TOURN/

http://mat.tepper.cmu.edu/TOURN

Dubins Traveling Salesperson Problem with Neighborhoods (DTSPN)

https://www.icb.ucsb.edu/research/publications/dubins-traveling-salesman-problem-neighborhoods-graph-based-approach

Traveling Umpire Problem

http://gent.cs.kuleuven.be/tup/en/

truck and trailer routing problem (TTRP)

Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42
6

cluster first-route second principle
mixed integer programming formulation for the TSP with Drone (TSP-D)
route first-cluster second heuristics based on local search and dynamic programming for the TSP with Drone (TSP-D)

covering salesman problem (CSP)
Flying Sidekick Traveling Salesman Problem
TSP with Drone (TSP-D)

truck and trailer routing problem (TTRP)


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x-and-y-axes travelling salesman problem

Cela The x-and-y-axes travelling salesman problem p3


Current Focus: Math for Chip / Chip Mathematics (Jan 2014 - )

My current focus can be summarized in two areas:

Mathematics for the Chip Industry

Now I am only focusing on mathematics for the chip technology, and particularly graph theory for the emerging chip technologies such as nano chips, quantum chips, photonic, superconducting, strained silicon, SiGe, spintronics, natural computing (biocomputing, bioelectric, chemical, cellular, dna, genetic, membrane, molecular, neuro, physarum etc). etc. I don't want to waste my time on areas where mature technologies and theories are already developed.

However, earlier I planned to first focus on combinatorial optimization and graph theory for detailed routing (channel routing in particular) of chips, then extend to other areas of chip design and lastly to all areas of chip industry - from R&D, design, fabrication, packaging, testing, simulation, to use - and with all mathematical tools, not just graph theory.

$$$$$$$$$$$$$$$$$$$$$$$$$

I was thinking why I should pursue mathematics for cryptology at end 2013, and asked myself, did this studies have great impact on human society and its development? I don't want to waste my time and talent on minor science, and cryptology only affects one less significant side of the civilization of today. On other hand, today's cryptography has diversified itself into a myriad of areas, unlike those 10 or 20 years ago, when the dominant protocols were clear enough - public cryptography with RSA and private security scheme with AES/DES and a number of key distributions, signature, certificate protocols. Today we have many other choices, and it's difficult which one is most appropriate for our use. And in the end I cannot figure out which to pursue.

After a few weeks thinking I determined that it is the chip technology which has the greatest impact on our life and society, for now and for the foreseeable future. Who possesses the key chip technologies, who controls the world. And I must possess some of the key technologies at any cost. And immediately I took action.

Our society is now heavily dependent on chip technology and to lesser extent to, on computer programming languages, and computer operation systems. These three are key to our civilization. As such I will keep myself updated with progress in these three areas, while chip technology will be the first priority.

Thus saying, it does not mean I will devote to the entire chip technology. My goal will be mainly on making some fundamental studies of mathematics on some key areas of chip technologies incl research and development, design, fabrication, packing, simulation and testing with focus on design. Most probably graph theory and combinatorics will be the most heavily studied areas, but it seems all maths are involved in chip technology. To make some meaningful chip math studies, I have to acquaint myself with most parts of chip technologies incl. MOS and transistors, electronic circuits, VLSI, and their designs, instruction sets (assembly languages) of some of the key processors. Of course I shall also review all those math branches which are useful in the studies - algebra, computation, computer complexity, probability, functional, analysis, and even number theory.

At the same time I need also follow the latest computer operation technologies mainly the kernels and the computer programming languages mainly C/C++.

For more information please go to the following links:

My research and authoring are focusing on graph theory - at present graph embedding - for new generations of IC technologies.

" Hypergraph models for FPGA technologies" - completed on Oct 17 2014

A research plan and its abstract were drafted for review.

My Writings

Over the last years I have written some papers about graph theory about VLSI routing/detailed routing/channel routing, hypergraph modeling for FPGA design, graph theory for advanced chip design particularly quantum computing, graph partitioning for VLSI design, graph embedding for VLSI (particularly quantum circuits) design, graph theory for 3d VLSI design etc. But I did not publish my results. Here below an incomplete listing:

Pure Graph Theory

Graph Theory – Introduction
Most important open problems in graph theory
TSP – Traveling Salesman Problems
graph actions
graph clustering
graph coloring
graph coupling
graph covering
graph editing tools
graph embedding
graph features
graph file formats
graph functions
graph laplacian
graph matching
graph models
graph packing
graph partition
graph transform
graph traversal
graph types
tree types

Applied Math and Graph Theories to Conventional IC Design

Chip design study notes – math foundations
Math for VLSI Routing

Graph theoretical applications to VLSI design

Graph theoretical applications to VLSI design - Graph types
Graph theoretical applications to VLSI design - Tree types

Graph theoretical applications to VLSI design - Graph/Hypergraph File Format in General
Graph theoretical applications to VLSI design - Graph/Hypergraph (Editing) Tools

Graph/Hypergraph modeling and it’s applications to VLSI design

Graph functions and it’s applications to VLSI design

Graph theoretical applications to VLSI design - abstract levels
Graph theoretical applications to VLSI design – graph coloring
Graph theoretical applications to VLSI design – graph coupling
Graph theoretical applications to VLSI design – graph covering
Graph theoretical applications to VLSI design – graph features
Graph theoretical applications to VLSI design – graph laplacian
Graph theoretical applications to VLSI design – graph matching
Graph theoretical applications to VLSI design – graph traversal
Graph theoretical applications to VLSI design – other phases of the chip technologies

Graph theoretical applications to VLSI design - Graph operations – a summary
Graph Embedding and it’s applications to VLSI design
Graph theoretical applications to VLSI design – graph packing
Graph to hypergraph clustering and it’s applications to VLSI design
Graph/Hypergraph partitioning and it’s applications to VLSI design
Graph to hypergraph transformation and it’s applications to VLSI design

Graph Theory for Reconfigurable Computing – Part I: Control & Data Flow Graph
Graph Theory for Reconfigurable Computing – Part XXX: Summary
Graph theoretical applications to chip design study notes – Part FPGA
Graph theoretical applications to chip design study notes – Part 3D IC

Graph theoretical applications to VLSI design – special, CMOS based chips review – ASIC, SOC, MPSoC, PSoC,? NOC, ASSP, DSP, AMS, CMP, SOI, SOS etc

Applied Graph Theory to New Generation of Information Processing and Computing

Graph theory and mathematics in new generation of information processing and computing
Open problems in new generation of information processing and computing

Graph theoretical applications to bio chips
Graph theoretical applications to Cellular Computing?
Graph theoretical applications to Chemical Computing (Reaction-Diffusion Computing)
Graph theoretical applications to deep submicron chips??????
Graph theoretical applications to DNA computing??????
Graph theoretical applications to gallium chips???
Graph theoretical applications to genetic circuits
Graph theoretical applications to Germanium Chips / Silicon-Germanium Chips?????
Graph theoretical applications to Graphene Chips
Graph theoretical applications to Indium Chips???
Graph theoretical applications to Liquid Chips????
Graph theoretical applications to membrane chips
Graph theoretical applications to molecular chips
Graph theoretical applications to Molybdenite Transistors
Graph theoretical applications to nano chips
Graph theoretical applications to Natural / Nature-Inspired Computing?????
Graph theoretical applications to neural computing
Graph theoretical applications to Organic Computing?
Graph theoretical applications to phase transition memory
Graph theoretical applications to Physarum Chip
Graph theoretical applications to Resonant Tunneling Devices???
Graph theoretical applications to photonic chips
Graph theoretical applications to Quantum chips
Graph theoretical applications to Single Electronics /Single Electron Transistor / Single Electron Tunnelling (Set) Devices
Graph theoretical applications to Spin Electron Chips?
Graph theoretical applications to strained silicon chips
Graph theoretical applications to superconducting chips

Hypergraph

Graph theoretical applications to VLSI design - Hypergraph introduction
Graph theoretical applications to VLSI design - Hypergraph types
Graph theoretical applications to VLSI design - Hypergraph clustering

Hypergraph models for Circuit Netlist VLSI

Mathematical Foundations for IC Technologies - Graph Theory, Combinatorial Optimization and Others, Part I: Graph Theory, Vol. I: Hypergraph, Section I: Hypergraph Models

Level of Hypergraph Applications to VLSI circuits
Hypergraph Applied to Various Types of IC Technology

IC DESIGN

Chip design study notes - general
Chip design study notes – electronic theories and technologies
Chip design study notes – physical design
Chip design study notes - routing
Chip design study notes – benchmark circuits

Graph Theory and Other Sciences
2017-02-11


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Terminology

Literature


3D tree

3D tree
Pathak, Mohit and Lim, Sung Kyu: Thermal-aware Steiner Routing for 3D Stacked ICs p7 2007 IEEE

Terminology

Literature


Arborescence trees

Arborescence trees
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

Terminology

Literature


A - Tree

A - Tree
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

A - Tree vs Steiner Tree

Using a slightly di erent delay model called the dominant time-constant model, a near-
optimal algorithm for minimum-delay routing is presented in [10]. The algorithm is based on
the concept of Arborescence-trees, which have the property that every driver-sink path is a
minimum length path. An A-tree, in general, may have longer wire length than a minimum
Steiner tree, but reduces delays when wire resistance is signi cant. It is shown in [10] that
minimizing delay is equivalent to nding an A-tree with minimum wire length. Figure 3 shows
the A-trees vs the Steiner tree.

An algorithm for nding near-optimal solutions is presented, and experimental results demon-
strate delay reductions of up to 40% based on typical MCM parameters. The A-tree algorithm
can also be extended to handle obstacles in the Manhattan plane.

Some performance-oriented algorithms do not directly minimize delay, but instead focus on
objectives related to delay. For example, close examination of the Elmore delay model reveals
that delay is related to the total wire length as well as the square of the source-sink path lengths.
This observation is used in [8] to derive a Bounded Radius Bounded Cost (BRBC) algorithm,
which takes a user-de ned parameter  and constructs a tree whose total wire length is at
most 2(1 + 2=) of the optimal Steiner length, and the longest path is at most (1 + ) times
the maximum source-sink distance. A performance-oriented minimum rectilinear Steiner tree
(POMRST) algorithm [33] minimizes total wire length subject to constraints on the lengths of
individual source-sink paths.

A - Tree
Pathak, Mohit and Lim, Sung Kyu: Thermal-aware Steiner Routing for 3D Stacked ICs p7 2007 IEEE

A - Tree
Salek A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm p6

Terminology

Literature


binary tree

binary tree

binary trees
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123
Another approach to construction low skew clock distributions involves matching the geometry of the network to the clock loads present in the design. These networks are designed by a bottom-up algorithmic approach as opposed to a top-view global approach [10]. Typically, these are constructed using buffered binary trees. To minimize skew, two clock sinks are chosen and the point between the two is calculated where the load from the sink and the clock routing is equal on both sides. At this point, a buffer is placed and this point become an effective clock sink for the next highest clock level. In this way, a load-balanced tree is recursively built to minimize skew. This step-by-step process can be seen in Fig. 13. This method is popular in the automatic synthesis and layout of clock network which is typically seen in commercial place and route CAD tools for ASIC designs.

B*-tree

Chen 3D-Floorplanning for Via and Wire length Minimization p50

B*-tree

Binary tree

B*-tree

Chen, Hsien-Te et al: A New Architecture for Power Network in 3D IC, 2011 EDAA, p6

In order to trade off many design factors in 3D floorplan at the
same time, nondeterministic algorithm, simulated annealing (SA),
is used in our algorithm as shown in Fig. 4. In addition, 3D B*-tree
structure is applied in our algorithm as a floorplan representation
[5].

Our tool is integrated in the tool developed by [5]. Hence, the
software platform used by two methods including floorplan representation in B*-tree and simulated annealing engine are
the same.

B*-tree

Cong, Jason; Wei, Jie and Zhang, Yan: A Thermal-Driven Floorplanning Algorithm for 3D ICs p8 Dec 2004 ...............
Floorplanning is a well-studied problem for 2D circuit design.
Floorplans can be classified into two categories in terms of block
configuration, slicing structure and non-slicing structure. Nonslicing
structure is more general but requires more complicated
representation data structures. Floorplanning algorithms are
normally based on simulated annealing (SA) optimization scheme,
using various kinds of floorplan representations. Many
floorplanning representations for 2D non-slicing general floorplan
have been proposed including sequence pair [18], BSG [16], B*-
Tree[4], O-Tree[11], CBL[12], TCG [17], etc. TCG representation
is effective in wirelength and area optimization since the relative
distances of the modules are implicitly stored in addition to the
relative positions between modules.

B*-tree

de Paulo 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans p13.pdf

B*-tree

de Paulo 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans p12.pdf

B*-tree

Falkenstern, Paul et al: . Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis. In Proc. 15th Asia and South Paci c Design Automation Conf. (ASP-DAC), pages 169- 174, 2010. p 6 ........................

Falkenstern, Paul et al: . Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis p17 ppt slides . In Proc. 15th Asia and South Paci c Design Automation Conf. (ASP-DAC), pages 169- 174, 2010.

binary tree
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

B*-tree

Lu, CHAO-HUNG et al: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits, JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 27, 287-302 (2011), p16

LU, CHAO-HUNG; CHEN, HUNG-MING AND LIU, CHIEN-NAN JIMMY: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits p16 JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 27, 287-302 (2011) 287

binary trees
Papa Hypergraph Partitioning and Clustering p38

binary trees
Sarhan Optimization of TSV-based Crossbars for a 3D Memory-Centric Network-on-Chip p7.pdf

Three-dimensional Integrated Circuits Design, EDA and Architecture
Xie, Yuan et al: Three-dimensional Integrated Circuits Design, EDA and Architecture June 2011 p156...........

Computer Science and Engineering Department, University Park, PA16802, USA

yuanxie@cse.psu.edu

http://www.cse.psu.edu/~yuanxie/

3D B*-tree

B*-tree Floorplan Model
The floorplanner used in this work is based on the B*-tree representa tion, which was proposed by Chang et al. [42]. A B*-tree is an ordered binary tree which can represent a non-slicing admissible floorplan. Fig ure 4.2 shows a B*-tree representation and its corresponding floorplan. The root of a B*-tree is located at the bottom-left corner. A B*-tree of an admissible floorplan can be obtained by depth-first-search procedure in a recursive fashion. Starting from the root, the left subtree is visited first then followed by the right subtree, recursively. The left child of node ni is the lowest unvisited module in Ri, which denotes the set of modules adjacent to the right boundary of module bi. On the other hand, the module, representing the right child of ni, is adjacent to and above module bi. We assume the coordinates of the root node are always (0,0) residing at bottom-left corner. The geometric relationship between two modules in a B*-tree is maintained as follows. The x-coordinate of node nj is xi+wi, if node nj is the left child of node ni. That is, bj is located and is adjacent to the right-hand side of bi: For the right child nk of ni, its x-coordinate is the same as that of ni, with module bk sitting adjacent to and above bi. While the original B*-tree structure was developed and used for the 2D floorplanning problem, we extend this model to represent a multi-layer 3D floorplanning (see Figure 4.3) and modify the perturbation function to handle 3D floorplans in this work.
Fig. 4.2: (a)an example floorplan (b) the corresponding B*-tree
Fig. 4.3: Extending B*-tree model to represent 3D floorplanning

There are six perturbation operations used in our algorithm and they are listed below:
(1) Node swap, which swaps two modules.
(2) Rotation, which rotates a module.
(3) Move, which moves a module.
(4) Resize, which adjusts the aspect-ratio of a soft module.
(5) Interlayer swap, which swaps two modules at different layers.
(6) Interlayer move, which moves a module to a different layer.
The rst three perturbations are the original moves de ned in [42].
Since these moves only have in uence on the fl oorplan in single layer, more interlayer moves, (5) and (6) are needed to explore the 3D floorplan solution space.
While test techniques and DFT solutions for 3D ICs have remained largely unexplored in the research community, ...

B*-tree

Zhou, Pingqiang et al: 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits p8 Aug 2007

binary trees
Zhou, Pingqiang: Interconnect Design Techniques for Multicore and 3D Integrated Circuits PhD Thesis August, 2012 p135

full binary tree

3-D Design: Architectures, Methodologies, and Test Circuits
Friedman, Eby G.: 3-D Design: Architectures, Methodologies, and Test Circuits p137 June 11, 2010 2nd Design for 3-D Silicon Integration Workshop ....................

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering

Department of Electrical and Computer Engineering

University of Rochester

Rochester, New York 14627 USA

Phone: (585) 275-1022 Fax: (585) 276-0074

Email: friedman@ece.rochester.edu

www.ece.rochester.edu/~friedman

Terminology

Literature


buffered tree

buffered tree
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123
A simple example of a buffered tree can be seen in Fig. 11.

Terminology

Literature


Butterfly-Fat-Tree

Butterfly-Fat-Tree
Pangracious, Vinod et al: Designing 3D Tree-based FPGA Interconnect Optimization And Thermal Analysis, "New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International Paris France,
Paris : France (2013)", p4

As illustrated in Figure 3, the programmable
interconnects of a Tree-based FPGA are arranged in a multilevel
network with the switch blocks placed at different tree
levels using a Butterfly-Fat-Tree network topology. The 3D
interconnect network organization and design validation are
presented in [5]. The inter-layer vias (TSV) are to be limited
because they are large in size compared to the minimum
feature size on the die, while the finest vias currently available
are about 1m X 1m with a pitch of about 1.6 to 3m [2].

...................

The Tree-based FPGA architecture unifies two unidirectional
upward and downward interconnection networks using a
Butterfly-Fat-Tree topology to connect DMSBs (Downward MSBs) and UMSBs (Upward MSBs) to LB inputs and outputs.
For a downward MSB (DMSB) interconnection network, a
reduction in the number of inputs at level ` impacts level
` + 1, since the number of DMSBs at level ` + 1 is equal
to the number of inputs at level `. In the case of the upward
interconnection network, a reduction in number of outputs at
level ` impacts at level ` + 1 since the number of UMSBs at
level ` + 1 is equal to the number of outputs at level `. The
Rent’s parameter [6] based upward and downward network
model is explained below.

Butterfly-Fat-Tree
Pangracious, Vinod et al: Pyhsical Design Exploration of 3D Tree-based FPGA Architecture, "GLSVLSI '13 Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, Paris : France (2013)"p2.

An innovative 3D physical design exploration methodology
for Tree-based FPGA architecture is presented in this pa-
per. In a Tree-based FPGA architecture, the interconnects
are arranged in a mult-dimensional network with the logic
unites and switch blocks placed at di erent levels, using a
Butter
y-Fat Tree network topology. A 3D physical design
exploration methodology leverage on Through Silicon Via
(TSVs) using a horizontal break-point to re-distribute the
Tree interconnects into multiple stacked active silicon layers
proposed in this paper.

The Tree-based FPGA ar-
chitecture uni es two unidirectional upward and downward
interconnection networks using a Butter
y-Fat-Tree topol-
ogy in order to connect DMSBs (Downward MSBs) and
UMSBs (Upward MSBs) to LB's inputs and outputs.

Butterfly-Fat-Tree
Pangracious Designing a 3D Tree-based FPGA Optimization of Butterfly Programmable Interconnect Topology Using 3D Technology p8.pdf

Butterfly-Fat-Tree
Choudhary Migration of On-Chip Networks from 2 Dimensional Plane to 3 Dimensional Plane p4.pdf

Butterfly-Fat-Tree

Feero, Brett Stanley and Pande, Partha Pratim: Networks-on-Chip in a Three-Dimensional Environment A Performance Evaluation, IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 1, JANUARY 2009, p14

Feero, Brett Stanley and Pande, Partha Pratim: Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation p14 IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 1, JANUARY 2009

Two types of tree-based interconnection networks that have
been considered for NoC applications are butterfly fat tree
(BFT) [16], [17] and the generic fat tree, or SPIN [18]. This
paper endeavors to quantify the enhancements achieved
when these networks are instantiated in a 3D IC environment.
Unlike the work with mesh-based NoCs, we do not
propose any new topologies for tree-based systems. Instead,
we investigate the achievable performance benefits by
instantiating already-existing tree-based NoC topologies in
a 3D environment.

3D environment.
The BFT topology we consider is shown in Fig. 4a. For a
64-IP SoC, a BFT network will contain 28 switches. Each
switch (Fig. 5a) in a BFT network consists of six ports, one to
each of four child nodes and two to parent nodes, with the
exception of the switches at the topmost layer. When
mapped to a 2D structure, the longest interswitch wire
length for a BFT-based NoC is l2DIC=2, where l2DIC is the
die length on one side [17], [5]. If the NoC is spread over a
20 mm  20 mm die, then the longest interswitch wire is
10 mm [5], as shown in Fig. 4c. Yet, when the same BFT
network is mapped onto a four-layer 3D SoC, wire routing
becomes simpler, and the longest interswitch wire length is
reduced by at least a factor of two, as can be seen in Fig. 4d.
This will lead to reduced energy dissipation as well as less
area overhead. The fat tree topology in Fig. 4b will have the
same advantages when mapped on to a 3D IC as the BFT.

..............................

Terminology

Literature


carry generation tree

Terminology

Literature


Clock Tree

3D-IC clock-tree

weighted clock-tree

global clock tree

balanced clock-tree

thermalaware buffered clock tree

zero-skew clock tree

regular clock tree

H-Clock Tree

clock H tree

Clock Tree
Benini 3D-MPSoCs architectural and design technology outlook p24.pdf

Clock Tree / Multi Stage Clock Tree / zero-skew clock tree / Zero Skew Tree
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

clock tree / global clock tree / thermalaware buffered clock tree / zero-skew clock tree
Chen Clock Tree Synthesis with Methodology of Re-use in 3D IC p6

Chen Clock Tree Synthesis with Methodology of Re-use in 3D IC p6

NNG (nearest neighbor graph)

Clock Tree

global clock tree

thermalaware buffered clock tree

zero-skew clock tree

Clock Tree
Chong, Jongwha: Thermal Aware Design Methodology for 3D-IC, 2011, p27

Thermal Estimation & Reduction at Floorplan Stage
?? Thermal estimation of 3D-IC at floorplan stage
?? Thermal reduction of 3D-IC at floorplan stage
??Layering optimization : Thermal reduction
6
Dielectric
Layer
Block 1 Block 2
Block 3
Block 4
Signal TSV
Metal Routing
Layers
Silicon
Pad
Block 5
A Routing
Group
P/G TSV
Clock TSV
Interconnects
??Heat Source
??Blocks
??Interconnects
?? Signal nets
?? Power/Ground (P/G) network
?? Clock tree network
??TSV (Through Silicon Via)

3rd Step : Virtual Routing (Synthesis) of Clock Net
?? BST (Bounded Skew Tree) based clock tree synthesis
?? Clock sinks like latch and flip-flop in the soft-macro block are
unknown
?? Set the same spacing of clock sink within the block

Clock Tree
CMP 3D Integration 2012 p43...........................
Clock Tree Synthesis

Clock Tree

Dilli, Zeynep: PHYSICAL ASPECTS OF VLSI DESIGN WITH A FOCUS ON THREE-DIMENSIONAL INTEGRATED CIRCUIT APPLICATIONS, PhD thesis, 2007, p263 .................

Clock Tree
Doan An MOO-based methodology for designing 3D-stacked integrated circuits CoDE-SMG p26.pdf

Clock Tree / regular clock tree
Gupta Yield Analysis and Optimization p29

Clock Tree

Hasan, Yasmeen: POWER AWARE PHYSICAL MODEL FOR 3D ICs, 2006, p10

Hasan, Yasmeen: POWER AWARE PHYSICAL MODEL FOR 3D IC’S p10 International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011

Clock Tree
T.-Y. Kim and T. Kim, “Clock Tree Embedding for 3D ICs,” in Proceedings of Asia and South Pacific Design Automation Conference, January 2010, pp. 486–491.

Clock Tree
Tak-Yung Kim and Taewhan Kim. Clock tree synthesis with pre-bond testa- bility for 3d stacked ic designs. In Proc. 47th ACM/IEEE Design Automation Conf. (DAC), pages 723{728, 2010.

Clock Tree

Knechtel, Johann et al: Multiobjective Optimization of Deadspace a Critical Resource for 3D-IC Integration IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012, November 5-8, 2012, San Jose, California, USA p8............

Clock Tree
H. S. Lee and K. Chakrabarty. Test challenges for 3d integrated circuits. IEEE Design & Test of Computers, 26(5):26–35, 2009.

Clock Tree
Lim 3D Circuit Design with Through-Silicon-Via: Challenges and Opportunities p42

Lim 3D Circuit Design with Through-Silicon-Via: Challenges and Opportunities p42

clock tree

Clock Tree
Luo, Guojie: Placement and Design Planning for 3D Integrated Circuits, 2011, PhD dissertation, p184 ............... 26

Clock Tree / H-Clock Tree

MINEO, CHRISTOPHER ALEXANDER: Clock Tree Insertion and Verification for 3D Integrated Circuits p84

MINEO, CHRISTOPHER ALEXANDER: Clock Tree Insertion and Verification for 3D Integrated Circuits p84

Clock Tree

H-Clock Tree

Clock Tree

Pavlidis, Vasilis F. and Friedman, Eby G.: Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs p6 GLSVLSI’05, April 17–19, 2005, Chicago, Illinois, USA.

Pavlidis, Vasilis F. and Friedman, Eby G.: Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits, Vol. 97, IEEE No. 1, January 2009 | Proceedings of the IEEE, p18

Pavlidis, Vasilis F. and Friedman, Eby G.: Chapter 5 Physical analysis of NOC topologies for 3D integrated systems p27

Pavlidis, Vasilis F. and Friedman, Eby G.: Physical design issues in 3d integrated technologies, 2010, p21.

Pavlidis, Vasilis F. and Friedman, Eby G.: Timing-driven via placement heuristics for three-dimensional ICs, 29 November 2007, p21...............

Pavlidis, Vasilis F. and Friedman, Eby G.: Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance p9 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 9, SEPTEMBER 2009 1873

Pavlidis, Vasilis F. : Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits p366

V. F. Pavlidis and E. G. Friedman, “Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits,” p18 Proceedings of the IEEE, Vol. 97, No. 1, pp. 123–140, January 2009.

V. Pavlidis, I. Savidis, and E. Friedman, “Clock Distribution Networks for 3-D Integrated Circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, September 2008, pp. 651–654.

V. F. Pavlidis and E. G. Friedman, "Timing Driven Via Placement Heuristics in 3-D ICs," p21 Integration, the VLSI Journal, Vol. 41, No. 4, pp. 489 -508, July 2008.

Pavlidis, Vasilis F. and Friedman, Eby G. 3-D Topologies for Networks-on-Chip p4

Pavlidis, Vasilis F. and Friedman, Eby G. 3-D Topologies for Networks-on-Chip p10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007

Pavlidis, Vasilis F. and Friedman, Eby G. Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits p4 2006 IEEE

V. F. Pavlidis and E. G. Friedman, “3-D Topologies for Networks-on-Chip,” IEEE Transactions on Very Large Integration (VLSI) Systems,Vol. 15, No. 10, pp. 1081-1090, October 2007

Clock Tree / clock H tree
Sekar Monolithic 3D Integrated Circuits p50

Sekar Monolithic 3D Integrated Circuits p50

clock H tree

Clock Tree
SULE, AMBARISH MUKUND. Design of Pipeline Fast Fourier Transform Processors using 3 Dimensional Integrated Circuit Technology, 2007 PhD Thesis p125

Clock Tree
TORKI 3D-IC Integration Developments & Cooperations for servicing p63

TORKI 3D-IC Integration Developments & Cooperations for servicing p63

Clock Tree

Clock Tree

TORKI CAD Tools for 3D-IC and TSV-based designs p33

TORKI CAD Tools for 3D-IC and TSV-based designs p33

Clock Tree

Three-dimensional Integrated Circuits Design, EDA and Architecture
Xie, Yuan et al: Three-dimensional Integrated Circuits Design, EDA and Architecture June 2011 p156...........

Computer Science and Engineering Department, University Park, PA16802, USA

yuanxie@cse.psu.edu

http://www.cse.psu.edu/~yuanxie/

Clock Tree

3D clock tree

3D clock routing tree

zero-skew clock tree for a 3D IC

Clock Tree Design

To leverage the multifaceted bene ts of latency, power, and high density
from interdie vias, researchers have also proposed methods to minimize
the wire length and power for forming a zero-skew clock tree for a 3D
IC. By doing so, the clock signals are directly relayed from other die
layers by routing themselves through the interdie vias, reducing trav-
eling distance by several orders of magnitude. Although this approach
improves the eciency of constructing the clock distribution network {
that is, better routability { it inadvertently introduces another problem
that makes prebond testability much more challenging. The results of
such 3D routing algorithms often generate a clock distribution network,
in which most of the die layers would contain a plethora of isolated clock
islands that are not fully connected.

Testing each prebond layer requires multiple synchronous clock in-
put sources { that is, using multiple test probes to feed those disjoint clock islands during the prebond test phase. Nonetheless, applying mul-
tiple test probes could also undermine the requirement of maintaining
a zero-skew clock tree. As to be discussed in 3D Testing, prebond test
is indispensable for the commercial success of 3D ICs, due to the yield
concern. As a result, with respect to 3D clock tree design, there are two
goals to achieve. First, each prebond layer under test should contain a
fully testable, zero-skew clock tree. Second, a zero-skew clock tree also
must be guaranteed for the nal integrated 3D chip after bonding.

To address this problem, Zhao et al [43] employ a redundancy design
by providing a con gurable, complete 2D clock tree for each layer for
prebond test purposes, while simultaneously maintaining a 3D clock
routing tree for normal operations postbond. On each layer, TSV-
bu ers are used to ensure the zero-skew of 2D clock trees. The 2D
trees are merely used for prebond test and will be gated o afterward.
One drawback of this approach is that the routability could be wors-
ened rather than improved as a result of the redundant clock trees. Kim
et al [44] propose an improved solution using much less bu er resources
with a new tree topology generation algorithm, and the transmission
gate control lines used in [43] are replaced by a specially designed com-
ponent called self controlled clock transmission gate (SCCTG).

Clock Tree
XuHu Modeling and Design Techniques for 3-D ICs under Process Voltage, and Temperature Variations p228.pdf

Clock Tree
Xu, Hu; Pavlidis, Vasilis F., and De Micheli , Giovanni: Skew Variability in 3-D ICs with Multiple Clock Domains, 2011, p4

Clock Tree
Xu, Qiang et al: Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges p7

Clock Tree
Ye 3D Optical Networks-on-chip (NoC) for Multiprocessor Systems-on-chip (MPSoC) p6

Ye 3D Optical Networks-on-chip (NoC) for Multiprocessor Systems-on-chip (MPSoC) p6

clock tree

Clock Tree
Zhang 3D-MMC A Modular 3D Multi-Core Architecture with Efficient Resource Pooling p6.pdf

Clock Tree
Zhou, Lili: A High-Throughput Low-Power Fully Parallel 1024-bit ?-Rate Low Density Parity Check Code Decoder in 3-Dimensional Integrated Circuits p2 2006 IEEE

balanced clock tree

balanced clock tree
Dickerson, Samuel J.: DESIGN OF A 3D INTEGRATED CIRCUIT FOR MANIPULATING AND SENSING BIOLOGICAL NANOPARTICLES Master Thesis 2007 p79 ................
Since such a large number of registers are required to control the electrode array, we designed a balanced clock tree to ensure synchronization of the control logic. We also made the 22
decision to distribute the inverted clock signal through the tree instead of generating it locally within each master-slave flip-flop. This tradeoff doubles the size of our clock tree but results in an overall area savings by eliminating one inverter cell for each bit of each shift register.

Multi Stage Clock Tree

Multi Stage Clock Tree / Zero - Skew Tree

Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................
4 Zero - Skew Tree Construction : : : : : : : : : : : : : : : : : : : : : : : : : : : : 38
5 A tapered interconnect : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 39
6 A Multi Stage Clock Tree Distribution : : : : : : : : : : : : : : : : : : : : : : : : 40

In addition to delay, it is sometimes important to minimize the skew of a tree, i.e., the
maximum di erence between the RC delays at di erent sink nodes in the tree. This is important
in clock trees, since the clock signal should arrive at all clock nodes at the same time for correct
operation of a synchronous digital circuit. Clock skew can be a signi cant part of the total
cycle time. An algorithm for constructing a tree with zero skew, based on the Elmore delay
model, was presented in [48]. The algorithm uses a recursive bottom-up strategy, building up
a zero-skew tree (ZST) by recursively merging zero-skew subtrees. Figure 4 shows a zero skew
tree construction. The original ZST algorithm has undergone improvements to minimize wire
length [47] and to guarantee planarity of the resulting tree [27].

Since clock distribution trees on an MCM can be very large, and heavily loaded, it is very
dicult to drive them with a single driver. Typically, bu ers are introduced at various nodes
in the tree, to avoid having a single very large driver, and to keep the slope of the received
waveform reasonably high. Such multi-stage clock trees introduce some interesting new opti-
mization problems, such as nding the optimal locations for the bu ers, minimizing the number
of bu ers, nding optimal sizes for the bu ers etc. An algorithm for minimizing the number of
bu ers in a given clock tree subject to a clock period constraint is presented in [46]. The basic algorithm is extended to handle upper bound constraints on the skew, and allow area and delay
tradeo s. Figure 6 shows a multi-stage clock tree distribution.

The disadvantage of constructing a matching-based hierarchical zero-skew clock tree is that
the wires dictated by the matching edges in higher level of hierarchy are relatively long and
they may introduce both a severe crosstalk noise due to bu er congestion of the generated tree
topology. The local congestion problem can be eliminated by distributing the bu ers over the
plane with minimum impact on wirelength. By reducing the congestion of bu ers, crosstalk delay
will also be signi cantly reduced. Thus, the authors in [24] investigated the problem of reducing
congestion, wirelength and clock skew during the growth of the clock tree. To take the three
performance constraints into account simultaneously, the bu er distribution was formulated as a
minimum length degree distributed spanning tree problem. An ecient solution to the problem
is proposed in [24]. The proposed algorithm can be applied to MCM clock net routing. H-tree
is preferable for clock distribution in the transmission line mode, since re
ections and crosstalk
can be minimized [2]. Thus, a clock tree routing scheme for hierarchical packaging system (e.g.,
MCM) would be as follows. An H-tree is used for inter-chip clock routing generating a set of
clock sub-sources, each of which is inside each chip. Whereas pins in each chip are interconnected
from the sub-source only inside the routing subregion using the proposed clock tree construction
scheme.

(Symmetric) Clock Trees

(Symmetric) Clock Trees
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

Compression of Clock Tree Browser into simpler hierarchy information ............................... 55

Block diagram of a Delay Lock Loop syncing the leaf of a clock tree with a reference
signal ................................................................................................................................ 63

CTS – Clock Tree Synthesis

Symmetric Clock Trees
The most common method of clocking a large system is by implementing a tree structure
to distribute the clock across the chip with minimal skew. In a general tree, there is a clock input
that serves as the root for the design. From this root, signals fan out across the chip. After this
signal is routed to a subsection of the die, it fans out yet again. In a symmetric clock tree, the
number of fanouts at each clock layer will be the same throughout the chip and will occur at
geometrically symmetric points on the die. Typically, a buffer is present at each fanout point to
drive the subsequent lines. This allows for tighter control of skew and protects against signal
degradation [10]. A simple example of a buffered tree can be seen in Fig. 11.

Terminology

Literature


complete tree

complete tree

BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

Using a complete tree clock distribution, we perform a cut at a given clock level to
produce a lower power 3D distribution on one die. The places where the cut is performed will be
driven by a clock driver from an adjacent die. In this way, we can examine the effect of TSV size

Terminology

Literature


directed tree

Terminology

Literature


fat-tree

Fat H-Tree

fat-tree
Das, Shamik: Design Automation and Analysis of Three-Dimensional Integrated Circuits, PhD thesis, May 2004, p176 .................
N-leaf planar fat-tree network exhibiting O(
p
N) bisection bandwidth.

fat-tree / Fat H-Tree
Matsutani Three-Dimensional Layout of On-Chip Tree-Based Networks p8

Matsutani Three-Dimensional Layout of On-Chip Tree-Based Networks p8

Fat Trees

Fat H-Tree

Terminology

Literature


full tree

full tree
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

Because the focus of this thesis is to enable testing on a single prebond die, the analysis
and clock modeling is confined to a single die. A model of a clock distribution network on a
single prebond die that is not fully connected is first produced. We then add the means to connect
these disconnected networks and compare the results to the same design if it had a full tree
distribution. This is a fair comparison because a full tree distribution on each die is the easiest
and most basic 3D clock distribution scheme because it matches the standard 2D scheme exactly.
Thus, we compare the in-operation power savings and skew during testing to the reference case of

Terminology

Literature


global tree

global tree
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

In the TLM hybrid architecture which can be seen in Fig. 17, a global tree supplies a
lower power global clock to local meshes. This ensures that data registers that communicate
directly can do so with minimal skew. This allows for power saving in the global distribution
because data signals that will travel larger distances may be pipelined anyway, so low global
skew would not be as detrimental to performance.

global tree

Knechtel, Johann et al: Multiobjective Optimization of Deadspace a Critical Resource for 3D-IC Integration IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012, November 5-8, 2012, San Jose, California, USA p8............

Terminology

Literature


Graph Model / Representations for 3D IC Design

H- and X-trees

H-trees

Horizontal Tree (H Tree) and Vertical Tree (V Tree)

H-trees

Ahn, Byung-Gyu et al: Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs p7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.11, NO.4, DECEMBER, 2011

At the floorplan stage, the locations of clock sinks in the soft-macro block are unknown. However, the number of clock sinks is known. The clock sinks are located by using an equal distribution within the block boundaries. After the virtual sinks assignment, H-tree model [8] is used to estimate the clock interconnect of intra-block. The Manhattan distance from the H-tree root to each sink is defined as intra-block-depth.

According to the initial clock topology generated by the H-tree model in the previous step, we apply the 3DMMM/ DME algorithm to estimate the inter-block clock network of 3D ICs. First, the roots of H-tree are regarded as a terminal set. 3D-MMM algorithm [9], which takes the upper bound for TSV count into account, is used to generate the inter-block abstract tree for 3D ICs. During this phase, clock TSV locations are decided. Then, the classic DME algorithm [10] is used to synthesize the virtual clock network. Note that the intra-block-depth needs to be considered in DME algorithm to achieve the zero skew.

H-trees
Benini 3D-MPSoCs architectural and design technology outlook p24.pdf

H-tree, X-tree , and Tapered H-tree

BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

Symmetric Trees
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123
More specifically, symmetric trees are often given names based on the shapes the clock routes make. Two such examples are the H-Tree and the X-Tree as shown in Fig. 12a and Fig. 12b. In both of these tree types, the center point of the structure is fed by a buffered clock signal. This then fans out to the center points of the four quadrants of the chip where another buffer drives another, smaller structure. This continues for several levels of progressively smaller structures until a local buffer drives the clock sinks. Using this methodology with symmetrically sized buffers, each clock signal has traveled the same distance and experienced the same insertion delay. Thus, most trees aim to eliminate the difference between the routing lengths for each leaf node. However, skew will still be present because of load mismatch at the clock sinks and process variations in the metal lines and in the drivers [10].

H-tree
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

The proposed algorithm can be applied to MCM clock net routing. H-tree
is preferable for clock distribution in the transmission line mode, since re
ections and crosstalk
can be minimized [2]. Thus, a clock tree routing scheme for hierarchical packaging system (e.g.,
MCM) would be as follows. An H-tree is used for inter-chip clock routing generating a set of
clock sub-sources, each of which is inside each chip. Whereas pins in each chip are interconnected
from the sub-source only inside the routing subregion using the proposed clock tree construction
scheme.

H-tree

Dilli, Zeynep: PHYSICAL ASPECTS OF VLSI DESIGN WITH A FOCUS ON THREE-DIMENSIONAL INTEGRATED CIRCUIT APPLICATIONS, PhD thesis, 2007, p263 .................

H-trees

3-D Design: Architectures, Methodologies, and Test Circuits
Friedman, Eby G.: 3-D Design: Architectures, Methodologies, and Test Circuits p137 June 11, 2010 2nd Design for 3-D Silicon Integration Workshop ....................

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering

Department of Electrical and Computer Engineering

University of Rochester

Rochester, New York 14627 USA

Phone: (585) 275-1022 Fax: (585) 276-0074

Email: friedman@ece.rochester.edu

www.ece.rochester.edu/~friedman

H-tree, X-tree

Friedman, Eby G.: The Rochester Cube and Other 3-D Circuits for Clock and Power Delivery November 22, 2009 p30 ............

H-tree, X-tree

Friedman, Eby G.: Three-Dimensional Integrated Circuits July 22, 2008 p36

H-trees
Hsu Multi-layer Global Routing Considering Via and Wire Capacities p6.pdf

H-tree
Lin, Mingjie and El Gamal, Abbas: A Routing fabric for monolithically stacked 3D-FPGAs p10.... FPGA’07, February 18–20, 2007, Monterey, California, USA.
Department of Electrical Engineering
Stanford University, CA 94305
f mingjie, abbas g@stanford.edu

H-tree
Miller TSV-Virtualization for Multi-Protocol-Interconnect in 3D-ICs p8

Miller TSV-Virtualization for Multi-Protocol-Interconnect in 3D-ICs p8

H-tree

H-tree
Savidis, Ioannis and Friedman, Eby G.: Test Circuits for 3-D Systems Integration p4

Clock and Power Distribution Networks for 3-D Integrated Circuits

Savidis, Ioannis et al: Clock and Power Distribution Networks for 3-D Integrated Circuits p13

Ioannis Savidis and Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester,
Rochester, New York 14627, USA
{iosavid, friedman}@ece.rochester.edu

Vasilis F. Pavlidis and Giovanni De Micheli
LSI-EPFL
1015-Lausanne, Switzerland
{vasileios.pavlidis, giovanni.demicheli}@epfl.ch

CLOCK DISTRIBUTION NETWORKS FOR 3-D ICS

Distributing the clock signal in 3-D ICs is a complex and challenging task as sequential elements synchronized by the same clock signal can be located on multiple planes [1]. In 2-D circuits, symmetric interconnect structures, such as H- and X-trees, are widely utilized to distribute the clock signal across a circuit [2]. An extension of an H-tree to three dimensions does not guarantee equidistant interconnect paths from the root to the leaves of the tree. The impedance of the TSVs can increase the time for the clock signal to arrive at the leaves of the tree on specific planes as compared to the time for the clock signal to arrive at the leaves of the tree located on the same plane as the clock driver [3]. Consequently, asymmetric topologies can be potential candidates for distributing the clock signal in a 3-D integrated system.

Another fundamental issue in the design of clock distribution networks is low power consumption, since the clock network dissipates a significant portion of the total power consumed by a synchronous circuit [2]. This demand is stricter for 3-D ICs due to the increased power density and related thermal concerns.

A test circuit investigating the distribution of the clock signal has been recently designed. The test circuit is fabricated by the MITLL process which is a fully depleted silicon-on-insulator process (FDSOI). The minimum feature size of the devices in this test circuit is 180 nm, with one polysilicon layer and three metal layers interconnecting the devices on each wafer. The dimensions of the TSVs in this test circuit are 1.75 μm × 1.75 μm [5]. Each block contains about 30,000 transistors and includes the same logic circuit but implements a different clock distribution architecture.

The function of the logic circuit common to the three blocks is to emulate different switching patterns and load conditions for the clock distribution networks under investigation. Random switching patterns are generated in each block by combining pseudorandom number generators and several groups of four-bit counters that switch current loads over different time intervals.

Each of the three blocks includes a different clock distribution structure, which are schematically illustrated in Fig. 1. The dashed lines depict vertical interconnects implemented by TSVs. These architectures combine different topologies, such as H-trees, rings, and meshes [2]. The fabricated 3-D test circuit is illustrated in Fig. 2. The highest operational frequency is 1.4 GHz. Clock skew measurements indicate that the topology in Fig. 1a produces, on average, the lowest skew as compared to the other two topologies. The clock skew among the planes is greater for the local mesh topology (see Fig. 1b) as compared to the H-tree topology, primarily due to the unbalanced clock load for certain local meshes. Alternatively, the clock distribution network that includes the global rings exhibits the highest clock skew among all topologies due to the greater difference in distance that the clock signal traverses on each plane [7].

Fig. 1 Three 3-D clock distribution networks within the test circuit, (a) H-trees, (b) H-tree and local meshes, and (c) H-tree and global rings.

H-tree, X-tree

Savidis, Ioannis et al: Clock and Power Distribution Networks for 3-D Integrated Circuits p13.....................

H-trees
Sun, Hongbin et al: 3D DRAM Design and Application to 3D Multicore Systems 2009 IEEE p12.

buffered H-Tree model

buffered H-Tree model

Souri, Shukri J: 3D ICs Interconnect Performance Modeling and Analysis, Ph.D. Dissertation Draft, Nov 2002, p123
Clock distribution capacitances are calculated using the BACPAC model proposed in [71] by considering a buffered H-Tree model.

Terminology

Literature


interconnect tree

interconnect trees
ALAM, SYED M. et al: Layout-Specific Circuit Evaluation in 3-D Integrated Circuits, Analog Integrated Circuits and Signal Processing, 35, 199–206, 2003, p7 .
The 3D circuits fabricated with wafer-bonding technology have two different types of vertical interconnects as shown in Fig. 1. The inter-wafer vias connect multiple interconnect trees in different wafers. And at the bonding surface, the adjacent metallization layers from two wafers can also be connected with vertical Cu lines. The vertical Cu lines create a new type of trees, referred to as a “3D tree,” which expands between two different wafers in a 3D circuit.
Fig. 1. Cross-section a 3D IC. Here DL and MLs correspond to
device and metal layers, respectively.

This type of via connects a metal layer to a 3D contact point at the top1 of a wafer. In Fig. 2, it is connected with Metal2, the topmost metallization layer of this particular wafer. The connected-to-top via can also connect other metal layers, such as Metal1 or Metal3 to a 3D contact point at the top. When two wafers are bonded on front-to-front, as shown in Fig. 1, a 3D tree is formed if the connected-to-top type vias of the topmost metal layers from the two wafers share the same 3D contact point at the bonding surface.

The connected-to-bottom type via extends between a metal layer and a 3D contact point at the bottom2 of a wafer. In Fig. 2, a connected-to-bottom via connects Metal1 to a 3D contact point. When two wafers are bonded on back-to-front, a 3D tree is formed if a connected-to-bottom via from the top wafer and a connected-to-top via of the topmost metal layer from the bottomwafer share the same 3D contact point. Similarly, two connected-to-bottom type vias of different wafers with the same 3D contact point can also create a 3D tree when they are bonded on back-to-back.

...................

ERNI-3D parses 3D circuit layouts, and extracts both conventional and 3D interconnect trees. It employs the Hierarchical Reliability Analysis approach, and filters out a group of immortal trees (trees that will never fail) using their current-density length products [11,12]. After the filtering process, stringent reliability models are applied to the remaining interconnect trees for computing their median and mean time to failures. Finally, multiple time to failures are combined using a joint probability distribution to report a single reliability figure for the whole chip. Electromigration models applied are based on effects in aluminum interconnects [11,12]. Figure 5 shows a screen shot of ERNI-3D working on a 3D 8-bit Adder layout.

interconnect trees

Pavlidis Timing Driven Via Placement Heuristics in 3-D ICs p21.pdf

Pavlidis, Vasilis F. : Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits p366

Terminology

Literature


interval tree

interval tree
Gupta Yield Analysis and Optimization p29

Terminology

Literature


inter-block abstract tree

inter-block abstract tree

Ahn, Byung-Gyu et al: Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs p7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.11, NO.4, DECEMBER, 2011
According to the initial clock topology generated by
the H-tree model in the previous step, we apply the 3DMMM/
DME algorithm to estimate the inter-block clock
network of 3D ICs. First, the roots of H-tree are regarded
as a terminal set. 3D-MMM algorithm [9], which takes
the upper bound for TSV count into account, is used to
generate the inter-block abstract tree for 3D ICs. During
this phase, clock TSV locations are decided. Then, the
classic DME algorithm [10] is used to synthesize the
virtual clock network. Note that the intra-block-depth
needs to be considered in DME algorithm to achieve the
zero skew.

Terminology

Literature


Load Matched Trees

Geometric Load Matched Trees
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

Another approach to construction low skew clock distributions involves matching the geometry of the network to the clock loads present in the design. These networks are designed by a bottom-up algorithmic approach as opposed to a top-view global approach [10]. Typically, these are constructed using buffered binary trees. To minimize skew, two clock sinks are chosen and the point between the two is calculated where the load from the sink and the clock routing is equal on both sides. At this point, a buffer is placed and this point become an effective clock sink for the next highest clock level. In this way, a load-balanced tree is recursively built to minimize skew. This step-by-step process can be seen in Fig. 13. This method is popular in the automatic synthesis and layout of clock network which is typically seen in commercial place and route CAD tools for ASIC designs.

In this way, a load-balanced tree is recursively built to minimize skew. This step-by-step process can be seen in Fig. 13. This method is popular in the automatic synthesis and layout of clock network which is typically seen in commercial place and route CAD tools for ASIC designs.

Terminology

Literature


local tree

local tree

local tree
Areibi, Shawki; Xie, Min and Vannelli, Anthony: AN EFFICIENT RECTILINEAR STEINER TREE ALGORITHM FOR VLSI GLOBAL ROUTING 1997 p6

Shawki Areibi
School of Engineering
University of Guelph
CANADA N1G 2W1
E-mail: sareibi@uoguelph.ca

Min Xie and Anthony Vannelli
Electrical Engineering Dept
University of Waterloo
CANADA N2L 2G1
E-mail: vannelli@cheetah.vlsi.uwaterloo.ca

Mesh + Local Trees (MLT)
Tree + Local Meshes (TLM)

BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123
Hybrid Clock Distributions
As if often the case when two competing solutions to a problem each have strengths and
weaknesses, it can be advantageous to develop a hybrid clock distribution network that seeks to
exploit the strengths of both a mesh and a tree based distribution while avoiding the costs. These
types of hybrid networks are referred to as Mesh + Local Trees (MLT) and Tree + Local Meshes
(TLM) [4].

local tree

Knechtel, Johann et al: Multiobjective Optimization of Deadspace a Critical Resource for 3D-IC Integration IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012, November 5-8, 2012, San Jose, California, USA p8............

Terminology

Literature


LT-Tree

LT-Tree
Salek A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm p6

Terminology

Literature


cost tree

minimum cost tree
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


multicast tree

delay-oriented Steiner multicast tree

the optimum multicast tree
Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.
To address the 3D-NoC synthesis problem, we formulate the problem as a combination
of a rip-up and reroute procedure for routing flows and a router merging
procedure for optimizing network topologies. The key part of the algorithm is a ripup
and reroute procedure that routes multicast flows by way of finding the optimum
multicast tree on a condensed multicast routing graph using the directed minimum
spanning tree formulation and the efficient algorithms [36, 37]. Then a router merging
procedure follows after to further optimize the implementation and reduce cost.
The router merging algorithm iteratively considers all possible mergings of two
routers connected with each other and merges them if the cost of the resulting topology
after merging is reduced.

multicast tree / the optimum multicast tree

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25
S. Yan (?)
University of California, San Diego, CA, USA
e-mail: shyan@ucsd.edu

The first method is Statically Scheduled Routing. For our NoC solutions, the required
data rates are specified and the routes are fixed. In this setting, data transfers
can be statically scheduled along the pre-determined paths with resource reservations
to ensure deadlock-free routing [44, 45]. The second method is Virtual Channels
insertion. As shown in [46], a necessary and sufficient condition for deadlock-free
routing is the absence of cycles in a channel dependency graph. In particular, we use
an extended channel dependency graph construction to find resource dependencies
between multicast trees3 and break the cycles by splitting a channel into two virtual
channels (or by adding another virtual channel if the physical channel has already
been split). The added virtual channels are implemented in the corresponding routers.
We applied this method into our NoC synthesis procedure and we have found
that virtual channels are rarely needed to resolve deadlocks in practice for custom
networks. In all the benchmarks that we tested in Sect. 8.8, no deadlocks were found
in the synthesized solutions. Therefore, we did not need to add any virtual channel.

Terminology

Literature


Multilevel Tree
Pangracious Designing a 3D Tree-based FPGA Optimization of Butterfly Programmable Interconnect Topology Using 3D Technology p8.pdf

Terminology

Literature


multi-crossing tree

multi-crossing tree
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


net subtree

Terminology

Literature


O-Tree

O-Tree
Chen 3D-Floorplanning for Via and Wire length Minimization p50

O-Tree

Cong, Jason; Wei, Jie and Zhang, Yan: A Thermal-Driven Floorplanning Algorithm for 3D ICs p8 Dec 2004 ...............

Floorplanning is a well-studied problem for 2D circuit design.
Floorplans can be classified into two categories in terms of block
configuration, slicing structure and non-slicing structure. Nonslicing
structure is more general but requires more complicated
representation data structures. Floorplanning algorithms are
normally based on simulated annealing (SA) optimization scheme,
using various kinds of floorplan representations. Many
floorplanning representations for 2D non-slicing general floorplan
have been proposed including sequence pair [18], BSG [16], B*-
Tree[4], O-Tree[11], CBL[12], TCG [17], etc. TCG representation
is effective in wirelength and area optimization since the relative
distances of the modules are implicitly stored in addition to the
relative positions between modules.

Terminology

Literature


parallel-prefix tree

Terminology

Literature


partition tree

partition tree
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


power tree

power tree
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

The MLT hybrid architecture, as seen in Fig. 16, ensures low global skew across the chip.
At the lower levels, the lower power tree is preferred here because the distance between points is
not large enough to cause considerable skew.

Terminology

Literature


P-Tree

P-Tree / Permutation- Constrained Routing Tree or P-Tree P-Tree
Salek A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm p6

Terminology

Literature


RC tree

RC tree

Boese High-Performance Routing Trees With Identi ed Critical Sinks p6

RC tree
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................
VLSI interconnect delay models either use the lumped capacitor delay model or the RC tree
16
model. The traditional \lumped capacitance" model for an interconnect, in which the delay of
a net is proportional to its length, is not accurate enough at the MCM level. Since the e ective
resistance of o -chip drivers is comparable to the resistance of the interconnect wires, the wire
resistance signi cantly a ects the delay and cannot be ignored. Also the delay in a multi-
terminal net is not only proportional to the netlength but also to the net topology. Hence we
can say that there is a need for more accurate and elaborate delay models for MCMs compared
to general VLSI design. The next few paragraphs outline this in greater detail. For a detailed
description of the interconnect delay models for MCMs please refer to [42].

RC tree
Cong Performance-Driven Global Routing for Cell Based IC’s p4

RC tree
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


rectilinear tree

rectilinear tree
OBENAUS, STEFAN THOMAS and SZYMANSKI, TED H.: Gravity: Fast Placement for 3-D VLSI, ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003, Pages 298–315., p18.

rectilinear tree
Zhang, Tianpei: Routing Issues in Nanometer-scale Integrated Circuits A PhD Dissertation September 2006 p160...........

Terminology

Literature


redundant tree

redundant tree
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123


RLC trees

RLC trees
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................
For reasonable accuracy, interconnects at the MCM level must be modeled as distributed
RLC trees. In this model, each wire segment in the tree is represented by a distributed-RLC
section, which consists of a distributed resistance and inductance in series, and a distributed
capacitance in parallel to ground. For delay estimation purposes, each distributed section is
typically approximated by splitting it into several lumped RLC sections. A rst order model
for the delay of an RLC tree is the Elmore model [14]. This model ignores the inductance
component, and also ignores higher order e ects such as \resistance shielding". However, it
has been demonstrated in [3] that this delay model has high \ delity", i.e., optimization done
based on this model tends to lead to high-performance routes. Figure 2 shows the di erent delay
models used. In [42] the author has developed a second order delay model for multi-terminal
interconnects which demonstrates the e ect of line inductance on second order delay models.

Literature


Routing Tree

routing trees

3D routing trees
routing trees in 3d ic
routing trees in 3d integrated circuits
routing trees in three dimensional integrated circuits
routing trees in 3d VLSI
routing trees in three dimensional VLSI
VLSI IC routing trees

Manhattan Routing Tree

rectilinear Steiner routing tree

minimum radius routing tree

minimum-cost routing tree

A routing solution of a net is a spanning tree T (called the routing tree of the net) which connects all of the terminals in the net.

Routing Tree

Routing Tree

Graph Models for Global Routing Grid Graph Nov 2002 p17.

The Routing-Tree Problem

Problem: Given a set of pins of a net, interconnect the pins by a "routing tree."

gate array standard cell building block

Minimum Rectilinear Steiner Tree (MRST) Problem: Given n points in the plane, find a minimum-length tree of rectilinear edges which connects the points.

MRST(P) = MST(P ∪ S), where P and S are the sets of original points and Steiner points, respectively.

Routing Tree

Areibi, Shawki; Xie, Min and Vannelli, Anthony: AN EFFICIENT RECTILINEAR STEINER TREE ALGORITHM FOR VLSI GLOBAL ROUTING 1997 p6 ....................... 4

Shawki Areibi
School of Engineering
University of Guelph
CANADA N1G 2W1
E-mail: sareibi@uoguelph.ca

Min Xie and Anthony Vannelli
Electrical Engineering Dept
University of Waterloo
CANADA N2L 2G1
E-mail: vannelli@cheetah.vlsi.uwaterloo.ca
K. D. Boese, A. B. Kahng, and G. Robins. \ High-Performance Routing Trees with Identi ed Critical Sinks ". In Proceedings of Design and Automation Conference, pages 182{187, June 1993.

rectilinear Steiner trees

K Rectilinear Steiner Trees (K-RST)

minimal rectilinear steiner tree (MRST)

minimum steiner tree

rectilinear MST - rectilinear minimum steiner tree

spanning tree

K-rectilinear spanning tree

minimal spanning tree

k rectilinear minimum spanning tree (K-RST)

coarse grid graph
As we move to deep sub-micron designs below 0.18 microns, the delay of a circuit, as well as power dissipation and area, is dominated by interconnections between logical elements (i.e. transistors)[1]. The focus of this paper is on the global routing problem. Both global and channel routing are NP-hard[2]; therefore, all existing solution methodologies are heuristics. The main aim is to develop an efficient K Rectilinear Steiner Trees (K-RST) algorithm. A k-RST routine is developed to generate a set of rectilinear Steiner trees for each net. The K-RST uses local tree segment transformations to ensure that there is no duplication of routing trees for a net. The shortest tree for a net is in general 11% shorter than that of the minimal spanning tree, which leads to area savings.
As feature sizes are scaled down, devices are much faster. Which results in an increase of clock rate – i.e. smaller cycle time. The interconnect delay can consume from 50% to 70% of the clock cycle [9, 10]. Therefore, to stay competitive, the routing trees for each net have to statisfy delay requirements, which require high performance interconnect topologies. Future implementation should consider the generation of high performance trees for each net.

Routing Tree / critical-sink routing tree / Elmore routing tree
Boese High-Performance Routing Trees With Identi ed Critical Sinks p6

Routing Tree

Cong, Jason: 3D IC Design Tools and Applications to Microarchitecture Exploration, 10/8/2007, p71 ....
Jason Cong
UCLA Computer Science Department
cong@cs.ucla.edu
http://cadlab.cs.ucla.edu/~cong
RCN graph
Init Routing Tree Generation

Routing Tree

Cong Performance-Driven Global Routing for Cell Based IC’s p4

Routing Tree

Cong, Jason: Thermal-Aware 3D IC Physical Design and Architecture Exploration p56
Jason Cong
UCLA Computer Science Department
cong@cs.ucla.edu
http://cadlab.cs.ucla.edu/~cong

RCN graph

one trunk Steiner tree
Init Routing Tree Generation

Routing Tree

Cong, Jason and Zhang, Yan: Thermal via planning for 3-D ICs, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2005, pp. 745-752............ p8

Jason Cong
Computer Science Department, UCLA
Los Angeles, CA 90095
cong@cs.ucla.edu

Yan Zhang
Computer Science Department, UCLA
Los Angeles, CA 90095
zhangyan@cs.ucla.edu
routing tree
The TTS-via number needed is first estimated at the coarsest level. The TTS-via planning algorithm is first called at the coarsest level after the initial routing tree generation to reduce temperature as much as possible. The refinement process then starts with the coarsest level solution and moves from the coarser level to the finer level in reverse order from the coarsening process. During each refinement, the TS-via planning algorithm will repeatedly refine the TS-via distribution within each coarser-level tile stack so that the coarser level solution is preserved. If Tinput is not met at the end of refinement, a proportional TS-via number adjustment based on binary search and the full thermal resistive model will be called. Details of the multilevel routing and TS-via optimization algorithm are available in [7].

Routing Tree

Deza, Antoine et al: Global Routing in VLSI Design Algorithms, Theory, and Computational Practice JCMCC 12 May 2011 p25.

Email addresses: deza@mcmaster.ca (Antoine Deza),

cdickson@bedlamgames.com (Chris Dickson),

terlaky@lehigh.edu (Tam?as P Terlaky),

vannelli@uoguelph.ca (Anthony Vannelli),

Hu.Zhang@rbccm.com (Hu Zhang).

lattice graph

planar lattice graph

planar edge-weighted lattice graph

virtual layer graph

grid graph

parallel grid graph

Steiner trees

minimum Steiner trees

rectilinear minimum Steiner tree

Steiner minimal tree

routing trees

K trees

minimum spanning tree
Additionally, we have also developed a class of heuristics to reduce running time as well as to improve the solution quality. The idea is to conˉne a certain percentage of the total nets to a single tree generated in the ˉrst iteration. We investigate two approaches for choosing nets in non-decreasing bounding-box area order or in non-decreasing sum of bounding-box dimensions order such that their routing trees are ˉxed throughout the algorithm. We ˉnd that using the heuristic of bounding-box area, we can decrease the over°ow by up to 25% as well as reducing the wire-length by up to 5%. Fixing based on the sum of bounding-box dimensions is also able to reduce over°ow by up to 20%, while making no sacriˉces in terms of wire-length.
We now evaluate the set of heuristics that involve ˉxing the routing trees for a certain percentage of the nets after the ˉrst iteration. The graphs in Figure 9 show the results for ˉxing nets based on their bounding box area. The x-axis shows the percentage of the total nets that are ˉxed after the ˉrst iteration. The y-axis shows the scaled values of the tree property we wish to evaluate. The three tree properties we focus on are wire-length, edge over°ow (as a percentage of the total number of edges) and maximum edge congestion, also known as maximum routing density (MRD). We scale each y-value to the reference value which occurs when we ˉx none of the nets. We can make several observations from these graphs. First, we can see that for almost all instances, the wire-length is inversely related to the percentage of nets we ˉx. This is intuitive as in the ˉrst iteration, the nets will be short. As we progress throughout the algorithm, the nets grow in length to detour around congested areas. If we ˉx nets after the ˉrst iteration, these nets will not grow in length. However, we must be careful as ˉxing too many nets will cause congested edges that can never be feasible. This is illustrated in Figure 9(e). We can see that as we ˉx too many nets, we have edges that are very highly congested. It should also be noted that in Figure 9(c), we see that ˉxing nets does reduce the total number of infeasible edges. On average, it appears that the 50% to 70% range is optimal for reducing the total number of over°owed edges.
Another considered heuristic is based on ˉxing routing trees for nets with small sums of bounding box dimensions. Figures 9(b), 9(d), and 9(f) illustrate the results of these tests. For our benchmark set, this heuristic appears to work well at reducing the number of infeasible edges, however the results for reducing the wire-length were mixed. We can see that ˉxing too many nets indeed reduces the wire-length, but we pay the price in terms of feasibility. We see that ˉxing 80% or more of the nets causes some edges to be highly congested. This is seen in Figure 9(f).

Fig. 9. Heuristics used to ˉxed a given percentage of nets

Routing Tree / Manhattan Routing Tree / rectilinear Steiner routing tree
Gupta Yield Analysis and Optimization p29

Routing Tree

Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Steiner tree

minimal Steiner tree

Minimum weighted Steiner tree

weighted rectilinear Steiner tree

minimum weight Steiner tree

minimum weighted rectilinear Steiner tree (WRST)

rectilinear Steiner trees (RST)

Steiner minimum tree

rectilinear Steiner minimum tree (RSMT)

Steiner min-max tree (SMMT)

spanning tree

minimum spanning tree (MST)

rectilinear minimum spanning tree

routing trees

minimum cost tree

partition tree

binary tree

RC tree

multi-crossing trees

routing graph

extended routing graph

dual graph

floorplan graph

grid graph

cell graph

tile graph

connection graph

net connection graph

timing graph
As multiple nets are routed over the routing graph G, a common boundary between two neighboring grid cells may be crossed by wires belonging to different nets. In terms of the graph representation, this implies that the routing trees for these nets utilize a common edge e ∈ E. The number of wires that utilize an edge e ∈ E is called the flow (or demand), f(e), on the edge. The number of available routing tracks, which forms an upper bound on the allowable demand, is referred to as the boundary capacity (or supply), u(e). The ratio of flow to capacity f(e)/u(e) for an edge is referred to as the density or congestion, λ(e). If f(e) > u(e), then the overflow on the edge is defined as φ(e) = f(e)?u(e); otherwise the overflow is zero. The most fundamental statement of the global routing problem is to route all of the nets to ensure that for each edge e corresponding to a cell boundary, the number of wires across it does not exceed its routing capacity, i.e., φ(e) = 0, ?e ∈ E.
=================================

Both maze routing and line probe methods are designed for connecting two pin nets. However, in practice, nets with more than two pins are often encountered in the routing problem. A common approach in dealing with a multi-pin net is to decompose it into a set of two-pin nets. One way of performing this decomposition is to begin with constructing a minimum spanning tree (MST) over the pins, and to maze-route each pair of pins that corresponds to an edge in the MST. In Figure 4(a), a possible solution using this procedure for routing a three-pin net, decomposed into two two-pin subnets, is shown. It is easily seen that such a procedure may not lead to the best routing quality. The wire length of a routing tree can often be reduced by introducing extra nodes in addition to the given pins, and constructing an MST over all of these nodes. The added nodes are called Steiner nodes, and an illustration is shown in an example in Figure 4(b).

Figure 4: A three pin net connected by (a) a spanning tree and (b) a Steiner tree.
===================================

3.3 0-1 integer linear programming

Global routing may be formulated as a special type of optimization problem, called a zero-one integer linear programming (0-1 ILP) problem [61]. For a set of candidate routing trees Ti = {Ti,1, Ti,2, ...} for net Ni, we use variable xi,j to indicate if tree Ti,j is selected for net Ni. The global routing problem can then be formulated as:
Minimize ?λ
Subject to: PTi,j∈Ti xi,j = 1, ?Ni ∈ N
Pi,j:e∈Ti,j xi,j ≤ ?λu(e), ?e ∈ E
xi,j = {0, 1}, ?Ni ∈ N, ?Ti,j ∈ Ti

The first constraint, along with the restriction of the xi,j ’s to {0, 1}, requires that one tree be chosen for each net. The second constraint and the objective together ensure that the maximum congestion is minimized.
===================================
The algorithm sorts the nets according to the perimeter of their bounding box and routes one net at a time, with the nets that have a smaller bounding box being routed earlier. The routing tree construction is carried out on a routing graph of the type described in Section 2, with the edge weights on the graph being proportional to the wire congestion. For a certain net, a cell is called terminal cell if it contains a pin of this net; otherwise, it is called non-terminal cell. An optimal Steiner min-max tree that spans the net on the routing graph is obtained through a two-step procedure in polynomial time. In the first step, a minimum spanning tree over all of the cells in the routing graph is constructed. In the second step, any degree-one non-terminal cells are eliminated from this MST. It can be proven that the resulting tree is an optimal Steiner min-max tree. The edge weights are updated dynamically after the routing of each net, reflecting changes in the congestion.
===================================
The simulated annealing technique is applied to global routing in [84], where only two-pin nets are considered and the number of bends for each net is no more than two. In the well-known TimberWolf package [76], simulated annealing is applied to both placement and global routing. In this package, a set of candidate routing trees is created for each net and one of the trees is randomly chosen as the initial solution. Each move implies a switch from one tree to another for a net. The cost to be minimized is the total wiring overflow over the entire routing graph. The net whose topology is to be changed by a move is randomly chosen from a grid cell boundary where an overflow exists.
===================================

In [65], Meixner and Lauther reroute a set of nets simultaneously using a single commodity min cost network flow formulation, so that the net ordering problem in rerouting is avoided. The method successively considers each node v′ ∈ V for a routing graph G = (V,E) and reroutes the nets that have either a sink node or a Steiner node with degree greater than two at v′. For each such net, its routing edges from v′ to the next sink or Steiner node with degree greater than two are ripped up, leaving behind a set of partial routing trees. For example, two nets N1 and N2 may leave behind the trees T1 and T2, respectively, shown in Figure 12(a).

Figure 12: An example of rerouting using a network flow model.
The problem is now to connect nodes at v′ to subtrees T1 and T2 for nets N1 and N2 without causing a wiring overflow, and simultaneously minimizing the wire length. To solve this problem, the partial routing graph is transformed into a network flow model as shown in Figure 12(b). Each undirected edge is mapped on to a pair of directed edges whose capacity is the corresponding wiring capacity and whose cost is the edge length. Two pseudo nodes v1 and v2 are added for nets N1 and N2, respectively, together with a target node. Every node in partial tree Ti is connected to the node vi, i = 1, 2, by means of a directed edge, and finally, each vi is connected to the target node. These edges all have a cost of zero and capacity of one. The node v′ serves as the source node, and a minimum cost flow for this network is determined for a total flow of p units through the network, where p is the number of partial routing trees. Such a flow can be used to determine an optimal solution, if it exists, that satisfies wiring capacities and minimizes the wire length. A sample solution for our example is illustrated in Figure 12(c).
================================
Over this network, k commodities must be transported from some vertices to other vertices. In global routing, we can treat each net as a commodity and we can say that there is a set of N = {N1,N2, ...,Nk} commodities that are to be shipped. For each commodity Ni, a certain amount di, namely the demand, is required to be shipped. In global routing, each Ni corresponds to a net with more than one pin and each di is always one. Each edge has a flow capacity u(e) and cost c(e), which have the same interpretation as in the global routing problem formulation. The routing can be expressed in terms of either edges or trees. In the edge-based expression, a variable fi(e) represents the amount of flow passing through edge e ∈ E. Note that fi(e) is always non-negative in an undirected network while it can be any real number for a directed network. The tree-based expression assumes that there is a set of possible routing trees Ti = {Ti,1, Ti,2, ...} for each net Ni. The binary variable xi,j is set to one if Ti,j ∈ Ti is selected for net Ni; otherwise, xi,j is zero. Of course, it is impractical to enumerate all of the possible trees and these trees are usually generated on the fly in practice.
================================

At the next level, the four super cells in level one are partitioned again as shown in the darkened lines in Figure 21(f). The corresponding routing graph is shown in Figure 21(g), where the solid edges are expanded from each super node in the previous hierarchical level and the dashed edges are expanded from the super edges of the previous hierarchical level. The routing on the cells expanded from same super node is similar to the H4 routing introduced earlier. The four super nodes in level one result in the routing network depicted in Figure 21(h). Note that for each net, the routes chosen at the previous level are transformed into a reduced routing graph as shown in Figure 21(h). A Steiner tree algorithm on this reduced routing graph is applied to join the trees in the forest to form the routing tree at the current level, as shown in Figure 21(i). This process is repeated until the hierarchy proceeds down to the level of the original building blocks. The final routing of this particular example is displayed in Figure 21(j). For the problem of routing k nets for n macros, the computational complexity of this algorithm is O(kn2).

Figure 21: An illustration of hierarchical routing for custom design.
======================================

The delay model employed in TIGER uses an upper bound of the signal propagation delay in an RC tree, defined as follows. Let Rd denote the driver resistance and CL the load capacitance for each sink. The wire resistance and capacitance per unit length are r and c, respectively. Consider a net N = {v0, v1, v2, ...}, where v0 is the source node and others are the sink nodes for which we construct a routing tree T over net N with wire length of W. For a sink vi ∈ N, if the routing path length from source v0 to vi is pr(v0, vi), then the delay upper bound is given as:

tup(vi) = β(Rd + rpr(v0, vi))(cW + CL) (10)
where β = 2.21, which represents the point at which the signal reaches 90% of its final value.
======================================

One of the ultimate objectives of timing-driven design is to achieve a specific clock cycle time, so that each register-to-register delay along each path is less than a constraint. This is referred to as a path-based constraint. There are typically multiple nets along a path between two adjacent stages of registers, as illustrated in the example in Figure 26, where the critical path is (v1, v2, v3, v4) and nets N1 and N2 are along that path. In contrast, in net-based approaches, the path delay constraint is decomposed into a set timing budgets assigned to the nets. If these budgets are allocated poorly, some nets located in congested areas may not have adequate timing slack to achieve a feasible routing to avoid the congestion. In TIGER, the routing tree is chosen so that the timing constraint along the critical path is always satisfied, and this provides greater flexibilities than the net-based constraints.

Figure 26: An example of a timing graph.
======================================

After the initial routing, where each net is routed to meet its timing constraint without considering congestion, the congestion is reduced through a hierarchical bisection and assignment process similar to [64]. For a set of trees in Figure 29, their soft edges are routed through the channels along the cutline, as in Figure 30. The assignment in [38] is based on routing each soft edge through the channels. Due to the complexities associated with timing constraints, the routing through the channel cannot be implemented through linear assignment as in [64]. The assignment problem is solved through a 54 network flow formulation, in which only those assignments that will not cause delay constraint violations constitute the legal candidates. Some assignments may force a wire to have a detour, and the timing slack of its corresponding net will be reduced. In the network flow formulation, the cost of each assignment is defined to be proportional to the slack consumption. If a routing tree has multiple soft edges crossing the cutline, then whether a soft edge can be elongated or not depends on whether its sibling edges have been elongated and if so, how far they have been elongated, since they all share the a common timing constraint and compete for a common timing slack resource. To resolve this scenario, this work identifies the congested area along the cutline by running a max-flow algorithm on the partially constructed network. The soft edges in the multi-crossing trees are elongated to permit an increase in the max-flow at the min-cut, by elongating them to pass through less congested areas to allow a feasible routing.

Figure 29: Assigning soft edges to each cell boundary along the thickened cutline.

Figure 30: A sample solution to the assignment problem in Figure 29.

C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng, and D. Karger. Prim-dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Transactions on Computer-Aided Design, 14(7):890–896, July 1995.

K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins. Near-optimal critical sink routing tree constructions. IEEE Transactions on Computer-Aided Design, 14(12):1417–36, December 1995.
"""""""""""??????????????????????

Routing Tree

Li: Yih-Lang (李毅郎): Modern 3-D Global Routing and Parallelism on X86 Multi-Core Platform Dec 2009 p70.

Routing Tree

Lin, Mingjie and El Gamal, Abbas: A Routing fabric for monolithically stacked 3D-FPGAs p10.... FPGA’07, February 18–20, 2007, Monterey, California, USA.
Department of Electrical Engineering
Stanford University, CA 94305
f mingjie, abbas g@stanford.edu

routing graph

routing tree

H-tree

The routing algorithm is described in Algorithm 1. The algorithm initially routes one net at a time using the shortest path it can nd without considering interconnect segment or logic block pin overuse. Each iteration of the router consists of sequential net rip-up and re-route according to the lowest cost path available. The cost of using a routing resource is a function of its current overuse and any overuse that occurred in prior routing iterations. By gradually increasing the cost of an oversubscribed routing resource, the algorithm forces nets with alternative routes to avoid using that resource, leaving it to the net that most needs it.

Algorithm 1 Congestion/Delay Routing Algorithm

1: Aij 1 for each signal net i and each sink j
2: while shared routing nodes exist do
3: for all nets i do
4: rip up routing tree RTi
5: initialize the queue PQ
6: for all sinks tij do
7: enqueue each node n in RTi at costs Aijdn to PQ
8: while tij is not found do
9: dequeue node m with the lowest cost from PQ
10: for all fanout node n of m do
11: if node n is unseen then
12: mark node n as seen
13: enqueue n to PQ with the cost of Aijdn+
(1 ?? Aij)dnpn
14: end if
15: end for
16: for all node n in the routed path tij to sj do
17: update the cost of node n
18: add n to RTi
19: end for
20: end while
21: end for
22: mark all nodes in PQ as unseen
23: update Aij for net i
24: end for
25: end while

Routing Tree / global routing trees
Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8
Jacob R. Minz, Somaskanda Thyagaraja, and Sung Kyu Lim
School of Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA
jrminz@ece.gatech.edu

floor connection graph

Floorplan Connection Graph

uniform grid graph

resource graph

routing resource graph

Layer Constraint Graph (LCG)

global routing trees

EXPERIMENTAL RESULTS

We implemented our algorithm GROUTE in C++/STL and ran experiments on a Dell Dimension 8800 Linux box. Our test cases are generated using our multi-layer SOP floorplanner on GSRC benchmark circuits [9]. The number of layer is fixed to four. Our layer usage results are based on the tile density w=10. The RSA/G-based global routing trees are generated based on 10×10 unless otherwise specified. We ran our algorithms for channel assignment and pin assignment on GSRC benchmarks and measured its solution quality as the values obtained for the various objectives. For our initial experiments, we have not taken the I/O layer into consideration. All the benchmarks completed in less than a few minutes. So we do not explicitly report the runtimes.

Routing Tree

Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8........................

flow graph

routing graph

Routing Tree

Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

grid graph

flow graph

routing graph

routing resource graph

Steiner trees

routing tree
Rectilinear Steiner arborescence creates a routing tree with minimum source to sink distances for all sinks, and the weight of the tree is also minimum. It was shown that constructing minimal rectilinear Steiner arborescence is NP-complete [13]. We modify the RSA/G heuristic [11] to consider congestion-driven weights during the arborescence construction for simultaneous performance and congestion consideration. Our algorithm starts by constructing the weighted shortest path subgraph for a given net to be rerouted by finding out all shortest paths from the source to sink in . The weight is based on the current usage of the routing resource graph. The nodes in the subgraph are ranked according to the weighted distance from the source node (higher distance translates to higher ranks). The heuristic constructs the topology by considering the nodes in descending order of their ranks and merging them iteratively to form Steiner nodes. During the tree construction we do not allow merging at the routing nodes that are occupied by the existing waveguides.

Routing Tree

Salek A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm p6

Salek A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm p6

Routing Tree

buffered Steiner tree

rectilinear Steiner tree

buffered rectilinear Steiner tree

LT-Tree

Permutation- Constrained Routing Tree or P-Tree P-Tree

A-Tree

global routing trees

global routing trees / Elmore Routing Tree (ERT) / Steiner Elmore Routing Tree (SERT)
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

routing graph

channel graphs

global routing trees

Elmore Routing Tree (ERT)

Steiner Elmore Routing Tree (SERT)

spanning tree

Steiner trees

minimum Steiner tree

performance-oriented minimum rectilinear Steiner tree

A - Tree

H-tree

clock trees

Multi Stage Clock Tree

zero-skew clock tree

Zero Skew Tree

RC tree

RLC trees

Arborescence trees
The nal step in the physical design process is routing which usually consists of global rout- ing, layer assignment and detailed routing [42]. The global routing step assigns nets or wires to di erent routing regions. Whereas the router in the detailed routing step actually nds a geometric path for each net and routes the terminals connected by the net. The primary goal of the global routing step is to reduce the length of the global routing trees since this reduces the area and delay. On the other hand, the layer assignment problem, which is in itself an NP complete problem, is a step in the routing process where each net is assigned to an x-y layer pair subject to the feasibility of routing the nets on a grid. The layer assignment step is important as it determines the number of layers in an MCM and hence the cost and the cooling mechanism required.
K. D. Boese, A. B. Kahng, and G. Robins. \ High-Performance Routing Trees with Identi ed Critical Sinks ". In Proceedings of Design and Automation Conference, pages 182{187, June 1993.

Multicast Routing Tree

Multicast Routing Tree (MRTree) / condensed multicast routing graph

Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

condensed multicast routing graph

communication demand graph

directed hypergraph

Routing Cost Graph

router cost graph

connectivity graphs

channel dependency graph

extended channel dependency graph

multicast tree

optimum multicast tree

Steiner tree

delay-oriented Steiner tree

minimum spanning tree

directed minimum spanning tree

rooted directed minimum spanning tree

minimum directed spanning tree

To address the 3D-NoC synthesis problem, we formulate the problem as a combination of a rip-up and reroute procedure for routing flows and a router merging procedure for optimizing network topologies. The key part of the algorithm is a ripup and reroute procedure that routes multicast flows by way of finding the optimum multicast tree on a condensed multicast routing graph using the directed minimum spanning tree formulation and the efficient algorithms [36, 37]. Then a router merging procedure follows after to further optimize the implementation and reduce cost. The router merging algorithm iteratively considers all possible mergings of two routers connected with each other and merges them if the cost of the resulting topology after merging is reduced.

Fig. 8.6 Illustration of the RIPUP-REROUTE procedure. a Initial connectivity. b RCG. c MRG. d MRTree. e Connectivity before reroute e7. f Connectivity after reroute e7

This RIPUP-REROUTE process is repeated for all the flows. The results of this procedure depend on the order that the flows are considered, so the entire procedure can be repeated for several times to reduce the dependency of the results on flow ordering2. Once the path of each flow is decided, the size of each router, the links that connect the routers are determined. Those routers and links constitute the network topology. The total implementation cost of all the routers and links in this topology is evaluated and the network topology is obtained.

In the RIPUP-REROUTE, each multicast routing step is formulated as a minimum directed spanning tree problem. Two important graphs, Multicast Routing Graph (MRG) and Multicast Routing Tree (MRTree), are used to help facilitate the rip-up and rerouting procedure. They are defined as follows.

Definition 4 A Multicast Routing Tree (MRTree) is the Minimum Directed Spanning Tree for multicast routing graph  Γ(N, A) with s ∈ N as the root.

Definition 4 A Multicast Routing Tree (MRTree) is the Minimum Directed Spanning
Tree for multicast routing graph (N, A) with s ∈ N as the root.

Once the RCG is constructed, the multicast routing graph (MRG) for the flow is generated from RCG (line 5). MRG is build by including every source and destination router of the flow as its nodes. For each pair of the nodes in MRG, the least cost directed path with least power consumption on RCG is found for the corresponding routers using Floyd-Warshall’s all pair shortest path algorithm and the cost is assigned as edge weight to the edge connecting the two nodes in MRG. Then the Chu-Liu/Edmonds algorithm [36, 37] is used to find the rooted directed minimum spanning tree of MRG with the source router as root. A rooted directed spanning tree of a graph is defined as a graph which connects, without any cycle, all n nodes in the graph with n ? 1 arcs such that the sum of the weight of all the arcs is minimized. Each node, except the root, has one and only one incoming arc. This directed minimum spanning tree is obtained as the multicast routing tree (MRTree) so that the routes of the multicast flow follows the structure of this tree. The details of Chu- Liu/Edmonds Algorithm is summarized in Algorithm 3. The multicast routing for flow f in RCG can be obtained by projecting MRTree back to RCG by expanding the correspond arcs to paths. A special case is when f is a unicast flow with source s and destination d. In this case, MRG will just consist of two nodes, namely s and d, and one directed arc from s to d. Therefore, the routing between s and d in RCG is simply a shortest path between s and d.

After the path is determined, the routers and links on the chosen path are updated.

As an example, Fig. 8.6b shows the RCG for rerouting the multicast flow e7. For clarity, only part of the edges are shown for RCG. The MRG and MRTree for e7 are shown in Fig. 8.6c, d respectively. By projecting MRTree back to RCG, the routing path for e7 is determined, namely e7 is bifurcates in the source router R4 to reach R6 and v6, then it transferred over the network link between R4 to R2 to reach v2, and then bifurcates to reach R5 and v5. The real physical connectivity between routers before and after rip-up and rerouting e7 are also shown in Fig. 8.6e, f. From them, we observe that the link between R4 and R5 and their corresponding ports are saved thus the power consumptions are reduced after rerouting e7 by utilizing the existing network resources for routing other flows.

The first method is Statically Scheduled Routing. For our NoC solutions, the required data rates are specified and the routes are fixed. In this setting, data transfers can be statically scheduled along the pre-determined paths with resource reservations to ensure deadlock-free routing [44, 45]. The second method is Virtual Channels insertion. As shown in [46], a necessary and sufficient condition for deadlock-free routing is the absence of cycles in a channel dependency graph. In particular, we use an extended channel dependency graph construction to find resource dependencies between multicast trees3 and break the cycles by splitting a channel into two virtual channels (or by adding another virtual channel if the physical channel has already been split). The added virtual channels are implemented in the corresponding routers. We applied this method into our NoC synthesis procedure and we have found that virtual channels are rarely needed to resolve deadlocks in practice for custom networks. In all the benchmarks that we tested in Sect. 8.8, no deadlocks were found in the synthesized solutions. Therefore, we did not need to add any virtual channel.

When a flow is rip-up and rerouted, its current path is deleted and the links and router ports resources it occupies are released (line 3). Then based on the current network connectivity and resources occupation, the RCG related to this flow is built and the weights of all edges in RCG are updated (line 4). In particular, for every pair of routers in RCG, the cost of this flow using those routers and the link connecting them is evaluated. This cost depends on the sizes of the routers, the traffic already routed on the routers and the connectivity of the routers to other routers. It also depends on whether an existing physical link will be used or a new physical link needs to be installed. If there are already router ports and links that can support the traffic, the marginal cost of reusing those resources is calculated. Otherwise, the cost of opening new router ports and installing new physical links to support the traffic is calculated. The cost is assigned as edge weight to the edge connecting the pair of routers in RCG. If the physical links used to connect the routers can not satisfy the delay constraints, a weight of infinity is assigned to the corresponding edges in RCG.

2 In the experiments, we’ve tried several flow ordering strategies such as largest flow first, smallest flow first, random ordering et al., and we found the ordering of smallest flow first gave the best results. Thus we used this ordering in our experiments. Also, we observed that repeating the whole RIPUP-REROUTE procedure twice is enough to generate good results.

multiple routing trees

performance-oriented routing tree

performance-oriented routing tree
Pathak, Mohit and Lim, Sung Kyu: Thermal-aware Steiner Routing for 3D Stacked ICs p7 2007 IEEE
Mohit Pathak and Sung Kyu Lim
School of Electrical and Computer Engineering
Georgia Institute of Technology
{mohitp, limsk}@ece.gatech.edu

routing graph

performance-oriented routing tree

Steiner tree

3D Steiner Tree

delay-oriented Steiner tree

performance-oriented Steiner trees

3D tree

3D A-tree
K. Boese, A. Kahng, B. McCoyy, and G. Robins, “Near-Optimal Critical Sink Routing Tree Constructions,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1995.

Overview of the Approach

The goal of our 3D Steiner routing is to address the following two important design objectives: performance and thermal. We tackle this problem in two steps:
1) Construction step: we first perform thermal analysis from the given 3D placement. We then construct a performance-oriented routing tree for each net under the non-uniform thermal profile. We recompute the temperature values to reflect the routing.
2) Refinement step: We optimize the thermal objective by relocating through vias in each tree under given timing constraints. Note that the through via relocation preserves the original tree topology while optimizing the thermal objective. We recompute the timing slacks and temperature values to reflect the relocation. We repeat this step until no more thermal improvement is possible.

Near-optimal critical sink routing tree

Elmore Routing Tree (ERT)

Elmore Routing Tree (ERT) / Steiner Elmore Routing
Tree (SERT)
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................
Another class of algorithms attempts to minimize Elmore delays directly during construction of the spanning tree for the net. The Elmore Routing Tree (ERT) and Steiner Elmore Routing Tree (SERT) algorithms [4] construct spanning and Steiner trees, respectively, using a greedy algorithm to minimize Elmore delay.

Terminology

Literature


balanced search tree

balanced search tree
Chang, Yen-Jung; Lee, Yu-Ting and Wang, Ting-Chi: NTHU-Route 2.0 A Fast and Stable Global Router p6

Yen-Jung Chang
Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 30013
Email: jalamorm@gmail.com

Yu-Ting Lee
Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 30013
Email: leetroy@gmail.com

Ting-Chi Wang
Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 30013
Email: tcwang@cs.nthu.edu.tw


3-D Slicing Tree

3-D Slicing Tree

Chen 3D-Floorplanning for Via and Wire length Minimization p50

3-D Slicing Tree

Fischbach, Robert; Lienig, Jens and Meister, Tilo: 3D Physical Design Challenges and Solutions p6............

3-D Slicing Tree
Friedman, Eby G.: 3-D Design: Architectures, Methodologies, and Test Circuits p137 June 11, 2010 2nd Design for 3-D Silicon Integration Workshop ....................

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering

Department of Electrical and Computer Engineering

University of Rochester

Rochester, New York 14627 USA

Phone: (585) 275-1022 Fax: (585) 276-0074

Email: friedman@ece.rochester.edu

www.ece.rochester.edu/~friedman

Floorplanning in 3-D

3-D Slicing Tree

?Slicing trees represent different floorplans
?Simulated annealing used to search good slicing floorplan
?Slicing tree isfull binary tree
?If nbasic modules, then
?2n -1 nodes
?n -1 internal nodes
?Neighborhood movements
?Exchange: two subtreesin array
?Rotation: in x, y, z directions

ExchangeRotation

3-D Slicing Tree
Law Block Alignment in 3D Floorplan Using Layered TCG p5

Literature


spanning trees

spanning trees

minimum spanning tree (MST)

3D minimum spanning tree (MST)

directed minimum spanning tree

rooted directed minimum spanning tree

rectilinear minimum spanning tree

k rectilinear minimum spanning tree (K-RST)

minimum spanning trees of bounded radius

bounded radius minimum spanning trees

K-rectilinear spanning tree

rooted directed spanning tree

minimum directed spanning tree

minimum-cost spanning tree (MST)

minimum radius spanning tree

bounded-radius spanning tree

spanning trees

spanning tree / minimum spanning tree (MST)
Graph Models for Global Routing Grid Graph Nov 2002 p17.

spanning tree / minimum spanning tree (MST) / minimum rectilinear spanning tree
Areibi, Shawki; Xie, Min and Vannelli, Anthony: AN EFFICIENT RECTILINEAR STEINER TREE ALGORITHM FOR VLSI GLOBAL ROUTING 1997 p6

Shawki Areibi
School of Engineering
University of Guelph
CANADA N1G 2W1
E-mail: sareibi@uoguelph.ca

Min Xie and Anthony Vannelli
Electrical Engineering Dept
University of Waterloo
CANADA N2L 2G1
E-mail: vannelli@cheetah.vlsi.uwaterloo.ca

spanning tree
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

Another class of algorithms attempts to minimize Elmore delays directly during construction
of the spanning tree for the net. The Elmore Routing Tree (ERT) and Steiner Elmore Routing
Tree (SERT) algorithms [4] construct spanning and Steiner trees, respectively, using a greedy
algorithm to minimize Elmore delay.

To take the three
performance constraints into account simultaneously, the bu er distribution was formulated as a
minimum length degree distributed spanning tree problem.

spanning tree / minimum spanning tree/ minimum spanning trees of bounded radius / bounded radius minimum spanning trees / bounded-radius spanning tree / minimum radius spanning tree / minimum cost spanning tree
Cong Performance-Driven Global Routing for Cell Based IC’s p4

spanning tree
Hsu TSV-Aware Analytical Placement for 3D IC Designs p6

spanning tree

minimum spanning tree (MST)

spanning tree
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.

spanning tree / minimum spanning tree
Li Modern 3-D Global Routing and Parallelism on X86 Multi-Core Platform p70.pdf

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

the directed minimum spanning tree

minimum directed spanning tree

the Minimum Directed Spanning Tree

rooted directed spanning tree

the rooted directed minimum spanning tree
In the RIPUP-REROUTE, each multicast routing step is formulated as a minimum
directed spanning tree problem. Two important graphs, Multicast Routing
Graph (MRG) and Multicast Routing Tree (MRTree), are used to help facilitate the
rip-up and rerouting procedure. They are defined as follows.

Then the
Chu-Liu/Edmonds algorithm [36, 37] is used to find the rooted directed minimum
spanning tree of MRG with the source router as root. A rooted directed spanning
tree of a graph is defined as a graph which connects, without any cycle, all n nodes
in the graph with n ? 1 arcs such that the sum of the weight of all the arcs is minimized.
Each node, except the root, has one and only one incoming arc. This directed
minimum spanning tree is obtained as the multicast routing tree (MRTree) so that
the routes of the multicast flow follows the structure of this tree. The details of Chu-
Liu/Edmonds Algorithm is summarized in Algorithm 3.

Then
it takes O(|V|2) to find the rooted directed minimum spanning tree as the multicast
tree by using the Chu-Liu/Edmonds algorithm.
???????????????

spanning tree
THIYAGARAJAN HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS p5

minimum spanning tree (MST)

minimum spanning tree / minimum-cost spanning tree (MST)
Boese High-Performance Routing Trees With Identi ed Critical Sinks p6

minimum spanning tree (MST)
Cong, Jason and Zhang, Yan: Thermal-Driven Multilevel Routing for 3-D ICs, Nov 2004, p6.
The Steiner tree heuristic
starts from a minimum spanning tree (MST), and a point-
to-path maze-searching engine is applied to each edge of the
initial MST.

minimum spanning tree (MST)
DICKSON Global Routing in VLSI Algorithms, Theory, and Computation p76.pdf

minimum spanning tree (MST)
Fischbach, Robert; Lienig, Jens and Meister, Tilo: 3D Physical Design Challenges and Solutions p6............

minimum spanning tree (MST)
He Integrated Interlayer Via Planning and Pin Assignment for 3D ICs p6.pdf

minimum spanning tree (MST)
Hsu, Chin-Hsiung; Chen, Huang-Yu and Chang, Yao-Wen: Multi-layer Global Routing Considering Via and Wire Capacities July 2008 p6........

minimum spanning tree (MST)
Hsu, Chin-Hsiung; Chen, Huang-Yu and Chang, Yao-Wen: Multilayer Global Routing With Via and Wire Capacity Considerations p12. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010

minimum spanning tree (MST)
Hsu Multilayer Global Routing With Via and Wire Capacity Considerations p12.pdf

minimum spanning tree (MST)
Lin Performance Benefits of Monolithically Stacked 3D-FPGA p10.pdf

minimum spanning tree (MST)
Luo, Guojie: Placement and Design Planning for 3D Integrated Circuits, 2011, PhD dissertation, p184 ............... 26

minimum spanning tree (MST) / directed minimum spanning tree / rooted directed minimum spanning tree / minimum directed spanning tree

Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

minimum spanning tree
Sapatnekar Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits p6

Sapatnekar Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits p6

minimum spanning tree (MST)

minimum spanning tree (MST)

Three-dimensional Integrated Circuits Design, EDA and Architecture
Xie, Yuan et al: Three-dimensional Integrated Circuits Design, EDA and Architecture June 2011 p156...........

Computer Science and Engineering Department, University Park, PA16802, USA

yuanxie@cse.psu.edu

http://www.cse.psu.edu/~yuanxie/
Figure 4.5 provides the
ow of thermal-driven 3D multilevel rout-
ing with TS-via (Through-Silicon Via) planning. A weighted area sum
model is used to estimate the routing resources, which are reserved for
local nets at each level. In addition, the average power density of each
tile is computed during the coarsening process. In the initial routing
stage, each multipin net generates a 3D Steiner tree, which starts from
a minimum spanning tree (MST). Then at each edge of the initial MST
a point-to-path maze-searching engine is applied. Steiner edges are gen-
erated when the searching algorithm reaches the existing edges of the
tree.

minimum spanning tree (MST)
Zhou, Lili; Wakayama, Cherry and Shi, C.-J. Richard: CASCADE A Standard Super-Cell Design Methodology with Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large Scale Integrated Circuits p11. 2006

minimum rectilinear spanning tree

directed spanning tree (dST)

directed spanning tree (dST) / directed minimum spanning tree (dMST)
Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.
In the RIPUP-REROUTE, each multicast routing step is formulated as a minimum directed spanning tree problem. Two important graphs, Multicast Routing Graph (MRG) and Multicast Routing Tree (MRTree), are used to help facilitate the rip-up and rerouting procedure. They are defined as follows.
Once the RCG is constructed, the multicast routing graph (MRG) for the flow is generated from RCG (line 5). MRG is build by including every source and destination router of the flow as its nodes. For each pair of the nodes in MRG, the least cost directed path with least power consumption on RCG is found for the corresponding routers using Floyd-Warshall’s all pair shortest path algorithm and the cost is assigned as edge weight to the edge connecting the two nodes in MRG. Then the Chu-Liu/Edmonds algorithm [36, 37] is used to find the rooted directed minimum spanning tree of MRG with the source router as root. A rooted directed spanning tree of a graph is defined as a graph which connects, without any cycle, all n nodes in the graph with n ? 1 arcs such that the sum of the weight of all the arcs is minimized. Each node, except the root, has one and only one incoming arc. This directed minimum spanning tree is obtained as the multicast routing tree (MRTree) so that the routes of the multicast flow follows the structure of this tree. The details of Chu- Liu/Edmonds Algorithm is summarized in Algorithm 3. The multicast routing for flow f in RCG can be obtained by projecting MRTree back to RCG by expanding the correspond arcs to paths. A special case is when f is a unicast flow with source s and destination d. In this case, MRG will just consist of two nodes, namely s and d, and one directed arc from s to d. Therefore, the routing between s and d in RCG is simply a shortest path between s and d.

To address the 3D-NoC synthesis problem, we formulate the problem as a combination of a rip-up and reroute procedure for routing flows and a router merging procedure for optimizing network topologies. The key part of the algorithm is a ripup and reroute procedure that routes multicast flows by way of finding the optimum multicast tree on a condensed multicast routing graph using the directed minimum spanning tree formulation and the efficient algorithms [36, 37]. Then a router merging procedure follows after to further optimize the implementation and reduce cost. The router merging algorithm iteratively considers all possible mergings of two routers connected with each other and merges them if the cost of the resulting topology after merging is reduced.

directed minimum spanning tree (dST)

Terminology

Literature


Steiner Tree

Steiner Tree

Def.: Given a graph G =(V; E), a subset R?V of vertices, and a length (or distance) function d: E→R+ on the edges, a Steiner tree is a connected and acyclic subgraph of G which spans all vertices in R. The vertices in R are usually referred to as terminals and the vertices in V\R as Steiner (or optional) vertices. Note that a Steiner tree might contain the Steiner vertices. The length of a Steiner tree is de4ned to be the sum of the lengths of all its edges.

While a spanning tree spans all vertices of a given graph, a Steiner tree spans a given subset of vertices.
minimum rectilinear Steiner tree <-- Rectilinear Steiner minimal tree <-- Steiner minimal tree <-- rectilinear Steiner tree < -- minimum rectilinear spanning tree (MST) <-- rectilinear minimum spanning tree <-- minimum spanning tree <-- spanning tree <-- tree

The Steiner tree problem
The so-called Steiner tree problem is to find a Steiner minimum tree (i.e., a Steiner tree of minimum length) in G. This problem is well known to be NP-complete [15], even in the Euclidean metric [8] or rectilinear metric [9]. However, it has many approximation algorithms with constant performance ratios [11,14].

k-Steiner tree
optimum k-Steiner tree

Metric Steiner tree problem on quasi- bipartite graphs

Geometric Steiner tree problem
A geometric Steiner tree is a tree, embedded in some defined metric space, which interconnects a given set of vertices.

GEOMETRIC STEINER MINIMAL TREES
The rectilinear Steiner ratio = SMT/MST

The Euclidean and rectilinear Steiner tree problems

Euclidean Steiner tree

In the 1970's both problems were shown to be NP hard

Rectilinear Steiner Tree

Full Steiner Trees FSTs

Full Steiner Tree Problem (FSTP)

A Steiner tree is full if all terminals are the leaves of the tree. The FSTP is to find a full Steiner tree with minimum length. If we restrict the lengths of edges to be either 1 or 2, then the problem is called the (1,2)-full Steiner tree problem (FSTP(1,2)).

Instance: A complete graph G =(V; E), a length function d: E→R+ on the edges, a proper subset R?V, and a positive integer bound B.

Question: Is there a full Steiner tree ?? in G such that the length of ?? is less than or equal to B?

The length function d is called a metric if it satisfies the following three conditions:
(1) d(x; y)≥0 for any x; y in V, where equality holds if and only if x=y,
(2) d(x; y)=d(y; x) for any x; y ∈V,
(3) d(x; y)≤d(x; z) + d(z; y) for any x; y; z in V (triangle inequality).

If we restrict that all edge lengths are either 1 or 2 (i.e., d: E→{1; 2}), then we call this restricted FSTP as FSTP(1,2), where such length function is a metric. For convenience, we use MIN-FSTP and MIN-FSTP(1,2) to be referred as the optimization
problems of FSTP and FSTP(1,2), respectively. Their formal de4nitions are as follows.

MIN-FSTP (Minimum full Steiner tree problem): Given a complete graph G = (V; E) with a length function d: E→R+ on the edges and a proper subset R?V of terminals, find a full Steiner tree of minimum length in G.

MIN-FSTP(1,2) (Minimum (1,2)-full Steiner tree problem): Given a complete graph G =(V; E) with a length function d: E→{1; 2} on the edges and a proper subset R?V of terminals, find a full Steiner tree of minimum length in G.

===============================================

In fact, the computation of the full Steiner tree also plays a very important role in the Steiner tree problem because any Steiner tree can be decomposed into many smaller components by splitting all the non-leaf terminals such that these components are full Steiner trees (hence they are called the full components).

A Steiner tree is called k-Steiner tree if all of its full components contains at most k terminals.

Borchers and Du showed that an optimum k-Steiner tree is a good approximation for a Steiner minimum tree if k is sufficiently large. Unfortunately, the problem of finding an optimum k-Steiner trees was shown to be NP-hard for k?. In this paper, we will show that the computation of an optimum full Steiner tree is not easier than that of an optimum k-Steiner tree.

minimal full Steiner tree

the FSTP is NP-complete and MAX SNP-hard, even when the lengths of edges are restricted to be either 1 or 2.

Euclidean FST EFST

Rectilinear FST RFST

Steiner Minimum / Minimal Trees

Simple SMTs
We call a SMT on a restricted set simple if each line has a terminal at one of its endpoints and if the SMT contains no crosses (Steiner points of degree 4).

Steiner Minimal Tree (SMT) Problem

Given n points on a plane, a Steiner minimal tree connects these points through some extra points (called Steiner points) to achieve a minimal total length. In the Steiner minimal tree problem, the vertices are divided into two parts: terminals and nonterminal vertices. The terminals are the given vertices which must be included in the solution. The cost of a Steiner tree is defined as the total edge weight. A Steiner tree may contain some nonterminal vertices to reduce the cost.

A SMT is generally used in initial net topology creation for global router and incremental net tree topology creation in physical synthesis. Therefore, it is often used as an accurate estimation for congestion and wire length during floorplan and placement.

Depending on the given metric, two versions of the Steiner tree problem have been studied.

Euclidean Steiner minimum tree (Esmt) problem

Euclidean Steiner minimal trees (Euclidean SMT): In this version, V is the entire Euclidean space and thus infinite. Usually the metric is given by the Euclidean distance (L2-norm). That is, for two points with coordinates (x1; y2) and (x2; y2), the distance is

√(x1-x2)2 + (y1-y2)2

Euclidean Steiner minimum tree (Esmt) problem

Euclidean SMTs ESMTs

Euclidean Steiner minimum tree obstacles (Esmto) problem

Esmto

Rectilinear Steiner Minimal Spanning tree

In some applications such as VLSI routing, L1-norm, also known as rectilinear distance, is used, in which the distance is defined as

|x1-x2|+|y1-y2|

Rectilinear Steiner minimum tree (Esmt) problem

Rectilinear SMTs RSMTs

Rectilinear Steiner minimum tree obstacles (Esmto) problem

Rsmto

(Graph) Steiner minimal trees (SMT):

In this version, the vertex set and metric is given by a finite graph.
Problem: Graph Steiner Minimal Tree
Instance: A graph G = (V;E;w) and a set L ⊂ V of terminals
Goal: Find a tree T with L ⊂ V (T) so as to minimize w(T).

Minimum Rectilinear Steiner Tree

exact algorithms:

  • GeoSteiner algorithm and implementation by Warme, Winter, and Zacharisen
  • Polynomial Time Approximation Scheme (PTAS) by Arora

heuristic algorithms:

  • Iterated 1-Steiner algorithm by Kahng and Robins
  • Borah et al.'s algorithm for the rectilinear Steiner minimal tree / Borah et al.'s edge substitute concept / approach
  • heuristic by Mandoiu et al.
  • 3/2 approximation algorithm of the metric Steiner tree problem on quasi-bipartite graphs
  • Zhou et al.'s spanning graph sweepline algorithm
  • Hwang's algorithm for minimal spanning tree construction

Rectilinear Steiner minimal tree
(where distances are measured with rectilinear metric)

Hanan in the 1960' s

Steiner Polygon

Steiner polygon criterion

Steiner hull

Steiner Routing

Steiner channel routing

Literature

Click here to see a list of hypergraph literature


Steiner Tree

BORRADAILE, GLENCORA; KLEIN, PHILIP and MATHIEU, CLAIRE: An O(n log n) Approximation Scheme for Steiner Tree in Planar Graphs p33

Daneshmand, Siavash Vahdati: Algorithmic Approaches to the Steiner Problem in Networks PhD Thesis Mannheim, 2003 p151

DE WET, PIETER OLOFF: GEOMETRIC STEINER MINIMAL TREES PhD Thesis JANUARY 2008 p81 ...............53

Dreyer, Derek R. and Overtony, Michael L.: Two Heuristics for the Euclidean Steiner Tree Problem p14 September 30, 2002

Erzin, Adil I. and Cho, Jun Dong: A Deep-Submicron Steiner Tree p15

Fo?meier Faster Approximation Algorithms for the Rectilinear Steiner Tree Problem p17.pdf

Fo?meier, U.; Kaufmann, M. and Zelikovsky, A.: Faster Approximation Algorithms for the Rectilinear Steiner Tree Problem p17

Frommer, Ian and Golden, Bruce: Solving the Euclidean Non-Uniform Steiner Tree Problem Using a Genetic Algorithm p27

Griffith Closing the gap Near-optimal Steiner trees in polynomial time1 p15.pdf

Griffith Closing the gap Near-optimal Steiner trees in polynomial time2 p36.pdf

Griffith Closing the gap Near-optimal Steiner trees in polynomial time p36.pdf

Grimwood, Geoffrey Ross: The Euclidean Steiner Tree Problem: Simulated Annealing and Other Heuristics Master Thesis 1994 p342 ....................... 27

Hanan On Steiners problem with rectilinear distance p12.pdf

HO, JAN-MING; VIJAYAN, GOPALAKRISHNAN AND WONG C. K.: New Algorithms for the Rectilinear Steiner Tree Problem p9 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL 9 NO 2, FEBRUARY 1990

Hu, Yu et al: An-OARSMan: An Obstacle-Avoiding Rectilinear Steiner Tree Algorithm with Good Length Performance p14

Huang, Tao and Young, Evangeline F. Y.: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees among Complex Obstacles p6 DAC ’11, Jun 05-10 2011, San Diego, California, USA

Huy, Nguyen Viet and Nghia, Nguyen Duc: Solving Graphical Steiner Tree Problem Using Parallel Genetic Algorithm p7

Hwang On Steiner minimal trees with rectilinear distance p12.pdf

Khosravinejad, Vahid and Bagheri, Alireza: A Heuristic Approach to Construction Rectilinear Steiner Trees p3 J. Basic. Appl. Sci. Res., 3(2s)342-344, 2013

Koch Solving Steiner Tree Problems in Graphs to Optimality p32????????????? 3

Lin, Chung-Wei and Chang, Yao-Wen: Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction p15

Lu, Chin Lung; Tang, Chuan Yi and Lee, Richard Chia-Tung: The full Steiner tree problem p13 Theoretical Computer Science 306 (2003) 55 – 67 .......................

Mandoiu, Ion I.; Vazirani, Vijay V. and Ganley, Joseph L.: A New Heuristic for Rectilinear Steiner Trees 1999 IEEE p6 .........................

Mandoiu, Ion I.; Vazirani, Vijay V. and Ganley, Joseph L.: A New Heuristic for Rectilinear Steiner Trees 1999 IEEE p24 .......................5

Miler, Zevi and Perkel, Manley: The Steiner Problem in the Hypercube p19

Paschos, Vangelis Th.; , Orestis A. and Zissimopoulos, Vassilis: Probabilistic Models for the STEINER TREE Problem p17

Polzin Algorithms for the Steiner Problem in Networks p126?

Qu, Rong et al: Particle Swarm Optimization for the Steiner Tree in Graph and Delay-Constrained Multicast Routing Problems p20

Rabkin, Mark: Efficient use of Genetic Algorithms for the Minimal Steiner Tree and Arborescence Problems with applications to VLSI Physical Design p7

RANDHAWA, REET SINGH: RANDOM METHODS FOR RECTILINEAR STEINER TREE PROBLEM WITH APPLICATIONS IN VLSI DESIGN p69 Master Thesis May, 1995

Robins, Gabriel and Zelikovsky, Alexander: Minimum Steiner Tree Construction p33

Santuari, Alessandro: Steiner Tree NP-completeness Proof p5 May 7, 2003

Soothill, Germander: The Euclidean Steiner Tree Problem p13 16. Februar 2010

Vygen, Jens: Steiner Trees in Chip Design Hangzhou, March 2009 p28 ...........ok

Wang Exact Algorithms for the Steiner Tree Problem p151.pdf

Wey, Chin-Long: Efficient Rectilinear Steiner Tree Construction with Rectangular Obstacles p 5 Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 ..................... ok

Wu, Bang Ye and Chao, Kun-Mao: Steiner Minimal Trees p6 An excerpt from the book \Spanning Trees and Optimization Problems," by Bang Ye Wu and Kun-Mao Chao (2004), Chapman & Hall/CRC Press, USA. ...................... ok

Zachariasen, Martin: Algorithms for plane Steiner tree problems PhD Thesis March 1998 p27

Zhou, Hai: Efficient Steiner tree construction based on spanning graphs, ISPD’03, April 6–9, 2003, p6................. ok

Steiner channel routing

Martin A and Weismantel R: Packing Paths and Steiner Trees Routing of Electronic Circuits, 1993, p20

Constraint graph channel routing

Pal, Achira et al: Graphs - The Tool to Visualize the Problems in VLSI Channel Routing, Assam University Journal of Science & Technology: ISSN 0975-2773 Physical Sciences and Technology Vol. 7 Number II 73-83, 2011

1. Arumaygum S. and S. Ramachandran, Invitation to Graph Theory, SciTech, 2001.
2. Bondy J. A. and U. S. R. Murty, Graph Theory with Applications, American Elsevier, 1976.
3. Broder A. and J. Solfi, Pessimal Algorithms and Simplexity Analysis, ACM SGAGACT NEWS,
Vol. 16, No. 3, pp. 49-53, 1984.
200 Rajat Kumar Pal et al.
4. Chiang C., M. Sarrafzadeh and C. K. Wong, A Powerful Global Router: Based on Steiner Min-
Max Trees, Proc. of IEEE Int. Conf. on Computer-Aided Design, pp. 2-5, 1989.
5. Clark J. and D. Holton, A First Look at Graph Theory, Allied Publishers, 1995.
6. Deo N., Graph Theory, Prentice-Hall, Inc., 2003.
7. Dijkstra E. W., A Note on Two Problems in Connexion with Graphs, Numerische Mathematik,
Vol. 1, pp. 269-271, 1959.
8. Gabor C. P., W. L. Hsu and K. J. Supowit, Recognizing Circle Graphs in Polynomial Time, Proc. of
26th IEEE Symposium on Foundation of Computer Science, pp. 106-116, 1985.
9. Garey M. R. and D. S. Johnson, The Rectilinear Steiner Tree Problem is NP-Complete, SIAM
Journal of Applied Mathematics, Vol. 32, pp. 826-834, 1977.
10. Garey M. R. and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NPCompleteness,
Freeman, San Francisco, 1979.
11. Golumbic M. C., Algorithmic Graph Theory and Perfect Graphs, Academic Press, 1980.
12. Hadlock F., Finding a Maximum Cut of a Planar Graph in Polynomial Time, SIAM Journal of
Computing, Vol. 4, No. 3, pp. 221-225, 1975.
13. Harary F., Graph Theory, Addison-Wesley, 1969.
14. Ho J. M., G. Vijayan and C. K. Wong, A New Approach to the Rectilinear Steiner Tree Problem,
IEEE Trans. on Computer-Aided Design, Vol. 9, No.2, pp. 185-193, 1985.
15. Kapoor and Ramesh, An Algorithm for Enumerating All Spanning Trees of Undirected and
Weighted Graphs, SIAM Journal of Computing, Vol. 24, pp. 247-265, 1997.
16. Kruskal J. B., On the Shortest Spanning Subtree of a Graph and the Traveling Salesman Problem,
Proc. of the American Mathematical Society, Vol. 7, No.1, pp. 48-50, 1956.
17. Pal R. K., Multi-Layer Channel Routing: Complexity and Algorithms. NAROSA Publishing House,
New Delhi (Indian Edition, Paperback), CRC Press, Boca Raton, USA and Alpha Sc. Intl. Ltd.,
UK (International Editions, Hardbound), Sep. 2000.
18. Papadimitriou C. H. and K. Steigliz, Combinatorial Optimization: Algorithms and Complexity,
Prentice-Hall, Inc., 1982.
19. Prim R. C., Shortest Connection Networks and Some Generalizations, Bell System Technical
Journal, 1957.
20. Reingold, Nievergelt and Deo, Combinatorial Algorithms, Prentice-Hall, Inc., 1977.
21. Rosen K. H., Discrete Mathematics, 2003.
22. Sherwani N. A., Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers,
Boston, 1993.
23. West D. B., Introduction to Graph Theory, Prentice-Hall, Inc., 2003.
24. Wilson R. J., Introduction to Graph Theory, Academic Press, 1979.

Ramsey Theory

Rosta, Vera: Ramsey Theory Applications: Dec 7, 2004 ?????????? 4

Turan Theory

Szemeredi’s Regularity Lemma

Regularity Lemma

Alon The Algorithmic Aspects of the Regularity Lemma p27

Bansal Regularity Lemmas and Combinatorial Algorithms p10??????????????? 3

Bansal Regularity Lemmas and Combinatorial Algorithms p21

Bhattacharyya Algorithmic regularity for polynomials and applications p33

Haxell Regularity for Hypergraphs p14

Joseph Introduction to the Regularity Lemma p58

Kohayakawa Szemeredis Regularity Lemma for Sparse Graphs p15

Komlos Szemeredis Regularity Lemma and its applications in graph theory p52

Mahdian The Regularity lemma p17

Sarkozy A Practical Regularity Partitioning Algorithm and its Applications in Clustering p13

Sarkozy A Practical Regularity Partitioning Algorithm and its Applications in Clustering p17

Simonovits Regularity Lemmas and Extremal Graph Theory p49

Terminology

Literature


Untitled Document

Steiner tree

Steiner tree

combined Steiner Tree

delay-oriented Steiner tree

buffered Steiner tree

minimum-weight Steiner tree

minimum weighted rectilinear Steiner tree (WRST)

node-weighted Steiner Trees

weighted rectilinear Steiner tree

performance-oriented Steiner trees

performance-oriented minimum rectilinear Steiner tree

orthogonal Steiner trees

rectilinear Steiner trees

K Rectilinear Steiner Trees (K-RST)

buffered rectilinear Steiner tree

minimal rectilinear steiner tree (MRST)

minimum steiner tree

rectilinear MST - rectilinear minimum steiner tree

optimal Recti- linear Minimal Steiner Tree (RMST)

Minimum Rectilinear Distance Steiner Tree (MRST)

Rectilinear and Euclidian Minimum distance Steiner Trees

minimum-cost Steiner tree

Steiner minimum tree

Steiner minimal tree

rectilinear Steiner minimum tree (RSMT)

Rectilinear Steiner Minimal Tree

Steiner min-max tree (SMMT)

K trees

Steiner tree

Steiner-trees
3-Dimensional VLSI routing, 2007, p19..
After having solved the single active layer routing problem we may ask the
question what if the terminals are not on a single layer. In this chapter we
will study the case where the terminals are placed on the bottom and on the
top layer. The object of the problem is the same as it was in the single active
layer routing problem: to connect the terminals in each net with Steiner-trees
in the 3-dimensional cubic grid by using as few layers as possible in such a
way that Steiner-trees which interconnect distinct nets are vertex-disjoint.
If we are allowed to introduce extra rows and columns (in both grid),
then the problem is always solvable, moreover:

Steiner Tree / Steiner minimum tree / Minimum Rectilinear Steiner Tree
Graph Models for Global Routing Grid Graph Nov 2002 p17.

Steiner Tree / minimum steiner tree / rectilinear Steiner trees / K Rectilinear Steiner Trees / Minimum Rectilinear Steiner Tree
Areibi, Shawki; Xie, Min and Vannelli, Anthony: AN EFFICIENT RECTILINEAR STEINER TREE ALGORITHM FOR VLSI GLOBAL ROUTING 1997 p6

Shawki Areibi
School of Engineering
University of Guelph
CANADA N1G 2W1
E-mail: sareibi@uoguelph.ca

Min Xie and Anthony Vannelli
Electrical Engineering Dept
University of Waterloo
CANADA N2L 2G1
E-mail: vannelli@cheetah.vlsi.uwaterloo.ca

Steiner tree / minimum Steiner tree / minimum-cost Steiner tree
Boese High-Performance Routing Trees With Identi ed Critical Sinks p6

Steiner Tree / minimum steiner tree / performance-oriented minimum rectilinear Steiner tree (POMRST) / Steiner Elmore Routing Tree (SERT)
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................
A - Tree vs Steiner Tree

A performance-oriented minimum rectilinear Steiner tree
(POMRST) algorithm [33] minimizes total wire length subject to constraints on the lengths of
individual source-sink paths.

Steiner Tree
Cong, Jason: Thermal-Aware 3D IC Physical Design and Architecture Exploration p56
NLP Formulation
?? Wire length mode – HPWL (3D bounding box)
?? TS via resource model - one trunk Steiner tree
? zv depends on the cell placement (x,y,z)
?? Relax the problem with continuous ‘z’
?? Smoothing the densities by
? Gain two more derivatives

Steiner Tree
Cong, Jason and Zhang, Yan: Thermal-Driven Multilevel Routing for 3-D ICs, Nov 2004, p6.................
During the initial routing stage, an initial 3-D Steiner tree is generated for each multipin net. The Steiner tree heuristic starts from a minimum spanning tree (MST), and a point- to-path maze-searching engine is applied to each edge of the initial MST. Steiner edges are generated when the searching algorithm touches the existing edges of the tree before the target point. Since the maze-searching algorithm can ˉnd the shortest path around obstacles, the problem of the ex- istence of many huge obstacles on the device layers can be solved. Then, the number of dummy TS-vias that need to be inserted is estimated through binary search. The upper bound of dummy TS-via numbers that can be inserted into each device layer is estimated by the amount of white space between the blocks. From our experience, the dummy TS-via number can be determined in fewer than ten iterations. Af- ter that, a TS-via number distribution step is carried out to assign the dummy TS-vias to the tiles.

3-D Steiner tree
Cong, Jason and Zhang, Yan: Thermal-Driven Multilevel Routing for 3-D ICs, Nov 2004, p6.

The new thermal-driven 3-D routing system, shown in Fig. 4 has a the similar \downward pass" as the scheme in [23], where the routing resources are estimated using a weighted area sum model, and the routing resources for local nets are reserved at each level. Moreover, the thermal-related infor- mation, such as the average power density of each tile is also computed during the coarsening process.

During the initial routing stage, an initial 3-D Steiner tree is generated for each multipin net. The Steiner tree heuristic starts from a minimum spanning tree (MST), and a point- to-path maze-searching engine is applied to each edge of the initial MST. Steiner edges are generated when the searching algorithm touches the existing edges of the tree before the target point. Since the maze-searching algorithm can ˉnd the shortest path around obstacles, the problem of the ex- istence of many huge obstacles on the device layers can be solved. Then, the number of dummy TS-vias that need to be inserted is estimated through binary search. The upper bound of dummy TS-via numbers that can be inserted into each device layer is estimated by the amount of white space between the blocks. From our experience, the dummy TS-via number can be determined in fewer than ten iterations. Af- ter that, a TS-via number distribution step is carried out to assign the dummy TS-vias to the tiles.

Steiner Tree
Deza, Antoine et al: Global Routing in VLSI Design Algorithms, Theory, and Computational Practice JCMCC 12 May 2011 p25.

Email addresses: deza@mcmaster.ca (Antoine Deza),

cdickson@bedlamgames.com (Chris Dickson),

terlaky@lehigh.edu (Tam?as P Terlaky),

vannelli@uoguelph.ca (Anthony Vannelli),

Hu.Zhang@rbccm.com (Hu Zhang).

Steiner Tree
DICKSON, CHRIS: Global Routing in VLSI Algorithms, Theory, and Computation Master Thesis, May 2007 p76

Steiner Tree

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3D IC
Hsu, Po-Yang; Chen, Hsien-Te and Hwang, TingTing: Stacking Signal TSV for Thermal Dissipation in Global Routing for 3D IC, ASPDAC’13, p26
Initial TSV Assignment

Steiner-trees
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Steiner tree
Kim, Dae Hyun; Kim, Suyoun and Lim, Sung Kyu: Impact of Nano-scale Through-Silicon Vias on the Quality of Today and Future 3D IC Designs p8

Steiner-trees / Minimum Steiner Tree / Rectilinear Steiner Minimum Tree (RSMT)

Li: Yih-Lang (李毅郎): Modern 3-D Global Routing and Parallelism on X86 Multi-Core Platform Dec 2009 p70.

Steiner-trees

Mahapackialakshmi Aerial Monotonic based Layer Assignment on 3D Global Routing p4.pdf

Steiner-trees
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

Steiner-trees
Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8........................
2) Topology generation: Steiner trees are generated for all
nets in each routing interval so that the performance of the
routed design is optimized.

Steiner tree / rectilinear Steiner trees / orthogonal Steiner trees
OBENAUS, STEFAN THOMAS and SZYMANSKI, TED H.: Gravity: Fast Placement for 3-D VLSI, ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003, Pages 298–315., p18.

rectilinear Steiner tree

Steiner-trees / 3D Steiner Tree / delay-oriented Steiner tree / performance-oriented Steiner trees
Pathak, Mohit and Lim, Sung Kyu: Thermal-aware Steiner Routing for 3D Stacked ICs p7 2007 IEEE

Steiner-trees / vertex disjoint Steiner-tree / pairwise vertex-disjoint Steiner-tree
Recski, Andras and Szeszler, David: 3-dimensional Routing, Aug 2008. p8.

Steiner tree / buffered Steiner tree / rectilinear Steiner tree / buffered rectilinear Steiner tree
Salek A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm p6

Steiner tree
Sanusi SEGRoute A New Global Routing Methodology Based on Grid Graph Segmentation p4.pdf

Steiner tree / delay-oriented Steiner tree

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

In [9, 10],
Yan et al. formulated the custom NoC synthesis problem based on set partitioning
of traffic flows and finding good network topologies using a Steiner tree formulation.

Steiner tree

Tayu, Satoshi and Ueno, Shuichi: The Complexity of Three-Dimensioal Channel Routing (Extended Abstract), 2005, p10

Abstract: The 3-D channel routing is a fundamental problem on the physical design of 3-D integrated circuits. The 3-D channel is a 3-D grid G and the terminals are vertices of G located in the top and bottom layers. A net is a set of terminals to be connected. The objective of the 3-D channel routing problem is to connect the terminals in each net with a Steiner tree (wire) in G using as few layers as possible and as short wires as possible in such a way that wires for distinct nets are disjoint. This paper shows that the problem is intractable.

A terminal is a vertex of G located in the top or bottom layer. A net is a set of terminals to be connected. A net containing k terminals is called a k-net. The object of the 3-D channel routing problem is to connect the terminals in each net with a Steiner tree (wire) in G using as few layers as possible and as short wires as possible in such a way that Steiner trees spanning distinct nets are vertex-disjoint. A set of nets is said to be routable in G if G has vertex-disjoint Steiner trees spanning the nets.

Suppose N is routable in the (W;D;H)-channel G, and let Si be a rectilinear Steiner tree connecting the terminals in net Ni, and S = fS1; S2; : : : ; Sg. Each Si can be represented by the coordinates of terminals of Ni, Steiner points, and bends of Si, and edges of Si. It should be noted that the number of Steiner points of Si is at most i ?? 1. Let i be the number of bends of Si, and =
P
i=1 i. Then the size of representing Si is
( i) and so the size of representing
S is

Since N = fN1;N2; : : : ;Ng is routable in G, there exist vertex-disjoint Steiner trees Si for Ni, 1  i  . Let S = fS1; S2; : : : ; Sg. For each m 2 [ + 1], let GX m be a subgrid of G induced by the vertices in f(x; y; z)j'm??1  x  'm; y 2 [D]; z 2 [H]g. If 'm ?? 'm??1  f( ), we can partially reroute S in GX m so that the number of bends in GX m is O( 2) by Theorem 8. Here, the columns de ned by x = 'm??1 and x = 'm are considered as the top and bottom layers of a 3-D channel.

Steiner tree
Terlaky Routing in VLSI Design and Communication Networks p26.pdf

Steiner tree
Vygen, Jens: Faster Resource Sharing and Global Routing in Theory and Practice Nov 2011 p88.

Steiner Tree
Wu, Tai-Hsuan et al: GRIP: Scalable 3D Global Routing Using Integer Programming, Proc. of Design Automation Conference, pp. 320-325, 2009, p6

3D Steiner tree

Three-dimensional Integrated Circuits Design, EDA and Architecture
Xie, Yuan et al: Three-dimensional Integrated Circuits Design, EDA and Architecture June 2011 p156...........

Computer Science and Engineering Department, University Park, PA16802, USA

yuanxie@cse.psu.edu

http://www.cse.psu.edu/~yuanxie/
Figure 4.5 provides the
ow of thermal-driven 3D multilevel rout-
ing with TS-via (Through-Silicon Via) planning. A weighted area sum
model is used to estimate the routing resources, which are reserved for
local nets at each level. In addition, the average power density of each
tile is computed during the coarsening process. In the initial routing
stage, each multipin net generates a 3D Steiner tree, which starts from
a minimum spanning tree (MST). Then at each edge of the initial MST
a point-to-path maze-searching engine is applied. Steiner edges are gen-
erated when the searching algorithm reaches the existing edges of the
tree.

Steiner tree
Xu 3D Global Router_ a Study to Optimize Congestion Wirelength and Via for Circuit Layout p87.pdf

Steiner Tree
Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................15
There are also other approaches that work on routability issue. Westra et. al. [27]
[28] proposed alternative framework that calculates congested region based on probabil-
ity theory. The way they calculate routing probability ignore that fact that segments for
a routed net should be connected, which is a major drawback. As a result, the proba-
bilistic framework shows no advantage over sequential rip-up and rerouting approaches
in solution quality. Besides, Chu et. al. proposed a look-up table based Steiner Tree
generation technique and package called FLUTE [29] [30] that provides optimal Recti-
linear Minimal Steiner Tree (RMST) for nets with up to 9 pins and good RMST solution
for nets with more than 9 pins. FLUTE enables global routers to use very good topology
to start with and greatly improves global routing solution. E ort needs to be taken not
only in the routing stage but also in the earlier placement stage. Placement determines
the instances and pin locations and poses great constraints on the routing solutions. Pan
and Chu [31; 33] pointed out that a placer integrated with an ecient global router to
model interconnects could help the placer to generate routing friendly placement results.
To achieve this kind of integration, global router has to be fast enough to be invoked
frequently to estimate the interconnections. Therefore, a high-quality global router also
need to be fast to address the routing task requirements.

Steiner tree
Xu MGR Multi-Level Global Router p6.pdf

Steiner tree

Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.
For designing custom NoC architectures without assuming an existing network
architecture, a number of techniques have been proposed in the 2D domain [7–10].
In [7], Srinivasan et al. presented NoC synthesis algorithms that consider systemlevel
floorplanning. In [8], Murali et al. presented a NoC synthesis flow with detailed
backend integration that also considers the floorplanning process. In [9, 10],
Yan et al. formulated the custom NoC synthesis problem based on set partitioning
of traffic flows and finding good network topologies using a Steiner tree formulation.
However, for the best of our knowledge, a fully automated 3D-NoC synthesis
solution remains an open problem.

Steiner Tree
Zhou, Lili; Wakayama, Cherry and Shi, C.-J. Richard: CASCADE A Standard Super-Cell Design Methodology with Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large Scale Integrated Circuits p11. 2006

minimum steiner tree

minimum steiner tree
Ahn, Byung-Gyu et al: Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs p7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.11, NO.4, DECEMBER, 2011
After the virtual pin assignment, virtual routing is constructed based on the Minimum Steiner Tree. In 3D ICs, the length of TSVs is insignificant comparing with the length of signal nets. In other words, the effect of multilayer is ignored temporarily and pins are assumed on one die. It facilitates the generating the MST using classical algorithm. After the SMT generating, TSVs are needed for the nets which pins are located at different dies. So, signal TSVs are inserted and the best way to place the signal TSV is near the source pin [6]. As embedding TSVs, inter-die signal interconnections are divided into several segments on different dies. Coordinates of TSVs are regarded as the end points of the segments. Every segment only occupies the routing resource of the die it located. Therefore, segments should be calculated separately in order to get the routing demand for each die.

minimum steiner tree
Chong, Jongwha: Thermal Aware Design Methodology for 3D-IC, 2011, p27
3rd Step : Virtual Routing of Signal Net
?? Virtual pin assignment of soft-macro block
?? 3D Routing based on MST (Minimum Steiner Tree)

minimum steiner tree
Karro, John and Cohoon, James P.: A Spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays 1999 p2.
When we consider an
individual net, we would like to place the logic blocks of
the net entirely within one grid block if possible, and failing
that, we would like to keep them in neighboring grid
blocks. This preference is heuristically achieved by considering
the thumbnail for each net: the minimum steiner tree
connecting the grid blocks the net occupies. By partitioning
the logic blocks in such a way as to minimize the total
length of the thumbnails, we tend to achieve our objective
of keeping the logic blocks of a given net close together.

Steiner Minimal Trees

Steiner minimum tree
Ababei, Cristinel ; Feng, Yan; Goplen, Brent et al.: Placement and routing in 3D integrated circuits. IEEE Design and Test of Computers, 22(6):520{531, 2005, p10
The overall flow of the solution technique is shown in Figure 13. In the first step, a Steiner minimum tree is built for each net, with a cost that depends on the length of the net (with a penalty that discourages, but does not prohibit, the use of more than the minimum number of inter-tier vias). This Steiner structure still affords considerable flexibility in the routing through the availability of soft edges [19], and in each layer, assuming L and Z shaped routes, the distribution of wire congestion is determined in the second step. Next, a hierarchical procedure is followed for the precise assignment of inter-tier via locations: this corresponds to to a sequence of assignment problems (assigning nets to vias) that are solved using network-flow techniques. Once the inter-tier via locations are determined, the final step performs a minimumcost maze routing in each layer, with a cost function that is based on the wire length, the temperature, and the congestion, to yield the global routing solution. Finally, any standard 2D detailed router may be used for detailed routing.

Steiner Minimal Trees
DICKSON, CHRIS: Global Routing in VLSI Algorithms, Theory, and Computation Master Thesis, May 2007 p76

Steiner Minimal Trees
Hsu, Chin-Hsiung; Chen, Huang-Yu and Chang, Yao-Wen: Multilayer Global Routing With Via and Wire Capacity Considerations p12. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010

rectilinear Steiner trees

rectilinear Steiner tree

rectilinear Steiner trees
HARALAMBIDES, JAMES: Multilevel Routing for 3-Dimensional Circuits, p5, Proceedings of the 10th WSEAS International Conference on COMPUTERS, Vouliagmeni, Athens, Greece, July 13-15, 2006 (pp1224-1228)

The above formula gives an estimate of the
actual routing cost for each net that is closely related
to the cost of the 3-Dimensional rectilinear Steiner
tree. Actual results may vary according to overall
circuit density and average node degree. The cost
serves as a valuable measure for the effectiveness of
the algorithm.

Completion of routing for a net is achieved
through a sequence of random pair-wise connections
between circuit nodes of the net or routing nodes
that have been assigned to this net currently.
Routing pairs of nodes of multi-terminal nets
according to 3-D rectilinear Steiner trees leads to a
number of connections being implemented either
inside or on the boundary of the convex sub-volume
defined by these two points. This doesn’t always
yield optimal results in an environment of
competing nets as sub-optimal interconnections locally may lead to a global optimum. To account
for such possibilities, we extend the size of the subvolume
by a user defined number of layers.

The above formula gives an estimate of the
actual routing cost for each net that is closely related
to the cost of the 3-Dimensional rectilinear Steiner
tree. Actual results may vary according to overall
circuit density and average node degree. The cost
serves as a valuable measure for the effectiveness of
the algorithm.

rectilinear Steiner tree

rectilinear Steiner trees
Meleis, Waleed M. et al: Architectural design of a three dimensional fpga. In Proc. Seventeenth Conf Advanced Research in VLSI, pages 256{268, 1997
Researchers at the University of Virginia have implemented 3-D place and route tools and have
shown the improvement by making use of three dimensions [3]. The 3-D CAD tools developed by
this group partition the design into cubes of 3′3′2 computational blocks, and use simulated
annealing to minimize the global routing cost. The cost is estimated using rectilinear Steiner trees.
The nets in the design are routed one at a time using an iterated KMB algorithm that attempts to
minimize the total path length per net. Their algorithms combined with a hypothetical 3-D FPGA
architecture, which assumes a standard FPGA architecture equipped with 3-D switch boxes, show
significant reduction in net length and routing resources used. This theoretical analysis of 3-D
FPGAs shows the importance of pursuing an architecture like our 3-D FPGA.

rectilinear Steiner Minimal trees

rectilinear Steiner Minimal tree
Panth Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs p34

Rectilinear Minimum Steiner Tree

Rectilinear Minimum Steiner Tree

Recti- linear Minimal Steiner Tree (RMST)
Cho, Minsik et al: BoxRouter 2.0 Architecture and Implementation of a Hybrid and Robust Global Router 2007 IEEE p6....

Recti- linear Minimal Steiner Tree (RMST)
Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................15
Besides, Chu et. al. proposed a look-up table based Steiner Tree
generation technique and package called FLUTE [29] [30] that provides optimal Recti-
linear Minimal Steiner Tree (RMST) for nets with up to 9 pins and good RMST solution
for nets with more than 9 pins.

Minimum Rectilinear Steiner Tree

Minimum Rectilinear Steiner Tree
Hao Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuit p140

Hao Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuit p140

3D Clock Tree

minimum rectilinear Steiner tree (MRST)

performance-oriented minimum rectilinear Steiner tree

orthogonal Steiner trees

orthogonal Steiner trees
OBENAUS, STEFAN THOMAS and SZYMANSKI, TED H.: Gravity: Fast Placement for 3-D VLSI, ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003, Pages 298–315., p18.

Rectilinear and Euclidian Minimum distance Steiner Trees

Rectilinear and Euclidian Minimum distance Steiner Trees / node-weighted Steiner Trees
Bahirat, Shirish and Pasricha, Sudeep: 3D-HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific 3D Network-On-Chip Architectures p8 Jan 2014

MEST and MRST based network formation
In this step, we initiate the network formation by generating Rectilinear and Euclidian Minimum distance Steiner Trees, where the link weight for link li,j is a function of normalized communication bandwidth, power, and latency:
??×????,??× ????????,???????? _???????+(1???)× ???????? _??????????????????????????????,????? (2)
where ????,??, bwi,j, and latencyi,j are link power consumption, link bandwidth, and link latency, respectively. We use separate weight values (??) for FSNPI links and electrical links due to their power consumption differences. We ultimately generate a Minimum Euclidean Distance Steiner Tree (MEST) for electrical links and a Minimum Rectilinear Distance Steiner Tree (MRST) for FSNPI links, as shown in Fig. 5(a)-(b). Note again that the routers are still not accurately mapped on the die during this stage, and we approximate virtual router locations at the center of each core. Finally, we connect all cores (virtual routers) utilizing FSNPI and electrical links.

Each cluster represents a router in the final solution. But we still need to determine which communication flows will utilize FSNPI links, electrical links, or a combination of both. This is accomplished using a push-relabel maximum flow algorithm. For every core ???? in the system, we create a corresponding pseudo core ??????, where inter-core communication for all n cores uses MEST links and all ??′cores uses MRST links. The n and ??′cores are linked with weights based on MRST and MEST links as shown in Fig. 5(d). Using the push-relabel maximum flow algorithm we generate a combined Steiner Tree and then merge the n and ??′cores. At the end of this stage, we utilize the max-flow min cut algorithm to determine 1-hop or 2-hop routing for FSNPI-based communication flows, to maximize bandwidth utilization while minimizing router resources.
presented a floorplan aware synthesis technique that considers wiring complexity of the NoC during topology synthesis along with min-cut partitioning to allocate switches to groups of custom cores and minimize NoC power. Srinivasan et al. [20] presented a low complexity genetic algorithm based approach to synthesize a low power custom NoC topology. Chatha et al. [21] presented synthesis techniques for an application-specific NoC that employed integer linear programming (ILP) and min-cut/flow algorithms as well as node-weighted Steiner Trees to obtain shortest paths. One limitation of these approaches is that they target single applications, which is increasingly impractical for today’s multi-programmed workloads. Other techniques aimed at regular NoC synthesis have mainly focused on mapping uniform size cores and their communication flows on regular mesh topologies [22]-[25]. Our recent work [26] was the first to propose a framework for synthesizing regular hybrid nanophotonic-electric NoC fabrics using particle swarm optimization (PSO) based design space traversal and optimization techniques.
Fig 5. (a) Layer one, Steiner Tree (MEST) for electrical network and Minimum Rectilinear Distance Steiner Tree (MRST) for FSNPI links (b) Layer two, MEST and MRST (c) clustering for dual level router mapping (d) TSV assignment and PCR generation

vertex disjoint Steiner-trees

vertex-disjoint Steiner trees

vertex disjoint Steiner-trees / pairwise vertex-disjoint Steiner-trees
A. Recski and D. Szeszler, \Routing vertex disjoint Steiner-trees in a cubic grid and connections to VLSI," Discrete Applied Mathematics, pp.44{52, 2007.
Recski, Andras and Szeszler, David: 3-dimensional Routing, Aug 2008. p8.

The specification of a (2-dimensional) single row routing or channel routing problem instance
involves a family of pairwise disjoint subsets of the terminals, called nets. By a routing we mean
an assignment of pairwise vertex-disjoint Steiner-trees in the 3-dimensional grid (of size w×n×k)
to each net, such that the assigned tree connects the terminals of the corresponding net.

The results surveyed in this paper allow multiterminal nets as well, and ensure vertex disjoint
paths (or Steiner-trees) for the interconnections of the terminals within each net. We consider
the 3-dimensional analogues of single row routing and channel routing. That is, terminals occupy
certain vertices of a w×n planar grid (single active layer routing problem) or two parallel w×n
grids (3-dimensional channel routing) and the third dimension (above the single grid or between
the two grids) is for interconnections only. The objective is to minimize the height h of the
routing.

A solution with a given spacing sw and sn of a routing problem N = {N1,N2, . . . ,Nt} is
a set T = {T1, T2, . . . , Tt} of pairwise vertex-disjoint Steiner-trees in the cubic grid of size
(w · sw)×(n · sn)×h (between the two parallel planar grids containing the terminals) such that the terminal set of Ti is Ni for every 1 ≤ i ≤ t. The Steiner-trees Ti are called wires. The height
h of the routing is to be minimized.

Recski, A. and D. Szeszl′er, Routing vertex disjoint Steiner-trees in a cubic grid — an
application in VLSI, Discrete Applied Mathematics (2007) 155, 44-52.

pairwise vertex-disjoint Steiner-trees

pairwise vertex-disjoint Steiner-trees
Reiss, Attila and Szeszler, David: 3-dimensional Channel Routing, Nov 2007. p10

The specification of a (2-dimensional) channel routing problem instance involves a family of
pairwise disjoint subsets of the terminals, called nets. By a routing we mean an assignment of
pairwise vertex-disjoint Steiner-trees in the 3-dimensional grid (of size w × n × k) to each net,
such that the assigned tree connects the terminals of the corresponding net.
Out of the wide literature on detailed routing, we are going to use the following result on
2-layer channel routing.

In [10] the single active layer routing problem (abbreviated as SALRP) is considered, which
can be regarded as a 3-dimensional analogue of single row routing. Here the terminals are placed
on a single planar grid of size w × n and the third dimension (above this grid, with height h)
is for interconnections only. Multiterminal nets are also allowed and the interconnection of the
terminals within each net is to be realized along vertex-disjoint paths (or Steiner-trees). One
can easily see even in small instances like 2×2 or 4×1 that a routing is usually impossible (with
an arbitrary height). Therefore it is allowed to extend the length and the width of the grid to
w′ = sw and n′ = sn, where the spacing s is a fixed integer. This is done by introducing s ? 1
pieces of empty rows and columns between every two consecutive rows and columns containing
the terminals. We are going to use the following result:

A solution with a given spacing sw and sn of a routing problem N = {N1,N2, . . . ,Nt} is
a set T = {T1, T2, . . . , Tt} of pairwise vertex-disjoint Steiner-trees in the cubic grid of size
(w · sw)×(n · sn)×h (between the two parallel planar grids containing the terminals) such that
the terminal set of Ti is Ni for every 1 ≤ i ≤ t. The Steiner-trees Ti are called wires. The height
h of the routing is to be minimized.

delay oriented Steiner tree
delay oriented Steiner tree

delay-oriented Steiner tree
Lim, S.K.: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, Chapter 2 Steiner Routing for 3D IC, p34 Springer Science+Business Media New York 2013
delay oriented Steiner tree

delay-oriented Steiner tree
Pathak, Mohit and Lim, Sung Kyu: Thermal-aware Steiner Routing for 3D Stacked ICs p7 2007 IEEE
delay oriented Steiner tree

delay-oriented Steiner tree

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25
In [27],
a thermal-aware Steiner routing algorithm for 3D ICs is proposed by constructing a
delay-oriented Steiner tree under a given thermal profile.

delay-oriented Steiner tree

Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.
Research in 3D NoC is only emerging recently. Several works have been done in
the area of 3D floorplanning and 3D placement and routing. Cong et al. [24, 25]
proposed thermal-driven design flows for 3D ICs including 3D floorplanning and
3D placement and routing algorithms. In [26], thermal effect was formulated as another
force in a force-directed approach to direct the placement procedure. In [27],
a thermal-aware Steiner routing algorithm for 3D ICs is proposed by constructing a
delay-oriented Steiner tree under a given thermal profile.

node-weighted Steiner Trees

Via Aware Steiner Tree

Via Aware Steiner Tree
Hsu, Chin-Hsiung; Chen, Huang-Yu and Chang, Yao-Wen: Multilayer Global Routing With Via and Wire Capacity Considerations p12. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010

Via Aware Steiner Tree
Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................15

Via-aware Steiner tree generation technique to adjust net topology to minimize via count.

The via aware Steiner tree generation technique extends the congestion driven Rectilinear Steiner Minimal Spanning tree.

Different tree topologies have significant impact on via count. They will generate differemt number of vias for the same number of pins. Here two special structures are defined: Horizontal Tree (H Tree) and Vertical Tree (V Tree). H tree is defined as a rectilinear tree with only one vertical trunks, with all the other trunks in between the vertical trunks and pin nodes to be horizontal. Similarly, vertical tree is de ned as a tree with only one horizontal trunk, with all the other trunks in between the horizontal trunk and pin nodes to be vertical. If each net is assigned onto two adjacent metal layers, as our layer assignment algorithm tries to achieve by keeping segments in one net close to each other, H Tree and V Tree are two extremes in terms of the number of vias. Other trees, like the RSMT (Rectilinear Steiner Minimal Tree) with smaller wirelength shown in Fig. xxx , have via count in between. However, it is not always the case that H Tree would have less number of vias than V Tree. If the resource on metal layer 1 is used up and the net has to go onto layer 2 and 3, it is obvious that V Tree is a better choice.

The number of vias generated during the global routing stage is a critical factor for
the yield of integrated circuits. However, most global routers only approach the problem
by charging a cost for vias in the maze routing cost function. The rst work of this
thesis, FastRoute 4.0 presents a global router that addresses the via number optimization
problem throughout the entire global routing
ow. It introduces the via aware Steiner
tree generation, 3-bend routing and layer assignment with careful ordering to reduce via
count. The integration of these three techniques with existing academic global routers
achieves signi cant reduction in via count without any sacri ce in runtime.

A via-aware Steiner tree generation technique to form good starting topologies for
multi-pin nets.

Via-aware Steiner tree generation technique to adjust net topology to minimize via
count.

3.1 Via Aware Steiner Tree
As most global routers start to consider vias only in the late stages as maze routing
and layer assignment, they overly rely on these techniques to solve congestion and reduce
via count, where via reduction is often compromised. Moreover, in a common ripup
and reroute framework, global routers avoid rerouting nets as much as possible to save
runtime. So the majority of nets do not go through ripup and reroute process. These
nets keep the original topologies, which are not optimized in terms of via count. Thus,
an early consideration of vias in tree topology generation is essential for the quality of
global router. Our via aware Steiner tree generation technique further extends congestion
driven Rectilinear Steiner Minimal Spanning tree proposed in FastRoute[31]. It computes
suitable topology at the beginning stage of global routing so that global router will
generate less number of via.
After analyzing net topologies, I found that di erent tree topologies have signi cant
impact on via count. As shown in Fig. 3.2, three topologies are generated for a 7-pin net.
Assuming horizontal wires are on metal layer 1 and vertical wires on metal layer 2, the
three topologies will generate 7, 14 and 9 vias respectively, ignoring the contacts between
poly-silicon and metal layers. Here two special structures are de ned: Horizontal Tree
(H Tree) and Vertical Tree (V Tree). H tree is de ned as a rectilinear tree with only one
vertical trunks, with all the other trunks in between the vertical trunks and pin nodes
to be horizontal. Similarly, vertical tree is de ned as a tree with only one horizontal
trunk, with all the other trunks in between the horizontal trunk and pin nodes to be
vertical. If each net is assigned onto two adjacent metal layers, as our layer assignment

algorithm tries to achieve by keeping segments in one net close to each other, H Tree
and V Tree are two extremes in terms of the number of vias. Other trees, like the RSMT
with smaller wirelength shown in Fig. 3, have via count in between. However, it is not
always the case that H Tree would have less number of vias than V Tree. If the resource
on metal layer 1 is used up and the net has to go onto layer 2 and 3, it is obvious that
V Tree is a better choice.
Figure 3.2 Via Aware Steiner Tree
So FastRoute 4.0 adjusts the net topology by the usage and capacity comparison
between horizontal metal layers and vertical ones, as
P
Pcap(h)
usg(h)
=
P
Pcap(v)
usg(v)
, where
P
cap(h) and
22
P
usg(h) is the sum of horizontal capacity and usage of grid edges within the bounding box
of each net.
P
cap(v) and
P
usg(v) are de ned for vertical edges. FastRoute 4.0 multiplies
this factor with the factor used in FastRoute[31] that generates congested driven RSMT
and use the result to scale vertical distances between the pin nodes. Finally, FastRoute
4.0 uses the scaled distance in FLUTE [29] [30] to generate adjusted topology for each
tree. Trees generated in this way will take consideration of both via count and congestion.
For example, if the horizontal resources are more abundant than vertical resources, it
scale down the vertical distances. The RSMT computed by FLUTE for such an scaled net
will have more horizontal edges. In this way, FastRoute 4.0 manipulate the constitution
of horizontal edges and vertical edges in the net structure to reduce via count. The
simulation shows a 3% via count reduction after pattern routing stage with less than 1%
overhead in wirelength and no over
ow overhead.
Rectilinear Steiner minimal tree (RSMT) construction is a fundamental problem that has many applications in VLSI design. In early design stages like physical synthesis, floorplanning, interconnect planning and placement, it can be used to estimate wireload, routing congestion and interconnect delay. In global and detailed routing stages, it is used to generate the routing topology of each net.
RSMT problem is NP-complete. So, in practice, rectilinear minimum spanning tree (RMST) is often used instead of RSMT. This approach is particularly common in early design stages in which the design space is being explored and hence a fast tree construction algorithm is crucial. The disadvantage of this approach is that the length of RMST may be much longer than that of RSMT since Steiner node is not allowed. (up to a difference of 50% in practice).

So we adjust the net topology by the usage and capacity comparison between horizontal metal layers and vertical ones, as

∑ cap ( h ) ∑ usg ( h ) ∑ cap ( v ) ∑ usg ( v )

, where

∑ cap ( h ) and ∑ usg ( h ) is the sum of horizontal capacity and usage of grid edges within the bounding box of each net.

∑ cap ( v ) and ∑ usg ( v ) are de ned for vertical edges.

We multiply this factor with the factor used in FastRoute that generates congested driven RSMT and use the result to scale vertical distances between the pin nodes. See info in this box:

1 capacity comparison factor refer

congestion-driven Steiner tree topology generation technique

and

an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions.

We focus on determining good Steiner tree topology and Steiner nodes locations according to congestion
information.

A congestion-driven Steiner tree topology construction method

A congestion-driven Steiner tree topology construction method to distribute routing demand according to the congestion map.

Most academic and industrial global routers decompose every multi-pin net into a set of two-pin nets by spanning tree or Steiner tree algorithms.

multi-pin nets are typically routed as Steiner trees

routing tree structures

RSMT or minimum spanning tree is constructed for each net and broken into two-pin nets.

Steiner tree structures to construct good Steiner trees

generate the Steiner minimal trees for all the nets using FLUTE

FLUTE is a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm.

1.1 For rectilinear Steiner minimal tree (RSMT) algorithm refer

?????????????????????

The FLUTE rectilinear Steiner minimal tree (RSMT)1 algorithm

The FLUTE rectilinear Steiner minimal tree (RSMT)1 algorithm is an extension of the wirelength estimation approach by fast lookup table.

Def: A rectilinear Steiner minimal tree is a tree with minimum total edge length in Manhattan distance to connect a given set of nodes possibly through some extra (i.e., Steiner) nodes.

the single trunk Steiner tree (STST), which is constructed by connecting each pin to a truck that goes either horizontally or vertically through the median position of all pins

Hanan grid

Let us introduce some notations. Consider an n-pin net. Let xi be the x-coordinate of some vertical Hanan grid line
such that x1 ≤ x2 ≤ · · · ≤ xn. Similarly, let yj be the y coordinate of some horizontal Hanan grid line such that y1 ≤ y2 ≤ · · · ≤ yn. Assume the pins are indexed in ascending order of y-coordinate. Let si be the rank of pin i if all pins are sorted in ascending order of x-coordinate. Therefore, the coordinates of the pin i is (xsi , yi).

Theorem 1 For any net, if there exists r such that si ≤ r for all i ∈ {1, . . . , r} , then an optimal RSMT can be constructed by merging the optimal RSMTs of {Pin 1, . . . , Pin r, (xr, yr)} and {(xr, yr), Pin r + 1, . . . , Pin n}.

Proof: si ≤ r for all i ∈ {1, . . . , r} implies si ≥ r + 1 for all i ∈ {r + 1, . . . , n}. In other words, the x-coordinates of the first r pins are always less than the x-coordinates of the remaining n ? r pins. The first r pins and the other n ? r
pins naturally form two clusters. In any optimal RSMT, there should be at least one “bridge” connecting the two clusters. An optimal RSMT T* that passes through the node (xr, yr) can be constructed by shifting the segments of
each bridge without changing the wirelength. Another RSMT T with the same or less wirelength to T can be obtained by merging the optimal RSMTs for the two clusters with the node (xr, yr) added to both. Hence, T should also be optimal.

Theorem 2 For any net, if there exists r such that si ≥ n ? r + 1 for all i ∈ {1, . . . , r}, then an optimal RSMT can be constructed by merging the optimal RSMTs of {Pin 1, . . . , Pin r, (xn?r+1, yr)} and {(xn?r+1, yr), Pin r + 1, . . . , Pin n}.

Batched 1-Steiner heuristic

Prim’s rectilinear minimum spanning tree (RMST) algorithm

Second, after generating the Steiner trees, we break all Steiner trees into two-pin nets. For every two pin net, we assign the demand to the global edges in the grid graph in the following way. If the two pins of a net have the same x
coordinates or y coordinates, we assign demand 1.0 to each global edge on the straight line connecting the two pins. If the two pins of a net have different x and y coordinates, we assume two possible L-shape (sometimes called 1-bend) routings for it - the upper L or lower L. For each edge on the two L-shape routings, we assign demand 0.5 to it. In this way, we get the very first congestion map.

Finally, in order to make the congestion map more accurate, we perform a fast rip-up and reroute using L-shaped pattern routing. For each two-pin net, we first remove its routing demand from the congestion map which is added in the second stage. Then we perform routing based on the current congestion map by taking the L-shape which passes through a less congested region. After a full round of L-shaped pattern routing for all the two-pin nets, we get
a solution and its corresponding congestion information. We use it as the congestion map for the following congestion-driven Steiner tree construction. Of course, we can use maze routing here, but it will consume a lot of runtime. Since we will change the Steiner tree structures later, it is not worthy to spend the time to perform maze routing in this phase.

Steiner tree structures

An edge shifting technique

An edge shifting technique to move the horizontal or vertical tree edges in a Steiner tree from congested regions to less congested regions without changing wirelength of the tree.

Finally, FastRoute 4.0 uses the scaled distance in FLUTE to generate adjusted topology for each tree. Trees generated in this way will take consideration of both via count and congestion.

For example, if the horizontal resources are more abundant than vertical resources, it scale down the vertical distances. The RSMT computed by FLUTE for such an scaled net will have more horizontal edges. In this way, FastRoute 4.0 manipulate the constitution
of horizontal edges and vertical edges in the net structure to reduce via count. The simulation shows a 3% via count reduction after pattern routing stage with less than 1% overhead in wirelength and no overflow overhead.

Chris Chu, FLUTE: Fast Lookup Table Based Wirelength Estimation Technique," IEEE Intl. Conf. on Computer-Aided Design , pp. 696-701, 2004

C. Chu and Y. C.Wong, FLUTE: Fast Lookup Table-based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 7083, 2008.

Steiner Elmore Routing Tree (SERT)

Terminology

Literature


vertex disjoint trees

vertex disjoint trees
3-Dimensional VLSI routing, 2007, p19..
In
other words, we have to nd vertex disjoint trees with given vertex sets in a
3-dimensional rectangular grid. Clearly, the number of required layers, that
is the height of the routing should be optimized. Because of the diculty
of the problem, most of the routing algorithms are approximate and they
will not necessarily nd the best solutions. As we will see, the problem is
not always solvable even with an arbitrary height, moreover even for small
instances (e.g. when the circuit board is 2x2) there does not exist a sucient
routing. Consequently, we introduce extra rows and columns to guarantee
solvability.

vertex disjoint trees
Arai, Yohei: A Note on the Three-Dimensional Single-Active-Layer Routing, Februaru 2007, p1
This is a special
case of the 3-D channel routing where each terminal is
located on the top or bottom layer. A set of nets is
said to be routable in G if G has vertex-disjoint trees
spanning the nets.

vertex disjoint trees
Kiss, Attila: 3-dimensional routing in VLSI design on a cube. 2005, p1
In a graph theoretical view detailed routing problem is searching for vertex-
disjoint Steiner-trees (trees with given sets containing specific terminals) on a
3-dimensional cubic grid.

vertex disjoint trees
Yamaguchi, Takafumi et al: Complexity 3d channel routing 2005 p2.

Terminology

Literature


Wallace tree


XOR tree

XOR tree
BUTTRICK, MICHAEL T.: TESTABLE CLOCK DISTRIBUTIONS FOR 3D INTEGRATED CIRCUITS Master Thesis, May 2011 p123

These taps are chosen so that the delay between each tap is one-half the period of the desired test
clock frequency. When these taps are fed through an XOR tree, the output will be a launch and
capture pulse at the test clock frequency as seen in Fig. 44.

XOR tree
Kumar, Amit et al: Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing, 2011 EDAA p6 ............

Terminology

Literature


constraint graphs

constraint graphs (CGs)
multi-constraint graph

vertical constrained graph

Layer Constraint Graph (LCG)
range constraints graph
floorplan constraint graphs

constraint graphs
Benini 3D-MPSoCs architectural and design technology outlook p24.pdf

constraint graphs
Gupta Yield Analysis and Optimization p29

Gupta Yield Analysis and Optimization p29

constraint graph

circuit timing graph

Manhattan Routing Tree

rectilinear Steiner routing tree

interval tree

regular clock tree

constraint graphs
Law Block Alignment in 3D Floorplan Using Layered TCG p5

Law Block Alignment in 3D Floorplan Using Layered TCG p5

constraints graphs

closure graphs

Transitive Closure Graph (TCG)

Layered Transitive Closure Graph (LTCG)

slicing tree

constraint graphs

Knechtel, Johann et al: Multiobjective Optimization of Deadspace a Critical Resource for 3D-IC Integration IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012, November 5-8, 2012, San Jose, California, USA p8............

constraint graphs
Li, Xin; Ma. Yuchun and Hong, Xianlong: A Novel Thermal Optimization Flow Using Incremental Floorplanning for 3D ICs p6 ?2009 IEEE

constraint graphs / Vertical Constraint Graph (VCB)
THIYAGARAJAN HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS p5

constraint graphs
Zhou, Pingqiang et al: 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits p8 Aug 2007

multi-constraint graph

vertical constrained graph

Layer Constraint Graph (LCG)

Layer Constraint Graph (LCG)
Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8

Layer Constraint Graph (LCG)
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

range constraints graph

Multiobjective Optimization of Deadspace, a Critical Resource for 3D-IC Integration

Knechtel, Johann et al: Multiobjective Optimization of Deadspace, a Critical Resource for 3D-IC Integration p8

IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012, November 5-8, 2012, San Jose, California, USA

To address both issues, we base our shifting algorithm on the concepts of constraint graphs (CGs) [17, Chapter 3], range constraints [32] and spatial slacks [1] in floorplanning. Representing a floorplan using a CG pair (horizontal and vertical graph) allows us to maintain a valid placement and to handle the relations between block positions efficiently. Spatial slacks describe maximal possible shifting ranges of blocks within the given floorplan outline, whereas range constraints are used to limit shifting within certain regions.

In our incremental flow, we initially generate the CG pair for each die separately, considering placed blocks, and update them during TSV planning. Furthermore, we transform block and TSV coordinates (x; y) into range constraints [x -δ ; x + δ]; [y - δ; y + δ], defining different shifting windows (Figure 3a). In order to judge the feasibility of considered sites during TSV planning, i.e., the capabilities for required block shifting, we determine and annotate slacks to the CGs. Note that we determine slacks for both possible shifting directions to account for non-packed floorplans. During slack determination, shifting windows are considered as limits, as illustrated in Figure 3b.

Fig. 3. Handling of range constraints. (a) Block and TSV boundaries are extended by range constraints, defining shifting windows (dotted rectangles). Note that shifting windows of TSVs originate from their rectangular keep-out zone (KOZ). (b) The related horizontal CG with annotated slacks. During slack determination, window dimensions are considered as limits. Affected slack values are underlined.

floorplan constraint graphs

Assembling 2D Blocks into 3D Chips

Knechtel, Johann; Markov, Igor L. and Lienig, Jens: Assembling 2D Blocks into 3D Chips p8 ISPD’11, March 27–30, 2011, Santa Barbara, California, USA. ..................
Floorplan modifications based on constraint graphs are
discussed in detail in [25].To this end, we maintain the floorplan configuration
using constraint graphs and implement block shifting as follows.
First, block dimension is inflated by the amount of displacement,
and then standard path-tracing algorithms are applied to the constraint
graph to find new block locations. To speed up this procedure,
path-tracing can be performed incrementally, not unlike in
incremental Static Timing Analysis.

Terminology

Literature


Graph Model / Representations for 3D IC Design

Graph
Tree
Clique
Forest

Planar graph

planar triangulated graph

complete graph
weighted directed complete graph
interval graphs

multigraph

directed multigraphs

connected graph

rectilinear graph

bipartite graph

edge-weighted bipartite graph

maximum weight bipartite graph

directed graphs

directed acyclic graph (DAG)

directional acyclic graph

annotated directed graph
Structured Directed Graph

complete directed acyclic graph

weighted shortest path subgraph
clique

resource compatibility graph

Definition The resource compatibility graph C+(V. E) is a graph whose vertex set V = (u;, i = 1.2.. . . , n,,,] is in one-to-one correspondence with the operations and whose edge set E = ( ( u , , L?] i. j = 1.2,. . . .n ,,,,I denotes the compatible operation pairs.

Line-of-sight graph


Graph Model / Representations for 3D IC Design

Grid / Lattice Graph for 3D IC Design

grid graph, also called a lattice graph

grid graph

3D grid graph
grid graph in 3d ic
grid graph in 3d integrated circuits
grid graph in three dimensional integrated circuits
grid graph in 3d VLSI
grid graph in three dimensional VLSI

global grid graph

parallel grid graph

uniform grid graph

weighted grid-graph

edge grid graph

global routing grid graph

3D global routing grid graph

Multi-Level Grid Graph

top level grid graph

higher level grid graph

higher level grid graphs

low level grid graphs

Lower Level Grid Graph

lowest level grid graph

Level-i grid graph

small grid graph

smaller sized grid graph

coarse grid graph

coarsened grid graph

coarser grid graph

finer grid graph

lattice graph

planar lattice graph

planar edge-weighted lattice graph

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Grid Graphs

Grid Graphs / Global Routing Grid Graph

Graph Models for Global Routing Grid Graph Nov 2002 p17.

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Graph Models for Global Routing: Grid Graph

 Each cell is represented by a vertex.
 Two vertices are joined by an edge if the corresponding cells are adjacent to each other.
 The occupied cells are represented as lled circles, whereas the others are as clear circles.

Global Routing by Integer Programming

 Suppose that for each net i, there are ni possible trees ti
1; ti
2; : : : ; ti
ni
to route the net.
 Constraint I: For each net i, only one tree ti j will be selected.
 Constraint II: The capacity of each cell boundary ci is not exceeded.
 Minimize the total tree cost.
 Question: Feasible for practical problem sizes?
{ Key: Hierarchical approach!

Grid Graphs / coarse grid graph
Areibi, Shawki; Xie, Min and Vannelli, Anthony: AN EFFICIENT RECTILINEAR STEINER TREE ALGORITHM FOR VLSI GLOBAL ROUTING 1997 p6

Shawki Areibi
School of Engineering
University of Guelph
CANADA N1G 2W1
E-mail: sareibi@uoguelph.ca

Min Xie and Anthony Vannelli
Electrical Engineering Dept
University of Waterloo
CANADA N2L 2G1
E-mail: vannelli@cheetah.vlsi.uwaterloo.ca

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

1. INTRODUCTION

Physical design of VLSI circuits is the process of mapping structural representations of circuits into layout representation of circuits. Structural representations describe the system in terms of logic components and their interconnects. Layout representations define circuits in terms of a set of geometric objects which specify the dimensions and locations of transistors and wires on a silicon surface. After the placement phase, we have to connect the pins among the modules according to the specified netlist. The routing area of the chip can be represented by a grid graph. The vertices of the grid graph represent the potential pins and vias, and the edges represent the capacity of a channel or a switch box. A channel is the routing space between two blocks and a switch box is the routing space enclosed by the blocks. The routing stage is divided into global routing and detailed routing.

2.1. Standard Cell Design

.....................................

The global routing problem is usually studied as a graph problem. The total area of the chip can be represented as a grid-graph where vertices are potential position of pins and vias. For standard cell layout style, each module of the circuit is represented by a vertex of the graph. If module ci and cj are placed adjacent to each other after placement phase, then there is an edge connecting the vertices that represent ci and cj . Figure 2 (b) shows a grid-graph with 15 vertices. The number of vertices is determine by Rx and the number of cell rows in the chip. Rx is the row with maximum number of modules in the chip. If a row does not have the same number of cells as Rx , we put empty vertices in that row to make the grid-graph have the same number of vertices per row.

Fig. 2. Segmentation of the chip and the coarse grid graph.
=================================

3.1.2. L-edge Generation and Local Tree Modification

Once steiner trees for all nets have been generated independently, we have to map the tree arcs to the underlying edges in the grid graph G. Each arc in a tree is mapped to an L– edge, using a specified L–orientation. An L–edge consists of a horizontal segment and/or a vertical segment depending on the location of a vertex and its parent. If a vertex and its parent are located on the same horizontal line then the arc is only mapped to a horizontal segment; the same applies for the pair of points that lie on the vertical line. If a pair of points is non-colinear, then both horizontal and vertical segments are needed to connect the points. Both segments are located on the border of the boundary box for the pair of points.
=================================
When we finish mapping the arcs of a tree to the edges of the grid graph, we check the edge usage to make sure that each edge is used once for a tree. If an edge is used more than once, then the extras are removed from the edge set of the tree. This is to make sure that we don’t over estimate the edge usage, and force it closer to the edge’s capacity which would make the solution to global routing problem inferior.

Grid Graphs / coarse grain grid graph
Chang, Yen-Jung; Lee, Yu-Ting and Wang, Ting-Chi: NTHU-Route 2.0 A Fast and Stable Global Router p6

Yen-Jung Chang
Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 30013
Email: jalamorm@gmail.com

Yu-Ting Lee
Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 30013
Email: leetroy@gmail.com

Ting-Chi Wang
Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 30013
Email: tcwang@cs.nthu.edu.tw

grid graph

coarse grain grid graph

balanced search tree

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Typically, the routing problem can be divided into global routing and detailed routing due to the problem complexity. During global routing, a design is often modeled as a two-dimensional (2D) coarse grain grid graph and then a global route for each net is determined from the graph. After that, a layer assignment process is applied for a multi-layer design, and finally detailed routing is solved by taking the solution from global routing as the input. The quality of global routing influences the timing, power and density of a chip, and thus global routing is a very crucial stage in the design cycle.

A. Problem Formulation

The global routing problem can be modeled as follows. There is a grid graph G(V,E). As illustrated by the three-layer (denoted by M1, M2, and M3) example shown in Fig. 1, each vertex in V corresponds to a global bin and each edge in E corresponds to a global edge which is a boundary between two adjacent global bins. There is also a set of nets, where each net is composed of a set of pins, and each pin corresponds to a vertex. The routing problem for a net is to find a route connecting all the pins of the net using the edges of G.

Fig. 1. (a) Decomposition of global bins (b) Grid graph for routing
The capacity cg of an edge g represents the number of available routing tracks. The demand dg represents the number of nets that pass through edge g. The overflow of an edge is defined to be the amount of demand that exceeds the capacity of the edge. We also define the congestion of edge g as the ratio of the demand to the capacity, i.e., dg / cg . The major objective of the global routing problem is to minimize the sum of the overflows among all edges (total overflow), while the second objective is to minimize the wirelength. In multi-layer designs, wirelength calculation also involves vias.

Grid Graphs

Cho, Minsik et al: BoxRouter 2.0 Architecture and Implementation of a Hybrid and Robust Global Router 2007 IEEE p6.... ............2

Minsik Cho, Katrina Lu, Kun Yuan, and David Z. Pan
Dept. of ECE, The University of Texas at Austin, Austin, TX 78712
{thyeros, yiotse, kyuan}@cerc.utexas.edu, dpan@ece.utexas.edu

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

A. Global Routing Background

The global routing problem can be modeled as a grid graph, where each rectangular region of the circuit can be represented by the same number of vertices as the number of metal layers in the given manufacturing process. Fig. 1 shows a grid graph for routing from a circuit in multi-metal layer manufacturing process. Each metal layer is dedicated to either horizontal or vertical wires. A vertex is called a global routing cell (G-cell), and each edge represents the boundary between G-cells. Each edge has maximum routing capacity, and each wire passing the edge takes some routing capacity based on its width/spacing. When the demand from wires exceeds the maximum routing capacity of the edge, overflow occurs. The number of overflow can be computed as the excessive demand [8], [13]. Thus, a global routing is to find paths that connect the pins inside the G-cells through the graph for every net with minimum number of overflows [8]. Since a net may have complex topology, it can be decomposed into two pin wires with Rectilinear Minimum Steiner Tree [1], [16].

Fig. 1. A circuit with netlists can be dissected into multiple grids which can be mapped into graph for global routing [1].

Grid Graphs
Cong Performance-Driven Global Routing for Cell Based IC’s p4
According to the result in [6], constructing a minimum spanning tree with bounded radius in a general graph is NP-complete. However, this result does not imply that the BRMST problem is NP-complete since in our formulation, terminals are in the Manhattan plane (whose underlying graph is a grid graph) rather than a general graph. So far, the exact complexity of the BRMST problem is still unknown, and the objective of this paper is to present a heuristic algorithm for the BRMST problem. Our goal is to construct a bounded-radius spanning tree with small cost.

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Cong Performance-Driven Global Routing for Cell Based IC’s p4

grid graph

routing tree

minimum radius routing tree

minimum-cost routing tree

spanning tree

minimum spanning tree

minimum spanning trees of bounded radius

bounded radius minimum spanning trees

bounded-radius spanning tree

minimum radius spanning tree

minimum cost spanning tree

RC tree

Grid Graphs / lattice graph
Deza, Antoine; Dickson, Chris; Terlaky Tamas; Vannelli. Anthony and Zhang, Hu: Global Routing in VLSI Design Algorithms, Theory, and Computational Practice JCMCC 12 May 2011 p25.

Email addresses: deza@mcmaster.ca (Antoine Deza),

cdickson@bedlamgames.com (Chris Dickson),

terlaky@lehigh.edu (Tam?as P Terlaky),

vannelli@uoguelph.ca (Anthony Vannelli),

Hu.Zhang@rbccm.com (Hu Zhang).

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Theorem 2.2 There is an approximation algorithm for (2) such that the objective value is bounded by:
8>><
>>:
r(1 + ")OPT + (exp(1) ? 1)(1 + ")
p
r ￠ OPT ln m; if r ￠ OPT > lnm;
r(1 + ")OPT +
exp(1)(1 + ") lnm
1 + ln(lnm=(r ￠ OPT))
; otherwise;
where OPT denotes the optimal value of the instance, r is the approximation ratio of the block solver, and m is the number of edges in the grid graph.

Line 1 involves initializing local variables as well as transforming the grid graph G into a virtual layer graph which will be denoted as H. In lines 2 ? 4 we generate a tree for each net in S. To achieve this, we simply call our approximate Steiner tree solver which will generate a tree when given the graph H and a net Sk. In line 5 we compute the edge congestion for each edge in G. The edge congestion for the edge ei is equal to the number of trees crossing it.

Algorithm 1: Approximation algorithm for global routing in VLSI design.
Input: A graph G = (V;E) and a set of nets S1, . . . , SK, where Sk μ V for
k 2 f1 : : :Kg.
Output: A set of K trees where the k-th tree in the set spans Sk.
1 Initialization of variables and virtual layer graph generation
2 for k ? 1 to K do
3 Call approximate Steiner tree solver to generate a tree for Sk
4 end
5 Compute edge congestion
6 while stopping criteria not satisfied do
7 Reweight edges in graph
8 for k ? 1 to K do
9 Call approximate Steiner tree solver to generate a tree for Sk
10 end
11 Compute a step length ? and move to new solution
12 Update edge congestion
13 end
14 Perform rounding such that we choose one tree to route each net Si

3.2 Minimum Steiner Tree Approximation

The minimum Steiner tree problem is APX-hard [7]. For certain instances, it is possible to get a true minimum Steiner tree fast for certain instances (but not in polynomial time for all instances). Geosteiner [35,36] is a software package that computes minimum Steiner trees, however it operates only on planar lattice graphs. Also, these graphs are assumed to have unit length. Although the edge lengths in our grid graph may have unit length, the edge weights in the virtual layer graph may not have unit length. Thus, this package is unsuitable in our algorithm. Additionally, Geosteiner does not run in polynomial time in the worst case. Recently developed Flute [9] provides improved techniques for generating rectilinear minimum Steiner trees but in our model the weighted graph H needed to obtain the theoretical approximation bound can not be assumed to be always rectilinear. We wish to clarify some similarities with existing approaches and stress that the main difference is the obtained theoretical approximation bound. In fact our algorithm does not use either Geosteiner or Flute to generate the minimum Steiner trees. The column generation technique in [38] is similar to our reweighting technique but, while we search for the minimum among all possible Steiner trees in Tk for each net Sk, the column generation technique in [38] uses only the minimum within a pre-determined subset of Tk. Again the main difference is that no theoretical approximation ratio for GRIP is given by the column generation technique in [38]. From now on, the notion of minimum Steiner tree will be abbreviated as MST.
In our implementation, we allow the solutions from a sequential router called Labyrinth [18] to warm start our algorithm. Labyrinth uses the maze runner heuristic introduced by Lee in [21]. While being very good at finding feasible solutions, Labyrinth has serveral limitations. First, the grid graph must be uniform. That is, there may not be holes in the graph. Also, capacity must be uniform across the graph, restricted to a single horizontal and vertical value. Additionally, this program does not take into account vias or bends in the trees. We may use these warm solutions to reduce the running time of our own algorithm, but in order to fully exploit this technique, further investigation is needed.
It is worth noting that it is unknown whether there exist feasible solutions (edge capacities constraints are fulfilled) for the MCNC benchmark instances. Therefore, our algorithm cannot always deliver feasible solutions, similar to other global routers, e.g., [40]. For solving the MCNC benchmark instances, we set the feasibility with the highest priority, i.e., to first minimize the violation of edge capacity constraints. Then we try to minimize the objective function (wire-length and via number) without increasing infeasibility. The motivation of this strategy is as follows: If the edge capacity is exceeded in a routing solution (even if on only one edge), we have, in parctice, to add an extra identical routing layer (a parallel grid graph) to accommodate the overflow wires for routing all nets, which leads to significant increase of manufacture costs. Therefore, we allow slight increase on the objective function value as the price to reach better feasibility in our routing solutions.

Grid Graphs / lattice graph

DICKSON, CHRIS: , SUPERVISORS: Dr. Antoine Deza: Global Routing in VLSI Algorithms, Theory, and Computation Master Thesis, May 2007 p76

grid graph

layer graph

virtual layer graph

lattice graph

path graphs

Minimum Spanning Trees

Steiner Tree

minimum Steiner tree

Steiner Minimal Trees

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

In the global routing problem, we aim to minimize the wire-length for the ultimate physical design of the circuit. Generally, the circuit is modeled as a grid graph. An m × n grid graph, also called a lattice graph, is the product of path graphs on m and n vertices. A path graph is a tree with two vertices of degree 1, and the remaining n ? 2 vertices of degree 2. An example of a grid graph is illustrated in Figure 1.4(a) (see page 15). Thus, the vertices of a grid graph represent the components in the circuit, and the edges represent the routing channels or the areas in which wire may be placed. A set of vertices which need to be connected with wire is known as a net. Each vertex contained in a net is called a terminal. In a particular instance of the global routing problem, we are given many nets to connect. Furthermore, each edge of the grid graph is associated with an integral capacity constraint. That is, the number of wires that may pass through that edge. A solution to the global routing problem is a set of trees that connects the terminals of each net, and satisfies the edge capacity constraints.

Figure 1.4: An example of the Steiner minimal tree problem in graphs.

Formally, we are given a planar, weighted grid graph G = (V,E) and a set of nets S1, . . . , SK  V . The edge set is associated with a length function l : E ! R+ [ {0} and a capacity function c : E ! R+ 2. We assume that |Sk| is bounded by some constant for all k = 1, . . . ,K. A feasible solution is a set of K trees spanning S1, . . . , SK with respect to the edge capacity constraints. The overall cost of the solution consists of two parts: (i) the edge cost and (ii) the total number of bends in the trees called the bend-dependent vertex cost (see Figure 2.1). The goal is to minimize the overall cost defined as a linear combination ltotal + vtotal, where ltotal is the sum of edge length of all K trees and vtotal is the sum of numbers of bends of all K trees, while ,  0 are predefined weights representing to the impact of the total wire-length and the total number of bends in the trees whose values are set according to the design requirements and are given in advance. In VLSI design, bends in trees are known as vias. For simplicity, we denote by ci the capacity of edge ei 2 E from now on. In addition, by scaling, we can set + = 1, i.e., the overall cost is a convex combination of the total edge length and the total number of bends.

Figure 2.1: Figure illustrating bends within a path.

We will apply the approximation algorithm L in [13] for convex minmax resource-sharing problems. Algorithm 4 (see page 26) is a specialization of L for the global routing problem. By applying this algorithm, we avoid the exponential size of T . In L, we generate K minimum Steiner trees for the K nets in each iteration. Thus, there is only a polynomial number of Steiner trees generated in total. In fact, it is shown in [26] that the approximation algorithm generates at most O(Km(logm + "?2 log "?1)) Steiner trees, where m is the number of edges in the grid graph, and the following result for the fractional global routing holds:

Theorem 2.1. Algorithm 4 is an r(1 + ")-approximation algorithm for the fractional global routing problem (2.2) provided that an r-approximate minimum Steiner tree solver is available.

Figure 2.2: Original grid graph G.
Theorem 2.2. Algorithm 4 is an approximation algorithm for the linear problem (2.2) such that the objective value is bounded by:
8><
>:
r(1 + ")OPT + (exp(1) ? 1)(1 + ")
p
r · OPT ln m, if r · OPT > lnm;
r(1 + ")OPT +
exp(1)(1 + ") lnm
1 + ln(lnm/(r · OPT))
, otherwise,
where OPT denotes the optimal value of the instance, r is the approximation ratio of the block solver, and m is the number of edges in the grid graph.

3.1 Outline

We now present a basic outline of the approximation algorithm used to solve the LP (2.2) in Chapter 2. We outline this in Algorithm 4.

Our input is given as a grid graph G = (V,E). Usually, this is simplified to two integers corresponding to the length and the width of graph G. Additionally, we may be given a list of missing vertices (holes) and/or an edge length function. If no edge lengths are specified, then they are assumed to be of unit-length, i.e., length one. We are also given a non-empty set of nets. Each net Sk is a set of vertices (coordinates) in G, where |Sk|  2 for k 2 {1 . . .K}.

Algorithm 4: Approximation algorithm for global routing in VLSI design.
Input: A graph G = (V,E) and a set S of nets where |S| = K and
Sk  V for k 2 {1 . . .K}.
Output: A set of K trees where each tree in the set spans its corresponding net in S.
1 Initialization of variables and virtual layer graph generation
2 for k 1 to K do
3 Call approximate Steiner tree solver to generate a tree for Sk
4 end
5 Compute edge congestion
6 while stopping criteria not satisfied do
7 Reweight edges in graph
8 for k 1 to K do
9 Call approximate Steiner tree solver to generate a tree for Sk
10 end
11 Compute a step length  and move to new solution
12 Update edge congestion
13 end
14 Perform rounding such that we choose one tree to route each net Si

Line 1 involves initializing local variables as well as transforming the grid graph G into a virtual layer graph which will be denoted as H. In lines 2 ? 4 we generate a tree for each net in S. To achieve this, we simply call our approximate Steiner tree solver which will generate a tree when given the graph H and a net Sk. In line 5 we compute the edge congestion for each edge in G. The edge congestion for the edge ei is equal to the number of trees that pass through it.

3.2 Steiner Tree Approximation

The Steiner minimal tree problem is APX-hard. An optimization problem is APX-hard if it is NP-hard and it admits a constant-factor approximation algorithm [3]. For certain instances, it is possible to get a true Steiner minimal tree fast (but not in polynomial time). GeoSteiner [27] is a software package that computes Steiner minimal trees, however it operates only on planar lattice/grid graphs. Also, these graphs are assumed to have unit length. Although the edge lengths in our grid graph may have unit length, the edge weights in the virtual layer graph may not have unit length. Thus, this package is unsuitable in our algorithm. Additionally, GeoSteiner does not run in polynomial time in the worst case. From now on, the notion of Steiner minimal trees will be abbreviated as SMT and the abbreviation MST refers to the minimum spanning tree problem.
In our implementation, we allow the solutions from a sequential router called Labyrinth [18] to warm start our algorithm. Labyrinth uses the maze runner heuristic introduced by Lee in [19]. While being very good at finding feasible solutions, Labyrinth has serveral limitations. First, the grid graph must be uniform. That is, there may not be holes (missing vertices) in the graph. Also, capacity must be uniform across the graph, restricted to a single horizontal and vertical value. Additionally, this program does not take into account vias or bends in the trees. We may use the solutions produced by Labyrinth to reduce the running time of our own algorithm. However, in order to fully exploit this technique, further investigation is needed.

Figure 4.1: A bounding-box for a net in a grid graph (edges ommited).

Grid Graph
Ellis-Monaghan Graph Theoretical Problems in Next-Generation Chip Design p17

Grid Graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68......................... 9
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Maze routing

One basic subproblem that is commonly encountered in global routing is that of finding a shortest path connecting two pins in the presence of wiring blockages. Perhaps the most well known solution to this problem is the maze routing [54,66] algorithm, which works on a routing graph similar to the grid graph in Figure 2(a). Each edge e has a cost c(e) associated with it, and this cost may be different for different routing directions. If an edge e is within the wiring blockage area, then its cost c(e) = ∞; otherwise its cost is finite and specified. A common cost metric is the rectilinear edge length, counted in terms of the number of grid cells.

Figure 2: The construction of a routing graph from the tessellation for a two-layer routing scheme. Via constraints are explicitly modeled in (b) but not in (a).

If there is an optimal shortest path, maze routing is guaranteed to find it. However, in practice, it is found that the maze routing algorithm is slow and has large memory requirements, and many efforts [78] have attempted to improve its speed and memory usage. Another well known class of methods is the category of line probe-based algorithms (see, for example, [34]), which do not rely on a grid graph. While these methods are faster than maze routing, they are not guaranteed to find a solution, even if one exists. For a good description on maze routing and related algorithms, the reader is referred to [78].

9.4 Hierarchical routing for custom design

The hierarchical methods introduced in sections are all based a uniform grid graph. In [62], Luk et al. proposed a hierarchical global routing method for custom circuit design based on a slicing floorplan, as shown in Figure 21(a), where each rectangle is a building block. The routing graph for such a design is a dual graph for the floorplan as shown in Figure 21(b). It is assumed that the detailed location of each pin has not been assigned at this stage, and therefore the pins within each building block are assumed to lie at its center, as shown in Figure 21(a) by the solid squares. In the routing graph in Figure 21(b), each node (round dot) corresponds to a building block and an edge is set up for every adjacent building blocks. Each edge has an edge length, given by the Manhattan distance between the two rectangles that this edge connects. In addition, a routing capacity is associated with each edge.

Grid Graphs

Li: Yih-Lang (李毅郎): Modern 3-D Global Routing and Parallelism on X86 Multi-Core Platform Dec 2009 p70.

grid graph

Routing trees

spanning tree

minimum spanning tree

Steiner tree

Minimum Steiner Tree

Rectilinear Steiner Minimum Tree (RSMT)

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Cost Function
??
Cost function is used to capture the cost to use a specific global edge in the grid graph
??
Abrupt function (Labyrinth)
??
Piece-wise linear function (Chi Dispersion Router)
??
Logistic function (FastRoute)

Grid Graphs

Mahapackialakshmi, K. and Sivakumar, P.: Aerial Monotonic based Layer Assignment on 3D Global Routing p4.... Special Issue of International Journal of Computer Applications (0975 – 8887) on International Conference on Electronics, Communication and Information Systems (ICECI 12)

grid graph

Steiner trees

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

2.1 Global Routing: Problem Formulation

The problem of global routing can be characterized as follows: there is a grid-graph G specifying a set of vertices V and a set of edges E. As shown in Figure 1, each vertex vi 2 V corresponds to a particular rectangular region (or cell) of the chip, and each edge eij 2 E corresponds to a boundary between adjacent vertices (with a maximum allowable resource mij). There is also a set of nets N, where each net ni 2 N is composed of a set Pi of pins (with each pin corresponding to a vertex vi). A solution is a mapping of nets to routes, in which each route connects all the pins of a net using the edges of the graph G. When evaluating a routing solution (or, for that matter, a routing engine), one is typically concerned with three metrics. Overflow refers to the total amount of demand that exceeds capacity over all edges. As it directly corresponds to the routability of the design, overflow is minimized (ideally zero). Wirelength is the combined length of segments needed to route all nets, and should also be minimized. In three-dimensional routing, this calculation can also include vias, special wires used to connect segments between adjacent layers of metal. Finally, one may be concerned with the runtime needed to construct the solution. This is especially true in cases where global routing is repeatedly used to guide a placement algorithm. Global routing is a textbook example of a multi-objective optimization problem, in which the relative importance of the individual criterion depends heavily on the greater context and application. As is illustrated in figure 1, the whole routing region is partitioned into a number of global bins. Each global bin is represented by one node and each common boundary is represented by one edge in the grid graph. The edge is called global edge with the capacity of ce. The overflow is defined as how much is usage ue over the ce. If ue is smaller than ce, oe = 0, otherwise oe = ue ? ce.

Figure 1: The bin decomposition and grid graph of the global routing problem formulation. (a) Global bin decomposition (b) Corresponding grid graph

5.1 Integer Programming Formulation

In a mathematical description of the global routing problem, we are given a grid-graph G = (V,E) describing the network topology, a set of (multi-terminal) nets given by N = {T1, T2, . . . , TN}, (with Ti ? V ), and edge capacities ue and weights ce ?e ∈ E. Denote by T (Ti) the collection of all Steiner trees (routes) connecting the terminals in Ti, and let the parameter ate = 1 if Steiner tree t contains edge e ∈ E, ate = 0 otherwise. Define the binary decision variable xit that is equal to 1 if and only if net Ti is routed with route t ∈ T (Ti). An integer program for the global routing problem can be written as,

Grid Graphs / uniform grid graph

Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

We model the floorplan layer in the SOP as a floor connection graph [2]. The routing layer is modeled as a uniform grid graph. These two kinds of graphs are connected through via edges. The advantage of our graph-based routing resource model is that we can consider layer/pin assignment and global routing simultaneously. We model the blocks in the floorplan as Block Nodes (BN). The nets can cross over to the adjacent routing layers only through the regions in the channel. The channel itself is represented by Channel Nodes (CN). The actual blocks form blockages for the nets, which cannot be routed through them. The nets can switch from floorplan layer to the routing layer only through designated regions which are represented as Layer-switch Nodes (LN) in the resource graph. The LN in this case is simply four corners of the blocks. They denote regions rather than points through which nets will traverse to adjacent routing intervals. The routing layers are represented by a grid graph, each node specifying a region in the layer and edges representing the adjacency between regions. These nodes are called Routing Nodes (RN). The concepts are illustrated in Figure 2, which shows the various views and types of nodes used in SOP.

Figure 2. The floorplan and the layer view of the resource graph with node and edge types. Double circle, square, black dot, and white dot respectively denote the layer switch, block, channel, and routing nodes.

Grid Graphs
Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Our goal during optical waveguide construction is to choose the most optimum nets for optical routing based on their locations and properties such as wirelength, delays, and number of bends. In our model, each routing layer is represented by a grid graph , where each node specifies a region in the layer and each edge represents the adjacency between neighboring regions. The nodes and edges are characterized by capacities. Specifically, the nodes are annotated with optical device capacities and the edge capacities correspond to number of waveguides. A simple calculation based on the dimensions given in [2] for a 1 cm by 1 cm package, represented by a 10 10 routing grid, gives the node capacity to be 4 and edge capacity can vary between 4 to 8 [4]. In this paper, we assume the edge capacity to be 4. In addition, each waveguide can carry up to 10 multiplexed signals. This means there are up to 40 nets that can be assigned to each routing edge in .

Grid Graphs
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Grid Graphs
Sanusi, Azeez O. and Bayoumi, Magdy A: . SEGRoute A New Global Routing Methodology Based on Grid Graph Segmentation 2005 p4...........

Azeez O. Sanusi
Center for Advanced Computer
Studies, University of Louisiana at
Lafayette
Lafayette, LA 70504

Magdy A. Bayoumi
Center for Advanced Computer
Studies, University of Louisiana at
Lafayette
Lafayette, LA 70504

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

ABSTRACT

In this paper, we propose a new global routing methodology named SEGRoute, which is based on grid graph segmentation of the given routing problem. The SEGRouting methodology first divides the grid graph of the routing problem into various segments; it then performs routing for the various segments (completing routing if possible and trying to maintain minimum wirelength) and then performs a “segment congestion-driven” Steiner tree construction for fast construction of Steiner trees and to eliminate routing congestion. We also propose an algorithm for efficient grid segmentation and methodologies for “segmentbased” global routing. Our experimental results show that SEGRoute produces better wirelength solutions and comparable congestion solutions in up to 96x and 57x faster runtimes than the state-of-the-art published global routers, Labyrinth 1.1 [1] [13] and Fengshui 5.1 [2] (the newest implementation of the Chi dispersion router).

In this paper we propose a new global router, SEGRouter which is based on the idea of grid segmentation. SEGRouter divides the grid graph into various segments; it then performs routing for the various segments, completing routing if possible and trying to maintain minimum wirelength, and then performs fast rectilinear Steiner tree construction pruning trees based on obtained segment congestion values. The major contributions of this work are as follows:

1) An efficient algorithm for rectilinear Steiner tree construction based on grid segmenting and segment congestion.
2) A simple and efficient algorithm for grid graph segmentation.
3) Proposed methodologies for “segment-based” global routing.

2. PRELIMINARIES

The grid graph model is the most commonly used model in global routing. In this model, the routing area is partitioned into rectangular regions called global bins with the assumption that all pins in a bin are at the center of the bin (with the centers making up the global routing graph). The boundary of each global bin is called a global edge and it corresponds to an edge in the grid graph (see figure 1). Each global edge has a maximum amount of routing resources i.e. capacity (The number of routing tracks available).

Figure 1. The grid graph model.

3. SEGRouter

3.1 Basic Idea

Here we present the basic Idea of the SEGRouter, we will go into more details in the following sub-sections. The idea of the SEGRouter is to divide the grid graph into various segments, perform routing on these segments (completing routing if possible). We then obtain segment congestion values and construct Steiner trees by quickly “pruning” topologies with pins in segments with higher congestion values.

3.3 Grid Segmentation

The methods described above can work well only if we can always be certain that the grid graphs will be divided into segments that are as balanced as possible. Since it is not always guaranteed that we will always be able to divide all grid graphs into a nonprime number of segments (as graph sizes vary), we need an algorithm that will ensure that segment sizes are as balanced as possible (the algorithm must create segments of equal sizes when possible). This being said, we must also make sure that the number and sizes of segments created are just enough to allow effective congestion estimation and RST construction, as too many segments could begin to have a negative effect on the run time since it could lead to a higher number of unlocked nets (we discuss this in more detail in section 4). Experimental results also showed that better RST construction can be achieved by making sure that most of the segments are square shaped. For example, it will be better to use 3 by 3 segments, creating 16 segments for a 16 by 10 (note that the notation x by y is used) grid graph rather than creating 20 segments of 2 by 4. The pseudo-code for the grid segmenting algorithm is given below and sample illustrations of how it segments unbalanced 16 by 10 grid graph is not shown due to space issues.

Algorithm:
Input: Size of grid graph; x by y
Output: Grid graph segmentation
1: SEG = 0;
2 for (i = 0 to x; increment i by sqrt(y))
3: for (z = 0 to y; increment z by sqrt(y))
Now we add create segments of size sqrt(y) by
sqrt(y)
4 for (j = i to sqrt(y); j = j + 1){
5: for (k = z to sqrt(y); k = k +1)
6: Grid[j[k] = SEG + 1;
Add bin to segment
}
7: SEG = SEG + 1; move to next segment
End

4. Experimental Results

We implement the SEGRouter in C++ and perform our tests on the ISPD 98 IBM benchmarks using a 1.5GHz Linux machine. We compare our result to Labyrinth 1.1 and Fenshui 5.1 (the newest implementation of the Chi dispersion router), which are two state of the art academic routers. Figure 2 below shows how the number of segments created affects the runtime of SEGRouting (as mention in section 3.3). Note from the figure that for a low amount of segments the runtime is high, as this will be almost equivalent to routing without the grid segmentation and segment- congestion driven Steiner tree construction. However as the number of segments get higher the runtime time will begin to increase again as too many segments would lead to a higher number of unlocked nets, hence more net will need to be considered during rip-up and re-route. In effect, we have to exploit the concave nature of the graph.

5. CONLUSION

In this paper, we present a new global router called SEGRouter which is based on the idea of grid graph segmenting and “segment-congestion” driven Steiner tree construction. SEGRouter has been shown to achieve better wirelength solutions and comparable congestion solutions when compared to Labyrinth 1.1 and Fengshui 5.1 in up to 96x and 57x faster runtimes respectively. In future, we hope to improve the solutions, especially congestion solutions. We believe that this is can be made possible by adopting and trying to incorporate some other routing schemes with the SEGRouting methodology. Though this has not yet been verified.

Grid Graphs
Shi Cooling of 3D-IC Using Non-Uniform Micro-channels and Sensor Based Dynamic Thermal Management p8

Shi Cooling of 3D-IC Using Non-Uniform Micro-channels and Sensor Based Dynamic Thermal Management p8

grid graph

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

lattice graph
Terlaky Routing in VLSI Design and Communication Networks p26.pdf

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Grid Graphs
Vygen, Jens: Faster Resource Sharing and Global Routing in Theory and Practice Nov 2011 p88.

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Routing: simplified view
Find vertex-disjoint Steiner trees connecting given terminal sets in a 3-dimensional grid graph.
Order of magnitude:
10 million Steiner trees in a graph with 100 billion vertices!
!Even linear-time algorithms are too slow!
Global routing: classical problem formulation
Instance:
I a global routing (grid) graph with edge capacities
I a set of nets, each consisting of a set of vertices (terminals)
Task: find a Steiner tree for each net such that
I the edge capacities are respected,
I and (weighted) netlength is minimum.

Grid Graphs
Wu, Tai-Hsuan et al: GRIP: Scalable 3D Global Routing Using Integer Programming, Proc. of Design Automation Conference, pp. 320-325, 2009, p6

grid graph

Steiner trees

minimum-weight Steiner tree

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Compared to [3], our candidate routes are generated by vary- ing a base Steiner route, considering congestion as weights in a grid-graph as well as the other candidate routes generated so far at each iteration of column generation.

2.1 An Integer Program for the GR Problem

In a mathematical description of the global routing prob- lem, we are given a grid-graph G = (V,E) describing the network topology, a set of (multi-terminal) nets given by N = {T1, T2, . . . , TN}, (with Ti ? V ), and edge capacities ue and weights ce ?e ∈ E. Denote by T (Ti) the collection of all Steiner trees (routes) connecting the terminals in Ti, and let the parameter ate = 1 if Steiner tree t contains edge e ∈ E, ate = 0 otherwise. Define the binary decision vari- able xit that is equal to 1 if and only if net Ti is routed with route t ∈ T (Ti). An integer program for the global routing problem can be written as

Figure 1: Improving routes via a shortest path algorithm on a weighted grid-graph

Figure 2: Modifying grid-graph of a subregion to handle floating terminals within our IP procedure.
Each subregion defines a new grid-graph G′(V ′,E′) and set of nets N′ ? N. The set N′ is composed of two types of nets, nets that have all terminals inside the subregion (Ti ? V ′), and nets that have at least one terminal outside the subregion (Ti 6? V ′). Figure 2(a) shows the latter type of these nets. The net in the figure belongs to three different subregions. The common boundaries of these subregions are shown in bold. Considering the top-right subregion, we can think of having a net with one fixed and two “floating” terminals. Each floating terminal represents a portion of a subregion boundary through which the net will connect to another subregion.

To specify such nets in our IP, we represent each float- ing terminal using an auxiliary node. The auxiliary node is added to the set of nodes V ′ in the grid-graph. Edges connecting the nodes that are on the subregion boundary to their corresponding auxiliary node are added to the set E′. The added edges have infinite capacity and zero cost in the definition of the integer program (ILP-GR). Figure 2(b) illustrates the addition of auxiliary nodes and edges. Af- ter applying this simple construction, the integer program (ILP-GR) is well-defined, and can be solved by the proce- dure outlined in Section 2.

The example of Figure 2 is for 2D routing, but in the gen- eral 3D case, each boundary of a subregion is a plane and graph G′ extends to the third dimension. The nodes on this vertical boundary plane are connected to their correspond- ing auxiliary node.
To detour long net segments outside a subregion, as required by step 3, we apply a shortest path algorithm on the grid- graph. We set the edge weights inside the target subregion to a large number to avoid getting re-routed inside that subre- gion. Also, outside the target subregion, the edges that have overflow will also have a large weight. The weights of the grid-graph gets updated every time a long net is detoured.

Grid Graphs
Xu, Yue and Chu, Chris: MGR Multi-Level Global Router Aug 2011 p6.
Yue Xu and Chris Chu
Department of Electrical and Computer Engineering
Iowa State University, Ames, Iowa 50011-3060, USA
fyuexu,cnchug@iastate.edu

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Abstract—Global routing faces an increasing problem size and urgent demand on improvement in solution quality. Despite of the recent developments of global routers, there exist only two types of choices: slow 3D routers with good solution quality or efficient 2D routers with relatively poor solution quality. We propose a multi-level 3D global router called MGR to fill the gap. MGR resorts to an efficient multi-level framework to reroute nets in the congested region on the 3D grid graph. Routing on the coarsened grid graph speeds up the global router while 3D routing introduces less vias. The powerful multi-level rerouting framework wraps three innovative routing techniques together: adaptive resource reservation in coarsening process, a new 3- terminal maze routing algorithm and network flow based solution propagation in uncoarsening process. As a result, MGR can achieve the solution quality close to 3D routers with comparable runtime of 2D routers.
It is natural to wonder whether we can make 2D routers to take a leap to generate solutions as good as 3D routers or whether it is possible to dramatically cut down 3D routers’ runtime to the level of 2D routers. The recent developments of 2D routers tend to disprove first attempt. Efforts to improve 2D maze routing by Liu et al. [6] or layer assignment by Lee et al. [8] only bring in marginal improvements. It seems that directly constructing routing solutions on multiple metal layers is indispensable for high quality global routers. To get the combination of short runtime and short wirelength, we propose a multi-level 3D global routing framework MGR to achieve high solution quality and keep runtime in check. MGR exploits 3D maze routing to explore a much larger solution space but formulates it on the coarsened grid graph to get small problem size.
We propose the first academic multi-level global router and name it MGR. MGR uses pattern routing and layer assignment to initiate a 3D solution. Then it uses a coarseninguncoarsening multi-level framework to reroute nets in the congested region. Rerouting on coarsened grid graph greatly speeds up MGR while 3D routing provides better solution quality by exploiting the entire 3D solution space. The two factors balance out and lead MGR to improve the performance and runtime of global routers. The key contributions of MGR include:

Fig. 1. Cell Structure and Grid Graph Views of the Multi-Level Framework
The rest of this paper is organized as follows. Section 2 introduces the global routing grid graph model and the flow of MGR. Section 3 details the key techniques used in MGR. The experimental results are provided in Section 4 and the paper concludes with Section 5.

A. Global Routing Grid Graph

In global routing, the die is partitioned into 3D global cells. Every cell is modeled as a node. On each metal layer, the boundary between two neighboring cells is given certain capacity to accommodate several cross-cell nets while intracell nets are ignored in global routing. Grid edges are created to model the capacity and usage on cell boundaries. The capacity ce of a grid edge is defined as the maximum number of nets that can use the grid edge. The usage ue is the actual number of nets that use the grid edge. Overflow oe is defined as max(ue ??ce; 0). All the grid edges together form the grid graph, as shown in the rightmost figure in Fig. 1(b).
For multi-level global routing, we need to create multi-level grid graphs. The original cell structure and grid graph with finest structure is denoted as level-1. The level increases as global cells in cell structure become larger and grid graph becomes coarser. We derive the level-2 cell structure from level-1 cell structure in the following manner. 4 neighboring cells are merged into one, as shown in Fig. 1(a) by grey areas. The top level is denoted as level-t. Level-i grid graph models the crossing on boundaries of level-i cell structure. For level- (i+1) grid graph, the four corresponding level-i grid nodes grouped in shadow are merged into a node as shown in Fig. 1(b). One level-(i+1) grid edge corresponds to two level-i grid edges. The hierarchy is built up until each layer in the top level grid graph becomes smaller than or equal to the size of 8-by-8. In the hierarchy, nets that exist on level-i grid graph but disappear in level-(i+1) grid graph are denoted as level-i nets. Level-i nets do not belong to level-(i-1) nets because they still exist on level-i. Grid graphs at all levels have the same number of metal layers as level-1 grid graph and coarsening on different layers is vertically synchronized to maintain regular 3D cell and grid graph structures.
In the rerouting stage, we use 3D routing to explore the entire solution space and adopt multi-level framework to speed up such exploration. MGR first coarsens the grid graph to build hierarchy. The goal of coarsening is to generate higher level grid graphs to reduce the problem size and calculate accurate routing resource estimation based on the initial solution on those grid graphs. We use adaptive resource reservation to adjust the capacities for high level grid edges, so that high level nets would not over utilize routing resources in congested region, which would reduce the need to rip-up and reroute high level routing solutions in low level grid graphs and thus effectively control run time and improve solution quality. After the coarsening stage, we achieve all levels of grid graphs and their routing resource estimations. MGR then uses 3D maze routing, including the newly proposed 3-terminal maze routing, to eliminate congestion on the level-t grid graph. Then MGR uses network flow based solution propagation to project routing of level-t nets onto level-(t-1) grid graph. For a level-t net, its routing solution can only use grid edges on level-(t-1) grid graph its level-t solution represents. In general, before propagating level-i solutions to level-(i-1), we use 3D maze routing to minimize congestion on level-i. Our newly proposed 3-terminal maze routing is adopted to enhance MGR’s congestion reduction capability. This rerouting and propagation iteration inner loops as shown in the right part of Fig. 2 works from level-t to level-2. At the end of this loop, we achieve a rerouted level-1 solution. If the overflow remains after multi-level rerouting, MGR uses 3D maze routing on level-1 grid graph to eliminate it.

III. MULTI-LEVEL GLOBAL REROUTING FRAMEWORK

A. Coarsening Process

The coarsening process generates smaller sized grid graphs for 3D maze routing. But it should not sacrifice routing quality with inaccurate estimations of routing resources on the coarsened grid graphs. MGR uses pattern routing and simple layer assignment to provide an initial solution so that the coarsening stage can calculate routing capability for higher level grid graphs based on the actual usage of lowest level grid graph. It differs from previous multi-level gridless routers in the way that previous works rely on inner cell routing blockage model to estimate boundary capacity.

In the coarsening process, we need to make sure that we do not render high level grid graphs with excessive capacity so that high level nets lack incentive to avoid congested region. Such situation will naturally happen if we simply add up the grid edge capacities of the two lower level grid edges corresponding to each higher level grid edge. A higher level grid edge represents larger layout boundary. The possibility of overflow on that boundary tends to diminish as the level goes higher, due to the fact that the demand will average out over a long boundary. The larger area a cell includes, the less likely demands on its boundary exceed the capacity. Just like ideal global routing would detour global nets from locally congested global cells, we want MGR to guide level-(i+1) nets to avoid congested edges on level-i. The most effective way to achieve this is through adaptively capacity adjustment for higher level edges. Without adjustment, the capacity of a level-(i+1) grid edge would be the sum of capacities of the two level-i grid edges it represents. This method has a major drawback. It ignores the congestion inside level-(i+1) cells and leads to much less detour than desirable amount. This stems from the nature of routing problem: If the boundary has ample routing resources while the cell is congested with intra-cell nets, routing on that boundary will aggravate intracell congestion. Thus, MGR adjusts the capacity of high level grid edges according to existing inner cell routing solution in an adaptive manner to guarantee that high level routing will not take up critical lower level routing resources for lower level nets.

Fig. 3. Coarsening Process in Grid Graph (graph would be changed)
Consider the coarsening step from level-i to level-(i+1), Fig. 3 shows a part of the grid graph that will go through the coarsening step. First, MGR contracts e1, e2, e3, and e4 into a level-i+1 grid graph node. For the node, MGR assigns a node adjustment value avn, which is oe1 + oe2 + oe3 + oe4, the sum of overflow of the level-i grid edges it includes. The node adjustment value represents the need to discourage higher level nets to use the node in order to resolve congestion on level-i. Nevertheless, routing on a grid graph with both edge and node constraints overly complicates the problem. So in the second phase, we convert the node adjustment value to edge capacity adjustment on the same level by distributing the node adjustment value to the capacity of grid edges connecting to the node. For the level-(i+1) edges that connect to n1, their capacities will each be reduced by a quarter of avn. If the node is at the corner of grid graph, the capacities of the two edges connecting to the node will be reduced by half of the node adjustment value. In this way, we propagate level-i overflow information into level-(i+1) grid graph.
Traditionally, sequential routers run as little maze routing as possible to save runtime. One advantage for MGR is that it has a relatively small problem on higher level grid graphs so it can afford running more maze routing. On higher levels, MGR picks up extra duty to balance out usage profile between large global cells to help eliminate lower level local congestions. To achieve that, MGR rips-up and reroutes every net using 3D maze routing for the top 2 levels to get better solutions. Running these extra maze routing improves high level solutions and consume little runtime due to small grid graphs and limited number of high level nets. On lower levels, MGR only use 3D maze routing to reroute congested nets, just like the behavior of traditional 2D sequential routers.

C. Routing Propagation to Lower Level

Once MGR reaches the top level and balances routing demands according to routing resources, it needs to propagate routing decisions made in the higher level to lower levels, in other words, from coarser grid graph to finer grid graphs.

Fig. 5. High Level Routing Propagation into Lower Level Grid Graph
The propagation for a single net is a relatively easy problem. As shown in Fig. 5, the higher level net just need to choose among the edges that is abstracted away during the corresponding coarsening process. Such propagation can easily be realized by dynamic programming. However, sequential net by net propagation ignores the impacts of one net onto its spatially correlated nets. The ideal solution with best results would be a simultaneous net propagation for all the high level nets. However, it has too big a problem size to finish in tight schedule, which is especially true for uncoarsening process for the few bottom levels. In the end, we come up with a balanced solution between solution quality and runtime concern. MGR propagates all the nets or part of the nets that use the same column or same row in the grid graph. We call each column or row a slice. In a grid graph, a slice is defined as the grid nodes on all metal layers of same row or column index together with all the grid edges among the nodes.
Without loss of generality, we pick a row on level-(i+1) for the following analysis. This row consists of 2 neighboring rows in level-i grid graph, together with all the vertical edges that connect them. This forms the backbone of one subproblem. In each subproblem, we use network flow algorithm to propagate routing solution on the row into the finer lower level grid structure. To save more via, we relax the problem by allowing each high level net to choose new routing layer instead of the metal layer decided in its high level solution. This relaxation helps MGR to correct any layer assignment mistakes made in the previous level. The uncoarsening problem is decomposed into network flow sub-problems on slices. The decomposition disentangles the complex uncoarsening problems but still concurrently considers the competitions among all the nets that use a single slice.
The formal problem formulation is defined as follows. We slice the entire column or row from the grid graph. On level-i, we have a single line with multiple layers while at level-(i- 1), we have 2 grid-edge lines together with a row of vertical grid edges that connects them. This slice of grids forms the backbone structure of the network flow problem. The grid graph edges are assigned a cost depending on the initial routing solutions and current routing solutions. The capacity and usage for the backbone is assigned in the following manner. Initially, the backbone has the capacity estimated during the coarsening process. Based on that, we add fixed usage that represents the propagated routing solution by level-i propagation subproblems finished earlier, if any. Furthermore, for each level-i nets not propagated yet but will use the vertical grid edges in the backbone, we add 0.5 usage on each of the two possible grid edges. For the network flow problem, we would compute the cost for each grid edge by a logistic function similar to [12] based on the capacity and usage calculated just above.

V. CONCLUSIONS

In this work, we propose a multi-level global router called MGR. MGR consists of uncoarsening process and coarsening process. In the uncoarsening process, MGR adaptively adjusts the capacities for high level grid graphs to effectively direct high-level nets from congested region. In the coarsening process, we propose a novel three-terminal maze routing and network flow based solution propagation. These two new techniques together guarantee better routing solutions. This multi-level solution can greatly speeds up global routing and provides better solutions comparing to existing academic global routers.

Grid Graphs
Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................15

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Since global routing usually has a very tight schedule to nish and does not need to
generate the detailed wiring geometries, it uses a simpli ed grid graph to represent the
entire layout and abstracts away all design rules.

During global routing, complex design rules are abstracted away and a design is
captured in a grid graph. As illustrated in Fig. 2.1, each layer of the entire routing region
is partitioned into rectangular regions called global cells, each of which is represented by
one node in the grid graph. The boundary on each metal layer between two global cells
is represented by one 3D grid edge in the grid graph on the speci c layer. The capacity
for a grid edge, i.e., ce, is de ned as the maximum number of wires that can cross the
grid edge. The usage, i.e., ue, is de ned as the actual number of wires crossing the grid
edge. The over
ow oe is de ned as max(ue ?? ce; 0). In the 3D model, a via is de ned
as a segment of wire that vertically connects one metal layer to a neighboring layer. 3D
capacity and usage represents the routing resources and usage on each metal layer. The
partitioning of metal layers into 3D global cells are synchronized so that cells on the
same planar positions are aligned in the up-down directions. Capacities and usage for
2D grid graph are similarly de ned as their 3D correspondents.

Wiring on the grid graph is greatly simpli ed. Only cross global cell connections are
considered in the global grid graph model. Nets with all the pins residing in a single
global cell are ignored in global routing process while multiple pins in the same global
cells belonging to a single net are replaced with a single pin inside the speci c global cell.
All design rules are abstracted into capacities and usage on the grid graph. Every net is
16
considered to have its pins located at the center of global cells. Thus,the wirelength is
discretized into the number of global cells boundaries each net will cross in routing.
Figure 2.1 Global cells and corresponding 3D global routing grid graph.

technique in coarsening stage to withhold routing resources form high level nets to get
better routing solutions. More importantly, MGR uses concurrent ILP to propagate high
level solutions to low level grid graphs. Such concurrency provides better solution than
sequentially assigning high level nets to low levels. The sequential method is essentially
equivalent to ordering long nets to short nets in ripup and reroute framework. The in-
troduced concurrency considers the competition between di erent nets when they tries
to use highly demanded wiring resources in congested region in the same time. As a re-
sults, MGR can generate solutions with quality much closer to GRIP only using runtime
comparable to traditional framework with 2D global router and layer assignment.

3D global routing grid graph

Routing Grid Graph Model for GLOBAL ROUTING

Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................

For global routing usually a simplifed grid graph is to represent the entire layout and to abstract away all design rules.During global routing, complex design rules are abstracted away and a design is captured in a grid graph. As illustrated in Fig., below

Figure Global cells and corresponding 3D global routing grid graph

each layer of the entire routing region (chip area) is partitioned into rectangular regions called global cells (or global bins and all the pins in a global bin are assumed to be at the center of the bin.), each of which is represented by one node in the grid graph. The boundary on each metal layer between two global cells (bins) is called global edge and is represented by one 3D grid edge in the grid graph on the specific layer. The capacity for a grid edge, i.e., ce, is defined as the maximum number of wires that can cross the grid edge. (The capacity of an edge represents the number of routing tracks for the corresponding boundary.) The usage, i.e., ue, is defined as the actual number of wires crossing the grid edge. The overflow oe is defined as max(ue - ce; 0).

Wiring on the grid graph is greatly simplified. Only cross global cell connections are considered in the global grid graph model. Nets with all the pins residing in a single global cell are ignored in global routing process while multiple pins in the same global cells belonging to a single net are replaced with a single pin inside the specific global cell. All design rules are abstracted into capacities and usage on the grid graph. Every net is considered to have its pins located at the center of global cells. Thus,the wirelength is discretized into the number of global cells boundaries each net will cross in routing.

Multi-Level Grid Graphs
Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................15

Coarsening Process in Grid Graph .
High Level Routing Propagation into Lower Level Grid Graph

The third work in this thesis combines the advantage of the two framework used to
minimize via usage in global routing: 3D routers with good solution quality and ecient
2D routers with layer assignment process. It results in a new multi-level 3D global router
called MGR (multi-level global router) that combines the advantage of both kinds. MGR
resorts to an ecient multi-level framework to reroute nets in the congested region on the
3D grid graph.

Routing on the coarsened grid graph speeds up the global router while
3D routing introduces less vias. The powerful multi-level rerouting framework wraps
three innovative routing techniques together: an adaptive resource reservation technique
in coarsening process, a new 3-terminal maze routing algorithm and a network
ow based
solution propagation method in uncoarsening process. As a result, MGR can achieve the
solution quality close to 3D routers with comparable runtime of 2D routers

directly constructing routing solutions on multiple metal layers is indispensable for high
quality global routers. To get the combination of short runtime and short wirelength, I
propose a multi-level 3D global routing framework MGR to achieve high solution quality
and keep runtime in check. MGR exploits 3D maze routing to explore a much larger
solution space but formulates it on the coarsened grid graph to get small problem size.

This is the rst academic multi-level global router and name it MGR. MGR uses
pattern routing and layer assignment to initiate a 3D solution. Then it uses a coarsening-
uncoarsening multi-level framework to reroute nets in the congested region. Rerouting on
coarsened grid graph greatly speeds up MGR while 3D routing provides better solution
quality by exploiting the entire 3D solution space. The two factors balance out and lead
14
MGR to improve the performance and runtime of global routers. The key contributions
of MGR include:

The rest of this paper is organized as follows. Section 2 introduces the global routing
grid graph model. Section 3 details the key techniques used in FastRoute 4.0. Section
3 gives a full description of how the underlying principle and techniques used in the
pre-processing detour global framework for global routing. Section 4 presents the algo-
rithms proposed and integrated to form an unique 3D hierarchical global router. The
experimental results are provided in Section 6 and this thesis concludes with Section 7.

Multi-Level Grid Graphs
For multi-level global routing, it is necessary to create multi-level grid graphs. The
original cell structure and grid graph with nest structure is denoted as level-1. The level
increases as global cells in cell structure become larger and grid graph becomes coarser.
MGR derives the level-2 cell structure from level-1 cell structure in the following manner.
4 neighboring cells are merged into one, as shown in Fig. 5.1(a) by gray areas. The top
level is denoted as level-t. Level-i grid graph models the crossing on boundaries of level-
i cell structure. For level-(i+1) grid graph, the four corresponding level-i grid nodes
grouped in shadow are merged into a node as shown in Fig. 5.1(b). One level-(i+1) grid
edge corresponds to two level-i grid edges. The hierarchy is built up until each layer
in the top level grid graph becomes smaller than or equal to the size of 8-by-8. In the
hierarchy, nets that exist on level-i grid graph but disappear in level-(i+1) grid graph are
denoted as level-i nets. Level-i nets do not belong to level-(i-1) nets because they still
exist on level-i. Grid graphs at all levels have the same number of metal layers as level-
1 grid graph and coarsening on di erent layers is vertically synchronized to maintain
regular 3D cell and grid graph structures.

In the rerouting stage, MGR uses 3D routing to explore the entire solution space and
adopt multi-level framework to speed up such exploration. MGR rst coarsens the grid
graph to build hierarchy. The goal of coarsening is to generate higher level grid graphs to
reduce the problem size and calculate accurate routing resource estimation based on the
initial solution on those grid graphs. It uses adaptive resource reservation to adjust the
capacities for high level grid edges, so that high level nets would not over utilize routing
resources in congested region, which would reduce the need to rip-up and reroute high
level routing solutions in low level grid graphs and thus e ectively control run time

and improve solution quality. After the coarsening stage, MGR achieves all levels of
grid graphs and their routing resource estimations. MGR then uses 3D maze routing,
including the newly proposed 3-terminal maze routing, to eliminate congestion on the
level-t grid graph. Then MGR uses network
ow based solution propagation to project
routing of level-t nets onto level-(t-1) grid graph. For a level-t net, its routing solution
can only use grid edges on level-(t-1) grid graph its level-t solution represents. In general,
before propagating level-i solutions to level-(i-1), MGR uses 3D maze routing to minimize
congestion on level-i. Our newly proposed 3-terminal maze routing is adopted to enhance
MGR's congestion reduction capability. This rerouting and propagation iteration inner
loops as shown in the right part of Fig. 5.2 works from level-t to level-2. At the end of
this loop, it achieves a rerouted level-1 solution. If the over
ow remains after multi-level
rerouting, MGR uses 3D maze routing on level-1 grid graph to eliminate it.

5.3 Multi-Level Global Rerouting Framework
5.3.1 Coarsening Process
The coarsening process generates smaller sized grid graphs for 3D maze routing. But
it should not sacri ce routing quality with inaccurate estimations of routing resources
on the coarsened grid graphs. MGR uses pattern routing and simple layer assignment to
provide an initial solution so that the coarsening stage can calculate routing capability
for higher level grid graphs based on the actual usage of lowest level grid graph. It di ers
from previous multi-level gridless routers in the way that previous works rely on inner
cell routing blockage model to estimate boundary capacity.
In the coarsening process, MGR needs to make sure that it does not render high
level grid graphs with excessive capacity so that high level nets lack incentive to avoid
congested region. Such situation will naturally happen if MGR simply adds up the grid
edge capacities of the two lower level grid edges corresponding to each higher level grid

according to existing inner cell routing solution in an adaptive manner to guarantee that
high level routing will not take up critical lower level routing resources for lower level
nets.
Figure 5.3 Coarsening Process in Grid Graph
Consider the coarsening step from level-i to level-(i+1), Fig. 5.3 shows a part of the
grid graph that will go through the coarsening step. First, MGR contracts e1, e2, e3, and
e4 into a level-i+1 grid graph node. For the node, MGR assigns a node adjustment value
avn, which is oe1+oe2+oe3+oe4, the sum of over
ow of the level-i grid edges it includes.

The node adjustment value represents the need to discourage higher level nets to use the
node in order to resolve congestion on level-i. Nevertheless, routing on a grid graph with
both edge and node constraints overly complicates the problem. So in the second phase,
MGR converts the node adjustment value to edge capacity adjustment on the same level
by distributing the node adjustment value to the capacity of grid edges connecting to the
node. For the level-(i+1) edges that connect to n1, their capacities will each be reduced
by a quarter of avn. If the node is at the corner of grid graph, the capacities of the two
edges connecting to the node will be reduced by half of the node adjustment value. In
this way, MGR propagates level-i over
ow information into level-(i+1) grid graph.

Traditionally, sequential routers run as little maze routing as possible to save runtime.
One advantage for MGR is that it has a relatively small problem on higher level grid graphs so it can a ord running more maze routing. On higher levels, MGR picks up extra
duty to balance out usage pro le between large global cells to help eliminate lower level
local congestions. To achieve that, MGR rips-up and reroutes every net using 3D maze
routing for the top 2 levels to get better solutions. Running these extra maze routing
improves high level solutions and consume little runtime due to small grid graphs and
limited number of high level nets. On lower levels, MGR only use 3D maze routing to
reroute congested nets, just like the behavior of traditional 2D sequential routers.

graphs so it can a ord running more maze routing. On higher levels, MGR picks up extra
duty to balance out usage pro le between large global cells to help eliminate lower level
local congestions. To achieve that, MGR rips-up and reroutes every net using 3D maze
routing for the top 2 levels to get better solutions. Running these extra maze routing
improves high level solutions and consume little runtime due to small grid graphs and
limited number of high level nets. On lower levels, MGR only use 3D maze routing to
reroute congested nets, just like the behavior of traditional 2D sequential routers.
5.3.3 Routing Propagation to Lower Level
Once MGR reaches the top level and balances routing demands according to routing
resources, it needs to propagate routing decisions made in the higher level to lower levels,
in other words, from coarser grid graph to ner grid graphs.

Once MGR reaches the top level and balances routing demands according to routing
resources, it needs to propagate routing decisions made in the higher level to lower levels,
in other words, from coarser grid graph to ner grid graphs.
Figure 5.5 High Level Routing Propagation into Lower Level Grid Graph
The propagation for a single net is a relatively easy problem. As shown in Fig.
5.5, the higher level net just need to choose among the edges that is abstracted away
during the corresponding coarsening process. Such propagation can easily be realized by
dynamic programming. However, sequential net by net propagation ignores the impacts
of one net onto its spatially correlated nets. The ideal solution with best results would
be a simultaneous net propagation for all the high level nets. However, it has too big a
problem size to nish in tight schedule, which is especially true for uncoarsening process
for the few bottom levels. In the end, MGR comes up with a balanced solution between

Via Grid Graphs
Xu, Yue: 3D Global Router a Study to Optimize Congestion, Wirelength and Via for Circuit Layout, (2012). Graduate Thesis and Dissertation, p87..................15
As shown in Fig. 3.6, FastRoute 4.0 creates a \via grid graph" to assign each edge
to metal layers. Each node on the graph is named as a \via node". Vertical edges
represent the possible places to add via while the horizontal edges are constructed from
the actual 2D path. FastRoute 4.0 pulls straight the original zigzagged 2-pin net to
form the horizontal edges in the via grid graph and copy the capacity and usage of
corresponding global edge from the edge grid graph. FastRoute 4.0 breaks the tree edge
into global grid edges and assign them to layers one by one. Such breakdown enables
us to keep the total number of wirelength and over
ow of the 2D solution unchanged.
Without loss of generality, it assume sources Si on the very left column and targets Tj
on the right. If it does not know the layer information about the ending node, layer
1 to L are all considered to be targets. Here, L is the layer numbers in a benchmark.
Otherwise, the target is set to be the spanning range of the ending node.

global grid graph

global grid graph

3D global routing grid graph

global routing grid graph

Multi-Level Grid Graphs

Multi-Level Grid Graphs

low level grid graphs

higher level grid graphs

small grid graphs

small grid graphs

coarser grid graph to ner grid graphs

coarsened grid graph

Via Grid Graph

via grid graph

Terminology

edge grid graph

Literature


Routing Graphs

Routing Graph = (Routing) Grid Graph

routing graph

3D routing graph
routing graph in 3d ic
routing graph in 3d circuits
routing graph in 3d integrated circuits
routing graph in three dimensional integrated circuits
routing graph in 3d VLSI
routing graph in three dimensional VLSI
routing sub-graph

Routing Graphs

routing graph
Graph Models for Global Routing Grid Graph Nov 2002 p17.

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Global-Routing Problem
 Given a netlist N=fN1;N2; : : : ;Nng, a routing graph G = (V;E), nd a
Steiner tree Ti for each net Ni, 1  i  n, such that U(ej)  c(ej), 8ej 2 E
and
Pn
i=1 L(Ti) is minimized,
where
{ c(ej): capacity of edge ej;
{ xij = 1 if ej is in Ti; xij = 0 otherwise;
{ U(ej) =
Pn
i=1 xij: # of wires that pass through the channel corresponding
to edge ej;
{ L(Ti): total wirelength of Steiner tree Ti.
 For high-performance, the maximum wirelength (maxni
=1 L(Ti)) is minimized
(or the longest path between two points in Ti is minimized).

The Routing-Tree Problem
 Problem: Given a set of pins of a net, interconnect the pins by a \routing
tree."

gate array standard cell building block
 Minimum Rectilinear Steiner Tree (MRST) Problem: Given n points
in the plane, nd a minimum-length tree of rectilinear edges which connects
the points.
 MRST(P) = MST(P [ S), where P and S are the sets of original points
and Steiner points, respectively.

???????????????????

routing graph
Boese High-Performance Routing Trees With Identi ed Critical Sinks p6

Boese High-Performance Routing Trees With Identi ed Critical Sinks p6

routing graph

Routing Trees

critical-sink routing tree

Elmore routing tree

Steiner tree

minimum Steiner tree

minimum-cost Steiner tree

minimum spanning tree

minimum-cost spanning tree (MST)

RC-tree

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

routing graph
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................

===================================================

Topology Optimization

When interconnect resistance becomes signi cant compared to the e ective resistance of the driver, the interconnect delay of a multi-terminal net becomes a function of the topology of the routing. One of the rst algorithms which attempted to optimize the topology for delay was presented in [34]. The algorithm iteratively constructs a tree for a multi-terminal net, by starting from a partially constructed tree (which is initially just the driver node), and connecting it to a sink node. The connection path is found using the \A" search algorithm, which is guided by a bene t value on each vertex in the routing graph based on estimates of the Elmore delay to all sinks in the tree, and the total wire length of the tree. An advantage of this algorithm is that it can be used on arbitrary routing graphs, so it can be used on channel graphs, or for area routing in the presence of obstacles. Many other performance-driven algorithms are restricted to the manhattan plane.
===================================================

The nal step in the physical design process is routing which usually consists of global rout- ing, layer assignment and detailed routing [42]. The global routing step assigns nets or wires to di erent routing regions. Whereas the router in the detailed routing step actually nds a geometric path for each net and routes the terminals connected by the net. The primary goal of the global routing step is to reduce the length of the global routing trees since this reduces the area and delay. On the other hand, the layer assignment problem, which is in itself an NP complete problem, is a step in the routing process where each net is assigned to an x-y layer pair subject to the feasibility of routing the nets on a grid. The layer assignment step is important as it determines the number of layers in an MCM and hence the cost and the cooling mechanism required.

===================================================

Another class of algorithms attempts to minimize Elmore delays directly during construction of the spanning tree for the net. The Elmore Routing Tree (ERT) and Steiner Elmore Routing Tree (SERT) algorithms [4] construct spanning and Steiner trees, respectively, using a greedy algorithm to minimize Elmore delay.

routing graph
Cho, Minsik et al: BoxRouter 2.0 Architecture and Implementation of a Hybrid and Robust Global Router 2007 IEEE p6....
Dept. of ECE, The University of Texas at Austin, Austin, TX 78712
{thyeros, yiotse, kyuan}@cerc.utexas.edu, dpan@ece.utexas.edu

Negotiation-based Routing
It is shown that negotiation-based routing is effective in
congestion elimination for FPGA [28]. The key idea of
negotiation-based approach is that the congestion history of
every edge in the routing graph will be considered for the
future routing. In detail, for each edge e, there are two cost
factors: hi(e) for historic cost at i-th iteration and p(e) for
the present congestion cost. The combination of these two
factors will provide the final cost for a wire to pass through
e. As hi(e) is increased for any congested edge e right after
each iteration, an edge which has been congested previously
tends to have high hi(e). Meanwhile, p(e) is solely related to
the present congestion of e. Thus, considering both hi(e) and
p(e) as routing cost will guide a router to avoid the presently
congested edges as well as previously congested edges. This is
very efficient technique to spread out wires to less congested
regions.

============================================

In fact, our 2D global routing can be applied for multiple
layers (3D) directly, but the advantage of 2D global routing
over 3D global routing is that it needs less computing power
and memory, as the global routing graph shrinks significantly.
Also, the mapping from 2D solution to 3D solution can be
done without making congestion worse, as long as a wire
can be splitted to avoid blockages at a cost of via and wire
width/spacing for every wire is fixed as a constant.

============================================

routing graph
Cong, Jason and Zhang, Yan: Thermal-Driven Multilevel Routing for 3-D ICs, Nov 2004, p6.
In this paper we assume a wafer bonding technology [1] and TS-vias of size 51m￡51m [18]. A set of °oorplan benchmarks is used to demonstrate our approach. However, the proposed routing algorithm can work for all three kinds of technologies if the routing layers and the device layer obstacles are properly modeled in the routing graph.

routing graph
Deng, Yangdong and Maly, Wojciech P.: 3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme, Tsinghua University Press, Beijing and Springer-Verlag Berlin Heidelberg 2010, p21 ....p190???.
Figure 4.2 2.5-D routing graph

routing graph
Fischbach, Robert; Lienig, Jens and Meister, Tilo: 3D Physical Design Challenges and Solutions p6............

routing graph

Hsu, Chin-Hsiung; Chen, Huang-Yu and Chang, Yao-Wen: Multilayer Global Routing With Via and Wire Capacity Considerations p12. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 5, MAY 2010
??????????????
In order to reduce the gap between global routing and detailed routing, we shall consider via usages and in-tile nets for our global routing congestion model. Besides, we observe that the popular DP based monotonic routing that has been successfully applied to the 2-D cases [13], [28] cannot be directly extended to the 3-D ones. The reason is that the 2-D routing graphs are directed acyclic when the routing paths are constrained to be monotonic, and thus finding a shortest path on a directed acyclic graph can be done in linear time. However, the 3-D routing graphs are not directed acyclic when the routing paths are constrained to be aerial-monotonic [A routing path is said to be aerial-monotonic if it does not contain any detour from the aerial (top) view.]. To remedy these deficiencies, we propose an efficient algorithm to find the optimal aerial-monotonic routing paths, and extend the algorithm to handle the detoured routing in only linear time. The major contributions of this paper are summarized as follows.

1) We develop a more effective congestion metric that
considers in-tile wires and residual via capacity for
global routing. This metric can prevent our router from
producing over congested global tiles that would complicate
subsequent detailed routing.
2) Two types of routing paths, the aerial-monotonic and
escaping-point routing paths, are introduced. The aerialmonotonic
routing extends the efficient 2-D monotonic
search to a 3-D routing graph, whereas the escapingpoint
routing allows reasonable detours to reduce the
congestion and overflow.
3) With our congestion metric, we develop a new global
router that features two novel routing algorithms for
congestion optimization, namely aerial monotonic routing
and multisource multisink escaping-point routing.
In a routing box of V nodes, in particular, the O(V)-
time escaping-point routing algorithm guarantees to find
the optimal solution and achieves the theoretical lowerbound
time complexity. Compared with the O(V lg V)-
time complexity of the multisource multisink maze
routing [28], our router can effectively find routing paths
in faster runtime.

4) Compared with the state-of-the-art global routers, the
experimental results show that our global router can
achieve better routing solutions with more reasonable
via distribution that can benefit and correctly guide
subsequent detailed routing.

Fig. 4. (a) Routing region contains 3× three global tiles. (b) Corresponding
3-D global routing graph with three layers of (a). Each tile is represented
by a global tile node, and the relationship between two tiles is modeled by
an edge. Note that each layer has a preferred horizontal or vertical routing
direction shown in this figure.

II. Problem Formulation

We partition the routing region into tiles (or called global cells) and model the routing region as a 2-D or 3-D routing graph composed of nodes and edges. The 2-D routing graph contains only a horizontal and a vertical layers, whereas the 3-D one has at least three layers. Fig. 4(b) illustrates a threelayer 3-D routing graph that models the routing region of Fig. 4(a). In the routing graph, the global tile node represents a tile, while the global edge (edge in short) models the relationship between adjacent tiles, e.g., the edge in the x or y-direction represents the boundary between adjacent tiles in the same layer, and the edge in the z-direction models the layer transition between tiles lying in the adjacent layers. Each horizontal/vertical edge is associated with a capacity to model the limited routing resources such as the number of available detailed routing tracks on the tile boundary. The main objective of global routing is to minimize the total overflow, which is calculated by the total amount of routing demand that exceeds the capacity for each edge, and/or the maximum edge overflow. To address the via-capacity issue, we associate a dynamic via capacity with each global node. Note that a via capacity is not associated with an edge connecting different layer tiles because resources on metal layers are much more critical than that on via layers. We estimate the dynamic via capacity by the area of the corresponding tile because wires and vias are geometrical rectangles in the layout. For stacked via consideration, we not only integrate layer assignment into global routing, but also constrain the in-tile stacked via count. Consequently, we define the via capacity of a tile t as

where at , ao, ai, vw, and vs denote the area of the tile t, the total area of the obstacles in t, the area of in-tile nets in t, the via width, and via spacing, respectively. Here, aw represents the probabilistic area of wires passing through the tile boundary, and the probabilistic length of a passing wire is averagely the half of the tile width (based on uniform distribution). Therefore, aw is defined as

where lt , μw, and μs denote the length of the tile t, the wire width, and wire spacing, respectively. μ ∈ B refers to a wire crossing through the boundary B of the tile t. By this model, the via resource of a global routing tile t depends on the usage of wires but does not affect the wire capacity of t. As illustrated in Fig. 5

Fig. 5. Example illustrating the calculation of via capacity.

A more practical 3-D global routing problem that considers the aforementioned two issues by estimating the area of the layout and routing on a 3-D routing graph is defined as follows.

The 3-D Routing Problem: Given a netlist, widths and spacings of vias and wires, and wire capacities, find 3-D routing paths connecting pins of each net such that the total number of wire and via overflow, and the total wirelength are minimized. Note that we minimize the total number of wire and via overflow first to make fair comparisons with the recent works. Alternatively, we may minimize the maximum wire and via overflow in a tile first, which is arguably a more suitable objective for global routing.
==================================

We propose efficient 3-D routing algorithms to find the corresponding optimal routing paths for the aerial-monotonic routing and the escaping-point routing.

1) Multisource Multisink Aerial-Monotonic Routing (MSAMR): We first develop an aerial-monotonic routing (AMR) algorithm to find an optimal 3-D aerial-monotonic routing path and then extend it to a 3-D MSAMR algorithm without sacrificing the optimality. Note that the 3-D routing graph is not directed acyclic when the routing paths are constrained to be 3-D aerial-monotonic. The z-direction global edge connecting two global tiles on two layers can be upward and downward, and thus cycles may be introduced in the 3-D routing graph. For example, Fig. 9(a) illustrates a routing graph for 2-D monotonic routing, and this graph is directed acyclic; Fig. 9(b) illustrates a routing graph for 3-D aerialmonotonic routing, and this graph is not directed acyclic. As a result, existing linear-time algorithms that find the shortest path on a directed acyclic graph is not applicable to this case, and it is thus desirable to develop an efficient algorithm for this problem.

Fig. 9. Difference between the routing graphs for 2-D monotonic routing and 3-D aerial-monotonic routing. (a) Routing graph for 2-D monotonic routing, which contains no cycle. (b) Routing graph for 3-D aerial-monotonic routing, which contains cycles.
The AMR algorithm iteratively performs the two-phase operations of the pile update and pile propagation, where a pile represents a set of global tile nodes in the z-direction of a global routing graph. Pile update is an inter-layer (zdirection) cost propagation within a pile, and pile propagation is an intra-layer (x and y-directions) cost propagation among piles. From an aerial view, the pile propagation behaves like the propagation of 2-D monotonic routing, propagating the cost of the nodes in a pile ρ to the nodes of ρ’s adjacent piles. Fig. 10 summarizes the AMR algorithm. Without loss of generality, we assume that s is at the lower-left corner of the bounding box and t is at the upper-right corner. In lines 1–4, the algorithm performs initialization, which sets the costs of nodes as infinity so that the costs can be updated during propagation; in lines 5–8, it iteratively performs the pile update and pile propagation (to be explained later). Finally, the algorithm traces back from t to s and returns an optimal aerial-monotonic routing path. Note that the total number of aerial-monotonic routing paths from the lower-left corner to the upper-right corner of an m×n×L grids is Cm?1 m+n?2 ·Lm+n?2.

The main difference from 2-D monotonic routing is that the AMR algorithm requires each pile ρ to conduct the pile update which updates the cost of the nodes in ρ upward followed by downward directions before applying the pile propagation on ρ. With the pile update, the AMR algorithm can guarantee to find an optimal 3-D aerial-monotonic routing path. Fig. 11 illustrates the AMR algorithm on a three-layer 3-D routing graph. Fig. 11(a) shows the pile propagation from the piles ρ1 and ρ2 to the pile ρ, and Fig. 11(b) depicts the upward and downward pile updates of ρ before it continues to propagate to adjacent piles ρ3 and ρ4, as shown in Fig. 11(c). Note that the dynamic via capacity can be addressed during the upward and downward pile updates. If any via overflow occurs, the cost of the node is increased by a via-overflow penalty. Note also that we can use the coloring method to avoid unnecessary downward updating and thus speed up the runtime, as shown in Fig. 12. In lines 1–7, the algorithm propagates to upper layers, and in lines 8–16, it propagates to lower layers. Initially, the edges are colored as blue (line 4). During the upward propagation, once an edge is updated by a smaller cost, the edge is colored as red (line 6) to avoid redundant propagation during the downward propagation. During the downward propagation, we check whether the color of an edge is blue (line 11) to avoid redundant propagations during back tracking. Note that the reason why we update the cost upward followed by downward is that nets start and end on the lowest layer—a net should connect contacts with metal wires, and contacts are located on a layer lower than all metal layers.

routing graph

Hsu, Chin-Hsiung; Chen, Huang-Yu and Chang, Yao-Wen: Multi-layer Global Routing Considering Via and Wire Capacities July 2008 p6........

""""""""""""""""""""""""""""""????????????????????????????

In order to reduce the gap between global routing and detailed routing, we shall consider via usages and in-tile nets for our global routing congestion model. Besides, we observe that the popular dynamic-programming (DP) based monotonic routing that has been successfully applied to the 2D cases [7], [15] cannot be directly extended to the 3D ones. The reason is that the 2D routing graphs are directed acyclic when the routing paths are constrained to be monotonic, and thus finding a shortest path on a directed acyclic graph can be done in linear time. However, the 3D routing graphs are not directed acyclic when the routing paths are constrained to be aerial-monotonic. (A routing path is said to be aerial-monotonic if it does not contain any detour from the aerial (top) view.) To remedy these deficiencies, we propose an efficient algorithm to find the optimal aerial-monotonic routing paths, and extend the algorithm to handle the detoured routing in only linear time. The major contributions of this paper are summarized as follows:

that considers
in-tile wires and residual via capacity for global routing. This
metric can prevent our router from producing over congested
global tiles that would complicate subsequent detailed routing.
? Two types of routing paths, the aerial-monotonic and escapingpoint
routing paths, are introduced. The aerial-monotonic routing
extends the efficient 2D monotonic search to a 3D routing
graph, whereas the escaping-point routing allows reasonable
detours to reduce the congestion and overflow. The escapingpoint
routing can explore more paths than the A*-search routing
to reduce the overflow and has lower time complexity than the
maze routing while preserving the solution optimality.
? With our congestion metric, we develop a new global router
that features two novel routing algorithms for congestion
optimization, namely least-flexibility-first routing and multisource
multi-sink escaping-point routing. In a routing box of
V nodes, in particular, the O(V )-time escaping-point routing
algorithm guarantees to find the optimal solution and achieves
the theoretical lower-bound time complexity. Compared with
the O(V lg V )-time complexity of the multi-source multi-sink
maze routing [15], our router can effectively find better routing
paths in faster runtime.
? Compared with the state-of-the-art global routers, the experimental
results show that our global router can achieve better
routing solutions with more reasonable via distribution that can
benefit and correctly guide subsequent detailed routing. Further,
ours is much more efficient than these global routers.

=============================================

PROBLEM FORMULATION
For global routing, the routing region is partitioned into tiles (or
called global cells) and a 2D or 3D routing graph composed of nodes
(called global tile nodes) and edges (called global edges) models
the routing region, where the global tile node represents a tile, and
the global edge models the relationship between adjacent tiles. Each
global edge is associated with a capacity to model the limited routing
resource such as the number of available detailed routing tracks on the
tile boundary or the maximum allowable via count between adjacent
layers. The main objective of global routing is to minimize the total
overflow, which is calculated by the total amount of routing demand
that exceeds the capacity for each edge, and/or the maximum edge
overflow.

=============================================

A more practical 3D global routing problem that considers the
aforementioned two issues by estimating the area of the layout and
routing on a 3D routing graph is defined as follows:
? The 3D Routing Problem: Given a netlist, widths and spacings
of vias and wires, and wire capacities, find 3D routing paths
connecting pins of each net such that the total number of wire
and via overflow, and the total wirelength are minimized.
Note that we minimize the total number of wire and via overflow
first to make fair comparisons with the recent works. Alternatively,
we may minimize the maximum wire and via overflow in a tile first,
which is arguably a more suitable objective for global routing.

=============================================

We propose efficient 3D routing algorithms to find the corresponding
optimal routing paths for the aerial-monotonic routing and the
escaping-point routing.
1) Multi-Source Multi-Sink Aerial-Monotonic Routing
(MSAMR): We first develop an aerial-monotonic routing (AMR)
algorithm to find an optimal 3D aerial-monotonic routing path and
then extend it to a multi-source multi-sink 3D aerial-monotonic
routing (MSAMR) algorithm without sacrificing the optimality. Note
that the 3D routing graph is not directed acyclic when the routing
paths are constrained to be 3D aerial-monotonic. The z-direction
global edge connecting two global tiles on two layers can be upward
and downward, and thus cycles may be introduced in the 3D routing
graph. As a result, existing linear-time algorithms that find the
shortest path on a directed acyclic graph is not applicable to this
case, and it is thus desirable to develop an efficient algorithm for
this problem.

=============================================

The AMR algorithm iteratively performs the two-phase operations
of the pile update and pile propagation, where a pile represents a
set of global tile nodes in the z-direction of a global routing graph.
From an aerial view, the pile propagation behaves like the propagation
of 2D monotonic routing, propagating the cost of the nodes in a
pile ρ to the nodes of ρ’s adjacent piles. The main difference from
2D monotonic routing is that the AMR algorithm requires each pile
ρ to conduct the pile update which updates the cost of the nodes
in ρ upward followed by downward directions before applying the
pile propagation on ρ. With the pile update, the AMR algorithm
can guarantee to find an optimal 3D aerial-monotonic routing path.
Fig. 6 illustrates the AMR algorithm on a three-layer 3D routing
graph. Fig. 6 (a) shows the pile propagation from the piles ρ1 and ρ2
to the pile ρ, and Fig. 6 (b) depicts the upward and downward pile
updates of ρ before it continues to propagate to adjacent piles ρ3 and
ρ4, as shown in Fig. 6 (c). Note that the dynamic via capacity can be
addressed during the upward and downward pile updates. Note also
that we can use the coloring method to avoid unnecessary downward
updating and thus speed up the runtime.

=============================================

Algorithm: TAMR(G, s, t, ext, L)
Input : G - a 3D routing graph;
s, t - 3D coordinates of source and target points;
ext - the extending value of the bounding box;
L - number of layers.
Output : Popt - an optimal escaping-point routing routing path.
begin
1 B ← the extended searching box by ext;
2 for g ∈ B
3 d(g)←∞; π(g) ← null;
4 gs ← G(s); d(gs) ← 0; π(gs) ← null;
5 for each direction δ ∈ {top-right, top-left, bottom-right, bottom-left}
6 pa ← s and decide pb by B in δ direction;
7 Aerial-Monotonic Routing (G, pa, pb, L);
8 Gs ← G;
9 for g ∈ B
10 d(g)←∞; π(g) ← null;
11 gt ← G(t); d(gt) ← 0; π(gt) ← null;
12 for each direction δ ∈ {top-right, top-left, bottom-right, bottom-left}
13 pa ← t and decide pb in δ direction
14 Aerial-Monotonic Routing (G, pa, pb, L);
15 Gt ← G;
16 find vst ∈ B such that d(Gs(vst)) + d(Gt(vst)) is minimum;
17 Ps ← back track from vst on Gs;
18 Pt ← back track from vst on Gt;
19 Popt ← combination of Ps and Pt;
end
Fig. 9. The two-phase aerial-monotonic routing (TAMR) algorithm.

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routing graph / extended routing graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.......................
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Depending on the design style, different forms of routing graphs are constructed to define the coarse regions for global routing. For gate array, sea of gates and standard cell designs, the entire routing area is typically tessellated into a grid array, as shown in Figure 1. Note that the horizontal grid line usually goes through the middle of a row of cells in the standard cell design. The dual graph of this tessellation is the routing graph G = (V,E), as shown in Figure 2(a). Each vertex v ∈ V represents a grid cell and each edge e ∈ E corresponds a boundary between two adjacent grid cells. In custom design, on the other hand, the cell placement is not regular as in gate array or standard cell design styles. Therefore, the routing graph is more appropriately based on the floorplan of the building blocks. This is illustrated for an example floorplan in Figure 3 where each rectangle represents a building block. Like the routing graph for gate array and standard cell designs, this routing graph is also a dual to the floorplan graph.

The global routing problem requires a set of nets N = {N1,N2, ...,Nk} to be routed over the routing graph G. A net Ni, 1 ≤ i ≤ k is a set of pins (or terminals) {vi,0, vi,1, vi,2, ...} ? V , among which vi,0 is the source pin and the others are sink pins. Under the coarse assumptions made for global routing, each pin is often assumed to lie at the center of the grid cell that contains the pin. The routing problem for a net Ni is to find an additional subset of vertices Vi,Steiner ? V and a set of edges Ei = {ei,1, ei,2, ...} ? E to form a rectilinear minimum spanning tree Ti = (Vi,Ei), where Vi = Ni ∪ Vi,Steiner.

As multiple nets are routed over the routing graph G, a common boundary between two neighboring grid cells may be crossed by wires belonging to different nets. In terms of the graph representation, this implies that the routing trees for these nets utilize a common edge e ∈ E. The number of wires that utilize an edge e ∈ E is called the flow (or demand), f(e), on the edge. The number of available routing tracks, which forms an upper bound on the allowable demand, is referred to as the boundary capacity (or supply), u(e). The ratio of flow to capacity f(e)/u(e) for an edge is referred to as the density or congestion, λ(e). If f(e) > u(e), then the overflow on the edge is defined as φ(e) = f(e)?u(e); otherwise the overflow is zero. The most fundamental statement of the global routing problem is to route all of the nets to ensure that for each edge e corresponding to a cell boundary, the number of wires across it does not exceed its routing capacity, i.e., φ(e) = 0, ?e ∈ E.

Another important consideration in routing global nets is to manage the number of vias on the net, and it is relatively easy to modify the above formulation to address this objective. Let us consider the routing problem under the reserved layer model, where the routing direction for all wires in a layer is identical. If a routing path makes a change in direction, i.e., a bend is induced, then a layer change is necessitated, and wires along different directions must be connected through a via at the bend position. For several reasons, such as considerations of reliability, area, and signal delay and quality, it is desirable to minimize or control the number of vias during routing. One way to do so is to limit the number of allowable vias in each grid cell. Under this scenario, the available via spaces in a grid cell may also be modeled by an edge, and we can obtain a routing graph G of the type shown in Figure 2(b) for a two-layer routing problem. This routing graph is identical to that defined earlier, except for the introduction of via edges along the grid. For a via edge e, we define f(e) as the number of vias utilized in the corresponding grid cell and u(e) as the number of available via spaces in the cell. In the literature, some works explicitly consider this via constraint while others do not, but these can often be extended fairly easily to do so.

routing graph
Lim, S.K.: Design for High Performance, Low Power, and Reliable 3D Integrated Circuits, Chapter 2 Steiner Routing for 3D IC, p34 Springer Science+Business Media New York 2013
Steiner routing
Note that the authors of [4] and [17] insert additional dummy TSVs for thermal
optimization. On the other hand, our thermal optimization is based on relocating
existing TSVs while maintaining the original routing topology. Thus, our thermal
optimization does not require valuable routing resource nor rip-up-and-reroute. In
addition, our routing trees are built under performance and thermal constraints.2

Figure 2.2 shows an overview of our performance and thermal-aware 3D Steiner
routing process. Given a netlist and its 3D placement, we first perform thermal
analysis to obtain the thermal distribution to be used during tree construction. Next,
we construct a performance-oriented routing tree for each net one by one under
the non-uniform thermal profile. The temperature values are updated periodically to reflect the thermal resistance and temperature changes from TSV usage.5 In our
tree refinement phase, we first perform timing analysis and obtain timing slack
for each pin. We also perform thermal analysis to identify thermal hotspots. We
then minimize the 3D on-chip temperature by relocating TSVs used in each tree
under the given timing constraints. The goal is to move TSVs closer to the hotspots
so that the thermal resistance values are reduced in those regions. Note that our
TSV relocation preserves the original tree topology while optimizing the thermal
objective. We recompute the timing slacks and temperature values to reflect the
relocation at every iteration. Lastly, we repeat the whole tree refinement phase until
no more thermal improvement is possible.

Fig. 2.2 Overview of our
performance and
thermal-aware 3D Steiner
routing

==============================================

Algorithm: 3D Steiner Tree Construction
input : netlist NL, routing graph G, thermal profile Z
output: 3D Steiner tree for each net
for each net n ∈ NL do
Tn = p0(n);
Qn = set of pins of n except p0;
while Qn = /0 do
for each pin a ∈ Qn do
for each edge e ∈ Tn do
x = connection point for a→e;
y = TSV location on e(x,a);
update dly(p) for all p ∈ Tn ∪a;
X(a,e) = max{dly(p)};
end
end
(amin,emin) = pin+edge pair with min X;
Tn = Tn ∪emin;
remove amin from Qn;
end
update Z periodically;
end
for each non-timing critical Tn violating capacity do
rip-up-and-reroute Tn under Z;
end
Algorithm 3: Pseudocode of performance and thermal-aware 3D Steiner tree
construction algorithm. In case e and a are located in different planes, e(r,a)
will utilize TSVs

===============================================
K. Boese, A. Kahng, B. McCoyy, G. Robins, Near-optimal critical sink routing tree constructions, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(12), 1417–1436 (1995)

routing graph
Lin, Mingjie and El Gamal, Abbas: A Routing fabric for monolithically stacked 3D-FPGAs p10.... FPGA’07, February 18–20, 2007, Monterey, California, USA.
Department of Electrical Engineering
Stanford University, CA 94305
f mingjie, abbas g@stanford.edu

?????????????????????

A previous study on the bene ts of monolithically stacked 3D-FPGA has estimated a 3.2x improvement in logic den- sity, a 1.7x improvement in delay, and a 1.7x improvement in dynamic power consumption over a baseline 2D-FPGA with no change in architecture. This paper describes a new routing fabric and shows that a 3D-FPGA using this fabric can achieve a 3.3x improvement in logic density, a 2.35x improvement in delay, and a 2.82x improvement in dynamic power consumption over the same baseline 2D- FPGA. The additional improvements in delay and power consumption are achieved by reducing net loading in several ways: (i) Only Single and Double interconnect segments are used. This reduces the total interconnect length used to implement each net. (ii) The routing fabric is hierarchical. Each logic block's inputs and outputs connect rst to lo- cal segments. These segments can be then programmably connected to local segments in neighboring routing blocks via programmable bu ers and/or to interconnect segments in routing channels via muxes with bu ered outputs. (iii) Interconnect segments can be directly connected to form longer segments using programmable bu ers without going through routing blocks. (iv) The routing block provides switching capability beyond that of a conventional switch box. A 3D-FPGA using this new routing fabric can be re- alized by stacking two con guration memory layers and a switch layer on top of a standard CMOS layer with a total of 12 metal layers interspersed between them. A CAD ow based on VPR with appropriate modi cations to the rout- ing graph generation and routing algorithm is developed and used in the performance analysis.

=============================================

To evaluate the performance of the new 3D-FPGA, we assume the same logic block as in the baseline 2D-FPGA and use a CAD ow based on VPR with some modi cations to the routing graph generation and routing algorithm. Results based on the 20 largest MCNC benchmark circuits show an average improvement of 3.3x in logic density, 2.35x in critical path delay, 2.57x in the geometric average pin-to-pin delay, and 2.82x in dynamic power consumption over the baseline 2D-FPGA. This provides further credence to the estimates in [3] and shows that additional improvements in delay and power consumption can be achieved by optimizing the 3D- FPGA architecture.

=============================================

Figure 10-(a) shows an example routing graph for a rout- ing block with W = 3 and d = 3. Each routing block in- put and output is represented by a node (so there are 2W nodes on each side). Solid edges correspond to direct con- nections while dashed edges correspond to extended con- nections. Figure 10-(b) shows how an extended connection from input node n1 to output node n2 is implemented using direct connections. The example corresponds to Figure 8.

Figure 8: (a) Extended routing capability of routing
block. (b) Example of an extended signal connec-
tion.

Figure 10: (a) Routing graph for routing block with
W = 3 and d = 3. (b) Extended connection between
n1 and n2.

==============================================

The main di erence between our router and VPR is that
we keep track of visited nodes during the breadth- rst-search
to improve the run time. This is described in lines 11, 12,
and 22. The need for this modi cation is that our routing
architecture results in many local cycles in the routing graph
due to the extended switching capability explained earlier.

===============================================

Algorithm 1 Congestion/Delay Routing Algorithm
1: Aij 1 for each signal net i and each sink j
2: while shared routing nodes exist do
3: for all nets i do
4: rip up routing tree RTi
5: initialize the queue PQ
6: for all sinks tij do
7: enqueue each node n in RTi at costs Aijdn to PQ
8: while tij is not found do
9: dequeue node m with the lowest cost from PQ
10: for all fanout node n of m do
11: if node n is unseen then
12: mark node n as seen
13: enqueue n to PQ with the cost of Aijdn+
(1 ?? Aij)dnpn
14: end if
15: end for
16: for all node n in the routed path tij to sj do
17: update the cost of node n
18: add n to RTi
19: end for
20: end while
21: end for
22: mark all nodes in PQ as unseen
23: update Aij for net i
24: end for
25: end while
0.00

routing graph
Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8

EXPERIMENTAL RESULTS

We implemented our algorithm GROUTE in C++/STL and ran experiments on a Dell Dimension 8800 Linux box. Our test cases are generated using our multi-layer SOP floorplanner on GSRC benchmark circuits [9]. The number of layer is fixed to four. Our layer usage results are based on the tile density w=10. The RSA/G-based global routing trees are generated based on 10×10 unless otherwise specified. We ran our algorithms for channel assignment and pin assignment on GSRC benchmarks and measured its solution quality as the values obtained for the various objectives. For our initial experiments, we have not taken the I/O layer into consideration. All the benchmarks completed in less than a few minutes. So we do not explicitly report the runtimes.

routing graph
Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8........................

After routing the net through the optical waveguides, it is desirable for the electrical part of the net not to go through these optical regions,thereby reducing overall electrical routing congestion. The electrical routes are ripped and rerouted using weights on the routing graph. The net is converted back to electrical if the delay exceeds the budget.

==============================================

The nodes in the routing graph corresponding to the waveguides are deleted, ensuring that the net subtrees do not use them, thereby reducing overall electrical routing congestion. However, if the worst delay for the net deteriorates beyond the performance budget after optical rerouting, the net is converted back to electrical.

==============================================

Rectilinear Steiner arborescence creates a routing tree with minimum source to sink distances for all sinks, and the weight of the tree is also minimum. It was shown that constructing minimal rectilinear Steiner arborescence is NP-complete [13]. We modify the RSA/G heuristic [11] to consider congestion-driven weights during the arborescence construction for simultaneous performance and congestion consideration. Our algorithm starts by constructing the weighted shortest path subgraph for a given net to be rerouted by finding out all shortest paths from the source to sink in . The weight is based on the current usage of the routing resource graph. The nodes in the subgraph are ranked according to the weighted distance from the source node (higher distance translates to higher ranks). The heuristic constructs the topology by considering the nodes in descending order of their ranks and merging them iteratively to form Steiner nodes. During the tree construction we do not allow merging at the routing nodes that are occupied by the existing waveguides.

routing graph / routing resource graph
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

routing graph / routing sub-graph

Panth, Shreepad et al: Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs p8. ISPD’14, March 30–April 2, 2014, Petaluma, CA, USA.

Panth Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs p34

?School of ECE, Georgia Institute of Technology, Atlanta, GA
§Qualcomm Research, San Diego, CA
{spanth,limsk}@ece.gatech.edu

Panth Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs p34

routing sub-graph

Rectilinear Steiner Minimal Tree

Monolithic 3D-IC Routing Demand Model
We maintain a 3D routing graph for the entire chip, and the demands
of each net are added into it. The supply on each edge is
computed from the technology LEF files depending on the number
of metal layers. This section is divided into two parts: The
first part discusses the decomposition of multi-pin nets into twopin
nets by constructing 3D Rectilinear Steiner Tress (RST), and
the second part discusses adding the demands of each two-pin net
into the routing graph.

==========================================

3D Demand Model for Two-Pin Nets
As mentioned earlier, we maintain a 3D routing graph for the
entire chip. This section assumes that we are looking only at that
sub-graph that a given two-pin net spans. We choose a probabilistic
demand model because: (1) It is very fast, and (2) The predicted demand
numbers are independent of net-ordering. The second property
is essential for a partitioner, as each re-compute of the demand of the same two-pin net must yield the same result. Note that our
model is general and applicable to any number of tiers, even though
this paper uses only the two-tier version.

============================================

Our heuristic is shown in Algorithm 1, with the top-level function
being MinOverflow(). Initially, the demand estimate is
cleared i.e, all nets are removed, and the utilization on each routing
edge is set to 0. Next, there are two stages, build and refine, both
of which are similar, and handled by the Stage() function. In the
build phase, all the nets are initially set to invalid. In both stages,
the nets are then sorted by bounding-box. This is because nets with
a larger bounding box have a greater impact on the routing graph,
and will be processed first. During the build phase, the 3D-RST
of the net currently being processed is added into the demand estimate,
and the net is set to valid. Next, irrespective of stage, the
FM() function (to be described later) is performed on the cells of
the current net. Note that in the build phase, the demand estimate
does not have all the nets included, only the ones that have been
processed so far. This is to avoid any noise introduced by a bad
initial random partitioning of the unprocessed nets.

==========================================

routing graph
Pathak, Mohit and Lim, Sung Kyu: Thermal-aware Steiner Routing for 3D Stacked ICs p7 2007 IEEE

The goal of our 3D Steiner routing is to address the
following two important design objectives: performance and
thermal. We tackle this problem in two steps:
1) Construction step: we first perform thermal analysis
from the given 3D placement. We then construct a
performance-oriented routing tree for each net under
the non-uniform thermal profile. We recompute the
temperature values to reflect the routing.
2) Refinement step: We optimize the thermal objective
by relocating through vias in each tree under given
timing constraints. Note that the through via relocation
preserves the original tree topology while optimizing the
thermal objective. We recompute the timing slacks and
temperature values to reflect the relocation. We repeat
this step until no more thermal improvement is possible.

===============================================

Thermal-aware 3D Steiner Routing Algorithm
input: netlist NL, routing graph R, thermal profile Z
output: 3D Steiner tree for each net
1. for (each net n ∈ NL)
2. Tn = p0(n);
3. Qn = set of pins of n except p0;
4. while (Qn = ?)
5. for (each pin a ∈ Qn)
6. for (each edge e ∈ Tn)
7. x = connection point for a → e;
8. y = through via location on e(x, a);
9. update d(p) for all p ∈ Tn;
10. X(a, e) = max{d(p)|p ∈ Tn ∪ a};
11. (amin, emin) = pin+edge pair with min X;
12. Tn = Tn ∪ emin;
13. remove amin from Qn;
14. for (each non-timing critical Tn violating capacity)
15. rip-up-and-reroute Tn under Z;
Fig. 1. Pseudocode of thermal-aware 3D Steiner routing algorithm. In case
e and a are located in different planes, e(r, a) will contain a through via.

===============================

Overview of the Approach
The goal of our 3D Steiner routing is to address the
following two important design objectives: performance and
thermal. We tackle this problem in two steps:
1) Construction step: we first perform thermal analysis
from the given 3D placement. We then construct a
performance-oriented routing tree for each net under
the non-uniform thermal profile. We recompute the
temperature values to reflect the routing.
2) Refinement step: We optimize the thermal objective
by relocating through vias in each tree under given
timing constraints. Note that the through via relocation
preserves the original tree topology while optimizing the
thermal objective. We recompute the timing slacks and
temperature values to reflect the relocation. We repeat
this step until no more thermal improvement is possible.

Routing Graph
Vygen, Jens: Faster Resource Sharing and Global Routing in Theory and Practice Nov 2011 p88.

Global routing: classical problem formulation
Instance:
I a global routing (grid) graph with edge capacities
I a set of nets, each consisting of a set of vertices (terminals)
Task: find a Steiner tree for each net such that
I the edge capacities are respected,
I and (weighted) netlength is minimum.

=====================================

Resources
Define resources for
I each edge of the global routing graph
I the total power consumption
I the critical area
Three ways to model timing constraints: based on
I the nets (the delay on each critical net is a resource; requires
delay budgeting)
I paths (the delay of each critical path is a resource)
I the timing graph (work in progress)

=============================================

More general: application to global routing
Given a global routing graph (3D grid with millions of vertices).
I Customers = nets (sets of pins; roughly: sets of vertices)
I Resources = edge capacities, power consumption, wiring
yield loss, timing constraints, ...
I Objective function is viewed as an additional resource
I Block = (convex hull of) set of Steiner trees for a net, with
space consumption for each edge
I Resource consumption is a nonlinear but convex function for
wiring yield loss, timing, power consumption
I Block solver = approximation algorithm for the Steiner tree
problem in the global routing graph (with edge weights)

=============================================

=============================================

=============================================

=============================================

=============================================

=============================================

routing graph

Three-dimensional Integrated Circuits Design, EDA and Architecture
Xie, Yuan et al: Three-dimensional Integrated Circuits Design, EDA and Architecture June 2011 p156...........

Computer Science and Engineering Department, University Park, PA16802, USA

yuanxie@cse.psu.edu

http://www.cse.psu.edu/~yuanxie/
We modify VPR/TPR so that they recognize the cluster structure in Virtex-4 FPGAs and generate the correct routing graph.
(1) We modify VPR/TPR so that they recognize the cluster structure in Virtex-4 FPGAs and generate the correct rout-ing graph.
(2) We then modify the architecture models in VPR/TPR to re ect the revised delay values of logic blocks and wire seg- ments, according to the parameters scaled from Table 5.1 and Table 5.2. The size of bu ers inserted in long interconnects are also re-optimized with the new delay parameters;
(3) We place and route the 20 largest MCNC benchmark circuits with the modi ed VPR/TPR, and quantify the relative improvement against the baseline 2D FPGA.

routing graph
Zhang, Tianpei Routing Issues in Nanometer-scale Integrated Circuits A PhD Dissertation September 2006 p160

This chapter presents some background material on routing that is used through the rest of
this thesis. Section 2.1 begins by presenting some basic definitions and an overview of a routing
flow, and is followed by Section 2.2, which discusses the concept of a routing graph. Next, buffer
insertion models are overviewed in Section 2.3, and performance metrics for delay, crosstalk and
temperature are presented in Section 2.4. Finally, the concept of Rent’s rule, which is used to
predict interconnect distributions, is detailed in Section 2.5.

=================================

Figure 2.2: (a) A routing grid and its corresponding global routing graph. (b) An inset view of
four globally routed nets simultaneously passing through the boundary between two GRCs.

===============================================

As multiple nets are routed over the routing graph, a common boundary between two
neighboring GRCs may be crossed by wires belonging to different nets. In terms of the graph representation,
this implies that multiple routing trees can utilize a common edge e 2 E. Figure 2.2(b)
depicts such a scenario: four globally routed nets simultaneously pass through the boundary (corresponding
to an edge in the routing graph) between two neighboring GRCs. Due to routing space
limitations on the boundary corresponding an edge e, we require that We  Ce, in which We is the
number of nets passing the edge e, defined as edge usage, and Ce is the upper bound of available
routing tracks over edge e, referred to as edge capacity. A violation of this requirement results
in overflow, which is numerically defined as We ? Ce. The most fundamental requirement for a
global routing solution is that all of the nets should be routed so that there is no overflow along
any routing graph edge.

===============================================

Figure 3.7: Updating SSA for one-child and two-child GRCs.

==========================================

Note that MANi and MNi are both defined per edge of the routing graph of Section 3.2.1 and
together define a basic structure of power network, thus enabling the power considerations to be
incorporated even before a detailed power architecture is determined. Any extra power lines/shields
beyond MNi and MANi will only improve the power grid performance [107]. This power grid
model works well on intermediate metal layers, as in [97], where the variable number of power lines
in adjacent blocks do not have to match exactly since they can be connected to each other through
upper layers. The edge capacities in the routing graph are shared by signal wires and power supply
wires, implying that if signal wires utilize too much of the routing capacity at a boundary, then
it is not possible to make enough room for supply wires. The supply wires in the supply grid are
used not only to carry power currents, but also work as shields between aggressor and victim signal
wires to reduce noise; we will use the terms supply wire and shield interchangeably.

==================================================

Problem Formulation
The formal statement of the problem is as follows. Given a tiling of a chip and the corresponding
routing graph G = (V,E), a set of nets N = {n1, n2, ..., nm}, the edge capacity Cij for
every edge eij 2 E, and the buffer capacity Bi for each routing cell i 2 V , the problem is to find
a routing solution that:
1. determines the routes for each net on the routing graph,
32
2. satisfies the power wire density constraints, i.e., the average and minimum density MANi
and MNi of each block must be met,
3. determines the GRCs in which a net is to be buffered, subject to the buffer capacity constraint,
4. finds Pij, k over each edge eij in the routing of net k, subject to the edge capacity constraint
(3.2),
5. satisfies noise constraint (3.4) for all nets.
6. ensures that the total amount of interconnects that can be driven by a buffer (gate) is at
most M grid units.

==================================================

Global Routing Flow
Our global routing seeks a feasible path on the routing graph for each net to satisfy the
requirement such as congestion and wire length etc. As an important step to distribute metal wires
on layout plane, our global routing also focuses on arrange nets in a more laterally uniform way so
as to achieve xy-uniformity and utilize less dummy metal fills during ILD CMP process. The global
routing flow first builds a minimum spanning tree (MST) based on Manhattan distance between
pins, using Prim’s algorithm [35], for each multiple-pin net, so as to decompose it into a set of
two-pin nets (for simplicity, two-pin net will be simply referred to as net in the following phases).
The order of routing those nets gives priority to shorter nets, i.e., by ranking all nets by their
bounding-box wire length, our global router processes nets with ascending order of wire length.
As observed in [67], longer nets have more flexibility to avoid congested regions, and therefore this
scheme can reduce congestion as well as total wire length. If there is still an overflow at the end,
we perform rip-up and reroute on all nets with the same order, as in [86].

==================================================

==================================================

Routing Capacity Deflation for Uniform Metal Distribution
Each two-pin-decomposed net is routed using Dijkstra’s algorithm [35] to identify the minimum
cost path connecting the two pins. As discussed in Section 6.2, a uniformly distributed
interconnect structure is conducive to fewer dummy metal fills, which leads to a more manufacturable
design. The cost function for the global routing algorithm must not only achieve routability,
i.e., avoid overflow on routing edges, but also should create a better xy-uniformity to avoid gener- ating high wire density regions. The cost function Coste that we use for passing an edge e in the
routing graph is defined as:
Coste = Clength(e) + · Ccong(e) + · Cbend(e) (6.10)
in which Clength(e) is the length cost, Ccong(e) is the congestion cost, and Cbend(e) 2 0, 1 is the
cost for introducing a bend, and its value depends on whether there is a bend in the propagation
direction; this is employed to suppress the number of vias for better interconnect reliability. The
parameters and are user-defined, and generally we use large value for to emphasize congestion
avoidance and uniformity in wire distribution. The congestion cost Ccong(e) takes the form:
Ccong(e) =
(We?Crcd, e ), in which
> 1 is a constant, We is the actual number of wires passing
the boundary, and the function punishes overuse of routing resources on an edge. It is noted
that, instead of using the actual edge capacity Ce, we utilize a routing capacity deflation (RCD)
technique and intentionally deflate routing capacity to a value Crcd, e < Ce. Plugged into the congestion
cost, this reduced capacity can guide routing to target Crcd, e as the routing usage goal,
hence encourage nets to spread over the routing plane laterally. In practice, the horizontal[vertical]
deflated capacity is calculated by averaging the total estimated horizontal[vertical] wire length over
all horizontal[vertical] edges. Thus defined deflated capacity can greatly help achieve a uniform
wire distribution as the routing usage goal itself is calculated as an effort of “averaging”.

==================================================

routing graph
Zhou, Pingqiang: Interconnect Design Techniques for Multicore and 3D Integrated Circuits PhD Thesis August, 2012 p135

?????????????????????

routing graph

directed routing graph

core graph

adjacency graph

adjacent graph

B*-tree

========================================

Our 3D NoC synthesis algorithm is performed on a directed routing graph G′(V ′,E′): V ′ is the vertex set, which is the union of core set V in the input core graph G(V,E, λ) and the set of added routers, Vs. We assume that the maximum number of routers that can be used in each 3D tier l equals to the number of cores in that tier, although it is easy to relax this restriction. The edge set E′ is constructed as follows: we connect cores in a tier l only to the routers in the same tier l and adjacent tiers l ? 1, l + 1 and the routers from all the 3D tiers form a complete graph. A custom NoC topology is a subgraph of the routing graph, G′.

The 3D NoC synthesis problem can be viewed as a multicommodity ow (MCF) problem. For a core graph G(V,E, λ) and a corresponding routing graph G′(V ′,E′) (corresponding to a flow network), let c(u, v) be the capacity of edge (u, v) ∈ E′. The capacity c(u, v) equals to the product of the operating frequency f and data link width W. Each commodity Ki = (si, ti, di), i = 1, · · · , k corresponds to the weight (traffic flow) along edge esi,ti in the core graph from source si to destination ti, and di = λ(esi,ti) is the demand for commodity i. Therefore, there are k = |E| commodities in the core graph. Let the flow of commodity i along edge (u, v) be fi(u, v). Then the MCF problem is to find the optimal assignment of flow which satisfies the constraints:

========================================

=====================================

2.5.1 Simulated Allocation Algorithm

SAL [8, 34] is a stochastic approach for finding near-optimal solutions for the multicommodity traffic flow problems in computer network design. It has been shown to be simpler, but often faster and more efficient, than other stochastic algorithms such as simulated annealing and evolutionary algorithms. We adopt the SAL framework from [34], but adapt it to solve the 3D NoC synthesis problem in our work. The details of the SAL algorithm used in our work are described in Algorithm 1.

In the core graph G(V,E, λ), let
? Pi be the number of available paths for traffic demand Ki = (si, ti, di),
? xip be the amount of traffic flow realizing the traffic Ki = (si, ti, di) allocated to
path p in routing graph G′,
? x = {xip : i = 1, 2, · · · , k, p = 1, 2, · · · , Pi} be the allocation state,
? |x| =
Σ
i
Σ
p xip be the total allocated traffic flow, and

? H = Σ i di be the total amount of traffic flow.

q(|x|) then
allocation(x);
end
disconnect(x);
if |x| = H then
n = n + 1;
counter = counter + 1;
if F(x) < Fbest then
Fbest = F(x);
xbest = x;
counter = 0;
end
end
until n = N or counter = M;

Note that in this section, we use single-path routing to introduce how the SAL method works. In Section 2.6.3, we extend SAL to deal with multipath routing problems. For single-path routing, we assume that each commodity is non-bifurcated, and in the routing graph, at most k paths, one per commodity, will have nonzero flows. Therefore, even though the number of paths can be exponentially large, it is never necessary to enumerate Pi; storing the allocation state x does not impose a significant memory overhead.

========================================

Procedure allocation(x) selects one currently non-allocated commodity, Ki = (si, ti, di), at random and allocates it to one of the allowable paths that have enough residual capacity to support Ki in the routing graph. The path for allocating Ki is chosen to be the minimum cost path p with respect to the cost function for the NoC topology construction step. Then we add flow xip = di to the current state x and reduce the capacities of the links on the selected path p in the routing graph by di. When routing commodity Ki, several new links and routers from the routing graph may be added to the NoC topology and the sizes of the routers on the path p may need to be adjusted accordingly.

========================================

========================================

========================================

2.5.3 Router Location Estimation and Path Cost Estimation

When routing a flow from source s to destination d in the allocation(x) step (refer to Section 2.5.1), our objective is to find a minimum cost path in the routing graph. While the initial solution considers the physical locations of only the cores, as flow allocation proceeds, new routers will be included in the NoC topology and their physical positions must be estimated to compute the link power and delay.

We estimate the router locations in the following way: for a newly added router i, the router is initially placed at the centroid of the source and destination nodes of router i in the routing graph. Given these initial estimates of the positions of the newly added routers, we apply Dijkstra’s shortest path algorithm on the routing graph to find the minimum cost path for the traffic flow, which is required by allocation(x). Here the path cost is the cost for NoC topology synthesis, as shown in Equation (2.2). When the 3D NoC synthesis step is complete, we feed the actual routers and links in the synthesized architecture to the floorplanner to update the router locations, for more accurate power and delay estimation. Since the floorplanner is stochastic, it is possible for the new floorplan to be vastly different from the one that was used to generate the NoC topology, negating the assumptions used to build the topology. To avoid this, we add a penalty to the objective function of the floorplanner to ensure that the blocks do not move far away from their initial locations, and optimize the precise locations of the routers, which were initially placed in (possibly illegal) centroid locations.

================================================

Several parameters affect the efficiency and performance of the SAL algorithm (Section 2.5.1). In choosing the q(γ) function for SAL, we found that for 0 < γ < 1, a constant function q(γ) = q0 = 0.9, can produce good solutions. The user-specified iteration limit N is empirically set to be three times of k, the number of commodities in the core graph, and M is set to be 50 or 100, depending on the size of MCF problem. We find that the best solutions are often obtained within k visited full allocation states for all the benchmarks.

================================================

2.6.3 3D-SAL-FP Based on Multipath Routing

In Section 2.6.2, our 3D-SAL-FP algorithm is based on single-path routing, which means that each commodity (traffic flow in the given core graph) is non-bifurcated and we choose one single path in the routing graph for one commodity. In this section, we extend 3D-SAL-FP to work with multipath routing where each commodity can be split into several subflows and each subflow can be routed independently in the routing graph.

Let L be the capacity of each subflow, then a commodity with traffic demand di can be split into ?di/L? subflows. Here we use the capacity L to control the granularity of the subflow, so that the size of the MCF problem in multipath routing can be controlled. In our experiments, L is set individually for each benchmark because the values of the traffic demand di varies greatly from benchmark to benchmark. After splitting the commodities in the core graph, we treat each of the resulting subflows as a single routing unit and select one minimum cost path to route it. Since the subflows constituting the same commodity can be routed on different paths on the routing graph, we refer to the new routing problem supporting subflows as multipath routing. In fact, the costs for the routers and links in the routing graph are state-dependent, when the subflows are routed one after another, it is highly possible for the subflows of one commodity to be routed on different paths.

========================================

========================================

extended routing graph

directed routing graph
directed routing graph

3D directed routing graph
directed routing graph in 3d ic
directed routing graph in 3d circuits
directed routing graph in 3d integrated circuits
directed routing graph in three dimensional integrated circuits
directed routing graph in 3d VLSI
directed routing graph in three dimensional VLSI

directed routing graph
Zhou, Pingqiang: Interconnect Design Techniques for Multicore and 3D Integrated Circuits PhD Thesis August, 2012 p135

Our 3D NoC synthesis algorithm is performed on a directed routing graph G′(V ′,E′): V ′ is the vertex set, which is the union of core set V in the input core graph G(V,E, λ) and the set of added routers, Vs. We assume that the maximum number of routers that can be used in each 3D tier l equals to the number of cores in that tier, although it is easy to relax this restriction. The edge set E′ is constructed as follows: we connect cores in a tier l only to the routers in the same tier l and adjacent tiers l ? 1, l + 1 and the routers from all the 3D tiers form a complete graph. A custom NoC topology is a subgraph of the routing graph, G′.

The 3D NoC synthesis problem can be viewed as a multicommodity ow (MCF) problem. For a core graph G(V,E, λ) and a corresponding routing graph G′(V ′,E′) (corresponding to a flow network), let c(u, v) be the capacity of edge (u, v) ∈ E′. The capacity c(u, v) equals to the product of the operating frequency f and data link width W. Each commodity Ki = (si, ti, di), i = 1, · · · , k corresponds to the weight (traffic flow) along edge esi,ti in the core graph from source si to destination ti, and di = λ(esi,ti) is the demand for commodity i. Therefore, there are k = |E| commodities in the core graph. Let the flow of commodity i along edge (u, v) be fi(u, v). Then the MCF problem is to find the optimal assignment of flow which satisfies the constraints:

=====================================

2.5.1 Simulated Allocation Algorithm

SAL [8, 34] is a stochastic approach for finding near-optimal solutions for the multicommodity traffic flow problems in computer network design. It has been shown to be simpler, but often faster and more efficient, than other stochastic algorithms such as simulated annealing and evolutionary algorithms. We adopt the SAL framework from [34], but adapt it to solve the 3D NoC synthesis problem in our work. The details of the SAL algorithm used in our work are described in Algorithm 1.

In the core graph G(V,E, λ), let
? Pi be the number of available paths for traffic demand Ki = (si, ti, di),
? xip be the amount of traffic flow realizing the traffic Ki = (si, ti, di) allocated to
path p in routing graph G′,
? x = {xip : i = 1, 2, · · · , k, p = 1, 2, · · · , Pi} be the allocation state,
? |x| =
Σ
i
Σ
p xip be the total allocated traffic flow, and

? H = Σ i di be the total amount of traffic flow.

q(|x|) then
allocation(x);
end
disconnect(x);
if |x| = H then
n = n + 1;
counter = counter + 1;
if F(x) < Fbest then
Fbest = F(x);
xbest = x;
counter = 0;
end
end
until n = N or counter = M;

Note that in this section, we use single-path routing to introduce how the SAL method works. In Section 2.6.3, we extend SAL to deal with multipath routing problems. For single-path routing, we assume that each commodity is non-bifurcated, and in the routing graph, at most k paths, one per commodity, will have nonzero flows. Therefore, even though the number of paths can be exponentially large, it is never necessary to enumerate Pi; storing the allocation state x does not impose a significant memory overhead.

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Procedure allocation(x) selects one currently non-allocated commodity, Ki = (si, ti, di), at random and allocates it to one of the allowable paths that have enough residual capacity to support Ki in the routing graph. The path for allocating Ki is chosen to be the minimum cost path p with respect to the cost function for the NoC topology construction step. Then we add flow xip = di to the current state x and reduce the capacities of the links on the selected path p in the routing graph by di. When routing commodity Ki, several new links and routers from the routing graph may be added to the NoC topology and the sizes of the routers on the path p may need to be adjusted accordingly.

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2.5.3 Router Location Estimation and Path Cost Estimation

When routing a flow from source s to destination d in the allocation(x) step (refer to Section 2.5.1), our objective is to find a minimum cost path in the routing graph. While the initial solution considers the physical locations of only the cores, as flow allocation proceeds, new routers will be included in the NoC topology and their physical positions must be estimated to compute the link power and delay.

We estimate the router locations in the following way: for a newly added router i, the router is initially placed at the centroid of the source and destination nodes of router i in the routing graph. Given these initial estimates of the positions of the newly added routers, we apply Dijkstra’s shortest path algorithm on the routing graph to find the minimum cost path for the traffic flow, which is required by allocation(x). Here the path cost is the cost for NoC topology synthesis, as shown in Equation (2.2). When the 3D NoC synthesis step is complete, we feed the actual routers and links in the synthesized architecture to the floorplanner to update the router locations, for more accurate power and delay estimation. Since the floorplanner is stochastic, it is possible for the new floorplan to be vastly different from the one that was used to generate the NoC topology, negating the assumptions used to build the topology. To avoid this, we add a penalty to the objective function of the floorplanner to ensure that the blocks do not move far away from their initial locations, and optimize the precise locations of the routers, which were initially placed in (possibly illegal) centroid locations.

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Several parameters affect the efficiency and performance of the SAL algorithm (Section 2.5.1). In choosing the q(γ) function for SAL, we found that for 0 < γ < 1, a constant function q(γ) = q0 = 0.9, can produce good solutions. The user-specified iteration limit N is empirically set to be three times of k, the number of commodities in the core graph, and M is set to be 50 or 100, depending on the size of MCF problem. We find that the best solutions are often obtained within k visited full allocation states for all the benchmarks.

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2.6.3 3D-SAL-FP Based on Multipath Routing

In Section 2.6.2, our 3D-SAL-FP algorithm is based on single-path routing, which means that each commodity (traffic flow in the given core graph) is non-bifurcated and we choose one single path in the routing graph for one commodity. In this section, we extend 3D-SAL-FP to work with multipath routing where each commodity can be split into several subflows and each subflow can be routed independently in the routing graph.

Let L be the capacity of each subflow, then a commodity with traffic demand di can be split into ?di/L? subflows. Here we use the capacity L to control the granularity of the subflow, so that the size of the MCF problem in multipath routing can be controlled. In our experiments, L is set individually for each benchmark because the values of the traffic demand di varies greatly from benchmark to benchmark. After splitting the commodities in the core graph, we treat each of the resulting subflows as a single routing unit and select one minimum cost path to route it. Since the subflows constituting the same commodity can be routed on different paths on the routing graph, we refer to the new routing problem supporting subflows as multipath routing. In fact, the costs for the routers and links in the routing graph are state-dependent, when the subflows are routed one after another, it is highly possible for the subflows of one commodity to be routed on different paths.

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Global Routing Graph

Global Routing Graph

3D global routing graph

2 layer global routing grid graph model
global routing graph

3D global routing graph
global routing graph in 3d ic
global routing graph in 3d circuits
global routing graph in 3d integrated circuits
global routing graph in three dimensional integrated circuits
global routing graph in 3d VLSI
global routing graph in three dimensional VLSI

Global Routing Graph
Sanusi, Azeez O. and Bayoumi, Magdy A: . SEGRoute A New Global Routing Methodology Based on Grid Graph Segmentation 2005 p4...........

Azeez O. Sanusi
Center for Advanced Computer
Studies, University of Louisiana at
Lafayette
Lafayette, LA 70504

AZEEZ SANUSI

Ph.D. Student, Computer Engineering,
VLSI Research Group, CACS
University of Louisiana at Lafayette

jbm8240@cacs.louisiana.edu

Magdy A. Bayoumi
Center for Advanced Computer
Studies, University of Louisiana at
Lafayette
Lafayette, LA 70504

Office The Center for Advanced Computer Studies (CACS) James R. Oliver Hall, Room # 201G 301 East Lewis Street Lafayette, Louisiana 70503 Phone +1-337-482-6147 Fax +1-337-482-5791 Email mab@cacs.louisiana dot edu
The grid graph model is the most commonly used model in global routing. In this model, the routing area is partitioned into rectangular regions called global bins with the assumption that all pins in a bin are at the center of the bin (with the centers making up the global routing graph). The boundary of each global bin is called a global edge and it corresponds to an edge in the grid graph (see figure 1). Each global edge has a maximum amount of routing resources i.e. capacity (The number of routing tracks available).

Global Routing Graph for 3D ICs

Routing Issues in Nanometer-scale Integrated Circuits

Zhang, Tianpei Routing Issues in Nanometer-scale Integrated Circuits A PhD Dissertation September 2006 p160 ...................

Minimum Spanning Tree (MST)

network flow graph

rectilinear tree

Steiner tree

spanning trees

Minimum Spanning Tree

rectilinear minimum spanning tree

routing tree

multiple routing trees

interconnect tree

binary tree

RC Trees

Chapter 2 Preliminaries

This chapter presents some background material on routing that is used through the rest of this thesis. Section 2.1 begins by presenting some basic definitions and an overview of a routing flow, and is followed by Section 2.2, which discusses the concept of a routing graph. Next, buffer insertion models are overviewed in Section 2.3, and performance metrics for delay, crosstalk and temperature are presented in Section 2.4. Finally, the concept of Rent’s rule, which is used to predict interconnect distributions, is detailed in Section 2.5.

2.2 Global Routing Graph

2.2.1 Global Routing Graph for 2D ICs

A fundamental notion in global routing is the global routing graph, which plays a central role in global routing resource planning and is a critical ingredient of the problem formulation. For a regular 2D IC, as shown in Figure 3.1(a), our global routing model tessellates the entire chip into an array of grid cells, referred to as the routing grid; each grid cell is then referred to as a global routing cell (GRC). The dual graph of the routing grid tessellation is the global routing graph G = (V,E). The elements of V and E are shown in Figure 2.2(a) as darkened dots and dashed lines, respectively. Each vertex v ∈ V represents a GRC and each edge e ∈ E corresponds to a
boundary bij , which connects two neighboring GRCs i and j. The grid length Le for an edge e is defined as the center-to-center distance between two neighboring GRCs.

During the global routing stage, the pins of a net Ni ∈ N are first mapped to the corresponding GRCs, thus we can obtain a set of vertices V Ii = {vi,0, vi,1, . . .} ? V , which are associated with those GRCs. The routing problem for a net Ni ∈ N is to find an additional set of vertices V Ai ? V , which are called Steiner vertices, and a set of edges Ei = {ei,0, ei,1, . . .} ? E, which are referred to as routing path, to form a rectilinear minimum spanning tree Ti = (Vi,Ei), where Vi = V Ii ∪ V Ai, so that some performance-related metric is optimized.

As multiple nets are routed over the routing graph, a common boundary between two neighboring GRCs may be crossed by wires belonging to different nets. In terms of the graph representation, this implies that multiple routing trees can utilize a common edge e ∈ E. Figure 2.2(b) depicts such a scenario: four globally routed nets simultaneously pass through the boundary (corresponding to an edge in the routing graph) between two neighboring GRCs. Due to routing space limitations on the boundary corresponding an edge e, we require that We ≤ Ce, in which We is the number of nets passing the edge e, defined as edge usage, and Ce is the upper bound of available routing tracks over edge e, referred to as edge capacity. A violation of this requirement results in overflow, which is numerically defined as We ? Ce. The most fundamental requirement for a global routing solution is that all of the nets should be routed so that there is no overflow along any routing graph edge.

Figure 2.2: (a) A routing grid and its corresponding global routing graph. (b) An inset view of four globally routed nets simultaneously passing through the boundary between two GRCs.

2.2.12 Global Routing Graph for 3D ICs
In three-dimensional (3D) ICs, devices are fabricated on a number of stacked active layers. Within each device layer, devices can be interconnected with traditional interconnect wires and vias. Connections between active layers are facilitated by vertical interconnect vias that span through two or more layers, providing a means for electrically connecting wires in those layers; we refer to such vias as interlayer vias.
To better characterize the unique interconnect resources in 3D ICs, we introduce a 3D global routing graph which is illustrated in Figure 2.3. We first build a regular 2D global routing graph for each active layer as in Section 2.2.1. Next, by stacking the global routing graphs of all layers and connecting each pair of vertically neighboring routing nodes with a vertical routing edge, we build a 3D global routing graph, which is shown by the darkened dots and dashed lines in Figure 2.3. There are two classes of edges in the graph:

Each lateral edge in the 3D global routing graph is derived from its counterpart in regular 2D global routing graph, and follows the same routing resource constraints as in Section 2.2.1;

Each vertical edge in the 3D routing graph corresponds to the interlayer vias connecting two vertically neighboring GRCs. As interlayer vias can only use the white space that is not occupied by devices while passing active layers, there is an upper limit on the number of interlayer vias for each vertical edge in the routing graph, referred to as interlayer via capacity Ui. We require Vi ≤Ui, in which Vi is the actual number of interlayer vias through GRC i, otherwise, we obtain vertical overflow.

Figure 2.3: A 3D global routing graph for a 3D IC with four active layers.

The problem of global routing in 3D ICs involves finding the spanning trees of all nets on the 3D global routing graph, so that there is no lateral and vertical overflow, and some specified performance-related metrics are optimized.
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Our global routing problem considers simultaneously routing a set of m nets, N = {n1, n2, . . . , nm}. During the routing process, we build the global routing grid and global routing graph as described in Section 2.2.1 and find the routing path in terms of routing graph edges for each net. As power wires are considered at the same time with signal wire routing and will share routing resources, the routability requirement for a routing edge e can be more specified as: Se +Pe  Ce, where Se and Pe are the total widths (including wire spacing) used by signal and power lines passing edge e, and Ce is the geometrical width of the routing cell boundary associated with edge e; violation of this will result in routing overflow. In routing layer arrangement, we follow a routing model in which horizontal and vertical lines are routed on different layers so that each layer is dedicated to routing in one direction. The aim of routing is to eliminate routing overflow while achieving other performance-related goals such as noise reduction.

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To effectively improve timing performance and block noise propagation, buffer insertion is addressed during the routing process. We employ the distributed buffer model as described in Section 2.3, and assume there are buffer sites pre-distributed across the layout plane. Applying routing grid to the layout plane as the tessellation discussed in Section 2.3, the number of buffer sites in each global routing cell (GRC) can be found, and they can be selectively implemented to be buffers and inserted to global nets passing the GRC. To emphasize the buffer planning role of routing grid, we redraw the global routing grid and its corresponding routing graph (which are discussed in Section 2.2.1) in Figure 3.1(a), and Figure 3.1(b) gives an inset view that buffer sites distributed in two neighboring GRCs are implemented to be buffers and inserted to globally routed nets. To control the interconnect delay and slew rate, a maximum wire length driven by a buffer (gate) is enforced as described in Section 2.3; in terms of global routing grid, this translates to a requirement that the maximum total interconnect length that can be driven by a buffer (gate) is the length of M GRCs.

Figure 3.1: (a) A routing grid and the corresponding global routing graph. (b) Buffer sites in GRCs are implemented to be buffers which are inserted to signal wires.

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Note that MANi and MNi are both defined per edge of the routing graph of Section 3.2.1 and together define a basic structure of power network, thus enabling the power considerations to be incorporated even before a detailed power architecture is determined. Any extra power lines/shields beyond MNi and MANi will only improve the power grid performance [107]. This power grid model works well on intermediate metal layers, as in [97], where the variable number of power lines in adjacent blocks do not have to match exactly since they can be connected to each other through upper layers. The edge capacities in the routing graph are shared by signal wires and power supply wires, implying that if signal wires utilize too much of the routing capacity at a boundary, then it is not possible to make enough room for supply wires. The supply wires in the supply grid are used not only to carry power currents, but also work as shields between aggressor and victim signal wires to reduce noise; we will use the terms supply wire and shield interchangeably.

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The formal statement of the problem is as follows. Given a tiling of a chip and the corresponding routing graph G = (V,E), a set of nets N = {n1, n2, ..., nm}, the edge capacity Cij for every edge eij 2 E, and the buffer capacity Bi for each routing cell i 2 V , the problem is to find a routing solution that:

1. determines the routes for each net on the routing graph, 32

2. satisfies the power wire density constraints, i.e., the average and minimum density MANi and MNi of each block must be met,

3. determines the GRCs in which a net is to be buffered, subject to the buffer capacity constraint,

4. finds Pij, k over each edge eij in the routing of net k, subject to the edge capacity constraint (3.2),

5. satisfies noise constraint (3.4) for all nets.

6. ensures that the total amount of interconnects that can be driven by a buffer (gate) is at most M grid units.

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The multiple-layer structure of 3D IC complicates the global routing problem, but we may extend some basic constructs from 2D routing to 3D. The 3D global routing grid and global routing graph can be built as in Section 2.2.2. Essentially the 3D global routing graph is an stacking of the 2D global routing graphs for all active layers, with vertical edges connecting neighboring ones, which represents interlayer vias. A net N in a 3D IC consists of a set of electrically equivalent pins, {n0, n1, n2, . . . , nk}, distributed in different GRCs (possibly on different active layers), of which 56 n0 is the source and n1, n2, ..., nk are sinks. If a net has pins distributed on different layers, it is referred to as an 3D net; otherwise it is called a 2D net. The global routing of a net in a 3D IC is to find a set of edges that connect all pins in the corresponding 3D global routing graph.

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Like signal interlayer vias, thermal vias can be planned in each GRC position i between two layers. Following the vertical edge capacity constraint for 3D global routing graph defined in Section 2.2.2, we require Vi  Ui, in which Ui is the interlayer via capacity for GRC i, and Vi is the total number of both signal interlayer vias and thermal vias going through GRC i. Here we assume that the interlayer vias for power grid are predetermined and there are dedicated resources for them, which are excluded from Ui.

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6.4.1 Routing Model and Algorithm Overview

Our routing algorithm is a complete routing flow, which includes three phases, as shown in Figure 6.5: global routing, layer assignment, and detailed routing. In the first global routing phase, we build the global routing graph as in Section 2.2.1. During the process, the chip is tessellated into a two-dimensional array of GRCs, or a routing grid. In general, this grid may be different from the CMP grid discussed earlier; however, we will show that there are some conveniences associated with using the same grid for both purposes. The global routing phase determines the rough routing regions, in terms of GRCs, that each net passes through, while satisfying the routing capacity requirements. At the same time, with the CMP dummy fill model that feeds into global routing, nets are also spread out laterally using a routing capacity deflation (RCD) technique to obtain a better xy-uniformity of metal distribution for minimized dummy fills.

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Global Routing for Uniform Metal Distribution
Global Routing Flow

Our global routing seeks a feasible path on the routing graph for each net to satisfy the requirement such as congestion and wire length etc. As an important step to distribute metal wires on layout plane, our global routing also focuses on arrange nets in a more laterally uniform way so as to achieve xy-uniformity and utilize less dummy metal fills during ILD CMP process. The global routing flow first builds a minimum spanning tree (MST) based on Manhattan distance between pins, using Prim’s algorithm [35], for each multiple-pin net, so as to decompose it into a set of two-pin nets (for simplicity, two-pin net will be simply referred to as net in the following phases). The order of routing those nets gives priority to shorter nets, i.e., by ranking all nets by their bounding-box wire length, our global router processes nets with ascending order of wire length. As observed in [67], longer nets have more flexibility to avoid congested regions, and therefore this scheme can reduce congestion as well as total wire length. If there is still an overflow at the end, we perform rip-up and reroute on all nets with the same order, as in [86].

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Routing Capacity Deflation for Uniform Metal Distribution

Each two-pin-decomposed net is routed using Dijkstra’s algorithm [35] to identify the minimum cost path conn ecting the two pins. As discussed in Section 6.2, a uniformly distributed interconnect structure is conducive to fewer dummy metal fills, which leads to a more manufacturable design. The cost function for the global routing algorithm must not only achieve routability, i.e., avoid overflow on routing edges, but also should create a better xy-uniformity to avoid generating high wire density regions. The cost function Coste that we use for passing an edge e in the routing graph is defined as:
Coste = Clength(e) + · Ccong(e) + · Cbend(e) (6.10)
in which Clength(e) is the length cost, Ccong(e) is the congestion cost, and Cbend(e) 2 0, 1 is the cost for introducing a bend, and its value depends on whether there is a bend in the propagation direction; this is employed to suppress the number of vias for better interconnect reliability. The parameters and are user-defined, and generally we use large value for to emphasize congestion avoidance and uniformity in wire distribution. The congestion cost Ccong(e) takes the form:
Ccong(e) = (We?Crcd, e ), in which
> 1 is a constant, We is the actual number of wires passing the boundary, and the function punishes overuse of routing resources on an edge. It is noted that, instead of using the actual edge capacity Ce, we utilize a routing capacity deflation (RCD) technique and intentionally deflate routing capacity to a value Crcd, e < Ce. Plugged into the congestion cost, this reduced capacity can guide routing to target Crcd, e as the routing usage goal,
hence encourage nets to spread over the routing plane laterally. In practice, the horizontal[vertical] deflated capacity is calculated by averaging the total estimated horizontal[vertical] wire length over all horizontal[vertical] edges. Thus defined deflated capacity can greatly help achieve a uniform wire distribution as the routing usage goal itself is calculated as an effort of “averaging”.

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multiple routing trees

As multiple nets are routed over the routing graph, a common boundary between two neighboring GRCs may be crossed by wires belonging to different nets. In terms of the graph representation, this implies that multiple routing trees can utilize a common edge e 2 E. Figure 2.2(b) depicts such a scenario: four globally routed nets simultaneously pass through the boundary (corresponding to an edge in the routing graph) between two neighboring GRCs. Due to routing space limitations on the boundary corresponding an edge e, we require that We  Ce, in which We is the number of nets passing the edge e, defined as edge usage, and Ce is the upper bound of available routing tracks over edge e, referred to as edge capacity. A violation of this requirement results in overflow, which is numerically defined as We ? Ce. The most fundamental requirement for a global routing solution is that all of the nets should be routed so that there is no overflow along any routing graph edge.

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Algorithm for Building Protection Solutions

A unitary step in the enumeration algorithm is to build the solution set array at the current GRC based on the arrays at its child cell(s). Solutions in set SSA[k], k 6= 0 are propagated from solutions in the lower indexed sets of the children GRCs. During the process, we update the noise margin according to different shielding choices to form new solutions, and the least cost child solution will be used to build solution in SSA[0] in which buffer is inserted right at current GRC. The main procedure in the algorithm calls function Find sol set array at the source cell, and returns the minimum cost solution that satisfies the noise constraint. The pseudo code for the algorithm is listed in Figure 3.6.

Algorithm: Shield buffer insertion for noise reduction
Input: Net N = {s [ P [ IN [ E}
Output: A protection solution with least protection cost at source s
1. SSA = Find sol set array(s)
2. return protection solution S = {PC, NM, In, stru} 2 SSA, with PC is minimized.
Function: Find sol set array
Input: t is the GRC to be processed.
Output: The SSA of this GRC.
1. SSA[i] = , i = 0, 1, ...M ? 1
2. if t 2 P, is a leaf
for i = 0 to M ? 1
SSA[i] = SSA[i] [ {0,NMspec, 0,};
3. else if t has one child l
SSAl = Find sol set array(l);
for i = 1 to M ? 1
for each Sl 2 SSAl[i ? 1]
SSA[i] = SSA[i][ Propagate(Sl , t);
4. Take minimum PC solution Sm from SSAl,
SSA[0] = SSA[0][ Propagate(Insert buf (Sm, t), t);
5. else if t has two children l and r
SSAl=Find sol set array(l); SSAr=Find sol set array(r);
for i = 2 to M ? 1
for each Sl 2 SSAl[j], Sr 2 SSAr[k] and j+k=i ? 2
SSA[i] = SSA[i][Propagate(Merge(Sl , Sr), t);
6. Take min Sml.PC + Smr.PC solutions Sml,Smr from SSAl, SSAr;
SSA[0] = SSA[0][Propagate(Insert buf (Merge(Sl, Sr), t), t);
7. Take minimum PC solution Sml from SSAl;
for i = 1 to M ? 1
for each Sr 2 SSAr[i ? 1]
SSA[i] = SSA[i][Propagate(Merge(Insert buf (Sml,t),Sr),t);
8. Take minimum PC solution Smr from SSAr
for i = 1 to M ? 1
for each Sl 2 SSAl[i ? 1]
SSA[i] = SSA[i][Propagate(Merge(Sl ,Insert buf (Smr,t)), t);
9. Prune solution set array SSA;
Functions:
Propagate(S, t) /* Extend solution by one grid length upward*/
if t is source, return S;
else return {S.PC + PCt(0,Nsh), S.NM ? NM(Nsh), S.In + In(Nsh), S.stru [ {0,Nsh}},
Nsh = 0, 1, 2;
Insert buf(S, t) /* Insert a buffer to existing solution S */
return {S.PC + PCt(1, 0), NMspec, 0, S.stru [ {1, 0}};
Merge(Sl , Sr) /* Merge two solutions */
return {Sl.PC + Sr.PC,min(Sl.NM, Sr.NM), Sl.In + Sr.In, Sl.stru [ Sr.stru};

Figure 3.6: Algorithm for building protection solution

Function Find sol set array finds the solution set array for a GRC. SSA is first initialized in line 1, and line 2 initializes the trivial case of a leaf cell , in which both noise current and protection cost are set to 0. Next, line 3 considers a single child cell and builds SSA[i] from SSA[i ? 1] of the child cell as illustrated in the left part of Figure 3.7. It considers the three possibilities for the number of sides to be shielded: 0, 1 or 2. SSA[M ? 1] of the child cell will be dropped to avoid violating the buffer load rule. In line 4, the protection solution with minimum protection cost is selected from the children solutions and a buffer is inserted. As a result, both the noise margin and noise current are recovered for this tuple. Line 5 deals with finding a solution set array for a GRC with two children. The complexity involved here is that when we build the solution, all of the combinations must be considered, as the right part of Figure 3.7 suggests. Line 6 picks the least cost solution from both the left and right children, and inserts a buffer to drive both children, thereby recovering the noise margin and noise current. However, a buffer can also be inserted only to the left or right branch. Lines 7 and 8 build solution tuples that correspond to these two cases, where a buffer is inserted to only one child branch and combined with solutions from the other. In the above steps, functions Propagate, Insert buf and Merge are called to build solutions. There can be a large number of solutions in the SSA for a GRC after the Propagate and Merge steps; however, it is not necessary to keep all of them, and the solution pruning in the last steps will greatly reduce the solution set size. There are three types of pruning techniques employed here:

?? We prune those solutions that violate the noise constraint (3.4).
? We prune the solutions that violate the buffer or wiring capacity.
? If a solution S1 is provably inferior to another solution S2 in the same SSA of a GRC, i.e.,
if PC1 > PC2, NM1 < NM2 and In1 > In2, then it is pruned from the set of solutions.

Figure 3.7: Updating SSA for one-child and two-child GRCs.

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C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng, and D. Karger, “Prim-Dijkstra Tradeoffs for Improved Performance-Driven Routing Tree Design,” IEEE Transactions on Computer- Aided Design, 14(7), pages 890-896, July 1995.

K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, “Near-Optimal Critical Sink Routing Tree Constructions,” IEEE Transactions on Computer-Aided Design, 14(12), pages 1417-36, December 1995.

Multicast Routing Graph (MRG)
multicast routing graph

3D multicast routing graph
multicast routing graph in 3d ic
multicast routing graph in 3d circuits
multicast routing graph in 3d integrated circuits
multicast routing graph in three dimensional integrated circuits
multicast routing graph in 3d VLSI
multicast routing graph in three dimensional VLSI

Multicast Routing Graph (MRG)

condensed multicast routing graph

Multicast Routing Graph (MRG)
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25
S. Yan (?)
University of California, San Diego, CA, USA
e-mail: shyan@ucsd.edu

Routing Cost Graph

router cost graph

communication demand graph

connectivity graphs

hypergraph

channel dependency graph

extended channel dependency graph

Steiner tree

delay-oriented Steiner tree

multicast tree

optimum multicast tree

Multicast Routing Tree

directed minimum spanning tree

rooted directed minimum spanning tree

rooted directed spanning tree

minimum directed spanning tree

Minimum Directed Spanning Tree

Preliminaries

communication demand graph
Definition 1 A communication demand graph (CDG) is an annotated directed hypergraph H( V, E, π, λ), where each node vi ∈ V corresponds to a module, and each directed hyperedge ek = s → D ∈ E represents a traffic flow from source s ∈ V to one or more destinations D = {d1, d2,…}, D ? V. The position of each node vi is given by π( vi) = ( xi, yi). The data rate requirement for each communication flow ek is given by λ( ek ).

Routing Cost Graph
Definition 2 The RCG( R, E) is a weighted directed complete graph (a full-mesh) with each vertex ri ∈ R represents a router, and each directed edge eij = ( ri, rj) ∈ E from ri to rj corresponds to a connection from ri to rj. A weight w( eij) is attached to each edge which represents the incremental cost of routing a flow f through eij.

To address the 3D-NoC synthesis problem, we formulate the problem as a combination of a rip-up and reroute procedure for routing flows and a router merging procedure for optimizing network topologies. The key part of the algorithm is a ripup and reroute procedure that routes multicast flows by way of finding the optimum multicast tree on a condensed multicast routing graph using the directed minimum spanning tree formulation and the efficient algorithms [36, 37].

To address the 3D-NoC synthesis problem, we formulate the problem as a combination of a rip-up and reroute procedure for routing flows and a router merging procedure for optimizing network topologies. The key part of the algorithm is a ripup and reroute procedure that routes multicast flows by way of finding the optimum multicast tree on a condensed multicast routing graph using the directed minimum spanning tree formulation and the efficient algorithms [36, 37].

To address the 3D-NoC synthesis problem, we formulate the problem as a combination of a rip-up and reroute procedure for routing flows and a router merging procedure for optimizing network topologies. The key part of the algorithm is a ripup and reroute procedure that routes multicast flows by way of finding the optimum multicast tree on a condensed multicast routing graph using the directed minimum spanning tree formulation and the efficient algorithms [36, 37].

Then a router merging procedure follows after to further optimize the implementation and reduce cost. The router merging algorithm iteratively considers all possible mergings of two routers connected with each other and merges them if the cost of the resulting topology
after merging is reduced.

Then a router merging procedure follows after to further optimize the implementation and reduce cost. The router merging algorithm iteratively considers all possible mergings of two routers connected with each other and merges them if the cost of the resulting topology after merging is reduced.

As an example, after initial network construction, the connectivity of routers for the example shown in Fig. 8.3a is shown in Fig. 8.6a. In this initial solution, each core is connected to a dedicated router.

Fig. 8.6 Illustration of the RIPUP-REROUTE procedure. a Initial connectivity. b RCG. c MRG. d MRTree. e Connectivity before reroute e7. f Connectivity after reroute e7

Fig. 8.6 Illustration of the RIPUP-REROUTE procedure. a Initial connectivity. b RCG. c MRG. d MRTree. e Connectivity before reroute e7. f Connectivity after reroute e7

====================================================================

Once the initial network is constructed and the initial flow routing is done, the key procedure of the algorithm—RIPUP-REROUTE procedure is invoked to route flows and find optimized network topology. The details are described in Algorithm 2.

In the RIPUP-REROUTE, each multicast routing step is formulated as a minimum directed spanning tree problem. Two important graphs, Multicast Routing Graph (MRG) and Multicast Routing Tree (MRTree), are used to help facilitate the rip-up and rerouting procedure. They are defined as follows.

In the RIPUP-REROUTE, each multicast routing step is formulated as a minimum directed spanning tree problem. Two important graphs, Multicast Routing Graph (MRG) and Multicast Routing Tree (MRTree), are used to help facilitate the rip-up and rerouting procedure. They are defined as follows.

Definition 3 Let f be a multicast flow with source s ∈ V and one or more destinations D ? V. i.e., D = {d1, d2, . . . , d|D|}, each di ∈ V.
A Multicast Routing Graph (MRG) is a complete graph (N, A) defined for f as follows:
? N = s ∪ D .
? There is a directed arc between every pair of nodes ( i, j) in N. Each arc ai, j ∈ A corresponds to a shortest path pi, j between the same nodes in the corresponding RCG, pi, j = e1 → e2 → … → ek.
? The weight for arc ai, j, w( ai, j), corresponds to the path weight of the corresponding shortest path pi, j in RCG. i.e.,

Definition 3 Let f be a multicast flow with source s ∈ V and one or more destinations D ? V. i.e., D = {d1, d2, . . . , d|D|}, each di ∈ V.
A Multicast Routing Graph (MRG) is a complete graph Γ(N, A) defined for f as follows:
? N = s ∪ D .
? There is a directed arc between every pair of nodes ( i, j) in N. Each arc ai, j ∈ A corresponds to a shortest path pi, j between the same nodes in the corresponding RCG, pi, j = e1 → e2 → … → ek.
? The weight for arc ai, j, w( ai, j), corresponds to the path weight of the corresponding shortest path pi, j in RCG. i.e.,

w(ai, j) =∑ w(ei)

ei  p

Definition 4 A Multicast Routing Tree (MRTree) is the Minimum Directed Spanning Tree for multicast routing graph Γ(N, A) with s ∈ N as the root.

Definition 4 A Multicast Routing Tree (MRTree) is the Minimum Directed Spanning Tree for multicast routing graph  Γ(N, A) with s ∈ N as the root.
Once the RCG is constructed, the multicast routing graph (MRG) for the flow is generated from RCG (line 5). MRG is build by including every source and destination router of the flow as its nodes. For each pair of the nodes in MRG, the least cost directed path with least power consumption on RCG is found for the corresponding routers using Floyd-Warshall’s all pair shortest path algorithm and the cost is assigned as edge weight to the edge connecting the two nodes in MRG. Then the Chu-Liu/Edmonds algorithm [36, 37] is used to find the rooted directed minimum spanning tree of MRG with the source router as root. A rooted directed spanning tree of a graph is defined as a graph which connects, without any cycle, all n nodes
in the graph with n ? 1 arcs such that the sum of the weight of all the arcs is minimized. Each node, except the root, has one and only one incoming arc. This directed minimum spanning tree is obtained as the multicast routing tree (MRTree) so that the routes of the multicast flow follows the structure of this tree. The details of Chu- Liu/Edmonds Algorithm is summarized in Algorithm 3. The multicast routing for flow f in RCG can be obtained by projecting MRTree back to RCG by expanding the correspond arcs to paths. A special case is when f is a unicast flow with source s and destination d. In this case, MRG will just consist of two nodes, namely s and d, and one directed arc from s to d. Therefore, the routing between s and d in RCG
is simply a shortest path between s and d.

Once the RCG is constructed, the multicast routing graph (MRG) for the flow is generated from RCG (line 5). MRG is build by including every source and destination router of the flow as its nodes. For each pair of the nodes in MRG, the least cost directed path with least power consumption on RCG is found for the corresponding routers using Floyd-Warshall’s all pair shortest path algorithm and the cost is assigned as edge weight to the edge connecting the two nodes in MRG. Then the Chu-Liu/Edmonds algorithm [36, 37] is used to find the rooted directed minimum spanning tree of MRG with the source router as root. A rooted directed spanning tree of a graph is defined as a graph which connects, without any cycle, all n nodes in the graph with n ? 1 arcs such that the sum of the weight of all the arcs is minimized. Each node, except the root, has one and only one incoming arc. This directed minimum spanning tree is obtained as the multicast routing tree (MRTree) so that the routes of the multicast flow follows the structure of this tree. The details of Chu- Liu/Edmonds Algorithm is summarized in Algorithm 3. The multicast routing for flow f in RCG can be obtained by projecting MRTree back to RCG by expanding the correspond arcs to paths. A special case is when f is a unicast flow with source s and destination d. In this case, MRG will just consist of two nodes, namely s and d, and one directed arc from s to d. Therefore, the routing between s and d in RCG is simply a shortest path between s and d.
As an example, Fig. 8.6b shows the RCG for rerouting the multicast flow e7. For clarity, only part of the edges are shown for RCG. The MRG and MRTree for e7 are shown in Fig. 8.6c, d respectively. By projecting MRTree back to RCG, the routing path for e7 is determined, namely e7 is bifurcates in the source router R4 to reach R6 and v6, then it transferred over the network link between R4 to R2 to reach v2, and then bifurcates to reach R5 and v5. The real physical connectivity between routers before and after rip-up and rerouting e7 are also shown in Fig. 8.6e, f. From them,
we observe that the link between R4 and R5 and their corresponding ports are saved thus the power consumptions are reduced after rerouting e7 by utilizing the existing network resources for routing other flows.

Terminology

Literature


spanning graph

spanning graph
Hsu TSV-Aware Analytical Placement for 3D IC Designs p6.pdf

Terminology

Literature


Steiner graph

shortest-path Steiner graphs

nearly-optimal Steiner graph

Rectilinear Shortest-path Steiner Graph

minimal rectilinear shortest-path Steiner graph (RSSG)

Steiner Graph
Cheng Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph p8

Steiner graph

shortest-path Steiner graph

Rectilinear Shortest-path Steiner Graph

minimal rectilinear shortest-path Steiner graph (RSSG)

nearly-optimal Steiner graph

Steiner graph

shortest-path Steiner graph

Rectilinear Shortest-path Steiner Graph

minimal rectilinear shortest-path Steiner graph (RSSG)

nearly-optimal Steiner graph

Cheng, Chung-Kuan et al: Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph, ISPD’12, March 25–28, 2012, Napa, California, USA., p8

Cheng Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph p8

Cheng, Chung-Kuan et al: Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph, ISPD’12, March 25–28, 2012, Napa, California, USA., p23

In this paper, we propose a new approach for gated bus syn-
thesis [16] with minimum wire capacitance per transaction
in three-dimensional (3D) ICs. The 3D IC technology con-
nects different device layers with through-silicon vias (TSV),
which need to be considered differently from metal wire due
to reliability issues and a larger footprint. Practically, the
number of TSVs is bounded between layers; thus, we first
devise dynamic programming and local search techniques to
determine the optimal TSV locations. We then employ two
approximation algorithms to generate a rectilinear shortest-
path Steiner graph in each device layer. One algorithm ex-
tends the well-known greedy heuristic for the Rectilinear
Steiner Arborescence problem and handles large cases with
high efficiency. The other algorithm utilizes a linear pro-
gramming relaxation and rounding technique which costs
more time and generates a nearly-optimal Steiner graph.
Experimental results show that our algorithms can construct
shortest-path Steiner graphs with 22% less total wire length
than the previous method of Wang et al. [16].

Figure 1(a) shows an implementation of the gated bus ar-
chitecture with two masters s1, s2 and four slaves t1, . . . , t4.
The gray multiplexers and demultiplexers mask off the un-
used path when transferring data from s2 to t1 so that s2
only needs to drive the path consisting of the three solid ar-
rows. Therefore, driven wire capacitance is greatly reduced.
Figure 1(b) shows the Steiner graph representation of Fig-
ure 1(a). The Steiner points of Figure 1(b) indicate where
to place multiplexers/demultiplexers in the bus architec-ture.

To have the minimum wire capacitance for every data
transaction, the Steiner graph must contain a shortest path
with length equal to the Manhattan distance between each
master-slave pair. We call such a Steiner graph a shortestpath
Steiner graph; our objective is to find a shortest-path
Steiner graph with smallest total wire length. In [16], Wang
et al. proposed a heuristic method that first constructs
a minimum rectilinear Steiner arborescence [8][13] starting
from a master, and then adds other masters one by one in
each iteration to obtain a shortest-path Steiner graph.

In this paper, we investigate the problem of gated bus
synthesis in 3D ICs to minimize total power consumption of
the gated bus architecture. Since constraints of TSVs are
different from these of on-die vias, e.g., larger footprint and
keep-out zones, we must consider TSVs separately in this
problem. We first develop dynamic programming and local
search algorithms to determine TSV locations that minimize
the sum of weighted shortest distances over all master-slave
pairs in a 3D IC design. Then, given the TSV locations thus
determined, we propose two approximation algorithms to
synthesize a shortest-path Steiner graph with smallest total
wire length on each layer of the 3D IC stack; this graph
determines locations of multiplexers and demultiplexers for
the gated bus architecture. The two algorithms include a
greedy heuristic that can handle large instances and a linear
programming relaxation and rounding method [15] that is
more accurate and suitable for solving cases with relatively
small scale. Overall, our method can reduce wire length by
up to 22% when compared to [16].

Problem Two: Given optimal (fixed, from Problem
One) locations of TSVs, construct a rectilinear shortest-
path Steiner Graph in each layer that minimizes the
total wire length subject to the existence of a layer-wise
rectilinear shortest path for each master-slave pair.
This is the minimal rectilinear shortest-path Steiner
graph (RSSG) problem, which was first considered in
[16].

PROBLEMTWO: APPROXIMATION ALGORITHMS
FOR GENERATING RECTILINEAR
A SHORTEST-PATH STEINER
GRAPH

Terminology

Literature


4-completion graph

4-completion graph
WANG, RENSHEN and CHENG, CHUNG-KUAN: Complexity of 3-D Floorplans by Analysis of Graph Cuboidal Dual Hardness p22. ACM Transactions on Design Automation of Electronic Systems, Vol. 15, No. 4, Article 33, Pub. date: Sept. 2010.

Terminology

Literature


adjacency graph

adjacent graph

adjacency graph
WANG, RENSHEN and CHENG, CHUNG-KUAN: Complexity of 3-D Floorplans by Analysis of Graph Cuboidal Dual Hardness p22. ACM Transactions on Design Automation of Electronic Systems, Vol. 15, No. 4, Article 33, Pub. date: Sept. 2010.

Terminology

Literature


architecture graph

architecture graph

Farnoosh Improving Reliability in Application-Specific 3D Network-on-Chip p6.pdf

Terminology

Literature


bipartite graph

bipartite graph

Jiang, Li et al: On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs p6 DAC ’13, May 29 - June 07 2013, Austin, TX, USA ...................

bipartite graph

C. Ferri, S. Reda, and R.I. Bahar, ―Parametric yield management for 3D ICs,‖ ACM Journal on Emerging Technologies in Computing Systems, vol. 4, Oct. 2008, pp. 1-22.

FERRI, CESARE; REDA, SHERIEF and BAHAR, R. IRIS: Parametric Yield Management for 3D ICs: Models and Strategies for Improvement p20 ACM Journal on Emerging Technologies in Computing Systems, Vol. V, No. N, April 2008

bipartite graph
Ferri, Cesare et al: Strategies for Improving the Parametric Yield and Profits of 3D ICs, ?2007 IEEE, p7

edge-weighted bipartite graph

Hasan, Yasmeen: POWER AWARE PHYSICAL MODEL FOR 3D ICs, 2006, p10

Hasan, Yasmeen: POWER AWARE PHYSICAL MODEL FOR 3D IC’S p10 International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011

Terminology

Literature


Carry generation graph

Terminology

Literature


Cayley graphs known as star graphs

Cayley graphs known as star graphs
Yeh VLSI layouts of complete graphs and star graphs p7

Yeh VLSI layouts of complete graphs and star graphs p7

complete graphs

Cayley graphs known as star graphs

star graphs

pancake graphs

Terminology

Literature


cell graph

cell graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


channel graphs

channel graph
Graph Models for Global Routing Grid Graph Nov 2002 p17.

channel graphs
Chattopadhyay, Subhomoy ; Bouldin, Donald W. and Dehkordi, Peyman H.: An Overview of Placement and Routing Algorithms for Multi-Chip Modules, Nov 1998, p43 ....................
When interconnect resistance becomes signi cant compared to the e ective resistance of the
driver, the interconnect delay of a multi-terminal net becomes a function of the topology of
the routing. One of the rst algorithms which attempted to optimize the topology for delay
was presented in [34]. The algorithm iteratively constructs a tree for a multi-terminal net, by
starting from a partially constructed tree (which is initially just the driver node), and connecting
it to a sink node. The connection path is found using the \A" search algorithm, which is guided
by a bene t value on each vertex in the routing graph based on estimates of the Elmore delay
to all sinks in the tree, and the total wire length of the tree. An advantage of this algorithm is
that it can be used on arbitrary routing graphs, so it can be used on channel graphs, or for area
routing in the presence of obstacles. Many other performance-driven algorithms are restricted
to the manhattan plane.

Terminology

Literature


circuit graph

circuit graph (synthesized and mapped circuit)

circuit graph

The circuit graph (synthesized and mapped circuit)

Banerjee, Kaustav; Souri, Shukri J.; Kapur, Pawan and Saraswat, Krishna C.: 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration, Proceedings of the IEEE, vol. 89, May. 2001, pp. 602-633. .....p 57 .

Banerjee, Kaustav; Souri, Shukri J.; Kapur, Pawan and Saraswat, Krishna C.: 3-D ICs A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration p32 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 5, MAY 2001

The circuit graph (synthesized and mapped circuit) is embedded
on a target graph which is planar (which corresponds to the physical substrate of the conventional single
Silicon substrate technology). However, with more than one Silicon layer available, the target graph is no
longer planar, and therefore placement and routing algorithms need to be suitably modified. Moreover, since
placement and routing information also affects synthesis algorithms, which in turn can affect the choice of
architectures, this modification needs to be propagated all the way to synthesis and architectural level.
Additionally, since 3-D ICs would likely involve SOI (silicon-on-insulator) type upper active layers, the
design process will need to address issues specific to SOI technology to realize significant performance
improvements [82], [83].

The circuit graph (synthesized and mapped circuit)

Souri, Shukri J: 3D ICs Interconnect Performance Modeling and Analysis, Ph.D. Dissertation Draft, Nov 2002, p123

The circuit graph (synthesized and mapped circuit) is embedded on a target graph which is planar (which corresponds to the physical substrate of the conventional single silicon substrate technology).

Terminology

Literature


coarse graphs

coarse graphs
Karypis, George and Kumar, Vipin: Multilevel k-way Hypergraph Partitioning p15.............

Terminology

Literature


Communication Graphs

inter layer communication graph

layer 1 communication graph layer 2 communication graph

Terminology

Literature

Terminology

Literature


Conflict Graph

conflict graph

conflict graph
Recski, Andras and Szeszler, David: 3-dimensional Routing, Aug 2008. p8.

As mentioned above, the second statement is a corollary of the first one. To prove the first
statement, we have to observe that a SALRP is trivially solvable on 2 layers if the increased
length n · sn is at least the number of nets and each row contains either one terminal or two
terminals belonging to the same net. From this we can obtain the necessary partition by edge-
coloring a suitably defined conflict graph (whose edges correspond to the nets). The coefficient of
3
2 comes from Shannon’s classic theorem [16] claiming that the chromatic index of a multigraph
is at most 3
2. Details can be found in [13].

However, if we break up each t-terminal net into t ? 1
terminal pairs then the construction of Theorem 5 works with the only difference being that
the maximum degree in the corresponding conflict graph, and thus the height of the obtained
routing is doubled.

The second statement is a corollary of the first one, using Theorem 7 and the above obser-
vation. The first statement is proved by a careful construction that again uses the edge-coloring
of a conflict graph (which is, in this case, bipartite) and a (2-dimensional) channel routing
algorithm of Recski and Strzyzewski [11]. Details can be found in [14].

resource conact graph
Definition . The resource conact graph G-(V. E) is a graph whose vertex set V = (u,. i = 1.2, . . . , n,,) is in one-to-one correspondence with the operations and whose edge set E = {(u;, u,) i. j = 1.2,. . . , n,,] denotes the conflicting operation pairs

Literature


Conflict-Net Graph

relaxed conflict-net (RCN) graph

Placement and Design Planning for 3D Integrated Circuits

Luo, Guojie: Placement and Design Planning for 3D Integrated Circuits PhD Thesis, 2011 p184

Conflict-Net Graph

We extended a metal wire layer assignment algorithm designed in [19] for die assignment in 3D placement. For a given legalized 3D placement, a conflict-net (CN) graph is created, as shown in Figure 13, where both the cells (netlist nodes) and the vias (TSVs) are the nodes of the CN graph. One via node is assigned for each net. There are two types of edges, net edges and conflicting edges. Within each net, all cells are connected to the via node by net edges in a star model. A conflict edge is created between cells that overlap with each other if they are placed on the same die.

We want to find a die assignment for each cell node in the graph so that the total cost, including edge costs and node costs, are minimized. Cost 0 is assigned to each net edge. If two cells connected by a conflicting edge are assigned to the same die, the cost of the conflicting edge is set to infinity; otherwise, the cost is set to 0. The cost of a via node is the height of that via, which represents the total TSV number in that net. The heights of the vias are determined by the dies of the cells that connect with them. The cost of a cell node j v is the thermal cost i , j t of assigning j v to die i, as in equation (21). The cost of a path is the sum of the edge costs and the node costs along that path.

The resulting graph is a directional acyclic graph. A dynamic programming optimization method can be used to find the optimal solution for each induced sub-tree of the graph in linear time. An algorithm that constructs a sequence of a maximal induced sub-tree from the CN graph is then used to cover a large portion of the original graph. It turns out that the average node number of the induced sub-trees can be as much as 40% to 50% of the total nodes in the graph. After the iterative optimization of the sub-trees, we can achieve a globally optimized solution. Please refer to [19] for the detailed algorithm to solve the die assignment problem with a CN graph.

Figure 13. Relaxed conflict-net graph

RCN graph
Cong, Jason: 3D IC Design Tools and Applications to Microarchitecture Exploration, 10/8/2007, p71 ....

Refinement through RCN graph

Layer Reassignment
through RCN Graph

RCN graph

Cong, Jason: Thermal-Aware 3D IC Physical Design and Architecture Exploration p56

Refinement through RCN graph

Layer Reassignment
through RCN Graph

RCN graph relaxed conflict-net (RCN) graph

Cong, Jason et al: Thermal-Aware 3D IC Placement Via Transformation p20 January 24, 2007
Moreover,
we proposed a novel relaxed conflict-net (RCN) graph-based layer
assignment method to further refine the 3D placements.
Compared to LST results, thermal-aware RCN graph-based
layer assignment algorithm (r = 10%) can further reduce the
maximum on-chip temperature by 37%, with only 6% TS via
number increase and 8% wirelength increase.

RCN graph relaxed conflict-net (RCN) graph

Luo, Guojie: Placement and Design Planning for 3D Integrated Circuits, 2011, PhD dissertation, p184 ............... 26

Thermal-Aware 3D IC Placement Via Transformation

Cong, Jason et al: Thermal-Aware 3D IC Placement Via Transformation, 2006 p6 .......................

Given a hypergraph H = (V, E), device layer number K, and a 2D placement P, the thermal-aware 3D placement transformation problem is to assign a position (xi, yi, zi) to every cell vi, so that the total wirelength and the TS via number are minimized, subject to constraints such as non-overlap constraints, temperature constraints, etc.

I transformation techniques, from a 2D placement to a 3D placement

  • local stacking transformation (LST),
  • folding-2, folding-4 and
  • window-based stacking/folding transformation

II layer assignment method

relaxed conflict-net (RCN) graph-based layer assignment method

Figure RCN Relaxed Conflict-Net Graph

We extended a metal wire layer assignment algorithm proposed in [6] for cell layer assignment in 3D placement. For a given legalized 3D placement, a conflict-net (CN) graph is created, as shown in Figure RCN above, where both the cells and the vias are nodes. One via node is assigned for each net. There are two types of edges, net edges and conflicting edges. Within each net, all cells are connected to the via node by net edges in star mode. A conflict edge is created between cells that overlap with each other if they are placed in the same layer

We want to find a layer assignment of each cell node in the graph so that the total cost, including edge costs and node costs are minimized. Cost 0 is assigned for all net edges. If two cells connecting by a conflicting edge are assigned to the same layer, the cost of the conflicting edge is set to infinity, otherwise, the cost is set to 0. The cost of a via node is the height of that via, which represents the total TS via number in that net. The heights of the vias are determined by the layers of the cells connecting with them. The cost of a cell node vj is the thermal cost ti,j of assigning vj to layer i. The cost of a path is the sum of the edge costs and the node costs along that path.

The resulting graph is a directional acyclic graph. A dynamic programming optimization method can be used to find the optimal solution for each induced sub-tree of the graph in linear time. An algorithm that constructs a sequence of maximal induced sub-tree from the CN graph is then used to cover a large portion of the original graph. It turns out that average node number of the induced sub-trees can be as many as 40%-50% of the total nodes in the graph. After the iterative optimization of the sub-trees, we can achieve a globally optimized solution. Please refer to [6] for the detailed algorithm to solve the layer assignment problem with CN graph.

Terminology

Terminology

Literature


connection graph

connection graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

connection graph

Lu, CHAO-HUNG et al: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits, JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 27, 287-302 (2011), p16

LU, CHAO-HUNG; CHEN, HUNG-MING AND LIU, CHIEN-NAN JIMMY: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits p16 JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 27, 287-302 (2011) 287

LU Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits p16

FCG (Floorplan Connection Graph)

FCG (Floorplan Connection Graph)
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

floor connection graph / Floorplan Connection Graph
Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8
Jacob R. Minz, Somaskanda Thyagaraja, and Sung Kyu Lim
School of Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA
jrminz@ece.gatech.edu

net connection graph

Terminology

Literature


connectivity graphs

connectivity graphs / channel connectivity graph
Graph Models for Global Routing Grid Graph Nov 2002 p17.

connectivity graphs

Papa Hypergraph Partitioning and Clustering p38

connectivity graphs

Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

connectivity graphs
Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.

As an example, the connectivity graphs before and after ROUTER-MERGING procedure
for the example of Fig. 8.3a are shown in Fig. 8.7a, b. It is shown that after
router merging, the network resources are reduced from four routers to three routers
and the total power consumption is reduced as well.

Terminology

Literature


core graph

core graph

Farnoosh Improving Reliability in Application-Specific 3D Network-on-Chip p6.pdf

core graph
Zhou, Pingqiang: Interconnect Design Techniques for Multicore and 3D Integrated Circuits PhD Thesis August, 2012 p135

?????????????????????

Terminology

Literature


Routing Cost Graph (RCG)

Routing Cost Graph (RCG)
Routing Cost Graph (RCG)
router cost graph

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

The details of RRRM are described in Algorithm 1. RRRM takes a communication
demand graph (CDG) and an evaluation function as inputs and generates an optimized
network architecture as output. It starts with initializing a network topology
by a simple router allocation and flow routing scheme. Then it uses a procedure of
rip-up and rerouting flows to refine and optimize the network topology. After that, a
router merging step is done to further optimize the topology to obtain the best result.

In the initialization, every flow is routed using its own network. To construct the
initial network topology, router allocation is considered at each core. A router is allocated
to a core if there are more than two flows coming into that core or more than
two flows going out from that core. After router allocation, a Routing Cost Graph
(RCG) is generated (Algorithm 1 line 2). RCG is a very important graph used in the
whole rip-up and reroute procedure of RRRM algorithm.

Definition 2 The RCG( R, E) is a weighted directed complete graph (a full-mesh)
with each vertex ri ∈ R represents a router, and each directed edge eij = ( ri, rj) ∈ E
from ri to rj corresponds to a connection from ri to rj. A weight w( eij) is attached to
each edge which represents the incremental cost of routing a flow f through eij.

Please note that RCG does not represent the actual physical connectivity between
routers and its edge weights change during the whole RIPUP-REROUTE
procedure for different flows. Also, the actual physical connectivity between the
routers is established during RIPUP-REROUTE procedure, which is explained in
the following sections.

Before RIPUP-REROUTE, initial network topology is constructed using InitialNetworkConstruction()
procedure. Each flow ek = ( sk, dk) in the CDG is routed
using a direct connection from router rsk to router rdk , where ri is the router that
core i connects to, and the path is saved in path( ek). Multicast flows are routed as
a sequence of unicast flows from the source to each of their destinations. If either
core i is not connected to any router, a direct connection is added between core i and
the other router if any. The links and router ports are configured and saved. If a connection
between routers can not meet the delay constraints, its corresponding edge
weight in RCG is set to infinity. This can be used to guide the rerouting of the flows
to use other valid links instead of this one in the RIPUP-REROUTE procedure.

As an example, after initial network construction, the connectivity of routers for
the example shown in Fig. 8.3a is shown in Fig. 8.6a. In this initial solution, each
core is connected to a dedicated router.

Fig. 8.6 Illustration of the RIPUP-REROUTE procedure. a Initial connectivity. b RCG. c MRG.
d MRTree. e Connectivity before reroute e7. f Connectivity after reroute e7

Once the initial network is constructed and the initial flow routing is done, the key
procedure of the algorithm—RIPUP-REROUTE procedure is invoked to route flows
and find optimized network topology. The details are described in Algorithm 2.

In the RIPUP-REROUTE, each multicast routing step is formulated as a minimum
directed spanning tree problem. Two important graphs, Multicast Routing Graph (MRG) and Multicast Routing Tree (MRTree), are used to help facilitate the
rip-up and rerouting procedure. They are defined as follows.

Routing Cost Graph (RCG)
Routing Cost Graph (RCG)
Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.
In the initialization, every flow is routed using its own network. To construct the
initial network topology, router allocation is considered at each core. A router is allocated
to a core if there are more than two flows coming into that core or more than
two flows going out from that core. After router allocation, a Routing Cost Graph
(RCG) is generated (Algorithm 1 line 2). RCG is a very important graph used in the
whole rip-up and reroute procedure of RRRM algorithm.
Definition 2 The RCG( R, E) is a weighted directed complete graph (a full-mesh)
with each vertex ri ∈ R represents a router, and each directed edge eij = ( ri, rj) ∈ E
from ri to rj corresponds to a connection from ri to rj. A weight w( eij) is attached to
each edge which represents the incremental cost of routing a flow f through eij.
Please note that RCG does not represent the actual physical connectivity between
routers and its edge weights change during the whole RIPUP-REROUTE
procedure for different flows. Also, the actual physical connectivity between the
routers is established during RIPUP-REROUTE procedure, which is explained in
the following sections.
When a flow is rip-up and rerouted, its current path is deleted and the links and
router ports resources it occupies are released (line 3). Then based on the current
network connectivity and resources occupation, the RCG related to this flow is built
and the weights of all edges in RCG are updated (line 4). In particular, for every pair
of routers in RCG, the cost of this flow using those routers and the link connecting
them is evaluated. This cost depends on the sizes of the routers, the traffic already
routed on the routers and the connectivity of the routers to other routers. It also
depends on whether an existing physical link will be used or a new physical link
needs to be installed. If there are already router ports and links that can support the
traffic, the marginal cost of reusing those resources is calculated. Otherwise, the cost
of opening new router ports and installing new physical links to support the traffic
is calculated. The cost is assigned as edge weight to the edge connecting the pair of
routers in RCG. If the physical links used to connect the routers can not satisfy the
delay constraints, a weight of infinity is assigned to the corresponding edges in RCG.
Once the RCG is constructed, the multicast routing graph (MRG) for the flow is
generated from RCG (line 5). MRG is build by including every source and destination
router of the flow as its nodes. For each pair of the nodes in MRG, the least cost
directed path with least power consumption on RCG is found for the corresponding
routers using Floyd-Warshall’s all pair shortest path algorithm and the cost is
assigned as edge weight to the edge connecting the two nodes in MRG. Then the
Chu-Liu/Edmonds algorithm [36, 37] is used to find the rooted directed minimum
spanning tree of MRG with the source router as root. A rooted directed spanning
tree of a graph is defined as a graph which connects, without any cycle, all n nodes
in the graph with n ? 1 arcs such that the sum of the weight of all the arcs is minimized.
Each node, except the root, has one and only one incoming arc. This directed
minimum spanning tree is obtained as the multicast routing tree (MRTree) so that
the routes of the multicast flow follows the structure of this tree. The details of Chu-
Liu/Edmonds Algorithm is summarized in Algorithm 3. The multicast routing for

Terminology

Literature


Communication Demand Graph (CDG)

communication demand graph
Seiculescu Chapter 9 3D Network on Chip Topology Synthesis Designing Custom Topologies for Chip Stacks p31.pdf

communication demand graph
Seiculescu SunFloor_3D_a_Tool_for_Networks_02.2_2 p6.pdf

communication demand graph

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25

3D Networks-on-Chip Synthesis

Given floorplanning information, the 3D-NoC synthesis step then proceeds to synthesize a 3D-NoC architecture that is optimized for the given specification and floorplan. Consider Fig. 8.3a that depicts a small illustrative example. Figure 8.3a only shows the portion of the input specification that corresponds to the networkattached modules and their traffic flows. It utilizes a graph representation called a communication demand graph, which is discussed in more details in Sect. 8.4. Multicast traffic flows are represented with directed hyperedges, which are shown graphically in Fig. 8.3a as a bundle of directed edges in a shaded region. For example, the traffic flow from v4 to v2, v5 and v6 is a multicast flow.

An example 3D floorplan is shown in Fig. 8.3b. The unlabeled rectangles represent modules that are not attached to the network and connected by conventional wiring. The communication demand graph with the floorplan positions annotated is illustrated in Fig. 8.3c. Figure 8.3d, e show two examples of synthesized 3D network topologies.

Fig. 8.3 Illustration of the 3D-NoC synthesis problem. a Example. b Floorplan. c CDG. d One architecture. e Alternative architecture

The input to our 3D-NoC synthesis problem is a communication demand graph (CDG), defined as follows:

Definition 1 A communication demand graph (CDG) is an annotated directed hypergraph H( V, E, π, λ), where each node vi ∈ V corresponds to a module, and each directed hyperedge ek = s → D ∈ E represents a traffic flow from source s ∈ V to one or more destinations D = {d1, d2,…}, D ? V. The position of each node vi is given by π( vi) = ( xi, yi). The data rate requirement for each communication flow ek is given by λ( ek ).

In general, traffic flows can either be unicast or multicast flows. Multicast flows are flows with |D|>1. For example, in Fig. 8.3c, e7 corresponds to a multicast flow from source v4 to destinations v2, v5 and v6.

Based on the optimization goals and cost functions specified by the user, the output of our 3D-NoC architecture synthesis problem is an optimized custom network topology with pre-determined routes for the specified traffic flows on the network such that the data rate requirements are satisfied. For example, Fig. 8.3d, e show two different topologies for the CDG shown in Fig. 8.3c.

communication demand graph
Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.

It utilizes a graph representation called
a communication demand graph, which is discussed in more details in Sect. 8.4.
Multicast traffic flows are represented with directed hyperedges, which are shown
graphically in Fig. 8.3a as a bundle of directed edges in a shaded region. For example,
the traffic flow from v4 to v2, v5 and v6 is a multicast flow.

An example 3D floorplan is shown in Fig. 8.3b. The unlabeled rectangles represent
modules that are not attached to the network and connected by conventional
wiring. The communication demand graph with the floorplan positions annotated
is illustrated in Fig. 8.3c. Figure 8.3d, e show two examples of synthesized 3D network
topologies.

The input to our 3D-NoC synthesis problem is a communication demand graph
(CDG), defined as follows:
Definition 1 A communication demand graph (CDG) is an annotated directed
hypergraph H( V, E, π, λ), where each node vi ∈ V corresponds to a module, and
each directed hyperedge ek = s → D ∈ E represents a traffic flow from source s ∈ V
to one or more destinations D = {d1, d2,…}, D ? V. The position of each node vi is
given by π( vi) = ( xi, yi). The data rate requirement for each communication flow ek
is given by λ( ek ).
In general, traffic flows can either be unicast or multicast flows. Multicast flows
are flows with |D|>1. For example, in Fig. 8.3c, e7 corresponds to a multicast flow
from source v4 to destinations v2, v5 and v6.
Based on the optimization goals and cost functions specified by the user, the output
of our 3D-NoC architecture synthesis problem is an optimized custom network
topology with pre-determined routes for the specified traffic flows on the network
such that the data rate requirements are satisfied. For example, Fig. 8.3d, e show
two different topologies for the CDG shown in Fig. 8.3c.

Terminology

Literature


dense graph

Terminology

Literature


Dependency Graph
Dependency graph is a directed graph representing inter-dependencies of several parameters. Order of dependency identified in such graphs support in characterizing each of the models at different level. This characterization also supports the propagation from one level to the other. Nevertheless, dependencies are also possible between parameters in the same level which leads to encapsulation of dependent parameters in an abstraction level.

Parameter dependency graph

Parameter dependency graph

Parameter dependency graph

VISWANATHAN, Vijayaragavan: Modeling and design of 3D Imager IC PhD Thesis Sept 2012 p176

Formulation

We know the design variables, input and output of a model. But there is a lack of methodology to identify interdependencies between design variable and communicating between different variables. So we propose the parameter dependency graph to overcome this problem. Dependency graph is a directed graph representing inter-dependencies of several parameters. Order of dependency identified in such graphs support in characterizing each of the models at different level. This characterization also supports the propagation from one level to the other. Nevertheless, dependencies are also possible between parameters in the same level which leads to encapsulation of dependent parameters in an abstraction level.

Figure 2.7 Parameter dependency graph

Figure 2.7 represents a simple dependency graph with several nodes and their dependency to other nodes represented with arcs. A-H are the parameters of the system. Two aspects have to be clearly defined: first the boundary between abstraction levels, and second the relationship between parameters at each level and through the levels. For example, it is possible to encapsulate the parameters as model 0 and model 1 or both of them together. For example: ‘B’ depends on both ‘D’ and ‘F’. Two different models modeling their dependency are possible or modeling them as a single model taking all the dependencies in a single step. These possibilities are chosen by the designer based on known constraints (e.g. complexity, simulation time, tools etc). To illustrate the above methodology image sensor application is taken into account.

The system is characterized by the following performance metrics: maximum frames per second (FPS), dynamic range (DR), signal-to-noise ratio (SNR), quantum efficiency, conversion gain, well capacity, noise, power consumption etc. We have limited the description at the system level to three main characteristics such as FPS, DR, SNR to demonstrate the approach. Each of these metrics give rise to individual dependency graphs. However, there are also cases where some parameters are inter-dependent for one or more performances to be achieved (e.g. Integration time (Tintegration)) which is detailed in the next section.

Frames per second (FPS) dependency graph

Frames per second (FPS) dependency graph
VISWANATHAN, Vijayaragavan: Modeling and design of 3D Imager IC PhD Thesis Sept 2012 p176

The first step in identifying the parameter dependency is to decompose the system into subblocks. Later, all the parameters which are related to FPS of each sub-block are identified with their relationship. The parameters which are considered to achieve the required FPS (performance) are individual timing parameters illustrated in Figure 2.8. The critical timing of the system is set by the timing of the pixel matrix size. The pixel matrix timing depends on parameters such as individual matrix row Treset, Tselect and Tintegration time where Treset, Tselect are the reset and select windows for resetting a pixel to the supply voltage and selecting the available output voltage from the discharge curve. Tintegration is the time available between the reset and select timing.

Along with the main timing parameters, there are other considerations such as column delay (Tcoldelay), which depends on the area of the 1 Mega pixel array to route the readout wire to the output pin of the pixel matrix. Trowdelay will take care of the delay which is maintained between each row to initiate the reset and select signal. All these parameters are related to the sensor block. Other timing parameters which must be considered for other blocks such as Tadc, Tcds can also be identified with their own parameter dependency graph in the same manner. The current work concentrates on the pixel matrix.
Figure 2.8 FPS dependency graph
Parameters which are related to area are indicated in rectangular box which is an environment related parameter (e.g area depends on technology). Hexagonal box represents the photocurrent available from the input light. Timing related performance (FPS ) and dependent parameters are in circular box.

Dynamic Range (DR) dependency grap

Dynamic Range (D.R) dependency graph
VISWANATHAN, Vijayaragavan: Modeling and design of 3D Imager IC PhD Thesis Sept 2012 p176
The main parameters which are considered to play a role in achieving the required dynamic range are the maximum photocurrent (Imax) and minimum photocurrent (Imin) of the pixel photodiode. Indeed, the dynamic range is given by [8]

-- (2.1)
Where Qmax is the maximum well capacity, Idark is the dark current, and σr 2 is the read noise power.
D.R depends on integration time parameter. FPS also depends on integration time. So this parameter has to take a value which will satisfy both FPS and D.R performances. Dark current depends on the area of the pixel and the temperature of the chip. These parameter dependencies are shown in Figure 2.9.
Figure 2.9 Dynamic range dependency graph

Signal to Noise Ratio (SNR) dependency graph

Signal to Noise Ratio (SNR) dependency graph
VISWANATHAN, Vijayaragavan: Modeling and design of 3D Imager IC PhD Thesis Sept 2012 p176

SNR dependency graph is depicted in Fig.7. SNR is given by[5]

-- (2.2)
where Iph is the signal available from the input picture. Idark the dark current and σr 2 is the read noise power.
SNR depends on various other blocks (e.g. ADC) other than pixel matrix. SNR performance for the pixel matrix defines the required output voltage and the possible noise which the block could have due to readout noise, temperature. The required voltage due to the SNR specification imposes a constraint for the range of Tintegration possible due to the FPS performance.
Figure 2.10 SNR dependency graph

channel dependency graph

channel dependency graph
Farnoosh Improving Reliability in Application-Specific 3D Network-on-Chip p6.pdf

channel dependency graph / extended channel dependency graph

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25
The second method is Virtual Channels
insertion. As shown in [46], a necessary and sufficient condition for deadlock-free
routing is the absence of cycles in a channel dependency graph.

channel dependency graph

channel dependency graph
Yan, Shan and Lin, Bill: Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures Nov 2010 p25.
The first method is Statically Scheduled Routing. For our NoC solutions, the required
data rates are specified and the routes are fixed. In this setting, data transfers
can be statically scheduled along the pre-determined paths with resource reservations
to ensure deadlock-free routing [44, 45]. The second method is Virtual Channels
insertion. As shown in [46], a necessary and sufficient condition for deadlock-free
routing is the absence of cycles in a channel dependency graph. In particular, we use
an extended channel dependency graph construction to find resource dependencies
between multicast trees3 and break the cycles by splitting a channel into two virtual
channels (or by adding another virtual channel if the physical channel has already
been split). The added virtual channels are implemented in the corresponding routers.
We applied this method into our NoC synthesis procedure and we have found
that virtual channels are rarely needed to resolve deadlocks in practice for custom
networks. In all the benchmarks that we tested in Sect. 8.8, no deadlocks were found
in the synthesized solutions. Therefore, we did not need to add any virtual channel.

extended channel dependency graph

3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems
Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25
In particular, we use
an extended channel dependency graph construction to find resource dependencies
between multicast trees3 and break the cycles by splitting a channel into two virtual
channels (or by adding another virtual channel if the physical channel has already
been split). The added virtual channels are implemented in the corresponding routers.
We applied this method into our NoC synthesis procedure and we have found
that virtual channels are rarely needed to resolve deadlocks in practice for custom
networks.

Terminology

Literature


directed acyclic graph

directed acyclic graph
B. Goplen and S. Sapatnekar, ―Placement of 3D ICs with thermal and interlayer via considerations,‖ Proceedings of the 44th Annual Conference on Design Automation (DAC), 2007, p. 626.

directed acyclic graph
Hamedani, Parisa Khadem et al: Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip p8 Nov 2011

Terminology

Literature


dual graph

dual graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


floorplan graph

floorplan graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


Flow Graph (DFG)

flow graph

flow graph

Jiang, Li et al: On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs p6 DAC ’13, May 29 - June 07 2013, Austin, TX, USA ...................

flow graph

Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8........................
Each edge in this flow graph is assigned
a capacity and cost value. We assign a capacity of 40 and cost
of 0 for every waveguide-to-sink edge because a maximum of
40 nets can use the waveguide and no waveguide costs different
from another. The minimum length of nets considered for optical
routing is 4 because it needs to utilize all edges of its waveguide

flow graph
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference

Three-Dimensional (3D) Chip Multiprocessor (CMP) Architecture
LI, JIAYIN et al: Thermal-Aware Task Scheduling in 3D Chip Multiprocessor with Real-Time Constrained Workloads, ACM Transactions on Embedded Computing Systems, Vol. 12, No. 2, Article 24, Publication date: February 2013., p22 ..............

Data-Flow Graph (DFG)

Data-Flow Graph (DFG)
De Micheli, Giovani: Synthesis And Optimization Of Digital Circuits, April 2005, p586 .................. 78

Data-flow graphs represent operations and data dependencies. Let the number of operations be n,,. A data-flow graph Gd(V, E) is a directed graph whose vertex set V = {ui; i = 1.2, . . . , n,,) is in one-to-one correspondence with the set of tasks. We assume here that operations require one or more operands and yield one or more results (e.g., an addition with two addends yielding a result and an overflow flag). The directed edge set E = [(ui, u,); i , j = 1.2, . . . ,naps) is in correspondence with the transfer of data from an operation to another one. Data-flow graphs can be extended by adding other types of dependencies, such as task serialization, that are represented by additional directed edges.

The data-flow graph model implicitly assumes the existence of variables (or carriers), whose values store the information required and generated by the operations. Each variable has a lifetime that is the interval from its birth to its death, where the former is the time at which the value is generated as an output of an operation and the latter is the latest time at which the variable is referenced as an input to an operation. The model assumes that the values are preserved during their lifetime, i.e., that some sort of storage (registers in case of synchronous implementations) is provided.

Data-Flow Graph (DFG)
Fang A Three-Tier Asynchronous FPGA p8.pdf

Data-Flow Graph (DFG)

LI, JIAYIN et al: Thermal-Aware Task Scheduling in 3D Chip Multiprocessor with Real-Time Constrained Workloads, ACM Transactions on Embedded Computing Systems, Vol. 12, No. 2, Article 24, Publication date: February 2013., p22 .............. 6

A Data-Flow Graph (DFG) is used to model an embedded system application. A DFG typically consists of a set of vertices V, each of which represents a task in the application, and a set of edges E, showing the dependencies among the tasks. The edge set
E contains edges eij for each task vi ∈ V that task vj ∈ V depends on. The weight of a vertex vi represents the task type of task i. In our model, the number of tasks may be larger than the number of task types. And the tasks with the same task type have
the same execution time. Also the weight of an edge eij means the size of data which is produced by vi and required by vj .

We use a cyclic DFG to represent a loop of an application. In a cyclic DFG, a delay function d(eij ) defines the number of delays for edge eij . For example, assuming d(eab) = 1 is the delay function of the edge from task a to b, which means the task b in the ith iteration depends on the task a in the (i ? 1)th iteration. In a cyclic DFG, edges without delay represent the intra-iteration data dependencies, while the edges with delays represent the inter-iteration dependencies. An example of a cyclic DFG is shown in Figure xxx where one delay is denoted as a bar.

Fig. xxx. (a) The DFG. (b) The static DAG.

There is a realtime constraint L, which is the deadline of finishing one period of the application. To generate a schedule of tasks in a loop, we use the static direct acyclic graph (DAG). A static DAG is a repeated pattern of an execution of the corresponding loop. For a given cyclic DFG, a static DAG can be obtained by removing all edges with delays.

Retiming is a scheduling technique for cyclic DFGs considering inter-iteration dependencies. Retiming can optimize the cycle period of a cyclic DFG by distributing the delays evenly. For a given cyclic DFG G, the retiming function r(G) is a function from the vertices set V to integers. For a vertex ui of G, r(ui) defines the number of delays drawn from each of the incoming edges of node ui and pushed to all of the outgoing edges. Let a cyclic DFG Gr be the cyclic DFG retimed by r(G), then for a edge eij , dr(eij ) = d(eij ) +r(vi) ?r(vj ), where dr(e) is the new delay function of edge eij after retiming and d(eij ) is the original delay function.

Control / Data Flow Graphs

Control / Data-Flow Graph (CDFG)
De Micheli, Giovani: Synthesis And Optimization Of Digital Circuits, April 2005, p586 .................. 78

Control-flow information, related to branching (or conditiona0 and iteration (or loop) constructs, can also be represented graphically. Many different models have been proposed to represent controUdata-&w graphs (CDFGs) [5, 17,231. The simplest approach is to extend further data-flow graphs by introducing branching vertices that represent operations that evaluate conditional clauses. A branching vertex is the tail of a set of alternative paths, corresponding to the possible branches. Iteration can be modeled as a branch based on the iteration exit condition. The corresponding vertex is the tail of two edges, one modeling the exit hom the loop and the other the return to the first operation in the loop.

network flow graph

network flow graph
Zhou, Lili; Wakayama, Cherry and Shi, C.-J. Richard: CASCADE A Standard Super-Cell Design Methodology with Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large Scale Integrated Circuits p11. 2006

signal flow graph

signal flow graph

SULE, AMBARISH MUKUND. Design of Pipeline Fast Fourier Transform Processors using 3 Dimensional Integrated Circuit Technology, 2007 PhD Thesis p125

application(s) task flow graph

application(s) task flow graph
Bahirat, Shirish and Pasricha, Sudeep: 3D-HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific 3D Network-On-Chip Architectures p8 Jan 2014
In this first step, we perform task to core mapping, scheduling, and link bandwidth estimation. The step involves mapping of n tasks to m heterogeneous cores for the given application(s) task flow graph. We perform task execution-time estimation as well as estimation of inter-core data transfers using an instruction simulator [35]. We implement a genetic algorithm (GA) [36] to accomplish task to core mapping. The GA chromosome consists of possible mappings for the given application tasks to available cores, as well as virtual link type (electrical or photonic) between cores to satisfy bandwidth and latency constraints at a coarse granularity. The specific parameters used in the GA implementation are described in detail in the experimental setup section (6.1). The GA cost function represents overall communication power and the GA attempts to create a mapping and task schedules to minimize this power.

Fig 7. Communication trace graph for multiple parallel applications (a) inter layer communication graph (b) layer 1 communication graph (c) layer 2 communication graph.

Fig. 7(a) shows the enhanced communication trace graph (CTG) of three office applications running in parallel, which is generated after running the GA algorithm and performing core to die mapping. Note the initial link selection that allocates some flows to electrical links and others to FSNPI links. Fig. 7(b) shows the floorplanning solution for this CTG graph for layer 1 and Fig. 7(c) shows the floorplanning solution for layer 2, where each application is depicted by a separate color. During floorplanning, we set weighed communication power constant ∝ and link distance constant ?? values at 0.5 each based on empirical analysis. We utilized a public domain GeoSteiner3.1 Steiner Tree solver [40] to generate the MEST and MRST networks and utilized the lp_solve optimizer [41] to solve the Mixed Integer Linear Programming (MILP). We set weight values for ∝ to 0.38 and ?? to 0.62, during MEST generation for electrical links and MRST generation for FSNPI links. We created clusters utilizing a 0.44 connection strength threshold to optimize electrical intra-cluster short distance communication and inter-cluster transmission using FSNPI links. Based on our analysis, we set a normalized Mth threshold of 39 bytes in PCR regions such that communication messages less than the size of Mth transverse through electrical links and the messages that exceed the size of the threshold travel through FSNPI links. We combined the various components of our 3D-HELIX framework using a python scripting interface [42].

test flow graph

test flow graph

SenGupta, Breeta; and Larsson, Erik: Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias p4 SWEDISH SYSTEM ON CHIP CONFERENCE, MAY 2011

Terminology

Literature


Full adder graphs

Full adder graphs

Imeson, Frank et al: Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation, 22nd USENIX Security Symposium. August 14–16, 2013 ? Washington, D.C., USA, p17

Imeson, Frank et al: Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation, 22nd USENIX Security Symposium. August 14–16, 2013 ? Washington, D.C., USA, p43

Terminology

Literature


graph embedding problem

graph embedding problem

Banerjee, Kaustav; Souri, Shukri J.; Kapur, Pawan and Saraswat, Krishna C.: 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration, Proceedings of the IEEE, vol. 89, May. 2001, pp. 602-633. .....p 57 .

Banerjee, Kaustav; Souri, Shukri J.; Kapur, Pawan and Saraswat, Krishna C.: 3-D ICs A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration p32 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 5, MAY 2001

At an abstract level, physical design (placement and routing) can
be viewed as a graph embedding problem.

graph embedding problem

Souri, Shukri J: 3D ICs Interconnect Performance Modeling and Analysis, Ph.D. Dissertation Draft, Nov 2002, p123

At an abstract level, physical design (placement and routing) can be viewed as a graph embedding problem.

Terminology

Literature


Graph Theory and IC Design

graph

tree

Graphs

4completion_graph

adjacency_graph

architecture_graph

bipartite_graph

carry_generation_graph

Cayley_star_graph

cell_graph

channel_graphs

circuit_graph

coarse_graph

communication_graph

conflict_graph

connection_graph

connectivity_graph

constraint_graph

core_graph

cost_graph

demand_ggraph

dense_graph

dependency_graph

directed_acyclic_graph

dual_graph

floorplan_graph

flow_graph

full_adder_graph

graph_embedding

graph_general

grid_lattice_graph

impedance_graph

intersection_graph

lattice_graph

layer_graph

logic_graph

multi_graph

multilevel_graph

nearest_neighbor_graph

netlist_graph

network_graph

optimization_graph

pancake_graph

parallel_prefix_graph

partitioning_graph

path_graph

platform_graph

quotient_graph

random graph

rectilinear_graph

relation_graph

residual_graph

resource_graph

routing_graph

sequencing_graph

shuffle_exchange_graph

spanning_graph

Steiner_graph

structured_directed_graph

Tanner_graph

task_graph

temperature_graph

tile_graph

timing_graph

trace_graph

transition_closure_graph

My current research and authoring are focusing on hypergraph applications in VLSI design. A survey will be published pretty soon. Updated on 2014-7-4.

>>>hypergraph

hypergraph_vlsi.docx

hypergraph_vlsi_A2K.htm

hypergraph_vlsi_L2Z.htm

Trees

3dtre

a_tree

arborescence_tree

binary_tree

buffered_tree

butterfly_fat_tree

carry_generation_tree

clock_tree

complete_tree

directed_tree

fat_tree

full_tree

global_tree

h_x_trees

inter_block_abstract_tree

interconnect_tree

load_matched_tree

local_tree

lt_tree

minimum_cost_tree

multi_crossing_tree

multicast_tree

multilevel_tree

net_subtree

o_tree

p_tree

parallel_prefix_tree

partition_tree

power_tree

rctree

rectilinear_tree

redundant_tree

rlctrees

routing_tree

search_tree

slicing_tree

spanning_tree

Steiner_tree

vertex_disjoint_tree

Wallace_tree

xor_tree

Grid

Path

Clique


impedance graph

rectilinear impedance graph

rectilinear impedance graph
VanAckern, Gary: Design Guide for CMOS Process On-Chip 3D Inductors using Thru-Wafer Vias, PhD thesis, May 2011. p143
A rectilinear impedance graph is shown in Figure A.2. Here it is clear that the xaxis
is real and spans from 0 impedance to ∞, while the y-axis is imaginary and spans?j.
Figure A.2 Rectilinear Impedance Plane (Complex)
The Smith Chart is a transformation of the rectilinear impedance graph into the
polar plane by stretching the two complex half-planes to connection as shown in Figure
A.3

Terminology

Literature


intersection graph

intersection graph

intersection graph

Knechtel, Johann; Markov, Igor L. and Lienig, Jens: Assembling 2D Blocks into 3D Chips p8 ISPD’11, March 27–30, 2011, Santa Barbara, California, USA. ..................

Relevant results from graph theory. Imai and Asano [12] conducted a study on intersections of axis-aligned rectangles in the plane. First, Imai and Asano proved that n axis-aligned rectangles (e.g., bounding boxes) have a single non-empty n-way intersection iff each pair of these rectangles overlap. Thus, rather than check all subsets of overlapping bounding boxes, we may search for cliques in a suitably defined intersection graph. This graph represents bounding boxes by vertices and connects overlapping boxes by edges. Second, they provided an O(n log n)-time algorithm for finding the maximum clique in intersection graphs with n vertices, even though this problem is NP-hard for general graphs [26]. In our context, however, a single clique is insufficient — we seek to partition the edges in the intersection graph into a small set of cliques, which is the NP-complete clique cover problem [6] (for interval graphs, this problem can be solved in polynomial time [8]).

Results by Imai and Asano imply that the largest possible net clusters correspond to maximum cliques in the intersection graph. However, in our context, large cliques may exceed the capacity of the largest available TSV island. Several TSV islands can be combined to implement such a clique, but this increases routing congestion and mechanical stress, and aggravates signal integrity problems [7, 31]. Another problem with using large cliques is that corresponding (small) intersections of net bounding boxes may not include any aligned deadspace, preventing the insertion of a TSV island. On the other hand, a smaller clique would imply fewer bounding boxes and a larger intersection that is more likely to admit TSV-island insertion. Thus, we need to develop our own algorithm for identifying clique covers. Our algorithm is presented next.

Infrastructure used by our clustering algorithm. Initially, all blocks are projected onto the virtual die. In order to identify clusters (cliques) of appropriate size, a uniform clustering grid G is constructed on the virtual die (Figure 5). A clustering grid links each net n to each tile  2 G covered by its net bounding box bbn, and thus results in size-limited (appropriate) clusters. Cluster regions must be close to aligned deadspace, otherwise TSV islands cannot be inserted. To calculate the amount of aligned deadspace, a nonuniform grid is constructed. Grid lines are drawn through the four edges of each block. Grid tiles not covered by blocks define deadspace. Formblocks overlapping with a particular tile , deadspace detection runs in O(m2) time [29], which is not prohibitively expensive because typically m < 50. In the uniform clustering grid, tiles with insufficient aligned deadspace (< d min) are marked as obstructed. Key parameters used in our algorithm are defined in Table 1 along with their values.
Figure 5: Uniform clustering grid G on virtual die. (a) Projected blocks from all active layers. We calculate the per-tile ratio of aligned deadspace, illustrated in the last row. (b) Projected net bounding boxes. According to their bounding boxes, we link nets to covered tiles. The intersection of net bounding boxes must be explicitly checked during clustering. In tile (1; 2), e.g., net bounding boxes bbn1 , bbn3 and bbn3 , bbn4 do not overlap pairwise, but all four nets are linked to the tile.

Channel Intersection Graph

Channel Intersection Graph / Extended channel intersection graph

Graph Models for Global Routing Grid Graph Nov 2002 p17.

Net Intersection Graph

Terminology

Net Intersection Graph

Cong, Jason; Labio, Wilburt and Shivakumar , Narayanan: Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation 1994 ACM 0-89791-690-5/94/0011/0056 p7

Net Intersection Graph (NIG): NIG =(V(NIG),
E(NIG)), where each node in V(NIG) represents a
net ni (1 ￡ i ￡ q), and there is an edge in E(NIG)
between ni and nj iff ni ? nj 1 f (i.e the two nets
share common modules). Note that NIG is a graph
instead of a hypergraph (see Fig. 1 (c)).

Literature


lattice graph

lattice graph

planar lattice graph

planar edge-weighted lattice graph

Terminology

Literature


layer graph

layer graph / virtual layer graph
Deza Global Routing in VLSI Design Algorithms, Theory, and Computational Practice p25.pdf

virtual layer graph

layer graph / virtual layer graph
DICKSON, CHRIS: Global Routing in VLSI Algorithms, Theory, and Computation Master Thesis, May 2007 p76

multilayer graphs
Trik An Overview of through-Silicon via – based Three Dimensional integrated Circuits (3D IC) to placement to Optimize timing p9

Trik An Overview of through-Silicon via – based Three Dimensional integrated Circuits (3D IC) to placement to Optimize timing p9

multilayer graphs

Terminology

Literature


logic graphs

logic graphs

logic graphs
Rahman System-Level Performance Evaluation of Three-Dimensional Integrated Circuits p8.pdf

logic graphs

Souri, Shukri J: 3D ICs Interconnect Performance Modeling and Analysis, Ph.D. Dissertation Draft, Nov 2002, p123

Terminology

Literature


multilevel graph

LAYERED GRAPHS

layer-blocks graph

layer-blocks graph
Ababei, Cristinel; Mogal, Hushrav , and Bazargan, Kia: Three-dimensional place and route for FPGAs p10‖ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, Jun. 2006, pp. 1132-1140..
The objective of minimizing the total vertical wire-length and maximum cut between any two adjacent layers is equivalent to minimizing the bandwidth of the EV-matrix associated to the layer-blocks graph which resulted from the above partitioning [38]. Edges of this graph have weights given by the number of edges of the initial netlist graph, which span different layer-blocks. The EV-matrix is an m×n matrix where m – the number of rows – is the number of edges in the graph and n – the number of columns – is the number of nodes. An element a(i, j)=1 in the matrix is nonzero if the j-th node is a terminal of the i-th net. If a node is not a terminal for a net, the corresponding EV-matrix element is zero. The bandwidth of a matrix is defined as the maximum distance between first and last non-zero entries, among all rows. An example of such a layer-blocks graph and its associated EV-matrix are presented in Fig. 5. In this example the bandwidth equals four due to second row, which has its first non-zero entry in the second column and its last nonzero entry in the sixth column.
An example of such a layer-blocks graph and its associated EV-matrix are presented in Fig. 5. In this example the bandwidth equals four due to second row, which has its first non-zero entry in the second column and its last nonzero entry in the sixth column.
Fig. 5. Layer-blocks graph and its associated EV-matrix.

Terminology

Literature


multi-graph

multi-graph

PHAN, HUY NGOC: DEVELOPMENT OF AN EXPERIMENTAL AND ANALYTICAL MODEL OF AN ACTIVE COOLING METHOD FOR HIGH-POWER THREE-DIMENSIONAL INTEGRATED CIRCUIT PhD Thesis May 2011 p134....................

Terminology

Literature


nearest neighbor graph

nearest neighbor graph
Chen Clock Tree Synthesis with Methodology of Re-use in 3D IC p6

Terminology

Literature


netlist graph

netlist graph
Ababei, Cristinel; Mogal, Hushrav , and Bazargan, Kia: Three-dimensional place and route for FPGAs p10‖ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, Jun. 2006, pp. 1132-1140..
Edges of this graph have weights given by the number of edges of the initial netlist graph, which span different layer-blocks.
Fig. 3. Illustration of initial partitioning and assignment to layers.

Terminology

Literature


network graph

network graph
He Integrated Interlayer Via Planning and Pin Assignment for 3D ICs p6.pdf

Terminology

Literature


OPTIMIZATION GRAPH

SYSTEM LEVEL COST FUNCTION OPTIMIZATION GRAPH

BEHAVIOR LEVEL COST FUNCTION OPTIMIZATION GRAPH

ACCURATE BEHAVIOR LEVEL COST FUNCTION OPTIMIZATION GRAPH

ADC SYSTEM LEVEL COST FUNCTION OPTIMIZATION GRAPH

Terminology

Literature


pancake graph

pancake graph
Yeh VLSI layouts of complete graphs and star graphs p7

Terminology

Literature


Parallel-prefix graph

Terminology

Literature


Partitioning Graph

Partitioning Graph

Ababei, Cristinel; Mogal, Hushrav , and Bazargan, Kia: Three-dimensional place and route for FPGAs p6

We note that a solution for the layer assignment problem may
not be optimal in terms of both objectives of wire-length and
maximum cut between adjacent layers. Therefore, for this step, we
use an efficient heuristic [19], which is able to find solutions with
very good trade-off between wire-length and maximum cut. This
technique is briefly described in what follows using the graph
example shown in Fig. 5.
Figure 5 Illustration of good and bad initial linear placement of partitions
into layers

First, we build the EV-matrix, which is
an m×n matrix where m – the number of rows – is the number of
edges in the graph and n – the number of columns – is the number
of nodes. An element a(i, j)=1 in the matrix is non-zero if the j-th
node is a terminal of the i-th net. If a node is not a terminal for a
net, the corresponding EV-matrix element is zero. The order of the

columns determines the order of the nodes in a linear placement.
To minimize wire length and cut cost of the linear placement, the
EV-matrix is transformed into a band matrix with the goal of
minimizing the width of the band. This problem is denoted as
B(EV-matrix)-min problem. The procedure to solve this problem
uses row and column exchanges and is based on a sorting
algorithm. The goal of getting the matrix to a band-form (which
translates into a best linear ordering) serves two objectives:

Partitioning Graph

Seiculescu Chapter 9 3D Network on Chip Topology Synthesis Designing Custom Topologies for Chip Stacks p31.pdf

Partitioning Graph

Seiculescu SunFloor_3D_a_Tool_for_Networks_02.2_2 p6.pdf

Terminology

Literature


path graph

path graph
DICKSON Global Routing in VLSI Algorithms, Theory, and Computation p76.pdf

Terminology

Literature


platform graph

platform graph
Andres, Benjamin et al: A Combined Mapping and Routing Algorithm for 3D NoCs Based on ASP, Jan 2013, p12..
Figure 1: A system model consisting of a task graph, a platform graph and mapping options.
The system architecture is modeled by a platform graph (R;ER). Its vertices R represent resources
like processors, buses, memories, etc., and the directed edges ER  R R model communication
connections between them. Given a task graph (P [C;ET ) and a platform graph (R;ER), mapping
options of processing tasks p 2 P are determined by Rp  R, providing resources on which p can
be implemented. The lower part of Figure 1 shows a platform graph containing six computational
and two communication resources along with 18 connections. It is assumed that communication
tasks can be routed via every resource. The mapping and routing model also includes a function
f : P  R ! N, returning the work load generated by mapping a process to a resource in percent.

Terminology

Literature


quotient graph
Yeh Multilayer VLSI Layout for Interconnection Networks p8.pdf

Terminology

Literature


rectilinear graph

rectilinear graph
Fischbach, Robert; Lienig, Jens and Meister, Tilo: 3D Physical Design Challenges and Solutions p6............

Terminology

Literature


relation graph

relation graph

Lu, CHAO-HUNG et al: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits, JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 27, 287-302 (2011), p16

LU, CHAO-HUNG; CHEN, HUNG-MING AND LIU, CHIEN-NAN JIMMY: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits p16 JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 27, 287-302 (2011) 287

Terminology

Literature


residual graph

residual graph

Jiang, Li et al: On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs p6 DAC ’13, May 29 - June 07 2013, Austin, TX, USA ...................

Terminology

Literature


resource graph

resource graph
Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8

routing resource graph

routing resource graph

routing resource graph
Ababei, Cristinel ; Feng, Yan; Goplen, Brent et al.: Placement and routing in 3D integrated circuits. IEEE Design and Test of Computers, 22(6):520{531, 2005, p10
Our routing algorithm is an extension of VPR’s routing engine. The 3D FPGA architecture (see Figure 1(a)) described in the architecture file is represented as a routing resource graph. Each node of the routing resource graph represents a wire (horizontal tracks in the xand ychannels of all tiers and vertical vias in the zchannels) or a logic block input or output pin. A directed edge represents a unidirectional switch (such as a tri-state buffer). A pair of directed edges represents a bidirectional switch (such as a pass transistor). We add extra penalties to bends of a route created by a horizontal track and a vertical via as well as to vertical vias themselves in order to discourage the routing engine to prefer vertical vias and therefore to avoid a net placed totally in one tier to be routed using tracks in different tiers.
Fig. 1. 3D FPGA and swtich example.

routing resource graph

routing resource graph
Ababei, Cristinel; Mogal, Hushrav , and Bazargan, Kia: Three-dimensional place and route for FPGAs p6
Our 3D routing engine is shared by TPR and SA-TPR. The 3D
FPGA architecture – described in the architecture file – is
represented as a routing resource graph. Each node of the routing
resource graph represents a wire (horizontal tracks in the x and y
channels of all layers and vertical vias in the z channels) or a logic
block (i.e., CLB) input or output pin. A directed edge represents a
unidirectional switch (such as a tri-state buffer). A pair of directed
edges represents a bi-directional switch (such as a pass transistor).
An example of a routing resource graph construction is shown in
Fig. 7.
Figure 7 Illustration of the routing graph construction
The 3D FPGA architecture – described in the architecture file – is represented as a routing resource graph. Each node of the routing resource graph represents a wire (horizontal tracks in the x and y channels of all layers and vertical vias in the z channels) or a logic block (i.e., CLB) input or output pin. A directed edge represents a unidirectional switch (such as a tristate buffer). A pair of directed edges represents a bidirectional switch (such as a pass transistor). An example of a routing resource graph construction is shown in Fig. 8.
Fig. 8. Illustration of the routing graph construction.

routing resource graph
Chandrasekhar, Vikram: CAD for a 3 dimensional FPGA, June 2007, p77................

routing resource graph

Fischbach, Robert; Lienig, Jens and Meister, Tilo: 3D Physical Design: Challenges and Solutions p6 2009

modeling routing resources for 3D ICs.

In order to investigate routability prediction in the 3D context, we must first address the issue of modeling routing resources for 3D ICs.

Routing resources can be modeled by a rectilinear graph with weighted edges as shown in Fig. 5a. Nodes correspond to regions in the design and weighted edges correspond to routing resources in those regions. Each of the nodes is assigned a location (x, y, z). Here, x and y are continuous coordinates within a layer, while z is discrete and specifies the interconnect layer. In practice, x and y are often artificially restricted to discrete values, and preferred directions for interconnects are assumed. These two measures simplify the design process by limiting the number of nodes as well as reducing the number of edges of the graph (Fig. 5b).

Figure 5: (a) General graph modeling interconnect resources and (b) a graph with a reduced number of edges by assuming preferred directions for routing [5].
This general model of routing resources is valid for 3D designs as well as for previous 2D technologies. This observation would imply that the complexity of routing prediction does not increase for 3D ICs. However, during 3D routing prediction, the number of interconnect layers that have to be taken into account is larger, design objectives differ compared to previous technologies, and additional 3D-specific constraints must be considered.
As discussed, routability prediction is characterized by a trade-off between accuracy and runtime. Balancing this trade-off is even more important for 3D routability prediction as solutions spaces are generally larger. Depending on the required accuracy, the routing graph has to be simplified by an appropriate degree. For 2D systems, the routing graph is simplified by combining routing layers (Fig. 6b) and/or by coarsening the routing grid (Fig. 6a). The former simplification discards any information about vias. The latter – which reduces the x- and y-resolution by an arbitrary factor – is the basic concept of global routing.

Figure 6: Simplifications of the routing graph. The coarsening of the routing grid is shown at the left while combining layers is illustrated at the right.
While merging all routing layers has proven to be effective for routability prediction of 2D ICs, this simplifica-tion is not applicable to 3D ICs due to the omission of inter-tier vias. These vias must be included during 3D routability prediction because of their impact on routing (blockages, electrical properties, etc.). Therefore, routing layers of different tiers have to be treated separately. This requires a new intermediate level of simplification when combining routing layers (Fig. 7). In a first step (from (a) to (b)), only layers of the same tier are combined. Only if a further simplification is necessary, layers of different tiers are merged (from (b) to (c)). In this case, however, characteristics of thermal and inter-tier vias are omitted and the routability prediction is only of limited use.

Figure 7: Simplifications of the routing graph for 3D ICs. In addition to the simplification shown in Fig. 6b, an intermediate level of simplification (b) is necessary. Simplification level (c) is only of limited use for 3D ICs due to its omission of thermal and inter-tier vias.
After reviewing the problem of modeling routing resources for 3D designs, the process of routability prediction is discussed next. Here, the adaptation of 2D methods, such as global routing and other, often faster methods, is required.

routing resource graph
Minz, Jacob Rajkumar et al: Optical Routing for 3-D System-On-Package, IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 4, DECEMBER 2007, p8........................
The weight is based on the current usage
of the routing resource graph. The nodes in the subgraph are
ranked according to the weighted distance from the source node
(higher distance translates to higher ranks). The heuristic constructs
the topology by considering the nodes in descending
order of their ranks and merging them iteratively to form Steiner
nodes. During the tree construction we do not allow merging at
the routing nodes that are occupied by the existing waveguides.

routing resource graph
Minz, Jacob Rajkumar and Lim, Sung Kyu : Global Routing for Three Dimensional Packaging Dec 2003 p8

Terminology

Literature


sequencing graph

sequencing graph
De Micheli, Giovani: Synthesis And Optimization Of Digital Circuits, April 2005, p586 .................. 78

We consider in this book one particular abstract model for tasks subject to data- and control-flow dependencies. This model will be used consistently to describe synthesis algorithms and the proof of their properties. The model is called sequencing graph and it is a hierarchical controUdata-flow graph, where control-flow primitives such as branching and iteration are modeled through the hierarchy, whereas data-flow and serialization dependencies are modeled by graphs. In addition, the hierarchical model supports a model call, i.e., the encapsulation of subsets of operations and their dependencies into blocks that can be multiply invoked.

To be more specific, we call sequencing graph G,(V, E) a hierarchy of directed graphs. A generic element in the hierarchy is called a sequencing graph entity, when confusion is possible between the overall hierarchical model and a single graph. A sequencing graph entity is an extended data-flow graph that has two kinds of vertices: operations and links, the latter linking other sequencing graph entities in the hierarchy. Sequencing graph entities that are leaves-of the hierarchy have no link vertices.

Let us consider first a sequencing graph entity that has only operation vertices, e.g., a non-hierarchical model or an entity that is a leaf of the hierarchy. The vertex set V is in one-to-one correspondence with the operations. The edge set E models the dependencies due to data flow or serialization. The graph has two major properties. First, it is ac),clic. Hence it models a partial order on the tasks. Acyclic dependencies suffice because iteration is modeled outside the graph entity, as shown later. Second, the graph is polar; i.e., there are two vertices, called source and sink, that represent the first and last tasks. Since there may not be a unique task to be executed first (or last) in the circuit specification, the source and sink vertices always model No-Operations. The source is the tail of directed edges to all those vertices representing the initial operations and the sink is the head of directed edges from all those representing the I final tasks.

The source and sink vertices are labeled by uo and u,, respectively. Therefore the graph has n,, + 2 vertices and subscript n is interchangeable with n,, + 1. The vertex set is then V = (u,; i = 0, 1.. . . , n) and the edge set E = {(v;, u,); i , j = 0, 1, . . . , n] represents those operation pairs such that operation u, follows directly vi for any i , j = 0, 1, . . . , n. We say that vertex v; is a predecessor (or direct predecessor) of u, when there is a path (or an edge) with tail ui and head u,. Similarly, we say that vertex u, is a successor (or direct successor) of v, when there is a path (or an edge) with tail v, and head 0;. Note that paths in the graph represent concurrent (and not alternative) streams of operations.

Let us consider now a generic sequencing graph entity. The same considerations presented above still apply, with the exception that some vertices are links to other sequencing graph entities, representing model call, branching. and iteration consuucts.

Branching constructs can be modeled by a branching clause and branching bodies. A branching body is a set of tasks that are selected according to the value of the branching clause. There are as many branching bodies as the possible values of the branching clause, and their execution is mutually exclusive. Branching is modeled by associating a sequencing graph entity with each branching body and a link vertex with the branching clause. The link vertex also models the operation of evaluating the clause and taking the branching decision. The selection of a branch body is then modeled as a selective model call to the corresponding sequencing graph.

Iterative constructs are modeled by an iteration clause and an iteration body. An iteration (or loop) body is a set of tasks that are repeated as long as the iteration clause is true. Iteration is modeled in sequencing graphs through the use of the hierarchy, thus preserving the acyclic nature of the graph. Iteration is represented as a repeated model call to the sequencing graph entity modeling the iteration body. The link vertex models the operation of evaluating the iteration clause.

The semantic interpretation of the sequencing graph model requires the notion of marking the vertices. A marking denotes the state of the corresponding operation, which can be (i) waiting for execution; (ii) executing; and (iii) having completed execution. Firing an operation means starting its execution. Then, the semantics of the model is as follows: an operation can bepred as soon as all its direct predecessors have completed execution.

We assume that a model can be reset by marking all operations as waiting for execution. Then. the model can he fired (i.e., executed) by firing the source vertex. The model has completed execution when the sink has completed execution. Pipelined circuits can be modeled by sequencing graphs where the source is fired before the sink has completed execution.

Some attributes can be assigned to the vertices and edges of a sequencing graph model, such as measures or estimates of the corresponding area or delay cost. In general, the delay of a vertex can be data independent or data dependent. Only dataindependent delays can be estimated before synthesis. Examples of operations with data-dependent delay are data-dependent delay branching and iteration. For example, a branch may involve bodies with different delays, where in the limit one branch body can be a No-Operation (e.g., a floating point data normalization requiring conditional data alignment). An example data-dependent iteration is given by an arithmetic divisor, based on an iterative algorithm.

Data-dependent delays can be bounded or unbounded. The former case applies to data-dependent delay branching, where the maximum and minimum possible delays can be computed. It applies also to some iteration constructs, where the maximum and minimum number of iterations is known. The latter case is typical of some other iteration constructs, as well as modeling external synchronization.

A sequencing graph model with data-independent delays can be characterized by its overall delay, called latency. Graphs with bounded delays (including dataindependent ones) are called bounded-latency graphs. Else they are called unboundedlatency graphs, because the latency cannot be computed.

We close this section by mentioning that the circuit behavior at the architectural level can be modeled by Petri nets. A wide literature on Petri nets is available [21]. Petri nets can be cast as directed bipartite graphs, where vertices correspond to places and transitions. The former can be thought of as states and the latter as operations. The Petri net model is more general and powerful, and it sets the framework to state properties of general concurrent circuits. On the other hand, modeling and synthesizing synchronous circuits can be achieved with simpler models, e.g., sequencing graphs or equivalent control/data-flow graphs. Indeed, just one type of vertices suffices, and there is no need to distinguish places from transitions. Petri nets fit better the modeling requirements of asynchronous circuits, which are beyond the scope of this book.


shuffle-exchange graph

”universal-purpose” graphs (like n-permuters, n-rearrangeable permutation networks, shuffle-exchange graphs)

shuffle-exchange graph

shuffle-exchange graph
Recski, Andras and Szeszler, David: 3-dimensional Routing, Aug 2008. p8.

Leighton, T., Complexity issues in VLSI: Optimal layouts for the shuffle-exchange graph
and other networks, The MIT Press, Cambridge, MA. (1983)

However, most of these results embed certain ”universal-purpose” graphs (like n-permuters,
n-rearrangeable permutation networks, shuffle-exchange graphs) into the 3-dimensional grid,
ensuring that pairs of terminals can be connected, moreover, in some papers along edge-disjoint
paths.

shuffle-exchange graph
Reiss, Attila and Szeszler, David: 3-dimensional Channel Routing, Nov 2007. p10
In single row routing and channel routing the inputs are essentially one-dimensional (one
or two lists of terminals) and the output is essentially two-dimensional (a fixed number of
planar layers). However, as technology permits more and more layers, a ”real” 3-dimensional
approach becomes reasonable. The research of 3-dimensional routing started in the 1980s and
there are plenty of deep results in this area, see [1, 2, 3, 4, 5, 6, 7, 8, 12, 13], for example.
However, most of these results embed certain ”universal-purpose” graphs (like n-permuters,
n-rearrangeable permutation networks, shuffle-exchange graphs) into the 3-dimensional grid,
ensuring that pairs of terminals can be connected, moreover, in some papers along edge-disjoint
paths.

Terminology

Literature


Structured Directed Graph

Structured Directed Graph
Min, Hyeun-Jeong and Cho, Sung-Bae: Creative 3D Designs Using Interactive Genetic Algorithm with Structured Directed Graph p10. PRICAI 2004, LNAI 3157, pp. 391–400, 2004. ? Springer-Verlag Berlin Heidelberg 2004

Terminology

Literature


Tanner graph

Tanner graph
Zhou, Lili: A High-Throughput Low-Power Fully Parallel 1024-bit ?-Rate Low Density Parity Check Code Decoder in 3-Dimensional Integrated Circuits p2 2006 IEEE

Terminology

Literature


task graph

task graph

the communication task graph (CTG)

task graph
Andres, Benjamin et al: A Combined Mapping and Routing Algorithm for 3D NoCs Based on ASP, Jan 2013, p12..
Figure 1: A system model consisting of a task graph, a platform graph and mapping options.
Combined Mapping and Placement Problem

In order to automate the mapping and routing of an application onto a a system, the application is
modeled by a task graph (T;ET ). Its vertices T represent tasks and are bipartitioned into process
tasks P and communication tasks C, that is, T = P [ C and P \ C = ;. The directed edges
ET  (P  C) [ (C  P) model data and control dependencies between tasks, where every
communication task has exactly one predecessor and an arbitrary (positive) number of successors,
thus assuming single-source multicast communication.

An exemplary task graph is shown in the upper part of Figure 1. The leftmost task ps reads data
from a sensor and sends it to a master task pm via communication task c1. The master task then
schedules the workload and passes data via communication task c2 on to the worker tasks p1 and
p2. Both workers send their results back to the master via communication tasks c3 and c4. Finally,
the master uses the combined result to control an actuator task pa via communication task c5.

The ASP instance for a task graph (P [ C;ET ) and a platform graph (R;ER) along with the
underlying mapping options, (Rp)p2P and the work load function f is defined as follows:
fpt(p). j p 2 Pg [
fsend(p; c). j (p; c) 2 ET ; p 2 P; c 2 Cg [
fread(p; c). j (c; p) 2 ET ; p 2 P; c 2 Cg [
fpr(r). j p 2 P; r 2 Rpg [
fload(p; r; l). j p 2 P; r 2 Rp; l = f(p; r)g [
fedge(r; s). j (r; s) 2 ERg [
fs(i). j i 2 f1; : : : ; ngg

task graph
Tsai Bi-Routing A 3D Bidirectional-channel Routing Algorithm for Network-based Many-core Embedded Systems p10.pdf

communication task graph (CTG)
Hamedani, Parisa Khadem et al: Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip p8 Nov 2011

communication task graph (CTG)
de Paulo 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans p12.pdf
de Paulo 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans p13.pdf

communication task graph (CTG)
Gnanaskaran Evaluation Of 3D Network-On-Chip Architectures By Using Layers p14.pdf

Terminology

Literature


temperature graph

temperature graph
Cherian, Annmol et al: THERMAL MODELING AND ANALYSIS OF 3- DIMENSINAL MEMORY INTEGRATION p15 D.C. Wyld, et al. (Eds): CCSEA 2011, CS & IT 02, pp. 242–256, 2011. ? CS & IT-CSCP 2011
The variation of leakage current with temperature and supply voltage is found in order to check
the accuracy of the thermal modelling process. If the curve follows the ideal curve then the
strategies taken are perfect. In this case both the characteristics follow the ideal curve and so the
strategies are accurate and perfect. Leakage current with temperature graph attached below.

Terminology

Literature


tile graph

tile graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

Terminology

Literature


timing graph

timing graph
Dong, Chen; Chilstedt, Scott and Chen, Deming: Variation Aware Routing for Three-Dimensional FPGAs April 2009, p6.

To perform 3D SSTA, each node in the timing graph must be
made to store variation in addition to nominal delay. In our timing
graph, we add normally distributed random variation and n × p
sets of PCs to each node, where n is the number of layers in the
stack and p is the number of independently correlated process
parameters. If each die is divided into m grid squares, there will be
m PCs in each set. The maximum number of PCs is therefore n ×
p × m. Since many of these PCs will remain empty, we allocate
memory for a set of PCs only when a non-zero value is stored.

.........................

The rest of the routing is iterative. During the first iteration,
the criticality of each pin in every net is set to 1 (the highest
criticality) to minimize the wire length of each pin. After all of the
nets are routed, SSTA is performed by traversing the updated
timing graph to calculate the new slack and critical path delays.
The criticality of pin j in net i is then computed, considering
variation in the slack and critical path according to equation 5.

timing graph
Gupta Yield Analysis and Optimization p29

timing graph / circuit timing graph
Hu, Jiang and Sapatnekar, Sachin S.: A Survey on Multi-net Global Routing for Integrated Circuits Dec 2004 p68.
{jhu, sachin}@mail.ece.umn.edu
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455, USA
Tel: 612-625-0025, Fax: 612-625-4583

timing graph
Luo, Guojie: Placement and Design Planning for 3D Integrated Circuits, 2011, PhD dissertation, p184 ............... 26

timing graph
Pangracious Designing a 3D Tree-based FPGA Optimization of Butterfly Programmable Interconnect Topology Using 3D Technology p8.pdf

timing graph
Vygen, Jens: Faster Resource Sharing and Global Routing in Theory and Practice Nov 2011 p88.

timing graph
XuHu Modeling and Design Techniques for 3-D ICs under Process Voltage, and Temperature Variations p228.pdf

Terminology

Literature


communication trace graph

communication trace graph
Bahirat, Shirish and Pasricha, Sudeep: 3D-HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific 3D Network-On-Chip Architectures p8 Jan 2014
Application communication trace graph G(V,M,L) for each application in a multi-application workload, where vi ∈ V is a set of processing cores, mi ∈ M a set of memory blocks, li ∈ L a set of directed communication links;

Terminology

Literature


Transition / Transitive Graph

transitive graph

TCG: transitive closure graph

Sequence k-tuple

transitive graph

transitive graph

Cong, Jason; Wei, Jie and Zhang, Yan: A Thermal-Driven Floorplanning Algorithm for 3D ICs p8 Dec 2004 ...............

Cong A Thermal-Driven Floorplanning Algorithm for 3D ICs p8.pdf
The existing works on 3D floorplanning can be divided into
two groups according to the 3D block representation. One kind of
approach is to extend the existing representation to a “true 3D”
representation (true 3D), such as 3D TCG [3] and sequence triple
[25], with a similar representation structure, a transitive graph and
a sequence, respectively, added for the third dimension position
representation. However, the chips and the blocks under the
current 3D technology are located in a limited number of device
layers. So the “true 3D” representation is not suitable for 3D IC
floorplanning for two reasons; for designs with fixed device layer
number, additional constraints will be needed for “true 3D”
representation to generate feasible results; also, for the same
reason, the additional complicated data structure for the z-axis
generates too much redundancy, which is not efficient in both

Transition/ Transitive Closure Graph (TCG)

3-D Transition Closure Graph (TCG)

3-D Design: Architectures, Methodologies, and Test Circuits
Friedman, Eby G.: 3-D Design: Architectures, Methodologies, and Test Circuits p137 June 11, 2010 2nd Design for 3-D Silicon Integration Workshop ....................

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering

Department of Electrical and Computer Engineering

University of Rochester

Rochester, New York 14627 USA

Phone: (585) 275-1022 Fax: (585) 276-0074

Email: friedman@ece.rochester.edu

www.ece.rochester.edu/~friedman

Floorplanning in 3-D

3-D Transition Closure Graph (TCG)
Transitive closure graph-basedrepresentation for general floorplans
?No additional constraint graphs for cost evaluation
?Supports incremental update of boundary information, shapes, and relative positions
?Independent of physical location
J.-M. Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for General Floorplans,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol. 13, No. 2, pp. 288-292, February 2005.

Transition Closure Graph (TCG)

Falkenstern, Paul et al: . Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis. In Proc. 15th Asia and South Paci c Design Automation Conf. (ASP-DAC), pages 169- 174, 2010. p 6 ........................

Falkenstern, Paul et al: . Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis p17 ppt slides . In Proc. 15th Asia and South Paci c Design Automation Conf. (ASP-DAC), pages 169- 174, 2010.

closure graphs / Transitive Closure Graph (TCG) / Layered Transitive Closure Graph (LTCG)
Law Block Alignment in 3D Floorplan Using Layered TCG p5

Transition Closure Graph (TCG)
Luo, Guojie: Placement and Design Planning for 3D Integrated Circuits, 2011, PhD dissertation, p184 ............... 26

Transition Closure Graph (TCG)
Zhou, Pingqiang et al: 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits p8 Aug 2007

state transition graph

Terminology

Literature


Untitled Document

Graph / Hypergraph File Format in General

http://graphml.graphdrawing.org/

http://cneurocvs.rmki.kfki.hu/igraphbook/igraphbook-foreign.html

http://www.open-graphtheory.org/gxlformat.html

http://igraph.org/c/doc/igraph-Foreign.html

https://www.mediawiki.org/wiki/Extension:Semantic_Graph

http://www.staff.science.uu.nl/~bisse101/Mondriaan/Docs/HYPERGRAPH.html

http://abel.math.umu.se/~klasm/Data/hypergraphs/turanhypergraphs.html

http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Fundamental/HGraph/

http://vlsicad.ucsd.edu/UCLAWeb/cheese/benchmarks.html

http://glaros.dtc.umn.edu/gkhome/taxonomy/term/63/0?page=3

http://www.sciencedirect.com/science/article/pii/S0167642305001176

https://networkx.readthedocs.io/en/latest/reference/readwrite.graphml.html

https://aclweb.org/aclwiki/index.php?title=Hypergraph_Format

https://github.com/igraph/rogdf/blob/master/OGDF/src/ogdf/fileformats/simple_graph_load.h

http://javadox.com/jung/jung/1.7.6/doc/edu/uci/ics/jung/graph/class-use/Hypergraph.html

https://networkx.github.io/documentation/networkx-1.10/reference/readwrite.graphml.html

https://www.it.uu.se/research/group/concurrency/adhoc/gbt

http://bioinformatics.oxfordjournals.org/content/early/2015/07/14/bioinformatics.btv385.full

http://webgraph-it.com/docs/about

https://gephi.org/gexf/lib/

http://cs.nyu.edu/shasha/papers/graphgrep/graphgrepsx.html

http://orientdb.com/orientdb-new-graphdb-engine-in-beta/

http://js.cytoscape.org/

https://www.microsoft.com/en-us/research/project/discussion-graph-tool/

http://hadim.fr/pygraphml/overview.html

https://eudml.org/doc/181835

http://webgraph.di.unimi.it/docs/it/unimi/dsi/webgraph/jung/JungAdapter.html

http://www.b-alexander.com/introduction-to-graph-and-hypergraph-theory.pdf

http://web.cs.ucdavis.edu/~gusfield/pphcd/E:/graph_realization/README.txt

http://wikipediaaudio.com/GraphML

http://r.pohape.ru/#/en/read.graph.html

http://graphstream-project.org/doc/Advanced-Concepts/The-DGS-File-Format/

http://www.tcs.hut.fi/Software/bliss/fileformat.shtml

Boost Graph Library

– C++, graph interface and components are generic
? JUNG
– Java-based, graph algorithms + visualization engine
? igraph
– C library with R and Python interfaces
? MultiThreaded Graph Library (MTGL)
– Boost Graph library-like, for multithreaded architectures

DOT language

http://en.wikipedia.org/wiki/DOT_language
http://graphviz.org/
a plain text graph description language -- Graphviz

GAMFF - A Graph and Matrix File Format

hypergraph

Zien GAMFF - A Graph and Matrix File Format p37

GD ’XXX Conferences - the Symposia on Graph Drawing

the Symposia on Graph Drawing (GD ’XX conferences) agreed to introduce a common file format. This report discusses several graph file formats have been proposed.

GEXF (Graph Exchange XML Format)

http://gexf.net/format/
GEXF (Graph Exchange XML Format) is a language for describing complex networks structures, their associated data and dynamics. Started in 2007 at

GML- GRAPH MODELLING LANGUAGE

GML [19], a widely used file format for both graph and layout specifications

http://en.wikipedia.org/wiki/Graph_Modelling_Language
http://www.infosun.fim.uni-passau.de/Graphlet/GML/
GML, the Graph Modelling Language [1, 2] is a file format for graphs whose key features are portability, simple syntax, extensibility and flexibility. GML is designed to represent arbitrary data structures. A GML file consists of hierarchical key-value lists. GML was bound to a specific system, namely Graphlet [3, 4]. However, it has been overtaken and adapted by several other systems for drawing graphs.

GML (Graph Modelling Language): There are many different programs that work with graphs but almost all of them use their own file format. As a consequence, exchanging graphs between different programs is almost impossible. Simple tasks like exchange of data, externally reproducible results or a common benchmark suite are much harder than neccessary.
Therefore, we have developed a new file format for the Graphlet system: GML. GML supports attaching arbitrary information to graphs, nodes and edges, and is therefore able to emulate almost every other format.
In the following the documentation, the parser and a technical report with respect to GML:
gml-documentation.tar.gz
gml-parser.tar.gz
gml-technical-report.pdf
http://www.fim.uni-passau.de/fileadmin/files/lehrstuhl/brandenburg/projekte/gml/gml-documentation.tar.gz
http://www.fim.uni-passau.de/fileadmin/files/lehrstuhl/brandenburg/projekte/gml/gml-parser.tar.gz
http://www.fim.uni-passau.de/fileadmin/files/lehrstuhl/brandenburg/projekte/gml/gml-technical-report.pdf

Himsolt GML A portable Graph File Format p8

GraphML

http://graphml.graphdrawing.org/
http://en.wikipedia.org/wiki/GraphML
http://en.wikipedia.org/wiki/GraphML
http://www.exlink-ch.com/site/0692DC507769E321.aspx
The purpose of a GraphML document is to define a graph. The GraphML document consists of a graphml element and a variety of sub elements: graph, node and edge. The first line of the document is an XML process instruction that defines that the document adheres to the XML 1.0 standard and that the encoding of the document is UTF-8, the standard encoding for XML documents. Of course other encodings can be chosen for GraphML documents.
Hyperedges

GraphXML

GraphXML is a graph description language in XML. The goal of GraphXML is to provide a general interchange format for graph drawing and visualization systems, and to connect those systems to other applications. The requirements of information visualization have greatly influenced design decisions during the development of GraphXML. Although GraphXML can be used for the description of purely mathematical graphs, restricted to the set of nodes and edges, information visualization applications require more features. For example, it should be possible to label graphs, nodes, and edges. It should also be possible to attach application-dependent data and external references. Applications might produce not just a single graph, but also a whole series of graphs, possibly ordered in time. We might want to control the visual appearance of the graphs, such as the colour of the edges, images used when iconifying a window containing a specific graph. The interchange format should be able to cope with these demands as well.

GRXL

GRXL draft version 0.1 is an XML DTD and worked example to show how a Grrr program might be stored in a form that allows conversion to other graph transformation systems. The approach adopted here explicitly includes the important attributes in the ATTLIST at the highest reasonable level. This approach allows for easier understanding of the resultant XML, and helps hand coding and editing.

GXL - GRAPH EXCHANGE LANGUAGE

http://en.wikipedia.org/wiki/GXL
http://www.gupro.de/GXL/

GXL [11.\\"SOO] (an
acronym for Graph eXchange Language)
GXL is designed to be a standard software exchange format for exchanging information derived from programs, and more generally for exchanging information that is conveniently represented as a graph. To facilitate this exchange the information is represented as a graph and the graph is transcribed the to XML.
Being a structural description, graphs have no meaning of their own. The meaning of graphs corresponds to the context in which they are exchanged. This context is, in part, given by a schema (essentially an E/R diagram or class diagram). In GXL, both the actual data representing the graph and the schema are passed as XML stream. Other information associated with the graph, such as user annotations or (x, y) locations for graph layout, is attached to the graph and passed in GXL as attributes.
GXL includes support for hypergraphs and hierarchical graphs and can be extended to support other types of graphs.

Holt GXL

A graph-based standard exchange format for reengineering p22

RDF - THE RESOURCE DESCRIPTION FRAMEWORK

The Resource Description Framework (RDF) is a framework for representing information in the Web. RDF has an abstract syntax that reflects a simple graph-based data model, and formal semantics with a rigorously defined notion of entailment providing a basis for well founded deductions in RDF data. RDF is designed to represent information in a minimally constraining, flexible way. It can be used in isolated applications, where individually designed formats might be more direct and easily understood, but RDF's generality offers greater value from sharing. The value of information thus increases as it becomes accessible to more applications across the entire Internet.

SVG

http://www.w3.org/Graphics/SVG/

Trivial Graph Format

http://en.wikipedia.org/wiki/Trivial_Graph_Format
http://en.wikipedia.org/wiki/YEd
http://docs.yworks.com/yfiles/doc/developers-guide/tgf.html
http://reference.wolfram.com/mathematica/ref/format/TGF.html
http://www.yworks.com/products/yfiles/doc/developers-guide/tgf.html
http://yed.yworks.com/support/manual/fileformat.html

XGMML - EXTENSIBLE GRAPH MARKUP AND MODELING LANGUAGE

http://www.cs.rpi.edu/~puninj/XGMML/
http://en.wikipedia.org/wiki/XGMML
http://www.cs.rpi.edu/~puninj/XGMML/
Extensible Graph Markup and Modeling Language (XGMML) is an XML 1.0 application based on Graph Modeling Language (GML) to describe graphs. The best way to describe a web site structure is using a graph structure so XGMML documents are a good choice for containing the structural information of a web site.

Ref

Bernard GRAPH FILE FORMATS p50
Bernard GRAPH FILE FORMATS p50
June 2007


def

Graph Operations

Graph_Indexing
Graph_Powering
Graph_traversal
graph_analysis
graph_analyzing
graph_classification
graph_cleaning
graph_clustering
graph_coloring
graph_comparison
graph_compression
graph_conversion
graph_coupling
graph_editing
graph_enumeration
graph_examine
graph_exchange
graph_immersions
graph_interpolation
graph_labeling
graph_matching
graph_mining
graph_partition
graph_processing
graph_profiling
graph_reduction
graph_searching
graph_seriation
graph_simplifying
graph_transform
graph_transformation

Community Browsing in Graph

[Baingana2013b]

graph clustering

[LUQMAN2012]
[Riesen2009]
[ARORA2006]

graph compression

graph enumeration

?

graph interpolation

graph isomorphism/ subgraph isomorphism
[Gibert2012]
[Riesen2009]

Graph Partitioning
[ARORA2006]

graph retrieval


Untitled Document

graph classification
[LUQMAN2012]


Untitled Document

Graph Matching
[Gibert2012]
[LUQMAN2012]
[Riesen2009]
[Zhao2013]

[Gibert2012]

[LUQMAN2012]
[Riesen2009]
[Zhao2013]

[Adamczewski2015]
The objective of graph matching is to find the correct correspondences between nodes of two graphs G1 and G2 with n1 and n2 nodes, respectively.

[Andrews1998]
A matching in a graph G is a subset M of the edges of G such that no two distinct edges in M are incident to the Si:Lme vertex.

[Bunke2000]
When graphs are used for the representation of structured objects, then the problem of measuring object similarity turns into the problem of computing the similarity of graphs, which is also known as graph matching.

If graphs are used for object representation this problem turns into determining the similarity of graphs, which is generally referred to as graph matching.

Standard concepts in graph matching include graph isomorphism, subgraph isomorphism, and maximum common subgraph.

[Duchenne2009]
Concretely, the corresponding hypergraph matching problem is formulated as the maximization of a multilinear objective function over all permutations of the features.

graph matching

[Adamczewski2015] Discrete Tabu Search for Graph Matching p9
Kamil

[Andrews1998] Parallel Algorithms for Maximum Matching in Complements of Interval Graphs and Related Problems p31
Marilyn G.

[Bunke2000] Graph Matching Theoretical Foundations, Algorithms, and Applications p7
2

Carroll Matching RDF Graphs p17
Jeremy J.

[Duchenne2009] A Tensor-Based Algorithm for High-Order Graph Matching p8
Olivier

HYPERGRAPH MATCHING MODELS???

Graph /Hypergraph Matching Models

HYPERGRAPH MATCHING MODELS???

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Hu Spectral Descriptors for Graph Matching p15

Graph matching
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Graph /Hypergraph Matching Models

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19

Emms Coined quantum walks lift the cospectrality of graphs and trees p15

Hu Spectral Descriptors for Graph Matching p15

Graph matching
Emms Coined quantum walks lift the cospectrality of graphs and trees p15

matching of graphs

Braunstein The laplacian of a graph as a density matrix: a basic combinatorial approach to separability of mixed states p19


Untitled Document

Graph Packings

Cooley EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf ..........

Graph Packings
[Cooley2009]

[Cooley2009]

[Caro1996]
An H-packing of a graph G is a set L = fG1; : : : ; Gsg of edge-disjoint subgraphs of G, where each subgraph is isomorphic to H.

[Kuhn2006a]
Given two graphs H and G, an H-packing in G is a collection of vertex disjoint copies of H in G.

[Pantel1999]
The problem of covering a graph with copies of graphs other than only K2 is called the graph packing problem.

[Sausen2013]

[Srinivasan2004]
Similarly, given ~w and a monotone decreasing f : Zn+ ! f0; 1g, a packing problem is to maximize ~w? ~x subject to f(~x) = 1.

?

?

graph packing

[Caro1996] Packing Graphs:The packing problem solved p7
Yair Caro and Raphael Yuster
1996
3

Goodman A Genetic Algorithm Approach to Compaction, Bin Packing, and Nesting Problems p73
? Erik D.

Grotschel The Steiner Tree Packing Problem in VLSIDesign p21
M.

Iwaniec Algorithms for Packing Soft Blocks of Vlsi Systems p6

Jeong A branch-and-price algorithm for the Steiner tree packing problem p21
Gue-woong

Kuhn AN ORE-TYPE THEOREM FOR PERFECT PACKINGS IN GRAPHS p23

Kuhn OPTIMAL PACKINGS OF HAMILTON CYCLES IN GRAPHS OF HIGH MINIMUM DEGREE p23

[Kuhn2006a] PERFECT PACKINGS WITH COMPLETE GRAPHS MINUS AN EDGE p15

Lau An Approximate Max-Steiner-Tree-Packing Min-Steiner-Cut Theorem p10?
Lap Chi

Martin Packing Paths and Steiner Trees Routing of Electronic Circuits p20

[Pantel1999] Graph Packing Problems p86

[Sausen2013] Models for the Steiner Tree Packing Problem p85
Michael

[Srinivasan2004] New Approaches to Covering and Packing Problems p10
Aravind


Untitled Document

graph theory for search engines

Aggarwal Theory Research at Google

Graph Labeling

Barabasi The physics of the Web

JULY 2001

random graphs

Bhawnani Mathematics at Google

Graph Theory in Google Maps

the web as a directed graph

graph hierarchies

BRYAN THE $25,000,000,000 EIGENVECTOR THE LINEAR ALGEBRA BEHIND GOOGLE

a web is an example of a directed graph

Ganta Search Engine Optimization through Web Page Rank Algorithm

HE Clustering and Searching WWW Images Using Link and Page Layout Analysis

2007

8

image graph

PageRank

HITS

PicASHOW

Markov Chain

ImageRanks

graph models

spectral graph theory

graph embedding problem

tree

??????????????????????

Korner Social-focused Network Analysis of User Goals Extracted from a Large Search Query Log

14


Untitled Document

graph theory for web crawling
graph theory for web crawler

graph theory for web spider

graph theory for web scraping

http://eddmann.com/posts/depth-first-search-and-breadth-first-search-in-python/
http://vigna.di.unimi.it/
https://webcms3.cse.unsw.edu.au/COMP1927/16s2/resources/5113

Bonato THE ROBOT CRAWLER GRAPH PROCESS p22

Broder Graph structure in the web p15

Chakrabarti Focused crawling: a new approach to topic-specific Web resource discovery p21
Soumen Chakrabarti 1 *,a, Martin van den Berg 2b, Byron Domc

okokok

Kumar SURVEY OF WEB CRAWLING ALGORITHMS p7

Kumar The Web as a graph p10

Lu An Approach to Deep Web Crawling by Sampling p7
McGregor Graph Mining on Streams p5


Graph Theory for Web Search

http://linkanalysis.wlv.ac.uk/5.htm

https://dl.acm.org/citation.cfm?id=1796041

http://dejanseo.com.au/search-quality-the-link-graph-theory/

http://environmentalresearchweb.org/cws/article/news/59878

http://www.inderscienceonline.com/doi/pdf/10.1504/IJWET.2014.063039

http://www.joergzuther.de/math/graph/homes.html

http://world.mathigon.org/Graph_Theory

http://www.open-graphtheory.org/

http://www.tandfonline.com/doi/abs/10.1080/01449290701840948

http://videolectures.net/fws06_boldi_gfgip/

http://webwhompers.com/graph-theory.html


Graph theory for web search
okokok

[AGARWAL2012] WEB GRAPH BASED SEARCH BY USING DENSITY OF KEYWORD AND AGE FACTOR p5

GAURAV AGARWAL1, SACHI GUPTA2 & SAURABH MUKHERJEE3
1& 2 Computer Science & Information Tech. Dept., Krishna Institute of Management & Technology, Moradabad, India
3Computer Science Department, Banasthali Vidyapith, Niwai, India
E-mail :

meetgaurav1@rediffmail.com

sachiagarwal@rediffmail.com

mukherjee.saurabh@rediffmail.com

International Journal of Computer Science and Informatics ISSN (PRINT): 2231 –5292, Volume-2, Issue-3, 2012

A search engine follows these steps:

  • Web crawling by crawler,
  • Indexing by Indexer and
  • Searching by Searcher
Page Graph System
Directional Web Graph: Web graph is an acyclic graph, in which nodes are representing the web pages and the edges are representing the links between the web pages.
okokok

[Bhawnani2014] Mathematics at Google p15

Avinash Bhawnani
IIT Kanpur
10/28/2014
graph Theory in Google Maps
directed graph

okokok
[Blondel2004] A Measure of Similarity between Graph Vertices: Applications to Synonym Extraction and Web Searching p20

SIAM REVIEW c 2004 Society for Industrial and Applied Mathematics Vol. 46, No. 4, pp. 647–666
Vincent D. Blondel?
Anah′? Gajardo?
Maureen Heymans§
Pierre Senellart?
Paul Van Dooren?

similarity between vertices of directed graphs

eigenvalues of graphs
6
okokok

[Brin1998] The Anatomy of a Large-Scale Hypertextual Web Search Engine p20

Sergey Brin and Lawrence Page

Sergey Brin and Lawrence Page
Computer Science Department,
Stanford University, Stanford, CA 94305, USA
sergey@cs.stanford.edu and page@cs.stanford.edu

link graph

citation (link) graph

PageRank

3
ZZZZZZZZZZZZ

[Broder2003] Graph structure in the web p15

Andrei Broder1, Ravi Kumar2, Farzin Maghoul1,
Prabhakar Raghavan2, Sridhar Rajagopalan2, Raymie Stata3,
Andrew Tomkins2, Janet Wiener3
1: AltaVista Company, San Mateo, CA.
2: IBM Almaden Research Center, San Jose, CA.
3: Compaq Systems Research Center, Palo Alto, CA.

http://www9.org/w9cdrom/160/160.html (1 de 15) [28/10/2003 18:08:36]

local and global properties of the web graph

  • diameter,
  • degree distributions,
  • connected components, and
  • macroscopic structure

"small world" phenomenon

Altavista crawls

directed graph

breadth-first searches
ZZZZZZZZZZZ

[Deo2002] Graph-theoretic analysis of the world wide web: new directions and challenges p21

ZZZZZZZZZZ

[Giatsidis2012] Search in BigData - When Big Text meets Big Graph p5

Christos Giatsidis, Fragkiskos D. Malliaros, Fran?ois Rousseau, Michalis Vazirgiannis
Computer Science Laboratory, école Polytechnique, France
{giatsidis, fmalliaros, rousseau, mvazirg}@lix.polytechnique.fr

Big Graph

k-core degeneracy
okokok

[Glickenstein2008] Math 443/543 Graph Theory Notes 8: Graphs as matrices and PageRank

David Glickenstein
October 30, 2008
okokok

[Húsek2005] DATA CLUSTERING: FROM DOCUMENTS TO THE WEB p31

Du?an Húsek, Jaroslav Pokorny, Hana Rezanková, Václav Sná?el
graph clustering
IpsenYYY The Mathematics Behind Googles PageRank p48.pdf
[Jeh2003] Scaling Personalized Web Search p9

Glen Jeh
Stanford University
glenj@db.stanford.edu
Jennifer Widom
Stanford University
widom@db.stanford.edu

web graph

directed graphs
okok

[LIN2012] From Clickstreams to Searchstreams: Search Network Graph Evidence from a B2B E-Market p3

Mei LIN
Singapore Management University, mlin@smu.edu.sg

clickstreams

searchstream data

search network graphs

cluster analysis

directed acyclic graphs (DAGs)

directed graph
[Metaxas2009] Web Spam, Social Propaganda and the Evolution of Search Engine Rankings p14

Panagiotis Takis Metaxas?
Wellesley College, Wellesley, MA 02481, USA,
pmetaxas@wellesley.edu
http://cs.wellesley.edu/~pmetaxas/

Web graph

graph isomorphism

directed graph

trust graphs

[Page 98] Lawrence Page, Sergey Brin, Rajeev Motwani, Terry Winograd. The PageRank Citation Ranking: Bringing Order to the Web. Manuscript in progress.

http://google.stanford.edu/~backrub/pageranksub.ps
ZZZZZZZZZZZ

[Pooja2014] Security Efficiency and User Interest Analysis Approach for Web Page Ranking p4

1Pooja, 2Hitesh Kapoor, 3Amit Raman
1Student M.Tech. (CSE), 2Asstt. Prof., CSE Deptt., 3Asstt. Prof., Mech. Deptt.
RPIIT, Technical Campus, Bastara, Karnal

IJSWS 14-261; ? 2014

user assisted WebPage ranking approach

WebPage ranking and prediction system is defined by Markov Model

WebPage graph

TordableYYY Mathematics at Google p52.pdf
TordableYYY Mathematics at Google.pdf
TordableYYY Mathematics at Google1 p52.pdf
TordableYYY Mathematics at Google2 p52.pdf
TordableYYY Mathematics at Google3 p52.pdf
[Wills2006] Google’s PageRank: The Math Behind the Search Engine p15

Rebecca S. Wills
Department of Mathematics
North Carolina State University
Raleigh, NC 27695
rmwills@ncsu.edu
May 1, 2006

Directed Web Graph

directed graph


Hypergraph

k-uniform hypergraph

Hypergraph, Hyper-graph, Hyper graph

weighted hypergraph

reduced hypergraph

dual hypergraph

clustered hypergraph

circuit hypergraphs

netlist hypergraph

multilevel hypergraph

k-way hypergraph

Multilevel K-way hypergraph

Coarsened Hypergraph

coarse hypergraph

coarser hypergraph

coarsest hypergraph

edge-coloring hypergraph

oriented hypergraph

An oriented hypergraph is an oriented incidence structure that extends the con-
cept of a signed graph.

Incidence-oriented hypergraphs

balanced incidence-oriented hypergraph

recursive label node hypergraphs

acyclic hypergraph

compact hypergraph

folded hyperpath

functional hypergraph

functional directed hypergraph

min-cut partitioning

Multi-level hypergraph partitioning

r-uniform hypergraph

Directed Hypergraph

Also called “labelled graphs” and “and-or graphs”

directed hyperedge or hyperarc

Hypergraph Structures

hyperpaths

minimum weight hyperpaths

hyperarc

hyperflows

spanning hypertree

Hypergraph Characteristics

rank

The rank of is the maximum size of an edge, r(gg) := max {IE[: E e E()}.

matching number

The matching number v() of is the maximum number of pairwise disjoint edges in E(/), i.e.,

fractional matching

A fractional matching ofo is a function w: E(oYg) -- (i.e., a vector in le(ae)l) satisfying
w(E) >= 0 for every edge E e E(o) and

covering number

The covering number r(’/g) of is the minimum cardinality of a cover T, where T c
V(Jct) is a cover if T f) E 4: for all E e E().

fractional covering number

The fractional covering number r* of a hypergraph H (V, E) is defined to be the minimum
possible value of ,,v t(x) where ranges over all functions t: V which satisfy ,xe t(x) >= for all edges e e E.

Degree

What is mostly done first, is to look at the degree. A hypergraph has two sorts of degree: the degree of a node, which is the number of hyperedges it is contained in, and the degree of a hyperedge, which is the number of nodes it contains.

Centrality

Hypergraph Partitioning

The hypergraph partitioning problem can be de ned as the task of dividing a hypergraph into two or more roughly equal sized parts such that a cost function on the hyperedges connecting vertices in di erent parts is minimized.
Kernighan-Lin (KL) based heuristics are widely used for graph/hypergraph partitioning because of their short run-times and good quality results.

Florian Ziegler - n-Level Hypergraph Partitioning

Hypergraph in VLSI

A research project about the hypergraph applications in VLSI technologies incl design, simulation, emulation, testing, packaging and more.

Hypergraph Literature

Click here to see a list of hypergraph literature

2017-02-11


Hypergraph Literature

Andrew E.

Hypergraph

Ausiello, Giorgio ; Franciosa, Paolo G. and Frigioni, Daniele: Directed Hypergraphs: Problems, Algorithmic Results, and a Novel Decremental Approach 2001 p17 ............. ok

Berge HYPERGRAPHS Combinatorics of Finite Sets p267.pdf

Berlt A Hypergraph Model for Computing Page Reputation onWeb Collections p15

################################

Brandes Blocks of Hypergraphs applied to Hypergraphs and Outerplanarity p12

Busseniers, Evo: General Centrality in a hypergraph, March 20, 2014, p16 ..................

CHUNG, F. R. K. et al: ON THE FRACTIONAL COVERING NUMBER OF HYPERGRAPHS SIAM J. DISC. MATH. Vol. 1, No. 1, February 1988 p5.

Cooper SPECTRA OF UNIFORM HYPERGRAPHS p32

Emtander, Eric: On hypergraph algebras March 31, 2008 p45

Gallo, Giorgio et al: DIRECTED HYPERGRAPHS AND APPLICATIONS October 1992 p23 .........

Gao Dynamic Shortest Path Algorithms for Hypergraphs p11

Gowers Hypergraph Regularity and the multidimensional Szemeredi Theorem p44

HAN Extremal Hypergraph Theory and Algorithmic Regularity Lemma for Sparse Graphs p117

Haxell An Algorithmic Version of the Hypergraph Regularity Method p6.pdf

Hein The Total Variation on Hypergraphs - Learning on Hypergraphs Revisited p9

Heintz, Benjamin and Chandra, Abhishek: Beyond Graphs: Toward Scalable Hypergraph Analysis Systems 2013 p4

Jin Overlapping Matrix Pattern Visualization: a Hypergraph Approach p10

Katona Hamiltoninan Chains in Hypergraphs A survey p10

Katona, Gyula Y.: Paths and cycles in hypergraphs 2013 p262

Kari Hypergraph Automata A Theoretical Model for Patterned Self-assembly p27.pdf

Kiraly Edge connectivity of undirected and directed hypergraph p143

Pu, Li and Faltings, Boi: Hypergraph Learning with Hyperedge Expansion 2010 p16

Ravindran, B.: Learning with Hypergraphs 2014 p25 ........................ ok

RODL APPLICATIONS OF THE REGULARITY LEMMA FOR UNIFORM HYPERGRAPHS p16

Sarkozy Cycles in Hypergraphs p27

Stell Relations on Hypergraphs p16

Thakur Linear Connectivity Problems in Directed Hypergraphs p51

Warme, David Michael: Spanning Trees in Hypergraphs with Applications to Steiner Trees, PhD Thesis, May 1998, p137........................

Zass Probabilistic Graph and Hypergraph Matching p8

Hypergraph Partitioning

Aykanat, Cevdet; Cambazoglu, B. Barla and Ucar, Bora: Multi-level direct K-way hypergraph partitioning with multiple constraints and fixed vertices p28 2 October 2007

Aykanat, Cevdet; Cambazoglu, B. Barla and Ucar, Bora: Multi-level direct K-way hypergraph partitioning with multiple constraints and fixed vertices p17 2 October 2007

Bezrukov On Partitioning of Hypergraphs p23

Bristow Hypergraph-Partitioning Based Decomposition for Parallel Sparse-Matrix Vector Multiplication p56.pdf

Bulo A Game-Theoretic Approach to Hypergraph Clustering p9

Buluc Graph and hypergraph partitioning p29.pdf

Catalyurek Hypergraph-Partitioning Based Decomposition for Parallel Sparse-Matrix Vector Multiplication p33.pdf

Catalyurek PaToH: Partitioning Tool for Hypergraphs p33 ................... 2

@@@@@@@@@@@@@@@@@@@@@@@@@@@

Choi A semidefinite programming approach to the hypergraph minimum bisection problem p16

Czygrinow PARTITIONING PROBLEMS IN DENSE HYPERGRAPHS p12??? 4

Devine, Karen D.: Parallel Hypergraph Partitioning for Scientific Computing p10

Durairaj Exploiting Hypergraph Partitioning for Efficient Boolean Satisfiability p6.pdf

Fischer Approximate Hypergraph Partitioning and Applications p32

Foscher Approximate Hypergraph Partitioning and Applications p37.pdf

Frank On decomposing a hypergraph into k connected sub-hypergraphs p12

Han Hypergraph Based Clustering in High Dimensional Data Sets A Summary of Results p8

Karypis, George and Kumar, Vipin: hMETIS A Hypergraph Partitioning Package Version 1.5.3 November 22, 1998 p20

Karypis Multilevel k-way Hypergraph Partitioning p15.pdf

Khanna A Hypergraph Partitioning Based Approach for Scheduling of Tasks with Batch-shared I/O p20

Klimmek A Simple Hypergraph Min Cut Algorithm p7

Krishnamoorthy Hypergraph Partitioning for Automatic Memory Hierarchy Management p12

Kucar HYPERGRAPH PARTITIONING TECHNIQUES p29

Lang Unsupervised Coreference Resolution with HyperGraph Partitioning p9

Leordeanu Efficient Hypergraph Clustering p9

Lyaudet NP-hard and linear variants of hypergraph partitioning p21

Miao A Hypergraph-Partitioned Vertex Programming Approach for Large-scale Consensus Optimization p6.pdf

Papa Hypergraph Partitioning and Clustering p38

Rajamanickam An Evaluation of the Zoltan Parallel Graph and Hypergraph Partitioners p16

Rajamanickam Parallel Partitioning with Zoltan: Is Hypergraph Partitioning Worth It p16

Rital, Soufiane; Cherifi, Hocine and Miguet, Serge: K-way Hypergraph Partitioning and Color Image Segmentation p4

RITAL Weighted Adaptive Neighborhood Hypergraph Partitioning for Image Segmentation p10

Selvakkumaran Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization p8.pdf

Sosonkina Hypergraph Partitioning for Parallel Iterative Solution of General Sparse Linear Systems p22

Trifunovi Parallel Multilevel Algorithms for Hypergraph Partitioning p37.pdf

Trifunovic, Aleksandar: : Parallel algorithms for hypergraph partitioning. PhD thesis, Imperial College London, 2006 p233 ...................... 65

Wrighton SAT-Based Optimal Hypergraph Partitioning with Replication p7.pdf

Yaros Imbalanced Hypergraph Partitioning and Improvements for Consensus Clustering p8

Yeh A General Purpose, Multiple-Way Partitioning Algorithm p9.pdf

Zhao An Effective Algorithm for Multiway Hypergraph Partitioning p33.pdf

Zhao An Effective Algorithm for Multiway Hypergraph Partitioning3 p33.pdf

Zhou Learning with Hypergraphs Clustering Classification and Embedding p8.pdf

Ziegler, Florian: n-Level Hypergraph Partitioning, July 27, 2012, p52............

Zien Multilevel Spectral Hypergraph Partitioning with Arbitrary Vertex Sizes p4

Hypergraph Partitioning in VLSI

Adya Improving Mincut Placement for VLSI Using Analytical Techniques p8.pdf

Alpert A HYBRID MULTILEVEL GENETIC APPROACH FOR CIRCUIT PARTITIONING p4.pdf

Alpert A Semi-Persistent Clustering Technique for VLSI Circuit Placement p8.pdf

Caldwell, Andrew E.; Kahng, Andrew B. and Markov, Igor L.: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning 2000 p16

Caldwell, Andrew E.; Kahng, Andrew B. and Markov, Igor L.: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning 2000 p21

Caldwell, Andrew E.; Kahng, Andrew B.; Kennings, Andrew A. and Markov, Igor L.: Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting April 1999 p6

Caldwell Improved Algorithms for Hypergraph Bipartitioning p6.pdf

Catalyurek Multithreaded Clustering for Multi-level Hypergraph Partitioning p12

Cherng a hypergraph based clustering algorithm for spatial data sets p8.pdf

Cong Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation p7.pdf

Gill Genetic Algorithm Based Approach To Circuit Partitioning p7.pdf

Hagen On Implementation Choices for Iterative Improvement Partitioning Algorithms p7.pdf

Ihler Modeling hypergraphs by graphs with the same mincut properties p8.pdf

Kahng Fast Hypergraph Partition p5.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain1 p4.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain2 p4.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain3 p25.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain4 p4.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain5 p4.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain6 p4.pdf

Karypis Multilevel Hypergraph Partitioning Application in VLSI Domain7 p25.pdf

Kennings Analytical Placement of Hypergraphs p10.pdf

Leighton Hypergraph partitioning algorithm p21

Mak A fast hypergraph min-cut algorithm for circuit partitioning p11.pdf

Manikandan Unimodular Hypergraph based clustering approaches for VLSI Circuit Partitioning p4.pdf

Ouyang Multilevel cooperative search application to the circuit hypergraph partitioning problem1 p7.pdf

Ouyang Multilevel cooperative search application to the circuit hypergraph partitioning problem1 p12.pdf

Ouyang Multilevel cooperative search application to the circuit hypergraph partitioning problem2 p7.pdf

Ouyang Multilevel cooperative search application to the circuit hypergraph partitioning problem2 p12.pdf

Ouyang Multilevel cooperative search application to the circuit hypergraph partitioning problem3 p7.pdf

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem1 p10.pdf

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem2 p9.pdf

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem2 p10.pdf

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem p9.pdf

Salce, Daniel and Zobel, Matthew: Multilevel Hypergraph Partitioning p32

Sikand Implementation of Multi-Way Partitioning Algorithm p5.pdf

Sinha Experimental Study of A Novel Variant of Fiduccia Mattheyses(FM) Partitioning Algorithm p6.pdf

Tan Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis p4.pdf

THIYAGARAJAN HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS p5.pdf

Wong Clustering Based Acyclic Multi-way Partitioning p4.pdf

Yan SafeChoice A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement p14.pdf

Zhou Learning with Hypergraphs: Clustering, Classification, and Embedding p8

Other Hypergraph Operations

Alon Approximate Hypergraph Coloring p15

Catalyurek Multithreaded Clustering for Multi-level Hypergraph Partitioning p12.pdf

Cheng ENISLE A Clustering Algorithm for Nearly Maximal and Minimal Connection on Hypergraph p10.pdf

CHUNG ON THE FRACTIONAL COVERING NUMBER OF HYPERGRAPHS p5

Eschbach Orthogonal Hypergraph Routing for Improved Visibility p4.pdf

Frieze Coloring simple hypergraphs p35

Gogoi Algorithm to color a Circuit Dual Hypergraph for VLSI Circuit p6.pdf

Kari Hypergraph Automata: A Theoretical Model for Patterned Self-assembly p27

PLUHAR GREEDY COLORINGS OF UNIFORM HYPERGRAPHS p6

Rusnak Oriented Hypergraphs: Introduction and Balance p29

Schwarz RATIO CUT HYPERGRAPH PARTITIONING USING BDD BASED MBOA OPTIMIZATION ALGORITHM p10

Sponemann Counting Crossings for Layered Hypergraphs p7.pdf

Terminology

Literature


Hypergraph for 3D IC Design

hypergraph in VLSI
hypergraph in ic
hypergraph in integrated circuits

hypergraph in 3d ic
hypergraph in 3d integrated circuits
hypergraph in three dimensional integrated circuits
hypergraph in 3d VLSI
hypergraph in three dimensional VLSI

hypergraph is applied in

  • partitioning
  • floor planning
  • placement
5W1H

Why hypergraph:

When hypergraph

Who hypergraph

What hypergraph

How hypergraph

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Hypergraph

Ababei, Cristinel; Mogal, Hushrav , and Bazargan, Kia: Three-dimensional place and route for FPGAs p10‖ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, Jun. 2006, pp. 1132-1140.. ............5

AbabeiYYY Placement and Routing in 3D Integrated Circuits p10.pdf

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

I. INTRODUCTION

........................

For the standard cell technology, [13] recently proposed a placement and global routing tool as well as a 3D layout editor. The placement algorithm is based on recursive min-cut partitioning of the circuit represented as a hypergraph and follows the same idea as in the Capo placer [23]. Interlayer via minimization is sought by using min-cut partitioning for layer assignment and wire-length (WL) minimization is done by considering the aspect ratio during partitioning. The user can select either hMetis [25] or PaToH [26] as the partitioning algorithm. Their global routing algorithm is a concurrent approach based on the idea in [24]. It was shown that 28% (51%) wire-length improvement could be obtained with two (five) layers, compared to [31] (the improvement is only 7% (17%) when inter-layer via minimization is the main objective). Wire-length reduction of up to 74% was reported in [33]. Deng and Maly showed – using a placement algorithm based on Capo – that the total wire-length can be reduced by 16% compared to flat placement, when two-layer integration is used [27]. It is important to note that current technologies allow for chemical mechanical polishing (CMP) substrate thinning down to about 5-10μm, hence allowing for multiple thin active device layers and interconnect levels be stacked on top of each other, resulting in short inter-layer vias with small aspect ratios [15].

III. PLACEMENT ALGORITHM

The simplified pseudo-code of the partitioning-based placement algorithm is shown in Fig. 2. In the first stage the circuit netlist undergoes the initial min-cut partitioning and assignment to layers. The second main phase is the actual placement of cells on all layers. In this section we present in more detail the two main steps of our placement algorithm.

Input:
Tech mapped netlist .net G(V,E)
Architecture description file
Algorithm:
1. Initial min-cut partitioning into layers
for via minimization
2. For all layers i = 0 to L-1 from top to bottom
3. Do partitioning based placement of layer i
4. Update timing slacks
5. Re-enumerate critical paths
6. Greedy overlap removal
7. Constraint generation for layers below
8. Write .p placement output file
Fig. 2. Pseudo-code of TPR placement algorithm.

A. Initial Partitioning and Assignment to Layers The initial partitioning-into-layers step is performed using the min-cut hMetis partitioning algorithm [25] and is further illustrated in Fig. 3. This is motivated by the limitations imposed by current technologies, which require us to minimize the usage of vertical connections (it was also observed in [14] that optimizing inter-layer interconnect is of key importance for 3D integration technologies).

Fig. 3. Illustration of initial partitioning and assignment to layers

After the initial partitioning into layers we assign blocks (i.e., partitions) to layers using a linear placement technique. The goal of this step is to minimize both the total vertical wire-length and maximum cut between any two adjacent layers. For example, in Fig. 4, we would like to assign the five blocks (as a result of the initial 5-way min-cut partitioning) to layers of the 3D architecture as in the case labeled “Good” rather than in the case labeled “Bad”. That is because the good layer assignment minimizes both the total wire-length and maximum cut between adjacent layers.

Fig. 4. Illustration of good and bad initial linear placement of partitions into layers.

The objective of minimizing the total vertical wire-length and maximum cut between any two adjacent layers is equivalent to minimizing the bandwidth of the EV-matrix associated to the layer-blocks graph which resulted from the above partitioning [38]. Edges of this graph have weights given by the number of edges of the initial netlist graph, which span different layer-blocks. The EV-matrix is an m×n matrix where m – the number of rows – is the number of edges in the graph and n – the number of columns – is the number of nodes. An element a(i, j)=1 in the matrix is nonzero if the j-th node is a terminal of the i-th net. If a node is not a terminal for a net, the corresponding EV-matrix element is zero. The bandwidth of a matrix is defined as the maximum distance between first and last non-zero entries, among all rows. An example of such a layer-blocks graph and its associated EV-matrix are presented in Fig. 5. In this example the bandwidth equals four due to second row, which has its first non-zero entry in the second column and its last nonzero entry in the sixth column.

Fig. 5. Layer-blocks graph and its associated EV-matrix.

The bandwidth minimization problem is known to be NPcomplete [38] and a solution for the layer assignment problem may not be optimal in terms of both objectives of wire-length and maximum cut between adjacent layers. Therefore, for this step, we use an efficient heuristic [37], which is able to find solutions with very good trade-off between wire-length and maximum cut. This technique is briefly described in what follows using the graph example shown in Fig. 5. We first build the EV-matrix, and then transform it into an as-close-aspossible to a band-form matrix. This problem is denoted as B(EV-matrix)-min problem (i.e., minimization of the bandwidth of the EV-matrix problem). The procedure to solve this problem uses row and column flips in order to sort rows and columns such that non-zero elements are moved towards the main diagonal. For example, for the matrix shown in Fig. 6, in order to “drift” non-zero elements from the upper half towards the main diagonal (i.e., from right to left) column flips are performed between columns 2 and 3 and then column 6 is moved between columns 3 and 4. This technique is performed to move non-zero elements from right to left and from top to bottom (for the upper right half) and from left to right and from bottom to top (for the lower left half). When the above procedure finishes, the example from Fig. 5 becomes as described in Fig. 6. A more detailed description can be found in [37]. The goal of getting the matrix to a bandform (which translates into a best linear ordering) serves two objectives:

--Cutsize minimization – by having all 1’s in the matrix clustered along the main diagonal, the cutsize (the number of nets cut by a vertical cut applied between any two consecutive nodes in the linear arrangement) is minimized everywhere in the linear arrangement

-- WL minimization – by minimizing the bandwidth (maximum distance spanned by any of the nets) of the EVmatrix, the total wire-length of all nets is minimized.

Fig. 6. Illustration of the EV-matrix band-width minimization for both wire-length and maximum cut between adjacent layers.

B. Placement Method

After the initial layer assignment, placement is performed on each layer starting with the top layer (layer 0) and continuing downwards till the last layer (layer L-1). The placement of every layer is based on edge-weighted quadpartitioning using the hMetis partitioning algorithm, and is similar to the approach in [29], which has the same quality as VPR but at 3-4 times shorter run times. Edge weights are usually computed inversely proportional to the timing slack of the corresponding nets. However, we also selectively bias weights of the most critical nets. The set of critical nets is comprised of edges on the current k-most critical paths. The placement algorithm has an integrated static timing analysis engine as well as a path enumeration algorithm [30]. The delay of the circuit (and therefore slacks) and the set of the most critical paths are periodically updated based on the delay assigned to all current cut nets by the partitioning engine. This ensures accurate estimation of the circuit delay as the placement algorithm progresses. The rate of delay update and critical paths re-enumeration is dictated by the runtime / estimation accuracy trade-off.

The recursive partitioning of a given layer stops when each placement region has less than four blocks. Complete overlap removal is done using a greedy heuristic which moves noncritical blocks (i.e., not on any critical paths) to the closest available empty location. When the placement of a layer is finished, we propagate placement constraints for the most critical nets. For example, assuming that layer k0 is the first layer (from the top) in which some terminals of a critical net are placed, the bounding box of the net is cumulatively projected to lower layers k0+1 through L-1 as a placement constraint for the rest of the terminals of the net in these layers. In special cases such as when two terminals are placed very closely on layer k0 and the projected bounding box on layers below is not large enough to accommodate all the terminals, there may be more terminals constrained inside a region which would not have enough CLB’s available to accommodate all the constrained terminals. If this situation is relatively relaxed (meaning that there are not too many such terminals or the constraint area is not too small) then they will translate in overlaps which will be removed at the end of the recursion. If the situation is such that more cells cluster together by being constrained in a relatively small area, then they will be eventually split during the partitioning process so that the unbalance factor will be satisfied but they will still be in proximity of each other. In both the above cases projected terminals will end up being close to each other.

In layers that have net bounding box constraints, terminals that have placement restrictions are fixed in appropriate partitions before a call to the hMetis partitioning engine. This technique explicitly minimizes the 3D bounding-boxes of critical nets, which leads to minimization of the total wirelength and circuit delay. Steps 3 to 8 of the algorithm shown in Fig. 2 are performed for all layers, and when the last layer is finished the circuit is completely placed.

Hypergraph

Alpert A HYBRID MULTILEVEL GENETIC APPROACH FOR CIRCUIT PARTITIONING p4.pdf

Alpert A HYBRID MULTILEVEL GENETIC APPROACH FOR CIRCUIT PARTITIONING p6.pdf

Hypergraph
Alpert Multilevel Circuit Partitioning p14.pdf

Hypergraph
Alpert, Charles J. and Kahng, Andrew B.: Recent directions in netlist partitioning a survey INTEGRATION, the VLSI journal 19 (1995) 1 81 p81.
okokok

Hypergraph

Armstrong, Edward: An Investigation of Parallel Methods for VLSI Circuit Partitioning, Master Thesis, December, 2013 p128 ...................... 86

Armstrong An Investigation of Parallel Methods for VLSI Circuit Partitioning p128

hypergraphs

1.2 The Circuit-Partitioning Problem

The circuit-partitioning problem is an applied case of hypergraph partitioning, as it pertains to the VLSI design process. A VLSI circuit is represented by a hypergraph H(V; E), where V = fvij1  i  ng is the set of vertices denoting modules, and E = fej j1  j  mg is the set of edges denoting nets. Note that a given net e is de ned to be a subset of V. A partitioning, P, of the circuit consists of distributing jVj modules into k blocks B1;B2; : : : ;Bk, where V = [k i=1Bi and Bi \ Bj = ;; i 6= j.

The cut-size is the cardinality of the collection of nets which have incident modules in more than one block. To elaborate, let block(m), be the the block in which module m is located; a net is considered cut if there exists two modules incident on the net are in disjoint blocks, cut(e) = 9fv1; v2j(v1 2 e) ^ (v2 2 e) ^ (block(v1) 6= block(v2))g. The cut-size then becomes the sum of all cut nets, cutsize(P) = jf8e 2 Ejcut(e) = truegj.

This thesis will deal with the hypergraph bi-partitioning problem, which is the hypergraph partitioning problem with number of blocks, k = 2. Given a balance criteria 0:0   1:0 the goal is to nd a partition P = fB1; B2g such that cut(P) is minimized and balance as set out by Equation 1.1 is satis ed. Typically a balance criteria of  0:1 is chosen [4].

(0:0  1 ?? jB1j=jVj  ) ^ (0:0  1 ?? jB2j=jVj  ) (1.1)

Figure 1.1: Hypergraph representation of a circuit.

Figure 1.1 outlines three hypergraph representations of a circuit with eight vertices and ve edges. Fig. 1.1(a) illustrates the raw hypergraph, while in Fig. 1.1(b) and Fig. 1.1(c) the set of edges has been divided into two disjoint subsets, known as blocks. Note that any nets that are connected to incident cells which are in di erent blocks cause the net to be cut. This is the case with both nets 2 and 3 in Fig. 1.1(b), and causes the partition to have a cut-size of two. Fig. 1.1(c) is preferred, as it reduces the cut-size to one.

.......................

2.3 Fiduccia-Mattheyses

The Fiduccia-Mattheyses (FM) algorithm is a well-known iterative heuristic for bi-partitioning hypergraphs [25]. This algorithm has linear time complexity, and is capable of working within balance constraints by performing single module moves between pairs of blocks. Its linear runtime is possible due to the use of a Bucket List (detailed in Section 2.3.3) for determining the next best module to move.

De nition 2.1 - Free and Locked Cells: The count of free modules for a given net, Nj , in a given block, Bf , is calculated as phi () in Equation 2.1. The count of locked modules for a given net, Nj , in a given block, Bf , is calculated as lambda () in Equation 2.2. Reviewing from Section 1.2, a given net e is de ned to be a subset of the hypergraph's vertices, V. This is to say that each net is de ned as a collection of vertices, e  V.

(Nj ;Bf ) = jfcjc 2 Bf and c 2 Nj and c is free gj (2.1)
(Nj ;Bf ) = jfcjc 2 Bf and c 2 Nj and c is locked gj (2.2)
[59] A. Trifunovic. Parallel algorithms for hypergraph partitioning. PhD thesis, Imperial College London, 2006.

Hypergraph

Caldwell, Andrew E; . Kahng, Andrew B. and Markov, Igor L.: Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning . Jan 2000 p16..................

Caldwell, Andrew E; . Kahng, Andrew B. and Markov, Igor L.: Caldwell Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning . Jan 2000 .p21................................

Hypergraph

Caldwell, Andrew E. et al: Hypergraph Partitioning for VLSI CAD Methodology for Heuristic Development, Experimentation and Reporting 1999 p6.

Caldwell Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting p6

Hypergraph

Chen, Yi-Hang; Chen, Yi-Ting and Huang, Juinn-Dar: Parallel Layer-Aware Partitioning for 3D Designs SASIMI 2013 Proceedings p4

Hypergraph

II. Proposed Algorithm

A. Problem Formulation

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

A design is modeled as a hypergraph G = (V, E), where V is a set of vertices including a set of functional cells C and a set of I/O pads I (i.e., V = C ?? I, C ?? I = ?? ); and E is a set of hyperedges. For each vertex v ?? V, area(v) denotes the area cost of v. A k-layer disjoint partition set of G with all the I/O terminals residing in the bottom-most layer is represented as L = {L0=I, L1, L2 … Lk}, where Li is the partition assigned to the i-th layer and is a subset of C. For each layer Li, ALi denotes the summation of area(v), ?? v ?? Li. And Aavg is used to indicate the average of the total area in the k layers, which is calculated by:

???????? = ???????? ????????(??)/??.
We further define the area constraint as:
???????? × (1 ?? r) ?? A???? ?? ???????? × (1 + r)
with a balanced ratio r, 0 < r < 1, for balancing the area of layers.

Hypergraph
Chen Tutorial on VLSI Partitioning p43

Hypergraph
Cong, Jason and Luo, Guojie: A 3D Physical Design Flow Based on OpenAccess May 2009 p5 .................. 3
Jason Cong1,2, Fellow, IEEE, and Guojie Luo1, Student Member, IEEE 1Computer Science Department, University of California, Los Angeles, CA 90095, USA 2California NanoSystems Institute, Los Angeles, CA 90095, USA {cong, gluo}@cs.ucla.edu

III. COMPONENTS IN 3D-CRAFT

B. Multilevel Placement for 3D ICs (mPL-3D)

Given a circuit represented as a hypergraph H ? (V,E) , the placement region R , and the number device layers K , the task of 3D placement problem is to assign every cell iv ?V a triple ( , , ) i i i x y z , which indicates that this cell is placed on the device layer {1,2, , } iz ? K K with its center at ( , ) . i i x y ?R The objective is to minimize the weighted sum of total wirelength and TS via number, under the non-overlap constraints and the TSV density constraints in each tier.

minimize ( , , ) ( ) ( )
subject to non-overlap constraints
(TSV density constriants) e E
OBJ x y z l e ? v e
?
?? ? ?

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

L. Cheng, L. Deng, and M. D. Wong, “Floorplanning for 3D VLSI design,” Proceedings of IEEE/ACM ASP-DAC 2005, pp. 405-411, 2005.

J. Cong and G. Luo, “A Multilevel Analytical Placement for 3D ICs,” Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 361-366, 2009.

W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, 2005.

B. Goplen and S. Sapatnekar, “Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach,” Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, pp. 86-89, 2003.

A.S. Grove, “Physics and Technology of Semiconductor Devices,” John Wiley & Sons, Inc., Hoboken, NJ, 1967.

Z. Li, X. Hong, Q. Zhou, Y. Cai, J. Bian, H. H. Yang, V. Pitchumani, and C.-K. Cheng, “Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization,” IEEE Trans. Circuits and Systems I, Vol.53, issue 12, pp. 2637-2646, 2007.

Y. Ma, X. Hong, S. Dong and C.K.Cheng, “3D CBL: an Efficient Algorithm for General 3-Dimensional Packing Problems,” Proceedings of the 48th MWS-CAS 2005, Vol. 2, pp. 1079- 1082, 2005.

P. Wilkerson, A. Raman, and M. Turowski, “Fast, Automated Thermal Simulation of Three-Dimensional Integrated Circuits,” ITherm 2004, Las Vegas, Nevada, 1-4 June 2004.

H. Yan, Q. Zhou, and X. Hong, “Thermal Aware Placement in 3D ICs Using Quadratic Uniformity Modeling Approach,” Integration, the VLSI Journal, vol. 42, no. 2, pp. 175-180, 2009.

T. Yan, Q. Dong, Y. Takashima, and Y. Kajitani, “How Does Partitioning Matter for 3D Floorplanning?,” Proceedings of the 16th ACM GLS-VLSI , pp.73-78, 2006.

http://OpenEDA.Si2.org

http://www.gaisler.com

http://www.magma-da.com

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Cong, Jason , and Luo, Guojie: A Multilevel Analytical Placement for 3D ICs 2008 p6

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Cong, Jason; Labio, Wilburt and Shivakumar , Narayanan: Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation 1994 ACM 0-89791-690-5/94/0011/0056 p7

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Cong Thermal-Aware 3D IC Placement Via Transformation p6.pdf

Cong Thermal-Aware 3D IC Placement Via Transformation p20.pdf

Jason Cong, Guojie Luo, Jie Wei, and Yan Zhang. Thermal-aware 3d ic placement via transformation. In Proc. Asia and South Paci c Design Automation Conf. ASP-DAC 2007, pages 780-785, 2007.

2. PROBLEM FORMULATION

Given a hypergraph H = (V, E), device layer number K, and a 2D placement P, the thermal-aware 3D placement transformation problem is to assign a position (xi, yi, zi) to every cell vi, so that the total wirelength and the TS via number are minimized, subject to constraints such as non-overlap constraints, temperature constraints, etc.

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Cong, Jason; Luo,Guojie and Shi, Yiyu: Thermal-Aware Cell and Through-Silicon-Via Co-Placement for 3D ICs p6

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Das, Shamik: Design Automation and Analysis of Three-Dimensional Integrated Circuits, PhD thesis, May 2004, p176 .................

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Chapter 2 Design Tools forThree-Dimensional IntegratedCircuits

2.4 Placement

.................................

2.4.5 Placement Algorithm: Partitioning

Formally, the circuit or sub-circuit is represented as a hypergraph H = (V,E), where V is a set of vertices representing the standard cells and E  2V is a set of hyperedges with a one-to-one mapping of hyperedges to nets in the circuit. Each vertex v 2 V is assigned a weight w(v) equal to the width of the cell, and each hyperedge e 2 E may be assigned a weight w(e) (though this is typically taken to be w(e) = 1). A two-way partitioning is then defined to be a map

p : V 7! {0, 1} . (2.9)

The partitions themselves are called 0 and 1; p(v) for some v may be fixed to 0 or 1 if v is an I/O pin or immovable cell (or in the case of sub-circuits, if the cell is external to the sub-circuit [48]). The partitioning is called valid if it satisfies a balance criterion on the sums-of-weights

Wi =
X
p(v)=i
w(v) (2.10)

such as |W0 ?W1|   (W0 +W1), where  is called the tolerance.

We define
c(e) =
8<
:
w(e) 9v1, v2 2 e|p(v1) = 0 ^ p(v2) = 1
0 otherwise
(2.11)

as the cut weight of edge e. In other words, c(e) is the weight w(e) if e contains vertices in both partitions, and zero otherwise. The cut of partitioning p is defined as

c(p) =
X
e2E
c(e). (2.12)

A min-cut partitioning of H is thus a valid partitioning p with the least cut c(p).

The problem of determining a two-way min-cut partitioning is NP-complete [49]; there are several heuristic algorithms. The vast majority of these are based on the Fiduccia- Mattheyses (FM) algorithm [50], which is itself an efficient variation of the Kernighan-Lin algorithm [51]. In FM partitioning, an initial (possibly invalid) partitioning p0 is chosen. A number of iterations of the outer FM loop generate partitionings pn, n = 0, 1, 2, . . ., where pi?1 is improved to pi in the ith pass of the loop. A single loop iteration consists of the formation of a list of the vertices in V . The list is ordered by the gain g(v); g(v) is the net improvement in cut if vertex v is moved to the opposite partition. The list is traversed in order, with the gains updated after each move. At the end of the traversal, the point in the list at which the minimum cut was reached is determined, and the moves after that point are reversed. The remaining moves constitute the improvement of pi?1 to pi; if the cuts c(pi) and c(pi?1) are equal, then there is no improvement, and FM stops.

FM is thus an iterative-improvement-based heuristic method; it is known that the quality of FM partitionings degrades somewhat with an increase in hypergraph size, mainly due to the inability of the FM algorithm to reach a large part of the solution space [52]. Thus, multi-level FM techniques have been proposed that are themselves recursive [52–54].

===============================================

2.7 PR3D: The Placement and Routing Tool

.............................

2.7.1 3-D Standard-Cell Placement Algorithm

For the reasons outlined in Section 2.4, we have implemented PR3D as a partitioning-driven placement tool. Thus, our placement framework consists of the embedding of a hypergraph representation of a netlist into a rectangular block that represents the available die area. We assume that the dimensions of the block (number of rows, width of each row) are fixed a priori (i.e. a fixed-die context). For 3-D integration, given a set number of device layers (specified at run-time by the user), we adjust the number of rows and widths of each row (prior to execution) such that the total area available for placement remains the same as in 2-D and the aspect ratio for each device layer is the same as in 2-D.

We proceed by recursively partitioning the block roughly into halves, assigning nodes to each partition such that the capacity of each partition is not exceeded and the number of hyperedges spanning both partitions is minimized. Each partitioning step is permitted a tolerance varying from 2% to 20% depending on the discreteness of the partition. Partitioning into wafers or parallel to rows, for example, must be done very precisely since the resulting partition sizes must be integral numbers of rows or wafers, but when partitioning perpendicular to rows, a higher tolerance will yield a better partitioning.

===============================================

Chapter 4 Performance Characteristics of 3-D ICs

4.2 Tool Adaptations for Performance-Driven Design

..................................

As Chapter 2 describes, the core placement algorithm is refinement by recursive bisection of the net list. Specifically, the circuit net list is represented by a hypergraph, with standard cells becoming nodes and wires becoming hyperedges. The die area is partitioned recursively into halves such that the number of nets crossing any partition is minimized [48].

===============================================

A. E. Caldwell, A. B. Kahng, and I. L. Markov. Improved algorithms for hypergraph bipartitioning. In Proc. ASP-DAC, pages 661–666, 2000.

U. V. Catalyurek and C. Aykanat. Hypergraph-partitioning-based decomposition for parallel sparse-matrix vector multiplication. IEEE Transactions on Parallel and Distributed Systems, 10(7):673–693, 1999.

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Applications in VLSI design. In Proceedings of the 34th Design Automation Conference, pages 526–529, 1997.

Hypergraph
Das, Shamik; Chandrakasan, Anantha and Reif, Rafael: Design Tools for 3-D Integrated Circuits Nov 2002 p4 ..........
Shamik Das
M.I.T., Department of E.E.C.S.
60 Vassar St. Room 39-625
Cambridge, MA 02139
e-mail: shamikd@mit.edu
Anantha Chandrakasan
M.I.T., Department of E.E.C.S.
50 Vassar St. Room 38-107
Cambridge, MA 02139
e-mail: anantha@mtl.mit.edu
Rafael Reif
M.I.T., Department of E.E.C.S.
50 Vassar St. Room 38-427
Cambridge, MA 02139
e-mail: reif@mtl.mit.edu

II. 3-D Standard Cell Tool Design

A. 3-D Standard Cell Placement

............................

Thus, our placement framework consists of embedding a hypergraph representation of a netlist into a rectangular block that represents the available die area. Each node of the hypergraph is a cell and the weight of each node is the cell area. Hyperedges correspond to electrical nets. We assume that the dimensions of the block (number of rows, width of each row) are fixed a priori (i.e. a fixed-die context). For the 3-D case, given a set number of device layers (specified at run-time by the user), we adjust the number of rows and widths of each row (prior to execution) such that the total area available for placement remains the same as in the 2-D case and the aspect ratio for each device layer is the same as in the 2-D case.

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

U. V. Catalyurek and C. Aykanat. Hypergraph-partitioningbased decomposition for parallel sparse-matrix vector multiplication. IEEE Transactions on Parallel and Distributed Systems, 10(7):673–693, 1999.

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Applications in VLSI design. In Proceedings of the 34th Design Automation Conference, pages 526–529, 1997.

Hypergraph
Das, Shamik; Chandrakasan, Anantha and Reif, Rafael: Timing, Energy, and Thermal Performance of ThreeDimensional Integrated Circuits p6 ............... GLSVLSI’04, April 26–28, 2004, Boston, Massachusetts, USA.

Shamik Das, Anantha Chandrakasan, and Rafael Reif
Microsystems Technology Laboratories
Massachusetts Institute of Technology
60 Vassar St. Rm. 39625
Cambridge, MA 02139
shamikd,anantha,reif@mtl.mit.edu

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

3. PLACEMENT BASED METHODOLOGY

3.1 The Placement Tool

We have previously developed a placement and routing tool for 2-D (i.e. conventional) and 3-D integrated circuits [9]. Called PR3D, this tool is capable of targeting standard-cell designs for a single wafer or for multiple wafers. PR3D, as a conventional wire-length-driven placement tool [10], is competitive with modern industry and academic tools such as Dragon [11], Capo [12], and Cadence Silicon Ensemble. As a design tool for 3-D ICs, PR3D is capable of wire-length-driven placement onto a user-specifiable number of wafers with inter-wafer interconnect parasitics that are also user-specified.

The core placement algorithm is refinement by recursive bisection of the net list. Specifically, the circuit net list is represented by a hypergraph, with standard cells becoming nodes and wires becoming hyperedges. The die area is partitioned recursively into halves such that the number of nets crossing any partition is minimized [13].

=====================================================

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Dutt Probability-Based Approaches to VLSI Circuit Partitioning p16

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Ellis-Monaghan, Joanna A.: Graphs in Chip Design - Graph Theoretical Problems in Next-Generation Chip Design 5/19/03 p17 ...................

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Introduction

.................................

Netlist partitioning is a fundamental part of the process of chip design. The size of a netlist, upwards of 3 million functional elements today, makes it computationally intractable. Thus, the netlist must be partitioned into more tractable components, while considering the delays on the wires. This amounts to a hypergraph partitioning problem that is NP hard. Since an optimal solution is not feasible, the goal is to find fast approximation heuristics for partitioning the netlist while respecting the delays.

Basic Definitions

......................................

A signal is a set of pins, no two of which are in the same gate, and exactly one of which is an output pin on its gate, which is also called the source pin of the signal. Thus, if we ignore the input/output information, a signal can be thought of as a hyperedge on the pins it connects. The size of a signal is the number of pins in it (from 2 to 1,000, with a mean of 3.5). Each pin is in at most one signal.

......................................

Some Approximating Reductions

Note that, as described above, a netlist is a hypergraph on the set of pins, such that each pin is in exactly two hyperedges (a gate and a signal), together with the delay information. However, as with any complex problem, it is often productive to reduce the general problem by choosing models that, although perhaps less accurate, are more tractable. In various contexts, researchers have simplified the above model in several ways. Among these are treating the gates as the vertices of a hypergraph — in other words, contracting the hyperedge associated with each gate to a single point. Further, each signal hyperedge may be replaced by a clique or directed claw.

Similarly, the topology of the wiring space may be simplified, for example by approximating it by a grid, or by one or more layers of grids, or even by several planar layers, ignoring orthogonality. It may be modeled by a grid in which edges are allowed to cross at grid points (see [Tho83] for a formalization). In some approaches, the delay information may be ignored, at least temporarily.

Results that apply to such approximating structures, if they can be made to inform the original problem, are potentially beneficial to the industry.

...........................................

Netlist Partitioning

Because a netlist can contain several million pins, the most natural approach is to subdivide it into more manageable portions. The basic idea is to do the placement and routing of smaller pieces separately and then make the necessary connections between these larger components. The difficulty is that after these larger components have been placed, it may be problematic to route the connecting wires, or it may not be possible to meet the delays between pins in different components.

Thus, the goal is to partition the gates in the netlist so that a minimum number of signals have gates in different parts of the partition. Furthermore, the partitions cannot be very uneven in size. Since in this context the netlist is simply a hypergraph with the gates as the vertices and the signals as the hyperedges, this is a question of hypergraph partitioning. However, even graph bisection into bounded sets is NP hard (see [GJS76], and for the hardness of approximation see [ALMSS92]), so optimal netlist partitioning is unfeasible. Alpert and Kahng [AK95] provide a comprehensive survey of both problem formulation and solution approaches to netlist partitioning. Combinatorial approaches include max flow/min cut, labeling, and covering. An important consideration in modeling the problem is that reducing the hypergraph structure to a graph model may fail to adequately capture essential characteristics, in particular the delays. For example, if the signals are converted to cliques, Ihler, Wagner, and Wagner [IWW93] have shown that there is no satisfactory assignment of weights to the clique edges to model the cost of cutting the hyperedge.

However, there are graph and hypergraph partitioning algorithms such as METIS and hMETIS that show experimental success (see [KAKS99]). Also, for graphs, under certain conditions such as edge density, there are polynomial time approximation algorithms for NP problems, many based on the algorithmic version of the graph regularity lemma of [ADLRY94]. Analogously, an algorithmic regularity lemma for hypergraphs was given in [CR01], and applied to hypergraph partitioning in [Czy02]. The challenge remains in the possibility of adapting such techniques for practical application to the partitioning problem.

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

Measuring Congestion

.........................................

Furthermore, the problem actually requires something more specific: what might be described as the thickness-dependent area of a hypergraph. The number of wiring layers available is known. The question then becomes how to find a hypergraph measure that, given the number of wiring layers, returns the minimum area on the placement layer necessary to embed the hypergraph.

Working along these lines, Wood [Woo], by modifying geometric thickness slightly to allow each edge to have a single bend, has shown that O m layers are required above a grid of size éê nùú ′ éê nùú , where m is the number of edges and n is the number of vertices of a graph. Furthermore, he provides an algorithm that with high probability produces a drawing in O(mlog3 nlog logn) time. Archdeacon [Arc], has also proposed (and found some preliminary bounds for) the grid-width as a possible measure, where the grid-width of a graph G is the smallest number n such that G is a minor of a two-layer n′ n grid.

Since congestion is a consequence of the interconnectedness of the netlist, it also seems reasonable that various measures of graph and hypergraph connectivity might inform this problem. The most common connectivity measures, edge and vertex connectivity, are too sensitive to local phenomena to measure global congestion. More promising candidates include tree- and pathwidth and the bramble number. Excellent surveys of these more complex measures can be found in [Ree97] and [Bod93]. In general, connectivity measures need to be adapted to account for the hypergraph structure, the delays, and the computational magnitude of the problem; as always, the challenge remains bridging the gap between theory and practice.

Identifying Localized Congestion

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

One possible approach to this problem would be to consider the restrictions inherent in the topology of the wiring space. For example, obstruction sets for hypergraph planarity have recently been determined [Deb02]. It would be very useful to find the set of hypergraph obstructions in the wiring space, since such structures would then be known to be impossible to place and wire. Even a partial list of such obstructions would be of benefit to the industry, since structures containing any of them might then be avoided even in the design stage and thus would never appear in a netlist.

Automating Small Configurations

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

The “inverse” problem of determining whether it is possible and, if so, how to fit a given hypergraph into a fixed volume is also of interest. Significant progress has. recently been made for doing something very close to this in [BCMW], at least in the case of three-dimensional grid drawing. [BCMW] gives an exact formula for the maximum number of edges possible in a graph drawn in a three-dimensional grid of fixed dimensions. However, grid-drawings permit vertices to lie on any lattice point, not just the placement layer: They permit both vertical and horizontal movement on the wiring layers; and they apply only to graphs, not general hypergraphs. Thus, more work must be done to adapt such techniques to the exact demands of the placement and routing problem.

[Czy02] A. CZYGRINOW, Partitioning problems in dense hypergraphs, Discrete Applied Mathematics, 116, 179-191, 2002.

[Deb02] M. DEBOWSKI, Results on planar hypergraphs and on cycle decompositions, Master’s Thesis, University of Vermont, 2002.

Netlist Hypergraph
Eschbach Orthogonal Hypergraph Routing for Improved Visibility p4

Netlist Hypergraph

Fischbach, Robert; Lienig, Jens and Meister, Tilo: 3D Physical Design Challenges and Solutions p6............2

FischbachYYY 3D Physical Design Challenges and Solutions p6.pdf
Robert Fischbach, Jens Lienig, Tilo Meister
Dresden University of Technology
Institute of Electromechanical and Electronic Design, Dresden, Germany
www.ifte.de
Email: {fischbach, lienig, meister}@ifte.de

routing graph

netlist hypergraph

minimum spanning tree (MST)

Slicing Tree

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

3 Placement

.................................

Besides accounting for thermal issues, 3D placement also requires new placement methodologies. One of the first 3D placement approaches is presented in [4]. Here, a netlist hypergraph is embedded into the layout area. A recursive bipartitioning procedure is used to assign nodes of the hypergraph to the partitions with partition’s capacities taken into account. The partitioning in vertical direction (z direction) correspondents to tier assignment. Thermal constraints are not considered in this approach.

L. Cheng, L. Deng, and M. D. F. Wong. Floorplanning for 3-D VLSI design. In ASPDAC, pages 405–411, 2005.

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Gogoi Algorithm to color a Circuit Dual Hypergraph for VLSI Circuit p6

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Hsu, Meng-Kai; Chang, Yao-We and Balabanov, Valeriy: TSV-Aware Analytical Placement for 3D IC Designs DAC'11, June 5-10, 2011, San Diego, California, USA 2011 ACM 978-1-4503-0636-2/11/06 p6 ........................

Hsu TSV-Aware Analytical Placement for 3D IC Designs p6.pdf
Meng-Kai Hsu1, Yao-Wen Chang1;2, and Valeriy Balabanov1
1Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan
2Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
kaie@eda.ee.ntu.edu.tw; ywchang@cc.ee.ntu.edu.tw; balabasik@gmail.com

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Placement

2. PROBLEM FORMULATION

The 3D placement problem can be formulated as a hypergraph H = (V;E) placement problem. Let vertices V = {v1; v2; :::; vn} represent blocks, and hyperedges E = {e1; e2; :::; en} represent nets. Let xi and yi be the respective x and y coordinates of the center of block vi, and zi be the device layer to which vi belongs. Given a placement region and the number of device layers k, we intend to determine the optimal positions of movable blocks so that the total wirelength and the number of required TSVs are minimized while satisfying the non-overlapping constraints among blocks and TSVs. Like traditional 2D placement, the 3D placement problem is usually solved in three stages [7], (1) global placement, (2) legalization, and (3) detailed placement. Global placement evenly distributes the blocks and finds the best position and layer for each block to minimize the target cost (e.g., wirelength, TSV counts). Then, legalization removes all cell overlaps for each layer. Finally, detailed placement refines the 3D placement solution.

Hypergraph

Johannes, Frank M.: Tutorial: Partitioning of VLSI Circuits and Systems, Proc. ACM/IEEE Design Automation Conference, 1996, pp. 83-87. DAC 96 - 06/96 Las Vegas, NV, USA
Frank M. Johannes
Institute of Electronic Design Automation
ECE Department, Technical University of Munich
Arcisstr. 21, D-80333 Munich, Germany
E-mail: Johannes@e-technik.tu-muenchen.de

Hypergraph

Kahng, Andrew B.: Futures for Partitioning in Physical Design p30

Kahng, Andrew B. : Futures for Partitioning in Physical Design p4

UCLA Computer Science Department, Los Angeles, CA 90095-1596
abk@cs.ucla.edu

http://vlsicad.cs.ucla.edu

http://vlsicad.cs.ucla.edu/~abk

Abstract

The context for partitioning in physical design is dominated by two concerns: top-down design and the focus on spatial embedding. The role of partitioning is exactly that of a facilitator of divide-and-conquer metaheuristics for floorplanning, timing and placement optimization. Formulations or optimization objectives for partitioning follow from its context and role. Finally, the available algorithm technology determines how effectively we can address a given partitioning formulation and optimize a given objective. This invited paper considers the future of partitioning for physical design in light of these factors, and proposes a list of technology needs. A living version of this paper can be found at vlsicad.cs.ucla.edu .

1 Introduction

Partitioning in VLSI physical design has been actively studied over the past two decades, with hundreds of works in the literature. A comprehensive review can be obtained from [3] [13] [19] [8]. The standard formulation seeks a multi-way partitioning of a vertex- and hyperedgeweighted directed hypergraph, with a minimum hyperedge-cut objective subject to partition size constraints. Recent years have seen several works that add I/O-count or path-cut constraints, replication and retiming degrees of freedom, hierarchy awareness, etc. to the standard formulation. However, the bulk of the literature still focuses on “min-cut” bipartitioning.

Partitioning is simply a facilitator of the divide-and-conquer approach. Its purpose is to decompose problems in a manner appropriate to the application, without losing solution quality. Increasingly, a large part of “solution quality” depends on preserving the previous activity that led up to the current state of the design. Hence, a critical future requirement for a partitioner is that it completely captures, and never loses, “design state” information.

[3] [13] [19] [8]

REFERENCES
[1] C. J. Alpert, personal communication, February 1998.
[2] C. J. Alpert, “The ISPD Circuit Benchmark Suite”, Proc.
ACM/IEEE Intl. Symp. on Physical Design, April 1998.
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[4] C. J. Alpert, J.-H. Huang and A. B. Kahng, “Multilevel Circuit
Partitioning”, Proc. ACM/IEEE Design Automation Conference,
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[5] K. Bazargan, S. Kim and M. Sarrafzadeh, “Nostradamus: A
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[6] K. D. Boese, Models for Iterative Global Optimization, Ph.D.
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[7] A. E. Caldwell, A. B. Kahng and I. L. Markov, manuscript, 1997.
[8] W. E. Donath, “Logic Partitioning”, in B. Preas and M. Lorenzetti,
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Cummings, 1988.
[9] A. E. Dunlop and B. W. Kernighan, “A Procedure for Placement
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[10] C. M. Fiduccia and R. M. Mattheyses, “A Linear Time Heuristic
for Improving Network Partitions”, Proc. ACM/IEEE Design
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849-866.
[12] D. J. Huang and A. B. Kahng, “Partitioning-Based Standard-Cell
Global Placement with an Exact Objective”, in Proc. ACM/IEEE
Intl. Symp. on Physical Design, Napa, April 1997, pp. 18-25.
[13] F. R. Johannes, “Tutorial: Partitioning of VLSI Circuits and Systems”,
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[14] A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, “Interconnect
Tuning Strategies for High-Performance ICs”, Proc. Design, Automation
and Test in Europe (DATE), Paris, February 1998.
[15] A. B. Kahng and R. Sharma, “Studies of Clustering Objectives
and Heuristics for Improved Standard-Cell Placement”,
manuscript, 1997.
[16] G. Karypis, R. Aggarwal, V. Kumar and S. Shekhar, “Multilevel
Hypergraph Partitioning: Applications in VLSI Domain”, Proc.
ACM/IEEE Design Automation Conference, 1997, pp. 526-529.
[17] M.-T. Kuo, L.-T. Liu and C.-K. Cheng, “Network Partitioning Into
Tree Hierarchies”, Proc. ACM/IEEE Design Automation Conference,
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[18] E. L. Lawler, K. N. Levitt and J. Turner, “Module Clustering to
Minimize Delay in Digital Networks”, IEEE Trans. on Computers
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[19] T. Lengauer, Combinatorial Algorithms for Integrated Circuit
Layout, Wiley-Teubner, 1990.
[20] J. Lillis, personal communication, February 1998.
[21] R. X. T. Nijssen and J. A. G. Jess, “Two-Dimensional Datapath
Regularity Extraction”, Proc. ACM/SIGDA Physical Design
Workshop, April 1996, pp. 111-117.
[22] M. Sarrafzadeh and M. Wang, “NRG: Global and Detailed Placement”,
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pp. 532-537.
[23] Semiconductor Industry Association, “The National Technology
Roadmap for Semiconductors: Technology Needs”, December
1997.
[24] R. H. Storer, S. D. Wu and R. Vaccari, “New Search Spaces for
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Management Science 38 (1992), pp. 1495-1509.
[25] P. R. Suaris and G. Kedem, “Quadrisection: A New Approach
to Standard Cell Layout,” Proc. IEEE/ACMInternational Conference
on Computer-Aided Design, 1987, pp. 474-477.
[26] W. Sun and C. Sechen, “Efficient and Effective Placements for
Very Large Circuits”, Proc. IEEE/ACM International Conference
on Computer-Aided Design, 1993, pp. 170-177.
[27] G. Vijayan, “Generalization of Min-Cut Partitioning to Tree
Structures and Its Applications”, IEEE Trans. on Computers 40(3)
(1991), pp. 307-314.
[28] C.-W. Yeh, C.-K. Cheng and T.-T. Y. Lin, “Optimization by Iterative
Improvement: An Experimental Evaluation on Two-Way
Partitioning”, IEEE Transactions on Computer-Aided Design 14
(1995), pp. 145-153.

Hypergraph

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “hMETIS-Hypergraph & Circuit
Partitioning,” Version 1.5.3, November 1998. (Available at: http://www-users.cs.umn.edu/?
karypis/metis/hmetis/)

Hypergraph / Multilevel hypergraph okokok

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel Hypergraph Partitioning: Applications in VLSI Domain DAC 97 - 06/97 Anaheim, CA, USA p4 ............

George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar
University of Minnesota, Department of Computer Science, Minneapolis, MN 55455
fkarypis, rajat, kumar, shekharg@cs.umn.edu

George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar
fkarypis, rajat, kumar, shekhargcs.umn.edu
University of Minnesota, Computer Science Department, Minneapolis, MN 55455
http://www.cs.umn.edu/?karypis

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Abstract

In this paper, we present a new hypergraph partitioning algorithm that is based on themultilevel paradigm. In themultilevel paradigm, a sequence of successively coarser hypergraphs is constructed. A bisection of the smallest hypergraph is computed and it is used to obtain a bisection of the original hypergraph by successively projecting and refining the bisection to the next level finer hypergraph. We evaluate the performance both in terms of the size of the hyperedge cut on the bisection as well as run time on a number of VLSI circuits.

1 Introduction

Hypergraph partitioning is an important problem and has extensive application tomany areas, including VLSI design [2], efficient storage of large databases on disks, and data mining [14]. The problem is to partition the vertices of a hypergraph in k roughly equal parts, such that the number of hyperedges connecting vertices in different parts is minimized. Formally, a hypergraph H = (V;Eh ) is defined as a set of vertices V and a set of hyperedges Eh, where each hyperedge is a subset of the vertex set V .

Hypergraphs can be used to naturally represent a VLSI circuit [14]. Hypergraph partitioning has many applications including design packaging, HDL-based synthesis, design optimization, rapid prototyping, simulation, and testing. A high quality hypergraph partitioning algorithm greatly affects the feasibility, quality, and cost of the resulting system.

The problem of computing an optimal bisection of a hypergraph is NP-complete. However, because of the importance of the probleminmany application areas, many heuristic algorithms have been developed. In a widely used class of iterative refinement partitioning algorithms, an initial bisection is computed (often obtained randomly) and then the partition is refined by repeatedly moving vertices between the two parts to reduce the hyperedge-cut. These algorithms often use the Schweikert- Kernighan [21] (an extension of Kernighan-Lin (KL) [17] for hypergraphs), or the faster Fiduccia-Mattheyses (FM) [8] refinement heuristic to iteratively improve the quality of the partition.

Another class of hypergraph partitioning algorithms [7, 10, 9, 22] consists of two different phases. In the first phase, they cluster the hypergraph to form a small hypergraph and use the FM algorithm to bisect the small hypergraph. In the second phase, they use the bisection of this contracted hypergraph to obtain a bisection of the original hypergraph. The overall performance of such a scheme depends upon the quality of the clusteringmethod. In many schemes, the projected partition is further improved using the FM refinement scheme [22].

Recently a new class of multilevel partitioning techniques was developed [3, 12, 11, 4]. These algorithms consist of three phases, namely, coarsening phase, initial partitioning phase, and uncoarsening and refinement phase. During the coarsening phase, a sequence of successively smaller (coarser) graphs is constructed; during the initial partitioning phase, a bisection of the coarsest graph is computed; and during the uncoarsening and refinement phase, the bisection is successively projected to the next level finer graph, and at each level an iterative refinement algorithm such as KL or FM is used to further improve the bisection. The various phases of multilevel bisection are illustrated in Figure 1. Karypis and Kumar extensively studied this paradigm in [16, 15] for partitioning of graphs. They presented new powerful graph coarsening schemes for which even a good bisection of the coarsest graph is a pretty good bisection of the original graph. This makes the overall multilevel paradigm even more robust. Furthermore, it allows the use of simplified variants of KL and FM refinement schemes during the uncoarsening phase, which significantly speeds up the refinement without compromising the overall quality. METIS [16], a multilevel graph partitioning algorithm based upon this work, routinely finds substantially better bisections and is often two orders of magnitude faster than the hitherto state-of-the-art spectral-based bisection techniques for graphs.

Figure 1: The various phases of the multilevel graph bisection.

The improved coarsening schemes ofMETIS work only for graphs, and are not directly applicable to hypergraphs. If the hypergraph is first converted into a graph (by replacing each hyperedge by a set of regular edges), then METIS [16] can be used to compute a partitioning of this graph. This technique was investigated by Alpert and Khang [1]. The conversion of a hypergraph into a graph by replacing each hyperedge by a clique does not result in an equivalent representation [14]. The fundamental problem associated with replacing a hyperedge by its clique, is that there exists no scheme to assign weight to the edges of the clique that can correctly capture the cost of cutting this hyperedge [13]. This hinders the partitioning refinement algorithm since vertices are moved between partitions depending on the reduction in the number of edges they cut in the converted graph, whereas the real objective is to minimize the number of hyperedges that are cut in the original hypergraph.

In this paper we present a multilevel hypergraph partitioning algorithm, hMETIS, that operates directly on the hypergraphs. A key contribution of our work is the development of new hypergraph coarsening schemes that allow the multilevel paradigm to provide high quality partitions quite consistently. The use of these powerful coarsening schemes also allow the refinement to be simplified considerably (even beyond the plain FMrefinement), making the multilevel scheme quite fast.

2 Multilevel Hypergraph Bisection

Coarsening Phase

The purpose of coarsening is to create a small hypergraph, such that a good bisection of the small hypergraph is not significantly worse than the bisection directly obtained for the original hypergraph. In addition to that, hypergraph coarsening also helps in successively reducing the size of the hyperedges. That is, after several levels of coarsening, large hyperedges are contracted to hyperedges connecting just a few vertices. This is particularly helpful, since refinement heuristics based on the Kernighan- Lin algorithm [17, 21, 8] are very effective in refining small hyperedges but are quite ineffective in refining hyperedges with a large number of vertices belonging to different partitions.

Figure 2: Various ways of matching the vertices in the hypergraph and the coarsening they induce.

The group of vertices that are merged together to form single vertices in the next level coarse hypergraph can be selected in different ways. We have developed three different algorithms for coarsening. In edge coarsening (illustrated in Figure 2(a)) a heavy-edge maximal matching of the vertices of the hypergraph is computed to select the pairs of vertices. These vertices are thenmerged together. In Hyperedge Coarsening(illustrated in Figure 2(b)) an independent set of hyperedges is selected and the vertices that belong to these hyperedges are contracted together. This scheme gives preference to the hyperedges that have large weight and those that are of small size. In Modified Hyperedge Coarsening(illustrated in Figure 2(c)) after the hyperedges to be contracted have been selected using the hyperedge coarsening scheme, all the uncontracted hyperedges are considered again. And for each uncontracted hyperedge, the vertices that do not belong to any other contracted hyperedge arematched to be contracted together.

Uncoarsening and Refinement Phase

We calculate the initial partitioning using “balanced” random bisection. This partitioning is then carried along in the uncoarsening phase. During the uncoarsening phase, a partitioning of the coarser hypergraph is used to obtain a partitioning for the finer graph. This is done by successively projecting the partitioning to the next level finer hypergraph and using a partitioning refinement algorithm to reduce the cut and thus improve the quality of the partitioning. Since the next level finer hypergraph has more degrees of freedom, such refinement algorithms tend to improve the quality.'

We have implemented two different partitioning refinement algorithms. The first is the FM algorithm [8] which repeatedly moves vertices between partitions in order to improve the cut. We have made two simplifications in FM, which are (i) we limit the maximum number of passes performed by the FMalgorithm to only two and (ii) we stop each pass of the FM algorithm as soon as we have performed k vertex moves that did not improve the cut (this modification is called early-exit FM (FM-EE)). The second algorithm, called Hyperedge Refinement(HER), moves groups of vertices between partitions so that an entire hyperedge is removed from the cut. Unlike FM, this algorithm has the capability to refine hyperedges that have many nodes on both sides of the partitioning boundary. Note that unlike FM, HER is not a hill-climbing algorithm, as it does not perform moves that can lead to a larger cut (i.e., negative cut reduction).

Hypergraph / Multilevel hypergraph okokok

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel Hypergraph Partitioning: Applications in VLSI Domain .March 27, 1998 p25

G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel Hypergraph Partitioning: Applications in VLSI Domain . IEEE Trans. VLSI Syst., 7(1):69–79, 1999.

George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar
University of Minnesota, Department of Computer Science, Minneapolis, MN 55455
fkarypis, rajat, kumar, shekharg@cs.umn.edu

George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar
fkarypis, rajat, kumar, shekhargcs.umn.edu
University of Minnesota, Computer Science Department, Minneapolis, MN 55455
http://www.cs.umn.edu/?karypis

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

1 Introduction

Hypergraph partitioning is an important problem and has extensive application to many areas, including VLSI design [16], efficient storage of large databases on disks [26], and data mining [25]. The problem is to partition the vertices of a hypergraph in k roughly equal parts, such that the number of hyperedges connecting vertices in different parts is minimized. A hypergraph is a generalization of a graph, where the set of edges is replaced by a set of hyperedges. A hyperedge extends the notion of an edge by allowingmore than two vertices to be connected by a hyperedge. Formally, a hypergraph H D .V; Eh / is defined as a set of vertices V and a set of hyperedges Eh, where each hyperedge is a subset of the vertex set V [29], and the size a hyperedge is the cardinality of this subset.

Figure1: (a) Circuit showing cells and nets, (b) hypergraph representation of the circuit, (c) weighted clique modeling of hypergraph.

During the course of VLSI circuit design and synthesis, it is quite important to be able to divide the system specification into clusters so that the inter-cluster connections are minimized. This step has many applications including design packaging, HDL-based synthesis, design optimization, rapid prototyping, simulation, and testing. In particular, many rapid prototyping systems use partitioning to map a complex circuit onto hundreds of interconnected FPGAs. Such partitioning instances are challenging because the timing, area, and I/O resource utilization must satisfy hard device-specific constraints. For example, if the number of signal nets leaving any one of the clusters is greater than the number of signal pins available in the FPGA, then this cluster cannot be implemented using a single FPGA. In this case, the circuit needs to be further partitioned, and thus implemented using multiple FPGAs. Hypergraphs can be used to naturally represent a VLSI circuit. The vertices of the hypergraph can be used to represent the cells of the circuit, and the hyperedges can be used to represent the nets connecting these cells (as illustrated in Figure1). A high quality hypergraph partitioning algorithm greatly affects the feasibility, quality, and cost of the resulting system.

1.1 Related Work

The problem of computing an optimal bisection of a hypergraph is at least NP-hard [30]. However, because of the importance of the problem in many application areas, many heuristic algorithms have been developed. The survey by Alpert and Khang [16] provides a detailed description and comparison of various such schemes. In a widely used class of iterative refinement partitioning algorithms, an initial bisection is computed (often obtained randomly) and then the partition is refined by repeatedly moving vertices between the two parts to reduce the hyperedge-cut. These algorithms often use the Schweikert-Kernighan heuristic [2] (an extension of the Kernighan-Lin (KL) heuristic [1] for hypergraphs), or the faster Fiduccia-Mattheyses (FM) [3] refinement heuristic to iteratively improve the quality of the partition. In all of these methods (sometimes also called KLFM schemes), a vertex is moved (or a vertex-pair is swapped) if it results in the greatest reduction in the edge-cuts, which is also called the gain for moving the vertex. The partition produced by these methods is often poor especially for larger hypergraphs, for a number of reasons. First, these methods choose vertices for movement based only upon local information. For example, it may be better to move a vertex with smaller gain, as it may allow many good moves later. Second, if many vertices have the same gain, then the method offers no insight on which of these vertices to move [4]. Third, a hyperedge that has more than one vertices on both sides of the partition line does not influence the computation of the gain of vertices contained in it, making the gain computation quite inexact [22]. Hence, these algorithms have been extended in a number of ways [4, 20, 22, 23].

The problem of computing an optimal bisection of a hypergraph is NP-complete. However, because of the importance of the problem in many application areas, many heuristic algorithms have been developed. The survey by Alpert and Khang [2] provides a detailed description and comparison of various such schemes. In a widely used class of iterative refinement partitioning algorithms, an initial bisection is computed (often obtained randomly) and then the partition is refined by repeatedly moving vertices between the two parts to reduce the hyperedge-cut. These algorithms often use the Schweikert- Kernighan [21] (an extension of Kernighan-Lin (KL) [17] for hypergraphs), or the faster Fiduccia-Mattheyses (FM) [8] refinement heuristic to iteratively improve the quality of the partition. The partition produced by these methods is often poor, especially for larger hypergraphs, for a number of reasons. First, these methods choose vertices for movement based only upon local information. Second, if many vertices have the same gain, then the method offers no insight on which of these vertices to move [18]. Third, a hyperedge that has more than one vertices on both sides of the partition line does not influence the computation of the gain of vertices contained in it, making the gain computation quite inexact [5]. Hence, these algorithms have been extended in a number of ways [18, 20, 5, 6] that tend to enhance the performance of the basic KL/FMrefinement algorithms, at the expense of increased run time.

Krishnamurthy [4] tried to introduce intelligence in the tie breaking process from among the many possible moves with the same high gain. He used a Look Ahead(LAr ) algorithm which looks ahead up to r -level of gains before making moves. PROP [22], introduced by Dutt and Deng, used a probabilistic gain computation model for deciding the vertices that needs to move across the partition line. It tries to capture the implications of moving a node across the partition boundary for a hyperedge that contains many vertices on both the sides of the partition. These schemes tend to enhance the performance of the basic KLFM familly of refinement algorithms, at the expense of increased run time. Dutt and Deng [23] proposed two new methods, namely CLIP and CDIP, for computing gains of hyperedges that contain more than one node on either side of the partition boundary. CDIP in conjunction with LA3 and CLIP in conjunction with PROP are two schemes that have shown the best results in their experiments.

..............................

Another class of hypergraph partitioning algorithms [5, 7, 13, 24] performs partitioning in two phases. In the first phase, the hypergraph is coarsened to form a small hypergraph, and then the FM algorithm is used to bisect the small hypergraph. In the second phase, they use the bisection of this contracted hypergraph to obtain a bisection of the original hypergraph. Since FM refinement is done only on the small coarse hypergraph, this step is usually fast. But the overall performance of such a scheme depends upon the quality of the coarsening method. In many schemes, the projected partition is further improved using the FM refinement scheme [13].

Recently a new class of partitioning algorithms was developed [10, 12, 11, 17] that are based upon the multilevel paradigm. In these algorithms, a sequence of successively smaller (coarser) graphs is constructed. A bisection of the smallest graph is computed. This bisection is now successively projected to the next level finer graph, and at each level an iterative refinement algorithm such as KLFM is used to further improve the bisection. The various phases of multilevel bisection are illustrated in Figure 2. The iterative refinement schemes such as KLFM become quite powerful in this multilevel context for the following reason. First, movement of a single node across partition boundary in a coarse graph can lead to movement of a large number of related nodes in the original graph. Second, the refined partitioning projected to the next level serves as an excellent initial partitioning for the KL or FM refinement algorithms. This paradigm was independently studied by Bui and Jones [10] in the context of computing fill reducing matrix reordering, by Hendrickson and Leland [12] in the context of finite element grid partitioning, and by Hauck and Borriello [17] (called Optimized KLFM) and by Cong and Smith [11] for hypergraph partitioning. Karypis and Kumar extensively studied this paradigm in [27, 33] for partitioning of graphs. They presented new graph coarsening schemes for which even a good bisection of the coarsest graph is a pretty good bisection of the original graph. This makes the overall multilevel paradigm even more robust. Furthermore, it allows the use of simplified variants of KLFM refinement schemes during the uncoarsening phase, which significantly speeds up the refinement without compromising the overall quality. METIS [27], a multilevel graph partitioning algorithm based upon this work, routinely finds substantially better bisections and is often two orders of magnitude faster than the hitherto state-of-the-art spectral-based bisection techniques [6, 8] for graphs.

Figure 2: The various phases of the multilevel graph bisection. During the coarsening phase, the size of the graph is successively decreased; during the initial partitioning phase, a bisection of the smaller graph is computed; and during the uncoarsening and refinement phase, the bisection is successively refined as it is projected to the larger graphs. During the uncoarsening and refinement phase the dashed lines indicate projected partitionings, and dark solid indicate partitionings that were produced after refinement. G0 is the given graph, which is the finest graph. GiC1 is next level coarser graph of Gi , vice versa, Gi is next level finer graph of GiC1. G4 is the coarsest graph.
Figure 2: Various ways of matching the vertices in the hypergraph and the coarsening they induce.

The improved coarsening schemes of METIS work only for graphs, and are not directly applicable to hypergraphs. If the hypergraph is first converted into a graph (by replacing each hyperedge by a set of regular edges), thenMETIS [27] can be used to compute a partitioning of this graph. This technique was investigated by Alpert and Khang [21] in their algorithm called GMetis. They converted hypergraphs to graphs by simply replacing each hyperedge by a clique, and then dropped many edges from each clique randomly. They used METIS to compute a partitioning of each such random graph and selected the best of these partitionings. Their results show that reasonably good partitionings can be obtained in a reasonable amount of time for a variety of benchmark problems. In particular, the performance of their resulting scheme is comparable to other state-of-the art schemes such as PARABOLI [15], PROP [22], and the multilevel hypergraph partitioner from Hauck and Borriello [17].

The improved coarsening schemes of METIS work only for graphs, and are not directly applicable to hypergraphs. If the hypergraph is first converted into a graph (by replacing each hyperedge by a set of regular edges), then METIS [16] can be used to compute a partitioning of this graph. This technique was investigated by Alpert and Khang [1]. The conversion of a hypergraph into a graph by replacing each hyperedge by a clique does not result in an equivalent representation [14]. The fundamental problem associated with replacing a hyperedge by its clique, is that there exists no scheme to assign weight to the edges of the clique that can correctly capture the cost of cutting this hyperedge [13]. This hinders the partitioning refinement algorithm since vertices are moved between partitions depending on the reduction in the number of edges they cut in the converted graph, whereas the real objective is to minimize the number of hyperedges that are cut in the original hypergraph.

The conversion of a hypergraph into a graph by replacing each hyperedge by a clique does not result in an equivalent representation, since high quality partitionings of the resulting graph do not necessarily lead to high quality partitionings of the hypergraph. This is illustrated in Figure 3. Figure 3(a) shows the original hyperedge and Figure 3(b) shows the graph obtained after replacing the hyperedge by its clique. The standard hyperedge to edge conversion [31] assigns a uniform weight of 1=.jej ? 1/ to each edge in the clique, where jej is the size of the hyperegde i.e., the number of vertices in the hyperedge. Thus, in our example, each edge is assigned a weight of 1=3. Figures 3(c) and 3(d) show two example bisections in which the edge-cuts are 1 and 4/3, respectively. So different partitionings of the converted graph lead to different cuts in the graph, whereas for the original hypergraph both of these partitionings result in a cut-size of one. The fundamental problem associated with replacing a hyperedge by its clique, is that there exists no scheme to assign weight to the edges of the clique that can correctly capture the cost of cutting this hyperedge [14]. This hinders the partitioning refinement algorithm since vertices are moved between partitions depending on the reduction in the number of edges they cut in the converted graph, whereas the real objective is to minimize the number of hyperedges that are cut in the original hypergraph. Furthermore, the hyperedge to clique conversion destroys the natural sparsity of the hypergraph, significantly increasing the run-time of the partitioning algorithm. Alpert and Khang [21] solved this problem by dropping many edges of the clique randomly. But this makes the graph representation even less accurate. A better approach is to develop coarsening and refinement schemes that operate directly on the hypergraph. Note that the multilevel scheme by Hauck and Borriello [17] operates directly on hypergraphs, and thus is able to perform accurate refinement during the uncoarsening phase. However, all coarsening schemes studied in [17] are edge-oriented; i.e., they only merge pairs of nodes to construct coarser graphs. Hence, despite a powerful refinement scheme (FM with the use of look-ahead LA3) during the uncoarsening phase, their performance is only as good as that of GMetis [21].

Figure 3: (a) original hypergraph, (b) graph obtained after clique conversion in which weight of each edge = 1/3, (c) an example partitioning with weight of hyperedges cut down =1, and (d) an example partitioning with weight of hyperedges cut down= 4/3

1.2 Our Contributions

In this paper we present a multilevel hypergraph partitioning algorithm, hMETIS, that operates directly on the hypergraphs. A key contribution of our work is the development of new hypergraph coarsening schemes that allow the multilevel paradigm to provide high quality partitions quite consistently. The use of these powerful coarsening schemes also allows the refinement to be simplified considerably (even beyond the plain FM refinement), making the multilevel scheme quite fast. We investigate various algorithms for the coarsening and uncoarsening phases which operates on the hypergraphs without converting them into graphs. We have also developed new multi-phase refinement schemes (v- and V-cycles) based on the multilevel paradigm. These schemes take an initial partition as input and try to improve them using the multilevel scheme. These multi-phase schemes further reduce the run-times as well as improve the solution quality. Figure 4 shows the general framework of our algorithm hMETIS, using both v- and V-cycles.

In this paper we present a multilevel hypergraph partitioning algorithm, hMETIS, that operates directly on the hypergraphs. A key contribution of our work is the development of new hypergraph coarsening schemes that allow the multilevel paradigm to provide high quality partitions quite consistently. The use of these powerful coarsening schemes also allow the refinement to be simplified considerably (even beyond the plain FM refinement), making the multilevel scheme quite fast.

We evaluate the performance both in terms of the size of the hyperedge cut on the bisection as well as run time on a number of VLSI circuits. Our experiments show that our multilevel hypergraph partitioning algorithm produces high quality partitioning in relatively small amount of time. The quality of the partitionings produced by our scheme are on the average 4% to 23% better that those produced by other state-of-the-art schemes [1, 5, 6, 19, 11]. The difference in quality over other schemes become even greater for larger hypergraphs. Furthermore, our partitioning algorithm is significantly faster, often requiring 4 to 10 times less time than that required by the other schemes. For many benchmark circuits in the well known ACM/SIGDA benchmark set 1, our scheme is able to find better partitionings than those reported in the literature for any other hypergraph partitioning algorithm.

We evaluate the performance both in terms of the size of the hyperedge cut on the bisection as well as run time on a number of VLSI circuits. Our experiments show that our multilevel hypergraph partitioning algorithm produces high quality partitioning in relatively small amount of time. The quality of the partitionings produced by our scheme are on the average 6% to 23% better than those produced by other state-of-the-art schemes [15, 19, 21, 22, 23]. The difference in quality over other schemes becomes even greater for larger hypergraphs. Furthermore, our partitioning algorithm is significantly faster, often requiring 4 to 10 times less time than that required by the other schemes. For many circuits in the well known ACM/SIGDA benchmark set [9], our scheme is able to find better partitionings than those reported in the literature for any other hypergraph partitioning algorithm.

Figure 4: Multilevel Hypergraph Partitioning with one embedded v-cycles followed by a V-cycle.

The rest of this paper is organized as follows. Section 2 describes the different algorithms used in the three phases of our multilevel hypergraph partitioning algorithm. A comprehensive experimental evaluation of these algorithms is provided in Section 3. Section 4 describes and experimentally evaluates a new partitioning refinement algorithmbased on the multilevel paradigm. Section 5 compares the results produced by our algorithm to those produced by earlier hypergraph partitioning algorithms.

2 Multilevel Hypergraph Bisection

2 Multilevel Hypergraph Bisection

We now present the framework of hMETIS, in which the coarsening and the refinement schemes treat hyperedges without any distortion. We have developed new algorithms for both of these phases, which in conjunction have the capability of delivering very good quality solutions. In the rest of this section, we briefly describe the algorithms used in the coarsening and the uncoarsening phases. Extensive descriptions can be found in [14].

We now present the framework of hMETIS, in which the coarsening and the refinement scheme work directly with hyperedges without using the clique representation to transform them into edges. We have developed new algorithms for both the phases, which in conjunction have the capability of delivering very good quality solutions.

2.1 Coarsening Phase

Coarsening Phase

The purpose of coarsening is to create a small hypergraph, such that a good bisection of the small hypergraph is not significantly worse than the bisection directly obtained for the original hypergraph. In addition to that, hypergraph coarsening also helps in successively reducing the size of the hyperedges. That is, after several levels of coarsening, large hyperedges are contracted to hyperedges connecting just a few vertices. This is particularly helpful, since refinement heuristics based on the Kernighan- Lin algorithm [17, 21, 8] are very effective in refining small hyperedges but are quite ineffective in refining hyperedges with a large number of vertices belonging to different partitions.

During the coarsening phase, a sequence of successively smaller hypergraphs are constructed. As in the case of multilevel graph bisection, the purpose of coarsening is to create a small hypergraph, such that a good bisection of the small hypergraph is not significantly worse than the bisection directly obtained for the original hypergraph. In addition to that, hypergraph coarsening also helps in successively reducing the sizes of the hyperedges. That is, after several levels of coarsening, large hyperedges are contracted to hyperedges connecting just a few vertices. This is particularly helpful, since refinement heuristics based on the KLFM familly of algorithms [1, 2, 3] are very effective in refining small hyperedges but are quite ineffective in refining hyperedges with a large number of vertices belonging to different partitions.

Groups of vertices that are merged together to form single vertices in the next level coarse hypergraph can be selected in different ways. One possibility is to select pairs of vertices with common hyperedges and merge them together, as illustrated in Figure 5(a). A second possibility is to merge together all the vertices that belong to a hyperedge as illustrated in Figure 5(b). Finally, a third possibility is to merge together a subset of the vertices belonging to a hyperedge as illustrated in Figure 5(c). These three different schemes for grouping vertices together for contraction are described below.

The group of vertices that are merged together to form single vertices in the next level coarse hypergraph can be selected in different ways. We have developed three different algorithms for coarsening. In edge coarsening (illustrated in Figure 2(a)) a heavy-edge maximal matching of the vertices of the hypergraph is computed to select the pairs of vertices. These vertices are thenmerged together. In Hyperedge Coarsening (illustrated in Figure 2(b)) an independent set of hyperedges is selected and the vertices that belong to these hyperedges are contracted together. This scheme gives preference to the hyperedges that have large weight and those that are of small size. In Modified Hyperedge Coarsening (illustrated in Figure 2(c)) after the hyperedges to be contracted have been selected using the hyperedge coarsening scheme, all the uncontracted hyperedges are considered again. And for each uncontracted hyperedge, the vertices that do not belong to any other contracted hyperedge arematched to be contracted together.

Figure 5: Various ways of matching the vertices in the hypergraph and the coarsening they induce. (a) In the edge-coarsening connected pairs of vertices are matched together. (b) In the hyperedge-coarsening all the vertices belonging to a hyperedge are matched together. (c) In the modified hyperedge coarsening, we match together both all the vertices in a hyperedge as well as groups of vertices belonging to a hyperedge.

Edge Coarsening The heavy-edge matching scheme used in the multilevel graph bisection algorithm can also be used to obtain successive coarser hypergraphs by merging the pairs of vertices connected by many hyperedges. In this edge coarsening (EC) scheme a heavy-edge maximal1 matching of the vertices of the hypergraph is computed as follows. The vertices are visited in a random order. For each vertex v, all unmatched vertices that belong to hyperedges incident to v are considered, and the one that is connected via the edge with the largest weight is matched with v. The weight of an edge connecting two vertices v and u is computed as the sum of the edge-weights of all the hyperedges that contain v and u. Each hyperedge e of size jej is assigned an edge-weight of 1=.jej?1/, and as hyperedges collapse on each other during coarsening, their edge-weights are added up accordingly.

This edge coarsening scheme is similar in nature to the schemes that treat the hypergraph as a graph by replacing each hyperedge with its clique representation [31]. However, this hypergraph to graph conversion is done implicitly during matching without forming the actual graph.

Hyperedge Coarsening Even though the edge coarsening scheme is able to produce successively coarse hypergraphs, it decreases the hyperedge weight of the coarse graph only for those pairs of matched vertices that are connected via a hyperedge of size two. As a result, the total hyperedge weight of successive coarse graphs does not decrease very fast. In order to ensure that for every group of vertices that are contracted together, there is a decrease in the hyperedge weight in the coarse graph, each such group of vertices must be connected by a hyperedge.

This is the motivation behind the hyperedge coarsening (HEC) scheme. In this scheme, an independent set of hyperedges is selected and the vertices that belong to individual hyperedges are contracted together. This is implemented as follows. The hyperedges are initially sorted in a non-increasing hyperedge-weight order and the hyperedges of the same weight are sorted in a non-decreasing hyperedge size order. Then, the hyperedges are visited in that order, and for each hyperedge that connects vertices that have not yet been matched, they arematched together. Thus, this scheme gives preference to the hyperedges that have large weight and those that are of small size. After all hyperedges have been visited, the groups of vertices that have been matched are contracted together to form the next level coarse graph. The vertices that are not part of any contracted hyperedges, they are simply copied to the next level coarse graph.

Modified Hyperedge Coarsening The hyperedge coarsening algorithmis able to significantly reduce the amount of hyperedge weight that is left exposed in successive coarse graphs. However, during each coarsening phase, a large majority of the hyperedges do not get contracted because vertices that belong to them have been contracted via other hyperedges. This leads to two problems. First, the size of many hyperedges does not decrease sufficiently, making FM-based refinement difficult. Second, the weight of the vertices (i.e., the number of vertices that have been collapsed together) in successive coarse graphs become significantly different, which distorts the shape of the contracted hypergraph.

To correct this problem we implemented a modified hyperedge coarsening (MHEC) scheme as follows. After the hyperedges to be contracted have been selected using the hyperedge coarsening scheme, the list of hyperedges are traversed again. And for each hyperedge that has not yet been contracted, the vertices that do not belong to any other contracted hyperedge are matched to be contracted together.

2.2 Initial Partitioning Phase

During the initial partitioning phase, a bisection of the coarsest hypergraph is computed, such that it has a small cut, and satisfies a user specified balance constraint. The balance constraint puts an upper bound on the difference between the relative size of the two partitions. Since this hypergraph has a very small number of vertices (usually less than 200 vertices) the time to find a partitioning using any of the heuristic algorithms tends to be small. Note that it is not useful to find an optimal partition of this coarsest graph, as the initial partition will be substantially modified during the refinement phase. We used the following two algorithms for computing the initial partitioning.

The first algorithm simply creates a random bisection such that each part has roughly equal vertex weight. The second algorithm starts from a randomly selected vertex and grows a region around it in a breadth-first fashion [33] until half of the vertices are in this region. Then the vertices belonging to the grown region are assigned to the first part and the rest of the vertices are assigned to the second part. After a partitioning is constructed using either of these algorithms, the partitioning is refined using the FM refinement algorithm.

Since both algorithms are randomized, different runs give solutions of different quality. For this reason, we perform a small number of initial partitionings. At this point we can select the best initial partitioning and project it to the original hypergraph as described in Section 2.3. However, the partitioning of the coarsest hypergraph that has the smallest cut may not necessarily be the one that will lead to the smaller cut in the original hypergraph. It is possible that another partitioning of the coarsest hypergraph (with higher cut) leads to a better partitioning of the original hypergraph after the refinement is performed during the uncoarsening phase. For this reason, instead of selecting a single initial partitioning (i.e., the one with the smallest cut), we propagate all initial partitionings.

Note that propagation of i initial partitionings increases the time during the refinement phase by a factor of i . Thus, by increasing the value of i , we can potentially improve the quality of the final partitioning at the expense of higher runtime. One way to dampen the increase in runtime due to large values of i , is to drop unpromising partitionings as the hypergraph is uncoarsened. For example, one possibility is to propagate only those partitionings whose cuts are with x% of the best partitionings at the current level. If the value of x is sufficiently large, then all partitionings will be maintained and propagated in the entire refinement phase. On the other hand, if the value of x is sufficiently small, then on average only one partitioning will be maintained, as all other partitionings will be eliminated at the coarsest level. For moderate values of x, many partitionings may be available at the coarests graph, but the number of such available partitionings will decrease as the graph is uncoarsened. This is useful for two reasons. First, it is more important to have many alternate partitionings at the coarser levels, as the size of the cut of a partitioning at a coarse level is less accurate reflection of the size of the cut of the original finest level hypergraph. Second, the refinement is more expensive at the fine levels, as these levels contain far more nodes than the coarse levels. Hence by choosing an appropriate value of x, we can benefit from the availability of many alternate partitionings at the coarser levels, and avoid paying the high cost of refinement at the finer levels by keeping fewer candidates on average.

In our experiments reported in this paper, we find 10 initial partitionings at the coarsest graph, and we drop all partitionings whose cut is 10% worse than the best cut at that level. This allows us to both filter out the really bad partitionings (and thus reduce the amount of time spent in refinement), and at the same time keep more than just one promising partitioning (so that to improve the overall partitioning quality). In our experiments we have seen that by keeping 10 partitionings, we can reduce the cut on the average by 3% to 4%, whereas the partitioning time increases only by a factor of two. Computing and propagatingmore partitionings does not further reduce the cut significantly. In our experiments, keeping 20 partitionings further reduces the cut by a factor less than 0.5%, on the average. Increasing the vaue of parameter x (from 10% to a higher value such as 20%) did not significantly improve the quality of the partitionings, although it did increase the run time.

2.3 Uncoarsening and Refinement

Phase During the uncoarsening phase, a partitioning of the coarser hypergraph is successively projected to the next level finer hypergraph, and a partitioning refinement algorithm is used to reduce the cut-set (and thus improve the quality of the partitioning) without violating the user specified balance constraints. Since the next level finer hypergraph has more degrees of freedom, such refinement algorithms tend to improve the quality.

We have implemented two different partitioning refinement algorithms. The first is the FM algorithm [3] which repeatedly moves vertices between partitions in order to improve the cut. The second algorithm, called HER, moves groups of vertices between partitions so that an entire hyperedge is removed from the cut. These algorithms are further described in the remaining of this section.

Fiduccia-Mattheyses (FM) The partitioning refinement algorithm by Fiduccia and Mattheyses [3] is iterative in nature. It starts with an initial partitioning of the hypergraph. In each iteration, it tries to find subsets of vertices in each partition, such that by moving them to other partitions, improves the quality of the partitioning (i.e., the number of hyperedges being cut decreases) and the balance constraint is not violated. If such subsets exist, then the movement is performed and this becomes the partitioning for the next iteration. The algorithm continues by repeating the entire process. If it cannot find such a subset, then the algorithm terminates, since the partitioning is at a local minima and no further improvement can be made by this algorithm.

In particular, for each vertex v, the FM algorithm computes the gain which is the reduction in the hyperedge-cut achieved by moving v to the other partition. Initially all vertices are unlocked, that is, they are free to move to the other partition. The algorithm iteratively selects an unlocked vertex v with the largest gain (subject to balance constraints) and moves it to the other partition. When a vertex v is moved, it is locked and the gain of the vertices adjacent to v are updated. After each vertex movement, the algorithm also records the size of the cut achieved at this point. Note that the algorithmdoes not allow locked vertices to be moved since this may result in thrashing (i.e., repeated movement of the same vertex). A single pass of the FM algorithm ends when there are no more unlocked vertices (i.e., all the vertices have been moved). Then, the recorded cut-sizes are checked, and the point where the minimum cut was achieved is selected, and all vertices that were moved after that point are moved back to their original partition. Now, this becomes the initial partitioning for the next pass of the algorithm. With the use of appropriate data-structures, the complexity of each pass of the FM algorithm is O.jEh j/ [3].

For refinement in the context of multilevel schemes, the initial partitioning obtained from the next level coarser graph, is actually a very good partition. For this reason we can make a number of optimizations to the original FM algorithm. The first optimization limits the maximum number of passes performed by the FM algorithm to only two. This is because, the greatest reduction in the cut is obtained during the first or second pass and any subsequent passes only marginally improve the quality. Our experience has shown that this optimization significantly improves the runtime of FM without affecting the overall quality of the produced partitionings. The second optimization aborts each pass of the FM algorithm before actually moving all the vertices. The motivation behind this is that only a small fraction of the vertices being moved actually lead to a reduction in the cut, and after some point, the cut tends to increase as we move more vertices. When FM is applied to a random initial partitioning, it is quite likely that after a long sequence of bad moves, the algorithm will climb-out of a local minima and reach to a better cut. However, in the context of a multilevel scheme, long sequence of cut-increasing moves rarely leads to a better local minima. For this reason, we stop each pass of the FM algorithm as soon as we have performed k vertex moves that did not improve the cut. We choose k to be equal to 1% of the number of vertices in the graph we are refining. This modification to FM, called early-exit FM (FM-EE), does not significantly affect the quality of the final partitioning, but it dramatically improves the run time (see Section 3).

Uncoarsening and Refinement Phase

We calculate the initial partitioning using “balanced” random bisection. This partitioning is then carried along in the uncoarsening phase. During the uncoarsening phase, a partitioning of the coarser hypergraph is used to obtain a partitioning for the finer graph. This is done by successively projecting the partitioning to the next level finer hypergraph and using a partitioning refinement algorithm to reduce the cut and thus improve the quality of the partitioning. Since the next level finer hypergraph has more degrees of freedom, such refinement algorithms tend to improve the quality.

HyperedgeRefinement (HER) One of the drawbacks of FM(and other similar vertex-based refinement schemes) is that it is often unable to refine hyperedges that have many nodes on both sides of the partitioning boundary. However a refinement scheme that moves all the vertices that belong to a hyperedge can potentially solve this problem. For example, Figure 6 shows an initial partitioning of the given hypergraph. The gain for each node is either 0 or -1. There is no sequence of moves which FM can select to reduce the size of the cutset (FM always select a vertex with highest gain first to move). Whereas, if we move all the vertices of hyperedge b from partition P0 to P1, we can save one hyperedge without affecting the required balance factor of 40/60. We have developed such a refinement algorithm that focuses on the hyperedges that straddle partitioning boundary and tries to move them so that they are interior to either one of the partitions.

Figure 6: Initial partitioning of the given hypergraph with the gains of each vertex. Required balance factor is 40/60.

Our hyperedge refinement (HER) works as follows. It randomly visits all the hyperedges and for each one that straddles the bisection, it determines if it can move a subset of the vertices incident on it, so that this hyperedge will become completely interior to a partition. In particular, consider a hyperedge e, that straddles the partitioning boundary, and let V 0 e and V 1 e be the vertices of e that belong to partition 0 and partition 1, respectively. Our algorithm computes the gain g0!1, which is the reduction in the cut achieved by moving the vertices in V0 e to partition 1, and the gain g1!0, which is the reduction in the cut achieved by moving the vertices in V 1 e to partition 0. Now, depending on these gains and subject to balance constraints, it may move one of the two sets V 0 e or V 1 e . In particular, if g0!1 is positive and g0!1 > g1!0, it moves V 0 e , and if g1!0 is positive and g1!0 > g0!1, it moves V 1 e .

Note that unlike FM, HER is not a hill-climbing algorithm, as it does not perform moves that can lead to a larger cut (i.e., negative cut reduction). Hence, this algorithm lacks the capability of being able to climb-out of local minima by allowing moves that increase the cut. It is possible to develop an FM-style refinement algorithm that moves entire hyperedges. This algorithm will maintain the gain of each hyperedge, and in each iteration, will move the hyperedge that leads to the highest gain. However, the computation of updating gain for each hyperedge is much more expensive than the computation of updating gain for each vertex in the original FM algorithm. The reason is that every time we move a subset of vertices we need to update the gains of not only the hyperedges that are incident on the hyperedge moved, but also of all the hyperedges that are incident on the incident hyperedges. On the other hand, our HER scheme does not need to perform such computations to update the gains, since it does not prioritize the moves according to the cut-reduction they perform. This considerably reduces the runtime of the HER algorithm.

In general, the partitioning obtained by iterative HER refinement can be further improved by FM refinement. The reason is that HER forces movement of an entire group of vertices that belongs to a hyperedge,whereas FMrefinement allows movements of individual vertices across partitioning boundary. On our experiments (see Section 3) we found that the final partitioning obtained by HER refinement can be substantially improved by a round of FM refinement.

Table 1: The characteristics of the various hypergraphs used to evaluate the multilevel hypergraph partitioning algorithms.

3 Experimental Results

We experimentally evaluated the quality of the bisections produced by our multilevel hypergraph partitioning algorithm on a large number of hypergraphs that are part of the widely used ACM/SIGDA circuit partitioning benchmark suite. The characteristics of these hypergraphs are shown in Table 1. We performed all our experiments on an SGI Challenge that has MIPS R10000 processors running at 200Mhz, and all reported run-times are in seconds. All the reported partitioning results were obtained by forcing a 45–55 balance condition.

As discussed in Sections 2.1, 2.2, and 2.3, there are many alternatives for each of the three different phases of a multilevel algorithm. It is not possible to provide an exhaustive comparison of all these possible combinations without making this paper unduly large. Instead, we provide comparisons of different alternatives for each phase after making a reasonable choice for the other two phases.

To compare the performance of the bisections produced by our multilevel hypergraph bisection and refinement algorithms, both in terms of bisection quality as well as runtime, we created Table 1. Table 1 shows the size of the hyperedge cut produced by our algorithms (hMETIS) and those reported by various previously developed hypergraph bisection algorithms. In particular, Table 1 contains results for the following algorithms: PROP [5], Opt. KLFM (scheme by Hauck and Borriello [11]) CLIP-PROPf [6], PARABOLI [19], and GMetis [1]. Note that for certain circuits, there are missing results for some of the algorithms. This is because no results were reported for these circuits. The column labeled “Best” shows the minimum cut obtained for each circuit by any of the earlier algorithms. Essentially, this column represents the quality that would have been obtained, if all the algorithms have been run and the best partition was selected.

The last two columns of Table 1 shows the partitionings produced by our multilevel hypergraph bisection and refinement algorithms. In particular, the column labeled “hMETIS-EE20” corresponds to the best partitioning produced from 20 runs of our multilevel algorithmthat uses early-exit FM during refinement (FM-EE).Of these twenty runs, ten runs are using hyperedge coarsening (HEC) and ten runs are using modified hyperedge coarsening (MHEC). The column labeled “hMETIS-FM20” corresponds to the best partitioning produced from20 runs when FMis used during refinement and coarsening is performed similarly to “hMETIS-EE20”. In both of these schemes, we used random initial partitionings during the initial partitioning phase.

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The last subtable of Table 1 shows the total amount of time required by the various partitioning algorithms. These run-times are in seconds on the respective architectures. Because of the difference in CPU speed at the various machines, it is hard tomake direct comparisons. However, we tested our code on Sparc5 and we found that it requires about four times more time than when it is running on R10000. Taking into consideration a scaling factor of four, we see that both hMETIS-EE20 and hMETIS-FM20 require less time than either PROP,Opt. KLFM, CLIP-PROPf , or PARABOLI. In particular, hMETIS-EE20 is about four times faster than PROP, nine times faster than CLIP-PROPf , ten times faster than PARABOLI, and fifteen times faster than Opt. KLFM. Comparing against GMetis, we see that hMETIS-EE20 requires approximately the same time, whereas hMETIS-FM20 is about twice as slow. Note that GMetis runs METIS 100 times on each graph but each of these runs is substantially faster than hMETIS, partly because METIS is a highly optimized code for graphs, and partly because coarsening and refinement for hypergraphs is more complex than the refinement schemes used in METIS. However, both hMETIS-EE20 and hMETIS-FM20 produce bisections that cut substantially fewer hyperedges than GMetis.

Furthermore, from Table 1, we can see that our scheme is more powerful relative to the other schemes for larger hypergraph. For example, restricting to only the larger hypergraphs (with 10K or more nodes) in the benchmark set, we find that hMETIS-FM20 performs 4.8% better than the “Best”.

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4 Multi-Phase Refinement with Restricted Coarsening

Although the multilevel paradigm is quite robust, randomization is inherent in all three phases of the algorithm. In particular, the random choice of vertices to be matched in the coarsening phase can disallow certain hyperedge-cuts reducing refinement in the uncoarsening phase. For example, consider the example hypergraph in Figure 7(a), and its two possible condensed versions (Figure 7(b) and 7(c)) with the same partitioning. The version in Figure 7(b) is obtained by selecting hyperedges a and b to be compressed in the hyperedge coarsening phase and then selecting pairs of nodes (4,5), (6,7), and (8,9) to be compressed in modified hyperedge coarsening phase. Similarly, version in Figure 7(c) is obtained by selecting hyperedge c to be compressed in the hyperedge coarsening phase and then selecting pairs of nodes (6,7) and (8,9) to be compressed in modified hyperedge coarsening phase. In the version of Figure 7(b) vertex A(4,5) can be moved from partition P0 to P1 to reduce the hyperedge-cuts by 1, but in Figure 7(c) no vertex can be moved to get reduce the hyperedge-cuts.

What this example shows is that in a multilevel setting a given initial partitioning of hypergraph can be potentially refined in many different ways depending upon how the coarsening is performed. Hence, a partitioning produced by a multilevel partitioning algorithm can be potentially further refined if the two partitions are again coarsened in a manner different than the previous coarsening phase (which is easily done given the random nature of all the coarsening schemes described here). The power of iterative refinement at different coarsening levels can also be used to develop a partitioning refinement algorithm based on the multilevel paradigm.

The idea behind this multi-phase refinement algorithm is quite simple. It consists of two phases, namely a coars ening and an uncoarsening phase. The uncoarsening phase of the multi-phase refinement algorithm is identical to the uncoarsening phase of the multilevel hypergraph partitioning algorithm described in Section 2.3. The coarsening phase however is somewhat different, as it preserves the initial partitioning that is input to the algorithm. We will refer to this as restricted coarsening scheme. Given a hypergraph H and a partitioning P, during the coarsening phase a sequence of successively coarser hypergraphs and their partitionings is constructed. Let .Hi ; Pi / for i D 1; 2; : : : ;m, be the sequence of hypergraphs and partitionings. Given a hypergraph Hi and its partitioning Pi , restricted coarsening will collapse vertices together that belong only to one of the two partitions. That is, if A and B are the two partitions, we only collapse together vertices that either belong to partition A or partition B. The partitioning PiC1 of the next level coarser hypergraph HiC1 is computed by simply inheriting the partition from Hi . For example, if a set of vertices fv1; v2; v3g from partition A are collapsed together to form vertex ui of HiC1, then vertex ui belong to partition A as well. By constructing HiC1 and PiC1 in this way we ensure that the number of hyperedges cut by the partitioning is identical to the number of hyperedges cut by Pi in Hi . The set of vertices to be collapsed together in this restricted coarsening scheme can be selected by using any of the coarsening schemes described in Section 2.1, namely edge-coarsening, hyperedge-coarsening, or modified hyperedge-coarsening.

Due to the randomization in the coarsening phase, successive runs of the multi-phase refinement algorithm can lead to additional reductions in the hyperedge cut. Thus the multi-phase refinement algorithm can be performed iteratively. Note that during the refinement phase, we only propagate a single partitioning; thus, multi-phase refinement is quite fast.

In the context of our multilevel hypergraph partitioning algorithm, this new multi-phase refinement can be used in a number of ways. In the rest of this section we describe three such approaches.

V-Cycle In this scheme we take the best solution obtained from the multilevel partitioning algorithm (Pb) and we improve it using multi-phase refinement repeatedly. We stop the multi-phase refinement when the solution quality cannot be improved further. The number of multi-phase refinement steps performed is problem dependent and in general increases as the size of the hypergraph increases. This is because of the larger solution space of the large hypergraphs. Figure 8 shows multilevel partitioning followed by a V-cycle.

v-Cycle Our experience with the multilevel partitioning algorithm has shown that refining multiple solutions is expensive, especially during the final uncoarsening levels when the size of the contracted hypergraphs is large. One way to reduce the high cost of refining multiple solutions during the final uncoarsening levels is to select the best partitioning at some point in the uncoarsening phase and further refine only this best partitioning using multiphase refinement. This is the idea behind the v-cycle refinement.

In particular, let Hm=2 be the coarse hypergraph at the midpoint between H0 (original hypergraph) and Hm (coarsest hypergraph). Let Pm=2 be the best partitioning at Hm=2. Then we use (Hm=2, Pm=2) as the input to multi-phase refinement. This is illustrated in Figure 9. Since Hm=2 is relatively small as compared to Hm, multi-phase refinement converges in a small number of iterations. By using v-cycles, we can significantly reduce the amount of time spent in the refinement phase, especially for large hypergraphs. However, the overall quality can potentially decrease because we may have not picked up the best overall partitioning at Hm=2.

vV-Cycle We can combine both V-cycles and v-cycles in the algorithm to obtain high quality partitioning in small amount time. In this scheme we use v-cycles to partition the hypergraph followed by the V-cycles to further improve the partition quality. V-cycles used in this way are particularly effective in significantly improving the hyperedge cut.

6 Conclusions and FutureWork

As the experiments in Section 3 show, the multilevel paradigm is very successful in producing high quality hypergraph partitionings in relatively small amount of time. The multilevel paradigm is successful because of the following reasons. The coarsening phase is able to generate a sequence of hypergraphs that are good approximations of the original hypergraph. Then, the initial partitioning algorithm is able to find a good partitioning by essentially exploiting global information of the original hypergraph. Finally, the iterative refinement at each uncoarsening level is able to significantly improve the partitioning quality because it moves successively smaller subsets of vertices between the two partitions. Thus, in the multilevel paradigm, a good coarsening scheme results in a coarse graph that provides a global view that permits computations of a good initial partitioning, and the iterative refinement performed during the uncoarsening phase provides a local view to further improve the quality of the partitioning.

The multilevel hypergraph partitioning algorithm presented here is quite fast and robust. Even a single run of the algorithm is able to find reasonably good bisections. With a small number of runs (e.g., 20) our algorithm is able to find better bisections than those found by all previously known algorithms formany of the well-known benchmarks. Also, our algorithmscales quite well for large hypergraphs. hMETIS is very fast, often requiring 4 to 15 times less time than that required by the other schemes. The quality of the bisection produced by hMETIS can be further improved by using the multi-phase refinement algorithm described in [14].

The multilevel hypergraph partitioning algorithm presented here is quite fast and robust. Even a single run of the algorithm is able to find reasonably good bisections. With a small number of runs (e.g., 20) our algorithm is able to find better bisections than those found by all previously known algorithms for many of the well-known benchmarks.

Our algorithm scales quite well for large hypergraphs. Due to the multilevel paradigm, the number of runs required to obtain high quality bisections does not increase as the size of the hypergraph increases. High quality bisections of hypergraphs with over 100,000 vertices are obtained in a few minutes on today’s workstations. Also, since the coarsening phase runs in time proportional to the size of the hypergraph, the runtime of the scheme increases linearly with hypergraph size. Furthermore, the scheme appears to be more powerful relative to the other schemes for larger hypergraph (please refer to Figure 10). Restricting to only the larger hypergraphs (with 10K or more nodes) in the benchmark set, we find that hMETIS-FM20vV performs 29.5%, 15.8%, 11.3%, 20.4%, 14.6%, 16.3%, and 8.4% better than PROP, CDIP-LA3 f , CLIP-PROP f , PARABOLI, GFM, GMetis, and Optimized KLFM, respectively. Note that hypergraph-based multilevel scheme as presented in this paper significantly outperforms the graph based multilevel scheme GMetis [21] that used METIS [27] to compute bisections of graph approximations of hypergraph. The reasons for this performance difference are as follows. First hypergraph-based coarsening cause much greater reduction of the exposed hyperedge-weight of the coarsest level hypergraph, and thus provides much better initial partitions than those obtained with edge-based coarsening. Second, the refinement in the hypergraph-based multilevel scheme directly minimizes the size of hyperedge-cut rather than the edge-cut of the inaccurate graph approximation of the hypergraph. The power of hMETIS over GMetis is much more visible on the largest benchmark golem3 on which even the best of 100 different runs produced a cut that is 50% worse than 10 runs of hMETIS-FM20vV . hMETIS also significantly outperforms Optimized KLFM [17] by Hauck and Borriello even though they used powerful refinement schemes (FM with LA3 [4]). This is primarily due to the more powerful hyperedge coarsening schemes used in hMETIS

It may be possible to improve the quality of the bisection produced by this algorithm in many ways. Further research may identify better coarsening schemes that are suitable for a wider class of hypergraphs. New powerful variants of the FM refinement schemes have been developed recently by Dutt et al., [22, 23]. It will be instructive to include such a refinement scheme during the uncoarsening phase to see if it makes the multi-level scheme more robust. However, it is unclear if the added cost of these more powerful refinement schemes will result in a cost effective improvement in the size of the bisection, because additional trials of the multilevel scheme can be made to potentially improve the bisection. A version of hMETIS is available on the WWW at the following URL: http://www.cs.umn.edu/?metis.

hMETIS is written in C language and is available at

http://www.cs.umn.edu/?karypis/metis

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[27] G. Karypis and V. Kumar. METIS 3.0: Unstructured graph partitioning and sparse matrix ordering system. Technical Report 97-061, Department of Computer Science, University of Minnesota, 1997. Available on the WWW at URL http://www.cs.umn.edu/?metis.
[28] S. Shekhar and D. R. Liu. CCAM: A connectivity-clustered access method for networks and network computations. IEEE Transactions on Knowledge and Data Engineering, 9(1), 1997.
[29] C. Berge. Graphs and Hypergraphs. American Elsevier, New york, 1976.
[30] Michael R. Garey and David S. Johnson. Computers and Instractability: A Guide to the Theory of NP– Completeness. W.H Freeman, San Francisco, CA, 1979.
[31] T. Lengauer. Combinatorial Optimization: Networks and Matroids. Holt, Rinehart, and Winston, Boston, MA, 1976.
[32] Christos H. Papadimitriou and Kenneth Steiglitz. Combinatorial Optimization. Prentice Hall, Englewood Cliffs, NJ, 1982.
[33] G. Karypis and V. Kumar. A fast and highly quality multilevel scheme for partitioning irregular graphs. SIAM Journal on Scientific Computing, 1998 (to appear). Also available on WWW at URL http://www.cs.umn.edu/?karypis. A short version appears in Intl. Conf. on Parallel Processing 1995.

Hypergraph / Multilevel k-way Hypergraph okokok

Karypis, George and Kumar, Vipin: Multilevel k-way Hypergraph Partitioning May 1999 p15............

hypergraph

George Karypis and Vipin Kumar
Department of Computer Science & Engineering
Army HPC Research Center
University of Minnesota, Minneapolis, MN 55455
Technical Report #98–036
fkarypis, kumarg@cs.umn.edu

http://www.cs.umn.edu/?karypis

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Abstract

In this paper, we present a new multilevel k-way hypergraph partitioning algorithm that substantially outperforms the existing state-of-the-art K-PM/LR algorithmfor multi-way partitioning. both for optimizing local as well as global objectives. Experiments on the ISPD98 benchmark suite show that the partitionings produced by our scheme are on the average 15% to 23% better than those produced by the K-PM/LR algorithm, both in terms of the hyperedge cut as well as the .K ? 1/ metric. Furthermore, our algorithm is significantly faster, requiring 4 to 5 times less time than that required by K-PM/LR.

1 Introduction

Hypergraph partitioning is an important problem with extensive application to many areas, including VLSI design [10], efficient storage of large databases on disks [14], and data mining [13]. The problem is to partition the vertices of a hypergraph into k roughly equal parts, such that a certain objective function defined over the hyperedges is optimized. A commonly used objective function is to minimize the number of hyperedges that span different partitions; however, a number of other objective functions are also considered useful [10].

The most commonly used approach for computing a k-way partitioning is based on the recursive bisection paradigm, that reduces the problem of computing a k-way partitioning to that of performing a sequence of bisections. The problem of computing an optimal bisection of a hypergraph is at least NP-hard [24]; however, many heuristic algorithms have been developed. The survey by Alpert and Kahng [10] provides a detailed description and comparison of various such schemes. Recently a new class of hypergraph bisection algorithms has been developed [11, 26, 15, 22], that are based upon the multilevel paradigm. In these algorithms, a sequence of successively smaller (coarser) hypergraphs is constructed. A bisection of the smallest hypergraph is computed. This bisection is then successively projected to the next level finer hypergraph, and at each level an iterative refinement algorithm (e.g., KL [1] or FM [3]) is used to further improve the bisection. Experiments presented in [26, 15, 22] have shown that multilevel hypergraph bisection algorithms can produce substantially better partitionings than those produced by non-multilevel schemes. In particular, hMETIS [20], a multilevel hypergraph bisection algorithm based upon the work in [26] has been shown to find substantially better bisections than current state-of-the-art iterative refinement algorithms for the ISPD98 benchmark set that contains many large circuits [18].

Despite the success of multilevel recursive bisection algorithms, there are a number of advantages of computing the k-way partitioning directly (rather than computing it successively via recursive bisection). First, a recursive bisection algorithm does not allows us to directly optimize objectives that are global in nature and depend on having a direct view of all k partitions. Some examples of such objectives are the sum of external degrees (SOED), scaled cost, and absorption [10]. Second, a k-way partitioning algorithm is capable of enforcing tighter balancing constraints while retaining the ability to sufficiently explore the feasible solution space to optimize the partitioning objective. This is especially true when the partitioning solution must simultaneously satisfy multiple balancing constraints [21]. Third, a method that obtains a k-way partitioning directly can potentially produce much better partitionings than a method that computes a k-way partitioning via recursive bisection [8].

For these reasons, researchers have investigated a number of k-way partitioning algorithms that try to compute a k-way partitioning directly, rather than via recursive bisection. The most notable of them are the generalization of the FM algorithm for k-way partitioning [4, 7], the spectral multi-way ratio-cut [6], the primal-dual algorithm of [5], the geometric embedding [9], the dual-net method [12], and the K-PM/LR algorithm [19]. A key problem faced by some of these algorithms is that the k-way FM refinement algorithm easily gets trapped in local minima. The recently developed K-PM/LR algorithm by Cong and Lim [19] attempts to solve this problem by refining a k-way partitioning by applying a sequence of 2-way FM refinement to pairs of domains. The pairing of domains is based on the gain of the last pass, and the pairwise cell movement passes continues until no further gain can be obtained. The experiments presented in [19] have shown that K-PM/LR outperforms the k-way FM partitioning algorithm of Sanchis [4, 7] by up to 86.2% and outperforms the recursive FM partitioning algorithm by up to 17.3%. Nevertheless, all of the above partitioners tend to produce solutions that are inferior to those produced by the state-of-the-art multilevel recursive bisection algorithms, especially when they are used to optimize an objective that can directly be optimized by the recursive bisection framework (e.g., minimize the hyperedge cut) [18].

In this paper we present a new k-way partitioning algorithmthat is based on the multilevel paradigm. The multilevel paradigm can be used to directly construct a k-way partitioning of a hypergraph using the framework illustrated in Figure 1. The hypergraph is coarsened successively as before. But the coarsest hypergraph is now directly partitioned into k parts, and this k-way partitioning is successively refined as the partitioning is projected back into the original hypergraph. A key contribution of our work is a simple and yet powerful scheme for refining a k-way partitioning in the multilevel context. This k-way partitioning refinement scheme is substantially simpler and faster than either the k-way FM[4], or the K-PM/LR algorithm[19], but is equally effective in the multilevel context. Furthermore, this new k-way refinement algorithm is inherently parallel [17] making it possible to develop high-quality parallel hypergraph partitioning algorithms.

Figure 1: The various phases of the multilevel k-way partitioning algorithm. During the coarsening phase, the size of the hypergraph is successively decreased; during the initial partitioning phase, a k-way partitioning of the smaller hypergraph is computed (a 6-way partitioning in this example); and during the uncoarsening phase, the partitioning is successively refined as it is projected to the finer (larger) hypergraphs.

We evaluate the performance of our multilevel k-way partitioning algorithmboth in terms of the partitioning quality as well as computational requirements on the ISPD98 benchmark [18]. Our experiments show that the multilevel kway hypergraph partitioning algorithm produces high quality partitioning in a relatively small amount of time. The quality of the partitionings produced by our scheme are on the average 15% to 23% better than those produced by the K-PM/LR [19] algorithm, both in terms of the hyperedge cut as well as the .K ?1/ metric. Furthermore, our algorithm is significantly faster, requiring 4 to 5 times less time than that required by K-PM/LR and provides partitions that adhere to tighter balancing constraints. Compared to the state-of-the-art multilevel recursive bisection, our experiments show that with respect to the hyperedge cut, our algorithm produces partitions of comparable quality, whereas with respect to the SOED, our algorithm produces partitions that are up to 18% better. Furthermore, our multilevel k-way partitioning algorithm is in general two times faster than multilevel recursive bisection, and this ratio increases with the size of the hypergraph.

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2 Multilevel k-way Hypergraph Partitioning

Formally, a hypergraph G D .V; E/ is defined as a set of vertices V and a set of hyperedges E, where each hyperedge is a subset of the vertex set V [23], and the size of a hyperedge is the cardinality of this subset. The k-way hypergraph partitioning problem is defined as follows: Given a hypergraph G D .V; E/ (where V is the set of vertices and E is the set of hyperedges) and an overall load imbalance tolerance c such that c  1:0, the goal is to partition the set V into k disjoint subsets, V1; V2; : : : ; Vk such that the number of vertices in each set Vi is bounded by jVj=.ck/  jVij  cjVj=k, and a function defined over the hyperedges is optimized.

The requirement that the size of each partition is bounded is referred to as the partitioning constraint, and the requirement that a certain function is optimized is referred to as the partitioning objective. Over the years, a number of partitioning objective functions have been developed. The survey by Alpert and Kahng [10] provides a comprehensive description of a variety of objective functions that are commonly used for hypergraph partitioning in the context of VLSI design.

One of the most commonly used objective function is to minimize the hyperedge-cut of the partitioning; i.e., the total number of hyperedges that span multiple partitions. Another objective that is often used is to minimize the sum of external degrees (SOED) of all hyperedges that span multiple partitions. Given a k-way partitioning and a hyperedge e, the external degree of e is defined to be 0, if e is not cut by the partitioning, otherwise it is equal to the number of partitions that is spanned by e. Then, the goal of the partitioning algorithm is to compute a k-way partitioning that minimizes the sum of external degrees of the hyperedges. An objective related to SOED is to minimize the .K ? 1/ metric [10, 19]. In the case of the .K ? 1/ metric, the cost of a hyperedge that spans K partitions is .K ? 1/, whereas for the SOED metric, the cost is K.

2.1 Coarsening Phase

During the coarsening phase, a sequence of successively smaller hypergraphs is constructed. As in the case of the multilevel hypergraph bisection algorithm [16], the coarsening phase servers the following three purposes. First it leads to a small hypergraph such that a good k-way partitioning of the small hypergraph is not significantly worse than the k-way partitioning directly obtained for the original hypergraph. Second, the different successively coarsened versions of the hypergraph allow local refinement techniques such as FM to become effective. Third, hypergraph coarsening also helps in successively reducing the sizes of the hyperedges. That is, at each level of coarsening, large hyperedges are contracted to smaller hyperedges. This is particularly helpful, since refinement heuristics based on the KLFMfamily of algorithms [1, 2, 3] are very effective in refining small hyperedges but are quite ineffective in refining hyperedges with a large number of vertices belonging to different partitions.

Two primary schemes have been developed for selecting what groups of vertices will be merged together to form single vertices in the next level coarse hypergraphs. The first scheme called edge-coarsening (EC) [16, 15, 22], selects the groups by finding a maximal set of pairs of vertices (i.e., matching) that belong in many hyperegdes. In this scheme, each group consists of at most two vertices (some vertices are not combined at all), and each vertex belongs to exactly one group. The second scheme that is called hyperedge-coarsening (HEC) [16] finds a maximal independent set of hyperedges, and the sets of vertices that belong to each hyperedge becomes a group of vertices to be merged together. In this scheme, each group can have an arbitrary number of vertices (even though preference is given to smaller groups), and each vertex also belongs to exactly one group. Experiments in [16] show that for certain problems, the hyperedge-coarsening scheme and its variations tend to outperform the edge-coarsening scheme, as they do a better job of reducing the total hyperedge weight of successively coarser hypergraphs.

However, both the edge- and the hyperedge-coarsening schemes share one characteristic that can potentially lead to less than ideal coarse representations of the original hypergraph, especially for hypergraphs corresponding to circuits. This common characteristic is that the grouping schemes employed by both approaches find maximal independent groups. That is, both the edge- and the hyperedge-coarsening schemes will find as many groups of vertices as they can, that are pair- or hyperedge-wise independent. The potential problem with this approach is that the independence (and to a certain degree, the maximality) requirement may destroy some clusters of vertices that naturally exist in the hypergraph. To see that consider the example shown in Figure 2(a). As we can see from this figure there are two natural clusters. The first cluster contains the five vertices on the left and the second cluster contains the five vertices on the right. These two clusters are connected by a single hyperedge; thus the natural cut for this hypergraph is one. Figure 2(b) shows the pairs of vertices that are found by the edge-coarsening scheme. In the edge-coarsening scheme, vertex F will prefer to merge with vertex G, but vertex G had already been grouped with vertex H, consequently, vertex E is grouped together with vertex E. Once the hypergraph is coarsened as shown in Figure 2(c), we can see that the natural separation point in this hypergraph has been eliminated, as it has been contracted in the vertex that resulted from merging E and F. A similar kind of example can be constructed using the hyperedge-coarsening as well.

Figure 2: An example in which the edge-coarsening scheme can lead to a coarse representation in which the natural clusters of the hypergraph have been obscured. The weights on the hyperedges of the coarse hypergraph (c) represent the number of hyperedges in the original hypergraph that span the same set of vertices in the coarse representation.

The above observation, led us to develop a new coarsening scheme that we will refer to as the FirstChoice (FC) coarsening scheme. The FC coarsening scheme is based up on the edge-coarsening scheme, and understanding how the EC scheme works is essential in understanding FC. In the rest of this section we briefly describe the EC scheme (further details can be found in [16, 15]), and describe how FC can be derived by modifying EC.

In the EC coarsening scheme, the vertices are visited in a random order. For each vertex v, all unmatched vertices that belong to hyperedges incident to v are considered, and the one that is connected via the edge with the largest weight is matched with v. The weight of an edge connecting two vertices v and u is computed as the sum of the edge-weights of all the hyperedges that contain v and u. Each hyperedge e of size jej is assigned an edge-weight of 1=.jej?1/, and as hyperedges collapse on each other during coarsening, their edge-weights are added up accordingly. This edge coarsening scheme is similar in nature to the schemes that treat the hypergraph as a graph by replacing each hyperedge with its clique representation [25]. However, this hypergraph to graph conversion is done implicitly during matching without forming the actual graph.

The FC coarsening scheme is derived from the EC coarsening scheme by relaxing the requirement that a vertex is matched only with another unmatched vertex. Specifically, in the FC coarsening scheme, the vertices are again visited in a random order. However, for each vertex v, all vertices (both matched and unmatched) that belong to hyperedges incident to v are considered, and the one that is connected via the edge with the largest weight is matched with v, breaking ties in favor of unmatched vertices. As a result, each group of vertices to be merged together can contain an arbitrarily large number of vertices. The one potential problem with this coarsening scheme is that the number of vertices in successive coarse graphs may decrease by a large factor, potentially limiting the effect of refinement [15]. For this reason, at each coarsening level, we stop the FC coarsening scheme as soon as the size of the resulting coarse graph has been reduced by a factor of 1.7. Our experiments have shown that by controlling the rate of coarsening in this fashion, we can ensure that there are sufficiently many coarsening levels, and that the refinement algorithm is effective in improving the partitioning quality during the uncoarsening phase.

The coarsening phase ends when the coarsest hypergraph has a small number of vertices. Since our goal is to compute a k-way partitioning, the number of vertices in this smaller hypergraph should be a function of k, to ensure that a reasonably balanced partitioning can be computed by the initial partitioning algorithm. In our experiments, for a k-way partition, we stop the coarsening process when the number of vertices becomes less than ck, where c D 100.

2.2 Initial Partitioning Phase

The second phase of a multilevel k-way partitioning algorithm is to compute a k-way partitioning of the coarsest hypergraph such that the balancing constraint is satisfied and the partitioning objective is optimized. Since during coarsening, the weights of the vertices and hyperedges of the coarser hypergraph were set to reflect the weights of the vertices and hyperedges of the finer hypergraph, the coarsest hypergraph contains sufficient information to intelligently enforce the balancing constraint and optimize the partitioning objective.

One way to produce the initial k-way partitioning is to keep coarsening the hypergraph until it has only k vertices left. These coarse k vertices can serve as the initial k-way partitioning of the original hypergraph. There are two problems with this approach. First, for many hypergraphs, the reduction in the size of the hypergraph in each coarsening step becomes very small after some coarsening steps, making it very expensive to continue with the coarsening process. Second, even if we are able to coarsen the hypergraph down to only k vertices, the weights of these vertices are likely to be quite different, making the initial partitioning highly unbalanced. In our algorithm, the k-way partitioning of the coarsest hypergraph is computed using our multilevel hypergraph bisection algorithm [16], that is available in the hMETIS package [20].

2.3 Uncoarsening Phase

During the uncoarsening phase, a partitioning of the coarser hypergraph is successively projected to the next level finer hypergraph, and a partitioning refinement algorithm is used to optimize the objective function without violating the partitioning balancing constraints. Since the next level finer hypergraph has more degrees of freedom, such refinement algorithms tend to improve the solution quality.

In the case of bisection refinement, the FMalgorithm [3] has been shown to produce very good results [16]. For each vertex v, the FM algorithm computes the gain which is the reduction in the value of the objective function achieved by moving v to the other partition. These vertices are inserted into two priority queues, one for each partition, according to their gains. Initially all vertices are unlocked, i.e., they are free to move to the other partition. The algorithm iteratively selects an unlocked vertex v with the largest gain from one of the two priority queues and moves it to the other partition. When a vertex v is moved, it is locked and the gain of the vertices adjacent to v are updated. After each vertex movement, the algorithm also records the value of the objective function achieved at this point. A single pass of the algorithm ends when there are no more unlocked vertices. Then, the recorded values of the objective function are checked, and the point where the minimum value was achieved is selected, and all vertices that were moved after that point are moved back to their original partition. Now, this becomes the initial partitioning for the next pass of the algorithm.

However, refining a k-way partitioning is significantly more complicated because vertices can move from a partition to many other partitions; thus, increasing the optimization space combinatorially. An extension of the FM refinement algorithm in the case of k-way refinement is described in [4]. This algorithm uses k.k ? 1/ priority queues, one for each type of move. In each step of the algorithm, the moves with the highest gain are found from each of these k.k?1/ queues, and the move with the highest gain that preserves or improves the balance, is performed. After the move, all of the k.k ? 1/ priority queues are updated. The complexity of k-way refinement is significantly higher than that of 2-way refinement, and is only practical for small values of k. Furthermore, as the experiments in [19] suggest, the k-way FM algorithm is also very susceptible of being trapped into a local minima that is far from being optimal.

Table 1: The characteristics of the various hypergraphs used to evaluate the multilevel hypergraph partitioning algorithms.

The hill-climbing capability of the FM algorithm serves a very important purpose. It allows movement of an entire cluster of vertices across a partition boundary. Note that it is quite possible that as the cluster is moved across the partition boundary, the value of the objective function increases, but after the entire cluster of vertices moves across the partition, then the overall value of the objective function comes down. In the context of multilevel schemes, this hill-climbing capability becomes less important. The reason is that these clusters of vertices are coarsened into a single vertex at successive coarsening phases. Hence, movement of a vertex at a coarse level really corresponds to the movement of a group of vertices in the original hypergraph.

If the hill-climbing part of the FM algorithm is eliminated (i.e., if vertices are moved only if they lead to positive gain), then it becomes less useful to maintain a priority queue. This is because vertices whose move results in a large positive gain will most likely be moved anyway even if they are not moved earlier (in the priority order). Hence, a variation of the FM algorithm that simply visits the vertices in a random order and moves them if they result in a positive gain is likely to work well in the multilevel context. Furthermore, the complexity of this algorithm will be independent of the number of partitions being refined, leading to a fast algorithm. This observation has lead to us to develop a greedy refinement algorithm. It consists of a number of iterations. In each iteration all the vertices are checked to see if they can be moved so that the partitioning objective function is optimized, subject to the partitioning balancing constraint (as described in Section 2). As the results in Section 3 show, despite the simplicity of our refinement algorithms, they produce high quality partitionings in small amount of time.

More precisely, our greedy k-way refinement algorithm works as follows. Consider a hypergraph Gi D .Vi ; Ei /, and its partitioning vector Pi . The vertices are visited in a random order. Let v be such a vertex, let Pi TvU D a be the partition that v belongs to. If v is a node internal to partition a then v is not moved. If v is at the boundary of the partition, then v can potentially be moved to one of the partitions N.v/ that vertices adjacent to v belong to (the set N.v/ is often refer to as the neighborhood of v). Let N0 .v/ be the subset of N.v/ that contains all partitions b such that movement of vertex v to partition b does not violate the balancing constraint. Now the partition b 2 N0 .v/ that leads to the greatest positive reduction (gain) in the objective function is selected and v is moved to that partition.

The above greedy refinement algorithm can be used to compute a partitioning that minimizes a variety of objective functions, by appropriately computing the gain achieved in moving a vertex. Our current implementation allows a choice of two different objective functions. The first minimizes the hyperedge cut and the second minimizes the sum of external degrees (SOED) (Section 2). Experiments with this greedy k-way refinement algorithm show that it converges after a small number of iterations. In our experiments, we found that for most hypergraphs, the algorithm converged within four to eight iterations.

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Journal, 21(4), 1996.
[15] C. J. Alpert, J. H. Huang, and A. B. Kahng. Multilevel circuit partitioning. In Proc. of the 34th ACM/IEEE Design Automation
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domain. In Proceedings of the Design and Automation Conference, 1997.
[17] George Karypis and Vipin Kumar. A coarse-grain parallel multilevel k-way partitioning algorithm. In Proceedings of the
eighth SIAM conference on Parallel Processing for Scientific Computing, 1997.
[18] C. J. Alpert. The ISPD98 circuit benchmark suite. In Proc. of the Intl. Symposium of Physical Design, pages 80–85, 1998.
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Design, 1998.
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domain. IEEE Transactions on VLSI Systems, 1998 (to appear). A short version appears in the proceedings of DAC 1997.

Hypergraph

Karypis, George: Multilevel Algorithms for Multi-Constraint Hypergraph Partitioning p10

Hypergraph

Kumar, Amit et al: Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing, 2011 EDAA p6 ............ 2

Kumar Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing p6

Kumar Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing p6

[4] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: applications in vlsi domain. IEEE Trans. VLSI Syst., 7(1):69–79, 1999.

[5] G. Karypis and V. Kumar. Multilevel k -way hypergraph partitioning. DAC, pages 343–348, 1999.

[14] M. Ouyang, M. Toulouse, K. Thulasiraman, F. Glover, and J.S. Deogun. Multilevel cooperative search for the circuit/hypergraph partitioning problem. IEEE Trans. on CAD, 21(6):685 –693, jun. 2002.

Hyper-Graph

weighted hypergraph

coarser hypergraph

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Abstract—

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

I. INTRODUCTION

.........................

In this work we propose a DFT method for pre-bond testing of 3D ICs using a hypergraph [4] based netlist partitioning scheme. Hypergraph based netlist partitioning is a method that has been used for various applications in VLSI design, for example design packaging, HDL synthesis, design optimization and design partitioning [4], [5]. In general the approaches have to be adapted to the problem at hand to work in a sufficiently efficient and effective way. Here, this is done for the first time in the context of partitioning a design to facilitate pre-bond testing of 3D-ICs. We show the efficiency of our approach by experimental evaluations and comparison to the results of applying an earlier partitioning procedure [4]. The main features and advantages of the proposed scheme are summarized below:

1) Proposed partitioning scheme leads to equal cluster/die sizes. All dies have approximately same amount of logic, resulting in saving in terms of area.

2) Partitioning algorithm assigns weights on hyperedges such that cut obtained is biased towards placing a flipflop at cut, resulting in savings of additional flip-flops required at each connection coming in/out of the die from another die.

3) Further saving of hardware is achieved by sharing flipflops [3] at the incoming and outgoing connections of a die.

In section II we give the motivation for this work followed by basic definitions. Basic concepts related to hypergraph based netlist partitioning are presented in Section III. The proposed hypergraph based biased netlist partitioning algorithm is presented in Section IV. Section V deals with the flip-flop sharing scheme. In section VI we discuss experimental results obtained. We conclude the paper is section VII.
II. MOTIVATION

.........................

DEC APLHA 21364 [2] uses a segmentation technique in which the circuit was divided into individual segments with registers at the border. During test mode registers isolate each segment, in normal mode they allow free movement of data from one segment to another. In [2], the entire circuit netlist is partitioned into several smaller circuit blocks called scan islands. Each island houses parallel local scan-chains and can be controlled and observed independently during test mode. Similar architecture for pre-bond 3D IC testing has been proposed in [9]. Fig. 2 shows a scan-island based test architecture, layer1 and layer2 form two different scan-islands (on different dies) and both can be tested independently of each other. Extra flip-flops are added at all the incoming and out-going connections of a die from another die, if a flipflop is not present on the interconnection. All flip-flops on a die are stitched together to form a scan-chain. Hypergraph based biased netlist partitioning and flip-flop sharing scheme’s proposed in this work, use scan-island based architecture. In pre-bond test individual dies forms independent scan-islands. The advantages of scan-island architecture are:
III. BASIC CONCEPTS RELATED TO HYPERGRAPH BASED NETLIST PORTITIONING

In this section we present some basic concepts and definitions used in this work.

Definition of Hypergrah

A hypergraph is a generalization of a graph, where the set of edges is replaced by a set of hyperedges. A hyperedge extends the notion of an edge by allowingmore than two vertices to be connected by a hyperedge. Formally, a hypergraph H= (V; Eh) is defined as a set of vertices V and a set of hyperedges Eh, where each hyperedge is a subset of the vertex set V [29], and the size a hyperedge is the cardinality of this subset.

A Hypergrah H = (V;E) is a set of vertices V and a set of hyperedges E, where each hyperedge is a subset of the vertex set V [4], [5]. E is the set of m hyperedges which are used to represent the nets of the circuit. The set E is a subset of the power set of 2V of the vertices V in H.

A Hypergrah H = (V;E) is a set of vertices V and a set of hyperedges E, where each hyperedge is a subset of the vertex set V [4], [5]. E is the set of m hyperedges which are used to represent the nets of the circuit. The set E is a subset of the power set of 2V of the vertices V in H.

A weighted hypergraph has non-negative numeric weights associated with each vertex, or each hyperedge, or both. Conventional graphs are a special case of hypergraphs, where all edges are defined by subsets of vertices of size two. Fig. xxx shows a circuit and its corresponding hypergraph.

A weighted hypergraph has non-negative numeric weights associated with each vertex, each hyperedge, or both. Conventional graphs are a special case of hypergraphs, where all edges are defined by subsets of vertices of size two. Fig. 3 shows a circuit and its corresponding hypergraph.

Fig. 3. Fig. HGBP 1 . Transformation of a circuit G in to hypergraph H. (i)Circuit G. (ii)Vertices of hypergraph H. (iii) Hyperedges added to H. (iv) Weight added to hyperedges.

Hierarchical Clustering:

Let

Ci : V ??! 2V ; i = 1; : : : ; l
be a family of l mappings where Ci maps the vertices of H into jVij clusters Ci1;Ci2; : : : ;CijVij such that Ciu \Civ= if u 6= v and SjV ij
j=1 Cij=V . The family of mappings mentioned above defines the hierarchical clustering [14] of vertices in H whenever jVij > jVi+1j for all i = 1; : : : ; l ?? 1.

Let Ci : V -> ! 2V ; i = 1; : : : ; l
be a family of l mappings where Ci maps the vertices of H into |Vi| clusters Ci1;Ci2; : : : ;CiVi such that Ciu ∩ Civ= ∅ if u≠v and ∪ j = 1 | Vi | Cij=V . The family of mappings mentioned above defines the hierarchical clustering [14] of vertices in H whenever |Vi| > |Vi+1| for all i = 1; : : : ; l -?? 1.

Coarsened Hypergraph:

A coarsened hypergraph [14] Hi = (Vi;Ei) is the set of vertices Vi and hyperedges Ei such that: 1) v 2 Vi is a cluster (subset) Cij of vertices from V as defined by the mapping Ci (Note: to simplify notation, v may also be denoted by the corresponding cluster Cij ) and 2) a subset e of Vi is a hyperedge of Hi if and only if there exists a hyperedge e02 E such that e0 has nonempty intersection with each cluster represented by the vertices in e.

Coarsened Hypergraph:

A coarsened hypergraph [14] Hi = (Vi;Ei) is the set of vertices Vi and hyperedges Ei such that:

1) v ∈ ∈ Vi is a cluster (subset) Cij of vertices from V as defined by the mapping Ci (Note: to simplify notation, v may also be denoted by the corresponding cluster Cij )

and 2) a subset e of Vi is a hyperedge of Hi if and only if there exists a hyperedge e' ∈E such that e' has nonempty intersection with
each cluster represented by the vertices in e.

k-way hypergrah partitioning: A k-way partitioning Pk=fC1;C2; : : : ;Ckg consists of k clusters (subsets of V ), C1;C2; : : : ;Ck such that C1[C2[: : :Ck = V and Ci\Cj= for 1  i  k and 1  j  k. if k= 2 we refer to P2 as bipartitioning.

k-way hypergrah partitioning:

A k-way partitioning Pk={C1;C2; : : : ;Ck} consists of k clusters (subsets of V ), C1;C2; : : : ;Ck such that C1∪C2∪ : : :Ck = V and C ∪ Cj= ∅ for 1 ≤ i ≤ k and 1 ≤ j ≤ k. if k= 2 we refer to P2 as bipartitioning.

Cutsize or Cost of Cut : The set of hyperedges cut by cluster C is given by E(C)=e 2 E s:t: 0 < je \ Cj < jej, i.e., e 2 E(C) if at least one, but not all, of pins of e are in C. The set of nets cut by a partitioning solution Pk can be expressed as E(Pk) = Sk h=1E(Ci) or equivalently E(Pk)= fe 2 Ej9u; v 2 e; h 6= l with u 2 Ch and v 2 Clg. We say that jE(Pk)j is the cost or size of cut Pk.

Cutsize or Cost of Cut :

The set of hyperedges cut by cluster C is given by E(C)=e ∈ E s:t: 0 < |e∩ C| < |e|, i.e., e ∈ E(C) if at least one, but not all, of pins of e are in C. The set of nets cut by a partitioning solution Pk can be expressed as E( Pk) = ∪ h = 1 k Ec i or equivalently E( Pk)= {e ∈ E | ∃ u; v ∈ e; h ≠ ll with u ∈ Ch and v ∈ Cl }. We say that |E(Pk)| is the cost or size of cut Pk.

With balance constraints the problem of k-way hypergraph partitioning is known to be NP complete [4], [5]. The proof of NP completeness can be derived from mapping the problem instance to subset-sum problem [15]. We propose a partitioning algorithm that attains the dual goal of reducing cut size and biasing the cut, such that majority of nets on the cut are driven by a flip-flop. Any hyperedge e on cut maps into a costly TSV in 3D IC. In this work we focus on bi-partitions, i.e. division of V into two partitions (dies) V1 and V2 such that V1 [ V2 = V , V1 \ V2 =  and jV1j  jV2j.

With balance constraints the problem of k-way hypergraph partitioning is known to be NP complete [4], [5]. The proof of NP completeness can be derived from mapping the problem instance to subset-sum problem [15]. We propose a partitioning algorithm that attains the dual goal of reducing cut size and biasing the cut, such that majority of nets on the cut are driven by a flip-flop. Any hyperedge e on cut maps into a costly TSV in 3D IC. In this work we focus on bi-partitions, i.e. division of V into two partitions (dies) V1 and V2 such that V1∪ V2 = V , V1 ∩V2 = ∅  and |V1| ≈ |V2|.

IV. K-WAY HYPERGRAPH BASED BIASED NETLIST PARTITIONING ALGORITHM

We now present hypergraph based biased netlist partitioning algorithm in this section. The proposed method is used for partitioning a design across k dies (partitions). For the sake of simplicity we discuss in detail two way partitoning in this work.

A. Algorithm Description

The algorithm can be broadly divided into four parts, transforming circuit netlist to a weighted hypergraph, merging phase followed by a random bisection phase. Later an uncoarsening and a refinement phase are run.

1) Hypergrah Construction from Netlist and Selective Weight Assignment:

Hypergraph [4], [5], [14] construction for a circuit netlist is discussed below . An integer index is allocated to each node v and edge e in hypergraph H.

Consider a circuit netlist G with n cells (combinational gates /buffers /primary-inputs /flip-flops). Allocate an index to every cell G=(g1; g2; : : : ; gn). Every net of circuit G originates at a cell gi and feeds a given number of say p cells.

1) For every cell gi in G there exists a vertex vi in the hypergraph H. Fig HGBP 1 (ii) shows the vertices of hypergraph H corresponding to circuit G in Fig HGBP 1 (i).
2) Every Hyperedge in H corresponds to a net in circuit G. Fig HGBP 1 (iii) illustrates hypergraph H with hyperedges added. Each hyperedge ei, corresponds to a net, fed by cell gi. Index i for hyperedge in ei in H is the same as cell gi.
3) A weight of 1 is assigned to hyperedge hi if gi is driven by a flip-flop, else, hi is assigned a weight of w > 1. Fig HGBP 1 (iv) shows weight assignments to hyperedges of H. In our implementation we used w = 10.

2) Merging Phase:

The initial merging phase is based on hierarchal clustering [4]. Vertices connected with heavier hyperedges are merged first. We randomly select hyperedges for merging if more that one hyperedge has the same weight. Fig. HGBP 2 shows an example of heavy hyper-edge based merging scheme. Since hyperedges not driven by a flip-flop are heavier, they have a higher probability of getting merged. Heavy edge merging increases the possibility of a biased bipartition, with more flip-flops on the cut.

Fig. 4. Fig. HGBP 2 An illustration of heavy edge merging in hypergraph.
Example: Consider a hypergraph H(V;E), shown in Fig. HGBP 2 (i), with 5 vertices V =(v1; v2; v3; : : : ; v5) and 3 hyperedges
E=(A;B;C), with weights wA=12, wB=5, wC=11, respectively. Heavy hyperedge merging algorithm will merge vertices v1; v2 corresponding to hyperedge A (heaviest hyperedge) into vertex vA, as shown in Fig. HGBP 2 (ii) to form hypergraph H1. In the next step vertices’s v4; v5 corresponding to hyperedge C with weight 11 are merged to form vertex vC, as illustrated in Fig.HGBP 2 (iii) to form hypergraph H2. After merging k hyperedges original hypergraph H (corresponding to netlist G) is reduced to a smaller hypergraph Hk. A bisection of the merged hypergraph is created and the solutions are refined using Kernighan-Lin algorithm. Kernighan-Lin (KL) algorithm [4] takes a greedy approach to interchange elements of two partitions to find a better solution i.e. reduce cut size. KL algorithm are known to be quite effective in refining solution of hyperedges with small number of vertices and inefficient for large number of vertices.

3) Random Bisection:

A bisection of the hypergraph Hk is obtained for a coarser hypergraph Hk with approximately 200 nodes, such that it has a small cut size, and divides the vertices V into two equal parts [14]. Since this hypergraph has a very small number of vertices, the time to find a partition (of netlist G) using any of the heuristic algorithms tends to be small. Note that it is not useful to find an optimal partition of this hypergraph Hk, as the initial partition will be substantially modified during the refinement phase [5]. In our procedure
we derived several cuts and only the best one was further processed.

4) Desplitting and Refinement:

During the desplitting phase, we start with merged vertices of the coarser hypergraph Hk (obtained from merging k hyperedges of original hypergraph H). Merged vertices are uncoarsened (un-merged) again to form original hypergraph H (the graph before merging phase) in k successive steps. Only one hyperedge is unmerged in one step. Cut size of merged hypergraph Hk remains same as that of un-merged (original) hypergraph H i.e. circuit netlist G with partitions. All incoming hyperedges to merged vertices
were connected to final merged vertex during the merging phase, resulting in the same cut size of hypergraph Hk and H. Cut sizes of intermediate hypergraphs Hm-1; : : : ;H (obtained during various steps in demerging phase) are further reduced by use of the Fiduccia-Mattheyses (FM) algorithm [4], [5]. The FM algorithm makes linear time passes to iteratively improve cut sizes by moving each vertex exactly once. FM works by prioritizing moves by gain. A move changes to which partition a particular vertex belongs and the gain is the corresponding change to the cut size. After each vertex is moved, gains for connected modules are updated.

B. Complexity Analysis for Partitioning Algorithm

We take an incremental approach for complexity analysis of hypergrah partitioning algorithm discussed above. Merging phase consists of merging vertices with heaviest hyperedges, which can be done in O(V ) times. Heaviest hyperedge can be found in O(log(E)). Overall complexity of merging operation is O(V log(E)). Random Bisection of a merged hypergaph is an O(V ) operation. Desplitting and Refinement is the last step. Desplitting takes same time as that for merging. However, refining the partitions created using FM algorithm takes O(V2). Therefore the overall complexity of the algorithm is of the order of O(V2).

VI. EXPERIMENTAL RESULTS AND DISCUSSIONS

A comprehensive set of experiments were performed on a linux workstation with Intel Xeon 2GHZ, 8 core processor and 16GB RAM. Experiments were performed on various academic benchmarks and industrial circuits provided by NXP. The proposed partitioning approach creates approximately equally sized partitions with small cut size and large percentage nets on cut were driven by a flip-flop. This leads to low TSV count and less number of additional flip-flops required for pre-bond testing. Hypergraph is constructed directly from the structural circuit. In this work we partition the circuit into two parts, however k-way partitioning can be performed by repartitioning of already obtained partitions as discussed in [4]. A weight is assigned to each node in the hypergrah. Weights to hyperedges are assigned according to the scheme presented in Section III, a lower weight to hyperedges driven by a flip-flop and a very large weight to other hyperedges.

We define weight ratio, w as the ratio of the weight assigned to nets driven by gates/buffers/primary-inputs and the weight assigned to edges driven by a flip-flop.. After exhaustive experimentation we obsereved that use of w = 10 lead to a reduced cut size with large number of flip-flops on the cut as desired. A very high value of w resulted in an increased cut size (thus more TSV’s) and low value of w resulted in reduced flip-flop count on cut. The cut size and number of flip-flops on cut, using the proposed scheme, are reported for two values of weight ratio (w) 1 and 10, respectively in Table I. We also compare our results with that by hmetis [4], [5], a hypergraph partitioning package available at http://glaros.dtc.umn.edu/gkhome/metis/hmetis/overview. The allowed imbalance between partitions generated using hmetis was set to 1% and is the same as that used in the proposed procedure.

The proposed netlist partitioning scheme produced high quality bi-partitions, typically more than 80% of nets on the cut were driven by flip-flops. Considering circuit Indus-3, for w = 10, cut size=223 and the number of flip-flops on cut=214, i.e. approximately 96% of nets on the cut were driven by design flip-flops. However, using hmetis, a cut size of 273 and 22 flip-flops on the cut were obtained. Compared to hmetis the proposed hypergraph based biased netlist partioning scheme with w = 10 resulted in smaller cut sizes in 7 out of 11 circuits. Additionally, as desired, considerably higher portion of the cut by the proposed method includes flipflops for all circuits. Table I shows that runtime for the proposed procedure increases almost linearly with circuit size. The proposed scheme was in general fast and a 3 million gate circuit took approximately only 17 minutes to partition. Runtimes for hmetis are shown in the last column of Table I.

VII. CONCLUSION

In this paper, a pre-bond 3D IC testing scheme is proposed. This technique uses hypergraph based biased netlist partitioning and flip-flop sharing. Biased netlist partitioning attains a dual goal of keeping cut size low with large percentage of nets on the cut were driven by flip-flops, thus reducing hardware. Logic cone based flip-flop sharing approach allows controllability and observability of pseudo-primary input/output without adding any additional flip-flops. Experimental results shows a significant reduction in the hardware required for scan-island based pre-bond testing.


Graph Model / Representations for 3D IC Design

Hypergraph, Hyper-graph, Hyper graph

Hypergraph

LEE, WAN-YU; JIANG, IRIS HUI-RU AND MEI, TSUNG-WAN: Generic Integer Linear Programming Formulation for 3D IC Partitioning p16 JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 28, 1129-1144 (2012)

LEE Generic Integer Linear Programming Formulation for 3D IC Partitioning p16 /////////////////////////// 5

LEE Generic Integer Linear Programming Formulation for 3D IC Partitioning? p14

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

2. PRELIMINARIES

2.2 Multilevel Multi-Way Partitioning

To produce a high-quality solution for large hypergraphs in a small amount of runtime, the multilevel partitioning adopts a bottom-up hierarchical approach based on recursive clustering; hMetis is one of the earliest and best multilevel hypergraph partitioning algorithms [8]. The multilevel scheme consists of three phases: coarsening (clustering), initial partitioning, and uncoarsening (disclustering) & refinement, as illustrated in Fig. 3. The initial bipartition is simply a random bipartition. The refinement on the uncoarsening hypergraphs is done by the classical Fiduccia and Mattheyses heuristic for bipartitioning on hypergraphs [9].

Fig. 3. The three phases of hMetis [8]: coarsening, initial partitioning, uncoarsening phases

..........................................................

3. GENERIC ILP FORMULATION FOR 3D IC PARTITIONING

3.2 Hypergraph Modeling

The input design is modeled as a hypergraph, G = (V, E). A vertex in V represents either an I/O terminal or a logic block, while a hyperedge in E denotes a net connecting two or more vertices. An l-layer 3D IC can be achieved by a multi-way partitioning on the input hypergraph. The TSV usage is counted by the number of TSVs used, including both TSV throughs and TSV IOs. The footprint is contributed by the largest area over l layers, so the minimum footprint can be achieved by minimizing the largest area or by balancing the area of each layer in the 3D IC.

3.3 ILP Formulation

Table 1 lists the notations used for ILP formulation and the basic constraints. Based on Table 1, the ?-bounded area limits the footprint. Therefore, the objective function only counts the number of TSVs used. The TSV usage can be given by
?ei ? E ?p = 1…l yi,p, (1)

..................................

.Table 1. Notations used in our generic ILP formulation.

where yi,p is a 0-1 variable computed by the contribution from a q-pin net ei = {vi1,vi2, . . . , viq} ? E to cut p, and the computation can be fulfilled by applying logical operations as follows,
yi,p = [(xi1,1 OR xi1,2 OR . . . OR xi1,p-1) OR
(xi2,1 OR xi2,2 OR . . . OR xi2,p-1) OR . . . OR
(xiq,1 OR xiq,2 OR . . . OR xiq,p-1)] AND
[(xi1,p OR xi1,p+1 OR . . . OR xi1,1) OR
(xi2,p OR xi2,p+1 OR . . . OR xi2,1)) OR . . . OR
(xiq,p OR xiq,p+1 OR . . . OR xiq,1)], 1 ? p ? l. (2)

Eq. (2) means yi,p = 1 if some logic blocks of net ei are located below cut p and some are above. Moreover, Table 2 details how to convert logical expressions [10], e.g., logical AND and logical OR, into mathematical constraints. Therefore, combining Tables 1 and 2 together allows us to successfully formulate the 3D IC partitioning problem as the following ILP:

4. AN EXTENSION TO MSV DESIGN

Table 3. Notations used in our extended ILP formulation for MSV design.

Hypergraph
Liu A gradient method on the initial partition of Fiduccia Mattheyes algorithm p6.pdf

Hypergraph
LU Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits p16.pdf

Hypergraph
LuoYYY Placement and Design Planning for 3D Integrated Circuits okokok p184.pdf

Hypergraph

Mak A fast hypergraph min-cut algorithm for circuit partitioning p11

Hypergraph

Manikandan Unimodular Hypergraph based clustering approaches for VLSI Circuit Partitioning p4

Hypergraph
Minz, Jacob; Wong, Eric and Lim, Sung Kyu: Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package p8 2005 Electronic Components and Technology Conference .............................. 3
Jacob Minz, Eric Wong, and Sung Kyu Lim
School of Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA 30332, USA
fjrminz, ewong, limskg@ece.gatech.edu

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Abstract

3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this article, we present the first physical layout algorithm for 3D SOP that performs thermal-aware 3D placement and crosstalkaware 3D global routing. Existing approaches consider thermal distribution and crosstalk issues as an afterthought, which may require expensive cooling scheme and additional routing layers. Our goal is to overcome this problem with our thermal and crosstalk-aware 3D layout tools. The traditional design objectives such as performance, area, wirelength, and via costs are considered simultaneously to ensure high quality results. Related experimental results demonstrate the effectiveness of our approach.

................................

4. Crosstalk-Aware SOP Global Routing Algorithm

B. Coarse Pin Distribution

................................

During our coarse pin distribution step, we superimpose all placement layers onto a single 2D layer with m￡ n grid and perform pin distribution so that each pin is assigned to one of the slots. We extend the mincut-based global placement algorithm [15] for coarse pin distribution. In [15], hypergraph nodes are partitioned into m ￡ n grid while minimizing the number of inter-partition connections (= cutsize) as well as their estimated wirelength. In our new heuristic algorithm, our cost function is based on (i) how far the new pin location is from the initial location, (ii) how evenly distributed the pins are, (iii) cutsize and wirelength, and (iv) how evenly distributed the inter-partition connections are. More specifically, we construct the initial m ￡ n placement according to the initial pin location. We then compute the move gain for each pin so that it represents how much the cost is improved if moved to another partition. We then perform a sequence of pin moves based on the gain until the quality of the solution is not improved.

Hypergraph
OBENAUS, STEFAN THOMAS and SZYMANSKI, TED H.: Gravity: Fast Placement for 3-D VLSI, ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003, Pages 298–315., p18...............................7
Authors’ addresses: S. T. Obenaus, 605-3460 Peel Street, Montreal, Quebec, H3A 2M1 Canada;
email: obenaus@obenaus.org; T. H. Szymanski, Department of Electrical and Computer Engineering,
McMaster University, 1280 Main Street West, Hamilton, Ontario, Canada L8S 4K1; email:
teds@ece.eng.mcmaster.ca.

rectilinear tree

Steiner tree

rectilinear Steiner trees

orthogonal Steiner trees

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

placement

3. THE MODEL

3.1 2-D Model

.........................

A circuit to be placed is abstracted into a hypergraph G(V, E). The circuit elements form the set V of nodes of the hypergraph, and the circuit nets form the set of hyperedges E that are subsets of V.

======================================

Definition 2. 2-D Placement Problem
Given a hypergraph G(V, E), find a reversible function f : V ! f1, : : : , n1g￡ f1, : : : , n2g, such that
P
e2E
jS(e, f )j is minimized.

Definition 1. Rectilinear Steiner Tree
A rectilinear Steiner tree S(V, f ) is the shortest tree that connects all nodes v 2 V at positions f (v) using only orthogonal horizontal and vertical segments. Its length is jS(V, f )j.

======================================

3.2 3-D Model

The three dimensional model is a natural extension of the 2-D model:
Definition 3. 3-D Placement Problem
Given a hypergraph G(V, E), find a reversible function f : V ! f1, : : : , n1g￡ f1, : : : , n2g ￡f1, : : : , n3g such that
P
e2E
jS(e, f )j is minimized.
This definition also describes the model used by Ohmura [1998].

======================================

4. ALGORITHM

Input: Default
G(V, E) hypergraph
(m1,m2,m3) gridsize
I number of iterations
K number of final
placements 25
r rescaling interval 10
Step Action Section
1: Perform random initial placement. (4.1)
2: For i D 1 to I
3: Compute force based iteration. (4.2)
4: if imodbI=Kc D 0
5: Compute a final placement. (4.4)
6: if imodr D 0
7: Perform bucket rescaling. (4.3)
Output best computed final placement.
Fig. 1. Gravity placement algorithm.

4.1 Random Initial Placement

Initially all circuit nodes are assigned a random initial position with a uniform distribution over the unit cube. Nets, that is, hyperedges, connecting the nodes are ignored. Circuit elements may overlap. In fact, we will tolerate node overlap until the final placement step (see Section 4.4). This is one of the most distinctive features of our algorithm and allows for very fast iterations.

4.2 Force-Based Iteration

In the force-based iteration, each node n’s new position x0n D (x0 n1, x0 n2, x0 n3) is the weighted average of its own position, and the positions of its neighbors.

x0
n
D
xn C
X
e2En
we
"?
X
n02e
xn0
!
? xn
#
1 C
X
e2En
we
?
jej ? 1
￠ (1)
where
En D set of hyperedges incident to node n,
we D 2
jej(jej ? 1)
D weight of edge e.

======================================

5. RESULTS

5.3 Recursive Partitioning Placement using Grid Splitting

As our partitioner, we chose the hMetis hypergraph partitioner developed by Karypis et al. [1997]. To our knowledge, this partitioner is currently the best of the published near-linear-run-time partitioners. Although we use recursive two-way partitioning along each axis in 3-D, we could easily implement 3-D quadrisection with a few modifications to the hMetis library interface. Restrictions in the current hMetis library interface made it necessary to compute a recursive, balanced (k C l)-way partitioning to achieve a k:l split as is sometimes necessary in step 12 of the algorithm in Figure 6 when an odd number of rows, columns, or layers needs to be split. While recursive multi-way partitioning increases run-time and memory requirement, it does not affect the quality of the cut (Karypis, personal communication). According to Karypis, the hMetis interface could easily be adapted to allow explicit k:l cuts.

Hypergraph

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem2 p7.pdf

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem3 p7.pdf

Ouyang Multilevel cooperative search for the circuit hypergraph partitioning problem p7.pdf

OuyangZZZ Multilevel cooperative search for the circuit hypergraph partitioning problem p7.pdf

Hypergraph
Papa, David A. and Markov, Igor L.: Hypergraph Partitioning and Clustering 2003 p38 ........................... 9

Hypergraph

k-way hypergraph

dual hypergraph

coarser hypergraph

coarsened hypergraphs

multilevel hypergraph

clustered hypergraph

circuit hypergraphs

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

1 Introduction

..............................

Logic Circuits.

Logic circuits are composed of gates (or standard cells) that perform logical operations and connected by metal wires. The same electrical signal may propagate from one gate to several other gates ? such a connection is called a net, and can be conveniently represented by a hyperedge. The hypergraph corresponding to a logic circuit directly maps gates to vertices and nets to hyperedges. The dual of this hypergraph is sometimes used as well. In the dual hypergraph, vertices correspond to nets, and hyperedges correspond to gates. An example of a logic circuit and corresponding hypergraph are given in Figure 2.

Figure 2: An example of a logic circuit and the corresponding hypergraph.

2 Motivation and Applications

............................

2.2 Integrated Circuit Design

VLSI circuit design has long provided driving applications and ideas for hypergraph partitioning heuristics. For example, the methods of Kernighan-Lin [46] and Fiduccia-Mattheyses [27] form the basis of today's move-based approaches. The method of Goldberg-Burstein [31] presaged the multilevel approaches recently popularized in the parallel simulation [29, 36, 42] and VLSI [9, 41, 10] communities. As noted in [6], applications in VLSI design include test, simulation and emulation; design of systems with multiple eld-programmable devices; technology migration and repackaging; and top-down oorplanning and placement.

Depending on the specic VLSI design application, a partitioning instance may have directed or undirected hyperedges, weighted or unweighted vertices, etc. However, in all contexts the instance represents at the transistor-level, gate-level, cell-level, block-level, chip-level, 4 or behavioral description module level ? a human-designed system. Such instances are highly non-random. Hence, the current practice remains to evaluate new algorithmic ideas against suites of human-designed benchmark instances. In the VLSI partitioning community, performance of algorithms is typically evaluated on the ISPD 1998 benchmarks released by IBM. Alpert [4] noted that previous circuits did not reect the complexity of modern partitioning instances, particularly in VLSI physical design; this motivated the release of eighteen larger benchmarks produced from internal designs at IBM [3].

Salient features of benchmark (real-world) circuit hypergraphs include:
 size: number of vertices can be in the millions (instances of all sizes are equally important),
 sparsity: average vertex degrees are typically between 3 and 5 for device-, gate-, and cell-level instances; higher average vertex degrees occur in block-level design,
 number of hyperedges (nets) typically between 0.8x and 1.5x of the number of vertices (each module typically has only one or two outputs, each of which represents the source of a new signal net),
 average net sizes are typically between 3 to 5,
 a small number of very large nets (e.g., clock, reset, test) connect hundreds or thousands of vertices.

Partitioning heuristics must be highly efcient in order to be useful in VLSI design.1 Because of this and also because of their exibility in addressing variant objective functions, fast and high-quality iterative move-based partitioners using the approach of Fiduccia-Mattheyses [27] have dominated recent practice.

The primary use of partitioning heuristics in VLSI design is that of top-down recursive min-cut bisection placement. In this placement framework, a region of a chip is divided geometrically, and the logic inside that region is partitioned topologically. Each of these pieces are then recursively divided until the regions are so small that an optimal end-case placer can solve the problem in a reasonable amount of time.

4 Summary of Techniques and Their Scale Dependence

The basic technique common to all VLSI partitioning applications is the Fiduccia-Mattheyses (FM) algorithm [27], which applies linear-time passes to iteratively improve a given partitionment by moving every vertex exactly once. A prevalent extension of this algorithm is the Multilevel FM (MLFM) algorithm, which improves both solution quality and runtime of partitioning large hypergraphs by clustering tightly connected components and partitioning the resulting smaller hypergraph. However, for sufciently small hypergraphs, ?at? FM can produce optimal solutions faster than MLFM, indicating that different techniques should be applied at different scales.

4.4 Multilevel Fiduccia-Mattheyses Framework

5 The Fiduccia-Mattheyses Heuristic

6 Multilevel Fiduccia-Mattheyses Partitioning Framework

7 Available Software and Benchmarks

There are two common, freely-available academic tools for performing hypergraph partitioning. MLPart [53] is an open source C++ implementation of MLFM hypergraph partitioning geared toward circuit hypergraphs and partitioning based placement. hMETIS [52] is the hypergraph version of METIS, a multilevel graph partitioning algorithm implemented in C. hMETIS is distributed freely for academic use in the form of a precompiled library and executables.

7.3 Integrated Circuit Benchmarks from IBM

A set of standard benchmarks derived from VLSI circuits at IBM were presented in ISPD in 1998 [3]. These instances range from 12506 vertices in IBM01 to 210341 vertices in IBM18. Additionally, partitioning in the context of VLSI placement results in hypergraphs with xed vertices. Benchmark hypergraphs with xed vertices were released at ISPD in 1999 [8]. Techniques for evaluating partitioning heuristics and experiments using these benchmarks were given in [17]. Examples of such comparisons between hMETIS and MLPart are found in [16].

hMETIS: http://www-users.cs.umn.edu/?karypis/metis/hmetis/.
MLPart: http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Partitioning/MLPart/

C. J. Alpert and A. B. Kahng, ?Recent Directions in Netlist Partitioning: A Survey,? Integration, 19, 1995, pp. 1-81.

S. Dutt and W. Deng ?VLSI Circuit Partitioning by Cluster-removal Using Iterative Improvement Techniques,? ICCAD, 1996, pp. 194-200.

L. Hagen and A. B. Kahng, ?A New Approach to Effective Circuit Clustering,? ICCAD, 1992, pp. 422-427.

B. Krishnamurthy, ?An Improved Min-cut Algorithm for Partitioning VLSI Net-works,? IEEE Trans. on Comp., vol. C-33, May 1984, pp. 438-446.

Hypergraph

Pavlidis Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits okokok p366.pdf

Pavlidis Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits p18.pdf

Hypergraph
Pavlidis Physical design issues in 3d integrated technologies p21.pdf

Hypergraph

Prathyush Multi-level sequential circuit partitioning for test vector generation for low power test in VLSI p8

Edge-coloring Hypergraph

edge-coloring hypergraphs
Recski, Andras and Szeszler, David: 3-dimensional Routing, Aug 2008. p8.

Andr′as Recski
Department of Computer Science and
Information Theory
Budapest University of Technology and
Economics
H-1521 Budapest, Hungary
recski@cs.bme.hu

D′avid Szeszl′er?
Department of Computer Science and
Information Theory
Budapest University of Technology and
Economics
H-1521 Budapest, Hungary
szeszler@cs.bme.hu

conflict graph

shuffle-exchange graph

Steiner-tree

vertex disjoint Steiner-tree

pairwise vertex-disjoint Steiner-tree

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

In Theorem 5 and Corollary 6 we only considered SALRP instances where each net is a terminal pair. However, allowing multiterminal nets is a crucial point in VLSI design. If we wanted to apply the proof method of Theorem 5 for the multiterminal case in a straightforward way, we would come across the problem of edge-coloring hypergraphs, where an analogue of Shannon’s theorem does not exist. However, if we break up each t-terminal net into t ? 1 terminal pairs then the construction of Theorem 5 works with the only difference being that the maximum degree in the corresponding conflict graph, and thus the height of the obtained routing is doubled.

Hypergraph

Sawicki, Sandro et al: 3D-Via Driven Partitioning for 3D VLSI Integrated Circuits CLEI ELECTRONIC JOURNAL, VOLUME 13, NUMBER 3, PAPER 1, DECEMBER 2010 p11 .........................

Sawicki 3D-Via Driven Partitioning for 3D VLSI Integrated Circuits p11

1, UFRGS – Universidade Federal do Rio Grande do Sul
PPGC/PGMicro – Instituto de Informática
Porto Alegre, RS, Brasil
2, UNIJUI – Universidade Regional do Noroeste do Estado do Rio Grande do Sul
DETEC – Departamento de Tecnologia
Ijui, Santa Rosa, RS, Brasil
{sawicki, wilke, johann, reis}@inf.ufrgs.br

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

Abstract.

A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. However, 3D-vias can impose significant obstacles and constraints to the 3D placement problem. Most of the existing placement algorithms completely ignore this fact, but they do optimize the number of vias using a min-cut partitioning applied to a generic graph partitioning problem. This work proposes a new approach for I/O pads and cells partitioning addressing 3D-vias reduction and its impact on the 3D circuit design. The approach presents two distinct strategies: the first one is based on circuit structure analyses and the second one reducing the number of connections between non-adjacent tiers. The strategies outperformed a state-of-the-art hypergraph partitioner, hMetis [8] in the number of 3D-vias 19%, 17%, 12% and 16% using two, three, four and five tiers.

===========================

1 Introduction

.............................

The number of 3D-vias required in a design is determined by the tier assignment of each cell, which is performed during the cell partitioning. The cell partitioning is usually performed by hypergraph partitioning tools (since it is straightforward to map a netlist into a hypergraph) such as hMetis [8] as done in [2]. On the other hand, hypergraph tools do not understand the distribution of partitions in the space (in 3D circuits they are distributed along in a single dimension) and fail to provide optimal results. It is important to understand that the amount of resources used is proportional to the vertical distance of the tiers; in fact, considering that the path from a tier to an adjacent involves regular vias going through all metal layers plus one 3D-via, it is clear that any vertical connection larger than adjacency might be too expensive in terms of routing resources and delay.

2 Problem Formulation

3 Proposed Algorithm Based on Circuit Structure

4 Reducing Non-Adjacent 3D-Vias

5 Experimental Results

===========================

6 Conclusions

This paper presented a new approach for I/O pads and cells partitioning targeting 3D-vias reduction. The methodology was based on two distinct strategies: circuit structure analyses and the number of connections between non-adjacent tiers. In the first strategy, we proposed that the I/O partitioning and placement is done upfront, while 3D placement will start from fixed I/O pins. In the paper, we showed empirically that doing the partitioning of I/O together with the cells leads to unbalanced number of pins, which invalidates the method. Our method is based on the idea of keeping the pins with logic proximity together in the same tier. In the second strategy the method demonstrates that hypergraph partitioners are not well suited for cell and I/O partitioning into 3D circuit because they do not handle long connections properly, affecting the total 3D-Via count. We demonstrated that our heuristic was able to improve the 3D-Via count by considering the positions of each tier within the 3D chip while partitioning the cells among the tiers. Finally, we highlight that our heuristic was able to perform partitioning while keeping area and I/O pin count balanced for all tiers.

Hypergraph

Schiffner A Multilevel Eigenvalue Based Circuit Partitioning Technique p5

Hypergraph
Schloegel Parallel Multilevel Algorithms for Multi-constraint Graph Partitioning p15.pdf

Hypergraph / directed hypergraph

Sheibanyrad A. et al.: 3D Integration for NoC-based SoC Architectures, Integrated Circuits and Systems, Springer Science+Business Media, LLC 2011, Chapter 8 Design of Application-Specific 3D Networks-on-Chip Architectures (by Yan, Shan and Lin, Bill) .......... page 25 .............................
S. Yan (?)
University of California, San Diego, CA, USA
e-mail: shyan@ucsd.edu

Routing Cost Graph

router cost graph

communication demand graph

connectivity graphs

hypergraph

channel dependency graph

extended channel dependency graph

Steiner tree

delay-oriented Steiner tree

multicast tree

optimum multicast tree

Multicast Routing Tree

directed minimum spanning tree

rooted directed minimum spanning tree

rooted directed spanning tree

minimum directed spanning tree

Minimum Directed Spanning Tree

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

8.4 Problem Description and Formulation

8.4.1 Problem Description

The input to our 3D-NoC synthesis problem is a communication demand graph (CDG), defined as follows:

Definition 1 A communication demand graph (CDG) is an annotated directed hypergraph H( V, E, π, λ), where each node vi ∈ V corresponds to a module, and each directed hyperedge ek = s → D ∈ E represents a traffic flow from source s ∈ V to one or more destinations D = {d1, d2,…}, D ? V. The position of each node vi is given by π( vi) = ( xi, yi). The data rate requirement for each communication flow ek is given by λ( ek ).

Hypergraph
Siozios, Kostas and Soudris, Dimitrios: A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs 2008 p36...........13
1 VLSI Design and Testing Center, Dept. of Electrical and Computer Engineering, Democritus University of
Thrace, Vas. Sofias 12, 67100, Xanthi, Greece, ksiop@ee.duth.gr
2 Dept. of Electrical & Computer Engineering, National Technical University of Athens, 9 Heroon
Polytechneiou, Zographou Campus, 157 80 Athens, Greece, dsoudris@microlab.ntua.gr
5W1H

Why hypergraph:

When hypergraph

Who hypergraph

What hypergraph

How hypergraph

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

1 INTRODUCTION

...................................

The rest of the paper is organized as follows. In Section 2 we describe the key features of the employed 3D FPGA for our exploration/evaluation procedure, while in Section 3 we describe the application encoding into a hypergraph form. The proposed algorithms for the P&R step are discussed in detail in Section 4, whereas Section 5 evaluates the power-aware algorithm against to alternative application implementation. Finally, conclusions are summarized in Section 6.

2 TARGET 3D RECONFIGURABLE ARCHITECTURE

====================================

3 APPLICATION ENCODING

In order to handle applications with our proposed P&R algorithm, they have to be appropriately encoded into a directed hypergraph form, denoted as , . In this form, each vertex of the hyergraph represents the application’s logic functionality implemented onto a logic block, while the directed hyperedge , corresponds to the communication link between the logic blocks and . In order to encode the application’s functionality, apart from the hypergraph construction, we associate a number of weights to hyperedges and vertexs.

More specifically, for each of the hyperedge ????,??, the weights define the communication bandwidth from vertex ???? to ???? (i.e. the number of wires between logic blocks ???? and ????), the power consumption, the timing criticality, as well as the electrical characteristics (in order to classify different wirelengths, TSVs, wires placed on the each layer, etc). Similarly, the weights of vertex ???? represent the area occupied by each block, its power consumption, the switched capacitance criticality, as well as its delay.

Regarding the values of these weights are calculated, as follows:
Communication bandwidth: The communication bandwidth for a hyperedge , equals to the number of wires that connects the logic blocks encoded with vertexs and . In case this communication affects vertexs assigned to different layers, then this is equal to the
edge-cut (number of TSVs) for this link.
Related to power consumption: We employ the models proposed in [2], appropriately extended in order to be aware about the extra hardware of the 3D FPGA (i.e. 3D SBs).
Related to delay: We employ the Elmore delay model [12].
Area: We use an area estimation model proposed in [20].

4 POWER-AWARE PLACEMENT AND ROUTING ALGORITHM

............................................

Figure 1 depicts the steps of application mapping onto a 3D FPGA. Initially, the application is appropriately encoded using a directed hypergraph form , (Figure 1(a)). The first task of the P&R algorithm deals with application partitioning to a number of sections (Figure 1(b)), each of which corresponds to the portion of the application’s functionality realized in each of the 3D device layers. Then, the placement algorithm assigns the application’s functionality of each layer to the available logic blocks (Figure 1(c)), while the routing algorithm forms the appropriate connections among them (Figure 1(d)).

Figure 1. Tasks for application implementation onto 3D FPGAs: (a) application hypergraph, (b) application partitioning to device layers, (c) application placement and (d) application routing

==================================

4.1 Algorithm for Power-Aware Partitioning and Layer Assignment

....................................

In order to quantify each of the derived solutions, we employ the cost function depicted in Equation (2). As our algorithm can be used for architecture-level exploration, rather than providing only an application partitioning, we calculate the Pareto-based space of alternative application partitions. These solutions balance the area occupied by active hardware resources, the number of interlayer connections and the variation of power consumption (i.e. power sources) among layers.

where denotes the variation of power sources over the 3D FPGA, the is equal to the total amount of hyperedge-cut, while the denotes the area balance among the device layers. The employed factors and provide higher flexibility to the cost function, as they of our proposed partitioning algorithm provides, can be used to tune the algorithm for further optimizing the partitioning result. Finally, we have to mention that the cost function, as well as the criticalities of the hypergraph (i.e. weights of vertexes and edges) are updated after each iteration, while the partitioning task stops when both the distribution of switched capacitance and the timing constraints are met.
N. Selvakkumaran and G. Karypis, “Multiobjective Hypergraph-Partitioning Algorithms for Cut and Maximum Subdomain-Degree Minimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2006), Vol. 25, No. 3, pp. 504-517.

Hypergraph

SzeszlerZZZ Combinatorial Algorithms in VLSI Routing p78.pdf

Circuit Partitioning

In a typical partitioning problem we are given a hypergraph H = (V;E); a weight function w : V 7! N on the set of its vertices; a cost function c : E 7! N on the set of its edges; the desired number of the partition classes r 2 N; and the minimal and maximal partition class weights b(i) 2 N and B(i) 2 N; i = 1; : : : ; r. We are looking for a partition Sr i=1 Vi of the set V for which b(i)  w(Vi)  B(i) holds for all i = 1; : : : ; r and the total cost of all hyperedges that intersect more than one partition class is minimum. (The problem is NP-hard even if the value of r is xed to r = 2 and we restrict ourselves to graphs instead of hypergraphs [8].)
?

Hypergraph

Tabrizi, Aysa Fakheri: Force-Directed Partitioning Technique for 3D IC Master Thesis, January, 2013 p109 ...................

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

2.2.1 Terminology

.........................

Connectivity information of cells can be represented in different ways such as hypergraph/graph representation, netlist representation and connectivity matrix [7]. 8 Each one of the representations is described in further detail here.

Hypergraph/Graph representation

A circuit can be represented by a graph G(V;E) where V is the set of vertices or nodes that includes the cells and set E represents the set of edges that are the connection between cells, i.e. nets [19].

In the graph representation each edge connects to only two cells. Since in practical circuit design, there are lots of nets that are connected to more than two cells, a graph representation is not an adequate representation of a circuit and hypergraph representation is mostly used. A hypergraph is generalization of graph in which one edge can connect two or more than two vertices. The nets that connect more than two cells are called hyperedges [19].

Figure 2.1: An example of a simple circuit schematic

============================================

In Figure 2.2, a hypergraph representation of the circuit with five cells, shown in Figure 2.1, and its corresponding graph representation are shown. In this figure vertices a to e represent the logic elements a to e shown in Figure 2.1 and the the edges represent the connection between logic elements. In this example, in converting a hypergraph to a graph, all hyperedges are converted to a set of edges that connect each pair of the nodes connected to a given hyperedge.

Figure 2.2: Hypergraph and graph representation of the circuit shown in Figure 2.1

2.2.2 2D Partitioning Problem

................................

With the increase in the number of circuit element, partitioning of 2D circuits is now performed by multi-level hypergraph partitioning algorithms such as hMetis [27, 17]. These multi-level algorithms on their own are based on iterative improvement techniques such as FM [26].

2.2.4 Fiduccia-Mattheyses (FM) Algorithm

............................................................

Unlike KL that swaps a pair of cells between two partitions, FM moves cells independently which makes the algorithm more flexible in solving unequal partition sizes. Another advantage of FM over KL is that hypergraphs can be used in FM. While KL minimizes the number of edges, FM minimizes the number of nets cut. That means if one net is connected to more than two cells and the net is cut, KL might count the cut more than once, while FM counts that only once which is practical. Figure 2.7 shows the shortcoming of partitioning methods using graph representation vs. hypergraph representation. Another advantage of FM is that it is applicable on graphs with different node areas.

Figure 2.7: Difference between the calculation of cuts in a graph, [a], and hypergraph, [b], representation of a circuit

2.2.5 Multilevel Partitioning

As circuit sizes have been growing exponentially, new techniques were needed to deal with this increase. In multilevel partitioning methods first the size of a graph is reduced using clustering techniques in the coarsening phase. Then, the coarsened circuit is partitioned using partitioning techniques in the initial partitioning phase. The last step of the algorithm is uncoarsening and refinement phase [27, 16, 17]. In Figure 2.22 the three phases of multilevel hypergraph partitioning are shown. Each one of these phases is described in the following.

Coarsening phase

During this phase the smaller hypergraphs are constructed by clustering groups of vertices with common hyperedges. The clustered vertices form a single vertices and the hyperedges inside a cluster are removed from the reduced hypergraph. In Figure 2.22 two levels of coarsening is shown. In this figure the original hypergraph consists of 18 vertices and the number of vertices are reduced to 12 after one level coarsening and it is reduced to 7 vertices after two level coarsening. There are different methods to cluster the vertices such as Edge Coarsening (EC), Hyperedge Coarsening (HEC), Modified Hyperedge Coarsening (MHEC) [27, 16, 17], best choice [28] and Netcluster [29].

Initial partitioning phase

At this phase, the coarsest hypergraph is partitioned such that it has the smallest number of net cut, and the sizes of the partitions are almost equal. FM algorithm [26] is mainly used to perform this step. The coarsest hypergraph typically contains 75-200 nodes for which the FM algorithm performance is nearly optimal.

Uncoarsening and refinement phase

In this phase at each level the coarse hypergraph is uncoarsened to one level finer hypergraph and every sub-cluster is assigned to the partition to which its parent cluster was located and a refinement algorithm is used to reduce the number of net cuts by moving the vertices between the partitions while maintaining the balance criteria. The most common algorithms that is used for the refinement is FM algorithm. Uncoarsening and refinement continue until the original graph is partitioned.

Chapter 3 Constructive 3D Partitioning

3.3 Proposed Constructive 3D Partitioning

...............................................

Among the different partitioning methods, multilevel hypergraph partitioning is selected to perform initial partitioning. hMetis tool is used to perform this task, which provides high quality 2D partitions and renders an efficient run time of the algorithm. Another technique used in the proposed algorithm is the linear ordering, which is mainly used in floor planning stage of the physical design. The algorithm arranges the previously generated partitions in a single row in a way that minimizes the length of connections and consequently the number of net cuts. Ordering the initial partitions rather than stacking them randomly results in locating the partitions that have more connections close to each other. This consequently reduces the length of connections and the number of long connections and gives the semi optimal combination of the partitions to form the tiers.

...................................

The inputs of the algorithm shown in Figure 3.3 are the netlist and the desired number of tiers, m. The output of the algorithm is the 3D partitioned netlist i.e. the tiers and their order and the number of TSVs needed. First, the netlist is divided into n partitions using multilevel hypergraph partitioning technique, where n is a multiple of m. Then the generated partitions are stacked using a linear ordering heuristic. Every n=m successive layers are merged and form the 3D tiers. In Section 3.3.1 the initial partitioning step is described. The linear ordering stage and merging the layers are described in Sections 3.3.2 and 3.3.3 respectively.

Figure 3.3: Proposed constructive algorithm flowchart

3.3.1 Multilevel Partitioning

In the first phase of the algorithm, the netlist is divided into several partitions using the method of multilevel hypergraph partitioning. Normally, the number of partitions is several times larger than the desired number of tiers. hMetis tool is used to form these partitions. The partitions are produced in a way that they have minimum numbers of connections with each other. These partitions provide a good initial solution in a reasonable time; however, this solution is not tailor made for 3D ICs. This algorithm divides netlist into partitions in a way that they have minimum interconnections with each other, but doesn’t consider the number of times that a net is cut when the partitions are stacked.

Chapter 4 Force Based Simulated Annealing
A multigraph is a graph that can have more than one edge between a pair of nodes. A multigraph can be used to represent the nets with different weights. The weight, w(e), for an edge, e 2 E, represents the weight of the corresponding edge. Finally, in a circuit, each logic element has a certain area. In this thesis, area(v), for each v 2 V represents the area of each cell.

Hypergraph

THIYAGARAJAN, M and MANIKANDAN, R.: HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS p5 April 2011

THIYAGARAJAN? HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS p5

Vertical Constraint Graph (VCB)

spanning tree
hypergraph

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

ABSTRACT

VLSI Cell partitioning is considered as Hypergraph model, which can be a treated a randomized algorithm through the markov chain. This approach helps to give a probabilistic algorithm through transition probability matrices of a markov chain for VLSI partitioning. In the second model SAT problem situation is used to model FPGA Layout. As almost all problems posed in VLSI design and analysis are NP Complete, any attempt to solve them is to identify some reduction tool to NP-Complete problems. One such reduction is attempted through SAT Problem.

INTRODUCTION

The Main problem of partitioning in VLSI Design and other related domain of study can be posed as getting sub domain of equal size of the vertices in a given hypergraph. A Variety of knowledge based algorithms have been developed which give different cost-quality tradeoffs. The edges at consecutive cells dominate each other to have incident one, two or more creating cluster like situation which can be modeled as a hypergraph. The contribution of links to specific node is relative important and thus demands for probabilistic algorithms to develop on stochastic function. Iterative refinement algorithms have been developed by Kernighan-Lin (KL) and Fiduccia- Mattheyses [1], [2], [3].

Earlier Researchers have placed the problem in searching for Max-Min cut on graphical representation of the design. Here, We give hyper graph concepts explained through discrete time and space sequence of random variables forming Markov chain. The classification of nodes studied through an analysis on variety of classified states of the Markov chain fitted to the situation

Section I:

1.1. Problem specification

Formally, the k -way min-cut partitioning problem can be stated as follows. Let a circuit C be represented by a hypergraph or netlist G = (V,E), where V is the set of nodes that represent the nets of the circuit. Each hyperedge or net connects two or more nodes together; generally the output of a node is connected to the inputs of several other nodes by a net. We will represent a net ni as a set of the nodes that it connects. We denote the number of nodes in V by n the number of hyperedges in E by e, the average number of nets that a node is connected to by qn, the average number of nodes that a net connect by qe, and the average number of neighbors of a node by d = qn (qe ?1) ? a node u is said to be a neighbor of another node u, if u and u are connected by a common net. A k ? way partitioning of G is a set of subsets { 1, 2,.... k} Pk = V V V of V such that each u ∈V belongs to exactly one Vi. Let r1 and r2 be two numbers between 0 and 1 such that r1 ≤ r2,≤1/ k and r2 ,≥1/ k. Then, an (r1,r2 ) ? balanced k ? partition in which r1 ≤|Vi | n ≤ r2 for each subset Vi of . Pk When k = 2,r1 =1? r2; however, for k ≥ 3 there is no obvious relation between r1 and r2 (except r1 ≤ r2 ). We assume that all nodes have unit size; the balance criterion is easily changed to reflect size constraints on the subset when this is not the case. The cutest of a k ? way partitioning is defined as

Ecut = {n1∈E | ?u ,∈nts.t. u∈Vi ,i ≠ j}

In other words, the cutest Ecut is the set of nets that connect nodes belonging to different subsets of Pk . The cost of size of the cutest of Pk is defined as

cost( ) ( ),where cut

Assume that there are n nodes in the hypergraph G, and that it is being partitioned into {V1,V2}. When partitioning a hypergraph or netlist, the gain of a node is not as apparent as in the case of graph. The FM netlist partitioner user a simple extension of the Kernighan-Lin node gain calculation (used for graph partitioning). For each node u, let I (u) be the set of nets to which u is connected that lie entirely in u's current subset, and E(u) be the set of nets that belong to the cutest and for which u is the only node connected to them in u's partition. Then the gain of u is given by

gain( ) : ( ) ( )

This gain definition of a node is the immediate decrease in the cutest cost if it is moved to the other subset. The partitioning process proceeds by determining the next best node ui to move in the ith step as follows. The “unlocked” note (initially all nodes are unlocked) with the maximum gain in either subset is determined. If the balance criterion on the two subsets can be maintained after moving this node from its current subset to the other one, it is chosen as the node ui . Node ui . is them moved to the other subset and “locked”, and the gain of all its neighbors are updated. The node gain (ui ) is inserted in an ordered set S, and the next best node is moved in a similar fashion such that the balance criterion is satisfied.

1.2. Data and analysis

We can represent this graph as an adjacency list.

Figure 1. The Adjacency list representation of the graph

Figure 2. Adjacency list representation of f

From the adjacency matrix given in fig.3 we get the number of edges for the hypergraph connection different vertices in fig.5. The vertical and horizontal representation on the writing is analyzed through Cross-correlation from the result we find that hypergraph can be converted into ordinary spanning tree of a regular graph.

Step 1: Average of each now is subtracted from every entry d1.
Step 2: Average pf each every column is subtracted from every entry d2..
Step 3: Product is summed the average is taken.
Step 4: We find the cross correlation between this movements.
Row variance = 12.36
Column variance = 14.66
Covariance between row and column entities = 9.38
Correlation between row and column = 0.7.
This shows that the hypergraph method is better than the vertical and horizontal method procedure in wing and cell partitioning. Markov distribution is shown below.

Fig.3 Markov distribution

In fig.3 we have given the probability transition matrix for a design with finite number of nodes, but in VLSI design we have to deal with large scale of nodes. Thus this matrix will be of infinite dimension and the markov-chain is studied through virtual memory systems, where in additional memory locations are treated as virtual memories.

Section 2:

2.1. Boolean SAT based FPGA detailed routing formation [6]

In this approach geometric FPGA routing task is transformed into a Boolean satisfiability (SAT) equation with the property that any assignment of input variables that satisfies the equation specifies a valid rout. The satisfiability equation is then modeled as constraint satisfaction problem, which helps in reducing procedural programming. Satisfying assignment for particular route will result in a valid routing and absence of a satisfying assignment implies that the layout is unroutable.

2.2. FPGA layouts

One of the most commonly used layout models in FPGA applications [see Fig.4(a)]. It consists of two-dimentional array of configurable logic blocks CLBs, connection blocks C blocks and switching blocks S blocks. Each CLB marked L in [Fig. 4(a)] contains the combinational and sequential logic that implements the functionality of a circuit. C and S blocks contain programmable switch form the routing resources. C blocks connect CLB pins to channels via programmable switches. S blocks are surrounded by C blocks and allow signals either pass through.

Fig.4. Island style FPGA model

A net consists of CLB pins that are interconnected with each other can be decomposed into one or more horizontal and/or vertical net segments each of which is an alternating sequence of C and S blocks forming an uninterrupted path. A detailed route of a net is a set of wire segments and routing switch following the topology specified by the global router such that no overlapping among detailed routes of different nets occurs.

The routing capacity of a given FPGA architecture is mainly expressed by three parameters W, Fc, Fs. The channel width is the number of tracks in a vertical or horizontal channel. The C block flexibility Fc is defined to be the number of tracks that each logic pin can connect to. The S block flexibility Fs denotes the number of other tracks that each wire segment entering an S block.

Each wire segment entering this S block can connect to one track on each of the other three sides, hence Fs = 3 [See Fig.4(b)]. Each logic pin can be connected up to any two tracks in the C block, thus Fc = 2 [In Fig.4(c)].

The optimal assignment of tasks to processing is, in almost all practical cases on NPcomplete problem. We must therefore make do with heuristics. These heuristics cannot guarantee that an allocation will be found that permits all tasks to be feasibly scheduled. We must check for feasibility.

These layouts can be considered the congruence classes in translating the NP-complete SAT problem to a polynomial time problem suggested by Hopcroft and Ullman [5]. Usually this problem is reduced to 3-SAT problem and the logic programming shown in fig.5 can be used to explain the situation.

SAT problem [5]

The Boolean expressions are unit from variables where values are Boolean (0, Y), logical operator AND and OR, any operator logical negation and parenthesis to great operators and operands.

A truth assignment of satisfies Boolean expression E assigns either true or false to each of the variables in E. A Boolean expression E is said to satisfiable if there exists atleast one truth assignment T that satisfied E. SAT problem is:

? given a Boolean expression is it satisfiable?

We have used to result the CSAT is NP-complete and in particular 3 SAT is NP complete.
We propose our layout problem as CSAT problem and used the construction of solution to solve our layout problem.

2.3. Data analysis

Here layout problem is considered and claim that work cover problem is SAT [5].

Proof:

The reduction is as follows. Let G with lower limit K be an instance of the independent-set problem. If G has n nodes, let G with upper limit n-K be the instance of the node-cover problem. We construct, evidently this transformation can be accomplished in linear time. No claim that

G has an independent set of size K if and only if G has a node cover of size n-K.

(If) Let N be the set of nodes of G, and let C be the node cover of size n-K. We claim that N-C is an independent set. Suppose not, that is, there is a pair of nodes V and W in N-C that has an edge between them in G. Then since neither V nor W is in C, the edge (U, W) in G is not covered by the alleged node cover C. We have proved by contradiction that N-C is an independent set. Evidently, this set has K nodes, so this direction of the proof is complete.

(Only if) Suppose I is an independent set of C nodes. We claim that N-I is a node cover of with n- K nodes. Again, we proceed by contradiction. If there is some edge (U, W) not covered by N-I, then both V and W are in I, yet are connected by an edge, which contradicts the definition of an independent set.

Layout

Fig.5a. Channel to be routed
Fig.5b. Matrix representation of Channel routing problem

E = (A≠C) Λ (A≠D) Λ (A≠B) Λ (C≠D) Λ (D≠B)
Fig.5c. Exclusively Constraint

Fig.5d. Vertical Constraint Graph (VCB)

V = (A>C) Λ (A>B) Λ (D>C) Λ (D>B)
Fig.5e. Vertical Ordering Constraint R = E Λ V
Fig.5f. Channel routability constraint

Fig.5g. Two feasible solutions

Fig.5. Boolean SAT modeling of channel routing problem
Any track number assignment that makes R = 1 corresponds to a feasible routing solution and completely specifies the net-to-track mapping. Two feasible assignments are shown in Fig.5g.

CONCLUSION

We have given an unified approach to VLSI partitioning problems considered so far over last two decades. A hybrid approach of Max-min algorithm, markov chain and hypergraph will give better result. An alternative method is considered through SAT problem . 3-CNF SAT problem is a convenient problem to reduce to other problems in order to solve them NP-Complete. Another NPComplete problem that is often easy to reduce to other problems is the vertex cover problem. One can use this vertex cover problem to any FPGA layout. Future work in this direction will help us to identify exactly other VLSI Design criteria.

Hypergraph

Thorolfsson, Thorlindur et al: Logic-on-Logic 3D Integration and Placement Sept 2010 p4

Hypergraph

Wu Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques ??okokok

Wu Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques p10.pdf
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 3, JUNE 2003
Yu-Liang Wu, Member, IEEE, Chak-Chung Cheung, David Ihsin Cheng, and Hongbing Fan
Y. L. Wu and C.-C. Cheung are with the Department of Computer Science
and Engineering, The Chinese University of Hong Kong, Hong Kong (e-mail:
ylw@cse.cuhk.edu.hk; cccheung@cse.cuhk.edu.hk).
D. I. Cheng is with Faraday Technology, Milpitas, CA 95035 USA (e-mail:
dcheng@faraday-usa.com).
H. Fan is with the Department of Computer Science, University of Victoria,
Victoria, BC V8W 3P6, Canada (e-mail: hfan@csr.csc.uvic.ca).

Partitioning
I. INTRODUCTION
In particular, Karypis and Kumar [22] propose a partitioner called hMetis-Kway. It first coarsens the hypergraph, then recursively bisects the graph into k parts, followed by uncoarsening the hypergraph with refinement algorithms. More recent research works [23]–[26], in comparison with hMetis-Kway, have shown that the solution by hMetis-Kway is such a high quality that the cut size cannot be further reduced greatly

Hypergraph
Yan SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement p14

Hypergraph

Yang 楊逸翔: 3D-Floorplanning for Via and Wire length Minimization Master Thesis June 2009 p50 ,,,,,,,,,,,,,,,,,,,,,,,,,,, 14

Hypergraph

floorplanning

第二章 相關研究

......................................

2.1 Multilevel k-way Hypergraph Partitioning

hMetis為目前最有效率的partition tool，我們將使用hMetis把modules分配至各層以及區塊。

hMetis主要分為三個步驟，分別為coarsening phase、initial partitioning phase以及uncoarsening and refinement phase如下圖:

.........................................

Coarsening phase:

coarsening phase主要的目的在簡化圖形，結合node使整體node數降低。而結合node的依據有Edge coarsening、Hyperedge coarsening以及first-choice coarsening。

Edge coarsening結合的方式為一次兩個點做結合，結合的依據為與點所連結的點中，哪一對被最多的hyperedge所連接，就將它結合，拜訪的點是由隨機選取的，但結合過的點就不能再做結合。下圖為edge coarsening的例子。

Hyperedge coarsening的結合方式為將所有的hyperedge所連結的點做結合，結合的順序也為hyperedge的權重，若權重相同則以hyperedge所連結的node數較多的優先結合。

第三章 問題定義及檔案格式

3.3 輸入及輸出資訊

由於我們會使用hMetis所以需要將以上的檔案整合為HGR(hyper graph)檔如圖3.3，第一行中的三組數字依序表示為hyper edge的數量、node的數量最後為hgr檔的格式，所以圖3.3這個hyper graph有7個hyper edges以及10個nodes，最後的”11”表示hyper edge及node都有權重。另外還有不加數字表示net與node皆無權重，”1”則表示hyper edge有權重、node的權重皆為1，”10”則表示node有權重，net的權重皆為1。第二至八行為hyper edge的描述，第一個數字為hyper edge的權重，接下來是這個hyper edge包含的nodes，以第二行來說這個hyper edge的權重為2，並包含node 0、8和5。第九行之後為node的權重，依序由node 0到9，也就是說第九行的1319是node 0的權重。

另外在hMetis裡還有一個fix file，fix file的作用在於將node指定partition後的group。如圖3.4第一行的0表示將node 0強制分配在group 0，第五行的1表示將node 4強制分配在group 1，其中-1表示這個node不指定。所以將這個hyper graph做partition並加入這個fix file的話node 0與node 3一定會在group 0，node 4與node 5會在group 1。

第四 章 演算法及流程介紹

4.2分層

這一節會介紹分層這個步驟，首先將測試檔轉為hyper graph，接著輸入至hMetis。在這一個步驟最重要的目的就是將module分層，並且考量cut數以及將各層的面積盡量均等。因為through via的成本很高，並且除了face-to-face的架構外都要花費而外的面積，因此我們希望能夠減少through via的數量。

4.4切割interlayer connection

在這個步驟我們需要將layer跟layer間有連線的net先找出來，然後篩選這些nets，如果net的權重大於W(由使用者定義)則保留，做這個的意義在於我們只要考量權重較重的net，如果將所有的net都納入，那麼會變成過度考量interlayer connection，這會使得繞線長度變差。最後將這些保留nets重建為vertical hyper graph後再由hMetis分成n等份，做這個步驟的用意在於考量層跟層之間的wire length，希望上下層之間有連線關係的modules之間的距離能夠短一點，進而縮短wire length，在切割時我們以min cut為第一考量。以圖4.4為例，都是由點A連線至點B，但a圖的連線距離比b圖長。所以我們透過這個步驟將interlayer連線較多的modules放在同一個block。

基於這些因素在分割完後，雖然是分配成n等份，但實際上已有了L*n個block了。在圖4.5(a)就是先找出所有interlayer connection的net並把它重建成hyper graph，接著將hyper graph partition成4份，圖4.5(b)就是這個hyper graph的最佳解，而就像先前所提到的，此時已將modules分配置12個blocks了，如圖4.5(c)。

Hypergraph
Yeh, Ching-Wei; Cheng, Chung-Kuan and Lin, Ting-Ting Y.: A General Purpose, Multiple-Way Partitioning Algorithm p9.pdf IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 13, NO. 12. DECEMBER 1994

Hypergraph
Zhou, Lili; Wakayama, Cherry and Shi, C.-J. Richard: CASCADE A Standard Super-Cell Design Methodology with Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large Scale Integrated Circuits p11. 2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

The authors are with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195 USA.

(E-mail: {llzhou, wakayama, shi}@ee.washington.edu).

Definition, Terminology, Structures

How it is generated

Uses / what is its use / applications

I. INTRODUCTION

..............................

Research effort has been dedicated to the development of 3D IC design tools. Ababei et al. developed physical tools for 3D FPGA design [10]. Das et al. implemented a 3D standard-cell placement and global routing tool [11]. Optimal placement was based on recursive min-cut partitioning of a circuit represented as a hypergraph. Inter-tier via (3D-via) minimization was sought by min-cut partitioning for tier assignment. During the partitioning phase, the aspect ratio was used to determine the wire-length minimization. Cong et al. proposed thermal-driven 3D floor-planning and routing algorithms [12][13]. Boplen and Sapatnekar presented thermal-driven force-directed standard-cell placement and thermal-via placement based on finite-element analysis [14][15].

Terminology

Literature


Research Plans

Letter4Math4Chip_CNEN.docx

Letter4Math4Chip_EN20150820.docx

Math4Chip_Design_Physical_Routing_Detailed.docx

math4chip_research_plan_abstract.docx

math4chip_research_plan_abstract.pdf

math4chip_research_plan_overall.docx

math4chip_research_plan_overall.pdf

math4chip_research_plan_overall1.pdf

图论与芯片技术研究计划Overall?Research?Objective

这个是我2014年11月份提交给NSF（美国科学基金会）的研究计划摘要

Overall Research Objective

Overview

The ultimate and overall aim of the project, for which the current application is one of the earlier stages – is to establish a comprehensive graph theoretic foundations specifically for the latest advanced VLSI/chips by systemizing and integrating the existing theories and methods and implementing and creating new ones.

Research Methods

A systematic and logic approach will be adopted towards the applications of graph theory in VLSI domain. Thus sporadic graph theoretical techniques and algorithms scattered here and there will be collected, categorized, analyzed, and theoretized. In most cases theoretical/logical reasoning and mathematical prove are the two main tools used to conduct the research.

Intellectual Merit

As a result of this project, dozens if not hundreds, of books/paper will be published. They will help the academia and the industry to understand the relationship between graph theory and VLSI more systematically. They are expected to be one of the major graph theoretic reference points for the VLSI industry.

Qualifications Of The Investigator

The PI is a well educated person with solid math skills and VLSI chip industry experiences.

Impacts

Graph theory is one of the mathematical foundation


Graph theory

I decided to study graph theory sometime in 2014, because I wanted to focus on math related to computer chip (VLSI) technology, considered by me the most important technology of our time. And graph theory is among the key math tools in VLSI design. Therefore I have decided then to focus on graph theory and algorithms for VLSI design. In two years I have found out graph theory itself is a huge topic and its applications to VLSI design is wide reaching and there is no way to do research on the full scope. Therefore I have taken pains to figure out for which VLSI technologies to apply which graph theoretic techniques. After many months’ investigations and researches I have decided to concentrate on graph embedding for the next generation of compter chip technologies – not the current silicon based CMOS technologies but the upcoming ones such as quantum circuits, spintronic based FET, superconducting circuits, molecular circuits, bio computing, reverse computing and a dozen others.

Tragically my mother died on March 11, 2016, and this incident has completely altered my life path and after more than a half year’s hesitation, I’ve taken another major decision, that is, to cancel all other studies and leave only graph theory on my research agenda. Therefore since Sept 11, 2016, I have stopped all my efforts in investigating the newest computer chip technologies and what’s left to do is only a bit of study of graph theory, and at the moment and for the foreseeable time it is graph embedding. Yet graph embedding itself is a very large subject and is worth years of painstaking efforts in studies. There are hundreds of embedding techniques and there are many other areas of graph theory which are similar to or related to graph embedding. Still there are questions as to the exact definition and scope of graph embedding. If you’re interested in this subject, we may exchange some views and research results privately, for I am not planning to disclose any of my research achievement.

For my past researches on other subjects please see my writing since 2003 as a PDF file uploaded into this site.

About my Graph Theory Studies

In this part of my website I will record my study history about graph theory, and its applications to integrated circuits design, particularly those forthcoming and promising technologies such as neoral computing, DNA computing etc.

I will report about my research progress with study notes and papers and booklets. I will also list literatures I am reading. I will also tell the world with whom I am communicating about my research results, if there is any.

graph_basic >>>

graph_theory_review.htm a bit summary

graph_studies_books.html - overall graph theory study program and literature index

Graph theory research plans graphresearchplans.html

00graph_intro.docx
00graph_openproblems.docx
graph_actions_operation.docx
graph_coloring.docx
graph_coupling.docx
graph_covering.docx
graph_crossing.docx
graph_features.docx
graph_file_formats.docx
graph_functions.docx
graph_languages.docx
graph_partition_a2j.docx
graph_partition_k2z.docx
graph_tranform.docx
graph_traversal.docx
graph_types1.docx
graph_types2.docx

graph_vlsi/graph_vlsi_types

00chip_math.docx
graph_vlsi/graph_vlsi_types_abstract_levels.docx
graph_vlsi/graph_vlsi_types_models_chip.docx
graph_vlsi/graph_vlsi_types_other_phases.docx
graph_vlsi/graph_vlsi_types_reconfigurable_cdfg.docx
graph_vlsi/graph_vlsi_types_reconfigurable_summary.docx

hypergraph

hypergraph_intro.docx
hypergraph_models_fpga.docx
hypergraph_models_fpga.pdf
hypergraph_models_fpga_def.docx
hypergraph_models_fpga_def_original.docx
hypergraph_models_fpga_original.docx
hypergraph_models_fpga_ref.docx
hypergraph_types.docx

tree

tree_types.docx

tsp

tsp1.docx

graph4ic_research

graph4Chip_Design_Physical_Routing_Detailed.docx
graph4chip_research_plan_abstract.docx
graph4chip_research_plan_abstract.pdf
graph4chip_research_plan_overall.docx
graph4chip_research_plan_overall.pdf
graph4chip_research_plan_overall1.pdf

graph_embedding >>>

under preparation

letters2math >>>

My letters to graph theorists

>>> graph_vlsi/graph_vlsi_types

  • 000Steiner_graph.htm
  • 000constraint_graph.htm
  • 000graph_general.htm
  • 000grid_lattice_graph.htm
  • 000routing_graph.htm
  • 000sample.htm
  • 000spanning_graph.htm
  • 4completion_graph.htm
  • Cayley_star_graph.htm
  • Tanner_graph.htm
  • adjacency_graph.htm
  • architecture_graph.htm
  • bipartite_graph.htm
  • carry_generation_graph.htm
  • cell_graph.htm
  • channel_graphs.htm
  • circuit_graph.htm
  • coarse_graph.htm
  • communication_graph.htm
  • conflict_graph.htm
  • conflict_net_graph.htm
  • connection_graph.htm
  • connectivity_graph.htm
  • core_graph.htm
  • cost_graph.htm
  • demand_ggraph.htm
  • dense_graph.htm
  • dependency_graph.htm
  • directed_acyclic_graph.htm
  • dual_graph.htm
  • floorplan_graph.htm
  • flow_graph.htm
  • full_adder_graph.htm
  • graph_embedding.htm
  • graph_vlsi/graph_vlsi_types.htm
  • impedance_graph.htm
  • intersection_graph.htm
  • lattice_graph.htm
  • layer_graph.htm
  • logic_graph.htm
  • multi_graph.htm
  • multilevel_graph.htm
  • nearest_neighbor_graph.htm
  • netlist_graph.htm
  • network_graph.htm
  • optimization_graph.htm
  • pancake_graph.htm
  • parallel_prefix_graph.htm
  • partitioning_graph.htm
  • path_graph.htm
  • platform_graph.htm
  • quotient_graph.htm
  • rectilinear_graph.htm
  • relation_graph.htm
  • residual_graph.htm
  • resource_graph.htm
  • sequencing_graph.htm
  • shuffle_exchange_graph.htm
  • structured_directed_graph.htm
  • task_graph.htm
  • temperature_graph.htm
  • tile_graph.htm
  • timing_graph.htm
  • trace_graph.htm
  • transition_graph.htm

>>> hypergraph_vlsi/graph_vlsi_types

  • hypergraph.htm
  • hypergraph_literature.htm
  • hypergraph_vlsi/graph_vlsi_types_a2k.htm
  • hypergraph_vlsi/graph_vlsi_types_l2z.htm

>>> tree_vlsi

  • 000Steiner_tree.htm
  • 000clock_tree.htm
  • 000routing_tree.htm
  • 000sample.htm
  • 000spanning_tree.htm
  • 3dtree.htm
  • Wallace_tree.htm
  • a_tree.htm
  • arborescence_tree.htm
  • binary_tree.htm
  • buffered_tree.htm
  • butterfly_fat_tree.htm
  • carry_generation_tree.htm
  • complete_tree.htm
  • directed_tree.htm
  • fat_tree.htm
  • full_tree.htm
  • global_tree.htm
  • h_x_trees.htm
  • inter_block_abstract_tree.htm
  • interconnect_tree.htm
  • interval_tree.htm
  • load_matched_tree.htm
  • local_tree.htm
  • lt_tree.htm
  • minimum_cost_tree.htm
  • multi_crossing_tree.htm
  • multicast_tree.htm
  • multilevel_tree.htm
  • net_subtree.htm
  • o_tree.htm
  • p_tree.htm
  • parallel_prefix_tree.htm
  • partition_tree.htm
  • power_tree.htm
  • rctree.htm
  • rectilinear_tree.htm
  • redundant_tree.htm
  • rlctrees.htm
  • search_tree.htm
  • slicing_tree.htm
  • steiner.htm
  • steiner_literature.htm
  • vertex_disjoint_tree.htm
  • xor_tree.htm


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00000Graph
├<0000general>
│	├0000graph_intro.docx
│	├000graphtheory.pdf
│	├000graphtheory1.pdf
│	├<0trees>
│	│	├<Steiner_tree>
│	│	│	├Grotschel The Steiner Tree Packing Problem in VLSI Design p21.pdf
│	│	│	└Ihler Class Steiner trees and VLSI-design p22.pdf
│	│	└tree_types.docx
│	├AHUJA Network Flows Theory, Algorithms, and Applications Ch1_3 p103.pdf
│	├Alfakih The Graph Realization Problem via Semi-Definite Programming p70.pdf
│	├Archdeacon Topological Graph Theory a Survey p67.pdf
│	├Augeri ON GRAPH ISOMORPHISM AND THE PAGERANK ALGORITHM p153.pdf
│	├AVIS Graph Theory and Combinatorial Optimization p272.pdf
│	├Azary Grassmann Learning for Recognition and Classification p132.pdf
│	├Babai Graph Isomorphism in Quasipolynomial Time p89.pdf
│	├Bacik Structure of Graph Homomorphisms p111.pdf
│	├Bader Graph Partitioning and Graph Clustering p258.pdf
│	├Baingana Embedding Graphs under Centrality Constraints p54.pdf
│	├BALASUNDARAM GRAPH THEORETIC GENERALIZATIONS OF CLIQUE OPTIMIZATION AND EXTENSIONS p207.pdf
│	├Bang-Jensen Digraphs Theory Algorithms and Applications p772.pdf
│	├BangJensen Digraphs Theory algorithms and applications p772.pdf
│	├BARAHIMI WEB-BASED DRAWING SOFTWARE FOR GRAPHS IN 3D AND TWO LAYOUT ALGORITHMS p72.pdf
│	├Barenboim Distributed Graph Coloring Fundamentals and Recent Developments p160.pdf
│	├Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow a Java Environment for Graph Drawing p144.pdf
│	├Berge HYPERGRAPHS Combinatorics of Finite Sets p267.pdf
│	├Bernard GRAPH FILE FORMATS p50.pdf
│	├Biggs Algebraic graph theory p211.pdf
│	├Bondy Graph Theory 2008 p654.pdf
│	├Bondy Graph theory 2008 p666.pdf
│	├Bondy Graph Theory with Applications 1982 p270.pdf
│	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front p18.pdf
│	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front1 p18.pdf
│	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228.pdf
│	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole1 p228.pdf
│	├Boyd InProv Visualizing Provenance Graphs with Radial Layouts and Time-Based Hierarchical Grouping p59.pdf
│	├Brewster Graph Homomorphism Tutorial p164.pdf
│	├Bridgeman Techniques and Tools for Graph Drawing p168.pdf
│	├Brink Spherical parameterization methods for 3d surfaces p152.pdf
│	├Brouwer Spectra of graphs p229.pdf
│	├Brouwer Spectra of graphs p255.pdf
│	├Buhler Quantum approaches to the graph isomorphism problem p128.pdf
│	├Bunke Applied Pattern Recognition p246.pdf
│	├Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81 (2).pdf
│	├Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81 (3).pdf
│	├Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81.pdf
│	├Cabello Algorithms for embedded graphs p93.pdf
│	├CAI GRAPH HOMOMORPHISMS WITH COMPLEX VALUES A DICHOTOMY THEOREM p106.pdf
│	├Cardinal The Complexity of Simultaneous Geometric Graph Embedding p71.pdf
│	├Caric Vehnicle Routing Problem p152.pdf
│	├Caro Ant Colony Optimization and its Application to Adaptive Routing in Telecommunication Networks p374.pdf
│	├CHARTRAND Chromatic Graph Theory p498.pdf
│	├Chibante Simulated Annealing Theory with Applications p300.pdf
│	├Chowdhury Point-Set Embeddings of Planar Graphs with Fewer Bends p67.pdf
│	├christos GRAPH MINING AND COMMUNITY EVALUATION WITH DEGENERACY p152.pdf
│	├Chung Four graph partitioning algorithms p117.pdf
│	├Cooley EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf
│	├Coxon Uniform Random Generation of Graphs with Graph Grammars p50.pdf
│	├Cracknell Simulating and Optimising a Delivery Network of Autonomous Courier Agents p151.pdf
│	├Cruz Graph Drawing Tutorial p107.pdf
│	├Csardi igraph a package for network analysis p70.pdf
│	├Csikvari Graph Polynomials and Graph Transformations in Algebraic Graph Theory p119.pdf
│	├Culler Planar graphs p69.pdf
│	├Cullum PERFORMANCE ANALYSIS OF AUTOMATED ATTACK GRAPH GENERATION SOFTWARE p159.pdf
│	├Dantzig Linear programming vol 1 Introduction p474.pdf
│	├Dantzig Linear programming vol 2 Theory and Extensions p475.pdf
│	├Dasgupta Algorithms p318.pdf
│	├<de>
│	│	├4 Graphentheorie p96.pdf
│	│	├Ausgewahlte Kapitel aus der Graphentheorie p54.pdf
│	│	├Diestel Graphentheorie II p326.pdf
│	│	├Eidmann Algorithmische Graphentheorie im Unterricht unter Verwendung objektorientierter Datenstrukturen p561.pdf
│	│	├Gekeler Kombinatorik und Graphentheorie p122.pdf
│	│	├Graphentheorie p115.pdf
│	│	├Graphentheorie p422.pdf
│	│	├Grotschel Graphen- und Netzwerkalgorithmen p218.pdf
│	│	├Hartmann Highlights aus Graphentheorie Operation Research (Mathematik III) p66.pdf
│	│	├Jabornegg Spektrale Graphentheorie Graph Sparsification und Eigenwertabschatzungen p99.pdf
│	│	├Kaderali Graphen Algorithmen und Netze p478.pdf
│	│	├Klotz Graphentheorie II p115.pdf
│	│	├KRIESELL Algebraische Graphentheorie p49.pdf
│	│	├Krumke Graphentheoretische Konzepte und Algorithmen p161.pdf
│	│	├Mugnolo Graphentheorie p118.pdf
│	│	├Schelthoff Graphentheorie und Kryptographie p192.pdf
│	│	├Schwartz Einführung in die Graphentheorie p135.pdf
│	│	└Srivastav Graphentheorie p79.pdf
│	├De Jong The Handbook of Evolutionary Computation p940.pdf
│	├Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166.pdf
│	├Demaine Graph Algorithms p500.pdf
│	├DeMillo Combinatorial graph embedding p87.pdf
│	├Diestel Graph Theory2000 p322.pdf
│	├Diestel Graph Theory2005 p422.pdf
│	├Dong Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance p67.pdf
│	├Dongarra Graph Algorithms in the Language of Linear Algebra p372.pdf
│	├dos Santos Evolutionary Computation p582.pdf
│	├Dujmovic Track Layouts of Graphs p160.pdf
│	├Duran Graph Coloring Problems p114.pdf
│	├Dvorak New Techniques in Coloring Embedded Graphs p284.pdf
│	├Eades How to Draw a Graph Revisited p191.pdf
│	├Ebner Optimal Crossing Minimization using Integer Linear Programming p87.pdf
│	├EC_wikibook p234.pdf
│	├Epskamp Package qgraph p73.pdf
│	├Ersfolk Scheduling Dynamic Dataflow Graphs with Model Checking p225.pdf
│	├EVERETS ASSEMBLY LANGUAGE REPRESENTATION AND GRAPH GENERATION IN A PURE FUNCTIONAL PROGRAMMING LANGUAGE p108.pdf
│	├Faloutsos Large Graph Mining – Patterns, Tools and Cascade analysis p69.pdf
│	├Ferrer Theory and algorithms on the median graph p174.pdf
│	├<fr>
│	│	├Blin Algorithmique des graphes p76.pdf
│	│	├Bondy Theorie des Graphes p706.pdf
│	│	├BORIES GRAPHES ET COMBINATOIRE p67.pdf
│	│	├Bretto éléments de théorie des graphes p380.pdf
│	│	├Dantal Theorie des graphes Principes et programmation p95.pdf
│	│	├DAVAL Les graphes p50.pdf
│	│	├Durand Theorie des graphes p125.pdf
│	│	├Gournay Théorie des graphes p197.pdf
│	│	├Lambiotte Théorie des graphes p59.pdf
│	│	├Mammeri Théorie des graphes p64.pdf
│	│	├Maquin Elements de Theorie des Graphes et Programmation Lineaire p69.pdf
│	│	├Miage Theorie des graphes et algorithmes p64.pdf
│	│	├Rapine Théorie des graphes p116.pdf
│	│	├Rigo Theorie des graphes p176.pdf
│	│	├Roux Theorie des graphes p124.pdf
│	│	├Régin Théorie des Graphes p302.pdf
│	│	├Sais Theorie des graphes p125.pdf
│	│	└Solnon Théorie des graphes et optimisation dans les graphes p53.pdf
│	├Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│	├Gallian A Dynamic Survey of Graph Labeling p384.pdf
│	├García Compact and Efficient Representations of Graphs p301.pdf
│	├Gibert Graph Embedding in Vector Spaces p66.pdf
│	├Gibert Vector Space Embedding of Graphs via Statistics of Labelling Information p162.pdf
│	├<gk>
│	│	├Θηλυκ?? Σημει?σει? στη ΘΕΩΡΙΑ ΓΡΑΦΗΜΑΤΩΝ p117.pdf
│	│	├Παπαδ?πουλο? Θεωρ?α Γραφημ?των p104.pdf
│	│	└Παπαδ?πουλο? Θεωρ?α Γραφημ?των p130.pdf
│	├Glover Handbook of metaheuristics p570.pdf
│	├Godsil Algebraic Graph Theory p453.pdf
│	├Golumbic Algorithmic Graph Theory and Perfect Graphs 2ed p338.pdf
│	├Golumbic Graph Theory, Combinatorics and Algorithms_ Interdisciplinary Applications p295.pdf
│	├Goodman A Genetic Algorithm Approach to Compaction, Bin Packing, and Nesting Problems p73.pdf
│	├Greco Travelling Salesman Problem p212.pdf
│	├Griffin Graph Theory Penn State Math 485 Lecture Notes p173.pdf
│	├Grilli Automated Local Linear Embedding with an application to microarray data p92.pdf
│	├Grohe Structural and Logical Approaches to the Graph Isomorphism Problem p90.pdf
│	├Guduru GRAPH DATA CONVERSION AND TREE VISUALIZATION p60.pdf
│	├Guichard An Introduction to Combinatorics and Graph Theory p141.pdf
│	├Guichard An Introduction to Combinatorics and Graph Theory p149.pdf
│	├Guichard An Introduction to Combinatorics and Graph Theory p153.pdf
│	├Hancock Advanced topics in spectral graph theory p134.pdf
│	├Harary Graph theory p281.pdf
│	├Harris Combinatorics and Graph Theory p392.pdf
│	├Hartman EXTREMAL PROBLEMS IN GRAPH THEORY p97.pdf
│	├Harvey On Treewidth and Graph Minors p163.pdf
│	├Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134.pdf
│	├Hendler Foundations of Artificial Intelligence p1035.pdf
│	├Hladky Structural Graph Theory p188.pdf
│	├Hu Visualizing Data with Graphs and Maps p76.pdf
│	├Iglesias Graph representation of documents content and its suitability for text mining tasks p72.pdf
│	├Jameson An Address Event Representation (AER) Multicast Router for Colour Vision p200.pdf
│	├Jampani Simultaneous Graph Representation Problems p94.pdf
│	├Johnson The Traveling Salesman Problem A Case Study in Local Optimization p103.pdf
│	├Joyner Algorithmic Graph Theory p322.pdf
│	├Junger THE TRAVELING SALESMAN PROBLEM p117.pdf
│	├Junghans Visualization of Hyperedges in Fixed Graph Layouts p131.pdf
│	├Kant Algorithms for Drawing Planar Graphs p237.pdf
│	├Kaul Graph Packing and Degree Sequences p72.pdf
│	├Kennedy Swarm intelligence p541.pdf
│	├Kepner Graph Algorithms in the Language of Linear Algebra p372.pdf
│	├Knobel From Random Graphs to Complex Networks A Modelling Approach p87.pdf
│	├Kocurova2007 Analysis of algorithms for computing the crossing number p119.pdf
│	├Kolla Merging Techniques for Combinatorial Optimization Spectral Graph Theory and Semidefinite Programming p96.pdf
│	├Krug New Approaches on Octilinear Graph Drawing p165.pdf
│	├Kuhnert Space Efficient Algorithms for Graph Isomorphism and Representation p117.pdf
│	├Lidicky Graph coloring problems p106.pdf
│	├Lovasz Geometric Representations of Graphs p213.pdf
│	├LUQM Fuzzy Multilevel Graph Embedding for Recognition Indexing and Retrieval of Graphic Document Images p186.pdf
│	├Martin Graph Theory and Social Networks p148.pdf
│	├Martin Notes on Extremal Graph Theory p101.pdf
│	├Marx Algorithmic graph structure theory p255.pdf
│	├Marx Graph Coloring with Local and Global Constraints p176.pdf
│	├McBride SYSTEM ANALYSIS THROUGH BOND GRAPH MODELING p325.pdf
│	├Miller Spectral Graph Theory, Linear Solvers, and Applications p134.pdf
│	├Mirrokni Large Scale Graph Mining Theory and Practice p65.pdf
│	├Mugnolo Graphentheorie p118.pdf
│	├Mumford Drawing Graphs for Cartographic Applications p144.pdf
│	├Muzychuk Graph Isomorphism problem, Weisfeiler-Leman algortihm and coherent configurations p96.pdf
│	├Needham Graph Modeling Dos and Donts p96.pdf
│	├ORLIN DYNAMIC NETWORK FLOWS p115.pdf
│	├Pantel Graph Packing Problems p86.pdf
│	├Picard Coinductive Graph Representation p64.pdf
│	├Potoczak Survey of Graph Embeddings into Compact Surfaces p117.pdf
│	├Rajappa Solving Combinatorial Optimization Problems Using Genetic Algorithms and Ant Colony Optimization p105.pdf
│	├Ray Graph Theory with Algorithms and its Applications p222.pdf
│	├Riesen Classification and Clustering of Vector Space Embedded Graphs p344.pdf
│	├Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346 (2).pdf
│	├Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346.pdf
│	├<ru>
│	│	├Burkatofskaya Теория графов Part 1 p203.pdf
│	│	├Domnin Элементы теории графовp144.pdf
│	│	├Kariof Graph theory russian p418.pdf
│	│	├Lazarev Graph theory Russian p220.pdf
│	│	├Melnikov Элементы теории графов p108.pdf
│	│	├Nocoba Элементы теории графов p107.pdf
│	│	├Nocof Элементы теории графов p107.pdf
│	│	├Penjam Теория графовp50.pdf
│	│	├Зарипова Дискретная математика Часть III Теория графов p179 (2).pdf
│	│	├Зарипова Дискретная математика Часть III Теория графов p179.pdf
│	│	├Захарова ТЕОРИЯ ГРАФОВ p60.pdf
│	│	├Лакеев ЭЛЕМЕНТЫ ТЕОРИИ ОБЫКНОВЕННЫХ ГРАФОВ p84.pdf
│	│	└ЛеденеваТ АЛГОРИТМЫ ТЕОРИ И ГРАФОВ КОДОВЫ ЕГРАФЫ p89.pdf
│	├Ruohonen GRAPH THEORY p114.pdf
│	├Saito Lecture 10 Graph Construction from Given Datasets p93.pdf
│	├Sarvottamananda Planar Graphs Planarity Testing and Embedding p151.pdf
│	├Sausen Models for the Steiner Tree Packing Problem p85.pdf
│	├Scheinerman Fractional Graph Theory p167.pdf
│	├Schulz Graph Partitioning and Graph Clustering in Theory and Practice p202.pdf
│	├Schwarz Graph Representations and Algorithms p164.pdf
│	├Seeland Structural Graph Clustering Scalable Methods and Applications for Graph Classification and Regression p206.pdf
│	├Seventh Cologne-Twente Workshop on Graphs and Combinatorial Optimization p204.pdf
│	├Shakarian A Review of Evolutionary Graph Theory With Applications to Game Theory p45.pdf
│	├Shaw Graph Embedding and Nonlinear Dimensionality Reduction p108.pdf
│	├Siebenhaller Orthogonal Graph Drawing with Constraints Algorithms and Applications p222.pdf
│	├Simonis Constraint Applications Using Graph Theory Results p71.pdf
│	├SKHIRI Large Graph Mining Recent Development, Challenges and Potential Solutions p113.pdf
│	├Smithers Graph Theory for the Secondary School Classroom p151.pdf
│	├Spinrad Graph theory p245.pdf
│	├Sp?nemann On the Automatic Layout of Data Flow Diagrams p99.pdf
│	├Stein Extremal graph theory p171.pdf
│	├Submodular Function_2ed p881.pdf
│	├Sun A contribution to the theory of signed graph homomorphism bound and Hamiltonicity p156.pdf
│	├Thulasiraman Handbook of Graph Theory Combinatorial Optimization and Algorithms p1217.pdf
│	├Toth Universality in Geometric Graph Theory p96.pdf
│	├Trinks Graph Polynomials and Their Representations p122.pdf
│	├Ullman CHAPTER 9 The Graph Data Model p78.pdf
│	├van der Hofstad Random Graphs and Complex Networks. Vo. I p328.pdf
│	├van der Hofstad Random Graphs and Complex Networks. Vol I p312.pdf
│	├van Dongen GRAPH CLUSTERING by FLOW SIMULATION p173.pdf
│	├van Dongen GRAPH CLUSTERING by FLOW SIMULATION p175.pdf
│	├Van Dooren Graph Theory and Applications p110 .pdf
│	├van Steen Graph Theory and Complex Networks An Introduction p299.pdf
│	├van Steen Graph Theory and Complex Networks p287.pdf
│	├Vanderbei Linear Programming Foundations and Extensions p466.pdf
│	├Veinott Lectures in Supply-Chain Optimization p261.pdf
│	├Vella A FUNDAMENTALLY TOPOLOGICAL PERSPECTIVE ON GRAPH THEORY p263.pdf
│	├Vogt An open source browser-based software tool for graph drawing and visualization p171.pdf
│	├Webster Solving Combinatorial Optimization Problems Using a New Algorithm Based on Gravitational Attraction p268.pdf
│	├West INTRODUCTION TO GRAPH THEORY 2nd Edition Solution Manual p260.pdf
│	├Wikipedia Social Network Analysis Theory and Applications p116.pdf
│	├Wilson Introduction to Graph Theory p180.pdf
│	├Woeginger Combinatorial Graph Theory p70.pdf
│	├Wu A Glimpse at Algorithmic Graph Theory p187.pdf
│	├Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf
│	├Yilma Results in Extremal Graph and Hypergraph Theory p99.pdf
│	├Yin W-graph representations for Coxeter groups and Hecke algebras p101.pdf
│	├Yu Introduction to Evolutionary Algorithms p433.pdf
│	├Yu2014 A Practical Torus Embedding Algorithm and Its Implementation p84.pdf
│	├Zewi Vector Representation of Graph Domination p66.pdf
│	├Ziegler n-Level Hypergraph Partitioning p52.pdf
│	└<ZZZgraph_theory>
│	  	├<graph_theory_math>
│	  	│	├<algebraic_graph_theory>
│	  	│	│	├Biggs Algebraic graph theory p211.pdf
│	  	│	│	├Csikvari Graph Polynomials and Graph Transformations in Algebraic Graph Theory p119.pdf
│	  	│	│	└Godsil Algebraic Graph Theory p453.pdf
│	  	│	├<algorithmic_graph_theory>
│	  	│	│	├Golumbic Algorithmic Graph Theory and Perfect Graphs 2ed p338.pdf
│	  	│	│	├Joyner Algorithmic Graph Theory p322.pdf
│	  	│	│	├Marx Algorithmic graph structure theory p255.pdf
│	  	│	│	└Wu A Glimpse at Algorithmic Graph Theory p187.pdf
│	  	│	├<metric_graph_theory>
│	  	│	│	└Bandelt Metric graph theory and geometry a survey p38.pdf
│	  	│	└<spectral_graph_theory>
│	  	│	  	├Brouwer Spectra of graphs p229.pdf
│	  	│	  	├Brouwer Spectra of graphs p255.pdf
│	  	│	  	├Gallier Spectral Theory of Unsigned and Signed Graphs Applications to Graph Clustering a Survey p122.pdf
│	  	│	  	├Hancock Advanced topics in spectral graph theory p134.pdf
│	  	│	  	├Kelleher Spectral Graph Theory p45.pdf
│	  	│	  	├Kolla Merging Techniques for Combinatorial Optimization Spectral Graph Theory and Semidefinite Programming p96.pdf
│	  	│	  	├Li李宇軒 Spectral Graph Theory p46.pdf
│	  	│	  	├Miller Spectral Graph Theory, Linear Solvers, and Applications p134.pdf
│	  	│	  	├Rittenhouse Properties and Recent Applications in Spectral Graph Theory p59.pdf
│	  	│	  	└Spielman Spectral Graph Theory and its Applications p75.pdf
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│	  	│	├<graph_minors_theory>
│	  	│	│	├Ghandchi Graph Minors Theory p23.pdf
│	  	│	│	└Harvey On Treewidth and Graph Minors p163.pdf
│	  	│	├<graph_ramsey_theory>
│	  	│	│	├Conlon Recent developments in graph Ramsey theory p54.pdf
│	  	│	│	└Dickson An Introduction to Ramsey Theory on Graphs p86.pdf
│	  	│	└<graph_structure_theory>
│	  	│	  	└Marx Algorithmic graph structure theory p255.pdf
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│	  	  	├<ATIS_Graph_Theory>
│	  	  	│	└Thompson ATIS Graph Theory p65.pdf
│	  	  	├<Chromatic_Graph_Theory>
│	  	  	│	└CHARTRAND Chromatic Graph Theory p498.pdf
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│	  	  	│	├000extremal_graph_theory.docx
│	  	  	│	├Engbers Graph theory — to the extreme p76.pdf
│	  	  	│	├Grzesik Flag Algebras in Extremal Graph Theory p63.pdf
│	  	  	│	├Hartman EXTREMAL PROBLEMS IN GRAPH THEORY p97.pdf
│	  	  	│	├Martin Notes on Extremal Graph Theory p101.pdf
│	  	  	│	├McClintock Extremal Graph Theory for Book-Embeddings p64.pdf
│	  	  	│	├Morris Extremal and Probabilistic Combinatorics p85.pdf
│	  	  	│	├Shapira Extremal Graph Theory p53.pdf
│	  	  	│	├Sperfeld Semidefinite programming in extremal graph theory p85.pdf
│	  	  	│	├Stein Extremal graph theory p171.pdf
│	  	  	│	└Yilma Results in Extremal Graph and Hypergraph Theory p99.pdf
│	  	  	├<fractional_graph_heory>
│	  	  	│	└Scheinerman Fractional Graph Theory p167.pdf
│	  	  	└<Structural Graph Theory>
│	  	  	  	└Hladky Structural Graph Theory p188.pdf
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│	│	│	  	  	├abg.js
│	│	│	  	  	├m_js_controller.js
│	│	│	  	  	├m_qs_click_protection.js
│	│	│	  	  	├m_window_focus_non_hydra.js
│	│	│	  	  	└osd_listener.js
│	│	├<3_data_007>
│	│	│	└show_ads_impl.js
│	│	├adsbygoogle.js
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
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│	│	├<3_data>
│	│	│	└codegists.js
│	│	├<3_data_002>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├4.js
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├analytics.js
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│	│	├a_003.htm
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 4 - codegist.net_files>
│	│	├4.js
│	│	├<4_data>
│	│	│	└<ads_data>
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│	│	│	└<ads_data>
│	│	│	  	└<ads_data>
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│	│	│	└osd.js
│	│	├<4_data_006>
│	│	│	└<ads_data>
│	│	│	  	└<ads_data>
│	│	│	  	  	└<index_data>
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│	│	├<4_data_007>
│	│	├adsbygoogle.js
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├integrator.js
│	│	├main.js
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 4 - codegists.com_files>
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│	│	├3.js
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│	│	├4_002.htm
│	│	├4_003.htm
│	│	├<4_data>
│	│	│	└codegists.js
│	│	├<4_data_003>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├analytics.js
│	│	├a_002.htm
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 5 - codegist.net_files>
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│	│	├5.htm
│	│	├5.js
│	│	├5_002.htm
│	│	├5_003.htm
│	│	├<5_data>
│	│	│	└codegist.js
│	│	├<5_data_003>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├a_002.htm
│	│	├a_003.htm
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 5 - codegists.com_files>
│	│	├2227875_492x328.jpg
│	│	├2308119_492x328.jpg
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│	│	├2452279_492x328.jpg
│	│	├2457990_492x328.jpg
│	│	├4.js
│	│	├5.htm
│	│	├5_002.htm
│	│	├5_003.htm
│	│	├5_004.htm
│	│	├<5_data_002>
│	│	│	└codegists.js
│	│	├<5_data_004>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├analytics.js
│	│	├a_002.htm
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├email-decode.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 6 - codegist.net_files>
│	│	├2348963_492x328.jpg
│	│	├2373884_492x328.jpg
│	│	├2440567_492x328.jpg
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│	│	├2452333_492x328.jpg
│	│	├2504033_492x328.jpg
│	│	├6.htm
│	│	├6.js
│	│	├6_002.htm
│	│	├6_003.htm
│	│	├6_004.htm
│	│	├6_005.htm
│	│	├6_006.htm
│	│	├<6_data>
│	│	│	└ads.htm
│	│	├<6_data_002>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	└m_js_controller.js
│	│	├<6_data_003>
│	│	│	└codegist.js
│	│	├<6_data_004>
│	│	│	├a.htm
│	│	│	├ads.htm
│	│	│	└osd.js
│	│	├<6_data_006>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├adsbygoogle.js
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 6 - codegists.com_files>
│	│	├2308119_492x328.jpg
│	│	├2357077_492x328.jpg
│	│	├2378106_492x328.jpg
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│	│	├2467997_492x328.jpg
│	│	├5.js
│	│	├6.htm
│	│	├<6_data>
│	│	│	└codegists.js
│	│	├adsbygoogle.js
│	│	├analytics.js
│	│	├beacon.js
│	│	├i.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 7 - codegist.net_files>
│	│	├2348963_492x328.jpg
│	│	├2373884_492x328.jpg
│	│	├2440567_492x328.jpg
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│	│	├2452333_492x328.jpg
│	│	├2504033_492x328.jpg
│	│	├7.htm
│	│	├7.js
│	│	├7_002.htm
│	│	├7_003.htm
│	│	├7_004.htm
│	│	├7_005.htm
│	│	├7_006.htm
│	│	├<7_data>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	├a.htm
│	│	│	  	├ads.htm
│	│	│	  	└<ads_data>
│	│	│	  	  	└PQMXuY6MlKBLQCoydS_eTwE-g1k9WHzhWAyB_BDUb3g.js
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│	│	│	└<ads_data>
│	│	│	  	├a.htm
│	│	│	  	├abg.js
│	│	│	  	├m_js_controller.js
│	│	│	  	├m_qs_click_protection.js
│	│	│	  	├m_window_focus_non_hydra.js
│	│	│	  	└osd_listener.js
│	│	├<7_data_003>
│	│	│	└codegist.js
│	│	├<7_data_004>
│	│	│	├a.htm
│	│	│	├ads.htm
│	│	│	└osd.js
│	│	├<7_data_005>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	└a.htm
│	│	├<7_data_006>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├adsbygoogle.js
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├email-decode.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 8 - codegist.net_files>
│	│	├2348963_492x328.jpg
│	│	├2373884_492x328.jpg
│	│	├2440567_492x328.jpg
│	│	├2442578_492x328.jpg
│	│	├2452333_492x328.jpg
│	│	├2504033_492x328.jpg
│	│	├8.htm
│	│	├8.js
│	│	├8_002.htm
│	│	├8_003.htm
│	│	├8_004.htm
│	│	├8_005.htm
│	│	├<8_data>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	└m_js_controller.js
│	│	├<8_data_003>
│	│	│	└codegist.js
│	│	├<8_data_004>
│	│	│	├a.htm
│	│	│	├ads.htm
│	│	│	└osd.js
│	│	├<8_data_005>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├a_002.htm
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 8 - codegists.com_files>
│	│	├2308119_492x328.jpg
│	│	├2357077_492x328.jpg
│	│	├2378106_492x328.jpg
│	│	├2452279_492x328.jpg
│	│	├2457990_492x328.jpg
│	│	├2467997_492x328.jpg
│	│	├6.js
│	│	├8.htm
│	│	├8_002.htm
│	│	├8_003.htm
│	│	├8_004.htm
│	│	├8_005.htm
│	│	├<8_data_003>
│	│	│	└codegists.js
│	│	├<8_data_004>
│	│	│	├ads.htm
│	│	│	└osd.js
│	│	├<8_data_005>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├analytics.js
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - 9 - codegist.net_files>
│	│	├2348963_492x328.jpg
│	│	├2373884_492x328.jpg
│	│	├2440567_492x328.jpg
│	│	├2442578_492x328.jpg
│	│	├2452333_492x328.jpg
│	│	├2504033_492x328.jpg
│	│	├9.htm
│	│	├9.js
│	│	├9_002.htm
│	│	├9_003.htm
│	│	├9_004.htm
│	│	├<9_data_002>
│	│	│	└codegist.js
│	│	├<9_data_003>
│	│	│	├ads.htm
│	│	│	└osd.js
│	│	├<9_data_004>
│	│	│	├show_ads_impl.js
│	│	│	└zrt_lookup.htm
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├a_002.htm
│	│	├a_003.htm
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
│	│	├mgid_logo_mini_43x20.png
│	│	├shAutoloader.js
│	│	├shCore.css
│	│	├shCore.js
│	│	├shThemeDefault.css
│	│	└style.css
│	├<Convert Adjacency List To Adjacency Matrix Java - codegist.net_files>
│	│	├1.js
│	│	├2373884_492x328.jpg
│	│	├2440567_492x328.jpg
│	│	├2442578_492x328.jpg
│	│	├2452333_492x328.jpg
│	│	├2464804_492x328.jpg
│	│	├2504033_492x328.jpg
│	│	├a.htm
│	│	├adsbygoogle.js
│	│	├a_002.htm
│	│	├a_003.htm
│	│	├a_004.htm
│	│	├a_005.htm
│	│	├a_006.htm
│	│	├<a_data>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	├a.htm
│	│	│	  	└ads.htm
│	│	├<a_data_002>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	├a.htm
│	│	│	  	├abg.js
│	│	│	  	├ads.htm
│	│	│	  	├<ads_data>
│	│	│	  	│	└PQMXuY6MlKBLQCoydS_eTwE-g1k9WHzhWAyB_BDUb3g.js
│	│	│	  	├m_js_controller.js
│	│	│	  	├m_qs_click_protection.js
│	│	│	  	├m_window_focus_non_hydra.js
│	│	│	  	└osd_listener.js
│	│	├<a_data_003>
│	│	│	└codegist.js
│	│	├<a_data_004>
│	│	│	├ads.htm
│	│	│	└<ads_data>
│	│	│	  	├ads.htm
│	│	│	  	└<ads_data>
│	│	│	  	  	└rolling.js
│	│	├<a_data_005>
│	│	│	├a.htm
│	│	│	├ads.htm
│	│	│	├osd.js
│	│	│	└zrt_lookup.htm
│	│	├<a_data_006>
│	│	│	├ads.htm
│	│	│	├<ads_data>
│	│	│	│	├ads.htm
│	│	│	│	└<ads_data>
│	│	│	│	  	├a
│	│	│	│	  	└google.gif
│	│	│	└show_ads_impl.js
│	│	├beacon.js
│	│	├ca-pub-3617567196023504.js
│	│	├i.js
│	│	├integrator.js
│	│	├main.js
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│	  	├shCore.js
│	  	├shThemeDefault.css
│	  	└style.css
├0000graph_resources.docx
├000graphtheory_contacts.txt
├<000graph_algorithms_software>
│	├<graph_algorithms_codes>
│	│	├<ccppcsharp>
│	│	│	├echo-akash.cpp
│	│	│	├echo-akash.cpp.bak
│	│	│	├graph.c
│	│	│	├spl0i7.cpp
│	│	│	└spl0i7.cpp.bak
│	│	├Dasgupta Algorithms p318.pdf
│	│	├Demaine Graph Algorithms p500.pdf
│	│	├<Dijkstra_shortest_path_algorithm>
│	│	│	└Peyer A Generalization of Dijkstra's Shortest Path Algorithm with Applications to VLSI Routing p24.pdf
│	│	├<haskell>
│	│	│	├ericnething.hs
│	│	│	├ericnething.hs.bak
│	│	│	├fgl-5.4.2.2.tar.gz
│	│	│	├<fgl-5.6.0.0>
│	│	│	│	├.gitignore
│	│	│	│	├.travis.yml
│	│	│	│	├ChangeLog
│	│	│	│	├<Data>
│	│	│	│	│	└<Graph>
│	│	│	│	│	  	├<Inductive>
│	│	│	│	│	  	│	├Basic.hs
│	│	│	│	│	  	│	├Example.hs
│	│	│	│	│	  	│	├Graph.hs
│	│	│	│	│	  	│	├<Internal>
│	│	│	│	│	  	│	│	├Heap.hs
│	│	│	│	│	  	│	│	├Queue.hs
│	│	│	│	│	  	│	│	├RootPath.hs
│	│	│	│	│	  	│	│	└Thread.hs
│	│	│	│	│	  	│	├<Monad>
│	│	│	│	│	  	│	│	├IOArray.hs
│	│	│	│	│	  	│	│	└STArray.hs
│	│	│	│	│	  	│	├Monad.hs
│	│	│	│	│	  	│	├NodeMap.hs
│	│	│	│	│	  	│	├PatriciaTree.hs
│	│	│	│	│	  	│	├<Query>
│	│	│	│	│	  	│	│	├ArtPoint.hs
│	│	│	│	│	  	│	│	├BCC.hs
│	│	│	│	│	  	│	│	├BFS.hs
│	│	│	│	│	  	│	│	├DFS.hs
│	│	│	│	│	  	│	│	├Dominators.hs
│	│	│	│	│	  	│	│	├GVD.hs
│	│	│	│	│	  	│	│	├Indep.hs
│	│	│	│	│	  	│	│	├MaxFlow.hs
│	│	│	│	│	  	│	│	├MaxFlow2.hs
│	│	│	│	│	  	│	│	├Monad.hs
│	│	│	│	│	  	│	│	├MST.hs
│	│	│	│	│	  	│	│	├SP.hs
│	│	│	│	│	  	│	│	└TransClos.hs
│	│	│	│	│	  	│	├Query.hs
│	│	│	│	│	  	│	└Tree.hs
│	│	│	│	│	  	└Inductive.hs
│	│	│	│	├<fgl-arbitrary>
│	│	│	│	│	├ChangeLog
│	│	│	│	│	├<Data>
│	│	│	│	│	│	└<Graph>
│	│	│	│	│	│	  	└<Inductive>
│	│	│	│	│	│	  	  	└Arbitrary.hs
│	│	│	│	│	├fgl-arbitrary.cabal
│	│	│	│	│	├LICENSE
│	│	│	│	│	├Setup.hs
│	│	│	│	│	└<test>
│	│	│	│	│	  	└TestSuite.hs
│	│	│	│	├fgl.cabal
│	│	│	│	├LICENSE
│	│	│	│	├README.md
│	│	│	│	├Setup.hs
│	│	│	│	└<test>
│	│	│	│	  	├benchmark.hs
│	│	│	│	  	├<Data>
│	│	│	│	  	│	└<Graph>
│	│	│	│	  	│	  	└<Inductive>
│	│	│	│	  	│	  	  	├<Graph>
│	│	│	│	  	│	  	  	│	└Properties.hs
│	│	│	│	  	│	  	  	├Proxy.hs
│	│	│	│	  	│	  	  	└<Query>
│	│	│	│	  	│	  	  	  	└Properties.hs
│	│	│	│	  	├test.hs
│	│	│	│	  	└TestSuite.hs
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│	│	│	└fgl-master.zip
│	│	├<java>
│	│	│	├BellmanFord.java
│	│	│	├Digraph.java
│	│	│	├dijkstra.java
│	│	│	├EdgeWeightedDigraph.java
│	│	│	├Graph.java
│	│	│	├Graph2.java
│	│	│	├Graph4
│	│	│	├Graph4.java
│	│	│	├imamhidayat92.java
│	│	│	├imamhidayat92.java.bak
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│	│	│	├mozi22.java
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│	│	│	│	├<Bridge.java_files>
│	│	│	│	│	├ga.js
│	│	│	│	│	└java.css
│	│	│	│	├CC.java.html
│	│	│	│	├<CC.java_files>
│	│	│	│	│	├ga.js
│	│	│	│	│	└java.css
│	│	│	│	├Cycle.java.html
│	│	│	│	├<Cycle.java_files>
│	│	│	│	│	├ga.js
│	│	│	│	│	└java.css
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│	│	│	│	├<DepthFirstPaths.java_files>
│	│	│	│	│	├ga.js
│	│	│	│	│	└java.css
│	│	│	│	├Graph.java.html
│	│	│	│	├<Graph.java_files>
│	│	│	│	│	├ga.js
│	│	│	│	│	└java.css
│	│	│	│	├NonrecursiveDFS.java.html
│	│	│	│	├<NonrecursiveDFS.java_files>
│	│	│	│	│	├ga.js
│	│	│	│	│	└java.css
│	│	│	│	├Sedgewick.txt
│	│	│	│	├Undirected Graphs.htm
│	│	│	│	└<Undirected Graphs_files>
│	│	│	│	  	├adjacency-lists.png
│	│	│	│	  	├algs4.css
│	│	│	│	  	├analytics.js
│	│	│	│	  	├cc-api.png
│	│	│	│	  	├cover-analysis-of-algorithms.png
│	│	│	│	  	├cover.png
│	│	│	│	  	├cover_002.png
│	│	│	│	  	├forest.png
│	│	│	│	  	├ga.js
│	│	│	│	  	├graph-anatomy.png
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│	│	│	│	  	├graph-input.png
│	│	│	│	  	├graph.png
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│	│	│	│	  	├maze22.png
│	│	│	│	  	├minecraft-maze.png
│	│	│	│	  	├movies.png
│	│	│	│	  	├paths-api.png
│	│	│	│	  	├routes.png
│	│	│	│	  	├search-api.png
│	│	│	│	  	├swfobject.js
│	│	│	│	  	├symbol-graph-api.png
│	│	│	│	  	├symbol-graph.png
│	│	│	│	  	└tree.png
│	│	│	├Sumitjain.java
│	│	│	├Sumitjain.java.bak
│	│	│	├Tareq-SiSalem.java
│	│	│	├Tareq-SiSalem.java.bak
│	│	│	├thmain.zip
│	│	│	├yuxiangdai.java
│	│	│	└yuxiangdai.java.bak
│	│	├<jupyter-notebook>
│	│	│	├anirudhjayaraman.ipynb
│	│	│	├anirudhjayaraman.ipynb.bak
│	│	│	├FredtCh1996.ipynb
│	│	│	├FredtCh1996.ipynb.bak
│	│	│	├isurudilhansenanayaka.ipynb
│	│	│	├isurudilhansenanayaka.ipynb.bak
│	│	│	├ukc.ipynb
│	│	│	└ukc.ipynb.bak
│	│	├Kepner Graph Algorithms in the Language of Linear Algebra p372.pdf
│	│	├<lisps>
│	│	│	└Schulte.txt
│	│	├<perl>
│	│	│	├<Graph-0.9704>
│	│	│	│	├Changes
│	│	│	│	├DESIGN
│	│	│	│	├<lib>
│	│	│	│	│	├<Graph>
│	│	│	│	│	│	├<AdjacencyMap>
│	│	│	│	│	│	│	├Heavy.pm
│	│	│	│	│	│	│	├Light.pm
│	│	│	│	│	│	│	└Vertex.pm
│	│	│	│	│	│	├AdjacencyMap.pm
│	│	│	│	│	│	├AdjacencyMatrix.pm
│	│	│	│	│	│	├Attribute.pm
│	│	│	│	│	│	├BitMatrix.pm
│	│	│	│	│	│	├Directed.pm
│	│	│	│	│	│	├Matrix.pm
│	│	│	│	│	│	├MSTHeapElem.pm
│	│	│	│	│	│	├SPTHeapElem.pm
│	│	│	│	│	│	├<TransitiveClosure>
│	│	│	│	│	│	│	└Matrix.pm
│	│	│	│	│	│	├TransitiveClosure.pm
│	│	│	│	│	│	├<Traversal>
│	│	│	│	│	│	│	├BFS.pm
│	│	│	│	│	│	│	└DFS.pm
│	│	│	│	│	│	├Traversal.pm
│	│	│	│	│	│	├Undirected.pm
│	│	│	│	│	│	└UnionFind.pm
│	│	│	│	│	├Graph.pm
│	│	│	│	│	├Graph.pod
│	│	│	│	│	└<Heap071>
│	│	│	│	│	  	├Elem.pm
│	│	│	│	│	  	└Fibonacci.pm
│	│	│	│	├Makefile.PL
│	│	│	│	├MANIFEST
│	│	│	│	├META.json
│	│	│	│	├META.yml
│	│	│	│	├README
│	│	│	│	├RELEASE
│	│	│	│	├<t>
│	│	│	│	│	├00_use.t
│	│	│	│	│	├01_isa.t
│	│	│	│	│	├02_trap.t
│	│	│	│	│	├03_derived.t
│	│	│	│	│	├04_dgraph.t
│	│	│	│	│	├05_ugraph.t
│	│	│	│	│	├06_new.t
│	│	│	│	│	├07_gen.t
│	│	│	│	│	├08_stringify.t
│	│	│	│	│	├09_eq.t
│	│	│	│	│	├10_has_vertices.t
│	│	│	│	│	├11_vertices.t
│	│	│	│	│	├12_has_vertex.t
│	│	│	│	│	├13_add_vertex.t
│	│	│	│	│	├14_delete_vertex.t
│	│	│	│	│	├15_has_edges.t
│	│	│	│	│	├16_edges.t
│	│	│	│	│	├17_has_edge.t
│	│	│	│	│	├18_add_edge.t
│	│	│	│	│	├19_delete_edge.t
│	│	│	│	│	├20_countvertexed.t
│	│	│	│	│	├21_multivertexed.t
│	│	│	│	│	├22_refvertexed.t
│	│	│	│	│	├23_hypervertexed.t
│	│	│	│	│	├24_mixvertexed.t
│	│	│	│	│	├25_countedged.t
│	│	│	│	│	├26_multiedged.t
│	│	│	│	│	├27_omnidirected.t
│	│	│	│	│	├28_hyperedged.t
│	│	│	│	│	├29_uniqedged.t
│	│	│	│	│	├30_mixedged.t
│	│	│	│	│	├31_hypervertex.t
│	│	│	│	│	├32_hypervertex_edges.t
│	│	│	│	│	├33_hyperedge.t
│	│	│	│	│	├34_omnivertexed.t
│	│	│	│	│	├35_uniqvertexed.t
│	│	│	│	│	├36_omniuniqvertexed.t
│	│	│	│	│	├37_hypervertex_implicit.t
│	│	│	│	│	├38_vertices_at.t
│	│	│	│	│	├39_edges_at.t
│	│	│	│	│	├40_edges_from.t
│	│	│	│	│	├41_edges_to.t
│	│	│	│	│	├42_add_path.t
│	│	│	│	│	├43_has_path.t
│	│	│	│	│	├44_delete_path.t
│	│	│	│	│	├45_add_cycle.t
│	│	│	│	│	├46_has_cycle.t
│	│	│	│	│	├47_delete_cycle.t
│	│	│	│	│	├48_get_vertex_count.t
│	│	│	│	│	├49_get_edge_count.t
│	│	│	│	│	├50_vertex_attributes.t
│	│	│	│	│	├51_multivertex_attributes.t
│	│	│	│	│	├52_edge_attributes.t
│	│	│	│	│	├53_multiedge_attributes.t
│	│	│	│	│	├54_graph_attributes.t
│	│	│	│	│	├55_attributes.t
│	│	│	│	│	├56_neighbourhood.t
│	│	│	│	│	├57_degree.t
│	│	│	│	│	├58_connections.t
│	│	│	│	│	├59_dfs.t
│	│	│	│	│	├60_bfs.t
│	│	│	│	│	├61_connected.t
│	│	│	│	│	├62_bcc.t
│	│	│	│	│	├63_scc.t
│	│	│	│	│	├64_mst.t
│	│	│	│	│	├65_ref.t
│	│	│	│	│	├66_simple.t
│	│	│	│	│	├67_copy.t
│	│	│	│	│	├68_transpose.t
│	│	│	│	│	├69_complete.t
│	│	│	│	│	├70_complement.t
│	│	│	│	│	├71_spt.t
│	│	│	│	│	├72_transitive.t
│	│	│	│	│	├73_diameter.t
│	│	│	│	│	├74_random.t
│	│	│	│	│	├75_attribute_array.t
│	│	│	│	│	├76_attribute_hash.t
│	│	│	│	│	├77_adjacency.t
│	│	│	│	│	├78_expect.t
│	│	│	│	│	├79_unionfind.t
│	│	│	│	│	├80_isomorphic.t
│	│	│	│	│	├81_dump.t
│	│	│	│	│	├82_cycle.t
│	│	│	│	│	├83_bitmatrix.t
│	│	│	│	│	├84_all_cessors.t
│	│	│	│	│	├85_subgraph.t
│	│	│	│	│	├99_misc.t
│	│	│	│	│	├g02_00directed.t
│	│	│	│	│	├g02_01undirected.t
│	│	│	│	│	├g02_02multiple.t
│	│	│	│	│	├g02_03degree.t
│	│	│	│	│	├g02_04attribute.t
│	│	│	│	│	├g02_05copy.t
│	│	│	│	│	├g02_06transpose.t
│	│	│	│	│	├g02_07complete.t
│	│	│	│	│	├g02_08complement.t
│	│	│	│	│	├g02_09scc.t
│	│	│	│	│	├MyDGraph.pm
│	│	│	│	│	├MyGraph.pm
│	│	│	│	│	├MyUGraph.pm
│	│	│	│	│	├pod-coverage.t
│	│	│	│	│	├pod.t
│	│	│	│	│	├simple.pl
│	│	│	│	│	├u_an_uf.t
│	│	│	│	│	├u_at1.t
│	│	│	│	│	├u_at2.t
│	│	│	│	│	├u_at3.t
│	│	│	│	│	├u_bb_rv.t
│	│	│	│	│	├u_bf.t
│	│	│	│	│	├u_bill.t
│	│	│	│	│	├u_bo_ap1.t
│	│	│	│	│	├u_bo_ap2.t
│	│	│	│	│	├u_bo_apx.t
│	│	│	│	│	├u_cd_rv.t
│	│	│	│	│	├u_dl_uf.t
│	│	│	│	│	├u_jh_va.t
│	│	│	│	│	├u_mn_va.t
│	│	│	│	│	├u_mo_rv.t
│	│	│	│	│	├u_ng_mst.t
│	│	│	│	│	├u_ng_path.t
│	│	│	│	│	├u_ng_scc.t
│	│	│	│	│	├u_rb_cc.t
│	│	│	│	│	├u_re_sd.t
│	│	│	│	│	├u_ro_ra.t
│	│	│	│	│	├u_sc_me.t
│	│	│	│	│	├u_sn_sva.t
│	│	│	│	│	├u_te_ae.t
│	│	│	│	│	├u_te_ea.t
│	│	│	│	│	└u_te_me.t
│	│	│	│	├TODO
│	│	│	│	└<util>
│	│	│	│	  	├cover.sh
│	│	│	│	  	├grand.pl
│	│	│	│	  	├renum.pl
│	│	│	│	  	├size.pl
│	│	│	│	  	└srand.pl
│	│	│	└Graph-0.9704.tar.gz
│	│	├<python>
│	│	│	├anonym.py
│	│	│	├anonym.py.bak
│	│	│	├Ben.py
│	│	│	├Czepiel.py
│	│	│	├dijkstra.py
│	│	│	├DijkstraShortestPathAlgorithm.py
│	│	│	├DijkstraShortestPathAlgorithm.py.bak
│	│	│	├gndemo.py
│	│	│	├graphs.py
│	│	│	├Klein graph2.py
│	│	│	├Klein graph2.py.bak
│	│	│	├marazmiki.py
│	│	│	├marazmiki.py.bak
│	│	│	├metis.py
│	│	│	├mst.py
│	│	│	├prim.py
│	│	│	├Python Software Foundation.py
│	│	│	├Scellato.txt
│	│	│	├shintoishere (2).py
│	│	│	├shintoishere (2).py.bak
│	│	│	├shintoishere.py
│	│	│	├spl0i7.py
│	│	│	├spl0i7.py.bak
│	│	│	├Tschacher.py
│	│	│	├Tschacher.py.bak
│	│	│	├Udacity Creating Network Graphs with Python.docx
│	│	│	├vevurka.py
│	│	│	├vevurka.py.bak
│	│	│	└zzzinfo.txt
│	│	└<ruby>
│	│	  	├<rgl-master>
│	│	  	│	├.codeclimate.yml
│	│	  	│	├.gitignore
│	│	  	│	├.travis.yml
│	│	  	│	├.yardopts
│	│	  	│	├ChangeLog
│	│	  	│	├<examples>
│	│	  	│	│	├canvas.rb
│	│	  	│	│	├examples.rb
│	│	  	│	│	├insel_der_tausend_gefahren.rb
│	│	  	│	│	├<north>
│	│	  	│	│	│	├g.10.0.graphml
│	│	  	│	│	│	├g.10.1.graphml
│	│	  	│	│	│	├g.10.11.graphml
│	│	  	│	│	│	├g.10.12.graphml
│	│	  	│	│	│	├g.10.13.graphml
│	│	  	│	│	│	├g.10.14.graphml
│	│	  	│	│	│	├g.10.15.graphml
│	│	  	│	│	│	├g.10.16.graphml
│	│	  	│	│	│	├g.10.17.graphml
│	│	  	│	│	│	├g.10.19.graphml
│	│	  	│	│	│	├g.10.2.graphml
│	│	  	│	│	│	├g.10.20.graphml
│	│	  	│	│	│	├g.10.22.graphml
│	│	  	│	│	│	├g.10.24.graphml
│	│	  	│	│	│	├g.10.25.graphml
│	│	  	│	│	│	├g.10.27.graphml
│	│	  	│	│	│	├g.10.28.graphml
│	│	  	│	│	│	├g.10.29.graphml
│	│	  	│	│	│	├g.10.3.graphml
│	│	  	│	│	│	├g.10.30.graphml
│	│	  	│	│	│	├g.10.31.graphml
│	│	  	│	│	│	├g.10.34.graphml
│	│	  	│	│	│	├g.10.37.graphml
│	│	  	│	│	│	├g.10.38.graphml
│	│	  	│	│	│	├g.10.39.graphml
│	│	  	│	│	│	├g.10.4.graphml
│	│	  	│	│	│	├g.10.40.graphml
│	│	  	│	│	│	├g.10.41.graphml
│	│	  	│	│	│	├g.10.42.graphml
│	│	  	│	│	│	├g.10.45.graphml
│	│	  	│	│	│	├g.10.46.graphml
│	│	  	│	│	│	├g.10.5.graphml
│	│	  	│	│	│	├g.10.50.graphml
│	│	  	│	│	│	├g.10.56.graphml
│	│	  	│	│	│	├g.10.57.graphml
│	│	  	│	│	│	├g.10.58.graphml
│	│	  	│	│	│	├g.10.6.graphml
│	│	  	│	│	│	├g.10.60.graphml
│	│	  	│	│	│	├g.10.61.graphml
│	│	  	│	│	│	├g.10.62.graphml
│	│	  	│	│	│	├g.10.68.graphml
│	│	  	│	│	│	├g.10.69.graphml
│	│	  	│	│	│	├g.10.7.graphml
│	│	  	│	│	│	├g.10.70.graphml
│	│	  	│	│	│	├g.10.71.graphml
│	│	  	│	│	│	├g.10.72.graphml
│	│	  	│	│	│	├g.10.74.graphml
│	│	  	│	│	│	├g.10.75.graphml
│	│	  	│	│	│	├g.10.78.graphml
│	│	  	│	│	│	├g.10.79.graphml
│	│	  	│	│	│	├g.10.8.graphml
│	│	  	│	│	│	├g.10.80.graphml
│	│	  	│	│	│	├g.10.82.graphml
│	│	  	│	│	│	├g.10.83.graphml
│	│	  	│	│	│	├g.10.85.graphml
│	│	  	│	│	│	├g.10.86.graphml
│	│	  	│	│	│	├g.10.88.graphml
│	│	  	│	│	│	├g.10.89.graphml
│	│	  	│	│	│	├g.10.9.graphml
│	│	  	│	│	│	├g.10.90.graphml
│	│	  	│	│	│	├g.10.91.graphml
│	│	  	│	│	│	├g.10.92.graphml
│	│	  	│	│	│	├g.10.93.graphml
│	│	  	│	│	│	├g.10.94.graphml
│	│	  	│	│	│	├g.12.8.graphml
│	│	  	│	│	│	├g.14.9.graphml
│	│	  	│	│	│	└Graph.log
│	│	  	│	│	├north.rb
│	│	  	│	│	├north2.rb
│	│	  	│	│	└rdep-rgl.rb
│	│	  	│	├Gemfile
│	│	  	│	├<images>
│	│	  	│	│	├example.jpg
│	│	  	│	│	├module_graph.jpg
│	│	  	│	│	└rgl_modules.png
│	│	  	│	├<lib>
│	│	  	│	│	└<rgl>
│	│	  	│	│	  	├adjacency.rb
│	│	  	│	│	  	├base.rb
│	│	  	│	│	  	├bellman_ford.rb
│	│	  	│	│	  	├bidirectional.rb
│	│	  	│	│	  	├bipartite.rb
│	│	  	│	│	  	├condensation.rb
│	│	  	│	│	  	├connected_components.rb
│	│	  	│	│	  	├dijkstra.rb
│	│	  	│	│	  	├dijkstra_visitor.rb
│	│	  	│	│	  	├dot.rb
│	│	  	│	│	  	├edge_properties_map.rb
│	│	  	│	│	  	├edmonds_karp.rb
│	│	  	│	│	  	├graphxml.rb
│	│	  	│	│	  	├graph_iterator.rb
│	│	  	│	│	  	├graph_visitor.rb
│	│	  	│	│	  	├graph_wrapper.rb
│	│	  	│	│	  	├implicit.rb
│	│	  	│	│	  	├mutable.rb
│	│	  	│	│	  	├path_builder.rb
│	│	  	│	│	  	├prim.rb
│	│	  	│	│	  	├rdot.rb
│	│	  	│	│	  	├topsort.rb
│	│	  	│	│	  	├transitivity.rb
│	│	  	│	│	  	├transitiv_closure.rb
│	│	  	│	│	  	└traversal.rb
│	│	  	│	├Rakefile
│	│	  	│	├<rakelib>
│	│	  	│	│	└dep_graph.rake
│	│	  	│	├README.md
│	│	  	│	├rgl.gemspec
│	│	  	│	├<script>
│	│	  	│	│	└test_all
│	│	  	│	└<test>
│	│	  	│	  	├bellman_ford_test.rb
│	│	  	│	  	├bipartite_test.rb
│	│	  	│	  	├components_test.rb
│	│	  	│	  	├cycles_test.rb
│	│	  	│	  	├dijkstra_issue24_test.rb
│	│	  	│	  	├dijkstra_test.rb
│	│	  	│	  	├directed_graph_test.rb
│	│	  	│	  	├dot_test.rb
│	│	  	│	  	├edge_properties_map_test.rb
│	│	  	│	  	├edge_test.rb
│	│	  	│	  	├edmonds_karp_test.rb
│	│	  	│	  	├graph_test.rb
│	│	  	│	  	├graph_xml_test.rb
│	│	  	│	  	├implicit_test.rb
│	│	  	│	  	├prim_test.rb
│	│	  	│	  	├rdot_test.rb
│	│	  	│	  	├test_helper.rb
│	│	  	│	  	├transitivity_test.rb
│	│	  	│	  	├traversal_test.rb
│	│	  	│	  	└undirected_graph_test.rb
│	│	  	└rgl-master.zip
│	├<graph_datastructures_algorithms_codes>
│	│	├<ccppcsharp>
│	│	│	├<lists>
│	│	│	│	├Ajinkya-Sonawane.c
│	│	│	│	├Ajinkya-Sonawane.c.bak
│	│	│	│	├anonym.c
│	│	│	│	├anonym.c.bak
│	│	│	│	├anonym1.c
│	│	│	│	├anonym1.c.bak
│	│	│	│	├arbhie2581.cpp
│	│	│	│	├arbhie2581.cpp.bak
│	│	│	│	├Barnwal.c
│	│	│	│	├Bhojasia.c
│	│	│	│	├Bhojasia.c.bak
│	│	│	│	├Chhabra.cpp
│	│	│	│	├Chhabra.cpp.bak
│	│	│	│	├Coleman.cpp
│	│	│	│	├Coleman.cpp.bak
│	│	│	│	├Daal.cpp
│	│	│	│	├Daal.cpp.bak
│	│	│	│	├Elkan.c
│	│	│	│	├Elkan.c.bak
│	│	│	│	├ferenczi.cpp
│	│	│	│	├geeksforgeeks.cpp
│	│	│	│	├geeksforgeeks.cpp.bak
│	│	│	│	├iokon.cpp
│	│	│	│	├iokon.cpp.bak
│	│	│	│	├Jamal.cpp
│	│	│	│	├Jamal.cpp.bak
│	│	│	│	├Manish.cpp
│	│	│	│	├Manish.cpp.bak
│	│	│	│	├Morris.c
│	│	│	│	├Morris.c.bak
│	│	│	│	├NiclasJonsson.cpp
│	│	│	│	├NiclasJonsson.cpp.bak
│	│	│	│	├quickgrid.cpp
│	│	│	│	├quickgrid.cpp.bak
│	│	│	│	├quickgrid2.cpp
│	│	│	│	├quickgrid2.cpp.bak
│	│	│	│	├quickgrid3.cpp
│	│	│	│	├quickgrid3.cpp.bak
│	│	│	│	├quickgrid4.cpp
│	│	│	│	├quickgrid4.cpp.bak
│	│	│	│	├sanfoundry.cpp
│	│	│	│	├sanfoundry.cpp.bak
│	│	│	│	├Sangam.cpp
│	│	│	│	├Ullman.cpp
│	│	│	│	├Ullman.cpp.bak
│	│	│	│	├Wagner.c
│	│	│	│	├Wagner.c.bak
│	│	│	│	├Wagner1.c
│	│	│	│	└Wagner1.c.bak
│	│	│	├<matrices>
│	│	│	│	├adj-matrix-code.txt
│	│	│	│	├AdjacencyMatrixGraphImp.cpp
│	│	│	│	├AlgoList.cpp
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│	│	│	│	├anonym.cpp
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│	│	│	│	├anonym1.cpp
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│	│	│	│	├anonym2.c
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│	│	│	│	├anonym3.cpp
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│	│	│	│	├cguy3.c
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│	│	│	│	├Daal.cpp
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│	│	│	│	├erip.cpp
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│	│	│	│	├notes.cpp
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│	│	│	│	├Ullman.cpp
│	│	│	│	└Ullman.cpp.bak
│	│	│	└<transformation>
│	│	│	  	├kuruma.cpp
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│	│	│	  	├Ouda.cpp
│	│	│	  	└Ouda.cpp.bak
│	│	├graph_datastructures_algorithms_codes.htm
│	│	├<haskell>
│	│	├<java>
│	│	│	├<lists>
│	│	│	│	├AdjacencyList.java
│	│	│	│	├AdjacencyList.java.bak
│	│	│	│	├AdjacencyListGraph(1).java
│	│	│	│	├AdjacencyListGraph.java
│	│	│	│	├AdjacencyListGraph3.java
│	│	│	│	├AdjListsGraph.java
│	│	│	│	├Anonym1.java
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│	│	│	│	├Anonym4.java
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│	│	│	│	├AnujPrashar.java
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│	│	│	│	├clrs-java.java
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│	│	│	│	├DeepBlackMagic.java
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│	│	│	│	├dharmendra.java.bak
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│	│	│	│	├geeksforgeeks.java
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│	│	│	│	├Glenn.java
│	│	│	│	├Glenn.java.bak
│	│	│	│	├hrishikesh-kumar.java
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│	│	│	│	├Jamal.java
│	│	│	│	├Jamal.java.bak
│	│	│	│	├JavaHopper.java
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│	│	│	│	├javaRancher2009.java
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│	│	│	│	├Sanfoudry.java
│	│	│	│	├Sanfoudry.java.bak
│	│	│	│	├Sanfoundry Java Program to Describe the Representation of Graph using Adjacency List.docx
│	│	│	│	├Sangam.java
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│	│	│	│	├Sean.java.bak
│	│	│	│	├Sedgewick.java
│	│	│	│	├Snipcademy.java.py
│	│	│	│	├Sumitjain.java
│	│	│	│	├Sumitjain.java.bak
│	│	│	│	├Thain.java
│	│	│	│	├Thain.java.bak
│	│	│	│	├Udayanga.java
│	│	│	│	├Udayanga.java.bak
│	│	│	│	├Wagner.java
│	│	│	│	├Wagner.java.bak
│	│	│	│	├Wagner1.java
│	│	│	│	├Wagner1.java.bak
│	│	│	│	└WeightedAdjacencyListGraph.java
│	│	│	├<matrices>
│	│	│	│	├AdjMatrixDiGraph.java
│	│	│	│	├AdjMatrixDiGraph.java.bak
│	│	│	│	├AdjMatrixGraph.java
│	│	│	│	├AdjMatrixGraph.java.bak
│	│	│	│	├AlgoList.java
│	│	│	│	├AlgoList.java.bak
│	│	│	│	├anonym.java
│	│	│	│	├anonym.java.bak
│	│	│	│	├Arndt.java
│	│	│	│	├Arndt.java.bak
│	│	│	│	├cpclass.java
│	│	│	│	├cpclass.java.bak
│	│	│	│	├dharmendra.java
│	│	│	│	├dharmendra.java.bak
│	│	│	│	├eleal.java
│	│	│	│	├eleal.java.bak
│	│	│	│	├GraphMatrix.java
│	│	│	│	├jinwu.java
│	│	│	│	├jinwu.java.bak
│	│	│	│	├Josephine.java
│	│	│	│	├Josephine.java.bak
│	│	│	│	├Manish.java
│	│	│	│	├Manish.java.bak
│	│	│	│	├MasterOdin.java
│	│	│	│	├MasterOdin.java.bak
│	│	│	│	├MatrixGraph.java
│	│	│	│	├myGraph.java
│	│	│	│	├pbesra.java
│	│	│	│	├pbesra.java.bak
│	│	│	│	├Sedgewick.java
│	│	│	│	├Sedgewick.java.bak
│	│	│	│	├someone.java
│	│	│	│	├someone.java.bak
│	│	│	│	└WeightedAdjacencyMatrixGraph.java
│	│	│	└<transformation>
│	│	│	  	├ed.java
│	│	│	  	└ed.java.bak
│	│	├<javascript>
│	│	│	├nivas8292.js
│	│	│	├nivas8292.js.bak
│	│	│	├w8r.js
│	│	│	└w8r.js.bak
│	│	├<lisps>
│	│	├<matlab>
│	│	│	├wanirepo.m
│	│	│	└wanirepo.m.bak
│	│	├<perl>
│	│	├<python>
│	│	│	├<lists>
│	│	│	│	├Abiy.py
│	│	│	│	├Abiy.py.bak
│	│	│	│	├Adjacency_List.py
│	│	│	│	├Adjacency_List.py.bak
│	│	│	│	├Bradfield.py
│	│	│	│	├Bradfield.py.bak
│	│	│	│	├ed.py
│	│	│	│	├ed.py.bak
│	│	│	│	├SQLAlchemy.py
│	│	│	│	├SQLAlchemy.py.bak
│	│	│	│	├theGreatWhatever.py
│	│	│	│	├theGreatWhatever.py.bak
│	│	│	│	├vevurka.py
│	│	│	│	├vevurka.py.bak
│	│	│	│	├yang.py
│	│	│	│	└yang.py.bak
│	│	│	├<matrices>
│	│	│	│	├ajasmar.py
│	│	│	│	├ajasmar.py.bak
│	│	│	│	├anonym.py
│	│	│	│	├anonym.py.bak
│	│	│	│	├anuvrat-tiku.py
│	│	│	│	├anuvrat-tiku.py.bak
│	│	│	│	├Baraa.py
│	│	│	│	├Baraa.py.bak
│	│	│	│	├Bolboa.py
│	│	│	│	├Bolboa.py.bak
│	│	│	│	├chabv.py
│	│	│	│	├chabv.py.bak
│	│	│	│	├exchez.py
│	│	│	│	├exchez.py.bak
│	│	│	│	├Hagberg.py
│	│	│	│	├JohanL.py
│	│	│	│	├JohanL.py.bak
│	│	│	│	├Manuel.py
│	│	│	│	├Manuel.py.bak
│	│	│	│	├NetworkX.py
│	│	│	│	├NetworkX.py.bak
│	│	│	│	├riccamastellone.py
│	│	│	│	├riccamastellone.py.bak
│	│	│	│	├scipy.txt
│	│	│	│	├tmsss.py
│	│	│	│	├tmsss.py.bak
│	│	│	│	├Toriyama.py
│	│	│	│	├Toriyama.py.bak
│	│	│	│	├toy.py
│	│	│	│	├toy.py.bak
│	│	│	│	├wjrl.py
│	│	│	│	├wjrl.py.bak
│	│	│	│	├<workhorse>
│	│	│	│	│	├bOOaa.png
│	│	│	│	│	└S9Dcx.png
│	│	│	│	└Workhorse.docx
│	│	│	└<transformation>
│	│	│	  	├Adrian.py
│	│	│	  	├Adrian.py.bak
│	│	│	  	├anonym.py
│	│	│	  	├anonym.py.bak
│	│	│	  	├anonym1.py
│	│	│	  	├anonym1.py.bak
│	│	│	  	├ed.py
│	│	│	  	├ed.py.bak
│	│	│	  	├Koledoye.py
│	│	│	  	├Koledoye.py.bak
│	│	│	  	├mpgn.py
│	│	│	  	├mpgn.py.bak
│	│	│	  	├Nepusz.py
│	│	│	  	├Nepusz.py.bak
│	│	│	  	├rupalbarman.py
│	│	│	  	├rupalbarman.py.bak
│	│	│	  	├talesa.py
│	│	│	  	└talesa.py.bak
│	│	├<ruby>
│	│	│	├<rgl-master>
│	│	│	│	├.codeclimate.yml
│	│	│	│	├.gitignore
│	│	│	│	├.travis.yml
│	│	│	│	├.yardopts
│	│	│	│	├ChangeLog
│	│	│	│	├<examples>
│	│	│	│	│	├canvas.rb
│	│	│	│	│	├examples.rb
│	│	│	│	│	├insel_der_tausend_gefahren.rb
│	│	│	│	│	├<north>
│	│	│	│	│	│	├g.10.0.graphml
│	│	│	│	│	│	├g.10.1.graphml
│	│	│	│	│	│	├g.10.11.graphml
│	│	│	│	│	│	├g.10.12.graphml
│	│	│	│	│	│	├g.10.13.graphml
│	│	│	│	│	│	├g.10.14.graphml
│	│	│	│	│	│	├g.10.15.graphml
│	│	│	│	│	│	├g.10.16.graphml
│	│	│	│	│	│	├g.10.17.graphml
│	│	│	│	│	│	├g.10.19.graphml
│	│	│	│	│	│	├g.10.2.graphml
│	│	│	│	│	│	├g.10.20.graphml
│	│	│	│	│	│	├g.10.22.graphml
│	│	│	│	│	│	├g.10.24.graphml
│	│	│	│	│	│	├g.10.25.graphml
│	│	│	│	│	│	├g.10.27.graphml
│	│	│	│	│	│	├g.10.28.graphml
│	│	│	│	│	│	├g.10.29.graphml
│	│	│	│	│	│	├g.10.3.graphml
│	│	│	│	│	│	├g.10.30.graphml
│	│	│	│	│	│	├g.10.31.graphml
│	│	│	│	│	│	├g.10.34.graphml
│	│	│	│	│	│	├g.10.37.graphml
│	│	│	│	│	│	├g.10.38.graphml
│	│	│	│	│	│	├g.10.39.graphml
│	│	│	│	│	│	├g.10.4.graphml
│	│	│	│	│	│	├g.10.40.graphml
│	│	│	│	│	│	├g.10.41.graphml
│	│	│	│	│	│	├g.10.42.graphml
│	│	│	│	│	│	├g.10.45.graphml
│	│	│	│	│	│	├g.10.46.graphml
│	│	│	│	│	│	├g.10.5.graphml
│	│	│	│	│	│	├g.10.50.graphml
│	│	│	│	│	│	├g.10.56.graphml
│	│	│	│	│	│	├g.10.57.graphml
│	│	│	│	│	│	├g.10.58.graphml
│	│	│	│	│	│	├g.10.6.graphml
│	│	│	│	│	│	├g.10.60.graphml
│	│	│	│	│	│	├g.10.61.graphml
│	│	│	│	│	│	├g.10.62.graphml
│	│	│	│	│	│	├g.10.68.graphml
│	│	│	│	│	│	├g.10.69.graphml
│	│	│	│	│	│	├g.10.7.graphml
│	│	│	│	│	│	├g.10.70.graphml
│	│	│	│	│	│	├g.10.71.graphml
│	│	│	│	│	│	├g.10.72.graphml
│	│	│	│	│	│	├g.10.74.graphml
│	│	│	│	│	│	├g.10.75.graphml
│	│	│	│	│	│	├g.10.78.graphml
│	│	│	│	│	│	├g.10.79.graphml
│	│	│	│	│	│	├g.10.8.graphml
│	│	│	│	│	│	├g.10.80.graphml
│	│	│	│	│	│	├g.10.82.graphml
│	│	│	│	│	│	├g.10.83.graphml
│	│	│	│	│	│	├g.10.85.graphml
│	│	│	│	│	│	├g.10.86.graphml
│	│	│	│	│	│	├g.10.88.graphml
│	│	│	│	│	│	├g.10.89.graphml
│	│	│	│	│	│	├g.10.9.graphml
│	│	│	│	│	│	├g.10.90.graphml
│	│	│	│	│	│	├g.10.91.graphml
│	│	│	│	│	│	├g.10.92.graphml
│	│	│	│	│	│	├g.10.93.graphml
│	│	│	│	│	│	├g.10.94.graphml
│	│	│	│	│	│	├g.12.8.graphml
│	│	│	│	│	│	├g.14.9.graphml
│	│	│	│	│	│	└Graph.log
│	│	│	│	│	├north.rb
│	│	│	│	│	├north2.rb
│	│	│	│	│	└rdep-rgl.rb
│	│	│	│	├Gemfile
│	│	│	│	├<images>
│	│	│	│	│	├example.jpg
│	│	│	│	│	├module_graph.jpg
│	│	│	│	│	└rgl_modules.png
│	│	│	│	├<lib>
│	│	│	│	│	└<rgl>
│	│	│	│	│	  	├adjacency.rb
│	│	│	│	│	  	├base.rb
│	│	│	│	│	  	├bellman_ford.rb
│	│	│	│	│	  	├bidirectional.rb
│	│	│	│	│	  	├bipartite.rb
│	│	│	│	│	  	├condensation.rb
│	│	│	│	│	  	├connected_components.rb
│	│	│	│	│	  	├dijkstra.rb
│	│	│	│	│	  	├dijkstra_visitor.rb
│	│	│	│	│	  	├dot.rb
│	│	│	│	│	  	├edge_properties_map.rb
│	│	│	│	│	  	├edmonds_karp.rb
│	│	│	│	│	  	├graphxml.rb
│	│	│	│	│	  	├graph_iterator.rb
│	│	│	│	│	  	├graph_visitor.rb
│	│	│	│	│	  	├graph_wrapper.rb
│	│	│	│	│	  	├implicit.rb
│	│	│	│	│	  	├mutable.rb
│	│	│	│	│	  	├path_builder.rb
│	│	│	│	│	  	├prim.rb
│	│	│	│	│	  	├rdot.rb
│	│	│	│	│	  	├topsort.rb
│	│	│	│	│	  	├transitivity.rb
│	│	│	│	│	  	├transitiv_closure.rb
│	│	│	│	│	  	└traversal.rb
│	│	│	│	├Rakefile
│	│	│	│	├<rakelib>
│	│	│	│	│	└dep_graph.rake
│	│	│	│	├README.md
│	│	│	│	├rgl.gemspec
│	│	│	│	├<script>
│	│	│	│	│	└test_all
│	│	│	│	└<test>
│	│	│	│	  	├bellman_ford_test.rb
│	│	│	│	  	├bipartite_test.rb
│	│	│	│	  	├components_test.rb
│	│	│	│	  	├cycles_test.rb
│	│	│	│	  	├dijkstra_issue24_test.rb
│	│	│	│	  	├dijkstra_test.rb
│	│	│	│	  	├directed_graph_test.rb
│	│	│	│	  	├dot_test.rb
│	│	│	│	  	├edge_properties_map_test.rb
│	│	│	│	  	├edge_test.rb
│	│	│	│	  	├edmonds_karp_test.rb
│	│	│	│	  	├graph_test.rb
│	│	│	│	  	├graph_xml_test.rb
│	│	│	│	  	├implicit_test.rb
│	│	│	│	  	├prim_test.rb
│	│	│	│	  	├rdot_test.rb
│	│	│	│	  	├test_helper.rb
│	│	│	│	  	├transitivity_test.rb
│	│	│	│	  	├traversal_test.rb
│	│	│	│	  	└undirected_graph_test.rb
│	│	│	└rgl-master.zip
│	│	├<scilab>
│	│	│	├benjaminBoboul.sce
│	│	│	└benjaminBoboul.sce.bak
│	│	└<swift>
│	│	  	├larryfox.swift
│	│	  	├larryfox.swift.bak
│	│	  	├raywenderlich.swift
│	│	  	└raywenderlich.swift.bak
│	└<graph_soft>
│	  	└0000graph_softtools.htm
├<000graph_datastructures_representation>
│	├<graph_datastructures_details>
│	│	├000graph_datastructures_detailsIntro.htm
│	│	├<algorithms>
│	│	├<arrays>
│	│	├<domains>
│	│	├graph_datastructures_details - 副本.htm
│	│	├graph_datastructures_details.htm
│	│	├graph_datastructures_detailsAlgorithms.htm
│	│	├graph_datastructures_detailsArrays.htm
│	│	├graph_datastructures_detailsDictionary.htm
│	│	├graph_datastructures_detailsDomains.htm
│	│	├graph_datastructures_detailsHybrid.htm
│	│	├graph_datastructures_detailsImplicit.htm
│	│	├graph_datastructures_detailsIndices.htm
│	│	├graph_datastructures_detailsLists.htm
│	│	├graph_datastructures_detailsMaps.htm
│	│	├graph_datastructures_detailsMatrices.htm
│	│	├graph_datastructures_detailsObjects.htm
│	│	├graph_datastructures_detailsPolynomials.htm
│	│	├graph_datastructures_detailsPrintable.htm
│	│	├graph_datastructures_detailsRows.htm
│	│	├graph_datastructures_detailsRules.htm
│	│	├graph_datastructures_detailsSequence.htm
│	│	├graph_datastructures_detailsSets.htm
│	│	├graph_datastructures_detailsStar.htm
│	│	├graph_datastructures_detailsTables.htm
│	│	├graph_datastructures_detailsVectors.htm
│	│	├<hybrid>
│	│	├<implicit>
│	│	│	└Sampath Kannan Implicat Representation of Graphs.docx
│	│	├<indices>
│	│	├<lists>
│	│	├<maps>
│	│	│	├Amit Patel Map representations.docx
│	│	│	└Ethan Using a Map for a Graph.docx
│	│	├<matrices>
│	│	├<objects>
│	│	│	└Kat Object and Pointer Graph representations.docx
│	│	├<polynomials>
│	│	├<printables>
│	│	├<rows>
│	│	│	├burkardt  Compressed Row (CR) Sparse Matrix File Format.docx
│	│	│	├Cheuk Compressed Row Storage.docx
│	│	│	├GNU Scientific Library – Reference Manual  Sparse Matrices Compressed Format.htm
│	│	│	├Jack Dongarra Compressed Row Storage.docx
│	│	│	├Scipy lecture Compressed Sparse Row Format (CSR).docx
│	│	│	├Sparse Matrix Compression Formats.htm
│	│	│	└SumNeuron Matrix Compression.docx
│	│	├<rules>
│	│	├<sequences>
│	│	├<sets>
│	│	├<stars>
│	│	├<tables>
│	│	└<vectors>
│	│	  	├Annamalai Representing graph as a vector.docx
│	│	  	├aroup Adjacency list Graph representation using vector and pair.docx
│	│	  	├David Corneliusen How can I create an adjacency matrix using vectors in a templated graph class in c.docx
│	│	  	├hubbu Making Adjacency List with Vectors.docx
│	│	  	└Parsons Vector representations of graphs.docx
│	├<graph_datastructures_literature>
│	│	├graph_datastructures_literature - 副本 (3).htm
│	│	├graph_datastructures_literature0.htm
│	│	├graph_datastructures_literatureA.htm
│	│	├graph_datastructures_literatureB.htm
│	│	├graph_datastructures_literatureC.htm
│	│	├graph_datastructures_literatureD.htm
│	│	├graph_datastructures_literatureE.htm
│	│	├graph_datastructures_literatureF.htm
│	│	├graph_datastructures_literatureG.htm
│	│	├graph_datastructures_literatureH.htm
│	│	├graph_datastructures_literatureI.htm
│	│	├graph_datastructures_literatureJ.htm
│	│	├graph_datastructures_literatureK.htm
│	│	├graph_datastructures_literatureL.htm
│	│	├graph_datastructures_literatureM.htm
│	│	├graph_datastructures_literatureN.htm
│	│	├graph_datastructures_literatureO.htm
│	│	├graph_datastructures_literatureP.htm
│	│	├graph_datastructures_literatureQ.htm
│	│	├graph_datastructures_literatureR.htm
│	│	├graph_datastructures_literatureS.htm
│	│	├graph_datastructures_literatureT.htm
│	│	├graph_datastructures_literatureU.htm
│	│	├graph_datastructures_literatureV.htm
│	│	├<graph_datastructures_literatureW>
│	│	│	└<Wagner2012>
│	│	│	  	├adjlist5.png
│	│	│	  	├capitals_smaller.gif
│	│	│	  	└capsnum.gif
│	│	├graph_datastructures_literatureW.htm
│	│	├graph_datastructures_literatureX.htm
│	│	├graph_datastructures_literatureY.htm
│	│	└graph_datastructures_literatureZ.htm
│	└<graph_datastructures_pdfpptdocx>
│	  	├Abiy Graph implementation and representation.docx
│	  	├Abu-Khzam A Hybrid Graph Representation for Exact Graph Algorithms p15.pdf
│	  	├Abu-Khzam A Hybrid Graph Representation for Recursive Backtracking Algorithms p12.pdf
│	  	├AHUJA Network Flows Theory, Algorithms, and Applications Ch1_3 p103.pdf
│	  	├AlgoList Undirected graphs representation.docx
│	  	├Amar Majority-Inverter Graph A Novel Data-Structure and Algorithms for Efficient Logic Optimization p6.pdf
│	  	├Appel An Alternate Graph Representation for the Tiger Compiler.docx
│	  	├Arikati Efficient computation of implicit representations of sparse graphs p16.pdf
│	  	├Atminas Implicit Representations and Factorial Properties of Graphs p28.pdf
│	  	├Barnes Graphs.pdf
│	  	├Barnwal Graph and its representations.docx
│	  	├Barták Graphs in Prolog.docx
│	  	├Basel Elementary Graph Algorithms PART-1 p34.pdf
│	  	├Beard Comparing object graph representation to adjacency list and matrix representations.docx
│	  	├Benoit Representing trees of higher degree p12.pdf
│	  	├Berkeley — Graph representations.docx
│	  	├Blelloch Lecture 13 — Shortest Weighted Paths p8.pdf
│	  	├Blelloch Lecture 7 Graph Representations Sets and Tables p11.pdf
│	  	├Bogner Feynman graph polynomials p35.pdf
│	  	├Boost Graph Library  Adjacency List - develop.docx
│	  	├Boost Graph Library  Adjacency Matrix - 1.51.0.docx
│	  	├Brabec Procedural Code Representation in a Flow Graph p12.pdf
│	  	├Braun FIRM A Graph-Based Intermediate Representation p8.pdf
│	  	├Brisaboa Compact Representation of Web Graphs with Extended Functionality p33.pdf
│	  	├Brisaboa K2trees for Compact Web Graph Representation p10.pdf
│	  	├Btechsmartclass Graph Representations.docx
│	  	├Buesser New Adjacency List and Multiplicity.pptx
│	  	├Buriol Web Graph representation and compression.ppt
│	  	├Burkardt GRAPH_REPRESENTATION.docx
│	  	├Cao Deep Neural Networks for Learning Graph Representations p8.pdf
│	  	├Catherine Clustering the Graph Representation of Data p26.pdf
│	  	├Chen Analysis of Algorithms I Graph Representation and BFS p41.pdf
│	  	├Chen EAGER Define and Construct an Enhanced Graph Representation for Multiscale Vector Field Data Summarization.docx
│	  	├Claude A Fast and CompactWeb Graph Representation p12.pdf
│	  	├CLAUDE Fast and Compact Web Graph Representations p30.pdf
│	  	├Codish Breaking Symmetries in Graph Representation p7.pdf
│	  	├COMPSCI Part 1 Graphs and Adjacency Matrices.pdf
│	  	├Cormen Representing graphs.docx
│	  	├Corn Adjacency Matrix.docx
│	  	├Cornell Lecture 21 Graph Representations and Traversals.docx
│	  	├Costantini Comparing different graph representations of logic programs under the Answer Set semantics p6.pdf
│	  	├CPLEX LP format.pdf
│	  	├Curtis An Implicit Representation of Chordal Comparabilty Graphs in Linear-time p14.pdf
│	  	├D'Autilia Shaping ideal cities the graph representation of the urban utopia p17.pdf
│	  	├de Greef Lecture 15 - Graph Data Structures and Traversals p37.pdf
│	  	├Deepa Data Structure for Graphs p4.pdf
│	  	├Depree Graph Operations And Representation p34 (2).pdf
│	  	├Depree Graph Operations And Representation p34.pdf
│	  	├Dezso LEMON – an Open Source C++ Graph Template Library1.pdf
│	  	├Dong Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance p67.pdf
│	  	├Du Lecture 3 Graph Representation for Regular Expressions p26.ppt
│	  	├Dvorak A dynamic data structure for counting subgraphs in sparse graphs p27.pdf
│	  	├Ediger STINGER High Performance Data Structure for Streaming Graphs p5.pdf
│	  	├Egyhazy On implementing graph representation p23.pdf
│	  	├Elite Graph Representation p27.pdf
│	  	├Ellis-Monaghan Graph Polynomials and Their Applications I The Tutte Polynomial p42.pdf
│	  	├Emms A matrix representation of graphs and its spectrum as a graph invariant p14.pdf
│	  	├ERDOS THE REPRESENTATION OF A GRAPH BY SET INTERSECTIONS p7.pdf
│	  	├Figueroa Tracking soccer players using the graph representation p4.pdf
│	  	├Gaillarda Graph representation of synonymy and translation resources for cross-linguistic modelisation of meaning p12.pdf
│	  	├Gansner GMap Visualizing Graphs and Clusters as Maps p8.pdf
│	  	├García Compact and Efficient Representations of Graphs p301.pdf
│	  	├Gavoille Shorter Implicit Representation for Planar Graphs and Bounded Treewidth Graphs p12.pdf
│	  	├Gkirtzou The Pyramid Quantized Weisfeiler-Lehman Graph Representation p17.pdf
│	  	├Goodrich Data Structures and Algorithms Introducing Graphs p9.pdf
│	  	├Gotshalks Graph Representation p12.pdf
│	  	├Grama Graph Algorithms p65.pdf
│	  	├GRAPH FILE FORMATS.pdf
│	  	├Graph Representation (2).pdf
│	  	├Graph Representation.pdf
│	  	├Graph Representation1.pdf
│	  	├graph_representation.pdf
│	  	├Gross Section 8.3 Graph Representations and Graph Isomorphism p11.pdf
│	  	├Hackerearth Graph Representation.docx
│	  	├Heap  Graph representation .docx
│	  	├Hedstrom Graph representation.docx
│	  	├Heissan Some Results on Graph Representations and Graph Colorings p60.pdf
│	  	├Hernandez Compressed Representation of Web and Social Networks via Dense Subgraphs p12.pdf
│	  	├Huan Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based acking Motifs p12.pdf
│	  	├HUAN Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based Packing Motifs p15.pdf
│	  	├Hugue Lecture 22 Graphs Representations and BFS.pdf
│	  	├Iglesias Graph representation of documents content and its suitability for text mining tasks p72.pdf
│	  	├Incidence tables of graphs.pdf
│	  	├Jampani Simultaneous Graph Representation Problems p94.pdf
│	  	├Joy A Standard for a Graph Representation for Functional Programs p8.pdf
│	  	├Kannan Implicit Representation of Graphs p11.pdf
│	  	├Kapanowski Weighted Graph Algorithms with Python p13.pdf
│	  	├Kapanowski Weighted graph algorithms with Python p26.pdf
│	  	├Kehr Genome alignment with graph data structures a comparison.docx
│	  	├Kenrick Implementing a Graph p29.pdf
│	  	├Kirsh An Implementation and Analysis of the Skip Graph Data Structure p12.pdf
│	  	├Kobler Interval graph representation with given interval and intersection lengths p10.pdf
│	  	├Kolter Graphs and Networks.pdf
│	  	├KOZA COMPRESSED MULTI-ROW STORAGE FORMAT FOR SPARSE MATRICES ON GRAPHICS PROCESSING UNITS p26.pdf
│	  	├Kudase A Brief Study of Graph Data Structure p5.pdf
│	  	├Kuhnert Space Efficient Algorithms for Graph Isomorphism and Representation p117.pdf
│	  	├Kumar Improved Algorithms and Data Structures for Solving Graph Problems in External Memories p34.pdf
│	  	├K?bler Interval graph representation with given interval and intersection lengths p11.pdf
│	  	├K?bler Interval Graph Representation with Given Interval and Intersection Lengths p13.pdf
│	  	├L18Graphs.pdf
│	  	├Lawlor Introduction to Graph Algorithms p8.pdf
│	  	├Lehmann Implementing Graph Query Languages over Compressed Data Structures A Progress Report p5.pdf
│	  	├Lei?a A Graph-Based Higher-Order Intermediate Representation p11.pdf
│	  	├Lenharth Graph Representations p5.pdf
│	  	├Loerch An Introduction to Graph Algorithms p46.pdf
│	  	├Lovasz Geometric Representations of Graphs p213.pdf
│	  	├Madduri Compact Graph Representations and Parallel Connectivity Algorithms for Massive Dynamic Network Analysis p11.pdf
│	  	├Madduri Scaling up graph algorithms on emerging multicore systems p22.pdf
│	  	├Maiya Visually Pleasing Graph Representation Using GraphDraw.docx
│	  	├Manchester Graph Representation and Traversal.docx
│	  	├Manevich Synthesizing Concurrent Graph Data Structures A Case Study p14.pdf
│	  	├Martin Graph Theory and Social Networks p148.pdf
│	  	├Matas The color adjacency graph of multi-coloured objects p18.pdf
│	  	├Mehlhorn Data Structures and Algorithms The Basic Toolbox - 8 Graph Representations p8.pdf.pdf
│	  	├Montes Graph Representation for Program Evolution an Overview p32.pdf
│	  	├Moore Introduction to Graphs p9.pdf
│	  	├Morris Graph Representations.docx
│	  	├Munro Dynamic Data Structures for Document Collections and Graphs p13.pdf
│	  	├Nanda Lecture 11 Graphs and their Adjacency Matrices p6.pdf
│	  	├NetworkGraph Theory Graph-based representations p13.pdf
│	  	├networkx_reference.pdf
│	  	├OJJ GRAPH REPRESENTATION.docx
│	  	├Okie Graphs - Terminology and Representation.docx
│	  	├Opendatastructures 12.2 AdjacencyLists A Graph as a Collection of Lists.docx
│	  	├opendatastructures.org.docx
│	  	├ORLIN DYNAMIC NETWORK FLOWS p115.pdf
│	  	├PageRank-Project.pdf
│	  	├Pahikkala Graph Kernels versus Graph Representations a Case Study in Parse Ranking p8.pdf
│	  	├Papadimitriou Combinatorial Algorithms & Data Structures Spring 2003 p9.pdf
│	  	├Park Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation p4.pdf
│	  	├Park Basic Graph Algorithms p38.pdf
│	  	├Patty Math 639, Compressed Row Storage (CRS) Format for Sparse Matrices p24.pdf
│	  	├Pfenning Lecture 23 Notes Representing Graphs.pdf
│	  	├Phukon The Composite Graph Model for Web Document and its Impacts on Graph Distance Measurement p8.pdf
│	  	├Piana A graph representation of basic macroeconomic scheme p27.pdf
│	  	├Picard Coinductive Graph Representation p64.pdf
│	  	├Picard Permutations in Coinductive Graph Representation p20.pdf
│	  	├Pisanski Graph representation.ppt
│	  	├Popov Algorithm of the Week Graphs and Their Representation.docx
│	  	├Popov Computer Algorithms Graphs and their Representation.docx
│	  	├PSF Python Patterns - Implementing Graphs.docx
│	  	├Rahman Implicit Representation of Graphs p42.pdf
│	  	├Rao Graph p19.pdf
│	  	├Reid-Miller Lecture 10 — Shortest Weighted Paths I p6.pdf
│	  	├Review on Graphs.pdf
│	  	├Rocca The giRaph package for graph representation in R p1.pdf
│	  	├Rotta Graph Representation.docx
│	  	├Rougier Implicit and Explicit Representations p17.pdf
│	  	├Rudich Implicit Representation of Graphs p12.pdf
│	  	├Sangam.docx
│	  	├Sb?rlea DFGR an Intermediate Graph Representation for Macro-Dataflow Programs p8.pdf
│	  	├Schwarz Graph Representations and Algorithms p164 (2).pdf
│	  	├Schwarz Graph Representations and Algorithms p164.pdf
│	  	├Sedziwy Effective graph representation p13.pdf
│	  	├Seibert Learning Aspect Graph Representations from View Sequences p8.pdf
│	  	├Shaffer graph.java.pdf
│	  	├Shai Transforming Engineering Problems through Graph Representations p28.pdf
│	  	├Shaia Graph theory representations of engineering systems and their embedded knowledge p13.pdf
│	  	├Shkotin Graph representation of context-free grammars p4.pdf
│	  	├Sidere Vector Representation of Graphs Application to the Classification of Symbols and Letters p6.pdf
│	  	├Siek Review of Elementary Graph Theory.docx
│	  	├Singh Role of Adjacency Matrix & Adjacency List in Graph Theory p5.pdf
│	  	├Situngkir Small World Network of Athletes Graph Representation of the World Professional Tennis Player p13.pdf
│	  	├Slesarenko How to select the best graph representation for a given task p18.pdf
│	  	├Sommer 8.1 Graph Representation in Memory p14.pdf
│	  	├Sowa Conceptual Graphs p26.pdf
│	  	├Stratis Graph Representation of Concurrent Programs in C++ p50.pdf
│	  	├Suanfazu Comparing object graph representation to adjacency list and matrix representations.docx
│	  	├Suanfazu Comparing object graph representation to adjacency list and matrix representations1.docx
│	  	├Sumitjain Graph Representation — Adjacency Matrix and Adjacency List.docx
│	  	├Tangwongsan Lecture 7 — Graph Representations, Sets, and Tables p11.pdf
│	  	├Thomas Pathfinding.pdf
│	  	├Thomsen Adjacency matrix code visualizer.docx
│	  	├Tilstra COMPARING MATRIX-BASED AND GRAPH-BASED REPRESENTATIONS FOR PRODUCT DESIGN p6.pdf
│	  	├Trinks Graph Polynomials and Their Representations p122.pdf
│	  	├Ullman Foundations of Computer Science CHAPTER 9 The Graph Data Model p78.pdf
│	  	├Wagner Graph Representation.docx
│	  	├Wang Handwritten Word Spotting Based on Graph Representation p13.pdf
│	  	├Wang Large-Scale Graph Processing Algorithms on the GPU p16.pdf
│	  	├Wang Text-Enhanced Representation Learning for Knowledge Graph p7.pdf
│	  	├Wolfram Graph Construction & Representation.docx
│	  	├Wu Structural Opinion Mining for Graph-based Sentiment Representation p10.pdf
│	  	├Xirouhakis an efficient graph representation p6.pdf
│	  	├Yin W-graph representations for Coxeter groups and Hecke algebras p101.pdf
│	  	├Zanibbi Graph Representations p2.pdf
│	  	├Zeps How to draw combinatorial map From graphs and edges to corner rotations and permutations p20.pdf
│	  	├Zewi VECTOR REPRESENTATION OF GRAPH DOMINATION p21.pdf
│	  	├Zewi Vector Representation of Graph Domination p66.pdf
│	  	├Zhao Semantic Single Video Segmentation with Robust Graph Representation p7.pdf
│	  	└ZZZtest.txt
├<000graph_embedding>
│	├<07tech>
│	│	├algorithms.htm
│	│	├algotechothers.htm
│	│	└<vvvgraphchi-cpp-master>
│	│	  	└<toolkits>
│	│	  	  	└<collaborative_filtering>
│	├applications.htm
│	├embedding_vlsi.htm
│	├embedding_vlsi_researchplan.htm
│	├features.htm
│	├graph_laplacian.htm
│	└tech.html
├<000graph_embedding_02synonym>
│	├0000synonym.txt
│	├definition.htm
│	├Geometric Graph Theory.txt
│	├<geometric_graph_theory>
│	│	├Ackerman On the light side of geometric graphs p6.pdf
│	│	├Pach The Beginnings of Geometric Graph Theory p20.pdf
│	│	└Toth Universality in Geometric Graph Theory p96.pdf
│	├geometric_graph_theory.htm
│	├<graph_capturing>
│	│	└Furlinger Capturing and Visualizing Event Flow Graphs of MPI Applications p10.pdf
│	├<graph_compilation>
│	│	├Alcazar A SAT Compilation of the Landmark Graph p8.pdf
│	│	└Kelly Compilation of XSLT into Data ow Graphs forWeb Service Composition p9.pdf
│	├graph_compilation.htm
│	├<graph_construction>
│	│	├Hong Graph Construction and Analysis as a Paradigm for Plan Recognition p6.pdf
│	│	├Khoreva Classifier Based Graph Construction for Video Segmentation p10.pdf
│	│	├Kim Degree-based graph construction p12.PDF
│	│	├Liu Large Graph Construction for Scalable Semi-Supervised Learning p8.pdf
│	│	├MIZUNO The construction of a regular graph p31.pdf
│	│	├Musco Graph Construction Through Laplacian Function Optimization p32.pdf
│	│	├Saito Lecture 10 Graph Construction from Given Datasets p93.pdf
│	│	└Wang Fast Graph Construction Using Auction Algorithm p10.pdf
│	├graph_construction.htm
│	├<graph_creation>
│	│	├Kumar Creating Graph Abstractions for the Interpretation of Combined Functional and Anatomical Medical Images p10.pdf
│	│	└Posner Creating a Network Graph with Gephi p16.pdf
│	├graph_creation.htm
│	├<graph_drawing>
│	│	├BARAHIMI WEB-BASED DRAWING SOFTWARE FOR GRAPHS IN 3D AND TWO LAYOUT ALGORITHMS p72.pdf
│	│	├Battista Algorithms for Drawing Graphs an Annotated Bibliography p44.pdf
│	│	├Brandenburg Selected Open Problems in Graph Drawing p20.pdf
│	│	├Bridgeman Techniques and Tools for Graph Drawing p168.pdf
│	│	├Chiba Drawing Plane Graphs Nicely p15.pdf
│	│	├Cruz Graph Drawing Tutorial p107.pdf
│	│	├Dujmovic Track Layouts of Graphs p160.pdf
│	│	├Eades How to Draw a Graph Revisited p191.pdf
│	│	├Eades Straight-Line Drawing Algorithms for Hierarchical Graphs and Clustered Graphs p34.pdf
│	│	├Eades Symmetric Graph Drawing p28.pdf
│	│	├El-Sayeda Study of Neural Network Algorithm for Straight-Line Drawings of Planar Graphs p7.pdf
│	│	├Feng Coherent Time-Varying Graph Drawing with Multifocus Context Interaction p12.pdf
│	│	├Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│	│	├FRUCHTERMAN Graph Drawing by Force-directed Placement p36.pdf
│	│	├Godiya Rapid Multipole Graph Drawing on the GPU p12.pdf
│	│	├Harel Graph Drawing by High-Dimensional Embedding p20.pdf
│	│	├Kant Algorithms for Drawing Planar Graphs p237.pdf
│	│	├Klau Quasi–Orthogonal Drawing of Planar Graphs p15.pdf
│	│	├Krug New Approaches on Octilinear Graph Drawing p165.pdf
│	│	├Mumford Drawing Graphs for Cartographic Applications p144.pdf
│	│	├M?kinen GENETIC ALGORITHMS FOR DRAWING BIPARTITE GRAPHS p15.pdf
│	│	├Radwan Hybrid GA for Straight-Line Drawings of Level Clustered Planar Graphs p7.pdf
│	│	├Ruegg Using One-Dimensional Compaction for Smaller Graph Drawings p23.pdf
│	│	├Samaranayake Force Directed Graph Drawing Algorithms for Macro Cell Placement p6.pdf
│	│	├Siebenhaller Orthogonal Graph Drawing with Constraints Algorithms and Applications p222.pdf
│	│	├Sim Automatic Graph Drawing Algorithms p16.pdf
│	│	├Six Techniques for the Refinement of Orthogonal Graph Drawings p29.pdf
│	│	├Tamassia Graph Drawing p10.pdf
│	│	└Wood Drawings of Graphs in Two and Three Dimensions p53.pdf
│	├graph_drawing.htm
│	├graph_drawing.txt
│	├<graph_editing>
│	│	├Andersen GraphShop An Interactive Software Environment for Graph Theory Research and Applications p50.pdf
│	│	├Berry Software and Algorithms for Graph Queries on Massively Multithreaded Architectures p32.pdf
│	│	├Ellson Graphviz and Dynagraph – Static and Dynamic Graph Drawing Tools p23.pdf
│	│	├Heiner Snoopy - A tool to design and execute graph based formalisms p11.pdf
│	│	├Lasinger Overview of Existing Software Tools for Graph Matching p10.pdf
│	│	├Lundqvist BOS A task-graph processing software framework for the Epiphany many-core architecture p4.pdf
│	│	├MathGVdirections.doc
│	│	├Patel Using SASGRAPH? Software to Create Graphs on the Web p10.pdf
│	│	└Tian TALE A Tool for Approximate Large Graph Matching p10.pdf
│	├<graph_encoding>
│	│	├Dagstuhl Graph encoding an overview p24.pdf
│	│	├Das Succinct Encodings of Graph Isomorphism p17.pdf
│	│	├Ionicioiu Encoding graphs into quantum states an axiomatic approach p33.pdf
│	│	├Pouly A Modeling and Encoding Method for Relative Layout Generation and Optimization in Manufacturing p34.pdf
│	│	└Urbania KOGNAC Efficient Encoding of Large Knowledge Graphs p8.pdf
│	├graph_encoding.htm
│	├<graph_extraction>
│	│	├Atkinson Accurate Call Graph Extraction of Programs with Function Pointers Using Type Signatures p10.pdf
│	│	└Vallerio Task Graph Extraction for Embedded System Synthesis p7.pdf
│	├graph_extraction.htm
│	├<graph_generation>
│	│	├Ahmad A Technique for Reachability Graph Generation for the Petri Net Models of Parallel Processes p5.pdf
│	│	├APPENDIX B GRAPH GENERATION AND COMPLEXITY MEASURES p8 .pdf
│	│	├Ashish A Modular Approach to Random Task Graph Generation p7.pdf
│	│	├Bader GTgraph A Synthetic Graph Generator Suite p4.pdf
│	│	├Bailey Automatic Generation of Graph Models for Complex Networks by Genetic Programming p8.pdf
│	│	├Cordeiro Random graph generation for scheduling simulations p10.pdf
│	│	├Coxon Uniform Random Generation of Graphs with Graph Grammars p50.pdf
│	│	├Cullum PERFORMANCE ANALYSIS OF AUTOMATED ATTACK GRAPH GENERATION SOFTWARE p159.pdf
│	│	├Dick Task graph for free p6.pdf
│	│	├ESTERLE Socio-Economic Vision Graph Generation and Handover in Distributed Smart Camera Networks p24.pdf
│	│	├EVERETS ASSEMBLY LANGUAGE REPRESENTATION AND GRAPH GENERATION IN A PURE FUNCTIONAL PROGRAMMING LANGUAGE p108.pdf
│	│	├Fernandez Minimal State Graph Generation p20.pdf
│	│	├Ingols Practical Attack Graph Generation for Network Defense p10.pdf
│	│	├Jeon TeGViz Distributed Tera-Scale Graph Generation and Visualization p4.pdf
│	│	├Johnsonbau A Graph Generation Software Package p4.pdf
│	│	├Kang An Efficient Generation of the Timed Reachability Graph for the Analysis of Real-Time Systems p23.pdf
│	│	├Lampka MTBDD-based Activity-Local State Graph Generation p4.pdf
│	│	├Lampka Symbolic Activity-Local State Graph Generation in the Context of Mobius p11.pdf
│	│	├Leist Graph Generation on GPUs using Dynamic Memory Allocation p7.pdf
│	│	├Leskovec Kronecker graph p37.pdf
│	│	├Leskovec Realistic, Mathematically Tractable Graph Generation and Evolution, Using Kronecker Multiplication p12.pdf
│	│	├Miyazaki Representative Graph Generation for Graph-Based Character Recognition p9.pdf
│	│	├Namouz Comparison of Graph Generation Methods for Structural Complexity Based Assembly Time Estimation p28.pdf
│	│	├Nobari Fast Random Graph Generation p12.pdf
│	│	├Nobari Fast Random Graph Generation1 p12.pdf
│	│	├Ou A Scalable Approach to Attack Graph Generation p10.pdf
│	│	├Ryszka GraphTool - a new System of Graph Generation p5.pdf
│	│	├Schluter Effects of Graph Generation for Unsupervised Non-Contextual Single Document Keyword Extraction p7.pdf
│	│	├Sorensen Safe-Path Graph Generation for Path Planning in Urban Environments p6.pdf
│	│	├Toma A Dependency Graph Generation Process for Client-side Web Applications p13.pdf
│	│	├VanHorn A Random Graph Generator p6.PDF
│	│	├Wardhana Automatic Generation of Enhanced Waypoint Graph for Volumetric Path Planning p6.pdf
│	│	├Winlaw A Clustering Graph Generator p16.pdf
│	│	├Ying Graph Generation with Prescribed Feature Constraints p12.pdf
│	│	└Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf
│	├graph_generation.htm
│	├<graph_layout>
│	│	├anoop On Some Graph Layout Problems and Solution Strategies p18.pdf
│	│	├Buchsbaum Rectangular Layouts and Contact Graphs p25.pdf
│	│	├BUCHSBAUM Rectangular Layouts and Contact Graphs p29.pdf
│	│	├Claussen Implementing an Algorithm for Orthogonal Graph Layout p47.pdf
│	│	├Diaz A survey on graph layout problems p22.pdf
│	│	├Diaz A survey on graph layout problems p54.pdf
│	│	├Dujmovic On Linear Layouts of Graphs p20.pdf
│	│	├Dujmovic Track Layouts of Graphs p160.pdf
│	│	├Fellows Graph Layout problems Parameterized by Vertex Cover p12.pdf
│	│	├Leeuw Graph Layout Techniques and Multidimensional Data Analysis p31.pdf
│	│	├SHIELDS AREA EFFICIENT LAYOUTS OF BINARY TREES ON ONE, TWO LAYERS p13.doc
│	│	└Sp?nemann On the Automatic Layout of Data Flow Diagrams p99.pdf
│	├graph_layout.htm
│	├<graph_making>
│	│	└Sudakov Making a K4-free graph bipartite p8.pdf
│	├graph_making.htm
│	├<graph_mapping>
│	│	└Bhatel Automated Mapping of Structured Communication Graphs onto Mesh Interconnects p17.pdf
│	├graph_mapping.htm
│	├<graph_modeling>
│	│	├Boonto Dynamics System and Modelling Linear Graph Modeling I p20.pdf
│	│	├McBride SYSTEM ANALYSIS THROUGH BOND GRAPH MODELING p325.pdf
│	│	├Mittelmann Graph Modeling for Quadratic Assignment Problems Associated with the Hypercube p15.pdf
│	│	├Needham Graph Modeling Dos and Donts p96.pdf
│	│	└Rowell Linear Graph Modeling State Equation Formulation p38.pdf
│	├graph_modeling.htm
│	├<graph_packing>
│	│	├Caro Packing GraphsThe packing problem solved p7.pdf
│	│	├Goodman A Genetic Algorithm Approach to Compaction, Bin Packing, and Nesting Problems p73.pdf
│	│	├Grotschel The Steiner Tree Packing Problem in VLSI Design p21.pdf
│	│	├Iwaniec Algorithms for Packing Soft Blocks of Vlsi Systems p6.pdf
│	│	├Jeong A branch-and-price algorithm for the Steiner tree packing problem p21.pdf
│	│	├Kaul Graph Packing and Degree Sequences p72.pdf
│	│	├Kuhn AN ORE-TYPE THEOREM FOR PERFECT PACKINGS IN GRAPHS p23.pdf
│	│	├Kuhn OPTIMAL PACKINGS OF HAMILTON CYCLES IN GRAPHS OF HIGH MINIMUM DEGREE p23.pdf
│	│	├Kuhn PERFECT PACKINGS WITH COMPLETE GRAPHS MINUS AN EDGE p15.pdf
│	│	├Lau An Approximate Max-Steiner-Tree-Packing Min-Steiner-Cut Theorem p10.pdf
│	│	├Martin Packing Paths and Steiner Trees Routing of Electronic Circuits p20.pdf
│	│	├Pantel Graph Packing Problems p86.pdf
│	│	├Sausen Models for the Steiner Tree Packing Problem p85.pdf
│	│	└Srinivasan New Approaches to Covering and Packing Problems p10.pdf
│	├<graph_realization>
│	│	├Ada On Bus Graph Realizability p4.pdf
│	│	└Alfakih The Graph Realization Problem via Semi-Definite Programming p70.pdf
│	├graph_realization.htm
│	├<graph_visualization>
│	│	├<pdf>
│	│	│	├000Dujmovic Track Layouts of Graphs p160.pdf
│	│	│	├000Vogt An open source browser-based software tool for graph drawing and visualization p171.pdf
│	│	│	├Aragón Graph Visualization Tool for Twittersphere users based on a high-scalable Extract, Transform and Load System p28.pdf
│	│	│	├Beck A Taxonomy and Survey of Dynamic Graph Visualization p28 (2).pdf
│	│	│	├Beck A Taxonomy and Survey of Dynamic Graph Visualization p28.pdf
│	│	│	├Boyd InProv Visualizing Provenance Graphs with Radial Layouts and Time-Based Hierarchical Grouping p59.pdf
│	│	│	├Carolina Graph Visualization Software for Networks of Characters in Plays p11.pdf
│	│	│	├CHAPTER 8 Visualization Techniques for Trees, Graphs, and Networks p20.pdf
│	│	│	├Deore Survey on Graph-Hierarchy Visualization Techniques p5.pdf
│	│	│	├Epskamp Package qgraph p73.pdf
│	│	│	├Ersoy Image-Based Edge Bundles Simplified Visualization of Large Graphs p10.pdf
│	│	│	├Erten Simultaneous Graph Drawing Layout Algorithms and Visualization Schemes p12.pdf
│	│	│	├Etemad Node-Ring Graph Visualization Clears Edge Congestion p8.pdf
│	│	│	├Furlinger Capturing and Visualizing Event Flow Graphs of MPI Applications p10.pdf
│	│	│	├Férey IMMERSIVE GRAPH-BASED VISUALIZATION AND EXPLORATION OF BIOLOGICAL DATA RELATIONSHIPS p6.pdf
│	│	│	├GANSNER An open graph visualization system and its applications to software engineering p29.pdf
│	│	│	├Gansner Interactive Visualization of Streaming Text Data with Dynamic Maps p25.pdf
│	│	│	├Gansner Visualizing Streaming Text Data with Dynamic Graphs and Maps p12.pdf
│	│	│	├Hadlak A Survey of Multi-faceted Graph Visualization p20.pdf
│	│	│	├Ham Interactive Visualization of Small World Graphs p8.pdf
│	│	│	├Herman Graph Visualization and Navigation in Information Visualization a Survey p21 (2).pdf
│	│	│	├Herman Graph Visualization and Navigation in Information Visualization a Survey p21.pdf
│	│	│	├Hu Visualizing Data with Graphs and Maps p76.pdf
│	│	│	├Hu Visualizing large graphs p32.pdf
│	│	│	├Huang A new algorithm for removing node overlapping in graph visualization p24.pdf
│	│	│	├Huang Navigating Product Catalogs Through OFDAV Graph Visualization p13.pdf
│	│	│	├Hurter Bundled Visualization of Dynamic Graph and Trail Data p14.pdf
│	│	│	├Jarukasemratana Recent large graph visualization tools a review p17.pdf
│	│	│	├Jarukasemratana Recent large graph visualization tools a review2 p17.pdf
│	│	│	├Junghans Visualization of Hyperedges in Fixed Graph Layouts p131.pdf
│	│	│	├Kairam GraphPrism Compact Visualization of Network Structure p8.pdf
│	│	│	├Kang Net-Ray Visualizing and Mining Billion-Scale Graphs p12.pdf
│	│	│	├Koutra Perseus An Interactive Large-Scale Graph Mining and Visualization Tool p4.pdf
│	│	│	├Kratochv?l GraDR Graph Drawings and Representations p44.pdf
│	│	│	├Kumar Visualization of Clustered Directed Acyclic Graphs with Node Interleaving p6.pdf
│	│	│	├Kwon A Study of Layout, Rendering, and Interaction Methods for Immersive Graph Visualization p14 (2).pdf
│	│	│	├Kwon A Study of Layout, Rendering, and Interaction Methods for Immersive Graph Visualization p14.pdf
│	│	│	├Langevin Multi-Scale Community Visualization of Massive Graph Data p4.pdf
│	│	│	├Lanum sample_ch01 Visualizing Graph Data p20.pdf
│	│	│	├Marshall An Object-Oriented Design for Graph Visualization p16.pdf
│	│	│	├Razoumov Graph Visualization with Gephi p12.pdf
│	│	│	├Rodin Visualization of Dynamic Reference Graphs p5.pdf
│	│	│	├Scalisi Exploiting Interaction in Dynamic Graph Visualization p35.pdf
│	│	│	├Spanakis Graph Visualization Tool for Vehicular Ad-Hoc Networks p2.pdf
│	│	│	├Tarawneh A General Introduction To Graph Visualization Techniques p14.pdf
│	│	│	├Wu Evaluation of Graph Sampling A Visualization Perspective p10.pdf
│	│	│	├Yang PIWI Visually Exploring Graphs Based on Their Community Structure p14.pdf
│	│	│	├Zimmer Displaying User Behavior in the Collaborative Graph Visualization System OnGraX p13.pdf
│	│	│	└?rnberg Comparison and implementation of graph visualization algorithms using JavaFX p62.pdf
│	│	└<ppt>
│	│	  	└Herman Graph Visualization and Navigation in Information Visualization a Survey p37.ppt
│	├graph_visualization_algorithms.htm
│	├graph_visualization_literature.htm
│	├sample.htm
│	├<temp>
│	│	├Alon Optimal Universal Graphs with Deterministic Embedding p9.pdf
│	│	├Bilski Optimum embedding of complete graphs in books p8.pdf
│	│	├Brass On Simultaneous Planar Graph Embeddings p12.pdf
│	│	├Bruhn Embedding graphs in surfaces MacLane’s theorem for higher genus p19.pdf
│	│	├Chen Directed Graph Embedding p6.pdf
│	│	├Childs Topological Graph Theory and Graphs of Positive Combinatorial Curvature p54.pdf
│	│	├Cygan Tight Lower Bounds on Graph Embedding Problems p23.pdf
│	│	├Dolev On Linear Area Embedding of Planar Graphs p24.pdf
│	│	├DUNCAN The Geometric Thickness of Low Degree Graphs p12.pdf
│	│	├Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134.pdf
│	│	├McClintock Extremal Graph Theory for Book-Embeddings p64.pdf
│	│	├Overbay Genetic Algorithms and Book Embeddings A Dual Layered Approach p8.pdf
│	│	├Plesca Graphs on Surfaces and Arithmetical Applications p42.pdf
│	│	├Rue Dynamic Programming for Graphs on Surfaces p21.pdf
│	│	├Rue Dynamic Programming for Graphs on Surfaces p22.pdf
│	│	├Seventh Cologne-Twente Workshop on Graphs and Combinatorial Optimization p204.pdf
│	│	├Tamassia On-line Planar Graph Embedding p39.pdf
│	│	├Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf
│	│	└Ye Entropic Graph Embedding via Multivariate Degree Distributions p11.pdf
│	├Topological graph theory.docx
│	├Topological graph theory.txt
│	├topological_graph_embedding.htm
│	├topological_graph_theory.htm
│	└<topo_theory>
│	  	├Ackerman  A crossing lemma for the pair-crossing number.pptx
│	  	├Ackerman  On topological graphs with at most four crossings per edge p30.pdf
│	  	├Ackerman Beyond planarity of graphs.pptx
│	  	├Ackerman On Grids in Topological Graphs p14.pdf
│	  	├Ackerman On the Maximum Number of Edges in Topological Graphs with no Four Pairwise Crossing Edges p5.pdf
│	  	├Archdeacon Topological Graph Theory a Survey p67.pdf
│	  	├Archdeacon Topological Graph Theory a Survey p67.txt
│	  	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front p18.pdf
│	  	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front1 p18.pdf
│	  	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228.pdf
│	  	├Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole1 p228.pdf
│	  	├Chapter 5 Topological Graph Theory p32.pdf
│	  	├Chapter III Adopting Topological Graph Theory to Traffic Management Problem p18.pdf
│	  	├Childs Topological Graph Theory and Graphs of Positive Combinatorial Curvature p54.pdf
│	  	├Craft Topological Graph Theory.pptx
│	  	├Hutchinson Some Conjectures in Chromatic Topological Graph Theory p19.pdf
│	  	├KNILL CLASSICAL MATHEMATICAL STRUCTURES WITHIN TOPOLOGICAL GRAPH THEORY p28.pdf
│	  	├Mohar Topological graph theory and crossing numbers p18.pdf
│	  	├Rooney Topological Graph Theory Lecture 15-16 Cycles of Embedded Graphs p6.pdf
│	  	├Sawollek A Survey of Embedding Problems in Topological Graph Theory.docx
│	  	└Vella A FUNDAMENTALLY TOPOLOGICAL PERSPECTIVE ON GRAPH THEORY p263.pdf
├<000graph_embedding_03types>
│	├types_0others.htm
│	├types_a.htm
│	├types_b.htm
│	├types_c.htm
│	├types_d.htm
│	├types_e.htm
│	├types_f.htm
│	├types_g.htm
│	├types_h.htm
│	├types_i.htm
│	├types_j.htm
│	├types_k.htm
│	├types_l.htm
│	├types_m.htm
│	├types_n.htm
│	├types_o.htm
│	├types_p.htm
│	├types_p_prototype.htm
│	├types_q.htm
│	├types_r.htm
│	├types_s.htm
│	├types_t.htm
│	├types_u.htm
│	├types_v.htm
│	├<types_v_Volume-respecting embedding>
│	│	├Feige Approximating the bandwidth via volume respecting embeddings p35.pdf
│	│	├Galanis Embeddings p50.pdf
│	│	├Lovasz Geometric representations of graphs p29.pdf
│	│	├Magen Near Optimal Dimensionality Reductions That Preserve Volumes p12.pdf
│	│	├Rao Small distortion and volume preserving embedding for Planar and Euclidian metrics p29.pdf
│	│	├Rao Small distortion and volume preserving embeddings for Planar and Euclidean metrics p7.pdf
│	│	└Wu Deep Semantic Embedding p7.pdf
│	└types_w.htm
├<000graph_embedding_11references>
│	├ref_0others.htm
│	├ref_a.htm
│	├ref_b.htm
│	├ref_c.htm
│	├ref_d.htm
│	├ref_e.htm
│	├ref_f.htm
│	├ref_g.htm
│	├ref_h.htm
│	├ref_i.htm
│	├ref_j.htm
│	├ref_k.htm
│	├ref_l.htm
│	├ref_m.htm
│	├ref_n.htm
│	├ref_o.htm
│	├ref_p.htm
│	├ref_q.htm
│	├ref_r.htm
│	├ref_s.htm
│	├ref_t.htm
│	├ref_u.htm
│	├ref_v.htm
│	├ref_w.htm
│	├ref_x.htm
│	├ref_y.htm
│	└ref_z.htm
├<000graph_embedding_basic>
│	├000Azary Grassmann Learning for Recognition and Classification p132.pdf
│	├000Baingana Embedding Graphs under Centrality Constraints p54.pdf
│	├000Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow a Java Environment for Graph Drawing p144.pdf
│	├000Brink Spherical parameterization methods for 3d surfaces p152.pdf
│	├000Bunke Applied Pattern Recognition p246.pdf
│	├000Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81 (2).pdf
│	├000Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81.pdf
│	├000Cabello Algorithms for embedded graphs p93.pdf
│	├000Cardinal The Complexity of Simultaneous Geometric Graph Embedding p71.pdf
│	├000CHARTRAND Chromatic Graph Theory p498.pdf
│	├000Chowdhury Point-Set Embeddings of Planar Graphs with Fewer Bends p67.pdf
│	├000Cooley EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf
│	├000Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166.pdf
│	├000DeMillo Combinatorial graph embedding p87.pdf
│	├000Ebner Optimal Crossing Minimization using Integer Linear Programming p87.pdf
│	├000Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│	├000Gibert Graph Embedding in Vector Spaces p66.pdf
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│	├000Grilli Automated Local Linear Embedding with an application to microarray data p92.pdf
│	├000Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134.pdf
│	├000Jameson An Address Event Representation (AER) Multicast Router for Colour Vision p200.pdf
│	├000Kocurova2007 Analysis of algorithms for computing the crossing number p119.pdf
│	├000Krug New Approaches on Octilinear Graph Drawing p165.pdf
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│	├000Potoczak Survey of Graph Embeddings into Compact Surfaces p117.pdf
│	├000Riesen Classification and Clustering of Vector Space Embedded Graphs p344.pdf
│	├000Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346.pdf
│	├000Sarvottamananda Planar Graphs Planarity Testing and Embedding p151.pdf
│	├000Sarvottamananda Planar Graphs, Planarity Testing and Embedding p151.pdf
│	├000Shaw Graph Embedding and Nonlinear Dimensionality Reduction p108.pdf
│	├000Yu2014 A Practical Torus Embedding Algorithm and Its Implementation p84.pdf
│	├Alam Pixel and Voxel Representations of Graphs p15.pdf
│	├Alipanahi Guided Locally Linear Embedding p25.pdf
│	├Archdeacon The Pagenumber of Complete Bipartite Graphs p2.docx
│	├ARORA Expander Flows, Geometric Embeddings and Graph Partitioning p30.pdf
│	├Asano A Linear-Space Algorithm for Distance Preserving Graph Embedding p23.pdf
│	├Bai Heat Kernels, Manifolds and Graph Embedding p9.pdf
│	├Baingana CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5.pdf
│	├Bandelt Metric graph theory and geometry a survey p30.pdf
│	├Belkin Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering p7.pdf
│	├Brand A unifying theorem for spectral embedding and clustering p8.pdf
│	├Brandes Colored Simultaneous Geometric Embeddings and Universal Pointsets p24.pdf
│	├Britt Embedding Logical Qubits into the D-Wave Hardware Graph p30.pptx
│	├Busa-Fekete Locally Linear Embedding and its Variants for Feature Extraction p6.pdf
│	├Cappos Simultaneous Graph Embedding with Bends and Circular Arcs p12.pdf
│	├Cardinal The Complexity of Simultaneous Geometric Graph Embedding p14.pdf
│	├Chang Robust Locally Linear Embedding p10.pdf
│	├Chang Robust Locally Linear Embedding p25.pdf
│	├Charikar Spectral Embedding of k-Cliques Graph Partitioning and k-Means p27.pdf
│	├Chepoi Constant approximation algorithms for embedding graph metrics into trees and outerplanar graphs p27.pdf
│	├CHUNG EMBEDDING GRAPHS IN BOOKS A LAYOUT PROBLEM WITH APPLICATIONS TO VLSI DESIGN p26.pdf
│	├Conte A Comparison of Explicit and Implicit Graph Embedding Methods for Pattern Recognition p11.pdf
│	├Cvetkovski Hyperbolic Embedding and Routing for Dynamic Graphs p7.pdf
│	├Cygan Tight Lower Bounds on Graph Embedding Problems p23.pdf
│	├Dell Graph Embedding and Extensions A General Framework for Dimensionality Reduction p21.ppt
│	├Dethlefsen A Common Platform for Graphical Models in R The gRbase Package p12.pdf
│	├Dolev PLANAR EMBEDDING OF PLANAR GRAPHS p15.pdf
│	├Erten Simultaneous Embedding of a Planar Graph and its Dual on the Grid o17.pdf
│	├Ferrer A Recursive Embedding Approach to Median Graph Computation p11.pdf
│	├Gagarin Embedding Graphs Containing K5-Subdivisions p17.pdf
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│	├Goodwin Imbedding Problems in Graph Theory p27.pdf
│	├Graham Isometric graph embeddings p18.pdf
│	├Groenen Multidimensional Scaling p14.pdf
│	├He Graph Embedding with Constraints p6.pdf
│	├He2009 Graph Embedding with Constraints p6.pdf
│	├Hong MultiPlane Graph Embedding (2.5D Graph Embeddability).docx
│	├Horaud A Short Tutorial on Graph Laplacians, Laplacian Embedding, and Spectral Clustering p43.pdf
│	├Huang Cross-view Graph Embedding p12.pdf
│	├H?jsgaard mimR – A Package for Graphical Modelling in R p11.pdf
│	├Jouili Graph Embedding Using Constant Shift Embedding p12.pdf
│	├Kermarrec Distributed Social Graph Embedding p6.pdf
│	├Keselman Many-to-Many Graph Matching via Metric Embedding p8.pdf
│	├Kleinberg Isomorphism and Embedding Problems for Infinite Limits of Scale-Free Graphs p10.pdf
│	├Kong An Iterative Locally Linear Embedding Algorithm p8.pdf
│	├Kuhn Embedding and Ramsey numbers of sparse k uniform hypergraphs p24.pdf
│	├Kuhn Embedding cycles of given length in oriented graphs p8.pdf
│	├Kuhn Embedding large subgraphs into dense graphs p28.pdf
│	├La_Rocca+Badsberg+Dethlefsen.pdf
│	├Lee Locally Linear Embedding versus Isotop p8.pdf
│	├Lipman Symmetry Factored Embedding And Distance p12.pdf
│	├Liu Projective Nonnegative Graph Embedding p11.PDF
│	├Los Embedding Groups of Graph Automorphisms in Surfaces p20.pdf
│	├Luo Cauchy Graph Embedding p8.pdf
│	├Luo Non-negative Laplacian Embedding p10.pdf
│	├Luqman Fuzzy multilevel graph embedding p15.pdf
│	├Matsubayashi Separator-Based Graph Embedding into Multidimensional Grids with Small Edge-Congestion p30.pdf
│	├McClintock Extremal Graph Theory for Book-Embeddings p64.pdf
│	├MOHAR A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21.pdf
│	├Najim More faithfulness graph embedding p9.pdf
│	├Newsome GEM Graph EMbedding for Routing and DataCentric Storage in Sensor Networks Without Geographic Information p13.pdf
│	├Nishana Graph Embedding and Dimensionality Reduction - A Survey p6.pdf
│	├Ou Asymmetric Transitivity Preserving Graph Embedding p10.pdf
│	├Overbay Genetic Algorithms and Book Embeddings A Dual Layered Approach p8.pdf
│	├Perrault-Joncas Directed Graph Embedding an Algorithm based on Continuous Limits of Laplacian-type Operators p9.pdf
│	├Pizzonia Minimum Depth Graph Embedding p12.pdf
│	├Rajan Embeddings Between Hypercubes and Hypertrees p13.pdf
│	├Raveaux Graph Embedding Problem p37.pdf
│	├Renz Hierarchical Graph Embedding for Efficient Query Processing in Very Large Traffic Networks p30.pdf
│	├Ridder Supervised locally linear embedding p8.pdf
│	├Robles-Kelly A Riemannian approach to graph embedding p15.pdf
│	├Rodl Hypergraph packing and graph embedding p18.pdf
│	├Saul An Introduction to Locally Linear Embedding p13.pdf
│	├Saxe Two papers on graph embedding problems p41.pdf
│	├Shaw Structure Preserving Embedding p8.pdf
│	├Shaw Visualizing Graphs with Structure Preserving Embedding p6.pdf
│	├Simonraj Embedding of Poly Honeycomb Networks and the Metric dimension of Star of David Network p18.pdf
│	├Song Clustered Embedding of Massive Social Networks p12.pdf
│	├Stefano Graph embedding via dissimilarity mapping for network comparison p4.pdf
│	├Sudakov Nearly optimal embeddings of trees p36.pdf
│	├Tamassia On-line Planar Graph Embedding p39.pdf
│	├Vadapalli Fault Tolerant Ring Embedding in Tetravalent Cayley Network Graphs p12.pdf
│	├Valveny Vector Space Embedding of Graphs via Statistics of Labelling Information p14.pptx
│	├Verbeek Metric Embedding, Hyperbolic Space, and Social Networks p10.pdf
│	├VITCC Graph Embedding.pdf
│	├Wang Knowledge Graph Embedding by Translating on Hyperplanes p9.pdf
│	├Wilkinson Multidimensional Scaling p30.pdf
│	├Xiao From One Point to A Manifold Knowledge Graph Embedding For Precise Link Prediction p7.pdf
│	├Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p12.pdf
│	├Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p54.ppt
│	├Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction1 p12.pdf
│	├Yang Non-Negative Graph Embedding p8.pdf
│	├Yang Variational Graph Embedding for Globally and Locally Consistent Feature Extraction p16.pdf
│	├Yeh VLSI layouts of complete graphs and star graphs p7.pdf
│	├Yu A Practical Algorithm for Embedding Graphs on Torus p18.pdf
│	├Zhang Robust (Semi) Nonnegative Graph Embedding p17.pdf
│	├Zhao Graph Attribute Embedding via Riemannian Submersion Learning p32.pdf
│	└Zhou Bounding the bandwidths for graphs p12.pdf
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│	├Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9.pdf
│	├Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42.pdf
│	├Angel A dynasearch neighborhood for the bicriteria traveling salesman problem p4.pdf
│	├ANGINIOL Self-Organizing Feature Maps and the Travelling Salesman Problem p5.pdf
│	├Antosiewicz Choice of best possible metaheuristic algorithm for the travelling salesman problem with limited computational time quality, uncertainty and speed p10.pdf
│	├ASCHEUER Solving the Asymmetric Travelling Salesman Problem with Time Windows by Branch-and-Cut p35.pdf
│	├Balas Linear Time Dynamic-Programming Algorithms for New Classes of Restricted TSPs A Computational Study p33.pdf
│	├Bar-Yehuda On Approximating A Geometric Prize-Collecting Traveling Salesman Problem With Time Windows p12.pdf
│	├Bartal The Traveling Salesman Problem Low-dimensionality Implies a Polynomial Time Approximation Scheme p10.pdf
│	├Bassetto The Single-Double Balanced Traveling Salesman Problem p16.pdf
│	├Basu Tabu Search Implementation on Traveling Salesman Problem and Its Variations A Literature Survey p11.pdf
│	├Biron The Traveling Salesman Problem Deceptivley Easy to State Notoriously Hard to Solve p31.pdf
│	├Brezina Solving the Travelling Salesman Problem Using the Ant Colony Optimization p5.pdf
│	├Bryant Genetic Algorithms and the Traveling Salesman Problem p34.pdf
│	├Budinich A Neural Network for the Travelling Salesman Problem with a Well Behaved Energy Function p8.pdf
│	├Cela The x-and-y-axes travelling salesman problem p3.pdf
│	├CERNY Thermodynamical Approach to the Traveling Salesman Problem An Efficient Simulation Algorithm I p11.pdf
│	├<commbinatorial optimization for delivery of goods>
│	│	├000commbinatorial optimization for delivery of goods.htm
│	│	├Bolhaar Strategic decisions in truck routing for a retail chain p90.pdf
│	│	├Caric Vehnicle Routing Problem p152.pdf
│	│	├Cracknell Simulating and Optimising a Delivery Network of Autonomous Courier Agents p151.pdf
│	│	├DAVULIS MODELLING AND OPTIMIZATION OF TRANSPORTATION COSTS p12.pdf
│	│	├Eitzen A Multi-Objective Two-Echelon Vehicle Routing Problem. An Urban Goods Movement Approach for Smart City Logistics p10.pdf
│	│	├Gambardellaa Ant Colony Optimization for vehicle routing in advanced logistics systems p6.pdf
│	│	├Grotschel Lectures on Combinatorial Optimization Modelling Transportation Problems p4.pdf
│	│	├Kindervater Vehicle Routing 2 Handling Side Constraints p21.pdf
│	│	├Leech DELIVERING THE GOODS p31.pdf
│	│	├Lu Ant Colony Optimization Solutions for Logistic Route Planning with Pick-up and Delivery p6.pdf
│	│	├Neagu Solving Distributed Delivery Problems with Agent-Based Technologies and Constraint Satisfaction Techniques p2.pdf
│	│	├Pellonpera Ant colony optimization and the vehicle routing problem p57.pdf
│	│	├Ropke A unified heuristic for a large class of Vehicle Routing Problems with Backhauls p36.pdf
│	│	├Veinott Lectures in Supply-Chain Optimization p261.pdf
│	│	└?atay AN ANT COLONY OPTIMIZATION APPROACH FOR THE CAPACITATED VEHICLE ROUTING PROBLEM WITH SIMULTANEOUS DELIVERY AND PICK-UP p8.pdf
│	├Dantzig Solution of a Large-Scale Traveling-Salesman Problem p22.pdf
│	├Demez Combinatorial Optimization Solution Methods of Traveling Salesman Problem p87.pdf
│	├Dorigo Ant colonies for the traveling salesman problem p10.pdf
│	├Dornberger Solving Optimization Problems by Metaheu-ristics Using the Open Opal Framework - Integration of Travelling Salesman Problem and Selected Solvers p20.pdf
│	├Dumitrescu The Traveling Salesman Problem with Pickup and Delivery Polyhedral Results and a Branch-and-Cut Algorithm p31.pdf
│	├Easton Solving the Traveling Tournament Problem A Combined Integer Programming and Constraint Programming Approach p10.pdf
│	├Gharan A Randomized Rounding Approach to the Traveling Salesman Problem p65.pdf
│	├Goldengorin How To Make a Greedy Heuristic for the Asymmetric Traveling p16.pdf
│	├Greco Travelling Salesman Problem p212 (2).pdf
│	├Greco Travelling Salesman Problem p212.pdf
│	├GUTIN THE TRAVELING SALESMAN PROBLEM AND ITS VARIATIONS p40.pdf
│	├Hahsler TSP – Infrastructure for the Traveling Salesperson Problem p21.pdf
│	├Haque Improving the Solution of Traveling Salesman Problem Using Genetic, Memetic Algorithm and Edge assembly Crossover p4.pdf
│	├Helvig The moving-target traveling salesman problem p22.pdf
│	├Hoffman Traveling salesman problem p9.pdf
│	├Isaacs Algorithms for the Traveling Salesman Problem with Neighborhoods Involving a Dubins Vehicle p6.pdf
│	├Ji The Traveling Salesman and the Quadratic Assignment Problems Integration Modeling and Genetic Algorithm p8.pdf
│	├Johnson The Traveling Salesman Problem A Case Study in Local Optimization p103.pdf
│	├Jones Computation of the Travelling Salesman Problem by a Shrinking Blob p27.pdf
│	├JONES THE TRAVELING SALESMAN PROBLEM AND HARMONIC ANALYSIS p9.pdf
│	├Jozefowiez Multi-objective Meta-heuristics for the Traveling Salesman Problem with Profits p19.pdf
│	├Junger THE TRAVELING SALESMAN PROBLEM p117.pdf
│	├Kanda Using Meta-learning to Classify Traveling Salesman Problems p6.pdf
│	├Kang Benchmarking Algorithms for Dynamic Travelling Salesman Problems p6.pdf
│	├Kumar Assignment and Travelling Salesman Problems with Coefficients as LR Fuzzy Parameters p16.pdf
│	├Laporte The Traveling Salesman Problem An overview of exact and approximate algorithms p17.pdf
│	├Letchford Compact Formulations of the Steiner Traveling Salesman Problem and Related Problems p28.pdf
│	├Letchford Mathematical Programming Approaches to the Traveling Salesman Problem p12.pdf
│	├Li Ant Colony Optimization for the Traveling Salesman Problem Based on Ants with Memory p6.pdf
│	├Lokar Traveling salesman problem p6.doc
│	├Lust The Multiobjective Traveling Salesman Problem A Survey and a New Approach p24.pdf
│	├Mandziuk Solving the Travelling Salesman Problem with a Hopfield - type neural network p18.pdf
│	├Maredia History, Analysis, and Implementation of Traveling Salesman Problem(TSP) and Related Problems p47.pdf
│	├Mattsson The Asymmetric Traveling Salesman Problem p64.pdf
│	├Monnot Approximation algorithms for the traveling salesman problem p22.pdf
│	├Montemanni The robust traveling salesman problem with interval data p21.pdf
│	├Nilsson Heuristics for the Traveling Salesman Problem p6.pdf
│	├Pacha-Sucharzewski Analysis of the Travelling Salesman Problem and an Application of Heuristic Techniques for Finding a New Solution p7.pdf
│	├PAPADIMITRIOU ON THE APPROXIMABILITY OF THE TRAVELING SALESMAN PROBLEM p20.pdf
│	├Pathak Travelling Salesman Problem Using Bee Colony With SPV p5.pdf
│	├Pizlo Traveling Salesman Problem A Foveating Pyramid Model p9.pdf
│	├Potvin The Traveling Salesman Problem A Neural Network Perspective p60.pdf
│	├Rasmussen TSP in Spreadsheets – a Guided Tour p23.pdf
│	├Renaud AN EFFICIENT COMPOSITE HEURISTIC FOR THE SYMMETRIC GENERALIZED TRAVELING SALESMAN PROBLEM p23.pdf
│	├Rostoker Travelling Salesman Problems p56.pdf
│	├Rothe Two solvable cases of the Traveling Salesman Problem p60.pdf
│	├Sadiq The Traveling Salesman Problem Optimizing Delivery Routes Using Genetic Algorithms p6.pdf
│	├Schneider Searching for backbones - an efficient parallel algorithm for the traveling salesman problem p16.pdf
│	├Schneider The time-dependent traveling salesman problem p5.pdf
│	├WANG SIGMA-DELTA QUANTIZATION ERRORS AND THE TRAVELING p21.pdf
│	├Yatsenko Fast Exact Method for Solving the Travelling Salesman Problem p4.pdf
│	└?tencek Traveling salesman problem p53.pdf
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│	├Cong Techniques for Designing Efficient Parallel Graph Algorithms for SMPs and Multicore Processors p11.pdf
│	├Ellis-Monaghan Graph Theoretical Problems in Next-Generation Chip Design p17.pdf
│	├Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│	├Galuzzi Graph Theory and Application Specific Processors p7.pdf
│	├Gogoi Algorithm for Designing VLSI Floorplan using Planar Triangulated Graph p9.pdf
│	├Hendrickson Graph partitioning models for parallel computing p16.pdf
│	├Lin Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing p4.pdf
│	└Lin TCG A Transitive Closure Graph-Based Representation for General Floorplans p12.pdf
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│	├graph_features.docx
│	├graph_features.txt
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│	│	├Bacik Structure of Graph Homomorphisms p111.pdf
│	│	├Borgs Counting Graph Homomorphisms p45.pdf
│	│	├Brewster Graph Homomorphism Tutorial p164.pdf
│	│	├CAI GRAPH HOMOMORPHISMS WITH COMPLEX VALUES A DICHOTOMY THEOREM p106.pdf
│	│	├HAHN Graph homomorphisms structure and symmetry p60.pdf
│	│	├Luksan FRACTIONAL GRAPH HOMOMORPHISMS p46.pdf
│	│	└Sun A contribution to the theory of signed graph homomorphism bound and Hamiltonicity p156.pdf
│	├<graph_isomorphism>
│	│	├Augeri ON GRAPH ISOMORPHISM AND THE PAGERANK ALGORITHM p153.pdf
│	│	├Babai Graph Isomorphism in Quasipolynomial Time p89.pdf
│	│	├Boldi Graph Fibrations, graph isomorphism, and PageRank p34.pdf
│	│	├Buhler Quantum approaches to the graph isomorphism problem p128.pdf
│	│	├Chandoo Completeness Results for Graph Isomorphism on Restricted Graph Classes p64.pdf
│	│	├Grohe Structural and Logical Approaches to the Graph Isomorphism Problem p90.pdf
│	│	├Kukluk Algorithm and Experiments in Testing Planar Graphs for Isomorphism p44.pdf
│	│	├McKay Practical Graph Isomorphism II p70.pdf
│	│	├Muzychuk Graph Isomorphism problem, Weisfeiler-Leman algortihm and coherent configurations p96.pdf
│	│	└<Subgraph Isomorphism Problem>
│	│	  	└Meana Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware p43.pdf
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│	│	└Bokal Minor-monotone crossing number p6.pdf
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│	└<maximal_common_subgraphs>
│	  	└Zhou Finding Maximal k-Edge-Connected Subgraphs from a Large Graph p12.pdf
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│	├000graph_file_formats.docx
│	├000graph_file_formats.htm
│	├Altair HyperGraph.pdf
│	├Andreas A Primer on Graph Processing with Bolinas p17.pdf
│	├Bernard GRAPH FILE FORMATS p50.pdf
│	├Brandes Graph Markup Language (GraphML) p26.pdf
│	├Csardi igraph a package for network analysis p70.pdf
│	├GANSNER An open graph visualization system and its applications to software engineering p29.pdf
│	├Ganzow A CSP Hypergraph Library p12.pdf
│	├Guduru GRAPH DATA CONVERSION AND TREE VISUALIZATION p60.pdf
│	├Iordanov HyperGraphDB A Generalized Graph Database p12.pdf
│	├Roughan Unravelling Graph-Exchange File Formats p22.pdf
│	├Ryszka GraphTool - a new System of Graph Generation p5.pdf
│	├Winter An Overview of the GXL Graph Exchange Language p13.pdf
│	├Winter An Overview of the GXL Graph Exchange Language1 p13.pdf
│	├Winter Exchanging Graphs with GXL p15.pdf
│	├Ziegler n-Level Hypergraph Partitioning p52.pdf
│	└Zien GAMFF - A Graph and Matrix File Format p37.pdf
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│	│	├Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81.pdf
│	│	├FROST Graph Classification with Differential Privacy p38.pdf
│	│	├Graph Classification p33.pdf
│	│	└Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346.pdf
│	├graph_classification.htm
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│	│	├Bader Graph Partitioning and Graph Clustering p258.pdf
│	│	├Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346.pdf
│	│	├Schulz Graph Partitioning and Graph Clustering in Theory and Practice p202.pdf
│	│	├Seeland Structural Graph Clustering Scalable Methods and Applications for Graph Classification and Regression p206.pdf
│	│	├van Dongen GRAPH CLUSTERING by FLOW SIMULATION p173.pdf
│	│	└van Dongen GRAPH CLUSTERING by FLOW SIMULATION p175.pdf
│	├<graph_coloring>
│	│	├Barenboim Distributed Graph Coloring Fundamentals and Recent Developments p160.pdf
│	│	├Duran Graph Coloring Problems p114.pdf
│	│	├Dvorak New Techniques in Coloring Embedded Graphs p284.pdf
│	│	├Lidicky Graph coloring problems p106.pdf
│	│	├Marx Graph Coloring with Local and Global Constraints p176.pdf
│	│	└Normann Parallel graph coloring on multi-core CPUs p45.pdf
│	├graph_coloring.docx
│	├graph_coupling.docx
│	├graph_covering.docx
│	├graph_crossing.docx
│	├graph_editing.htm
│	├<graph_labeling>
│	│	└Gallian A Dynamic Survey of Graph Labeling p384.pdf
│	├<graph_matching>
│	│	├Adamczewski Discrete Tabu Search for Graph Matching p9.pdf
│	│	├Andrews Parallel Algorithms for Maximum Matching in Complements of Interval Graphs and Related Problems p31.pdf
│	│	├Bunke Graph Matching Theoretical Foundations, Algorithms, and Applications p7.pdf
│	│	├Carroll Matching RDF Graphs p17.pdf
│	│	└Duchenne A Tensor-Based Algorithm for High-Order Graph Matching p8.pdf
│	├graph_matching.htm
│	├graph_matching.txt
│	├<graph_mining>
│	│	├christos GRAPH MINING AND COMMUNI TY EVALUAT ION WI TH DEGENERACY p152.pdf
│	│	├Faloutsos Large Graph Mining – Patterns, Tools and Cascade analysis p69.pdf
│	│	├McGregor Graph Mining on Streams p5.pdf
│	│	├Mirrokni Large Scale Graph Mining Theory and Practice p65.pdf
│	│	├Rahmani An Introduction to Graph Mining p49.pdf
│	│	├SKHIRI Large Graph Mining Recent Development, Challenges and Potential Solutions p113.pdf
│	│	└Tools for Large Graph Mining.pdf
│	├graph_packing.htm
│	├<graph_partition>
│	│	├AURORA MULTI-LEVEL GRAPH PARTITIONING p62.pdf
│	│	├Bader Graph Partitioning and Graph Clustering p258.pdf
│	│	├Chung Four graph partitioning algorithms p117.pdf
│	│	└Trevisan Spectral Graph Theory and Graph Partitioning p62.pdf
│	├graph_partition_a2j.docx
│	├graph_partition_k2z.docx
│	├graph_tranform.docx
│	├<Graph_traversal>
│	│	└Adrian Graphs and Graph Traversals p36.ppt
│	└graph_traversal.docx
├<0graph_theory4webcrawling>
│	├<000graph_theory4search_engines>
│	│	├000graph_theory4search_engines.htm
│	│	├Aggarwal Theory Research at Google.pdf
│	│	├Barabasi The physics of the Web.pdf
│	│	├Bhawnani Mathematics at Google.pdf
│	│	├BRYAN THE $25,000,000,000 EIGENVECTOR THE LINEAR ALGEBRA BEHIND GOOGLE.pdf
│	│	├Ganta Search Engine Optimization through Web Page Rank Algorithm.pdf
│	│	├HE Clustering and Searching WWW Images Using Link and Page Layout Analysis.pdf
│	│	├Korner Social-focused Network Analysis of User Goals Extracted from a Large Search Query Log.pdf
│	│	├Koukla Optimizing keyword positions for search engine marketing.pdf
│	│	├Kuppusamy SEMANTIC SNIPPET CONSTRUCTION FOR SEARCH ENGINE RESULTS BASED ON SEGMENT EVALUATION.pdf
│	│	├Langville Google’s PageRank and Beyond The Science of Search Engine Rankings.pdf
│	│	├NAMBIAR THEORY OF SEARCH ENGINES.pdf
│	│	├Peretti On the mathematical background of Google PageRank algorithm.pdf
│	│	├Preethi Case and Relation (CARE) based Page Rank Algorithm for Semantic Web Search Engines.pdf
│	│	├Silvestrov Mathematics behind Internet.pdf
│	│	├Stein Analysis of Clustering Algorithms for Web-based Search.pdf
│	│	├Wills Google’s PageRank The Math Behind the Search Engine.pdf
│	│	└Zhang DESIGN AND IMPLEMENTATION OF A SEARCH ENGINE WITH THE CLUSTER RANK ALGORITHM.pdf
│	├000graph_theory4webcrawling.htm
│	├Bonato THE ROBOT CRAWLER GRAPH PROCESS p22.pdf
│	├Broder Graph structure in the web p15.pdf
│	└Kumar The Web as a graph p10.pdf
├<0graph_types>
│	├<data_flow_graph>
│	│	├Ersfolk Scheduling Dynamic Dataflow Graphs with Model Checking p225.pdf
│	│	└Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf
│	├<Dynamic graph>
│	│	└Demetrescu Dynamic graphs p20.pdf
│	├<eulerian_graph>
│	│	└Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
│	├<fuzzy_graph>
│	│	└Zhang Speeding up VLSI layout verification using fuzzy attributed graphs approach p11.pdf
│	├<graph_of_graphs>
│	│	└Pignolet Exploring the Graph of Graphs Network Evolution and Centrality Distances p10.pdf
│	├graph_types1.docx
│	├graph_types2.docx
│	├<median_graph>
│	│	└Ferrer Theory and algorithms on the median graph p174.pdf
│	├<planar_graph>
│	│	├Culler Planar graphs p69.pdf
│	│	└Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf
│	└<random_graph>
│	  	├Ioannides RANDOM GRAPHS AND SOCIAL NETWORKS An Economics Perspective p66.pdf
│	  	├Knobel From Random Graphs to Complex Networks A Modelling Approach p87.pdf
│	  	├van der Hofstad Random Graphs and Complex Networks. Vo. I p328.pdf
│	  	└van der Hofstad Random Graphs and Complex Networks. Vol I p312.pdf
├<0hypergraph>
│	├000hypergraph_intro.docx
│	├000hypergraph_models_fpga.docx
│	├000hypergraph_models_fpga.pdf
│	├000hypergraph_models_fpga_def.docx
│	├000hypergraph_models_fpga_def_original.docx
│	├000hypergraph_models_fpga_original.docx
│	├000hypergraph_models_fpga_ref.docx
│	├000hypergraph_types.docx
│	└Berge HYPERGRAPHS Combinatorics of Finite Sets p267.pdf
├<0openproblems>
│	├0000graph_openproblems.docx
│	├BONATO Sketchy Tweets Ten Minute Conjectures in Graph Theory p8.pdf
│	├Bondy BEAUTIFUL CONJECTURES IN GRAPH THEORY p45.pdf
│	├Chung Open problems of Paul Erdos in graph theory p44.pdf
│	├Eppstein Some Open Problems in Graph Theory and Computational Geometry p15.pdf
│	├Ghosh Unsolved Problems in Visibility Graph Theory p11.pdf
│	├Hansen What Forms Do Interesting Conjectures Have in Graph Theory p22.PDF
│	├Lovasz Graph homomorphisms Open problems p10.pdf
│	├Sloane Unsolved Problems in Graph Theory Arising from the Study of Codes p13.pdf
│	└Zentz The Oberwolfach Problem in Graph Theory p7.pdf
├graphtheory.chm
├<img>
│	├graph1.png
│	├graph2.png
│	└graph3.jpg
├Letter4graph4Chip_CNEN.docx
├Whores_ChipMath_Old1.docx
├Whores_ChipMath_Old2.docx
├Whores_ChipMath_Websites.txt
├Whores_ChipMath_WebsitesTemp.txt
└<ZZZgraphtheory_sciences>
      ├<Chemical_Graph_Theory>
      │	└Balaban Chemical Graph Theory and the Sherlock Holmes Principle p28.pdf
      ├<Evolutionary_Graph_Theory>
      │	└Shakarian A Review of Evolutionary Graph Theory With Applications to Game Theory p45.pdf
      ├Liu Automatic RunTime Extraction of Communication Graphs From Multithreaded Applications p6.pdf
      └Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf


def

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Graph Theoretic Software & Tools
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Keywords

graph editor
graph editing tools
graph tools
graph software

graph theory software
Graph visualization tools

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AbuGraph

AbuGraph is a Java application for graph drawing and visualization. It can be used by another program by using a TCP connection. This enables viewing of a graph data structure which is part of another application.

http://abugraph.sourceforge.net/

https://sourceforge.net/projects/abugraph/

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AbuGraph

AbuGraph is a Java application for graph drawing and visualization. It can be used by another program by using a TCP connection. This enables viewing of a graph data structure which is part of another application.

http://abugraph.sourceforge.net/

https://sourceforge.net/projects/abugraph/

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AGD (Algorithms for Graph Drawing)

AGD (Algorithms for Graph Drawing)

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aiSee Graph Visualization

http://www.absint.com/aisee/

aiSee automatically calculates a customizable layout of graphs specified in GDL (graph description language). aiSee supports 15 basic graph layout algorithms, recursive subgraph nesting, fish-eye views and easy printing. It has been optimized to handle large graphs automatically generated by applications (e.g. compilers).

Discontinuation notice: As of November 1st, 2014, aiSee is no longer available as a stand-alone product. It is now only offered as an integral part of our powerful, state-of-the-art tools for static analysis of safety-critical applications:

Attributed Graph Grammar System (AGG)

https://graphalchemist.github.io/Alchemy/#/

AllegroMCODE

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Altair HyperMesh

http://www.altairhyperworks.com/product/HyperMesh

annas

code.google.com/p/annas/

https://github.com/gt4j/annas

a Java framework designed for researchers in Graph Theory

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BabelGraph

Social network analysis, visualization and simulation tool. The software is open source, written in C++ and OpenGL.

http://www.babelgraph.org/

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Bandage

a Bioinformatics Application for Navigating De novo Assembly Graphs Easily

https://rrwick.github.io/Bandage/

https://github.com/rrwick/Bandage

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BioJAKE

BioJAKE

Biopath

Biopath is a platform for a convenient electronic access to the biochemical knowledge. It provides information from different views and in distinct levels of detail. Biopath provides powerful search mechanisms for substances and reaction networks, it gives access to different types of information on enzymes, reactions and metabolism and automatically computes visual representations of complex reactions nets. Biopath is easy to use and can be updated and extended (detailed description).
http://www.fim.uni-passau.de/en/fim/faculty/chairs/theoretische-informatik/projects/biopath.html

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bioWeb3D

https://www.ebi.ac.uk/~jbpettit/bioWeb3D/

https://github.com/jbogp/bioWeb3D/

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blazegraph

https://www.blazegraph.com/company/

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Bolinas

Andreas A Primer on Graph Processing with Bolinas p17.pdf

http://www.isi.edu/licensed-sw/bolinas/

Bolinas is a package for graph processing, developed at USC/ISI by Jacob Andreas, Daniel Bauer, David Chiang, Karl Moritz Hermann, Bevan Jones, and Kevin Knight. Bolinas follows in the footsteps of Carmel, a finite-state (string) transducer package written by Jonathan Graehl, and Tiburon, a tree transducer package written by Jonathan May.

Bolinas can process rooted, directed, cyclic, edge and node-labeled (hyper-)graphs. It is based on Synchronous Hyperedge Replacement Grammar (SHRG), a context free grammar formalism that works by repeatedly rewriting nonterminal hyperedges with larger graph fragments.

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http://www.bondgraph.com

Boost C++ Libraries.

http://www.boost.org/

http://www.boost.org/

BOS

A task-graph processing software framework for the Epiphany many-core architectureBOS: A task-graph processing software framework for the Epiphany many-core architecture

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BPMN( Business Process Model and Notation) diagram

BPMN( Business Process Model and Notation) diagram

CCVisu: A Tool for Force-Directed Graph Layout

CCVisu is a light-weight Java tool for force-directed graph layout and visual clustering. The layout is minimized using the algorithm of Barnes and Hut, and several energy models are supported. The resulting layouts are provided in text format, as VRML or SVG, or displayed on the screen.

http://ccvisu.sosy-lab.org/

CGV - Coordinated Graph Visualization

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ChemDraw

Chemlab

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Cmap

http://cmap.ihmc.us/

http://graphexploration.cond.org/

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COSBILab Graph

http://www.cosbi.eu/research/prototypes/graph

Cytoscape

http://cytoscape.org/

Cytoscape is an open source software platform for visualizing molecular interaction networks and biological pathways and integrating these networks with annotations, gene expression profiles and other state data. Although Cytoscape was originally designed for biological research, now it is a general platform for complex network analysis and visualization. Cytoscape core distribution provides a basic set of features for data integration, analysis, and visualization. Additional features are available as Apps (formerly called Plugins).

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http://www.datavizcatalogue.com/

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Dia project

dot

Eleftherios Koutsofios and Stephen C. North. Drawing graphs with dot. Murray
Hill, NJ, October 1993.

Dragon

Oscar Hernandez, Chunhua Liao, and Barbara Chapman. Dragon: A static and
dynamic tool for OpenMP. In Proceedings of the Workshop on OpenMP Applications
and Tools (WOMPAT 2004), pages 53–66, 2004.

https://www.draw.io/

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http://www.dynagraph.org/

The Dynagraph engines draw graphs (networks, flowcharts) which change over time.

Newbery and Tichy’s Edge system

Enterprise Architect

Factorized Graph Matching

http://www.f-zhou.com/gm_code.html

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https://franz.com/

https://en.wikipedia.org/wiki/Franz_Inc

https://allegrograph.com/about-franz-inc/

http://www.pharmatechoutlook.com/news/franz-releases-graph-visualization-software-to-build-connections-between-data-nwid-44.html

Semantic Graph Database

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http://www.free-graph-theory-software.org/

Gato

gato.sourceforge.net/

a software which visualizes algorithms on graphs

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GDS (Graph Drawing Server)

GDS

Brown University's Graph Drawing Server : GDS
http://cs.brown.edu/cgc/graphserver/
We envision a graph drawing and translation service for the WWW with dual objectives: drawing user-specified graphs, and translating graph-descriptions and graph drawings from one format to another.

GDToolkit (Graph Drawing Toolkit)

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GDToolkit - a Graph Drawing Toolkit

GDToolkit (also known as GDT) is a Graph Drawing Toolkit designed to efficiently manipulate several types of graph, and to automatically draw them according to many different aesthetic criteria and constraints.

http://www.dia.uniroma3.it/~gdt/

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GEM-2

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Gephi

https://gephi.org/
http://gephi.org/
http://gephi.github.io/users/supported-graph-formats/
project by different actors, deeply involved in graph exchange issues, the gexf specifications are mature enough to claim being both extensible and open, and suitable for real specific applications.

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GIOTTO3D

(Apache) Giraph

The giRaph package for graph representation in R
Luca La Rocca, Jens Henrik Badsberg and Claus Dethlefsen
https://giraph.apache.org/
https://cwiki.apache.org/confluence/display/GIRAPH/Index
https://cwiki.apache.org/confluence/pages/viewpage.action?pageId=29688451

Gliffy

GLMol

Gluskap

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GOBLIN

goblin2.sourceforge.net/

Goblin is a full-featured tool chain for handling graphs

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GoDiagram - .NET and Java diagram components

Add custom interactive diagrams to .NET and Java user interfaces, including networks, workflows, flowcharts, org charts, and design tools. Optional automatic layout and instruments.

http://www.nwoods.com/

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gR project described by Lauritzen (2002)

graphical tool dynamicGraph by Badsberg (2005) which is also part of the gR project.

Lauritzen, S.L. (2002) �gRaphical Models in R�, R News, 2, 39.

Lauritzen, S.L. (1996) �Graphical Models�, Clarendon Press, Oxford, UK.

https://www.r-project.org

http://cran.r-project.org/src/contrib/Views/gR.html

http://www.ci.tuwien.ac.at/gR/

http://www.ci.tuwien.ac.at/gR/gR.html

http://www.springer.com/978-1-4614-2298-3

http://www.ci.tuwien.ac.at/Conferences/gR-2002/

Rowe et al.’s graph editor, Grab

Graclus software

Graclus (latest: Version 1.2) is a fast graph clustering software that computes normalized cut and ratio association for a given undirected graph without any eigenvector computation.

https://www.cs.utexas.edu/users/dml/Software/graclus.html

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Graphab

Graphab software is devoted to the modelling of ecological networks from the framework of graph theory. It is the only tool able to include construction and visualization of graphs, connectivity analyses and links with external data. It is easily compatible with Geographical Information Systems.

http://thema.univ-fcomte.fr/productions/graphab/

graphalg

sourceforge.net/projects/graphalg/
Software for Teaching Graph Theory

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GraphBase

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http://graphbase.net/GraphTools.html

Graph Drawings and Representations
EuroGIGA Project No. 10-EuroGIGA-OP-003

The Stanford GraphBase is a collection of programs written by Donald Knuth. Its main purpose is to generate and examine graphs but can also be used as a library to write ones own programs.

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GraphChi

http://graphlab.org/graphchi/

http://code.google.com/p/graphchi/

http://www.kdnuggets.com/2012/07/graphchi-fast-large-scale-graph-software.html

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GraphClust

http://cs.nyu.edu/shasha/papers/GraphClust.html

Graph Databases Book
www.graphdatabases.com

graph-dict

https://github.com/ufkapano/graphsdict/

https://www.graphdracula.net/

Graph::Easy

The graph::easy web page:

http://search.cpan.org/~tels/Graph-Easy/

http://www.graphdrawing.de/

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Graph Drawing Resources

Links to research groups and software.

http://www.cs.brown.edu/people/rt/gd.html

http://graphdrawing.org/index.html

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GraphEd

GraphEd is an interactive, extendable editor for graphs and graph gramatics. GraphEd was replaced by Graphlet and is not supported anymore.

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GraphGL

GraphGrep

http://www.cs.nyu.edu/cs/faculty/shasha/papers/graphgrep/

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GraphLab: Distributed Graph-Parallel API

http://docs.graphlab.org/graph_formats.html
http://forum.graphlab.com/discussion/193/graph-file-formats

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Graphlet

Graphlet?

Graphlet (no more available) is a toolkit for the implementation of editors and drawing algorithms for graphs. Graphlet is based on GTL (graphlet-5.0.1-lgpl).
http://www.fim.uni-passau.de/fileadmin/files/lehrstuhl/brandenburg/projekte/graphlet/graphlet-5.0.1-lgpl.tar.gz

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Graph Magics

A tool for graph theory, having a generator and offering various algorithms: shortest paths, network flows, maximal clique, optimal coloring etc.

http://www.graph-magics.com/

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Graph Markup Language (GraphML)

http://graphml.graphdrawing.org/

GraphShop

An Interactive Software Environment for Graph Theory Research and Applications

Aaron Andersen
Utah State University

2011

http://stringoftheseus.com/projects/GraphShop/

Graph Matching Toolkit

http://www.fhnw.ch/wirtschaft/iwi/gmt

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GraphTea

http://www.graphtheorysoftware.com/

GraphTea is a software framework to work on graphs and social networks. It helps you to:

  • draw a graph
  • get reports about it
  • run algorithms on it
  • visualize it

https://github.com/graphtheorysoftware/GraphTea

The Graph Template Library (GTL), 2015, GitHub repository

https://github.com/rdmpage/graph-template-library/

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GraphThing

graph.seul.org/

a tool that allows you to create, manipulate and study graphs

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GraphTool

The graph-tool python library, figshare,

https://graph-tool.skewed.de/

graph-utils

sourceforge.net/projects/graphutils/
utilities realizing theoretical graph algorithms

Graphvis

Gravisto

Gravisto contains an powerful data structure, which is easy to extend, to save graphs. Furthermore it is an object-oriented framework for the implementation of graph drawing editors and algorithms. Gravisto was implemented in Java from scratch.
http://gravisto.fim.uni-passau.de/

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GraphViz

Graphviz and Dynagraph � Static and Dynamic Graph Drawing Tools
John Ellson, Emden R. Gansner, Eleftherios Koutsofios, Stephen C. North,
and Gordon Woodhull
AT&T Labs - Research, Florham Park NJ 07932, USA

http://www.graphviz.org/

http://www.apnorton.com/blog/2016/03/08/Visualizing-Graphs-in-Program-Output/ ?

https://chocolatey.org/packages/Graphviz

https://chocolatey.org/packages/Graphviz

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https://graphwalker.github.io/

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GraphX

http://graphstream-project.org/

http://www.datascienceassn.org/content/top-5-graph-visualisation-tools

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Graph Rewriting and Transformation (GReAT)

GRINEdit

www.nishiohirokazu.org/grinedit/

an open source visualization software for Graphs

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GRaphs for Object-Oriented VErification (GROOVE)

grTheory

www.mathworks.com/matlabcentral/fileexchange/4266
28 functions for different tasks of graph theory

https://www.cs.ucsb.edu/~xyan/software/gSpan.htm

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gteditor

A graph editor and tool for sketching graphs and performing some common graph operations developed in Java.

http://code.google.com/p/gteditor/

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GTL

GTL (Graph Template Library) is a STL based library, which provides necessary classes and algorithms for the work with graphs. Furthermore it contains modules for more complex graph algorithms (GTL-1.2.4-lgpl).
http://www.fim.uni-passau.de/fileadmin/files/lehrstuhl/brandenburg/projekte/gtl/GTL-1.2.4-lgpl.tar.gz

GTL-java provides the GTL graph structure and algorithms for Java (GTL_java-1.0.0-lgpl).
http://www.fim.uni-passau.de/fileadmin/files/lehrstuhl/brandenburg/projekte/gtl-java/GTL_java-1.0.0-lgpl.tar.gz

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GUESS: The Graph Exploration System

An Open Source program written in Jython to visualize graphs and perform operations on them. Provides a Jython based scripting language with syntactic sugar for operating on graphs.

http://graphexploration.cond.org/

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H3Viewer

Honeycomb

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Hypercube

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Hypercube - Graph visualization tool p5

HyperGraph

HyperGraph visualizes hyperbolic trees and graphs. It is used to show topic maps, sitemaps or hierarchies.

http://hypergraph.sourceforge.net/

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HyperGraphDB

http://hypergraphdb.org/learn?page=IntroInstall&project=hypergraphdb

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Hypertree

Hypertree - an efficient program for solving the Graph Realization Problem.
http://www.cs.ucdavis.edu/~gusfield/pphcd/E:/graph_realization/README.txt

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HyperView

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Altair HyperView 80 Tutorials p88

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igraph

igraph Package igraph p322

http://igraph.org/

https://github.com/szhorvat/IGraphM

http://cneurocvs.rmki.kfki.hu/igraph/index.html

http://igraph.org/python/

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IBM: ILOG Visualization for Java

Simplifies complicated diagrams. The package rearranges complex graph data sets into clear on-screen drawings. Core information represented by nodes and links is much easier to understand.

http://www-01.ibm.com/software/integration/visualization/java/

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In Situ Framework

JavaScript InfoVis Toolkit

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JGraph

www.jgraph.com/jgraph.html

the leading Java Swing Graph Visualization and Layout library

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http://jgrapht.org/

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Jostle

https://www3.cs.stonybrook.edu/~algorith/implement/jostle/implement.shtml

JS Graph

http://www.tensegrity-software.com/

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js1k 618

js1k.com/demo/618

#js1k demo submission by Lars R?nnb?ck

http://jung.sourceforge.net/

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Keylines

Keylines

http://www.datascienceassn.org/content/top-5-graph-visualisation-tools

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LEDA – Library of Efficient Data Types and Algorithms.

http://www.algorithmic-solutions.com/

LEMON – an Open Source C++ Graph Template Library

http://lemon.cs.elte.hu/

LGL - Large Graph Layout

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LinLogLayout

A light-weight tool for force-directed graph layout and graph clustering (community detection). Includes reusable Java classes (LGPL license) for optimizing various energy models (including LinLog) and the modularity measure.

http://code.google.com/p/linloglayout/

Graph clustering and force-directed graph layout

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LINK

http://dimacs.rutgers.edu/~berryj/manual/node5.html#SECTION03020000000000000000

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Linkurious

https://linkurio.us/graph-visualization-software-linkurious-v0-9-1/

https://love2d.org/forums/viewtopic.php?t=82273

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MagicDraw

Maple

www.maplesoft.com/support/help/Maple/view. aspx?path=GraphTheory
routines for creating, drawing, manipulating, and testing graphs

Marklogic

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Mascopt

A set of java tools for network and graph optimization problems. It features basic graph algorithms and graphical user interfaces. Mascopt is under LGPL license.

http://www-sop.inria.fr/mascotte/mascopt

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Mathematica

http://www.wolfram.com/

The basic function to generate a random graph is RandomGraph[gdist, n] which generates n graphs with the graph distribution gdist.

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Matlab

http://strategic.mit.edu/downloads.php?page=matlab_networks

?

https://omictools.com/marvis-graph-tool

?

Maxima

maxima.sourceforge.net/docs/ manual/en/maxima_56.html
Free computer algebra system

http://glaros.dtc.umn.edu/gkhome/metis/metis/overview

?

?
Microsoft Visio

Microsoft Visio

?

The MultiThreaded Graph Library (MTGL)

nauty

cs.anu.edu.au/~bdm/nauty/

a program for computing automorphism groups of graphs

?

http://ophid.utoronto.ca/navigator/

?

Neo4j

https://neo4j.com/

https://neo4j.com/developer/guide-data-visualization/

?

http://www.netvis.org/

networkD3 in R

?

NetworkX

http://networkx.github.io/

http://networkx.github.io

for Python

The Network Simulator - ns-2

http://isi.edu/nsnam/ns/

http://nwb.slis.indiana.edu/

http://nwb.cns.iu.edu/download.html

NetworkX

networkx.lanl.gov/

High productivity software for complex networks

https://networkx.lanl.gov/wiki

http://networkx.lanl.gov/

?

NodeBox Graph library

http://nodebox.net/code/index.php/Graph#loading_the_library

Nodes3D

Nodes3D is an open-source, platform independent, interactive 3D graph visualization system based on C and OpenGL.

http://brainmaps.org/index.php?p=desktop-apps-nodes3d

https://www.novamind.com/

?

NS2

http://isi.edu/nsnam/ns/

?

?

OcORD

OcORD is a software tool for rectangular dualization.

Oculus Rift

OGDF( Open Graph Drawing Framework) ?

OGDF - The Open Graph Drawing Framework

OGDF is an open-source C++ library containing a wealth of data structures and algorithms for graph drawing, including sophisticated features like SPQR-trees, planarity tests, graph planarization, and orthogonal layout.

http://www.ogdf.net/

?

?

http://ogp.me/

?

?

http://openaccess.city.ac.uk/15378/

http://www.openscenegraph.org/

?

?

The Open Source Java Graph Library

JGraph is a freely available Java Graph Component for the visualization and layout of graphs.

http://www.jgraph.com/

http://orgnet.com/index.html

OrientDB

?

https://www.padowan.dk/

https://www.padowan.dk/download/

Pajek

Pajek - a Package for Large Network Analysis
This program runs under Windows NT/9x and provides some analysis tools for large networks and graph-drawing capabilities.

http://vlado.fmf.uni-lj.si/pub/networks/pajek/

http://pajek.imfm.si/doku.php

?

Petersen

http://www.mathcove.net/petersen/lessons/intro?les=0

?

http://www.dasi.msstate.edu/projectVisualization.php

http://eclectic.ss.uci.edu/~drwhite/pgraph/p-graphs.html

?

Piccolo

?
PIGALE

PIGALE - Public Implementation of a Graph Algorithm Library and Editor
PIGALE is a graph editor and an algorithm library essentially concerned with planar graphs. Written in C++ and interfaced with the Qt library, it is particularly intended for graph theoretical research. PIGALE is released under GPL.
http://pigale.sourceforge.net/

?

?

?

http://www.graphpad.com/scientific-software/prism/

Prefux
Prefux is a data visualization library that aims to migrate the Prefuse library to JavaFX

?

Prefuse

http://www.prefuse.org

https://julian.pustkuchen.com/en/node/497

?

PROgrammed Graph REwrting Systems (PROGRES)

offers a visual and operational specification language for defining graphs, transformation rules that is combined with the environment for executing specifications in this language.

PyMol
PyMol

https://aur.archlinux.org/packages/python-graph-tool/

?

python-graph, GitHub repository,

https://github.com/pmatiello/pythongraph/

http://www.r-project.org/

?

Rational Rose
Rational Rose

http://rawgraphs.io/

?

http://regiograph.gfk.com/

?

?

The graph package

http://robertdick.org/python/mods.html

http://www.sagemath.org/

http://www.sagemath.org/doc/reference/graphs/

?

SAS/GRAPH

Software to Create Graphs on the Web

SAS Institute Inc., Cary, NC

http://sigmajs.org/

?

http://graph.seul.org/

?https://graph-tool.skewed.de/

https://graph-tool.skewed.de/

?

?

?

http://pycallgraph.slowchop.com/en/master/

?

https://www.smartdraw.com/

?

Snoopy

A tool to design and execute graph based formalisms

Social Cosmo Browser

http://socnetv.sourceforge.net/

?http://vis.stanford.edu/papers/graphprism

http://www.stanford.edu/group/sonia/

stinger

http://www.cc.gatech.edu/stinger

stixar-graphlib

code.google.com/p/stixargraphlib/
A java library of efficient graph algorithms

https://www3.cs.stonybrook.edu/~algorith/implement/north/implement.shtml

?

http://strategoxt.org/Tools/GraphTools

?

TALE: A Tool for Approximate Large Graph Matching
Yuanyuan Tian, Jignesh M. Patel
EECS Department, University of Michigan,
Ann Arbor, Michigan, USA
{ytian, jignesh}@eecs.umich.edu

TALE

A Tool for Approximate Large Graph Matching

http://www.tandd.com/software/td_graph.html

?

?

?

http://www.teraplot.com/

?

?

ThingSpan

http://www.objectivity.com/

?

TGFF

?

?

?

Tom Sawyer
Tom Sawyer Perspectives
Tom Sawyer Visualization
Tom Sawyer Layout
Tom Sawyer Analysis

GLT and GET

Tom Sawyer Software

http://www.tomsawyer.com/
https://www.tomsawyer.com/
Tom Sawyer Softwares GRAPH LAYOUT TOOLKIT(GLT) and GRAPH EDITOR TOOLKIT(GET)?

Graph analysis and data visualization software that helps buildapplications to visually present critical information from all types of relational data. Free demonstration available.

?

?

http://www.touchgraph.com/navigator

?

TreeGraph

http://treegraph.bioinfweb.info/

Tulip

Tulip

http://tulip.labri.fr/

?

?

http://tulip.labri.fr/

System dedicated to the visualization of huge graphs. It manages graphs with a number of elements (nodes and edges) up to 500,000 on a personal computer. It features 3D visualization and modification. GPL.

?

UbiGraph

ubietylab.net/ubigraph/

a tool for visualizing dynamic graphs

?

http://compilers.cs.ucla.edu/avrora/cfg.html

?

uDraw(Graph)

Graph Drawing Software

Draws automatically large, directed graphs in high quality. It includes a graph editor, navigation features, an API for use by other programs and is available for Windows, Linux, FreeBSD and Solaris in English and German.

http://www.informatik.uni-bremen.de/agbkb/graph-visualization/?

http://www.informatik.uni-bremen.de/uDrawGraph/en/index.html

?

?

https://www.bioinf.uni-leipzig.de/Software/GraphProducts/

http://www.rw.cdl.uni-saarland.de/~sander/html/gstools.html

http://www.dia.uniroma3.it/~compunet/www/view/group-tools.php?id=gd

?

very_nauty lib

keithbriggs.info/very_nauty.html

C library of graph algorithms

?

Visual Environment for Graph Grammar Induction and Engineering (VEGGIE)

is a tool which supports graph parsing to analyze the graphical user interface

?

VGJ

a graph drawing software

?http://visant.bu.edu/

?

VisANT

VisnaCom

On the pages of VisnaCom (in german) an editor for compound graphs is presented. It was created in the scope of two diploma theses supported by Marcus Raitner at the ?ffnet einen internen Link im aktuellen Fensterchair of Prof. Dr. Franz Brandenburg. Both diploma theses are based on results of the dissertation "Efficient Visual Navigation of Hierarchically Structured Graphs" of Marcus Raitner.
http://www.fim.uni-passau.de/en/fim/faculty/chairs/theoretische-informatik/projects/visnacom.html
http://www.fim.uni-passau.de/?id=441

?

?

http://www.visualcomplexity.com/vc/blog/?page_id=7

?

http://www.visualdatatools.com/DataGraph/

?

Visual Paradigm

The Visualization Toolkit (VTK)

Walrus - Graph Visualization Tool

http://www.caida.org/tools/visualization/walrus/?

https://www.caida.org/tools/visualization/walrus/?

https://www.caida.org/tools/visualization/walrus/Walrus is a tool for interactively visualizing large directed graphs in three-dimensional space. By employing 3D hyperbolic geometry to display graphs under a fisheye-like distortion, it provides a display that simultaneously shows local detail and the global context.

?

We3Graph

Web 3DNA

?

http://webcodetools.com/open-graph-generator

?

Web Community Chart

WebGL

http://webgraph.di.unimi.it/

?

?

WiGis

WilmaScope

World flights

yED

yFiles

http://www.yworks.com/
https://www.yworks.com/products/yed

https://www.yworks.com/products/yed

http://www.yworks.com/en/index.html

?

yFiles for Java

http://www.yworks.com/en/products_yfiles_about.htm

An extensive Java class library that provides algorithms and components for analyzing, viewing and layouting graphs, diagrams and networks.

?

?

?

?

?

?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?

graph databases
?
?
?
?
?
?
?
?

graph theory libraries
?

?

Annas

Java framework designed for developers and researchers in the fields of graph theory.

https://github.com/gt4j/annas

Open source graph theory Java library http://annas.gt4j.org
?

?

The Boost Graph Library (BGL)

http://www.boost.org/doc/libs/1_35_0/libs/graph/doc/index.html
?
?
GoVisual

GoVisual-API is a library of layout algorithms that can be integrated into C++, .NETor Java applications. Includes advanced layout for UML diagrams and cluster diagrams.

http://www.oreas.com/

?
?
?
?
?
?
?
?
?

?

Ref

?

University of Passau? Prof. Dr. Franz Brandenburg
http://www.fim.uni-passau.de/en/fim/faculty/chairs/theoretische-informatik/projects.html

?
?
?
?


Graph Studies

graph_studies.html

zzz_graph_general_ref.htm
zzz_graphdocs.html

Books

Andrew B. Kahng and Ion Mandoiu. RMSTPack: Rectilinear minimum spanning tree algorithms.
http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/RSMT/RMST/

Bang-Jensen, JØrgen and Gutin, Gregory: Digraphs - Theory, Algorithms and Applications, Springer-Verlag, 15th August 2007, p772 ..............................25?????

Baniassad, Elisa L A: Design pattern rationale graphs: linking design to source PhD Thesis Dec 2002 p196

Bondy, J.A. and Murty, U.S.R.: Graph Theory, Springer, 2008, p666 .........................245

Bondy, J. A. and Murty, U. S. R.: Graph theory with applications Elsevier 1982 p270

M. Borah, R. M. Owens, and M. J. Irwin. An edge based heuristic for Steiner routing. 13(12):1563–1568, December 1994.

Buluc, Aydin et al: Recent Advances in Graph Partitioning Nov 2013 p36

A. E. Caldwell, A. B. Kahng, and I. L. Markov. VLSI CAD Bookshelf.

H. Chen, C. Qiao, F. Zhou, and C.-K. Cheng. Refined single trunk tree: A rectilinear Steiner tree generator for interconnect prediction. In Proc. ACM Intl. Workshop on System Level Interconnect Prediction, pages 85–89, 2002.

http://www.gigascale.org/bookshelf/.

Chris Chu. FLUTE: Fast lookup table based technique for RSMT construction and wirelength estimation.
http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/RSMT/

C. Chu, Y. Wong. Fast and Accurate Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. In Proc. Intl. Symp. on Physical Design, pages 28-35, 2005..................4

COUPRIE, Camille: Graph-based variational optimization and applications in computer vision PhD Thesis Oct 2011 p169

Diestel, Reinhard: Graph Theory, 2005, Springer, 2005, p422..................................50

@@@@@@@@@@@@@@@@@@

GeoSteiner – software for computing Steiner trees. http://www.diku.dk/geosteiner/

Golumbic, Martin Charles: Algorithmic Graph Theory and Perfect Graphs 2ed, ELSEVIER, 2OO4, p338 ..........

Golumbic, Martin Charles: An Introduction to Algorithmic Graph Theory, Nov 2011, Part 1 p14.

Graph Algorithms Aug 2012 p500 ......................... 20

Griffin, Christopher: Graph Theory Penn State Math 485 Lecture, 2011-2012, p173

J. Griffith, G. Robins, J. S. Salowe, and T. Zhang. Closing the gap: Near-optimal Steiner trees in polynomial time. IEEE Trans. Computer-Aided Design, 13(11):1351–1365, November 1994.

M. Hanan. On Steiner’s problem with rectilinear distance. SIAM Journal of Applied Mathematics, 14:255– 265, 1966.Hwang, Frank K.; RICHARDS, Dana S. and WINTER, Pawel: The Steiner tree problem p350

Harary Graph theory p281.pdf

Harju Graph theory p100.pdf

How to Partition a Billion-Node Graph p12

F. K. Hwang. On Steiner minimal trees with rectilinear distance. SIAM Journal of Applied Mathematics, 30:104–114, 1976.

F. K. Hwang, D. S. Richards, and P.Winter. The Steiner tree problem. Annals of Discrete Mathematics, 1992. Elsevier Science Publishers.

Joyner, David , Van Nguyen, Minh, and Cohen, Nathann: Algorithmic Graph Theory, Version 0.3, 19 March 2010, p105 ?????????????

Joyner, David , Van Nguyen, Minh , and Cohen, Nathann: Algorithmic Graph Theory, Version 0.7, March 24, 2013, p322

Kaderali, Firoz; Poguntke, Werner: Graphen, Algorithmen und Netze, 2007 p478 ....................28

Koller, Daphne and Friedman, Nir: Probabilistic Graphical Models Principles and Techniques The MIT Press 2009 p1270

LOUREIRO, Rui: Bond Graph Model Based on Structural Diagnosability and Recoverability Analysis : Application to Intelligent Autonomous Vehicles PhD Thesis Dec 2012 p173

I. I. Mandoiu, V. V. Vazirani, and J. L. Ganley. A new heuristic for rectilinear Steiner trees. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, 1999.

Marx, Dániel: Algorithmic graph structure theory, February 27, 2013????????????

Milanic, Martin: Algorithmic Graph Theory Part III Perfect Graphs and Their Subclasses, March 2013, p72

Mosina, Natalia: PROBABILITY ON GRAPHS AND GROUPS: THEORY AND APPLICATIONS p150 PhD Thesis 2009

Motulsky, Harvey: GraphPad Prism Version 4 Users's Guide 2003 p176

Pal, Rajat Kumar and Sarma, Samar Sen: An Encounter with Graphs, Journal of Physical Sciences, Vol. 10, 15 November, 2006, pages 188 – 200, p13

Prakasam, Pragadeesh et al: A multilevel cooperative search algorithm for the graph colouring problem p4

Preis, Robert: Analyses and Design of Efficient Graph Partioning Methods, PhD Dissertation, July 2000, p140

Ray, Santanu Saha: Graph Theory with Algorithms and its Applications In Applied Science and Technology, Springer India 2013???????????

Shrinivas S.G. et. al., APPLICATIONS OF GRAPH THEORY IN COMPUTER SCIENCE AN OVERVIEW, International Journal of Engineering Science and Technology Vol. 2(9), 2010, 4610-4621

Sinha Experimental Study of A Novel Variant of Fiduccia Mattheyses(FM) Partitioning Algorithm p6

Simonovits, Miklos: Introduction to Extremal Graph Theory, 2006?????????

Studeny, Milan and Vomlel, Jirí: Proceedings of the Third European Workshop on Probabilistic Graphical Models September 12?15, 2006 p344

Tazari, Siamak: Algorithmic Graph Minor Theory: Approximation, Parameterized Complexity, and Practical Aspects, PhD Dissertation, July 2010, p224 ................... 21

Van Dooren, Paul: Graph Theory and Applications August 2009 p108???????

van Steen, Maarten: An Introduction to Graph Theory and Complex Networks, Version: January 2010???p287????????? 3-16

Veksler, Olga: Efficient graph based energy minimization methods in computer vision PhD Thesis Aug 1999 p100

Natarajan Viswanathan and Chris Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In Proc. Intl. Symp. on Physical Design, pages 26–33, 2004.

Wainwright, Martin J et al: Graphical models, exponential families, and variational inference Sept 2003 p103

Wainwright, Martin J and Jordan, Michael I. : Graphical models, exponential families, and variational inference p305 Foundations and TrendsR in Machine Learning Vol. 1, Nos. 1–2 (2008) 1–305

Warme, David M; Winter, Pawel and Zachariasen, Martin: Exact algorithms for plane Steiner tree problems: A computational study, April 1998, p34........................

D. M. Warme, P. Winter, and M. Zachariasen. Exact algorithms for plane Steiner tree problems: A computational study. In D.Z. Du, J.M. Smith, and J.H. Rubinstein, editors, Advances in Steiner Trees, pages 81–116. Kluwer Academic Publishers, 2000.

Wu Graph Theory p340 ???????????????????

Zhou, Hai: Efficient Steiner tree construction based on spanning graphs, ISPD’03, April 6–9, 2003, Monterey, California, USA, p6 ......................

Hai Zhou. Efficient Steiner tree construction based on spanning graphs. In Proc. Intl. Symp. on Physical Design, pages 152–157, 2003.

H. Zhou, N. Shenoy, and W. Nicholls. Efficient spanning tree construction with delaney triangulation. Information Processing Letters, 81(5), 2002.

C. Berge, Theory of Graphs and Its Applications. Methuen, London (1962).

C. Berge, Perfect graphs. Six Papers on Graph Theory. Indian Statistical
Institute, Calcutta (1963) 1-21.

Bondy BEAUTIFUL CONJECTURES IN GRAPH THEORY p45
Adrian Bondy

Bondy Graph Theory 2008 p654.pdf

Bondy Graph Theory 2008 p654 .......................... okokok

Bondy, J. A. and Murty, U. S. R.: Graph theory with applications Elsevier 1982 p270 .....................okokok

Bondy Graph Theory with Applications 1982 p270.pdf
Bondy Graph theory 2008 p666.pdf

A. Brandst?adt, V.B. Le, J.P. Spinrad, Graph Classes, SIAM Monographs Discr. Math. and
Appl. SIAM, Philadelphia, 1999.

N. L. Biggs, E. K. Lloyd, and R. J. Wilson, Graph Theory, 1736–1936. Oxford
University Press, London (1976).

G. Chartrand and L. Lesniak, Graphs & Digraphs, Fourth Edition. Chapman
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? G. Chartrand and P. Zhang, Introduction to Graph Theory. McGraw-Hill,
Boston (2005).

Chung Open problems of Paul Erd?os in graph theory p44
F. R. K. Chung

Diestel Graph Theory2000 p322.pdf
Diestel Graph Theory2005 p422.pdf

Griffin Graph Theory: Penn State Math 485 Lecture Notes p173
Christopher Griffin

J. Gross and J. Yellen, Graph Theory and Its Applications, Second Edition.
Chapman & Hall/CRC, Boca Raton, FL (2006).
? J. Gross and J. Yellen (editors), Handbook of Graph Theory. Chapman &
Hall/CRC, Boca Raton, FL (2004).

Guichard An Introduction to Combinatorics and Graph Theory p149
David Guichard

Gusfield Graphs and Graph Theory in Computational Biology p138.ppt
Harary Graph theory p281.pdf
Harris Combinatorics and Graph Theory p392.pdf

Harju GRAPH THEORY p100
Tero Harju

A. J.W. Hilton and R. J. Wilson, Snarks. Graph Theory and Its Applications:
East and West. Ann. New York Acad. Sci. (1986) 606-622.

D. K¨onig, Theorie der endlichen und unendliehen Graphen. Teubner, Leipzig
(1936).

Mason Graph Theory and Networks in Biology p52.pdf
Mugnolo Graphentheorie p118.pdf

O. Ore, Theory of Graphs. Math. Soc. Colloq. Pub., Providence, RI (1962).

R. Rashidi, The Theory and Applications of Stratified Graphs. Ph.D. Disser-
tation, Western Michigan University (1994).

Ray Graph Theory with Algorithms and its Applications p222.pdf
Spinrad Graph theory p245.pdf

Ruohonen GRAPH THEORY p114
Keijo Ruohonen

Sudakov Graph Theory p78
Benny Sudakov

Van Dooren Graph Theory and Applications p110

van Steen Graph Theory and Complex Networks p287.pdf

J. J. Watkins and R. J. Wilson, A survey of snarks. Graph Theory, Combinatorics,
and Applications. Wiley-Interscience Publ., Wiley, New York (1991)
1129-1144.

West INTRODUCTION TO GRAPH THEORY 2nd Edition Solution Manual p260.pdf

R. A. Wilson, Graphs, Colourings, and the Four-Colour Theorem. Oxford
University Press, Oxford (2002).

Wilson Graph Theory and Spectral Methods for Pattern Recognition p103.pdf

Wilson Introduction to Graph Theory p180.pdf ............. okokok

000Bader Graph Partitioning and Graph Clustering p258.pdf
000BangJensen Digraphs Theory algorithms and applications p772.pdf
000Berge HYPERGRAPHS Combinatorics of Finite Sets p267.pdf
000Brouwer Spectra of graphs p229.pdf
000CHARTRAND Chromatic Graph Theory p498.pdf
000Dasgupta Algorithms p318.pdf
000Demaine Graph Algorithms p500.pdf
000Dongarra Graph Algorithms in the Language of Linear Algebra p372.pdf
000Gallian A Dynamic Survey of Graph Labeling p384.pdf
000Golumbic Algorithmic Graph Theory and Perfect Graphs 2ed p338.pdf
000Joyner Algorithmic Graph Theory p322.pdf
000Marx Algorithmic graph structure theory p255.pdf
000Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346.pdf
000Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf
000van der Hofstad Random Graphs and Complex Networks. Vo. I p328.pdf
000van der Hofstad Random Graphs and Complex Networks. Vol I p312.pdf
Bondy Graph Theory 2008 p654.pdf
Bondy Graph Theory with Applications 1982 p270.pdf
Bondy Graph theory 2008 p666.pdf
Diestel Graph Theory2000 p322.pdf
Diestel Graph Theory2005 p422.pdf
Griffin Graph Theory Penn State Math 485 Lecture Notes p173.pdf
Harary Graph theory p281.pdf
Mugnolo Graphentheorie p118.pdf
Ray Graph Theory with Algorithms and its Applications p222.pdf
Ruohonen GRAPH THEORY p114.pdf
Seventh Cologne-Twente Workshop on Graphs and Combinatorial Optimization p204.pdf
Smithers Graph Theory for the Secondary School Classroom p151.pdf
Spinrad Graph theory p245.pdf
Submodular Function_2ed p881.pdf
Van Dooren Graph Theory and Applications p110 .pdf
West INTRODUCTION TO GRAPH THEORY 2nd Edition Solution Manual p260.pdf
Wilson Introduction to Graph Theory p180.pdf
van Steen Graph Theory and Complex Networks p287.pdf

de/

4 Graphentheorie p96.pdf
Ausgewahlte Kapitel aus der Graphentheorie p54.pdf
Diestel Graphentheorie II p326.pdf
Eidmann Algorithmische Graphentheorie im Unterricht unter Verwendung objektorientierter Datenstrukturen p561.pdf
Gekeler Kombinatorik und Graphentheorie p122.pdf
Graphentheorie p115.pdf
Graphentheorie p422.pdf
Grotschel Graphen- und Netzwerkalgorithmen p218.pdf
Hartmann Highlights aus Graphentheorie Operation Research (Mathematik III) p66.pdf
Jabornegg Spektrale Graphentheorie Graph Sparsification und Eigenwertabschatzungen p99.pdf
KRIESELL Algebraische Graphentheorie p49.pdf
Kaderali Graphen Algorithmen und Netze p478.pdf
Klotz Graphentheorie II p115.pdf
Krumke Graphentheoretische Konzepte und Algorithmen p161.pdf
Mugnolo Graphentheorie p118.pdf
Schelthoff Graphentheorie und Kryptographie p192.pdf
Schwartz Einführung in die Graphentheorie p135.pdf
Srivastav Graphentheorie p79.pdf

fr/

BORIES GRAPHES ET COMBINATOIRE p67.pdf
Blin Algorithmique des graphes p76.pdf
Bondy Theorie des Graphes p706.pdf
Bretto éléments de théorie des graphes p380.pdf
DAVAL Les graphes p50.pdf
Dantal Theorie des graphes Principes et programmation p95.pdf
Durand Theorie des graphes p125.pdf
Gournay Théorie des graphes p197.pdf
Lambiotte Théorie des graphes p59.pdf
Mammeri Théorie des graphes p64.pdf
Maquin Elements de Theorie des Graphes et Programmation Lineaire p69.pdf
Miage Theorie des graphes et algorithmes p64.pdf
Rapine Théorie des graphes p116.pdf
Rigo Theorie des graphes p176.pdf
Roux Theorie des graphes p124.pdf
Régin Théorie des Graphes p302.pdf
Sais Theorie des graphes p125.pdf
Solnon Théorie des graphes et optimisation dans les graphes p53.pdf

gk/

Θηλυκ?? Σημει?σει? στη ΘΕΩΡΙΑ ΓΡΑΦΗΜΑΤΩΝ p117.pdf
Παπαδ?πουλο? Θεωρ?α Γραφημ?των p104.pdf
Παπαδ?πουλο? Θεωρ?α Γραφημ?των p130.pdf

ru/

Burkatofskaya Теория графов Part 1 p203.pdf
Domnin Элементы теории графовp144.pdf
Kariof Graph theory russian p418.pdf
Lazarev Graph theory Russian p220.pdf
Melnikov Элементы теории графов p108.pdf
Nocoba Элементы теории графов p107.pdf
Nocof Элементы теории графов p107.pdf
Penjam Теория графовp50.pdf
Зарипова Дискретная математика Часть III Теория графов p179 (2).pdf
Зарипова Дискретная математика Часть III Теория графов p179.pdf
Захарова ТЕОРИЯ ГРАФОВ p60.pdf
Лакеев ЭЛЕМЕНТЫ ТЕОРИИ ОБЫКНОВЕННЫХ ГРАФОВ p84.pdf
ЛеденеваТ АЛГОРИТМЫ ТЕОРИ И ГРАФОВ КОДОВЫ ЕГРАФЫ p89.pdf

>>> Documents

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000graph_resources.docx
00graph_intro.docx
00graph_openproblems.docx
graph_actions.docx
graph_cluster.docx
graph_coloring.docx
graph_coupling.docx
graph_covering.docx
graph_crossing.docx
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graph_matching.docx
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graph_vlsi_other_phases.docx
graph_vlsi_reconfigurable_cdfg.docx
graph_vlsi_reconfigurable_summary.docx

>>>Otherlanguages/

de/

Diestel Graphentheorie II p326.pdf

Eidmann Algorithmische Graphentheorie im Unterricht unter Verwendung objektorientierter Datenstrukturen p561

Gekeler Kombinatorik und Graphentheorie p122

Grotschel Graphen- und Netzwerkalgorithmen p218

Hartmann Highlights aus Graphentheorie Operation Research (Mathematik III) p66
Robert Hartmann

Jabornegg Spektrale Graphentheorie Graph Sparsification und Eigenwertabschatzungen p99

Krumke Graphentheoretische Konzepte und Algorithmen p161

Mugnolo Graphentheorie p118.pdf ................... okokok

Schwartz Einführung in die Graphentheorie p135 ......... okokok

fr/

Bretto éléments de théorie des graphes p380

Bondy Theorie des Graphes p706.pdf

Dantal Theorie des graphes Principes et programmation p95.pdf

Gournay Théorie des graphes p197.pdf

Maquin Elements de Theorie des Graphes et Programmation Lineaire p69

Rapine Théorie des graphes p116

Rigo Theorie des graphes p176.pdf

Roux Theorie des graphes p124.pdf

Sais Theorie des graphes p125 .................. okokok

gk/

Θηλυκ?? Σημει?σει? στη ΘΕΩΡΙΑ ΓΡΑΦΗΜΑΤΩΝ p117.pdf

Παπαδ?πουλο? Θεωρ?α Γραφημ?των p104 okokok

Παπαδ?πουλο? Θεωρ?α Γραφημ?των p130 okokok

ru/

Karpob Graph theory russian p418.pdf

Lazarev Graph theory Russian p220.pdf

Nocoba Элементы теории графов p107.pdf

Зарипова Дискретная математика Часть III Теория графов p179.pdf

000extremal_graph_theory

000extremal_graph_theory.docx

extremal_graph_theory.docx

Alon Problems and results in Extremal Combinatorics Part I p21.pdf
Alon Problems and results in Extremal Combinatorics p18.pdf
Aouchiche Variable Neighborhood Search for Extremal Graphs 20 Automated Comparison of Graph Invariants p20.pdf
Balbuena Extremal K(s,t)-free bipartite graphs p14.pdf
Bollobás Graphs Extremal and Random p8.pdf
Borgs Counting Graph Homomorphisms p45.pdf
Chapter 10 Extremal Theory p25.pdf
Chernikov Applications of model theory in extremal graph combinatorics p30.pdf
Diwan Extremal Graph Theory p33.pptx
ERD?S COMPACTNESS RESULTS IN EXTREMAL GRAPH THEORY p14.pdf
Engbers Graph theory — to the extreme p76.pdf
FüREDI Extremal Hypergraphs and Combinatorial Geometry p10.pdf
Garnick Extremal Graphs without Three-Cycles or Four-Cycles p9.pdf
Glasscock What is a Graphon p7.pdf
Grzesik Flag Algebras in Extremal Graph Theory p63.pdf
Hartman EXTREMAL PROBLEMS IN GRAPH THEORY p97.pdf
Hernando Extremal Graph Theory for Metric Dimension and Diameter 1 p5.pdf
Hernando Extremal Graph Theory for Metric Dimension and Diameter p28.pdf
Kang Extremal Graph Theory p3.pdf
Liu Discrete Geometry and Extremal Graph Theory p8.pdf
Markstrom Extremal graphs for some problems on cycles in graphs p15.pdf
Martin Notes on Extremal Graph Theory p101.pdf
McClintock Extremal Graph Theory for Book-Embeddings p64.pdf
Morris Extremal and Probabilistic Combinatorics p85.pdf
Nikiforov Some new results in extremal graph theory p41.pdf
Polak On the applications of Extremal Graph Theory to Coding Theory and Cryptography p14.pdf
Shapira Extremal Graph Theory p53.pdf
Simonovits Extremal Graph Problems Degenerate Extremal Problems and Supersaturated Graphs p25.pdf
Sperfeld Semidefinite programming in extremal graph theory p85.pdf
Stein Extremal Infinite Graph Theory p41.pdf
Stein Extremal graph theory p171.pdf
Sudakov Turans theorem variations and generalizations p26.pdf
Szemeredi Extremal graph theory p33.pdf
Thomason Extremal graph theory p3.pdf
Thomason Extremal_Graph_Theory_2013 p37.pdf
Ustimenko On Extremal Graph Theory for Directed Graphs and its Applications to Information Security p2.pdf
Vetrík Selected Topics in the Extremal Graph Theory p6.pdf
Yilma Results in Extremal Graph and Hypergraph Theory p99.pdf

Graph Embedding

000Baingana Embedding Graphs under Centrality Constraints p54.pdf
000Behzadi An Improved Spring-based Graph Embedding Algorithm and LayoutShow a Java Environment for Graph Drawing p144.pdf
000Cardinal The Complexity of Simultaneous Geometric Graph Embedding p71.pdf
000Chowdhury Point-Set Embeddings of Planar Graphs with Fewer Bends p67.pdf
000Cooley EMBEDDING PROBLEMS FOR GRAPHS AND HYPERGRAPHS p234.pdf
000Gibert Graph Embedding in Vector Spaces p66.pdf
000Gibert Vector Space Embedding of Graphs via Statistics of Labelling Information p162.pdf
000Grilli Automated Local Linear Embedding with an application to microarray data p92.pdf
000Heath ALGORITHMS FOR EMBEDDING GRAPHS IN BOOKS p134.pdf
000LUQMAN Fuzzy Multilevel Graph Embedding for Recognition Indexing and Retrieval of Graphic Document Images p186.pdf
000Mumford Drawing Graphs for Cartographic Applications p144.pdf
000Potoczak Survey of Graph Embeddings into Compact Surfaces p117.pdf
000Riesen Classification and Clustering of Vector Space Embedded Graphs p344.pdf
000Shaw Graph Embedding and Nonlinear Dimensionality Reduction p108.pdf
ARORA Expander Flows, Geometric Embeddings and Graph Partitioning p30.pdf
Alipanahi Guided Locally Linear Embedding p25.pdf
Asano A Linear-Space Algorithm for Distance Preserving Graph Embedding p23.pdf
Azary Grassmann Learning for Recognition and Classification p132.pdf
Bai Heat Kernels, Manifolds and Graph Embedding p9.pdf
Baingana CENTRALITY-CONSTRAINED GRAPH EMBEDDING p5.pdf
Belkin Laplacian Eigenmaps and Spectral Techniques for Embedding and Clustering p7.pdf
Brand A unifying theorem for spectral embedding and clustering p8.pdf
Brandes Colored Simultaneous Geometric Embeddings and Universal Pointsets p24.pdf
Brink Spherical parameterization methods for 3d surfaces p152.pdf
Britt Embedding Logical Qubits into the D-Wave Hardware Graph p30.pptx
Bunke_Applied_Pattern_Recognition p246.pdf
Busa-Fekete Locally Linear Embedding and its Variants for Feature Extraction p6.pdf
CHUNG EMBEDDING GRAPHS IN BOOKS A LAYOUT PROBLEM WITH APPLICATIONS TO VLSI DESIGN p26.pdf
Cabello Algorithms for embedded graphs p93.pdf
Cappos Simultaneous Graph Embedding with Bends and Circular Arcs p12.pdf
Cardinal The Complexity of Simultaneous Geometric Graph Embedding p14.pdf
Chang Robust Locally Linear Embedding p10.pdf
Chang Robust Locally Linear Embedding p25.pdf
Charikar Spectral Embedding of k-Cliques Graph Partitioning and k-Means p27.pdf
Cvetkovski Hyperbolic Embedding and Routing for Dynamic Graphs p7.pdf
DeMillo Combinatorial graph embedding p87.pdf
Dehm-Andone Einflüsse des Filterentwurfs auf die Empfangsqualit?t breitbandiger Funküberwachungsempf?nger p166.pdf
Dell Graph Embedding and Extensions A General Framework for Dimensionality Reduction p21.ppt
Dolev PLANAR EMBEDDING OF PLANAR GRAPHS p15.pdf
Eades Symmetric Graph Drawing p28.pdf
Erten Simultaneous Embedding of a Planar Graph and its Dual on the Grid o17.pdf
Ferrer A Recursive Embedding Approach to Median Graph Computation p11.pdf
Gagarin Embedding Graphs Containing K5-Subdivisions p17.pdf
Gagarin Embeddings of Small Graphs on the Torus p19.pdf
Gassner Simultaneous Geometric Graph Embeddings p12.pdf
Goodwin Imbedding Problems in Graph Theory p27.pdf
Graham Isometric graph embeddings p18.pdf
Graph Embedding.pdf
GraphTA-Valveny.pptx
Groenen Multidimensional Scaling p14.pdf
Harel Graph Drawing by High-Dimensional Embedding p20.pdf
He Graph Embedding with Constraints p6.pdf
Horaud A Short Tutorial on Graph Laplacians, Laplacian Embedding, and Spectral Clustering p43.pdf
Huang Cross-view Graph Embedding p12.pdf
Jameson An Address Event Representation (AER) Multicast Router for Colour Vision p200.pdf
Jouili Graph Embedding Using Constant Shift Embedding p12.pdf
Kermarrec Distributed Social Graph Embedding p6.pdf
Keselman Many-to-Many Graph Matching via Metric Embedding p8.pdf
Kleinberg Isomorphism and Embedding Problems for Infinite Limits of Scale-Free Graphs p10.pdf
Kong An Iterative Locally Linear Embedding Algorithm p8.pdf
Lee Locally Linear Embedding versus Isotop p8.pdf
Liu Projective Nonnegative Graph Embedding p11.PDF
Los Embedding Groups of Graph Automorphisms in Surfaces p20.pdf
Luo Cauchy Graph Embedding p8.pdf
Luo Non-negative Laplacian Embedding p10.pdf
Luqman Fuzzy multilevel graph embedding p15.pdf
MOHAR A LINEAR TIME ALGORITHM FOR EMBEDDING GRAPHS IN AN ARBITRARY SURFACE p21.pdf
Matsubayashi Separator-Based Graph Embedding into Multidimensional Grids with Small Edge-Congestion p30.pdf
Najim More faithfulness graph embedding p9.pdf
Nishana Graph Embedding and Dimensionality Reduction - A Survey p6.pdf
Perrault-Joncas Directed Graph Embedding an Algorithm based on Continuous Limits of Laplacian-type Operators p9.pdf
Pizzonia Minimum Depth Graph Embedding p12.pdf
Raveaux Graph Embedding Problem p37.pdf
Renz Hierarchical Graph Embedding for Efficient Query Processing in Very Large Traffic Networks p30.pdf
Ridder Supervised locally linear embedding p8.pdf
Robles-Kelly A Riemannian approach to graph embedding p15.pdf
Rodl Hypergraph packing and graph embedding p18.pdf
Sarvottamananda Planar Graphs Planarity Testing and Embedding p151.pdf
Sarvottamananda Planar Graphs, Planarity Testing and Embedding p151.pdf
Saul An Introduction to Locally Linear Embedding p13.pdf
Saxe Two papers on graph embedding problems p41.pdf
Shaw Structure Preserving Embedding p8.pdf
Shaw Visualizing Graphs with Structure Preserving Embedding p6.pdf
Song Clustered Embedding of Massive Social Networks p12.pdf
Stefano Graph embedding via dissimilarity mapping for network comparison p4.pdf
Tamassia On-line Planar Graph Embedding p39.pdf
Verbeek Metric Embedding, Hyperbolic Space, and Social Networks p10.pdf
Wilkinson Multidimensional Scaling p30.pdf
Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p12.pdf
Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction p54.ppt
Yan Graph Embedding and Extensions A General Framework for Dimensionality Reduction1 p12.pdf
Yang Non-Negative Graph Embedding p8.pdf
Yang Variational Graph Embedding for Globally and Locally Consistent Feature Extraction p16.pdf
Yeh VLSI layouts of complete graphs and star graphs p7.pdf
Yu Topology Mapping for Blue GeneL Supercomputer p13.pdf
Zhang Robust (Semi) Nonnegative Graph Embedding p17.pdf
Zhao Graph Attribute Embedding via Riemannian Submersion Learning p32.pdf
doc/

>>> Documents

graph_embedding_def.docx

graph_embedding_def_XXX.htm
graph_embedding_defothers.docx
graph_embedding_defothersXXX.htm
graph_embedding_ref.docx

????????????

graph_embedding_refXXX.docx

graph_embedding4ic_ref.docx

graph_laplacian.docx

graph_packing.docx

Hypergraph

Berge HYPERGRAPHS Combinatorics of Finite Sets p267.pdf
Gogoi Algorithm to color a Circuit Dual Hypergraph for VLSI Circuit p6.pdf
THIYAGARAJAN HYPER GRAPH AND COPROCESSOR DESIGN FOR VLSI PARTITIONING PROBLEMS p5.pdf

>>>Documents

hypergraph_intro.docx
hypergraph_models_fpga.docx
hypergraph_models_fpga.pdf
hypergraph_models_fpga_def.docx
hypergraph_models_fpga_def_original.docx
hypergraph_models_fpga_original.docx
hypergraph_models_fpga_ref.docx
hypergraph_types.docx

Open Problems

BONATO Sketchy Tweets Ten Minute Conjectures in Graph Theory p8.pdf
Brandenburg Selected Open Problems in Graph Drawing p20.pdf
Chung Open problems of Paul Erdos in graph theory p44.pdf
Eppstein Some Open Problems in Graph Theory and Computational Geometry p15.pdf
Ghosh Unsolved Problems in Visibility Graph Theory p11.pdf
Hansen What Forms Do Interesting Conjectures Have in Graph Theory p22.PDF
Lovasz Graph homomorphisms Open problems p10.pdf
Sloane Unsolved Problems in Graph Theory Arising from the Study of Codes p13.pdf
Zentz The Oberwolfach Problem in Graph Theory p7.pdf

TSP

ANGINIOL Self-Organizing Feature Maps and the Travelling Salesman Problem p5.pdf
ASCHEUER Solving the Asymmetric Travelling Salesman Problem with Time Windows by Branch-and-Cut p35.pdf
Afaq On the Solutions to the Travelling Salesman Problem using Nature Inspired Computing Techniques p9.pdf
Agatz Optimization Approaches for the Traveling Salesman Problem with Drone p42.pdf
Angel A dynasearch neighborhood for the bicriteria traveling salesman problem p4.pdf
Antosiewicz Choice of best possible metaheuristic algorithm for the travelling salesman problem with limited computational time quality, uncertainty and speed p10.pdf
Balas Linear Time Dynamic-Programming Algorithms for New Classes of Restricted TSPs A Computational Study p33.pdf
Bar-Yehuda On Approximating A Geometric Prize-Collecting Traveling Salesman Problem With Time Windows p12.pdf
Bartal The Traveling Salesman Problem Low-dimensionality Implies a Polynomial Time Approximation Scheme p10.pdf
Bassetto The Single-Double Balanced Traveling Salesman Problem p16.pdf
Basu Tabu Search Implementation on Traveling Salesman Problem and Its Variations A Literature Survey p11.pdf
Biron The Traveling Salesman Problem Deceptivley Easy to State Notoriously Hard to Solve p31.pdf
Brezina Solving the Travelling Salesman Problem Using the Ant Colony Optimization p5.pdf
Bryant Genetic Algorithms and the Traveling Salesman Problem p34.pdf
Budinich A Neural Network for the Travelling p8.pdf
CERNY Thermodynamical Approach to the Traveling Salesman Problem An Efficient Simulation Algorithm I p11.pdf
Cela The x-and-y-axes travelling salesman problem p3.pdf
Dantzig Solution of a Large-Scale Traveling-Salesman Problem p22.pdf
Demez Combinatorial Optimization Solution Methods of Traveling Salesman Problem p87.pdf
Dorigo Ant colonies for the traveling salesman problem p10.pdf
Dornberger Solving Optimization Problems by Metaheu-ristics Using the Open Opal Framework - Integration of Travelling Salesman Problem and Selected Solvers p20.pdf
Dumitrescu The Traveling Salesman Problem with Pickup and Delivery Polyhedral Results and a Branch-and-Cut Algorithm p31.pdf
Easton Solving the Traveling Tournament Problem A Combined Integer Programming and Constraint Programming Approach p10.pdf
GUTIN THE TRAVELING SALESMAN PROBLEM AND ITS VARIATIONS p40.pdf
Gharan A Randomized Rounding Approach to the Traveling Salesman Problem p65.pdf
Goldengorin How To Make a Greedy Heuristic for the Asymmetric Traveling.pdf
Greco Travelling Salesman Problem p212.pdf
Hahsler TSP – Infrastructure for the Traveling Salesperson Problem p21.pdf
Haque Improving the Solution of Traveling Salesman Problem Using Genetic, Memetic Algorithm and Edge assembly Crossover p4.pdf
Helvig The moving-target traveling salesman problem p22.pdf
Hoffman Traveling salesman problem p9.pdf
Isaacs Algorithms for the Traveling Salesman Problem with Neighborhoods Involving a Dubins Vehicle p6.pdf
JONES THE TRAVELING SALESMAN PROBLEM AND HARMONIC ANALYSIS p9.pdf
Ji The Traveling Salesman and the Quadratic Assignment Problems Integration Modeling and Genetic Algorithm p8.pdf
Johnson The Traveling Salesman Problem A Case Study in Local Optimization p103.pdf
Jones Computation of the Travelling Salesman Problem by a Shrinking Blob p27.pdf
Jozefowiez Multi-objective Meta-heuristics for the Traveling Salesman Problem with Profits p19.pdf
Junger THE TRAVELING SALESMAN PROBLEM p117.pdf
Kanda Using Meta-learning to Classify Traveling Salesman Problems p6.pdf
Kang Benchmarking Algorithms for Dynamic Travelling Salesman Problems p6.pdf
Kumar Assignment and Travelling Salesman Problems with Coefficients as LR Fuzzy Parameters p16.pdf
Laporte The Traveling Salesman Problem An overview of exact and approximate algorithms p17.pdf
Letchford Compact Formulations of the Steiner Traveling Salesman Problem and Related Problems p28.pdf
Letchford Mathematical Programming Approaches to the Traveling Salesman Problem p12.pdf
Li Ant Colony Optimization for the Traveling Salesman Problem Based on Ants with Memory p6.pdf
Lokar Traveling salesman problem p6.doc
Lust The Multiobjective Traveling Salesman Problem A Survey and a New Approach p24.pdf
Mandziuk Solving the Travelling Salesman Problem with a Hopfield - type neural network p18.pdf
Maredia History, Analysis, and Implementation of Traveling Salesman Problem(TSP) and Related Problems p47.pdf
Mattsson The Asymmetric Traveling Salesman Problem p64.pdf
Monnot Approximation algorithms for the traveling salesman problem p22.pdf
Montemanni The robust traveling salesman problem with interval data p21.pdf
Nilsson Heuristics for the Traveling Salesman Problem p6.pdf
PAPADIMITRIOU ON THE APPROXIMABILITY OF THE TRAVELING SALESMAN PROBLEM p20.pdf
Pacha-Sucharzewski Analysis of the Travelling Salesman Problem and an Application of Heuristic Techniques for Finding a New Solution p7.pdf
Pathak Travelling Salesman Problem Using Bee Colony With SPV p5.pdf
Pizlo Traveling Salesman Problem A Foveating Pyramid Model p9.pdf
Potvin The Traveling Salesman Problem A Neural Network Perspective p60.pdf
Rasmussen TSP in Spreadsheets – a Guided Tour p23.pdf
Renaud AN EFFICIENT COMPOSITE HEURISTIC FOR THE SYMMETRIC GENERALIZED TRAVELING SALESMAN PROBLEM p23.pdf
Rostoker Travelling Salesman Problems p56.pdf
Rothe Two solvable cases of the Traveling Salesman Problem p60.pdf
Sadiq The Traveling Salesman Problem Optimizing Delivery Routes Using Genetic Algorithms p6.pdf
Schneider Searching for backbones - an efficient parallel algorithm for the traveling salesman problem p16.pdf
Schneider The time-dependent traveling salesman problem p5.pdf
WANG SIGMA-DELTA QUANTIZATION ERRORS AND THE TRAVELING.pdf
Yatsenko Fast Exact Method for Solving the Travelling Salesman Problem p4.pdf
?tencek Traveling salesman problem p53.pdf

>>> Documents

tsp.docx

tsp1.docx

Combinatorics

000van Lint A course in combinatorics p618.pdf

2001

at least 4 pages a day

53

J.H. VAN LINT

R.M. WILSON

Richard Michael Wilson

Professor of Mathematics at the California Institute of Technology.

Brualdi Introductory combinatorics p618.pdf
Cook Research Trends in Combinatorial Optimization 2009 p565.pdf
Graham Handbook of Combinatorics Vol 2 p640.pdf

Guichard An Introduction to Combinatorics and Graph Theory p141

Keller Applied Combinatorics p345.pdf
Korte Combinatorial optimization theory and algorithms 2007 p646.pdf
MARTELLO Surveys in Combinatorial Optimization p395.pdf
SchrijverZZZ A Course in Combinatorial Optimization p223.pdf

optimization/

Berlier A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms p341.pdf
Chibante Simulated_Annealing Theory with Applications p300.pdf
Dantzig Linear programming vol 1 Introduction p474.pdf
Dantzig Linear programming vol 2 Theory and Extensions p475.pdf
De Jong The Handbook of Evolutionary Computation p940.pdf
Hendler Foundations of Artificial Intelligence p1035.pdf
Hendriks High Level Synthesis Performance Analysis and Code Optimization p105.pdf
Kennedy Swarm intelligence p541.pdf
Vanderbei Linear Programming Foundations and Extensions p466.pdf
Yu Introduction to Evolutionary Algorithms p433.pdf
dos Santos Evolutionary_Computation p582.pdf

>>> Documents

?combinatorics.docx

OperationsResearch

HILLIER INTRODUCTION TO OPERATIONS RESEARCH p1237.pdf

Complexity Theory

Gacs Complexity of Algorithms p242.pdf
Thompson A Complexity Theory for VLSI p106.pdf
Vincius Complexity dichotomy on degree-constrained VLSI layouts with unit-length edges p8.pdf

Discrete Math

discrete_ref.htm

Graph Algorithms

Dasgupta Algorithms p318.pdf

Demaine Graph Algorithms p500.pdf ......................... 269

Dongarra Graph Algorithms in the Language of Linear Algebra p372.pdf

Dijkstra_shortest_path_algorithm/

Peyer A Generalization of Dijkstra's Shortest Path Algorithm with Applications to VLSI Routing p24.pdf

?
Dasgupta Algorithms p318.pdf
Demaine Graph Algorithms p500.pdf
Dijkstra_shortest_path_algorithm/
Dongarra Graph Algorithms in the Language of Linear Algebra p372.pdf

Graph Features

graph_homomorphism/

Borgs Counting Graph Homomorphisms p45.pdf

graph_isomorphism/

Buhler Quantum approaches to the graph isomorphism problem p128.pdf
Rautaray A Novel Algorithm for Isomorphic Graph p4.pdf

graph_features
├<Graph Database>
├<graph description>
├<graph formats>
│ └Bernard GRAPH FILE FORMATS p50.pdf
├<graph forms>
├<graph homomorphism>
│ ├Bacik Structure of Graph Homomorphisms p111.pdf
│ ├Borgs Counting Graph Homomorphisms p45.pdf
│ ├Brewster Graph Homomorphism Tutorial p164.pdf
│ ├CAI GRAPH HOMOMORPHISMS WITH COMPLEX VALUES A DICHOTOMY THEOREM p106.pdf
│ ├HAHN Graph homomorphisms structure and symmetry p60.pdf
│ ├Luksan FRACTIONAL GRAPH HOMOMORPHISMS p46.pdf
│ └Sun A contribution to the theory of signed graph homomorphism bound and Hamiltonicity p156.pdf
├<graph isomorphism>
│ ├00graph_isomorphism.txt
│ ├Augeri ON GRAPH ISOMORPHISM AND THE PAGERANK ALGORITHM p153.pdf
│ ├Babai Graph Isomorphism in Quasipolynomial Time p89.pdf
│ ├Boldi Graph Fibrations, graph isomorphism, and PageRank p34.pdf
│ ├Buhler Quantum approaches to the graph isomorphism problem p128.pdf
│ ├Chandoo Completeness Results for Graph Isomorphism on Restricted Graph Classes p64.pdf
│ ├Grohe Structural and Logical Approaches to the Graph Isomorphism Problem p90.pdf
│ ├Kukluk Algorithm and Experiments in Testing Planar Graphs for Isomorphism p44.pdf
│ ├McKay Practical Graph Isomorphism II p70.pdf
│ ├Muzychuk Graph Isomorphism problem, Weisfeiler-Leman algortihm and coherent configurations p96.pdf
│ └<Subgraph Isomorphism Problem>
│ └Meana Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware p43.pdf
├<graph minor>
│ └Bokal Minor-monotone crossing number p6.pdf
├<graph picture>
├<graph similarity>
├<graph structure>
└<maximal common subgraphs>
├00maximal common subgraphs.txt
└Zhou Finding Maximal k-Edge-Connected Subgraphs from a Large Graph p12.pdf

Graph Operations

graph_clustering/

van Dongen GRAPH CLUSTERING by FLOW SIMULATION p175.pdf

graph_coloring/

Barenboim Distributed Graph Coloring Fundamentals and Recent Developments p160.pdf
Casselgren On Some Graph Coloring Problems p32.pdf
Dvorak New Techniques in Coloring Embedded Graphs p264.pdf

Dvorak New Techniques in Coloring Embedded Graphs p264

Dvorak New Techniques in Coloring Embedded Graphs p284

9

Linial Graph coloring with no large monochromatic components p14.pdf
Maitra Noise Reduction in VLSI Circuits using Modified GA Based Graph Coloring p8.pdf

graph_labeling/

Gallian A Dynamic Survey of Graph Labeling p384.pdf

graph_matching/

Bunke Graph Matching Theoretical Foundations, Algorithms, and Applications p7

Nagel A LOW-POWER VLSI ARCHITECTURE FOR FACE VERIFICATION USING ELASTIC GRAPH MATCHING p4.pdf

graph_operations
├<graph analysis>
├<graph analyzing>
├<graph capturing>
│ └Furlinger Capturing and Visualizing Event Flow Graphs of MPI Applications p10.pdf
├<graph classification>
│ ├Bunke CLASSIFICATION AND CLUSTERING OF GRAPHS BASED ON DISSIMILARITY SPACE EMBEDDING p81.pdf
│ ├FROST Graph Classification with Differential Privacy p38.pdf
│ ├Graph Classification p33.pdf
│ └Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346.pdf
├<graph clustering>
│ ├Bader Graph Partitioning and Graph Clustering p258.pdf
│ ├Schulz Graph Partitioning and Graph Clustering in Theory and Practice p202.pdf
│ ├Seeland Structural Graph Clustering Scalable Methods and Applications for Graph Classification and Regression p206.pdf
│ ├van Dongen GRAPH CLUSTERING by FLOW SIMULATION p173.pdf
│ └van Dongen GRAPH CLUSTERING by FLOW SIMULATION p175.pdf
├<Graph Coloring>
│ ├Barenboim Distributed Graph Coloring Fundamentals and Recent Developments p160.pdf
│ ├Duran Graph Coloring Problems p114.pdf
│ ├Dvorak New Techniques in Coloring Embedded Graphs p284.pdf
│ ├Lidicky Graph coloring problems p106.pdf
│ ├Marx Graph Coloring with Local and Global Constraints p176.pdf
│ └Normann Parallel graph coloring on multi-core CPUs p45.pdf
├<GRAPH COMPRESSION>
├<graph conversion>
├<graph coupling>
├<graph discovery>
├<GRAPH ENUMERATION>
├<graph examine>
├<graph exchange>
├<Graph Indexing>
├<graph interpolation>
├<graph labeling>
│ └Gallian A Dynamic Survey of Graph Labeling p384.pdf
├<graph mining>
│ ├christos GRAPH MINING AND COMMUNI TY EVALUAT ION WI TH DEGENERACY p152.pdf
│ ├Faloutsos Large Graph Mining – Patterns, Tools and Cascade analysis p69.pdf
│ ├Mirrokni Large Scale Graph Mining Theory and Practice p65.pdf
│ ├Rahmani An Introduction to Graph Mining p49.pdf
│ └SKHIRI Large Graph Mining Recent Development, Challenges and Potential Solutions p113.pdf
├<graph partition>
│ ├AURORA MULTI-LEVEL GRAPH PARTITIONING p62.pdf
│ ├Chung Four graph partitioning algorithms p117.pdf
│ └Trevisan Spectral Graph Theory and Graph Partitioning p62.pdf
├<Graph Powering>
├<graph production>
├<graph profiling>
├<graph reduction>
├<GRAPH RETRIEVAL>
├<graph seriation>
├<graph simplifying>
├<graph transformation>
└<Graph traversal>
└Adrian Graphs and Graph Traversals p36.ppt

Graph Theory

graph_zzz_theory/

graph_minors_theory/

Ghandchi Graph Minors Theory p23.pdf
Harvey On Treewidth and Graph Minors p163.pdf

graph_ramsey_theory/

Conlon Recent developments in graph Ramsey theory p54.pdf
Dickson An Introduction to Ramsey Theory on Graphs p86.pdf

graph_structure_theory/

Marx Algorithmic graph structure theory p255.pdf

zzz_graph_heory/

algebraic_graph_theory/

Csikvari Graph Polynomials and Graph Transformations in Algebraic Graph Theory p119.pdf

algorithmic_graph_theory/

Golumbic Algorithmic Graph Theory and Perfect Graphs 2ed p338.pdf
Joyner Algorithmic Graph Theory p322.pdf

Ｍarx Algorithmic graph structure theory p255 ........... okokok

Pandey Applications of Algorithmic Graph Theory to the Real World Problems p5.pdf

Chemical Graph Theory

Balaban Chemical Graph Theory and the Sherlock Holmes Principle p28
Alexandru T. Balaban

Chromatic_Graph_Theory/

M. Behzad, Graphs and Their Chromatic Numbers. Ph.D. Thesis, Michigan
State University (1965).

CHARTRAND Chromatic Graph Theory p498

extremal_graph_theory/

Alon Problems and results in Extremal Combinatorics Part I p21
Alon Problems and results in Extremal Combinatorics p18

Aouchiche Variable Neighborhood Search for Extremal Graphs 20 Automated Comparison of Graph Invariants p20

Balbuena Extremal K(s,t)-free bipartite graphs p14

Bela Bollobas
Bollobas Extremal Graph Theory
Bollobás Graphs Extremal and Random p8

Borgs Counting Graph Homomorphisms p45

Chapter 10 Extremal Theory p25

Chernikov Applications of model theory in extremal graph combinatorics p30

Diwan Extremal Graph Theory p33.pptx

Engbers Graph theory — to the extreme p76

ERD?S COMPACTNESS RESULTS IN EXTREMAL GRAPH THEORY p14

FüREDI Extremal Hypergraphs and Combinatorial Geometry p10

Garnick Extremal Graphs without Three-Cycles or Four-Cycles p9

Glasscock What is a Graphon p7

Grzesik Flag Algebras in Extremal Graph Theory p63

Hartman EXTREMAL PROBLEMS IN GRAPH THEORY p97.pdf

Hernando Extremal Graph Theory for Metric Dimension and Diameter p28
Hernando Extremal Graph Theory for Metric Dimension and Diameter 1 p5

Kang Extremal Graph Theory p3

Liu Discrete Geometry and Extremal Graph Theory p8

Markstrom Extremal graphs for some problems on cycles in graphs p15

Martin Notes on Extremal Graph Theory p101.pdf

McClintock Extremal Graph Theory for Book-Embeddings p64.pdf

Morris Extremal and Probabilistic Combinatorics p85

Nikiforov Some new results in extremal graph theory p41.pdf

Polak On the applications of Extremal Graph Theory to Coding Theory and Cryptography p14

Shapira Extremal Graph Theory p53.pdf

Simonovits Extremal Graph Problems Degenerate Extremal Problems and Supersaturated Graphs p25

P. Soltan, D. Zambitskii, C. Pris·acaru, Extremal Problems on Graphs and Algorithms of
their Solution, S?tiint?a, Chi?sin·au, 1973 (Russian).

Sperfeld Semidefinite programming in extremal graph theory p85.pdf

Stein Extremal graph theory p171.pdf
Stein Extremal Infinite Graph Theory p41.pdf

Sudakov Turans theorem variations and generalizations p26

Szemeredi Extremal graph theory p33

Thomason Extremal_Graph_Theory_2013 p37.pdf
Thomason Extremal graph theory p3

Ustimenko On Extremal Graph Theory for Directed Graphs and its Applications to Information Security p2

Vetrík Selected Topics in the Extremal Graph Theory p6

Yilma Results in Extremal Graph and Hypergraph Theory p99.pdf

fractional_graph_heory/

Scheinerman Fractional Graph Theory p167.pdf
Scheinerman Fractional Graph Theory1 p167.pdf

Geometric Graph Theory

Pach The Beginnings of Geometric Graph Theory p20
Janos Pach

metric_graph_theory

Bandelt Metric graph theory and geometry: a survey p30
Hans-J?urgen Bandelt and Victor Chepoi

P.M. Winkler, The metric structure of graphs: theory and applications. in Survey in Combi-
natorics 1987, C. Whitehead (ed.), London Math. Soc. Lect. Notes Ser., vol. 123, Cambridge
University Press, Cambridge, 1987, pp. 197{221.

spectral_graph_theory/

Brouwer Spectra of graphs p229.pdf

Andries E. Brouwer, Willem H. Haemers
Brouwer Spectra of graphs p255

Hancock Advanced topics in spectral graph theory p134.pdf

Spielman Spectral Graph Theory and its Applications p75.pdf ..............okokok

Structural Graph Theory

Mgr. Jan Hladky, Ph.D.
Hladky Structural Graph Theory p188

topological_graph_theory/

Gross and Tucker

Topological Graph Theory

Mohar Topological graph theory and crossing numbers p18.pdf

Vella A FUNDAMENTALLY TOPOLOGICAL PERSPECTIVE ON GRAPH THEORY p263.pdf

graph_theory
├<graph_zzz_theory>
│ ├<graph_minors_theory>
│ │ ├Ghandchi Graph Minors Theory p23.pdf
│ │ └Harvey On Treewidth and Graph Minors p163.pdf
│ ├<graph_ramsey_theory>
│ │ ├Conlon Recent developments in graph Ramsey theory p54.pdf
│ │ └Dickson An Introduction to Ramsey Theory on Graphs p86.pdf
│ └<graph_structure_theory>
│ └Marx Algorithmic graph structure theory p255.pdf
└<zzz_graph_heory>
├<ATIS Graph Theory>
│ └Thompson ATIS Graph Theory p65.pdf
├<Chromatic_Graph_Theory>
│ └CHARTRAND Chromatic Graph Theory p498.pdf
├<extremal_graph_theory>
│ ├Engbers Graph theory — to the extreme p76.pdf
│ ├Grzesik Flag Algebras in Extremal Graph Theory p63.pdf
│ ├Hartman EXTREMAL PROBLEMS IN GRAPH THEORY p97.pdf
│ ├Martin Notes on Extremal Graph Theory p101.pdf
│ ├McClintock Extremal Graph Theory for Book-Embeddings p64.pdf
│ ├Morris Extremal and Probabilistic Combinatorics p85.pdf
│ ├Shapira Extremal Graph Theory p53.pdf
│ ├Sperfeld Semidefinite programming in extremal graph theory p85.pdf
│ ├Stein Extremal graph theory p171.pdf
│ └Yilma Results in Extremal Graph and Hypergraph Theory p99.pdf
├<fractional_graph_heory>
│ └Scheinerman Fractional Graph Theory p167.pdf
└<Structural Graph Theory>
└Hladky Structural Graph Theory p188.pdf

Graph Types

data_flow_graph/

Choi Software Synthesis for Dynamic Data Flow Graph p46.doc
Ersfolk Scheduling Dynamic Dataflow Graphs with Model Checking p225.pdf
Oh Rate Optimal VLSI Design from Data Flow Graph p4.pdf
Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf

digraph/

Bang-Jensen Digraphs Theory Algorithms and Applications p772.pdf
BangJensen Digraphs Theory algorithms and applications p772.pdf

eulerian_graph/

Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
Khade An Approach for Minimizing CMOS Layout by Applying Eulers Path Rule p4.pdf

fuzzy_graph/

Zhang Speeding up VLSI layout verification using fuzzy attributed graphs approach p11.pdf

graph_of_graphs/

Pignolet Exploring the Graph of Graphs Network Evolution and Centrality Distances p10.pdf

median_graph/

Ferrer Theory and algorithms on the median graph p174.pdf

planar_graph/

Culler Planar graphs p69.pdf

Gogoi Algorithm for Designing VLSI Floorplan using Planar Triangulated Graph p9.pdf
Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf

random_graph/

Ioannides RANDOM GRAPHS AND SOCIAL NETWORKS An Economics Perspective p66.pdf
Knobel From Random Graphs to Complex Networks A Modelling Approach p87.pdf
Newman Random Graphs as Models of Networks p36.pdf
van der Hofstad Random Graphs and Complex Networks. Vo. I p328.pdf
van der Hofstad Random Graphs and Complex Networks. Vol I p312.pdf

0graph_types
├<data_flow_graph>
│ ├Ersfolk Scheduling Dynamic Dataflow Graphs with Model Checking p225.pdf
│ └Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf
├<digraph>
│ ├Bang-Jensen Digraphs Theory Algorithms and Applications p772.pdf
│ └BangJensen Digraphs Theory algorithms and applications p772.pdf
├<Dynamic graph>
│ └Demetrescu Dynamic graphs p20.pdf
├<eulerian_graph>
│ └Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
├<fuzzy_graph>
│ └Zhang Speeding up VLSI layout verification using fuzzy attributed graphs approach p11.pdf
├<graph_of_graphs>
│ └Pignolet Exploring the Graph of Graphs Network Evolution and Centrality Distances p10.pdf
├<median_graph>
│ └Ferrer Theory and algorithms on the median graph p174.pdf
├<planar_graph>
│ ├Culler Planar graphs p69.pdf
│ └Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf
└<random_graph>
├Ioannides RANDOM GRAPHS AND SOCIAL NETWORKS An Economics Perspective p66.pdf
├Knobel From Random Graphs to Complex Networks A Modelling Approach p87.pdf
├van der Hofstad Random Graphs and Complex Networks. Vo. I p328.pdf
└van der Hofstad Random Graphs and Complex Networks. Vol I p312.pdf

Optimization

Berlier A Parallel Genetic Algorithm for Placement and Routing on Cloud Computing Platforms p341.pdf
Chibante Simulated_Annealing Theory with Applications p300.pdf
Dantzig Linear programming vol 1 Introduction p474.pdf
Dantzig Linear programming vol 2 Theory and Extensions p475.pdf
De Jong The Handbook of Evolutionary Computation p940.pdf

dos Santos Evolutionary_Computation p582.pdf

Hendler Foundations of Artificial Intelligence p1035.pdf
Hendriks High Level Synthesis Performance Analysis and Code Optimization p105.pdf
Kennedy Swarm intelligence p541.pdf
Vanderbei Linear Programming Foundations and Extensions p466.pdf
Yu Introduction to Evolutionary Algorithms p433.pdf

Others

DORAIRAJ DESIGN OF ALGORITHM TRANSFORMATIONS FOR VLSI ARRAY PROCESSING p102.pdf
Govindarajan Algorithm for design space exploration p216.pdf
Govindarajan Algorithm for design space explorationUN p216.pdf
Lucchesi Contributions of Jayme Luiz Szwarcfiter to Graph Theory and Computer Science p15.pdf
Meinel Algorithms and data stuctures in VLSI designs p279.pdf

graphtheory_math

graphtheory_math
├<algebraic_graph_theory>
│ └Csikvari Graph Polynomials and Graph Transformations in Algebraic Graph Theory p119.pdf
├<algorithmic_graph_theory>
│ ├Golumbic Algorithmic Graph Theory and Perfect Graphs 2ed p338.pdf
│ ├Joyner Algorithmic Graph Theory p322.pdf
│ └Wu A Glimpse at Algorithmic Graph Theory p187.pdf
├<metric_graph_theory>
│ └Bandelt Metric graph theory and geometry a survey p38.pdf
└<spectral_graph_theory>
├Brouwer Spectra of graphs p229.pdf
├Brouwer Spectra of graphs p255.pdf
├Gallier Spectral Theory of Unsigned and Signed Graphs Applications to Graph Clustering a Survey p122.pdf
├Hancock Advanced topics in spectral graph theory p134.pdf
├Kelleher Spectral Graph Theory p45.pdf
├Kolla Merging Techniques for Combinatorial Optimization Spectral Graph Theory and Semidefinite Programming p96.pdf
├Li李宇軒Spectral Graph Theory p46.pdf
├Miller Spectral Graph Theory, Linear Solvers, and Applications p134.pdf
├Rittenhouse Properties and Recent Applications in Spectral Graph Theory p59.pdf
└Spielman Spectral Graph Theory and its Applications p75.pdf

Othersciences

graphtheory_sciences
├<Chemical_Graph_Theory>
│ └Balaban Chemical Graph Theory and the Sherlock Holmes Principle p28.pdf
├<Evolutionary Graph Theory>
│ └Shakarian A Review of Evolutionary Graph Theory With Applications to Game Theory p45.pdf
├<fluid>
│ └Manjula Graph Applications to Fluid Mechanics p5.pdf
├<ThermoDynamics>
│ └Peana Thermodynamic Investigations of Random Graph Models p8.pdf
└<zzz_graph theory in vlsi design>
├Cong Techniques for Designing Efficient Parallel Graph Algorithms for SMPs and Multicore Processors p11.pdf
├Ellis-Monaghan Graph Theoretical Problems in Next-Generation Chip Design p17.pdf
├Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177.pdf
├Galuzzi Graph Theory and Application Specific Processors p7.pdf
├Held Combinatorial Optimization in VLSI Design p65.pdf
├Hendrickson Graph partitioning models for parallel computing p16.pdf
├Lin Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing p4.pdf
├Lin TCG A Transitive Closure Graph-Based Representation for General Floorplans p12.pdf
├Liu Automatic RunTime Extraction of Communication Graphs From Multithreaded Applications p6.pdf
├Simonis Constraint Applications Using Graph Theory Results p71.pdf
├Szeszler Combinatorial Algorithms in VLSI Routing p78.pdf
└Zaretsky Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code p15.pdf

Trees

tree_types.docx

Steiner_tree/

Parent Directory
Grotschel The Steiner Tree Packing Problem in VLSI Design p21.pdf
Ihler Class Steiner trees and VLSI-design p22.pdf

zzz_graph theory in vlsi design


Graph Theory

My current research and authoring are focusing on hypergraph applications in 3D VLSI design. A survey will be published pretty soon. Updated on 2014-7-4.

Branches

Algebraic graph theory

Algorithmic Graph Theory

Enumerative graph theory

extremal graph theory

random graph theory

Spectral graph theory

Types of Graphs

null graph

empty graph

general graph

universal graph

simple graph

connected acyclic simple graph

multigraphs

complement graphs

Complete graph

PERFECT GRAPH

Superperfect Graphs

bipartite graph

quasi-bipartite graphs

complete bipartite graphs

directed graph or Digraph

Undirected graph

oriented graph

strict digraph

Random Graphs

THRESHOLD GRAPHS

Extremal graphs

Comparability graph

theta graph

Hereditary graph

friendship graph

Pseudograph

Directed pseudograph

connected digraph

strongly connected digraph

weighted graph

connected weighted graph

COGRAPHS

SPLIT GRAPHS

line graph

INTERVAL GRAPHS

planar graph

connected simple planar graph

grid graph

Chordal graphs

Circular-Arc Graphs

triangulated graph

Eulerian graph

Hamiltonian graph

Petersen Graph

Moore Graph

Harary graphs

Subgraph

Teilgraph

Untergraph

spanning subgraph

induced subgraph

Forbidden induced subgraph

Even Subgraphs

edge-deleted subgraph

vertex-deleted subgraph

Hypergraph

See this page for details

k-uniform hypergraph

Graph Structures

Clique

A clique in a graph G = (V, E) is a set K  V such that the subgraph induced by K is isomorphic to the complete graph KjKj.

Forest

=============================================

Pseudo?random structures

Graph and geometric thickness

?(G) = the chromatic number of G

=============================================

Trees

Tree width

Rectilinear trees

Hexagonal trees

Spanning tree

spanning

Minimum spanning tree MST

A minimum spanning tree MST for the terminals in Z is a shortest network spanning Z without introducing Steiner points

Minimum Spanning Trees

Given a weighted graph

Find a spanning tree whose weight is minimum

Prim’s algorithm

start with an arbitrary node S

T<-{s}

while T is not a spanning tree

find the closet pair x?V-T, y?T

add (x,y) to T

runs in O(n2) time

very simple to implement

always gives a tree of minimum cost

Kruskal’s algorithm

minimum weight spanning tree

Steiner Tree

See further here.

Walks

A (v0, vk)-walk in G is an alternating sequence [v0, e1, v1, e2 . . . vk??1, ek, vk] of vertices and edges from G with ei = hvi??1, vi

closed walk

i. In a closed walk, v0 = vk.

Paths

a path is a trail in which and edges and vertices are distinct.

Trails

A trail is a walk in which all edges are distinct;

Euler trail

Cycles

A cycle is a closed trail in which all vertices except v0 and vk are distinct.

Circuit

Eulerian circuit

Hamiltonian circuit

Components

A subgraph H of G is called a component of G if H is connected and not contained in a connected subgraph of G with more vertices or edges.

Tour

Euler tour

spanning arborescence

Matroids

vertex cut

minimal vertex cut

cut vertex

edge cut

Cut edge

Minor or subcontraction

Network

A digraph with weighted edges in the context of graph theory is called a network.

isthmus / bridge

An isthmus of a connected graph G is an edge whose deletion results in a disconnected graph. (Some authors call this a bridge

=================================

Terms and Definitions

order of a graph

size of a graph

multiplicity of a graph

girth of a graph

circumference

distance

(geodesic) distance

crossing number of a graph

edge cover

A set C of vertices in a graph G is said to cover the edges of G if every edge of G is incident with at least one vertex of C. Such a set C is called an edge cover of G.

adjacency matrix

incidence matrix

graph isomorphism

vertex independent

edge independent

independent

Graph Theories

Geometric graph theory

Graph Structure Theory

“Graph structure theory” usually refers to the theory developed by Robertson and Seymour on graphs excluding minors.

Definition
Graph H is a minor of G (H  G) if H can be obtained from G by deleting edges, deleting vertices, and contracting edges.

Graph theoretical modeling and analysis

Extremal graph theory

Ramsey Theory

Ramsey Theory

Turan Theory

Szemeredi’s Regularity Lemma

Regularity Lemma

Counting Lemma

Graph Operations

Planar embeddings

Graph drawing

Algebraic Constructions

G\e and G/e obtained from G by deleting and contracting a link e

Graph partitioning

Graph partitioning GP within the area of numerical analysis techniques for GP

hypergraph partitioning

parallel methods

Graph Growing

max-ow min-cut theorem based partitioning

Geometric Partitioning

geometric graph partitioning

Streaming Graph Partitioning (SGP)

Multilevel Graph Partitioning

multilevel methods

multilevel algorithms graph partitioning

Spectral Partitioning

Spectral bisection

linear algebra - Spectral partitioning uses methods from linear algebra

combinatorial bounds

combinatorial optimization methods

combinatorial graph partitioning

static partitioning

Load balancing of dynamic simulations

parallel aspects

coarsening by matching

Metaheuristics

heuristics and approximation algorithms used in the multilevel GP framework

local search by node-swapping heuristics

heuristics - simple-minded but fast heuristics

evolutionary methods that can use multiple runs of other algorithms (e.g., multilevel)

genetic algorithms

breadth first search - Graph growing uses breadth rst search or similar ways

computational geometry

shortest path computations

parallel solvers, mapping onto a set of parallel processors

migration minimization when repartitioning a dynamic graph

Flow computations

multi-commodity flows

streaming algorithms

branch-and-bound framework

Bubble Framework

Random Walks and Diffusion

semi-denite programming

Linear programming

Node-swapping Local Search

Extension to k-way Local Search

Tabu Search

edge colorings and vertex colorings

Graph Algorithms & Methods

3-graph Regularity Method
===============================

shortest path algorithm

Greedy algorithm

Let G be a connected weighted graph with n vertices. At each point, we will have a set {e1, e2, . . . , ei} of i independent edges (i = 0 to start), so that G:{e1, e2, . . . , ei} has n?i
components. If i < n?1, let ei+1 be an edge with ends in different components of G:{e1, e2, . . . , ei} and whose cost is minimum with respect to this property. Stop when we have chosen n ? 1 edges.

With e1, . . . , en?1 chosen as above, the spanning tree T0 := G:{e1, . . . , en?1} has the property that c(T0) ≤ c(T) for any spanning tree T.

Dijkstra’s Algorithm

We determine the shortest route or shortest distance along with the shortest path between any two fixed pair of vertices of a directed or undirected graph. One of the most important and useful algorithm is Dijkstra’s shortest path algorithm, a greedy algorithm that efficiently finds shortest paths in a graph. A greedy algorithm for an optimization problem always makes the choice that looks best at the moment and adds it to the current subsolution. It builds a solution by repeatedly selecting the locally optimal choice among all options at each stage.

Dijkstra’s algorithm solves shortest path problem to find the shortest path from a given node s, called a starting node or an initial node, to all other nodes in the network. This algorithm solves only the problems with non-negative costs (weights), i.e., cij ≥ 0 for all (i; j)∈ E:

modified Dijkstra’s shortest path algorithm
===============================

Floyd-Warshall’s Algorithm
===============================

Minimum Spanning Trees

A spanning tree T of a weighted graph G is called a minimal spanning tree if its weight is minimum.

Given a weighted graph
Find a spanning tree whose weight is minimum

Prim’s algorithm

start with an arbitrary node S
T<-{s}
while T is not a spanning tree
find the closet pair x œV-T, yœT
add (x,y) to T
runs in O(n2) time
very simple to implement
always gives a tree of minimum cost

Dijkstra-Prim method

Kruskal’s Algorithm

Boruvka Algorithm.

Graph Search

===============================

Breadth First Search Algorithm to Find the Shortest Path

A tree-search in which the adjacency lists of the vertices of T are considered on a firstcome first-served basis, that is, in increasing order of their time of incorporation into T, is known as breadth-first search.

Algorithm 6.1 Breadth-First Search (BFS)
Input: a connected graph G(r)
Output: an r-tree T in G with predecessor function p, a level function such that
(v) = dG(r, v) for all v ∈ V , and a time function t

the queue Q
1: set i := 0 and Q := ?
2: increment i by 1
3: colour r black
4: set (r) := 0 and t(r) := i
5: append r to Q
6: while Q is nonempty do
7: consider the head x of Q
8: if x has an uncoloured neighbour y then
9: increment i by 1
138 6 Tree-Search Algorithms
10: colour y black
11: set p(y) := x, (y) := (x) + 1 and t(y) := i
12: append y to Q
13: else
14: remove x from Q
15: end if
16: end while
17: return (p, , t)

===============================

Depth-first search

Depth-first search is a tree-search in which the vertex added to the tree T at each stage is one which is a neighbour of as recent an addition to T as possible.

Algorithm 6.4 Depth-First Search (DFS)
Input: a connected graph G
Output: a rooted spanning tree of G with predecessor function p, and two time functions f and l
1: set i := 0 and S := ?
2: choose any vertex r (as root)
3: increment i by 1
4: colour r black
5: set f(r) := i
6: add r to S
7: while S is nonempty do
8: consider the top vertex x of S
9: increment i by 1
10: if x has an uncoloured neighbour y then
11: colour y black
12: set p(y) := x and f(y) := i
13: add y to the top of S
14: else
15: set l(x) := i
16: remove x from S
17: end if
18: end while
19: return (p, f, l)

===============================

Graph detailed routing

track graph

Dijkstra without future cost

Dijkstra with future cost

weighted bipartite matching based heuristic

Voronoi diagram

Graph channel routing

Graph theory based algorithm

Most of the problems in VLSI physical design are modeled with graphs. The graphs in the area are generally perfect. Perfect graphs have interesting property that the algorithms based on these graphs are polynomial in nature in time complexity.

The initial graphs for channel routing are horizontal and vertical constraint graphs. It is observed that optimal routing solely dependant upon the graphs is NP-hard in nature. The lower band in channel routing can be obtained by using chordal graphs. The other graphs that come to our notice in VLSI physical design are Permutation graphs, Intersection graphs, Circle graphs, Interval graphs, etc. The computation of maximum independent set, minimum coloring, maximum clique detection, etc. are normally done in terms of graphs. Obviously graph algorithms are backbone of the area, as described in brief in the following section.

Graphs - The Tool to Visualize the Problems in VLSI Channel Routing

Graph: The Tool to Realize the Problems in VLSI

==============================

graph-based interconnect optimization algorithm, called the GRATS-tree algorithm
==============================

Minimum Clique Cover 1 (MCC1)

Constraint graph channel routing

Graph Theoretic 3D VLSI

Click to learn more ...

Graph Problem

The (weighted) Steiner Tree Problem

The Steiner Tree Packing Problem

Graph Theoretic Functions

The number of components of G is denoted c(G)

The independence number α(G)

k(G) denote the size of a minimal vertex cut for graph G

vertex connectivity κ(G)

λ(G) the size of a minimal edge cut

edge-connectivity λ( G)

detour order τ(G)

chromatic number Χ(G)

The number of components of G is denoted as ω(G).

The maximum clique size or clique number ω(G)

the smallest degree of a vertex of δ(G)

orientation of G : G →

Given a graph G, define Ω(G) to be the number of connected components of G with odd order

define Σ(G) to be the number of connected components of G with even order.

The number of arcs in D is denoted by a(D).

underlying graph of D, denoted G(D).

associated digraph of G, denoted D(G).

Γ(x) to denote the set of all vertices adjacent to a given vertex x; these vertices are also
called the neighbors of x.

The vertices which dominate a vertex v are its in-neighbours, those which are dominated by the vertex its outneighbours. These sets are denoted by N D - and N D + , respectively.

The minimum indegree and outdegree of D are denoted by δ?(D) and δ+(D), respectively;

the maximum indegree and outdegree of D are denoted Δ?(D) and Δ+(D), respectively.


Graph theory for novel IC designs focusing on neural computation

Ackerman On Grids in Topological Graphs p14.pdf
Archdeacon Topological Graph Theory a Survey p67.pdf
Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front p18.pdf
Bonnington Combinatorial maps and the foundations of Topological Graph Theory 01_front333 p18.pdf
Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228.pdf
Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228jjj.pdf
Chapter 5 Topological Graph Theory p32.pdf
Chapter III Adopting Topological Graph Theory to Traffic Management Problem p18.pdf
Childs Topological Graph Theory and Graphs of Positive Combinatorial Curvature p54.pdf
Craft Topological Graph Theory.pptx
Hutchinson Some Conjectures in Chromatic Topological Graph Theory p19.pdf
KNILL CLASSICAL MATHEMATICAL STRUCTURES WITHIN TOPOLOGICAL GRAPH THEORY p28.pdf
Mohar Topological graph theory and crossing numbers p18.pdf
Rooney Topological Graph Theory Lecture 15-16 Cycles of Embedded Graphs p6.pdf
Sawollek A Survey of Embedding Problems in Topological Graph Theory.docx
Topological graph theory.docx
Vella A FUNDAMENTALLY TOPOLOGICAL PERSPECTIVE ON GRAPH THEORY p263.pdf

Graph theory for novel IC designs focusing on neural computation

Dear Prof Moussa,

I am writing this mail to know if you have vacancies available for me to occupy in order to carry out my research project. I am currently working on graph theoretic studies of IC (Integrated Circuits ) technologies – mainly the design phase. I have found out that the majority of the graph theoretic technologies are relevant to IC designs, and a preliminary review shows that thousands of graphs/hypergraphs/trees, metrics, features, functions, operations, algorithms and optimzations are involved in the design of ICs. Over the last 22 months or so I have explored several fields of upcoming new generation of IC technologies (quantum circuits, DNA computing, membrane computing, cellular and chemical computing to name a few) as well as several graph theoretic issues related to IC design. And now I am focusing on neural computing which is one of the recent research hotspots. I don’t work on the old, traditional chip technologies which is now deadlocked.

My task is to find out which graph theoretic aspects are playing which roles in the new generation, non-silicon CMOS IC design and possibly also to work out some improvements of graph algorithms to ameliorate the design efficiency and (less ardently) to help the development of EDA tools and platforms.

I hold no PhD or postdoc title, although I was granted PhD admissions into some of the elite universities in the early 1990's, and I have not published a single piece of paper in notorious scientific journals although I have prepared hundreds of drafts in several science branches. I have my own way of studies and research. My logical and systemtatic approach are very unique, so that my strength is the ability to figure out a complete system out of the sporadic research activities here and there by many other experiments and theoretists. This talent is on one hand unique and on the other hand it takes more time to finalize my research subject.

Yours sincerely,

Mark Chen

Graph theoretic aspects of IC technologies:

Here ICs are meant the new generation, non-conventional, non CMOS computing systems such as:

  1. Neural computing
  2. Bio chips
  3. Cellular Computing?
  4. Chemical Computing
    • Reaction-Diffusion Computing
  5. DNA computing??????
  6. Gallium chips???
  7. Germanium Chips / Silicon-Germanium Chips???
  8. Graphene Chips?????
  9. Indium Chips?
  10. Liquid Chips??
  11. Membrane chips
  12. Molecular chips
  13. Molybdenite Transistors
  14. Natural / Nature-Inspired Computing???
  15. Organic Computing??????
  16. Photonic chips
  17. Physarum Chip????
  18. Quantum chips
  19. Resonant Tunneling Devices?
  20. Roll-Away Computer / Flexible Electronics
  21. Single Electronics /Single Electron Transistor / Single Electron Tunnelling (Set) Devices
  22. Spin Electron Chips??????
  23. Strained silicon chips
  24. Superconducting chips

GRAPH TYPES

adjacency graph????
architecture graph
Cayley Graph
cell graph??
cluster graphs??
cographs???
communication graph
connection graph??
connectivity graphs??????
configuration graph
Constraint Graph
control flow graph
data flow graph
datapath graph
de Bruijn graph
dependence / dependency graph
distance graph
distribution graph
dual graph?
dynamic graph
eulerian graph
expanded graph?????
flow graph
grid graph??
hierarchical graph
implication graph???
incidence graphs???
interval graph
kernel graph
layer graph
line graph??
mapping graph
nearest neighbor graph??????
netlist graph
Petersen graph
process graph
quantum (metric) graphs????
qubit graph??
random graph
resource graph
routing graph
spanning graph?????
specification graph
state graph
(quantum) state graph (sg)?
stream graph????
Tanner graph
task graph
Teich graph
timing graph
topology graph
transformation graph

HYPERGRAPH

affinity hypergraph
cellular hypergraphs????
clique hypergraph?
compatibility hypergraph????
conflict hypergraphs????
connection graph??
constraint hypergraph??
dual hypergraph????
eulerian hypergraphs??
extremal hypergraph????
folded hyperpath????
fuzzy hypergraph???
hierarchical hypergraph?????
hypercircuit??????
hypercubic graphs?
implication hypergraph
interval hypergraph??????
linear hypergraph??
multi-hypergraph???
neighborhood hypergraph?
oriented hypergraph?????
orthogonal hypergraph
quantum hypergraph???
random hypergraph??????
regular hypergraph
signed hypergraph
spanning hypertree??????
stanford hypergraph?????
topological hypergraphs?????
transition hypergraph???
transversal hypergraphs?????
uniform hypergraph?????
hypergraph automata???
hypergraph automorphism
hypergraph embedding??????
hypergraph matching???
hypergraph-product??????
hypergraph states??

GRAPH STRUCTURES

graph minor
graph topology

GRAPH CHARACTERISTICS OR FUNCTIONS

graph automorphism????
graph complement?
graph connectivity
graph functional????
graph geodesic
graph hamiltonian?
graphs homeomorphic?
graph homomorphisms
graph isomorphism
graph package
graph kernels??
graph polynomials?
graph powers???
graph spectra???
graph topology
subgraph isomorphism
Laplacian matrix of the graph
cartesian product of graphs??????
cospectrality of graphs?
independence number of graph?????
laplacian of graph??
laplacian matrices of graphs?????
projective rank of graph??????
shannon capacity of graph
spectrum of graph??
strong product of graphs???? 6
symmetric powers of graph
symmetric squares of graphs????
tensor powers of graphs?????

composition of graphs?
random walks on graphs????

GRAPH OPERATIONS???

graph augmentation?????
graph/ hypergraph clustering
graph coloring
graph compilation
graph covering
graph discovery
graph drawing
graph embedding
graph expansion????
graph extraction
graph growth???
graph mapping
graph matching
graph merging
graph mining???
graph optimization
graph packing
graph/ hypergraph / clique partitioning
graph products
graph profiling
graph scattering?????
graph seriation
graph transformation
graph traversal/ transverses
graph union?????
graph visualization

TREES

3d tree
b-tree
binary tree
binary search tree
Cayley tree
configuration trees
dataflow tree
decision tree??
h-tree???
interval tree??????
line tree??????
partition tree?????
random tree??????
rc tree??
rlc trees??????
routing tree
search tree
spanning tree
Steiner tree
transition tree???
traversal tree????
tree-covering
tree decompositions?????
tree search??
tree traversal????

MESHES AND OTHER STRUCTURES

mesh topology
reconfigurable mesh
RING
TORUS
folded torus

The bold typed items are the important ones which need more attention.

Standard letters

?new

Dear Prof XXX,

I am honored to have read your paper “Embedding large subgraphs into dense graphs” and several of similar papers of yours, for I happen to be interested in the graph theoretic aspects of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, spin-based computing etc). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the generation of the netlist.

I am not an established graphtheorist, rather, an independent and self taught researcher in this field. Nobody knows my work, nothing has been published out of my hands, although I have prepared hundreds of papers and dozens of books or study notes in this and many other fields.

I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, graph embedding is understood as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant and corrupt. They ignore people like me who have no decent position in their system. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Therefore I need to have contacts with the external academic circles to communicate my ideas and to know what others are doing and thinking about. I want to know if you are interested in joining this circle or not.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:
new:
https://sites.google.com/site/markchenstudio/
old:
https://sites.google.com/site/markchen0088/

old

Dear Prof Cappos,

I am honored to have read your 2006 paper “Simultaneous Graph Embedding with Bends and Circular Arcs” coauthored with Alejandro Estrella-Balderrama, Joseph Fowler and Stephen Kobourov, for I happen to be interested in the graph theoretic issues of integrated circuits design (particularly the next generations of ICs such as quantum circuits, nano chips, DNA computing and a bunch of other novice IC techs). For the graph theory part, I am currently specifically working on graph embedding, for it is the very first step towards an IC layout after the netlist is generated.

I am not an established who’s who, rather, a newcomer in this field. Nobody except myself know my work, nothing has been published out of my hands. But I am still wandering what is really meant of graph embedding? There are confusing definitions and implications. Many consider embedding = graph drawing or visualization or layout, some call it graph packing. Embedding is also written as imbedding sometimes. In my opinion, out of my studies of quantum circuits, graph embedding is defined as follows: given a guest graph G and a host graph H, the problem is to find a mapping from each node of G to one of H, and a mapping from each edge of G to one path in H. That was what I meant when I was studying the socalled Chimera graph of the DWave quantum circuits. Simply put, to embed smaller graphs into bigger ones. For Chimera graphs are created out of a number of smaller complete graphs.

I will spend a few months or even years on the graph embedding stuff. I am working solo, here in a small village in China, about 200 km southwest to Shanghai. Therefore I have no one to consult for many puzzling problems. Fortunately we have an Internet, although not as good as yours, because of reasons I won’t elaborate. The Chinese Academia right now is very arrogant. They ignore people like me who have no decent position in the Academia. They won’t answer any of my questions. Therefore I am turning to the foreign societies for help. What I need is people with whom I can exchange views with and get helps occasionally. Perhaps someday when I think I have found something, I may go out and meet someone to talk about my findings. So I would like you to give some help to clarify what is really meant the term of graph embedding.

Thank you in advance for your attention and help!

Best regards,

Mark Chen
Huzhou, Zhejiang, China
Web:? https://sites.google.com/site/markchen0088/


topological graph theory or topological graph embedding

2016-10-25
topological graph theory or topological graph embedding

Dear Prof. Ackerman，

I am pleased to write you about topological graph theory or topological graph embedding (hereafter TGTE) , after having read your papers found on the web.

I've been studying graph embedding (GE) for a while, and found out there are huge number of algorithms, methods and theorems there. I started to learn GT from my interest in VLSI - Very Large Scale Integrated (Circuits) - design, GT plays very important role there, from the high level synthesis to physical design. GE is concerned with the realization of VLSI circuits out of the netlists which are produced by some kinds of HDL - Hardware Language. Therefore the efficiency of embedding graphs is essential to chip design.

I plan to prepare for an indepth study of GE, and starting from TGTE, because there are hundreds of embedding techniques, which I cannot handle them all at the moment. I have found some literature from the web, incl. yours: But I think there are more. I've went to your site, and downloaded several of them pertinent to my research topics. Can I have more copies of your papers in TPGE?

GE has many similar terms to or at least close relations with

  • graph construction,
  • graph drawing,
  • graph encoding,
  • graph generation,
  • graph layout,
  • graph mapping,
  • graph modeling,
  • graph packing,
  • graph realization,
  • graph representation,
  • graph visualization, and
  • several other names.

TGTE is very much involved with many kinds of graphs, sometimes I think it is synonymous with GE at all.

I would like to cearly define them and distingush them in the finest grade and degree - their similarity as well as their differences. If I have the necessary time and possibility, I will try to develop some sort of platforms to unite all the existing techniques in order to provide an option to select the right methods in presenting your choice of graph embedding. That is a difficult task though, but worth trying.

I hope to receive some advice from you, if you feel convenient.

Thank you for your paper as well as your information in advance!

Best regards,

Mark Chen

An independent researcher in China


Math Languages

MathLang
├<APPL>
│ └GLEN APPL A Probability Programming Language 2001 p40.pdf
└<Fortran>
├FORTRAN完全自学手册 p407.pdf
├<myfile>
│ └<codes>
│ ├<Debug>
│ │ └myfile.pdb
│ ├myfile.mak
│ ├myfile.mdp
│ └Text1.f90
└彭国伦 Fortran95程序设计p593.pdf

1.????? 数学程序语言
2.????? Fotran
2.1.?????? Fotran 66 / 77/ 90 / 95 / 2003 / Visual FORTRAN / Fortran
2.2.?????? 一些免费的Fortran编译器和开发环境
2.3.?????? 收费的Fortran编译器

数学程序语言

programming languages / tools for math
数学编程语言/工具

Reference

https://www.physicsforums.com/threads/best-programming-language-for-a-math-major.616557/

www.ampl.com

Ana (programming language)

APL 是A Programming Language 或Array Processing Language 的缩写

APPL: A Probability Programming Language - Mathematics

Bc (programming language)

COMSOL Script

https://www.dartlang.org/

https://dlang.org/

http://www.mat.univie.ac.at/~neum/FMathL.html

Fortress (programming language)

GNU Data Language

HASKELL
http://haskell.cs.yale.edu/?post_type=publication&p=178

Hoc (programming language)

www.ibrarian.net

IDL
IDL (programming language)

IDRIS

J
J语言
J (programming language)

JULIA
Julia (programming language)
Julia 在数学编程语言
http://julialang.org/

MPI

Nickle (programming language)

nim-lang.org

NumPy

Ox (programming language)

http://probabilistic-programming.org/wiki/Home

R语言
http://www.r-project.org/

Scala集成了面向对象编程和函数式编程的各种特性
http://www.scala-lang.org/documentation/getting-started.html

SciPy
ScientificPython
http://www.scipy.org/

SequenceL

www.sigapl.org

Speedcoding

WOLFRAM LANGUAGE
https://www.wolfram.com/language/

Fotran

000Fortran 90 Handbook?? 186??? ?? 533? /? 835

Fotran 66 / 77/ 90 / 95 / 2003 / Visual FORTRAN / Fortran

###########################??? FORTRAN Settings ###############################
###########################??? FORTRAN Settings ###############################
FORTRAN Path dir:
I:\Fortran\g95\bin;I:\Fortran\g95\lib\gcc-lib\i686-pc-mingw32\4.0.3
###########################??? FORTRAN Settings ###############################
###########################??? FORTRAN Settings ###############################

Fortran 90? page 1

http://www.mcs.anl.gov/~itf/dbpp/text/node84.html
http://sip.clarku.edu/tutorials/F.html
http://www.fortran.gantep.edu.tr/compiling-g95-basic-guide.html
http://www.ibiblio.org/pub/languages/fortran/
http://www.nsc.liu.se/~boein/f77to90/f77to90.html
http://www.liv.ac.uk/HPC/F90CourseIntro3DayHomePage.html
http://personalpages.manchester.ac.uk/staff/david.d.apsley/lectures/fortran/index.htm
http://www.mhhe.com/engcs/general/chapman/intro/
http://www.cs.mtu.edu/~shene/COURSES/cs201/NOTES/fortran.html
http://www.osc.edu/supercomputing/training/f90/
http://www-teaching.physics.ox.ac.uk/Unix+Prog/hargrove/tutorial_90/08_subprograms.html
http://www-teaching.physics.ox.ac.uk/Unix+Prog/hargrove/tutorial_90/13_extra.html
http://www.personal.psu.edu/hdk/fortran.html
http://www.owlnet.rice.edu/~ceng303/manuals/fortran/index.html
http://www.cse.scitech.ac.uk/arc/fortran90.shtml
http://www.sdsc.edu/~tkaiser/f90.html
http://vlm089.citg.tudelft.nl/swan/online_doc/swanpgr/node2.html
http://www.cisl.ucar.edu/tcg/consweb/Fortran90/F90Tutorial/tutorial.html
http://aeneas.ps.uci.edu/absoft/pc_e.htm
http://groups.engin.umd.umich.edu/CIS/course.des/cis400/fortran/fortran.html
http://terpconnect.umd.edu/~nsw/ench250/fort-tut.htm
http://www.urz.uni-heidelberg.de/Dokumentation/Fortran90forF77.html
http://www.physics.unlv.edu/~pang/cp2_f.html
http://micro.ustc.edu.cn/Fortran/ZJDing/?

Fortran 编程指南Sun? Studio 11
Fortran 编程指南Sun? Studio 8

http://blog.sina.com.cn/s/blog_6b3aefef0101e5fr.html

一些免费的Fortran编译器和开发环境

Free Fortran Compilers and IDEs

2009-12-02 22:48
linux 上不用说了，一般都带着g77。但是在Windows平台上，由于很多科学计算程序（尤其是早期的）都是用Fortran语言写的，因此找一个好用的编译器还颇费周折。下面这个列表来自互联网，基本上包括了目前还活跃开发者的几款fortran编译器。很多都有Windows平台下的二进制版本，像 g77，g95，gfortran。

Absoft Pro Fortran MP
Absoft Absoft Pro Fortran 95，简称APF95 8.0

CVF, compaq visual fortran， 使用了MS Visual Studio，容易上手，现在版本6.6。
Compaq Compaq Visual Fortran，简称CVF 6.6C

DJGPP GNU G77 (Fortran 77) for MSDOS
http://www.delorie.com/djgpp/
This is a development system based on the well-known GNU compiler system that includes compilers for Fortran 77, C, C++, Objective C, etc. It generates 32 bit MSDOS executables that is Windows 95 long-filename-aware. It is a very complete system with IDEs, graphics libraries, lexical analyser generators (flex), parser generators (bison), text processing utilities (like grep, sed), a program maintainence utility (ie, make), a dos extender, and so on. The compiler, utilities and libraries come with source code.

F2C - Fortran to C Translator
http://www.netlib.org/f2c/
This is a well-known Fortran to C converter that comes with source code. The site also includes pre-compiled binaries (executables) for MSDOS and Microsoft Windows, although these are by no means the only systems supported - the compiler works on Unix systems like BSD, Linux, etc. You have to compile the compiler yourself on those systems. Libraries containing the runtime support needed (together with the C source code) are also included. You need a C compiler to generate binaries from your Fortran sources.

f2j - Fortran to Java Compiler
http://sourceforge.net/projects/f2j
f2j translates Fortran 77 source code to Java class files. It is distributed under the GNU GPL and runs on Linux, SunOS/Solaris.

F编译器是Fortran Company / NAGWare F Compiler 编译器
http://www.fortran.com/F
ftp://ftp.swcp.com/pub/walt/F?

FORCE Project - Fortran Compiler and Editor
http://www.guilherme.tk/
FORCE is actually just an IDE for Fortran 77 that integrates the GNU Fortran 77 compiler (G77). It no longer appears to be maintained.

G95
http://www.g95.org/
http://www.g95.org/

G95 is an open source Fortran 95 compiler. At the time this was written, most of the ISO Fortran 95 standard has been implemented. Platforms supported include Linux(x86, Intel IA64, AMD x86_64), Windows, Macintosh OS X, FreeBSD, Sparc Solaris and HP-UX.

G95/gFortran的Windows版本

Gfortran - the GNU Fortran Compiler
http://gcc.gnu.org/wiki/GFortran
http://gcc.gnu.org/wiki/GFortran
gfortran, part of the GNU Compiler Collection, is a free Fortran 95/2003 compiler. Like all things GNU, it comes with source code. Precompiled binaries (executables) are available for Windows, Linux, Mac OS X, the old Mac OS (PPC), etc.

HP Fortran Compiler（由Fortran PowerStation进化过来的）

Intel Fortran Compiler for Linux
http://www.intel.com/cd/software/products/asmo-na/eng/340679.htm
The Intel Fortran Compiler for Linux is free for personal, non-commercial use (registration required). It features an optimizing compiler, the Intel Debugger (GUI and command-line), mixed language support (C and Fortran), full compliance with the ISO Fortran 95 standard, support for the evolving Fortran 2003 standard, multi-threaded application support (OpenMP and auto-parallelization), ability to handle big-endian data files, compatibility with various Linux tools (like make, gdb and Emacs), substantial compatibility with Compaq Visual Fortran, etc. The optimizing compiler supports interprocedural optimization, profile guided optimization, automatic vectorizer, etc.

Intel Intel Fortran Compiler，简称IFC 10.1
Intel Visual Fortran

Intel Fortran Compiler
Intel Fortran Compiler 8.0? http://www.intel.com/software/products/global/eval.htm ??
您已经注册 英特尔? Visual Fortran 编译器 Windows* 专业版 以便评估。 您将收到一封包含下面列出的序列号与下载位置的电子邮件，以供日后参考。
您有30 天的时间评估该产品，本许可证将于2010/3/1 到期。
https://registrationcenter.intel.com/RegCenter/RegisterSNInfo.aspx?sn=V7XH-DFHZFCVN&EmailID=helioslab%40gmail.com&Sequence=1047432

后续步骤：

步骤 1 ?
保存此序列号，安装产品时将需要使用它：
序列号： V7XH-DFHZFCVN

Lachey / Fujitsu Fortran 95 编译器
Lahey Lahey/Fujitsu LF95，简称LF95 7.2

http://msdn.microsoft.com/zh-cn/evalcenter/bb633753.aspx

MinGW'S G77 (GNU Fortran)
http://www.mingw.org/
This system comes with the GNU G77 Fortran compiler (among other things, including a C/C++ compiler), which you can use to generate Win32 executables from F77 code. Like many systems based on the GNU tools, Mingw32 comes with complete with various programming tools, such as a program maintainence program (ie, make), text processing tools (sed, grep), lexical analyser generator (flex), parser generator (bison), etc.

MS Fortran PowerStation

N.A.Software N.A.Software FortranPlus，简称NAS 2.2

Open Source Watcom / OpenWatcom Fortran Compiler
http://www.openwatcom.org/
The Watcom (now OpenWatcom) Fortran 77 compiler is now available free of charge, complete with source code. This compiler, which generates code for Win32, Windows 3.1 (Win16), OS/2, Netware, MSDOS (16 and 32 bit), etc, was a well-known compiler some years back (until Sybase terminated it).

PGI Fortran
https://www.pgroup.com/
helioslab@voila.fr
Macrovision公司的PGI Visual Fortran

Salford FTN95 Fortran 95 Compiler
http://www.silverfrost.com/32/ftn95/ftn95_personal_edition.asp
Salford FTN95 is a Fortran 95 compiler that supports Fortran 77, Fortran 90 and Fortran 95. The compiler generates exectuables for Win32 (but Win32 console and GUI applications) and the Microsoft .NET framework. It comes with CHECKMATE, a tool that lets programmers check the correctness of their code at runtime. Also included is Plato 3 (an IDE), full source level debugging, documentation and examples. You may only generate code for your personal use on your home computer, and all executables will display a banner on execution.
Salford SalfordFTN95，简称FTN95 3.4.1605

Simply.Fortran

Sun Studio Compilers and Tools
http://developers.sun.com/prodtech/cc/downloads/index.jsp
Sun? Studio Fortran 95 编译器 f95
Sun Studio Compilers and Tools for Linux and Solaris OS on Sparc and x86/x64 platforms includes command line tools as well as a NetBeans-based IDE for developing, compiling and debugging C, C++ and Fortran programs. It also includes performance analysis tools.

Key：
33106-060-1186591-00003
33206-067-6495834-00007

收费的Fortran编译器

SimuWorld.linkka.com 补充几款收费但是功能较强大的类似产品，有银子的朋友可以考虑：

Intel 的 Visual Fortran Compiler Professional Edition for Windows http://software.intel.com/en-us/intel-compilers/
他们主要是兼容最新Fortran标准，并可以很好地和各自公司的产品线相结合使用，例如数学库和调试器。

Portland Group 的 Parallel Fortran Compilers and Tools for Microsoft Windows http://www.pgroup.com/products/pvf.htm

2017-02-12


Math Software & Tools

数学软件工具一览

MathEditingTools.docx

MathSofttools
├<MatLab>
│ ├Attaway MATLAB编程与工程应用第二版 p382.pdf
│ ├Chapman MATLAB编程第二版 339.pdf
│ ├Chapman Matlab编程第二版 p346.pdf
│ ├Houcque INTRODUCTION TO MATLAB FOR ENGINEERING STUDENTS p74.pdf
│ ├Liuhao MATLAB R2014a完全自学一本通 p722.pdf
│ ├matlab-help.chm
│ ├Matlab2014软件教程完美版 p152.pdf
│ ├MATLAB实用中文手册 p263.pdf
│ ├<matlab教程电子书>
│ │ ├01.pdf
│ │ ├02.pdf
│ │ ├03.pdf
│ │ ├04.pdf
│ │ ├05.pdf
│ │ ├06.pdf
│ │ ├07.pdf
│ │ ├08.pdf
│ │ ├09.pdf
│ │ ├10.pdf
│ │ ├11.pdf
│ │ ├12.pdf
│ │ ├13.pdf
│ │ ├14.pdf
│ │ ├15.pdf
│ │ ├16.pdf
│ │ ├17.pdf
│ │ ├18.pdf
│ │ ├19.pdf
│ │ ├20.pdf
│ │ ├21.pdf
│ │ ├22.pdf
│ │ ├jb51.net.txt
│ │ ├服务器软件.url
│ │ └脚本之家.url
│ ├McMahon MATLAB揭秘 p241.pdf
│ ├Moler MATLAB数值计算 p293.pdf
│ ├Sunxiang MATLAB.基础教程 p397.pdf
│ ├WangZL 精通MATLAB70 p536.pdf
│ ├yice Matlab经典教程—从入门到精通 p281.pdf
│ ├ZhangDF MATLAB语言高级编程 p403.pdf
│ ├Zhao Matlab编程基础及应用 p276.pdf
│ ├张志涌 精通MATLAB p712.PDF
│ ├张立科 MATLAB7.0从入门到精通 p560.pdf
│ ├管爱红 初学者宝典 Matlab基础及其应用教程 p276.PDF
│ └蒲俊 MATLAB6.0数学手册 p286.PDF
└<SciLab>
└SciLab Introduction to SciLab p87.pdf

1.????? LabVIEW
2.????? Mathematica
3.????? MatLab /Octave
4.????? Rlab
5.????? Sage
6.????? SciLab

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MATH TOOLS/SOFTWARE
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

programming languages / tools for math
数学编程语言/工具

http://www.mathontheweb.org/mathweb/mi-software.html

http://teachingcollegemath.com/2008/05/top-10-open-source-tools-for-math/

ADMB

AIMMS

AMPL
AMPL软件

Analytica (software)

APMonitor

ARITH-MATIC

http://www.axiom-developer.org/

http://www.boost.org/

Dc (computer program)

Deeplearning4j

Euler (software)

FreeMat

GAUSS (software)

Genius (mathematics software)
www.jirka.org/genius.html

https://gephi.org/

Gretl

HADES (software)

Honeywell ARGUS

http://igraph.sourceforge.net/

ILNumerics

JLab

LabVIEW

M2001

Magma (computer algebra system)

Maple
Maple (software)

MATH-MATIC

Mathematica

MATHEMATICA
Wolfram Mathematica
http://www.wolfram.com/mathematica/

MatLab /Octave

MATLAB / GNU OCTAVE octave
GNU Octave
http://www.gnu.org/software/octave/
http://www.math.ufl.edu/help/matlab-tutorial/

http://www.jb51.net/books/list640_1.html

http://maxima.sourceforge.net/

MEX file

MIMIC

ND4J (software)

ND4S

O-Matrix

OpenBUGS

Paradiseo

Rlab

Rlab

Sage

http://www.sagemath.org/

SAMPL

http://www.sas.com/

ScicosLab

SciLab

Scilab
Scilab Image Processing
http://www.scilab.org/download/
http://www-irma.u-strasbg.fr/~sonnen/SCILAB_HELP/frame.html
http://hkumath.hku.hk/~nkt/Scilab/IntroToScilab.html

Speakeasy (computational environment)

Stan (software)

SYSLAB

Sysquake

Theano (software)

Literature

MatLab

Attaway MATLAB编程与工程应用第二版 p382.pdf
Chapman MATLAB编程第二版 339.pdf
Chapman Matlab编程第二版 p346.pdf
Houcque INTRODUCTION TO MATLAB FOR ENGINEERING STUDENTS p74.pdf
Liuhao MATLAB R2014a完全自学一本通 p722.pdf
MATLAB实用中文手册 p263.pdf
Matlab2014软件教程完美版 p152.pdf
McMahon MATLAB揭秘 p241.pdf
Moler MATLAB数值计算 p293.pdf
Sunxiang MATLAB.基础教程 p397.pdf
WangZL 精通MATLAB70 p536.pdf
ZhangDF MATLAB语言高级编程 p403.pdf
Zhao Matlab编程基础及应用 p276.pdf
matlab-help.chm
matlab教程电子书
yice Matlab经典教程—从入门到精通 p281.pdf
张志涌 精通MATLAB p712.PDF
张立科 MATLAB7.0从入门到精通 p560.pdf
管爱红 初学者宝典 Matlab基础及其应用教程 p276.PDF
蒲俊 MATLAB6.0数学手册 p286.PDF

SciLab

SciLab Introduction to SciLab p87.pdf
2016-10-222017-02-12


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@@@@@@@@@@@@@@@@@@@@@@
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Quantum Computation, Quantum Information Processing
D.W. Leung
wcleung@math.uwaterloo.ca
http://www.math.uwaterloo.ca/%7Ewcleung/
Quantum Information Processing
M. Mosca
http://info.iqc.ca/mmosca/
http://cacr.uwaterloo.ca/~mmosca/
michele.mosca@uwaterloo.ca
Quantum Computing, Algorithms and Cryptography
A. Nayak
http://www.math.uwaterloo.ca/%7Eanayak/
Ashwin.Nayak@uwaterloo.ca
Quantum Computation and Quantum Information, Theoretical Computer Science

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2016-10-22


Algebra

Algebra is the foundation of number theory, and it seems number theory is part of modern algebra. On other hand, number theory has helped the development of abstract algebra. Therefore I have to familiarize with most of the algebraic sciences, particularly the abstract algebra. Here below is the algebraic terminology and major theorems as a result of my reading. It's not the research paper.

Book Chapters

RELATIONS
MAPS FUNCTION OR MAPPING
BINARY OPERATIONS
SERIES
CATEGORIES
FUNCTOR
SETS
MAGMA
SEMI GROUP
GROUPOID
MONOID
GROUP
GALOIS THEORY
RINGS
DOMAINS
IDEAL
MODULES
FIELDS
MATRICES
POLYNOMIAL
LATTICE
VECTOR SPACES
CONSTRUCTIVE ALGEBRA
HOMOLOGICAL ALGEBRA
LIE ALGEBRA
TENSORALGEBRA
ALGEBRAIC STRUCTURES

Literature

Adamek ALGEBRAIC THEORIES A CATEGORICAL INTRODUCTION TO GENERAL ALGEBRA p228.pdf
Adamek algebraic_theories p228.pdf
Adamek YYY algebraic.theories p126.pdf
Adamek ZZZ ALGEBRAIC THEORIES A CATEGORICAL INTRODUCTION TO GENERAL ALGEBRA p126.pdf

Adamek ALGEBRAIC THEORIES A CATEGORICAL INTRODUCTION TO GENERAL ALGEBRA p228

Algebraic Topology part2 p107.pdf

Albuquerque FromLieAlgebrasToQuantumGroups p214

Amalia YYY developing students understandings of cosets normality and quotient group p114.pdf
AmaliaYYY developing students understandings of cosets p114.pdf
ANDREOTTI INVERSE GALOIS THEORY p152.pdf
Arapura YYY Abstract Algebra done Concretely p103.pdf
Ash Abstract Algebra The Basic Graduate Year p407.pdf
Ash Algebra Abstract The Basic Graduate Year p298.pdf

Ash, Robert B.: Abstract Algebra: The Basic Graduate Year, October 2000

Ash, Robert B.: Abstract Algebra: The Basic Graduate Year, October 2000, p407.................78

Ash Abstract Algebra The Basic Graduate Year p298

AxlerYYY Linear Algebra Done Right 2nd Ed p261.pdf

Baker Algebra & Number Theory p68
14

Baker An Introduction to Galois Theory p106.pdf
BakerYYY An Introduction to Galois Theory p130.pdf

BallarinYYY Computer algebra and theorem proving p122.pdf

BANICA VERGNIOUX FUSION RULES FOR QUANTUM REFLECTION GROUPS
BANICA VERGNIOUX GROWTH ESTIMATES FOR DISCRETE QUANTUM GROUPS
BANICA VERGNIOUX INVARIANTS OF THE HALF-LIBERATED ORTHOGONAL GROUP

Barr Category Theory for Computing Science p556.pdf
Barr CATEGORY THEORY FOR COMPUTING SCIENCE p558.pdf
Barr Category Theory Lecture Notes for ESSLLI p133.pdf
Barr Category Theory Lecture Notes for ESSLLI2 p133.pdf

Barr CATEGORY THEORY FOR COMPUTING SCIENCE p558??????????? 39

BARR, MICHAEL AND WELLS, CHARLES: CATEGORY THEORY FOR COMPUTING SCIENC, 2012.

Baumslag Shaums_Group_theory p285

Baumslag Shaums_Group_theory p285.pdf
Baumslag Topics in Combinatorial Group Theory p200.pdf
Beachy YYY ABSTRACT ALGEBRA A STUDY GUIDE FOR BEGINNERS p113.pdf
Beachy YYY ABSTRACT ALGEBRA A STUDY GUIDE FOR BEGINNERS p166.pdf
Beachy YYY ABSTRACT ALGEBRA A STUDY GUIDE FOR BEGINNERS p177.pdf
Beezer YYY Sage for Abstract Algebra p159.pdf
BoorYYY Linear Algebra p289.pdf
Borel Linear Algebraic Groups 2ed p300.pdf

Borel Linear Algebraic Groups 2ed p300

Bowen IntroductionToVectorsAndTensorsVol1 Linear and Multilinear Algebra p304

BowenZZZ IntroductionToVectorsAndTensorsVol1 Linear and Multilinear Algebra p304.pdf
BrinZZZ MODERN ALGEBRA p314.pdf

Brin MODERN ALGEBRA p314??????????????? 92

Brin, Matthew G.: MODERN ALGEBRA, NOTES FOR MATH 401-402 at Binghamton University, 2011

Brown Nonabelian algebraic topology Part I p190.pdf
Bruzzo INTRODUCTION TO ALGEBRAIC TOPOLOGY AND ALGEBRAIC GEOMETRY p138.pdf
bsc_mathsYYY A TEXT BOOK OF CLASSICAL ALGEBRA AND CALCULUS p236.pdf
BurrisSanka A Course in Universal Algebra p331.pdf
BurrisYYY univ-algebra p331.pdf

BurrisSanka A Course in Universal Algebra p331

Burris A Course in Universal Algebra p331

CameronYYY Notes on Algebraic Structures p102.pdf

CarrelYYY FUNDAMENTALS OF LINEAR ALGEBRA p412.pdf

Cartan homological algebra p421.pdf

Cartan homological algebra p421

Categorical Algebra2 p130.pdf
ChurchillZZZ Introduction to Differential Galois Theory p130.pdf
Clark YYY Elementary Abstract Algebra p105.pdf
Clark ZZZ_Elements_of_abstract_algebra p236.pdf
CoffmanZZZ Trace, Metric, and Reality Notes on Abstract Linear Algebra p163.pdf
Connel YYY Elements of Abstract and Linear Algebra p146.pdf
CookeXXX Classical Algebra - Its Nature, Origins and Uses (Wiley, 2008) p208.pdf
coopersteinYYY Elementary Linear Algebra p767.pdf
Cvitanovic GroupTheory p297.pdf

Cvitanovic GroupTheory p297

Davis Lecture Notes in Algebraic Topology p392

Davis Lecture Notes in Algebraic Topology p392.pdf
DawkinsYYY College Algebra p356.pdf
Debarre ZZZ Algebre2 p121.pdf
DebarreYYY Algebre2 p121.pdf
DentonYYY Linear Algebra in Twenty Five Lectures p395.pdf
DHoker quantum_field_theory p255.pdf

DHoker quantum_field_theory p255

DOLGACHEV Classical Algebraic Geometry a modern view p721

DOLGACHEV Classical Algebraic Geometry a modern view p721.pdf
Dolgachev Lectures on Modular Forms p149.pdf
DolotinZZZ Introduction to Non-Linear Algebra p141.pdf

Dolotin Introduction to Non-Linear Algebra p141

Durbin Modern Algebra an Introduction p350

Durbin an-IntroductionModern-Algebra p350.pdf
Durbin Modern Algebra an Introduction p350.pdf
Dutta Introduction to Commutative Algebra p162.pdf

Dutta Introduction to Commutative Algebra p162

Djokovic Rational Orthogonal versus Real Orthogonal p12
El-AlfyYYY COMPUTER ALGEBRA p123.pdf
Elements of Algebraic Topology e-part2 p111.pdf
Elman ZZZ Lectures in Abstract Algebra Preliminary Version p409.pdf

Elman Lectures in Abstract Algebra Preliminary Version p409

Evens Algebraic Topology p250

Evens Algebraic Topology p250.pdf

FIMA VERGNIOUX ON A COCYCLE IN THE ADJOINT REPRESENTATION OF THE ORTHOGONAL FREE QUANTUM GROUPS

Finan YYY A Semester Course in Basic Abstract Algebra p224.pdf
FINDELL ZZZ LEARNING AND UNDERSTANDING IN ABSTRACT ALGEBRA p433.pdf
Fink Classical Class Field Theory and Recent Developments p135.pdf
Finston YYY An Introduction to Abstract Algebra via Applications p127.pdf
Finston YYY An Introduction to Abstract Algebra via Applications p151.pdf
Fraleigh YYY Solutions to A First Course in Abstract Algebra p141.pdf

Fuller Analysis of affine equivalent boolea functions to encryption p167

GarrettPaul Abstract Algebra p412

Garrett YYY Intro Abstract Algebra p200.pdf
GarrettPaul Abstract Algebra p412.pdf
Gasarch Van der Waerdens Theorem Variants and Applications p210.pdf

Gasarch Van der Waerdens Theorem Variants and Applications p210

Gasarch Van der Waerdens Theorem Variants and Applications p210

Gilbert ZZZ Modern algebra with applications 347s.pdf
GilbertZZZ Modern algebra with applications 347s.pdf
Gonzalez lie.algebras.p179.pdf
GOODMAN ZZZ ALGEBRA ABSTRACT AND CONCRETE p580.pdf
GouveaZZZ How Algebra Became Modern p157.pdf
GublerYYY Algebra und Zahlentheorie p185.pdf
Hank ComputationalAlgebraicTopology p140.pdf
HefferonYYY Linear Algebra p463.pdf
Hermann ZZZ Abstract Algebra p383.pdf

Hermann Abstract Algebra p383

higheralgebra p950

higheralgebra p950.pdf
Hill YYY AbstractAlgebraForSecondaryMathTeachers p256.pdf
Hill ZZZ Abstract Algebra for Secondary Mathematics Teachers p383.pdf

Hill Abstract Algebra for Secondary Mathematics Teachers p383

Hobby The structure of finite algebra p212

Hobby The structure of finite algebra p212.pdf
Holm Gorenstein homological algebra PhDthesis p169.pdf
Hopkins algebraic topology p99.pdf
Howlett YYY An undergraduate course in Abstract Algebra p143.pdf
Hubery Commutative Algebra and Algebraic Geometry p112.pdf
HuberyXXX Fields and Galois Theory p110.pdf
Hulpke Notes on Computational Group theory p162.pdf
Hulpke YYY Abstract Algebra in GAP p179.pdf
humphreys Intro to lie algebras and representation theory p186.pdf
Hungerford Algebra p528.pdf

Hungerford Algebra p528

JacobsonZZZ Lectures On Quadratic Jordan Algebras p134.pdf
Jezek ZZZUNIVERSAL ALGEBRA p233.pdf

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Kleshchev Lectures on Algebraic Groups p166

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Knighten, Robert L.: Notes on Category Theory, November 9, 2007

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MilneL Etale Cohomology p202

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Morett Notes on Multi-Linear Algebra and Tensor Calculus p61

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Perry YYY Notes on Abstract Algebra p130.pdf
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Pivato Visual Abstract Algebra p243

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QuantumZZZ Algebra,Algebraic Topology,Category Theory,Higher Dimensional Algebra p434.pdf
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Ramanathan Lectures on the Algebraic Theory of Fields p228.pdf

Ramanathan Lectures on the Algebraic Theory of Fields p228

Roberts Introduction to Applied Algebraic Topology Persistent Homology p160.pdf
Rotman Advanced_modern_algebra_2003 p1056.pdf
Rotman Galois Theory p173 .pdf
Rotman-An Introduction to Homological Algebra 2nd Ed p721.pdf
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Siksek YYY Introduction to Abstract Algebra p115.pdf
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Simmons An introduction to Category Theory p436

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SpivakZZZ Category Theory for Scientists Old Version p267.pdf

Spivak Category Theory for Scientists p267

Starbird Algebraic Topology p127.pdf
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Stein A Brief Introduction to Classical and Adelic Algebraic Number Theory2004 p190

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Steinberger algebra p558

SteinbergerZZZ algebra p558.pdf
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Stewart Galois Theory p325????????????????????? 86

Stewart, Ian: Galois Theory, Chapman & Hall, 2003

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Tornero An introduction to global class field theory p206

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Vercruysse Galois Theory for Corings and Comodules p274

Vergnioux Haar integrals on finite and compact quantum groups

Vergnioux Groupes quantiques discrets et algèbres d'opérateurs

VERGNIOUX Habilitation à Diriger des Recherches Research Account

Vergnioux K-amenability for amalgamated free products of amenable discrete quantum groups

Vergnioux KK-théorie équivariante et opérateur de Julg-Valette pour les groupes quantiques

Vergnioux Mémoire

????????
R. Vergnioux, Orientation of quantum Cayley trees and applications, J. Reine Angew. Math. 580 (2005) 101–138.

Vergnioux Paths in quantum Cayley trees and L2-cohomology p26
Quantum Cayley graph
quantum Cayley trees

VERGNIOUX THE K-THEORY OF FREE QUANTUM GROUPS

VERGNIOUX THE PROPERTY OF RAPID DECAY FOR DISCRETE QUANTUM GROUPS

classical Cayley graph

Roland Vergnioux
roland.vergnioux@math.unicaen.fr
http://www.math.unicaen.fr/~vergnioux/index.html.en

Walker ZZZ AbstractAlgebraBook p317.pdf

Wallace Beginning and Intermediate Algebra p489

WEIBEL AN INTRODUCTION TO HOMOLOGICAL ALGEBRA p441.pdf
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weibel AN INTRODUCTION TO HOMOLOGICAL ALGEBRA p462

WeltmanYYY-College Algebra Revised p531.pdf
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Zeidler Abstract Algebra p488

German

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Naji Gruppentheorie und ZahlentheorieWeb p1099.pdf
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Russian

Linear Algebra

Charles L. Byrne
Department of Mathematical Sciences
University of Massachusetts Lowell
Byrne Applied and Computational Linear Algebra: A First Course p504

Beezer A First Course in Linear Algebra p980

Byrne Applied and Computational Linear Algebra A First Course p504

Cherney Linear Algebra p430

David Cherney, Tom Denton and Andrew Waldron

Dawkins Linear Algebra p331
2005 Paul Dawkins 1 http://tutorial.math.lamar.edu/terms.asp

Finan Fundamentals of Linear Algebra p196
Marcel B. Finan
Arkansas Tech University

Hefferon Linear Algebra p449

Algebra - Set Theory

Alexopoulos Notes on Set Theory and Probability Theory p37
Michelle Alexopoulos

Andre Axioms and Set Theory p459

Calini Set Theory and Logic p58
Supplementary Materials
Math 103: Contemporary Mathematics with Applications

Garbacz Set Theory p49
Pawel Garbacz

Kanamori SET THEORY FROM CANTOR TO COHEN p65
Akihiro Kanamori

Meadows Set Theory some basics and a glimpse of some advanced techniques p91
Toby Meadows

Nesin Foundations of Mathematics I Set Theory p170
(only a draft)
Ali Nesin

Roitman Introduction to Modern Set Theory p129
Judith Roitman

SIMONS Against Set Theory p14
PETER SIMONS

Weiss AN INTRODUCTION TO SET THEORY p119
Professor William A. R. Weiss

Universal Algebra
Burris A Course in Universal Algebra p331


Algebra - Boolean

Boolean Algebra / Logic Algebra

ANDREKA et al: ALGEBRAIC LOGIC, Aug 2003, p129.....................ok

Blumensath, Achim: Logic, Algebra & Geometry, DARMSTADT Jan 11, 2014,..p596................11 / .35

Couturat, LOUIS: The Algebra of Logic. 2004, p102.

Kang, Sungho: Boolean Algebra, July 2003, p107.................31

Kovács Boolean Algebra and Propositional Logic p51
Laura Kovács


Algorithm

Computer Algorithm / Progamming

Design and Analysis of Algorithms

algorithmic computer science

algorithms for linear and convex optimization

Network flow algorithms

Parallel Computing

Agarwal A Survey of Techniques Used in Algebraic and Number Theoretic Algorithms Kunming Tutorial, May 2005 p307

Cormen, Thomas H.: Introduction.to.Algorithms, Second Edition, The MIT Press, 2002????p1203..................................998

Dasgupta Algorithms p318
Copyright c
2006 S. Dasgupta, C. H. Papadimitriou, and U. V. Vazirani
July 18, 2006

Halbwachs Synchronous programming of reactive systems p16.pdf
Halbwachs Synchronous programming of reactive systems p182.pdf
Halbwachs Synchronous programming of reactive systems p26.pdf
Halbwachs Synchronous programming of reactive systems1 p26.pdf
Harel Statecharts A Visual Formalism for Complex Systems p44.pdf

Knuth The Art Of Computer Programming Vol 4 p200

Knuth The Art of Computer Programming Vol 2 p704

Knuth The Art of Computer Programming Vol 3 p792

Knuth The Art of Computer Programming Vol 4 prefascle oc p65

Knuth The art of computer progamming mmix p140

Knuth The art of computer programming GAC p65

Knuth The art of computer progamming mmix p140.pdf
Knuth The art of computer programming GAC p65.pdf
Knuth The Art of Computer Programming Vol 2 p704.pdf
Knuth The Art of Computer Programming Vol 3 p792.pdf
Knuth The Art Of Computer Programming Vol 4 p200.pdf
Knuth The Art of Computer Programming Vol 4 prefascle oc p65.pdf


Calculus

Chung Understanding Basic Calculus p292

34

Chung Understanding Basic Calculus p292
117

L00MIS ADVANCED CALCULUS p592

Predoi DIFFERENTIAL CALCULUS p279

Thomas Introduction to Differential Calculus p44

Thompson Calculus Made Easy p292


Category Theory

AWODEY Category Theory p328

Barr Category Theory p133

Bower Category Theory and Galois Theory p11
5

Cheng Category Theory p71

Easterbrook An introduction to Category Theory for Software Engineers p43
Dr Steve Easterbrook

9

Fokkinga A Gentle Introduction to Category Theory p80

Johnstone Part III - Category Theory p52

Oosten Basic Category Theory p88

Pareigis Category Theory p90

Riehl Category theory in context p258

SCHMITT A CONCRETE INTRODUCTION TO CATEGORIES p60

Streicher Introduction to CATEGORY THEORY and CATEGORICAL LOGIC p117

Turi Category Theory Lecture Notes p61


Memetic Algorithm

Memetic / Evolutionary / Genetic / Hierarchical / Advanced Local Search / Channel Routing / Algorithm

Memetic Algorithms for Channel Routing

Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit Layout in the form of circuit routing. The effect of local search, clustering and good initial solution on the overall Memetic algorithm by using the circuit routing as a paradigm.

The traditional approach in routing is to construct an initial solution by using constructive heuristic algorithms. A final solution is then produced by using iterative improvement techniques where a modification is usually accepted if a reduction in cost occurs, otherwise it is rejected.

Constructive heuristic algorithms produce an initial solution from scratch. It takes a negligible amount of computation time compared to iterative improvement algorithms and provides a good starting point for them. However, the solution generated by constructive algorithms may be far from optimal. Thus, an iterative improvement algorithm is performed next to improve the solution.

Begin
For j: =1 to μ do
I: =generate solution ();
I: =local search (I);
Add individual I to P;
endfor
Repeat
For i: = 1 to pcross. μ do
Select two parents IA,Ib ? P randomly;
Ic: =recombine (Ia, Ib);
Ic: =local-search(Ic);
Add individual Ic to P?;
endfor;
For i:= 1 to pmut . μ do
Select an indiv idual I ? P randomly ;
Im: =mutate (I);

Im: =local-search (Im);
Add individual Im to P?;
endfor
P: =select (P υ P?)
If converged (P) then P: =local-search (mutate (P));
Until terminate=true;
end;

Evolutionary

Evolutionary Computation VLSI routing

Evolutionary technique VLSI routing

This paper presented several approaches to integrating Evolutionary Computation models with local search techniques (i.e. Memetic Algorithms) for efficiently solving underlying VLSI circuit routing problems. The methodology presented in the paper explained how clustering reduces the complexity of the circuit and thereby enables the Evolutionary technique to explore the solution space more effectively.

Constructive heuristic techniques GRASP (greedy randomized adaptive search procedure)

Constructive heuristic techniques VLSI routing

GRASP (greedy randomized adaptive search procedure) VLSI routing

Constructive heuristic techniques in the form of GRASP (greedy randomized adaptive search procedure) and Cluster Growth were utilized to inject the initial population with good initial solutions to diversify the search and exploit the solution space.

Cluster Growth VLSI routing

Therefore, a hierarchical approach in the form of multilevel clustering is utilized to reduce the complexity of the search space. A bottom-up technique gradually clusters cells at several levels of the hierarchy. At the top level a Genetic Algorithm is applied where several good initial solutions are injected to the population.

Although iterative improvement algorithms can produce a good final solution, the computation time of such algorithms is also large. Therefore, a hierarchical approach in the form of multilevel clustering is utilized to reduce the complexity of the search space. A bottom-up technique gradually clusters cells at several levels of the hierarchy. At the top level a Genetic Algorithm is applied where several good initial solutions are injected to the population

Genetic Algorithm for Channel Routing

Genetic algorithms are optimization strategies that imitate the biological evolution process. A population of individuals representing different problem solutions is subjected to genetic operators, such as, selection, crossover and mutation that are derived from the model of evolution. Using these operators the individuals are steadily improved over many generations and eventually the best individual resulting from this process is presented as the best solution to the problem.

An overview of the genetic algorithm presented in this paper is shown in figure.

create initial population (Pc)
fitness_calculation (Pc)
pbest = best_individual (Pc)
for generation = 1 until max_generation
Pn = 0
for off spring = 1 until max_descendant
Pα= selection (Pc)
Pβ= selection (Pc)
Pn= Pn U crossover (pα, pβ)
endfor
fitness-calculation (pn)
Pc = reduction (Pc U Pn)
Pbest = best_individual (pbest U pc)
Mutation (Pc) fitness_calculation (Pc)
endfor
optimize (Pbest)

Creation of initial population

The initial population is constructed from randomly created routing structures, i.e .individuals. First, each of these individuals is assigned a random initial row number yind. Let S = {s1… si…sk} be the set of all pins of the channel which are not connected yet and let T = {t1…tj…tl} be the set of all pins having at least one connection to other pin. Initially T = 0. A pin Si ? S is chosen randomly among all elements in S. If T contains pins {tu...tj ...tv} (with 1≤u<v≤l) of the same net, a p in t j is randomly selected among them. Otherwise a second pin of the same net is randomly chosen from S and transferred into T. Both pins (si, tj) are connected with a so-called “random routin g”. Then si is transferred into T. The process continues with the next random selection of si ? S until S = 0. The creation of the initial population is finished when the number of completely routed channels is equal to the p op ulation size │Pc│. As a consequence of our strategy, these initial individuals are quite different from each other and scattered all over the search space.

Calculation of fitness

The fitness F (p) of each individual p ? P is calculated to assess the quality of its routing structure relative to the rest of the population P. The selection of the mates for crossover and the selection of individuals which are transferred into the next generation are based on these fitness values. First, two functions Fl (p) and F2(p ) are calculated for each individual p ? P according to equations (1) and (2).

F1 (p) = 1/nrow (1)
Where nrow = number of rows of p.
F2 (p) = 1/ Σnind
i=1(lacc (i) +a * lopp (i)) +b * vind
Where lacc (i) = net length of net i of net segments according to the preferred direction of the layer,
lopp (i) = net length of net i of net segments opposite to the preferred direction of the layer
a = cost factor for the preferred direction,
nind = number of nets of individual p,
vind= number of vias of individual p and b = cost factor for vias.

The final fitness F (p) is derived from Fl (p) and F2 (p) in such a way that the area minimization, i.e. the number of rows, always predominates the net length and the number of vias. After the evaluation of F (p) for all individuals of the population P these values are scaled linearly as described in order to control the variance of the fitness in the population.

Selection strategy

The selection strategy is responsible for choosing the mates among the individuals of the population Pc. According to the terminology of our selection strategy is actually stochastic sampling with replacement. That means any individual pi ? pc is selected with a probability

F (pi)/Σp?pcF (p)

The two mates needed for one crossover are chosen of each other. An individual may be independently selected any number of times in the same generation.

times in the same generation.
Connection on layer 1
Connection on layer 2
Via connection to the descendent
Net segments

Crossover operator

During the crossover, two individuals are combined to create a descendant. Let pα and pβ be copies of the mates and pγ be their descendant.

First, a cut column xc is randomly selected with 1 ≤ xc< xind, where xind represents the number of columns of the individuals. The individual pα (pβ) transfers the routing structure to pγ which is located to the left (right) of the cut column xc and not touched by xc. Assume that the part of pα (or pβ) which has to be transferred into pγ contains rows not occupied by any horizontal segments. Then the row number of pα (or pβ) is decremented by deleting this row until no empty row is left. The initial row number yindγ of pγ is equal to the maximum of (yindα, y indβ). The mate which now contains fewer rows than pγ is extended with additional row(s) at random position(s) before transferring its routing structure to pγ.

The routing of the remaining open connections in p γ is done in a random order by our random routing Strategy (see Figure4 (e, f)).

If the random routing of two points does not lead to a connection within a certain number of extension Lines, the extension lines are deleted and the channel is extended at a random position yadd with 1≤yadd ≤ y indγ. If the repeated extension of the channel also does not enable a connection, pγ is deleted entirely and the crossover process starts again with a new random cut column xc applied to pα and pβ.

The crossover process of creating pγ is finished with deleting all rows in pγ that are not used for any horizontal routing segment.

Reduction strategy

Our reduction strategy simply chooses the Pc fittest individuals of (Pc υ Pn) to survive as pc into the next generation

Mutation operator

Mutation operators perform random modifications on an individual. The purpose is to overcome local Optima and to exploit new regions of the search space. Our mutation operator works as follows. Define a surrounding rectangle with random sizes (xr, yr) around a random centre position (x, y, z).All routing structures inside this rectangle are deleted. The remaining net points on the edges of this rectangle are now connected

Local Search Technique with Dynamic Hill Climbing Capability

local search technique VLSI routing

A local search technique with dynamic hill climbing capability is applied to the chromosomes to enhance their quality. The system tackles some of the hard constraints imposed on the problem with intermediate relaxation mechanism to further enhance the solution quality. The pseudo-code for memetic algorithm is presented given below.

Furthermore, the local search technique was able to enhance the convergence rate of the Evolutionary Algorithm by finely tuning the search on the immediate area of the landscape being considered.

A local search technique with dynamic hill climbing capability is applied to the chromosomes to enhance their quality. The system tackles some of the hard constraints imposed on the problem with intermediate relaxation mechanism to further enhance the solution quality. The pseudo-code for memetic algorithm is presented given below.

Local Search

global and local search

Local search is a general-purpose optimization method that works with fully sp ecified solutions f ? F of a problem instance (F, c). it makes use of the notion of a neighborhood N(f) of a feasible solution f, which consist of a subset of f that is close to f in some sense neigborhood is a function that assigns a number of feasible solutions to each feasible solution: N : F 2F. Here 2F denotes the power set of F, the set of all its subsets. Any g ? N (f) is called a neighbor of f.

Local_search ()
{
Struct feasible_solution f;
Set of struct feasible_solution G;
F initial_solution ();
Do
{
G {g|g ? N (f), c (g) < c (f)};
If (G! =0)
F any element of G;
}
while (G! =0);
Report f;
}
Figure 5: the pseudo-code description of local search
The principle of local search is too subsequently Visit a number of feasible solutions in the search space, each solution being in the neighborhood of the previous one. Such a transition from one solution to the next is called a move or a local transformation. One starts with a feasible solution f and then moves to some g ?N (f), such that c (g) < c (f).This is repeated until some feasible solution is found.

Hierarchical Channel Router

hierarchical wire routing

Hierarchical routing

Hierarchical wire routing

boundary crossing placement

Hierarchical Routing

Hierarchical Channel Router

Hierarchical Channel Router

? Uses a divide-and-conquer approach.
– A routing problem in m×n grid is reduced to 2×n grid.
– Each column in these sub-grids is treated as a supercell.
– Capacity of each vertical boundary is the sum of corresponding boundary capacities.
– Nets are routed one at a time in the 2×n grid.
– Each row of 2×n is partitioned into 2×n grid.
– Terminal position for the new 2×n grids are defined by the routing in the previous hierarchy.

Hierarchical Channel Router
 Uses a divide and conquer approach.
 A routing problem in m n grid is reduced to 2  n grid.
 Each column in these subgrids is considered as a supercell.
 Capacity of each vertical boundary is the sum of corresponding boundary capacities.
 Nets are routed one at a time in the 2  n grid.
 Each 2  n, grid is partitioned into a 2  n grid.
 Terminal positions for the new 2  n are de ned by the routing

in previous hierarchy.

=============================
Burstein and Pelavin

=============================

Probabilistic Memetic Algorithm

Hong, Chuleui and Kim, Yeongjoon: The Efficient Hybrid Approach to Channel Routing Problem p8, International Journal of Advanced Science and Technology Vol. 42, May, 2012

Pal, Rajat K. et al: A Mimetic Algorithm for Computing a Nontrivial Lower Bound on Number of Tracks in Two-Layer Channel Routing p12, Journal of Physical Sciences, Vol. 11, 2007, 199-210

Varatharajan.R: An Effective Memetic Algorithm for Solving Channel Routing Problems, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Journal of Computer Applications (IJCA), p 17-22


Search Methods

Search Methods/Search techniques/Search algorithms

Adaptive Search

Adaptive Search

Greedy randomized adaptive search procedures (GRASP)

Parallel GRASP

A GRASP is an iterative process for nding approximate solutions to combinatorial optimization. Let, as before, f (x) denote the objective function to be minimized over a feasible domain D. A generic layout of GRASP is given in Figure 4. The GRASP iterations terminate when some stopping criterion, such as maximum number of iterations, is satised. Each iteration consists of a construction phase, and a local search phase. If an improved solution is found, then the incumbent is updated. A high-level description of these two phases is given next.

Layout of GRASP
Input: A problem instance
Output: A (sub-optimal) solution
1. Initialization: set x = ￥;
2. while (stopping criterion not satised) do
(a) Construct a greedy randomized solution x;
(b) Find local minimum ? x in neighborhood N(x) of x;
(c) If f ( ? x) < f (x) then update x = ? x;
3. Output the best solution found x;

In the construction phase, a feasible solution is built up, one element at a time. The choice of the next element to be added is determined by ordering all elements in a candidate list with respect to a greedy function. An element from the candidate list is randomly chosen from among the best candidates in the list, but is not necessarily the top candidate. The solution set S is initialized empty, and the construction iterations are repeated until the solution is built. To do this, the restricted candidate list is setup. This candidate list contains a subset of candidates that are well ordered with respect to the greedy function. A candidate selected from the list at random is added to the solution. The greedy function is adapted to take into account the selected element.

The solutions generated in the construction are not guaranteed to be locally optimal and therefore local search is applied to produce a locally optimal solution.

GRASP can be easily implemented on an MIMD multi-processor environment. Each processor can be initialized with its own copy of the procedure, the problem data, and independent pseudo-random number sequences. The GRASP iterations are then independently executed in parallel and the best solution found over all processors is the GRASP solution. This approach was implemented by Pardalos, Pitsoulis, and Resende [39] to approximately solve instances of the QAP of dimension up to n = 128. On a Kendall Square KRS-1 parallel computer with 128 processors (of which only 64 were utilized), the authors were able to achieve on average a speedup factor of 62 and speedup factors of 130 and 221 on single instances of dimensions n = 30 and n = 22, respectively.

Another approach to implement GRASP parallel was proposed by Feo, Resende, and Smith, where the problem being optimized is decomposed into many smaller problems, and each processor is given a set of small problems, that are solved with GRASP one after the other. Using this approach to approximately solve large instances of the maximum independent set problem, the authors were able to achieve almost linear speedup on an eight processor Alliant FX/80 MIMD computer.

=======================================================

Best-First Search (BeFS)

used to find optimal solutions w/ any cost function, Can be done when a provable lower-bound of the cost can be determined for each branching choice from the “current partial soln node” [e.g., TSP, global routing]

Binary Search

Branch and Bound

Breadth-First Search (BFS)

mainly used to find a soln at min. distance from root of search tree [e.g., maze routing when cost = dist. from root]

Breadth- rst search (BFS) is a strategy for running through the nodes of a graph.

Depth-First Search (DFS)

mainly used to find any solution when cost is not an issue [e.g., FPGA detailed routing---cost generally determined at the global routing phase]

A depth- rst search is a type of algorithm that visits each vertex of a graph, proceeding from vertex-to-vertex in this search but moving along a spanning tree of that graph.

Exact Search Algorithms

Greedy Randomized Adaptive Search Procedures (GRASP)

Heuristic Search Algorithms

Local Search

After a prescribed number of iterations by evolutionary algorithm local search algorithm is applied to few random individual to have better solution. Local search methods are iterative algorithms that tend to enhance solution by stepwise improvement and make an attempt to reach optimum solutions. More often results in suboptimal solutions by trapping themselves in local minima/maxima. The simplest form of local search is repetitively flipping elements in a solution resulting a gain in the objective function. Eventually local minima will be reached whereby flipping any element in the solution will result in loss of object. Although these algorithms are simple, there have been many complex improvements for CAD tools which involve large dynamic memory and linked list usages. For refining the solution obtained by GA, the local search(LS) is applied. This can be used before cross over or after cross over, it can also be used for parents selection, and used before or after mutation to increase the number of fitness variables.

Parallel Search Algorithms

Parallel Search

Parallel Heuristic Search

Scatter Search Algorithm

Tabu Search

Tabu search belongs in the class of local search techniques, after finding local optima the solution is marked as tabu (taboo) so that the algorithm does not visit that possibility in the near future.

Parallel Tabu Search


Simulated Annealing

Simulated Annealing 1983

Simulated annealing is a popular algorithm which produces nearoptimal solutions to combinatorial optimization problems. It is commonly thought to be slow. Use of estimated cost functions common in VLSI placement and parallel algorithms which generate errors can increase speed but degrade the outcome.

Ackley function

Metropolis algorithm

for approximate numerical simulation of the behavior of a manybody system at a finite temperature

Parallel Simulated Annealing

Evolutionary design of digital circuits / evolutionary logic design

Simulated Evolution algorithm

Simulated annealing channel routing

parallel channel routing algorithm for Simulated annealing channel routing?

parallel simulated annealing-based channel routing algorithm

Literature
AL-SAIARI, UTHMAN SALEM: DIGITAL CIRCUIT DESIGN THROUGH SIMULATED EVOLUTION November 2003 p164........................

Chibante Simulated Annealing Theory with Applications p300 ........................

Greening, Daniel Rex: Simulated Annealing with Errors, 1995. p158.

Grimwood, Geoffrey Ross: The Euclidean Steiner Tree Problem: Simulated Annealing and Other Heuristics, Master Thesis, 1994 p342....................

Kirkpatrick, S. ; Gelatt, C. D. ; and Vecchi, M. P.: Optimization by Simulated Annealing, Science, New Series, Vol. 220, No. 4598. (May 13, 1983), pp. 671-680, p12

Nahar, Surendra: SIMULATED ANNEALING AND COMBINATORIAL OPTIMIZATION, 1986, p7

Neller, Todd W. and La Pilla, Christopher J.: Decision-Theoretic Simulated Annealing, May 20, 2010, p14

Rutenbar, R. A.: Simulated Annealing Algorithms An Overview, p8, Jan 1989

Sechen Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing p9


Operations Research / Combinatorial Optimization

The subject of combinatorial optimization consists of a set of problems that are central to the disciplines of computer science and engineering. Research in this area aims at developing efficient techniques for finding minimum or maximum values of a function of very many independent variables. This function, usually called the cost function or objective function, represents a quantitative measure of the "goodness" of some complex system. The cost function depends on the detailed configuration of the many parts of that system.

There are four types of optimization problems, i.e.,

  • constrained optimization,
  • multimodal optimization,
  • multiobjective optimization, and
  • combinatorial optimization,

which form the central core of optimization and thus the main topics in the field of operations research (OR).

Optimization theory

C onstrained optimization

Multimodal optimization

Multiobjective optimization

Multi-Objective Optimization

Discrete Optimization Problems (DOP)

Stochastic Optimization Algorithms

Black-box optimization algorithms

Black box optimization tools

Specially designed optimization algorithms

Optimal control of partial differential equations

Combinatorial Optimization / Combinatorics

Additive Combinatorics

Algebraic combinatorics

Geometric Combinatorics

Polyhedral combinatorics

Enumerative combinatorics

Existential combinatorics

Constructive combinatorics

Combinatorial algorithms

Combinatorial analysis

Combinatory analysis

The document depository:

combinatorics.docx

Combinatorial Optimization for Algorithmic Design

Literature

Berthe, Valerie and Rigo, Michel: Combinatorics, Automata and Number Theory, p86, Dec 2009

Brualdi, Richard A.: Introductory combinatorics, Fifth Edition, p618, Pearson, 2010...................

Comtet, Louis: Advanced Combinatorics p177, D Reidel Publishing, 1974

Cook, William J. et al: Research Trends in Combinatorial Optimization p565???Springer 2009 ............................. 19

DAHL, GEIR and MANNINO, CARLO: NOTES ON COMBINATORIAL OPTIMIZATION p80?????October 1, 2012 .

Gasarch, William: A Survey of Recursive Combinatorics, May 2007, p131

Graham Handbook of Combinatorics Vol 2 , Elsevier, 1995, p640??.............................14

Groetschel, Martin: Development in combinatorial optimization p46, Birkhaeuser Verlag, 1984

Harris, John M. , Hirst, Jeffry L. and Mossinghoff, Michael J.: Combinatorics and Graph Theory, Second Edition, Springer, 2008, p392? .................................

Hasle, Geir: Discrete Optimization - Heuristics p239, January 11.-16. 2009?.............................?57

Hellenoid, Geir T.: Algebraic Combinatorics p93, 2008

Keller, Mitchel T. and Trotter, William T.: Applied Combinatorics, Preliminary Edition, January 6, 2013, p345 .............................

Korte, Bernhard and Vygen, Jens: Combinatorial Optimization - Theory and Algorithms, Fourth Edition, Springer, 2008 p646.............................9

LAWLER, EUGENE L.: Combinatorial Optimization: Networks and Matroids, Holt, Rinehart and Winson, 1976 p384

MARTELLO, Silvano et al: SURVEYS IN COMBINATORIAL OPTIMIZATION, ELSEVIER SCIENCE PUBLISHERS, 1987 p395.............................72

Pardalos, Panos M. et al: Parallel Search for Combinatorial Optimization Genetic Algorithms, Simulated Annealing, Tabu Search and GRASP, Workshop on Parallel Algorithms for Irregularly Structured Problems, Lyon, France (September 4?6, 1995), p14

Schrijver, Alexander: A Course in Combinatorial Optimization, February 1, 2006, p223

SRIVASTAV,ANAND: DERANDOMIZATION IN COMBINATORIAL OPTIMIZATION, Kluwer Academic Publishers, p135

SRIVASTAV, ANAND: DERANDOMIZATION IN COMBINATORIAL OPTIMIZATION p135 Kluwer Academic Publishers Dec 2013................................ 6

van Lint, J. H. and Wilson, R. M.: A Course in Combinatorics, SECOND EDITION, Cambridge University Press, 2001, p618 .................. 24

@@@@@@@@@@@@@@@@@@@@@@@@@@@@

Vygen, Jens: Combinatorial Optimization and Applications in VLSI Design p204 March 2006 ..........................

Wolpert, David H and Macready, William G. : No Free Lunch Theorems for Optimization, IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. 1, NO. 1, APRIL 1997, p16 .

=============================

Brualdi Introductory combinatorics p618.pdf
Chibante Simulated Annealing Theory with Applications p300.pdf
Cook Research Trends in Combinatorial Optimization 2009 p565.pdf
Dantzig Linear programming vol 1 Introduction p474.pdf
Dantzig Linear programming vol 2 Theory and Extensions p475.pdf
De Jong The Handbook of Evolutionary Computation p940.pdf
Graham Handbook of Combinatorics Vol 2 p640.pdf
Guichard An Introduction to Combinatorics and Graph Theory p141.pdf
Guichard An Introduction to Combinatorics and Graph Theory p149.pdf
Guichard An Introduction to Combinatorics and Graph Theory p153.pdf
Harris Combinatorics and Graph Theory p392.pdf
Hendler Foundations of Artificial Intelligence p1035.pdf
Keller Applied Combinatorics p345.pdf
Kennedy Swarm intelligence p541.pdf
Korte Combinatorial optimization theory and algorithms 2007 p646.pdf
MARTELLO Surveys in Combinatorial Optimization p395.pdf
Schrijver A Course in Combinatorial Optimization p223.pdf
Vanderbei Linear Programming Foundations and Extensions p466.pdf
Yu Introduction to Evolutionary Algorithms p433.pdf
dos Santos Evolutionary Computation p582.pdf
van Lint A course in combinatorics p618.pdf

Miscellenous Algorithms

Algorithms directly applied to chip design at various stages, and possibly also for other phases of chip life cycles such as research and development, fabrication, packaging, testing etc. Algorithms involved include the most popular techniques such as evolutionary, genetic, simulated annealing, particle swarm partition, heuristics, iterative, memetic, neuro networks, multi-commodity flow, and other methods.
These algorithms are very popular at the moment in the design of ICs' various stages such as physical design. How they can be optimized is a great challenge, though.

analytical methods physical placement

Ant Colony Optimization

Ant Colony Optimization 2006/2007???

Ant Colony Optimization (ACO) is a recently proposed metaheuristic approach for solving hard combinatorial optimization problems. The inspiring source of ACO is the pheromone trail laying and following behavior of real ants, which use pheromones as a communication medium. In analogy to the biological example, ACO is based on the indirect communication of a colony of simple agents, called (artificial) ants, mediated by (artificial) pheromone trails. The pheromone trails in ACO serve as distributed, numerical information, which the ants use to probabilistically construct solutions to the problem being solved, and which the ants adapt during the algorithm’s execution to reflect their search experience.

The first example of such an algorithm is Ant System (AS), which was proposed using as an example application the well-known Traveling Salesman Problem (TSP). Despite encouraging initial results, AS could not compete with state-of-the-art algorithms for the TSP. Nevertheless, it had the important role of stimulating further research on algorithmic variants, which obtain much better computational performance, as well as on applications to a large variety of different problems. In fact, now there exists a considerable amount of applications obtaining world class performance on problems like the quadratic assignment, vehicle routing, sequential ordering, scheduling, routing in Internet-like networks, and so on. Motivated by this success, the ACO metaheuristic has been proposed as a common framework for the existing applications and algorithmic variants. Algorithms, which follow the ACO metaheuristic, will be called ACO algorithms.

Ant Colony Optimization with Tabu Search

Ant Colony Optimization Routing Algorithm with Dynamic Local Search 2006/2007

Ant Colony Optimization Routing Algorithm with Tabu Search 2010

blind alley

Literature

Pandhi, Rohtash Bhushan: VLSI Circuit Partitioning Using Ants Colony Optimization, Master Thesis, , June 2004, p67

Yoshikawa, Masaya and Otani. Kazuo Ant Colony Optimization Routing Algorithm with Tabu Search March 2010, p4

Approximation algorithms and mathematical programming

Artificial intelligence

Artificial Intelligence (AI)

boolean_algebra_design

Boolean algebra for Chip / VLSI Design

Boolean algebra for switching circuit design

Literature

Staehler, Robert E: An Application of Boolean algebra to switching circuit design p26 1952 ,,,,,,,,ok

computational_physical_layout

computer_arithmetic_design

Constraint logic programming

Constraint Logic Programming CLP is a merger of two declarative paradigms: constraint solving and logic programming.

stochastic programming approach with chance constraints

Stochastic Chance Constrained Programming

Prolog

Beta-Prolog

Backtracking algorithm

state tables

constraint satisfaction problem

Deutsch's diofficult problem

Jaffar, Joxan and Maher, Michael J: Constraint Logic Programming: A Survey, 2005, p84.

Niederlinski, Antoni: A gentle guide to Constraint Logic Programming via eclipse, 2014, p545.

Logic programming channel routing?

Constraint satisfaction

Convex optimization

Luo, Chaomin: Novel Convex Optimization Approaches for VLSI Floorplanning, 2008, PhD Thesis, p187......................28

curvilinear_detailed_routing

Divide & Conquer (D&C)

[e.g., merge-sort, partition-driven placement

hierarchical or divide-&-conquer (D&C) manner:

Dynamic programming

Dynamic Programming

Bellman pioneered the systematic study of dynamic programming in the 1950s.

Dynamic Programming is an algorithm design technique for optimization problems: often minimizing or maximizing.

Dynamic Programming: Appropriate when you have recursive subproblems that are not independent

Dynamic Programming (DP) is useful to solve this sort of recursive problem".

Dynamic programming

Dynamic programming, like the divide-and-conquer method, solves problems by combining the solutions to subproblems. Divideand- conquer algorithms partition the problem into independent subproblems, solve the subproblems recursively, and then combine their solutions to solve the original problem. In contrast, dynamic programming is applicable when the subproblems are not independent, that is, when subproblems share subsubproblems.

Like divide and conquer, DP solves problems by combining solutions to subproblems.

Unlike divide and conquer, subproblems are not independent. Subproblems may share subsubproblems, However, solution to one subproblem may not affect the solutions to other subproblems of the same problem.

DP reduces computation by Solving subproblems in a bottom-up fashion. Storing solution to a subproblem the first time it is solved. Looking up the solution when subproblem is encountered again.

Key: determine structure of optimal solutions

A dynamic-programming algorithm solves every subsubproblem just once and then saves its answer in a table, thereby avoiding the work of recomputing the answer every time the subsubproblem is encountered.

Dynamic programming is typically applied to optimization problems. In such problems there can be many possible solutions. Each solution has a value, and we wish to find a solution with the optimal (minimum or maximum) value. We call such a solution an optimal solution to the problem, as opposed to the optimal solution, since there may be several solutions that achieve the optimal value.

Steps in Dynamic Programming

The development of a dynamic-programming algorithm can be broken into a sequence of four steps.
1. Characterize the structure of an optimal solution.
2. Recursively define the value of an optimal solution.
3. Compute the value of an optimal solution in a bottom-up fashion.
4. Construct an optimal solution from computed information.

  • Characterize structure of an optimal solution.
  • Define value of optimal solution recursively.
  • Compute optimal solution values either top-down with caching or bottom-up in a table.
  • Construct an optimal solution from computed values.

Steps 1–3 form the basis of a dynamic-programming solution to a problem. Step 4 can be omitted if only the value of an optimal solution is required. When we do perform step 4, we sometimes maintain additional information during the computation in step 3 to ease the construction of an optimal solution.

matrix multiplication

optimal buffer insertion
Murali, T. M.: Lecture 15 Dynamic Programming, October 14-28, 2009, p195............59

Evolutionary algorithms

Evolutionary Computation / Evolutionary Algorithm

Evolutionary Computation is the field of study devoted to the design, development, and analysis of problem solvers based on natural selection (simulated evolution).

Evolutionary Computation is further divided into:

  • Genetic Algorithm (GA)
  • Genetic Programming (GP)
  • Evolutionary Strategies (ES)
  • Evolutionary Programming (EP)

Simulated Evolution

Stochastic Evolution

stochastic evolutionary computing (EC) algorithms

Evolutionary Algorithms for the physical design of VLSI circuits?????????

========================================

COPY, STINFO: HYBRID ARCHITECTURES FOR EVOLUTIONARY COMPUTING ALGORITHMS January 2008 p158

De Jong Kenneth; Fogel, Lawrence and Schwefel, Hans-Paul: The Handbook of Evolutionary Computation, 1997 IOP Publishing Ltd and Oxford University Press, p940.

dos Santos, Wellington Pinheiro: Evolutionary Computation, 2009 In-teh, p582.

Shanavas, I. Hameem and Gnanamurthy, R. K.: Physical Design Optimization Using Evolutionary Algorithms, International Journal of Computer and Electrical Engineering, Vol. 4, No. 3, June 2012, p7 ......................... ok

Trapp, Matthias: Evolutionary algorithms an introduction.pps

Yu, Xinjie and Gen, Mitsuo: Introduction to Evolutionary Algorithms, Springer, 2010, p433 ......................... 28

Flow based

Fuzzy

fuzzy mathematical programming for circuit optimization considering the uncertainty due to process variations

Fuzzy set theory

fuzzy linear program

fuzzy membership functions

fuzzy numbers and fuzzy programming

Genetic Algorithm

Goodman, Erik D.: Introduction to Genetic Algorithms, GEC Summit (World Summit on Genetic and Evolutionary Computation), Shanghai, June, 2009, p81...............

Thangavelu Genetic Algorithms A Tutorial p92.

Genetic Algorithm for VLSI Design

In the 1960's, biologists began to use digital computers to perform simulations of genetic systems. Although these studies were aimed at understanding natural phenomena, some were not too distant from the modern notion of a genetic algorithm (GA). Genetic algorithms, as they are used today, were rst introduced by John Holland. Genetic algorithms try to imitate the development of new and better populations among different species during evolution, just as their early biological predecessors. Unlike most standard heuristic algorithms, GAs use information of a population of individuals (solutions) when they conduct their search for better solutions and not only information from a single individual. GAs have been applied to a number of problems in combinatorial optimization. In particular, the development of parallel computers has made this an interesting approach.

A GA aims at computing sub-optimal solutions by letting a set of random solutions undergo a sequence of unary and binary transformations governed by a selection scheme biased towards high-quality solutions. Solutions to optimization problems can often be coded to strings of nite length. The GAs work on these strings. The encoding is done through the structure named chromosomes, where each chromosome is made up of units called genes. The values of each gene are binary, and are sometimes called alleles. The problem is encoded by representing all its variables in binary form and placing them together in a single chromosome. A tness function evaluates the quality of a solution represented by a chromosome.

There are several critical parts which strongly affect the success of genetic algorithms:
? Representation of the solutions.
? Generation of the initial population.
? Selection of which individuals in an old population that will be allowed to affect the individuals of a new population. In terms of evolution, this relates to the selection of suitable parents in the new population.
? Genetic operators, such as crossover and mutation. That is, how to recombine the genetic heritage from the parents in the previous generation.
If P(t) denotes the population at time t, the GA can be described as in Figure (1).

P(0) is usually generated at random. The evaluation of a population P(t) involves computing the tness of the individuals and checking if the current population satises certain termination conditions. Types of termination rules include:

? A given time limit which is exceeded.
? The population is dominated by a few individuals.
? The best objective function value of the populations is constant over a given number of generations.

======================================

Layout of Genetic Algorithm

Input: A problem instance
Output: A (sub-optimal) solution
1. t = 0, initialize P(t), and evaluate the tness of the individuals in P(t)
2. while (termination condition is not satised) do
(a) t = t +1
(b) Select P(t), recombine P(t) and evaluate P(t)
3. Output the best solution among all the population as the (sub-optimal) solution.

Parallel Genetic Algorithms (PGAs)

Due to their inherent parallel properties, GAs have been successfully implemented on parallel computers, introducing this way a new group of GAs, Parallel Genetic Algorithms (PGAs). In a PGA the population is divided into subpopulations and an independent GA is performed on each of these subpopulations. Furthermore, the best individuals of a local population are transferred to the other subpopulations. Communication among the subpopulations is established to facilitate the operations of selection and recombination. There are two types of communication: (1) among all nodes where the best string in each subpopulation is broadcasted to all the other subpopulations, and (2) among the neighboring nodes, i.e. only the neighboring subpopulations receive the best strings.

The most important aspects of PGAs, which result in a considerable speedup relative to sequential GAs, are the following:
? Local selection, i.e. a selection of an individual in a neighborhood is introduced, in contrast with the selection in original GAs which is performed by considering the whole population.
? Asynchronous behavior which allows the evolution of different population structures at different speeds, possibly resulting in an overall improvement of the algorithm in terms of CPU time.
? Reliability in computation performance, i.e. the performance of one processor does not affect the performance of the other processors.

Jog et al. consider two basic categories of parallel genetic algorithms:
1. The coarse-grained PGAs, where subpopulations are allocated to each processor of the parallel machine. The selection and recombination steps are performed within a subpopulation.
2. The ne-grained PGAs, where a single individual or a small number of individuals are allocated to each processor.

======================================

GA for VLSI Design, Layout and Test automation- partitioning-automatic placement, routing technology, Mapping

for FPGA- Automatic test generation- Partitioning algorithm Taxonomy-Multi way Partitioning.

Advanced Algorithms in Genetic Algorithm

Hybrid genetic – genetic encoding-local improvement-WDFR-Comparison of Cas- Standard cell placement-GASP

algorithm-unified algorithm.

=========================================

minimizing silicon area

wirelength minimization

Multiscale Optimization in VLSI Physical Design Automation

Genetic Algorithm Based ATPG

A simple genetic algorithm (GA) can be used for the generation of individual test vectors for combinational as well as sequential circuits. In a typical GA, a population of individuals (or chromosomes) is defined, where each individual is a candidate solution for the problem at hand. As the individual represents a test vector for combinational circuit test generation, each character in the individual is mapped to a primary input. If a binary coding is used, the individual simply represents a test vector. Each individual is associated with a fitness, which measures the quality of this individual for solving the problem. In the test generation context, this fitness measures how good the candidate individual is for detecting the faults. The fitness evaluation can simply be computed by logic or fault simulation. Based on the evaluated fitness, the evolutionary processes of selection, crossover, and mutation are used to generate a new population from the existing population. The process is repeated until the fitness of the best individual cannot be improved or is satisfactory.

One simple application of GAs for test generation is to select the best test vectors for each GA run. A simple view of a GA framework is illustrated in Figure 4.38. The test generator starts with a random population of n individuals, and a (fault) simulator is used to calculate the fitness of each individual. The best test vector evolved in any generation is selected and added to the test set. Then, the fault set is updated by removing the detected faults by the added vector(s). The GA process repeats itself until no more faults can be detected.

Because a new random population is used initially, the GA process may not guarantee that a successful vector can be found. Likewise, in sequential circuits, a number of vectors may be necessary to drive the circuit to a state before the fault can be excited. Therefore, a progress limit should be used to limit the amount of execution allowed before the the entire process stops. When the population does not start with a right combination of individuals, the GA process may not result in an effective test vector. When this happens, the GA is reinitialized with a new random population, and a new GA attempt proceeds. This overall procedure is shown in Algorithm 13.
Note that in this procedure, the GA operators of selection, crossover, and mutation are applied in each iteration. Rather than exposing the reader to the numerous schemes for each GA operator, the following discussion will focus on the classic methods. First, for the selection operator, two popular schemes are often used: binary tournament selection and roulette wheel selection. In binary tournament selection, to select one individual from the population, two individuals are first randomly chosen from the population, and the one with the greater fitness value is selected as a parent individual. This is repeated to select a second parent. Note that, because a comparison is made in the process, selection is biased toward the more fit individuals. In the roulette wheel selection scheme, the n individuals in the population are mapped onto n slots on the wheel, where the size of each slot corresponds to the fitness of the individual, as illustrated in Figure 4.39. Thus, when the roulette wheel is spun, the position where the marker lands will determine the individual selected. Note that both roulette wheel and binary tournament selections may be conducted with or without replacement. When no replacement is used, the individuals selected are not put back into the population for the subsequent selection. In other words, an individual will not be selected more than once as a candidate parent individual. Finally, when comparing the effectiveness of roulette wheel with binary tournament selections, the notion of selection pressure is necessary. Selection pressure is the driving force that determines the convergence rate of the GA population, in which the population converges to n identical (or very similar) individuals. Note that fast convergence may not necessarily lead to a better solution. Roulette wheel selection with replacement results in a higher selection pressure than binary tournament selection when there are some highly fit individuals in the population. On the other hand, when individuals’ fitnesses have a small variance, binary selection will apply a higher selection pressure.

Algorithm 13 Simple_GA_ATPG
1: test set T =?;
2: while there is improvement do
3: initialize a random GA currentPopulation;
4: compute fitness of currentPopulation;
5: for i = 1 to maxGenerations do
6: add the best individual to test set T;
7: nextPopulation =?;
8: for j = 1 to populationSize/2 do
9: select parent1 and parent2 from currentPopulation;
10: crossoverparent1 parent2 child1 child2;
11: mutatechild1;
12: mutatechild2;
13: place child1 and child2 to nextPopulation;
14: end for
15: compute fitness of nextPopulation;
16: currentPopulation = nextPopulation;
17: end for
18: end while

The next GA operator to be discussed is the crossover operator. Again, the discussion will focus on classic crossover techniques. In essence, once two parent individuals are selected, crossover is applied to the two parent individuals to produce two children individuals, where each child inherits parts of the chromosomes from each parent. The idea behind crossover is that the building blocks from two different solutions are combined in a random fashion to produce two new solutions. Intuitively, a more fit individual contains more valuable building blocks when compared with a less fit individual. Because the selection biases toward more fit individuals, the building blocks from the more fit parents are passed down to the next generation. When the valuable building blocks from different fit parents are combined, more fit individuals may result. In the following, one-point, two-point, and uniform crossover are explained.

Suppose the length of an individual is . In one-point crossover, the two parents are crossed at a randomly chosen point, r, between 1 and ?1. Consequently, the first child inherits the first r bits from parent #1 and the final ?r bits from parent #2, while the second child inherits the first r bits from parent #2 and the final ?r bits from parent #1. Table 4.7 illustrates an example of the one-point crossover scheme. The vertical line in the table indicates the crossover point.

Similar to the one-point crossover, two-point crossover works in a similar fashion except that two points are chosen instead of one. The portion of the parent individuals between the two points are swapped to produce the new individuals. Table 4.8 illustrates an example for the two-point crossover scheme. Again, the vertical lines indicate the crossover point.

Finally, in uniform crossover, a crossover mask is first generated randomly, and the bits between the two parent individuals are swapped whenever the corresponding bit position in the crossover mask is one. Table 4.9 illustrates an example for the uniform crossover scheme.

The third GA operator to be discussed is the mutation operator. It allows the child individual to vary slightly from the two parents it had inherited. The mutation operator simply selects a random bit position in an individual and flips its logic value with a mutation probability. An example of mutating bit #3 is shown in Table 4.10. Let  be the mutation probability. If  is too small, children individuals that are produced after crossover may rarely see any mutation. In other words, it is less likely that new genes (building blocks) will be produced. On the other hand, if  is too large, too much random perturbation may occur, and the resemblance may soon be lost after a few generations.

Issues Concerning the GA Population

The population size should be a function of the individual length. In sequential circuits, the individual length is equal to the number of primary inputs in the circuit multiplied by the test sequence length. The population size may be increased from time to time to increase the diversity of the individuals, thereby helping to expand the search space.

One pertinent issue in the GA population is the encoding of the individuals: whether a binary or nonbinary coding should be used. In a binary coding, the individual is simply the test vector itself (or a sequence of vectors in the case of sequential circuits). Thus, the GA operates directly on that string. For instance, bitwise crossover and bitwise mutation can be used. (Bitwise mutation is simply the flipping of a single bit in the vector.) On the other hand, in a nonbinary coding, several bits are combined and represented by a separate character in the alphabet, and the GA operates on the individual as a string of characters. Special operators are needed for the nonbinary alphabet. For example, crossover can now occur only at multi-bit boundaries, and mutation involves replacing a given character in an individual with a randomly generated character. Finally, in a nonbinary coding, a larger population size and mutation rate may be required to ensure adequate diversity.

Obtaining a compact test set is another concern; thus, an accurate fitness measure is needed. As fault simulation is used to compute the fitness, computation of the fitnesses in each GA generation can be costly. To reduce this cost, approximation can be used, in which a fault sample from the complete fault list may be used. In doing so, fault simulation only has to consider the faults in the sample rather than the entire fault list.

Another method to reduce the execution time is to use overlapping populations in the GA. In overlapping populations, some individuals from the parent generation are copied over to the offspring generation. Therefore, only a fraction of the population is replaced in each generation.

The success of using GAs to obtain the desired solution depends also on how the GA parameters are chosen. First and foremost, the population size of the GA should be such that adequate diversity is represented. In the context of test generation, certain values on specific primary inputs may be necessary to excite a fault. If no individual in the initial population has this specific combination, then none of the strings in the population would have been able to excite the fault. As the number of bit combinations increases exponentially with the vector length, the population size should be large enough to appropriately reflect the embedded diversity. However, the population should not be too large to the extent that the cost of evaluating the fitnesses of individual becomes infeasible. These two factors must be carefully considered when determining the GA population size.

Issues Concerning GA Parameters

The first GA parameter to be considered is the number of generations necessary to achieve a desirable solution. Similar to population size, the number of generations necessary to obtain an individual with a specific bit pattern requires the GA designer’s attention. For instance, if the target fault demands a pattern of “1011” among four bits in the vector, and if this pattern is absent in the initial population, it may take several generations before an individual arrives at this pattern. The number of generations is also related to the population size. Larger populations will likely require more generations to allow for more diverse pairs of individuals to be as parent individuals. Thus, it may suffice to have a small population and a small number of generations to target the easy to detect faults and then increase both the population size and the number of generations when targeting the more difficult faults.

The next two parameters are the crossover and mutation probabilities. A crossover probability of 1.0 means that two parent individuals are always crossed so that two children individuals are produced from the parents. Mutation is used to introduce added diversity. A population after several generations will be more likely to have individuals that are more fit than those in the initial population. As the more fit individuals may have similarities, mutation can randomly flip certain bits among the individuals to decrease their similarity. However, mutation can also destroy those good patterns already achieved in some individuals. Thus, an appropriate mutation probability is needed to achieve an appropriate balance.

Issues Concerning the Fitness Function

How the fitness values are computed for the individuals in the population is a very important concern, as the search critically relies on the fitness values. An ill-defined fitness metric can mislead the GA to arrive at a suboptimal solution, or even no solution at all. For instance, a population whose individuals’ fitnesses are similar will not allow the selection process to identify more highly fit individuals to act as parents. Furthermore, without a metric, the individuals may become indistinguishable even when they really are distinguishable. For example, if the fitness function is simply a binary function, where an individual’s fitness is equal to one if the target fault is excited and zero otherwise, this will result in many individuals with fitness equal to zero if they do not excite the target fault. It is clear, however, that some individuals may be closer to exciting the target fault than others. However, the aforementioned binary fitness function would prevent the GA from distinguishing those more fit individuals from the less fit ones.

At the start of the ATPG process, there may exist many easy-to-detect faults; therefore, it may be advantageous to first detect them before targeting the harder faults. In this regard, dividing the ATPG process into different phases would be desirable. As an example, CONTEST [Agrawal 1989] targets test generation in three phases, each having its own distinct fitness measure.

A two-stage ATPG process is described here. In the first stage, the aim is to detect as many faults as possible. The fitness function could simply be the number of faults detected. This fitness metric allows the GA to bias toward those vectors that could potentially detect more faults. One can refine this fitness function to become:

Fitness = ×detected+×excited

In this case, individuals that detect the same number of faults may be distinguished.

Initially, when there are still many easy faults undetected, many individuals will have high fitness values. As vectors are added to the test set and detected faults removed from the fault list, the average fitness of individuals will be expected to come down. When this occurs, it will become increasingly difficult for the GA to distinguish good individuals from the less fit individuals, as discussed earlier. Consequently, the ATPG enters the second stage, where the goal is targeting individual faults instead.

In the second stage, each GA process targets a specific fault. Thus, the fitness function should also be adjusted similarly for this purpose. The fitness ought to measure how close the individual is to exciting the fault, as well as how close it is to propagating the fault-effect to a primary output. For measuring how close the individual is to exciting the fault, one can check the number of necessary value assignments. For instance, suppose the target fault is h/0 at the output of AND gate h, as illustrated in Figure 4.40. Then, an individual that sets both inputs of h to logic 0 (Case 2 in the figure) is further away from exciting the fault than another individual that sets one input to logic 1 (Case 1 in the figure). For measuring how close the individual propagates a fault effect to a primary output, the fitness can measure the number of D or D present in the circuit generated by the individual, together with the observability value associated with the lines to which the DD has propagated.

For sequential circuits, it may be appropriate to have a stage zero where the goal is to initialize all the flip-flops. The fitness of an individual is then simply the number of additional flip-flops set to logic zero or logic one, as done in [Rudnick 1994a] [Rudnick 1994b]. Note that only logic simulation is needed in this stage. For subsequent stages, the fitness function may take into account the fault-effects that propagate to flip-flops as well, as it may take several time frames in order to propagate the fault-effect to a primary output.

As calculating the fitnesses of individuals dominates the computational cost of the GA, care must be taken when designing the fitness functions. Data structures that allow for fast access to the fault-free and faulty values in the circuit, for instance, would be desired. When fitness value calculation becomes prohibitive, one may reduce the cost by estimating the fitness instead of computing the exact fitness. In stage one, for example, fault samples may be used instead of simulating all faults. Also, counting the number of events in logic simulation may be used to estimate the number of faults excited; this may eliminate the high cost of fault simulation. When using such fitness estimates, one must be aware of the potential loss in the quality of the derived solution and that the final fault coverage may also be reduced.

Greedy Channel Router

http://www.cs.uky.edu/~lewis/cs-heuristic/text/local/greedy.html

http://dl.acm.org/citation.cfm?id=809239

http://pages.cs.wisc.edu/~tvrdik/7/html/Section7.html

http://www.engr.uconn.edu/~tehrani/teaching/cad/

Greedy channel scanning

R.L. Rivest and C.M. Fiduccia “ A Greedy Channel Router”, 19th DAC, 1982? P418-424

Greedy channel routers divide the channel into horizontal tracks and vertical columns. This approach works on one vertical column at a time, scanning from left to right.? The approach is termed “greedy” because each column is optimized individually,? although the entire channel is not guaranteed to be optimal. The greedy router sweeps from column to column, trying to join segments of nets assigned to multiple tracks. The greedy channel scan is capable of providing fast solutions but cannot be easily extended to handle arbitrary obstacles.

===================================

Greedy Channel Router

? The channel routers discussed in the earlier sections route the channel one track at a time.
? A heuristic for channel routing known as the ‘greedy channel router’ routes the channel column by column.
? In each column the router applies a sequence of greedy but intelligent heuristics to maximize the number of tracks available in the next column.
? It does not use horizontal or vertical constraints. All decisions are made locally at the column.
? The algorithm handles routing problems even with cycles in the VCG.
? Routing is always completed, sometimes with additional columns at the end of the channel called spillover.
? Unlike other channel routers, in this technique a net can occupy two different tracks until the heuristic decides to merge them.
? Also, instead of doglegging only at terminal locations, the greedy router allows any horizontal connection to change tracks.

Definitions

? Initial-channel-width
? Minimum-jog-length
? Steady-net-constant
? Rising, falling, and steady nets
? Split net and collapsible net
? Spillover area

Greedy Channel Router .....
? The greedy router takes as input the specific channel routing problem and three non-negative integers, initial-channel-width, minimum-joglength, and steady-net constant.
? The router scans the channel column-by-column from left to right.
? It uses six steps in routing each column.
? The wiring at a given column is completed before proceeding to the next. We will now explain the general idea and the various steps involved.

Steps of Greedy Channel Router
? Step 1: Make feasible top and bottom connections in minimal manner.
? Step 2: Free up as many tracks as possible by collapsing split nets.
? Step 3: Add jogs to reduce the range of split nets.
? Step 4: Add jogs to raise rising nets and lower falling nets.
? Step 5: Widen channel if needed to make previously infeasible top or bottom connections.
? Step 6: Extend to next column.

===================================

Greedy algorithm

Rivest and Fiduccia

BHATIA, DINESH and SHANKAR, V.: Greedy Segmented Channel Router p11 VLSI DESIGN 1996, Vol. 5, No. 1, pp. 11-21

Ho, Tai-Tsung , Iyengar, S . Sitharama , Senior Member, IEEE, and Zheng, Si-Qing, Member, IEEE: A General Greedy Channel Routing Algorithm, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. IO, NO. 2, FEBRUARY 1991. p204-212

Rivest, Rouald L. and Fiduccia, Charles M. : A "GREEDY" CHANNEL ROUTER ', March 1981

Yuen, Chi-kan.; 袁志勤: A double-track greedy algorithm for VLSI channel routing Master Thesis, 1997, p114

==========================================

greedy channel scanning multilayer router called NEMO

Heuristics

Deterministic, stochastic

(General) Adaptive Heuristics

Classical Heuristics

Constructive Heuristic Techniques

General Heuristics

Greedy Heuristics

Meta-Heuristic Algorithms

Ant Colony, Ant colony meta-heuristics, Ant colony optimization

  • Tabu Search, Tabu search meta-heuristics
  • Particle Swarm
  • Simulated Annealing
  • Evolution algorithms

agnarsson, Ragnar M: Meta-Heuristics in Multi-core Environments 2010 p49

Sequence Heuristics

Special Heuristics

The Nearest Neighbor heuristic

============================================

Classical Purtubation Methods

Cluster Growth

Hill climbing

Search Hill Climbing

Probablistic Hill Climbing

Hill descending

WALKSAT

Hasle, Geir: Discrete Optimization - Heuristics January 11.-16. 2009 p239 ............ 29

LU, GUANGFA: SEQUENTIAL / PARALLEL HEURISTIC ALGORITHMS FOR VLSI STANDARD CELL PLACEMENT Master Thesis, August 2004 p179

Moore, Andrew W. : Iterative Improvement - Search Hill Climbing, Simulated Annealing, WALKSAT, and Genetic Algorithms, March 2004, slide, p14

Porumbel, Daniel Cosmin: Heuristic Algorithms And Learning Techniques: Applications to the Graph Coloring Problem, PhD Thesis Draft July 2010 p131

Hierachical algorithms

Hierarchical

hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search

Hierarchical Routing Framework

The hierarchical approach recursively divides a routing region into a set of subregions and solve those
subproblems independently.
Drawbacks: lack the global information for the interaction among subregions.

Hierarchical Routing Revisited
? Global routing can be formulated as a linear assignment problem:
? xi,j = 1 if net i is assigned to section j; xi,j = 0 otherwise.
? Each net crosses the cut line exactly once:
? Capacity constraint of each section:
? wij: cost of assigning net i to section j. Minimize

Burstein, Michael: HIERARCHICAL CHANNEL ROUTER 1983 IEEE p7

Dragos, Sanda and Collier, Martin: Macro-routing a new hierarchical routing protocol Oct 2004 p5

OLUKOTUN, 0. A. AND MUDGE, T. N.: Hierarchical Gate-Array Routing on a Hypercube Multiprocessor p12 JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 8,3 13-324 ( 1990)

Parekh, Abhay: Hierarchical Routing October 16, 2002 p48 ........................

Integer and linear programming

Linear Programming / Quadratic Programming / Integer Programming / Mixed Integer Programming / Mixed Integer Linear Programming

Linear Integer Programming

Linear Integer Programming

Mixed Integer Programs –MIP

Pure Integer Programs –IP, PIP

0-1 programs

Quadratic Programming

Binary Integer Programming (BIP)

Integer programs are LPs (Linear programming)where some variables are integers

Linear Programming Problems

A linear programming problem is made up of an objective function and a system of constraints. The objective function is an algebraic expression in two or more variables describing a quantity that must be maximized or minimized. It has the form z = Ax + By The system of constraints are made up of a system of linear inequalities. In applications, the variables are also limited to positive values. The solution to the linear programming problem, if it exists, will occur at the vertices (corner points) of the solution region obtained from the system of constraints.

Literature

Bixby, Robert E.: A Brief History of Linear and Mixed-Integer Programming Computation, 2010

Cornuejols, Gerard et al: A Tutorial on Integer Programming, 1995

Dantzig, George B. and Thapa, Mukund N.: Linear programming vol 1 Introduction, Springer, 1997, p474 ........25

Dantzig, George B. and Thapa, Mukund N.: Linear programming vol 2 Theory and Extensions, Springer, 2003, p475

Eisner Solvers for Mixed Integer Programming p61.ppt

Fergusson, Thomas S.: LINEAR PROGRAMMING - A Concise Introduction p66

Gentry, Sommer: Integer Programming and Branch and Bound, November 24th, 2003

Kostoglou, Vassilis: Linear programming p104.

Krumke, Sven O.: Integer Programming - Polyhedra and Algorithms, January 4, 2006, p180

Lewis, Catherine: Linear Programming: Theory and Applications, May 11, 2008, p66

MODULEB LINEAR PROGRAMMING, June 2005, p32

Nollenburg, Martin: Integer-Programming Methods in Graph Drawing 2007 p72

Richards, Arthur: Mixed-integer Programming for Control, 2005 American Control Conference, June 8-10, 2005. Portland, OR, USA

Vanderbei, Robert J.: Linear Programming: Foundations and Extensions, 2001, p466 .................. 118

Iterative improvement

Memetic Algorithms

Memetic Algorithms 1988

Memetic algorithms (MAs) are optimization techniques based on the synergistic combination of ideas taken from other metaheuristics, such as populational search (as in evolutionary techniques), and local search (as in gradient-ascent techniques).

Memetic algorithms is an improvisation over genetic algorithms and combines global and local search by using evolutionary algorithms to perform exploration while the local search methods are used for exploitation. Here, exploitation is the process of visiting entirely new regions of a search space where the gain can be high.

The generic denomination of `Memetic Algorithms' (MAs) is used to encompass a broad class of metaheuristics (i.e. general purpose methods aimed to guide an underlying heuristic). The method is based on a population of agents and proved to be of practical success in a variety of problem domains and in particular for the approximate solution of NP Optimization problems.

The combination of EAs (Evolutionary Algorithm) with local search (LS) was named memetic algorithms (MAs).

MAs have also been named hybrid genetic algorithms (GAs), genetic local searches, Lamarkian GAs, and Baldwinian GAs.

Metaheuristics --> { Memetic Algorithms (MAs) [also named Hybrid Evolutionary Algorithms (HEA), or hybrid genetic algorithms (HGAs), or Lamarkian GAs (LGA) , or Baldwinian GAs (BGA) or genetic local searches (GLS) ] = { EAs (Evolutionary Algorithm) + local search (LS) } or { Traditional Genetic
Algorithms (GAs) + Simulated Annealing (SA) }

Evolutionary Algorithm is a kind of Evolutionary Computation (EC) methods.

========================================

Memetic Algorithm (MA)

The memetic algorithm is a combination of an Evolutionary Algorithm (EA) and Local Search (LS). The EA are used for finding the global optimum. The LS used here will aid the EA to convergence speed. The evolutionary algorithm used in this work is genetic algorithm. There are two type of memetic algorithm.

Exhaustive MA: Few solutions are selected from the final generation and improved using local search.

Intermediate MA: After a predetermined number of iteration by GA, local search is applied to few random individual. This is done to have a better solution than the local maxima. This work deals with intermediate memetic algorithm.

Consider the graph G = (V,E) with vertex |v|= u and in integer 1<k< n/4. Initialize a randomly generated population P of k elements. Population P has 1 to k elements. Assume each parent p1 to pk belong to the population P. Perform two point crossover for pa and pb from population P using the fitness function (f) =k.M(p)/n , where M(p) is the number of node of partition with maximum cardinality among n partitions. Assume Pa(I) and Pb(I) are the children from pa and pb respectively. If Pa(I) has not satisfied the fitness (Pa(I) is not in I) then choose pa randomly from j >i .Swap Pa(i) and Pa(j). Copy the first element k elements of pa in q1,q3..If Pb(I) has not satisfied the fitness (Pb(I) is not in I) then choose pb randomly from h >k .Swap Pb(h) and Pb(i).Copy the first element k elements of pb in q2,q4..Create two vectors L , L’ with 2(n-k) elements. If (jmod 2 =1) then L(i)= Pa[k+(j+1)/2] and L’(i)= Pb[k+(j+1)/2],else L(j)=Pa[k+(j+1)/2] and L’(j)= Pb[k+(j+1)/2]. Check the fitness of L(i),L’(i), L(j) and L’(j).If L(i) is not in q1, then copy L’(i) in q1 and L(i) in q2. If L(j) is not in q3, then copy L’(j) in q3 and L(j) in q4. Repeat the process again with L(i)and L(j) , L’(i) and L’(j) to get new offspring. The new offsprings can have more fitness value or less fitness value depending upon the parents. Less fitness offspring can be discarded then to reduce the number of cycles.

The fitness of the individual in partitioning is based on the delay of the module. The fitness of the individual is given by weighted evaluations of maximum delay (D). Da identifies a particular sub graph, Dm is a pre-determined maximum value, and Df is the weighting factor. The sum of the weighting factors equals one. The complete fitness function is Gp = {Da/Dm> 1, Da/Dm (1) Da/Dm ≤ 1 , Da/Dm * Df }

Assuming an individual is fully feasible and meets constraints, the value of Gp <= 1, with smaller values being better.

At the beginning, a set of Polish Expressions is given for floorplanning. It is denoted as P, randomly generated expression to compose a population. The fitness for floorplanning of the individual is based on the area of the module. Area of a block can be calculated by the general formula A=LW, where L stands for length of the module and W stands for width of the module. Total Area = Σ An (2)

The fitness of the individual is given by weighted evaluations of maximum area (A). Aa identifies a particular sub graph, Am is a pre-determined maximum value, and Af is the weighting factor. The sum of the weighting factors equals one. The complete fitness function is Gf = {Aa/Am > 1, Aa/Am (3) Aa/Am ≤ 1 , Aa/Am * Af }

Literature

Bunglowala, Aaquil and Singhi, B. M. A : Solution to combinatorial Optimization Problem using Memetic Algorithms p4, International Journal Of Computer Science And Applications Vol. 1, No. 3, December 2008

Feng, Liang et al: Towards Probabilistic Memetic Algorithm: An Initial Study on Capacitated Arc Routing Problem p7, April 2010........................

Krasnogor Memetic Algorithms p125.ppt .............................. 48

Merz Memetic Algorithms for Combinatorial Optimization Problems Fitness Landscapes and Effective Search Strategies p221.pdf

Moscato, Pablo and Cotta, Carlos: A Gentle Introduction to Memetic Algorithms, 2000, p36.............

Moscato, Pablo and Cotta, Carlos: An Introduction to Memetic Algorithms (Spanish), 2003, p18.

Memetic channel routing

Multi commodity network flow
SRIVASTAV, ANAND: DERANDOMIZATION IN COMBINATORIAL OPTIMIZATION, Kluwer Academic Publishers, 2013 p135.................10

Multilevel framework

Multilevel Framework 2001

Framework for Multilevel Routing Considering Routability and Performance

The two-stage multilevel framework consists of coarsening followed by uncoarsening. Global routing, detailed routing, and resource estimation are integrated at each level of the framework, leading to more accurate routing resource estimation during coarsening and thus facilitating the solution refinement during uncoarsening. Further, the exact routing information obtained at each level makes the framework more flexible in dealing with various routing objectives (such as crosstalk, power, etc).

Multilevel Full-Chip Routing for the X-Based Architecture

the X-architecture’s pervasive uses of diagonal routing can reduce wirelength and via count.

the X-initiative

The multilevel framework

general X-Steiner tree (XST) algorithm based on the delaunay triangulation approach for the X-architecture

Ho, Tsung-Yi et al: A Fast Crosstalk and Performance-Driven Multilevel Routing System p6 2003

Ho, Tsung-Yi et al: Multilevel Full-Chip Routing for the X-Based Architecture, June 13–17, 2005, p6

Lin, Shih-Ping and Chang, Yao-Wen: A Novel Framework for Multilevel Routing Considering Routability and Performance 2001, p7

Multilevel Full-Chip Routing Framework

Lin and Chang, “A novel framework for multilevel routing considering routability and performance,” ICCAD-2002 (TCAD, 2003).

Multiplication algorithms

Network coding
NEMADE, NIKHIL PANDIT: APPLICATION OF NETWORK CODING FOR VERY-LARGE-SCALE INTEGRATION (VLSI) ROUTING Master Thesis May 2008 p67.,,,,,,,,,,,,,,,

Network flow

Neural networks

Alti, Priya and Bhaumik, Basabi: NEURAL GLOBAL ROUTER p6 1997 ..................ok

Islam, Taj-ul: CHANNEL ROUTING: EFFICIENT SOLUTIONS USING NEURAL NETWORKS, August 1993, p128 ..........................49

Suzuki, Kyotaro et al: Neural network parallel computing for multilayer channel routing problems 1995 p16..................

nonlinear problem

crisp nonlinear problem

nonlinear programming problem

Nonlinear least squares methods

Ordered binary decision diagram

PARTICLE SWARM
PARTICLE SWARM OPTIMIZATION

PARTICLE SWARM OPTIMIZATION 1995

The particle swarm optimization (PSO) is an optimization technique inspired by swarm intelligence and theory in general such as bird flocking, fish schooling and even human social behavior. PSO is a population-based evolutionary algorithm in which the algorithm is initialized with a population of random solutions. However, unlike most of other population-based evolutionary algorithms, PSO is motivated by the simulation of social behavior instead of the survival of the fitness. The advantages of PSO over many other optimization algorithms are its simplicity in implementation and its ability to converge to a reasonably good solution quickly. Since the PSO algorithm was proposed, it has aroused great interest among the academic community, massive research results have been presented in only a few years. Hence particle swarm optimization technique will be made use to find the optimal solution for the floorplanning.

POWER DISSIPATION IN VLSI WIRE ROUTING USING PARTICLE SWARM OPTIMIZATION TECHNIQUE

Minimization of Floorplanning Area and Wire Length Interconnection Using Particle Swarm Optimization

Sowmya, B , MP, Sunil: Minimization of Floorplanning Area and Wire Length Interconnection Using Particle Swarm Optimization, August 2013, p10...................4

TEP, ALIFF BIN MOHD: POWER DISSIPATION IN VLSI WIRE ROUTING USING PARTICLE SWARM OPTIMIZATION TECHNIQUE, 7 December 2010, p196...................

Polyhedral techniques

probability_physical_partitioning

Quadratic programming

Spindler, Peter: Efficient Quadratic Placement of VLSI Circuits PhD Thesis, 20.12.2007 p137...........................

Reduce & Conquer (R&C)

[e.g., multilevel techniques such as the hMetis partitioner]

Reed-Muller

Reed-Muller (RM) forms

Dual Forms of Reed-Muller (DFRM)

SAT based routing

SAT Algorithm

SAT Algorithm based on reduced Ordered Binary Decision Diagram

Velev, Miroslav N.and Gao, Ping: Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems, 978-3-9810801-3-1/DATE08 ? 2008 EDAA

Search Methods

click to learn more ...

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Simulated annealing

click to learn more ...

statistical design optimization

statistical_methods_design

Submodular functions and matroids

Switching function

And other iterative algorithms and combinatorial optimization techniques for VLSI design.

Other Optimization and Combinatorial Techniques


Complex analysis

ANALYSIS COMPLEX

<DIR> en

Agarwal An Introduction to Complex Analysis p346

AlderYYY An Introduction to Complex Analysis forEngineerp178.pdf

AnaetschevaZZZ complex function RUSS p204.pdf

Beck Complex Analysis p159

Beck A First Course in Complex Analysis p127

Bennewitz COMPLEX ANALYSIS p116

Berg Complex Analysis p192

Berg, Christian: Complex Analysis p192, 2010

DangeloZZZ An Introduction to Complex Analysis and Geometry p169.pdf

KuttlerYYY Complex Analysis Summer 2001 p157.pdf

Li Complex Analysis p91

magazinikovZZZ complex functions RUSS p206.pdf

Marsden Basic Complex Analysis p519

Mathews Complex Analysis for Mathematics and Engineering p528

McMullen Complex Analysis p106

Sawyer Lecture Notes in Complex Analysis p121

Schlag A concise course in complex analysis and Riemann surfaces p181

Schlag A concise course in complex analysis and Riemann surfaces p207

Stein, Elias M. and Shakarchi, Rami: Complex Analysis, PRINCETON UNIVERSITY PRESS, October 20, 2007, p398 ........................ 25

Stein COMPLEX ANALYSIS p398

Sternberg Theory of functions of a real variable p393

Taylor, Michael: Introduction to Complex Analysis, May 2011, p243 ............... 7

Teschl Topics in Real and Functional Analysis p177

Wedhorn Complex Analysis p71

Wiegerinck Advanced Function Theory p154

<DIR> de

000Cooper analysis iii p62.pdf
Balser Funktionentheorie-Master p80.pdf
Biran funktionentheorie p127.pdf
Mueller Grundlagen der angewandte Analysis p257.pdf
Nickelsen Komplexitatstheorie-08-feb p76.pdf

<DIR> fr

ANALYSE COMPLEXE ET HARMONIQUE p108ZZZ.pdf
AudinZZZ ANALYSE COMPLEXE p148.pdf
BahouriZZZ analyse_complexe p156.pdf
BergYYY Complex Analysis p192.pdf
CharpentierZZZ Analyse_Complexe p113.pdf
CharpentierZZZ Introduction à Lanalyse Complexe p60.pdf
COLMEZZZZ éLéMENTS DANALYSE ET DALGèBRE p422.pdf
GirouxZZZ Analyse complexe p93.pdf
GolseXXX Analyse reelle et complexe p244.pdf
HairerZZZ Analyse Complexe p125.pdf
Kummer Mémoire sur la théorie des nombres complexes composés de p123.pdf
KUMMERZZZ Mémoire sur la théorie des nombres complexes composés p123.pdf
Laurent-ThiébautZZZ Fonctions holomorphes p94.pdf
NICOLASZZZ Analyse complexe et analyse spectrale p95.pdf
Paris-DauphineXXX Analyse Complexe p77.pdf
PlautZZZ Analyse complexe p74.pdf
SchneidersZZZ Fonctions de Variables Complexes p104.pdf
Series entieres - Proprietes des fonctions analytiques p52ZZZ.pdf
TenenbaumZZZ Analyse complexe p126.pdf
trepreau1ZZZ ANALYSE COMPLEXE p67.pdf
VALIRONZZZ Fonctions de variable complexe p272.pdf
YgerZZZ Analyse Complexe p183.pdfANALYSE COMPLEXE ET HARMONIQUE p108ZZZ.pdf
AudinZZZ ANALYSE COMPLEXE p148.pdf
BahouriZZZ analyse_complexe p156.pdf
BergYYY Complex Analysis p192.pdf
CharpentierZZZ Analyse_Complexe p113.pdf
CharpentierZZZ Introduction à Lanalyse Complexe p60.pdf
COLMEZZZZ éLéMENTS DANALYSE ET DALGèBRE p422.pdf
GirouxZZZ Analyse complexe p93.pdf
GolseXXX Analyse reelle et complexe p244.pdf
HairerZZZ Analyse Complexe p125.pdf
Kummer Mémoire sur la théorie des nombres complexes composés de p123.pdf
KUMMERZZZ Mémoire sur la théorie des nombres complexes composés p123.pdf
Laurent-ThiébautZZZ Fonctions holomorphes p94.pdf
NICOLASZZZ Analyse complexe et analyse spectrale p95.pdf
Paris-DauphineXXX Analyse Complexe p77.pdf
PlautZZZ Analyse complexe p74.pdf
SchneidersZZZ Fonctions de Variables Complexes p104.pdf
Series entieres - Proprietes des fonctions analytiques p52ZZZ.pdf
TenenbaumZZZ Analyse complexe p126.pdf
trepreau1ZZZ ANALYSE COMPLEXE p67.pdf
VALIRONZZZ Fonctions de variable complexe p272.pdf
YgerZZZ Analyse Complexe p183.pdf

<DIR> gk

Analysis Greek grfa p129ZZZ.pdf
Analysis greek p210ZZZ.pdf
MetaptuqiakZZZ? Anlush II Chapter1 Greek p45.pdf
ΕΚΔΟΣΗZZZ ΜΑΘΗΜΑΤΙΚΩΝ p475.pdf
Μ?τση?ZZZ Σημει?σΑν?λυση? p69.pdf
Σουρλ?? ZZZMigadiki.Analysi p160.pdf
Σουρλ??ZZZ Megasiki Analysis GREEK p173.pdf

<DIR> ru

AnaetschevaZZZ complex function RUSS p204.pdf
BugajevaZZZ complex functions p90.pdf
BuschuevaZZZ complex functions RUSS u_lectures p110.pdf
complexZZZ functions RUSSIAN p92.pdf
complexZZZ functions RUSS p80.pdf
magazinikovZZZ complex functions RUSS p206.pdf
sidorovZZZ analytiscal functions RUSS p68.pdf
Айерлэнд Классическоеp416.pdf
БорисоваZZZ ТЕОРИЯ ФУНКЦИЙ p85.pdf
ЗахаровZZZ комплексного переменного p39.pdf
ИВАНОВZZZ КОМПЛЕКСНАЯ ПЛОСКОСТЬ p180.PDF
ИВАНОВZZZ КРИВЫЕ И ОБЛАСТИ НА КОМПЛ p159.PDF
КАРАСЁВZZZ ТЕОРИЯ ФУНКЦИЙ p200.pdf
ЛаврентьевZZZ МЕТОДЫ p750.pdf
ЛьвовскийZZZ Лекции p136.pdf
НАХМАНZZZ КОМПЛЕКСНОГО ПЕРЕМЕННОГО p105.pdf
СвешниковZZZ Теория функцийp321.pdf
ТитчмаршZZZ Теория функций p468.pdf
ШабатZZZ Введение анализ p577.pdf


Complexity theory

Arora Computational Complexity Modern Approach p489

Arora Computational Complexity: A Modern Approach p489
Draft of a book: Dated January 2007
Comments welcome!
Sanjeev Arora and Boaz Barak
Princeton University
complexitybook@gmail.com

Blakey, Ed: A Model-Independent Theory of Computational Complexity: From Patience to Precision and Beyond , 2010???????? 37

BlaserYYY Computational Complexity Theoryp119.pdf

Cai Lectures in Computational Complexity p169

Gacs Complexity of Algorithms p242

HastadYYY Complexity Theory p130.pdf

ParberryYYY Lecture notes complexity theory p119.pdf

Parberry Parallel Complexity Theory p212

Talbot Complexity and Cryptography An Introduction p305

TheoryofComputationlectp139

Trevisan, Luca: Lecture Notes on Computational Complexity, May 2004, p171 ...................... 46

ZimandYYY exitential p156.pdf


Cryptography

quantum cryptography

http://think.univie.ac.at/index.php?id=137232

http://www.bristol.ac.uk/physics/research/quantum/research/cryptography/

http://www.qi.damtp.cam.ac.uk/node/38

http://wcms.inf.ed.ac.uk/lfcs/graduate%20study/quantum-cryptography

http://www.postgraduate.hw.ac.uk/prog/109/

http://www.doc.ic.ac.uk/~nd/surprise_97/journal/vol1/mjc5/

http://ece.arizona.edu/tags/quantum-cryptography

http://pure.au.dk/portal/en/publications/quantum-cryptography-in-integrated-circuits-with-bragg-gratings%289fd1f4ac-7f97-4450-955f-f9eb6cc7ba58%29.html

www.quantumcryptography.blogspot.com/?

http://www.theory.caltech.edu/people/preskill/colloquium/Quantum_Cryptography.html

http://www.encryptsolutions.com/2011/08/15/attack-on-quantum-cryptography/

http://code.google.com/p/qcrypto/

http://research.physics.illinois.edu/QI/Photonics/crypto.html

http://www.infosecurity-magazine.com/view/27477/quantum-cryptography-is-not-provably-secure/

http://people.isy.liu.se/jalar/qkg/ceniit.html

http://www.magiqtech.com/MagiQ/Home.html

http://www.cs.mcgill.ca/~crepeau/CRYPTO/Biblio-QC.html
http://crypto.cs.mcgill.ca/~crepeau/COMP649/

http://www.nanotech-now.com/news.cgi?story_id=45724

http://www.princeton.edu/~achaney/tmve/wiki100k/docs/Quantum_cryptography.html

http://2013.qcrypt.net/

http://www.quantenkryptographie.at/

http://www.quantiki.org/wiki/Quantum_cryptography

http://vcq.quantum.at/

http://www.quantumlah.org/research/topic/qcrypto/

http://www.qubit.org/tutorials.html

https://www.schneier.com/cgi-bin/mt/mt-search.cgi?tag=quantum%20cryptography

http://www.secoqc.net/

http://news.stanford.edu/news/2012/november/toward-quantum-cryptography-111512.html

http://www.toshiba.eu/eu/Cambridge-Research-Laboratory/Quantum-Information-Group/Quantum-Key-Distribution/

http://www.informatik.uni-trier.de/~ley/db/series/natosec/natosec26.html

http://www.gap-optique.unige.ch/wiki/research:quantum_cryptography

http://www.parabola.unsw.edu.au/vol42_no3/node2.html

http://www.uqcc.org/

https://courses.cs.ut.ee/all/MTAT.07.024/2012_fall/uploads/

http://cqiqc.physics.utoronto.ca/highlights/quantum-cryptography-light-fantastic.html

http://en.wikipedia.org/wiki/Quantum_cryptography

http://www.cse.wustl.edu/~jain/cse571-07/ballots.htm

http://www.cs.xu.edu/~kinne/quantum/crypt.html

Post quantum cryptography

The four possible replacement methods include:

http://u.cs.biu.ac.il/~tsaban/CGCColloq.html

http://pq.crypto.tw/pqc11/index.shtml

http://cryptojedi.org/papers/

https://cryptoworks21.ca/training/modules/4/

http://hassanansari.com/post-quantum-cryptography/

http://www.maa.org/publications/maa-reviews/post-quantum-cryptography

http://toc.csail.mit.edu/?q=node/175

http://postquantum.cr.yp.to/

http://pqcrypto.org/

http://quantumfrontiers.com/2013/03/17/post-quantum-cryptography/

https://www.securityinnovation.com/products/encryption-libraries/ntru-cryptography.html

http://www.stevens.edu/algebraic/SCPQ/

https://www.cdc.informatik.tu-darmstadt.de/en/cdc/research/post-quantum-cryptography/

http://icis.cpsc.ucalgary.ca/node/738

http://cseweb.ucsd.edu/~daniele/papers/PostQuantum.html

http://jqi.umd.edu/workshops/2010-quantum-information/abstract/post-quantum-cryptography-introduction-and-trends

http://www.informatik.uni-trier.de/~ley/db/conf/pqcrypto/index.html

http://pqcrypto2014.uwaterloo.ca/

http://en.wikipedia.org/wiki/Post-quantum_cryptography

http://pqcrypto2013.xlim.fr/

<DIR> en

Abadi Reconciling Two Views of Cryptography p34.pdf
AlbaniZZZ Information Security Guideline 2011 p128.pdf

Adida Advances in Cryptographic Voting Systems p254

Albuquerque FromLieAlgebrasToQuantumGroups p214.pdf
AnantharamZZZ Recent progress in multiuser information theory with correlated sources p128.pdf
Anderson_Security_Engineering p1082.pdf
ApplebaumZZZ Rabins trapdoor permutation Goldwasser-Micali Cryptosystem and Primality Testing p35.pdf
Arora Computational Complexity A Modern Approach p26.pdf
Attrapadung A Survey on Recent Advances in Broadcast Encryption p138.pdf
Attrapadung Broadcast Encryption p155.pdf

Attrapadung A Survey on Recent Advances in Broadcast Encryption p138

Attrapadung Broadcast Encryption p155

Attribute-Based Cryptography p114

Barker Guideline for Implementing Cryptography In the Federal Government p97.pdf
Batuwantudawe New Techniques for Security Proofs of Quantum Cryptography p122.pdf

Batuwantudawe New Techniques for Security Proofs of Quantum Cryptography p122

Bellare Introduction to Modern Cryptography p283.pdf
BellareYYY Introduction to Modern Cryptography p283.pdf
BellareZZZ Introduction to Modern Cryptography p283.pdf

BellareRogaway Introduction to Modern Cryptography p283

Bernstein Post Quantum Cryptography p248???????????????? 31

Bernstein Post Quantum Cryptography p248

Bernstein, Daniel J. ·Buchmann, Johannes and Dahmen, Erik: Post-Quantum Cryptography, Springer-Verlag Berlin Heidelberg, 2009 ................ 13

Beuchat An Introduction to Pairing-Based Cryptography p440

Blake Advances in Elliptic Curve Cryptography p299

bok_978-3-642-15031-9.pdf
Bowden Cryptography and Democracy Dilemmas of Freedom p40.pdf

Bregman Public Keys and Private Keys in Quantum Cryptography p112

Broadcast Encryption and Some Other Primitives p113

Brown Elliptic Curve Cryptography p144

Brydon On the Security of Leakage Resilient Public Key Cryptography p100

Byrne Mathematics of Signal Processing A First Course p410.pdf
Cameron Notes on cryptography p132.pdf
CameronYYY Notes on cryptography p132.pdf
Carlet Boolean Functions for Cryptography and Error Correcting Codes p148.pdf

Carlet Boolean Functions for Cryptography and Error Correcting Codes p148

ch02 Mathematics of Cryptography p36.pdf
ch10-crypto p60.pdf

Chen New Techniques for Cryptanalysis of Cryptographic Hash Functions p213

Cohen, Henri and Frey, Gerhard: Handbook of Elliptic and Hyperelliptic Curve Cryptography, 2006, Chapman & Hall/CRC, p843 ?????????? 81

craig A FULLY HOMOMORPHIC ENCRYPTION SCHEME p209

craig A FULLY HOMOMORPHIC ENCRYPTION SCHEME p209.pdf
cryptography.pdf
DasZZZ Chapter4The Intractable Mathematical Problems p250.pdf
DASZZZ Introduction to Cryptography p664.pdf
DAVID Lightweight Cryptography for Passive RFID Tags p148.pdf

DAVID Lightweight Cryptography for Passive RFID Tags p148

Davis Cryptography p14.pdf
Debdeep Desig of cellular automata encryption p259.pdf
DelfsKneblZZZ Introduction to Cryptography - Principles and Applications p372.pdf

Debdeep Desig of cellular automata encryption p259

DenisZZZ Cryptography for Developers (2007) p450.pdf

Denning-CryptographyDataSecurity p419

diffie.hellman New Directions in Cryptography p12.pdf
DigitalZZZ Signature Standard (DSS) p130.pdf
Doc CRYPTOGRAPHY p172.pdf
DocYYYZ CRYPTOGRAPHY p172.pdf

Doumen Some Applications of Coding Theory in Cryptography p88

Fisher Coding and Cryptography p61

Fuller Analysis of affine equivalent boolea functions to encryption p167.pdf

Funder Cryptography_with_Quantum_Mechanics p103.pdf?????????? 17

GUNEYSU CRYPTOGRAPHY AND CRYPTANALYSIS ON RECONFIGURABLE DEVICES p213

GasserZZZ BUILDING A SECURE COMPUTER SYSTEM p250.pdf
Geers Strategic_Cyber_Security_p169.PDF

Goldreich Modern Cryptography, Probabilistic Proofs and Pseudorandomness p213.pdf
GoldreichYYY Foundations of Cryptography p305.pdf
GoldreichYYY Modern Cryptography, Probabilistic Proofs and Pseudorandomness p213.pdf
GoldwasserYYY Lecture Notes on Cryptography p289.pdf
goldwasserYYY_bellare_Lecture Notes on Cryptography p283.pdf
GoldwasserZZZ Lecture Notes on Cryptography p289.pdf
goldwasser_bellare_Lecture Notes on Cryptography p283.pdf

goldwasser_bellareZZZ_Lecture Notes on Cryptography p283

GoldwasserBellare Lecture Notes on Cryptography p289

Goluch The development of homomorphic cryptography p112

Greveler Applications of Broadcast Encryption for Digital Rights Management of Multimedia Broadcasts p251

Greveler Applications of Broadcast Encryption for Digital Rights Management of Multimedia Broadcasts p251.pdf
GRIGORIEV TROPICAL CRYPTOGRAPHY p9.pdf
Gruska CODING CRYPTOGRAPHY and CRYPTOGRAPHIC PROTOCOLS p1450.pdf

Gruska, Jozef: CODING, CRYPTOGRAPHY and CRYPTOGRAPHIC PROTOCOLS p1450 (slides), December 6, 2011 ??? 82

Gupta Handbook.Of.Research.On.Information.Security.And.Assurance p586.pdf

HankersonMenezesVanstoneZZZ Guide to elliptic curve cryptography p332

Harrington_Network Security A Practical Approach p385.pdf
Helmer Information Security p376.pdf

Hendrych, Martin: Experimental Quantum Cryptography, Doctoral Thesis, September 2002, p104 ????????????? 44
Henry The Theory and Applications of Homomorphic Cryptography p139.pdf

Henry The Theory and Applications of Homomorphic Cryptography p139

Hitchcock, Yvonne Roslyn: Elliptive curve for light weight crypto p247, Dec 2003 ????????? 133

Hoffstein An Introduction to Mathematical Cryptography p530.pdf
HoffsteinYYY An Introduction to Mathematical Cryptography chapt 1and2 p126.pdf
HoffsteinZZZ An Introduction to Mathematical Cryptography p530.pdf
hudde-code-based-cryptography-library p122.pdf

hudde-code-based-cryptography-library p122

Hughes Quantum Cryptography p84

INTRODUCTION TO CRYPTOGRAPHY p16.pdf
JanacekYYY-introduction-to-mathematics-for-computer p153.pdf
Juma Leakage resilience and black-box impossibility results in cryptography p180.pdf

Juma Leakage resilience and black-box impossibility results in cryptography p180

Katz Introduction_to_Modern_Cryptography p512

Katz Introduction_to_Modern_Cryptography p520.pdf
KatzZZZ Introduction_to_Modern_Cryptography p512.pdf
KeshavZZZ Mathematical Foundations of Computer Networking p324.pdf
Kessler An Overview of Cryptography p23.pdf
Khader Attribute Based Authentication Schemes p173.pdf

Khader Attribute Based Authentication Schemes p173

kohel Cryptography p243.pdf
kohelYYY Cryptography p143.pdf

Korner Coding and Cryptography p104

Kranakis Primality and cryptography p225

kupcu Efficient Cryptography for the Next Generation Secure Cloud p275

Lane Machine Learning Techniques for the Computer Security Domain p151.pdf
Leander Lightweight_cryptography p166.pdf
Leander-Lightweight_cryptography p166.pdf

Leander Lightweight_cryptography p166

LeeWang Advances_in_Cryptology_ASIACRYPT_2011 p775

LehmannYYY Mathematics for Computer Science 2004 p339.pdf
LehmannYYY Mathematics for Computer Science 2010 p556.pdf
LehmannYYY Mathematics for Computer Science 2011 p697.pdf
LehmannZZZ Mathematics for Computer Science 2013 p848.pdf
LehmanZXX Mathematics for Computer Science p697.pdf
LehneYYY Privacy in Telecommunications p142.pdf
Lindell Foundations of Cryptography p98.pdf
Lindell Introduction to Cryptography p83.pdf
Lomonaco A Quick Glance at Quantum Cryptography p54.pdf

lorenz Cryptography Based on Error Correcting Codes p94

Lynn thesis ON THE IMPLEMENTATION OF PAIRING-BASED CRYPTOSYSTEMS p126

Lynn thesis ON THE IMPLEMENTATION OF PAIRING-BASED CRYPTOSYSTEMS p126.pdf

Mao ModernCryptographyTheoryandPractice p755

marco The Future of Cryptography Under Quantum Computers p43.pdf

Mathar Cryptography Advanced Methods of Cryptography p124

Maurer Abstract Cryptography p169.pdf
MaurerXXX abstract cryptography p169.pdf
MaurerZZZ Abstract Cryptography p169.pdf
Menezes chap14 Efficient Implementation p45.pdf
Menezes chap8 Public-Key Encryption p38.pdf
MenezesZZZ et al HANDBOOK of APPLIED CRYPTOGRAPHY p794.pdf
MenezesZZZ handbook_of_applied_cryptography p794.pdf

Menezes Handbook Of Applied Cryptography p794

Meskanen On the NTRU Cryptosystem p126

Meskanen On the NTRU Cryptosystem p126.pdf
MeyerZZZ Mathematics for Computer Science 2010 p519.pdf

Mogollon Cryptography.and.Security.Services Mechanisms.and.Applications p489
MollinZZZ An introduction to cryptography p393.pdf

Mollin An INTRODUCTION to CRYPTOGRAPHY p393

Mullan Some results in group-based cryptography p101

Myasnikov Group-based cryptography p47.pdf
NAI An Introduction to Cryptography p86.pdf

nemes Quantum Resistant Cryptography p42

NISTZZZ An Introduction to Computer Security p290.pdf
NISTZZZ ComputerSecurityIncidentHandlingGuide p147.pdf
Number Theory and Cryptography p28.pdf
OppligerZZZ Contemporary Cryptography p469.pdf

Oppliger Contemporary Cryptography p469
orourke Efficient NTRU Implementations p199.pdf
PaarZZZ Past and Future of Cryptographic Engineering p167.pdf
PaarZZZ Understanding Cryptography p382.pdf

Peikert Some Recent Progress in Lattice-Based Cryptography p74

PeltierZZZ Information Security Risk Analysis p343.pdf
PeltierZZZ_Information_Security_Fundamentals p262.pdf
Pelzl PRACTICAL ASPECTS OF CURVE-BASED CRYPTOGRAPHY AND CRYPTANALYSIS p222.pdf
Persichetti Improving the efficiency of Code-Based Cryptography p147.pdf
Persochetti Improving the efficiency of code based encryption p142.pdf

Persochetti Improving the efficiency of code based encryption p142

PistoiaZZZ Java 2 Network Security p684.pdf

Porschman LIGHTWEIGHT CRYPTOGRAPHY, Cryptographic Engineering for a PervasiveWorld, DISSERTATION for the degree Doktor-Ingenieur, February 2009, p197.??????????? 127

Porschman LIGHTWEIGHT CRYPTOGRAPHY p197.pdf
Roe thesis Cryptography and Evidence p74.pdf

Rose LATTICE-BASED CRYPTOGRAPHY A PRACTICAL IMPLEMENTATION p103

Rosenthal Cryptography p91.pdf
RuohonenYYY MATHEMATICAL CRYPTOLOGY p136.pdf
RuohonenZZZ MATHEMATICAL CRYPTOLOGY p147.pdf

Ruohonen MATHEMATICAL CRYPTOLOGY p136

R?dulescu Public-key Cryptography - The RSA and the Rabin Cryptosystems p160

rupp COMPUTATIONAL ASPECTS OF CRYPTOGRAPHY AND CRYPTANALYSIS Schaefer An introduction to cryptography and cryptanalysis p114.pdf
SchaeferYYY An introduction to cryptography and cryptanalysis p114.pdf
SchaeferZZZ An introduction to cryptography and cryptanalysis p114.pdf
Schneier Applied Cryptography p662.pdf
SchneierZZZ Applied Cryptography p662.pdf

Schneier Applied Cryptography p662
SE-05 Cryptography p42.pdf
SeidelXXX Preparing Tomorrows Cryptography Parallel Computation p169.pdf
SeifriedZZZ Linux Administrators Security Guide p152.pdf

Silverman The Arithmetic of Elliptic Curves p522

Silverman An Introduction to the Theory of Lattices and Applications to Cryptography p76

smart-Cryptography An Introduction p432

Stajano Romantic Cryptography p10.pdf
STALLINGSZZZ Cryptography and Network Security Principles and Practice 5th Ed p900.pdf
StallingsZZZ cryptography-network-security-5th-edition p900.pdf
StallingsZZZ cryptography-network-security-5th-edition1 p900.pdf
StallingsZZZ cryptography-network-security-5th-edition2 p900.pdf

Stallings Cryptography and Network Security Principles and Practice 5th Edition p900
SteinYYY Discrete-Mathematics-for-Computer-Scientists3 p526.pdf

Stinson CryptographyTheoryandpractice(3ed) p611

Subramanian_-_Computer_security,_privacy_and_politics p333.pdf
TALBOTZZZ Complexity and Cryptography An Introduction p305.pdf
Tapsen public key cryptography p15.pdf

Tehan White-Box Cryptography p76
TelXXX Cryptography and Beyond p162.pdf
Tettero Intrinsic Information Security p352.pdf
Trappe Introduction_to_Cryptography_with_Coding_Theory-p591.pdf

Trappe, Wade and Washington Lawrence C: Introduction to Cryptography with Coding Theory, Pearson, 2006, p591?..............????????? 414
Trevisan Cryptography Lecture Notes from CS276, Spring 2009 p154.pdf
TrevisanYYY Cryptography Lecture Notes from CS276, Spring 2009 p154.pdf

Umana, Valerie Gauthier: Post-Quantum Cryptography p156.pdf,??PhD Thesis, October 2011 ??????? 32

Vahlis Cryptography Leakage Resilience Black Box Separations and Credential-free Key Exchange p164

Vahlis Cryptography Leakage Resilience Black Box Separations and Credential-free Key Exchange p164.pdf
VARRETTEYYY Introduction `a la cryptographie p128.pdf

Verneuil, Vincent: Cryptographie à base de courbes elliptiques et sécurité de composants embarqués, Elliptic curve cryptography and security of embedded devices, Thèse présentée pour obtenir le grade de Docteur, p200???? le 13 juin 2012 ?????? 83

VinceYYY Mathematics for Computer Graphics 2006 p251.pdf
VinceYYY Mathematics for Computer Graphics 2010 p296.pdf

Washington, LAWRENCE C.: ELLIPTIC CURVES NUMBER THEORY AND CRYPTOGRAPHY, SECOND EDITION, Taylor & Francis Group, 2008 p 524????? 45

Wehner quantum_cryptography-an_introduction p82

Weir Visual cryptography and its applications p144.pdf
West-Brown Handbook for Computer Security Incident Response Teams p223.pdf

WongKenneth_Thesis Cryptology p201

Yang, Bo-Yin: Post -Quantum Cryptography p307, 4th InternationalWorkshop, PQCrypto 2011, Taipei, Taiwan, November 29 – December 2, 2011, Proceedings, Springer????????????????????? 4
Zhang IMPROVEMENTS AND GENERALISATIONS OF SIGNCRYPTION SCHEMES p126.pdf

Zhang IMPROVEMENTS AND GENERALISATIONS OF SIGNCRYPTION SCHEMES p126

<DIR> de

BestZZZ Grundbegriffe der Kryptographie p121.pdf
Haenni Kryptographie in Theorie und Praxis p189.pdf
HaenniYYY Kryptographie in Theorie und Praxis p189.pdf
SchnorrYYY Gitter und Kryptographie 2009 p116.pdf
SchnorrYYY Kryptographie p114.pdf

<DIR> fr

Bagga Cryptographie à Base de Politiques Théorie et Applications p194.pdf
BaggaYYY Cryptographie à Base de Politiques Théorie et Applications p194.pdf
blanc-TECHNIQUES DE CRYPTOGRAPHIE p30.pdf
Bresson Cryptographie p72.pdf
Chabot Introduction a la cryptographie p66.pdf
Préaux Cryptographie p97.pdf
RouchonZZZ CRYPTOGRAPHIE ET THéORIE DES NOMBRES p73.pdf
VARRETTE Introduction `a la cryptographie p128.pdf
Verneuil_Ellipticcurvecryptographyndsec p200.pdf

<DIR> gk

Lec6 kryptografia p24.pdf

<DIR> ru

crypto-present p16.pdf
crypto-text Криптография вчера, сегодня, завтра p9.pdf
Forouzan КРИПТОГРАФИЯ p36.pdf
Kronbberk quantum cryptography p112.pdf
Nikolenko 02-secretkey p75.pdf
Nikolenko 04-publickey2 p41.pdf
Nikolenko 05-lattices p63.pdf
Rabzev КВАНТОВАЯ КРИПТОГРАФИЯ p31.pdf
Saloma kriptografiq s otkrytym klom p320.pdf
SalomaYYY kriptografia s otkrytym klvq Russ p320.pdf
Slauer Прикладная криптографияp122.pdf


Differential Equations

<DIR> en

Chasnov Introduction to Differential Equations p128
31

okokok
McDonald BERNOULLI EQUATIONS p31

Miersemann Partial Differential Equations Lecture Notes p205

Salamon, Simon: Differential Equations and Discrete Mathematics October 1996 p115.......................... 10

Terrell Notes on Differential equations p100

Teschl Ordinary Differential Equations and Dynamical Systems p364

Tracy Lectures on Differential Equations p175

<DIR> de

BaumXYZ Einfuhrung in die Theorie der gewohnlichen Differentialgleichungen p100.pdf
BaumXYZ Gleichung p94.pdf
HoffmannZZZ PARTIELLE DIFFERENTIALGLEICHUNGEN II Variationsmethoden p132.pdf
MichelZZZ gewohnliche Differentialgleichungen p115.pdf
Schweizer, Ben: Partielle Differentialgleichungen, 25. Oktober 2011. p222??????????????? 44

<DIR> fr

<DIR> gk

<DIR> ru


Discrete Mathematics

BabaiZZZ Discrete Mathematics Lecture Notes p178.pdf
BabaiZZZ Discrete Mathematics p96.pdf
BogartZZZ Discrete Math for Computer Science Students p344.pdf
BogartZZZ DISCRETE MATHEMATICS THROUGH GUIDED DISCOVERY p122.pdf

Bogart Discrete Math for Computer Science Students p344

CaldwellZZZ Logic and Discrete Mathematics for Computer Scientists p200.pdf
carolinaZZZ Discrete Mathematics p70.pdf
ChenZZZ Discrete_Mathematics p190.pdf
CormenYYY Introduction to Algorithms p984.pdf
CormenYYY Introduction to Algorithms-2nd-edition p1202.pdf
EppZZZ Discrete_Mathematics_with_Applications p993.pdf

EPP DISCRETE MATHEMATICS WITH APPLICATIONS p993

Finan Lecture Notes in Discrete Mathematics p224

FinanXXX Lecture Notes in Discrete Mathematics p168.pdf
FinanZZZ Lecture Notes in Discrete Mathematics p224.pdf
GallierZZZ Discrete Mathematics for Computer Science Some Notes p256.pdf
HostenZZZ Social Networks and Discrete Mathematics p8.pdf
KerstingZZZ DiskreteMathematik p105.pdf
KrantzZZZ Discrete Mathematics Demystified p369.pdf
LalZZZ Lecture Notes on Discrete Mathematics p111.pdf

Lal Lecture Notes on Discrete Mathematics p188

LermaZZZ Notes on Discrete Mathematics p154.pdf
LichtblauZZZ Differential Evolution in Discrete and Combinatorial Optimization p30.pdf
LovaszZZZ Discrete Mathematics p139.pdf

Lovász Discrete Mathematics:Elementary and Beyond p302

Lovasz Discrete Mathematics p139

ODonnelZZZ Discrete Mathematics Using a Computer p441.pdf

Pass A Course in Discrete Structures p133
12

Rosen Discrete Mathematics and Its Applications p1071

Rosen Discrete.Mathematics.and.Its.Applications 7th ed 2012 p1071.pdf
RosenZZZ discrete mathematics and Its Applications 4th ed 1999 p722.pdf
RosenZZZ Discrete Mathematics and Its Applications, 4th Ed 1999 p700.pdf
santosZZZ-discrete_math_lecture_notes1 p104.pdf
SchnorrZZZ Diskrete Mathematik p143.pdf
SedgewickZZZ Algorithm 44ShortestPaths p68.pdf
SedgewickZZZ Algorithms 4th edition p969.pdf
SedgewickZZZ AlgorithmsFourthEdition p969.pdf
SedgewickZZZ An_introduction_to_the_analysis_of_algorithms p593.pdf
SteinZZZ Discrete-Mathematics-for-Computer-Scientists p526.pdf
TheobaldZZZ Skriptum Diskrete Mathematik p111.pdf
TheobaldZZZ Skriptum Diskrete Mathematik p81.pdf
VeeravaguBarreraZZZ Dijkstras algorithm.ppt
WellsZZZ CLASS NOTES FOR DISCRETE MATHEMATICS p267.pdf

Wells CLASS NOTES FOR DISCRETE MATHEMATICS p267

WinskelZZZ Discrete Mathematics II Set Theory for Computer Science p90.pdf

Bogart Discrete Math for Computer Science Students p344.pdf
EPP DISCRETE MATHEMATICS WITH APPLICATIONS p993.pdf
Finan Lecture Notes in Discrete Mathematics p224.pdf
Lal Lecture Notes on Discrete Mathematics p188.pdf
Lovasz Discrete Mathematics p139.pdf
Lovász Discrete Mathematics Elementary and Beyond p302.pdf
Pass A Course in Discrete Structures p133.pdf
Rosen Discrete Mathematics and Its Applications p1071.pdf
Wells CLASS NOTES FOR DISCRETE MATHEMATICS p267.pdf


ERGODIC THEORY

Camí Ergodic Theory p50
(Lecture Notes)
Joan Andreu Lázaro Camí

Dajani A Simple Introduction to Ergodic Theory p145
Karma Dajani and Sjoerd Dirksin

Dajani, Karma and Dirksin, Sjoerd: A Simple Introduction to Ergodic Theory, December 18, 2008, p134 ................18

Kettler Ergodic Theory p33

Sarig Lecture Notes on Ergodic Theory p137

Sarig Lecture Notes on Ergodic Theory p115

Sarig Lecture Notes on Ergodic Theory p115.pdf

Sarig Lecture Notes on Ergodic Theory p137

Steif Notes on Ergodic Theory p52
by Jeff Steif
3

Steif Notes on Ergodic Theory p52

Viana Foundations of Ergodic Theory p76
Marcelo Viana and Krerley Oliveira

Zimmer Ergodic Theory, Groups, and Geometry p93
Robert J. Zimmer


FOURIER ANALYSIS

Berg Fourier Analysis p116

Gripenberg Fourier Analysis p137

Peacock Fourier Analysis p79
26

Schoenstadt An Introduction to Fourier Analysis p270......................222


Fractal Geometry

Falconer Fractal Geometry p155

okokok

Falconer Fractal Geometry p155

Krantz Fractal Geometry p5

Krantz Fractal Geometry p5
Steven G. Krantz

PEARSE AN INTRODUCTION TO DIMENSION THEORY AND FRACTAL GEOMETRY: FRACTAL DIMENSIONS AND MEASURES p22
ERIN PEARSE

PEARSE AN INTRODUCTION TO DIMENSION THEORY AND FRACTAL GEOMETRY FRACTAL DIMENSIONS AND MEASURES p22

XU FRACTAL GEOMETRY AND DYNAMICS p60

XU FRACTAL GEOMETRY AND DYNAMICS p60
MOOR XU


functional analysis

FUNTIONAL

<DIR> en

Allan functional analysis,hilbert spaces and banach algebras p145.pdf

Arnold FUNCTIONAL ANALYSIS1 p36

Avramidi, Ivan: Methods of Mathematical Physics, February 12, 2005, p173????????????? 44

Bass Functional analysis p182
19

Belton Functional Analysis p127

Belton Functional Analysis_notes p127???????????????????? 9

Buhler FUNCTIONAL ANALYSIS p375

Cannarsa Lecture Notes on Measure Theory and Functional Analysis p216

Gamel Elements of Functional Analysis p56.pdf
Hang Functional Analysis Notes p83.pdf
Johnsen Notes on Functional Analysis p79.pdf
KornerZZZ Introduction to Functional Analysis Part III, Autumn 2004 p33.pdf
KutatelazeZZZ Functional analysis Russian p366.pdf
lfa01-ims.pdf
lfa02-ccc.pdf
lfa03-nvs.pdf
lfa04-ips.pdf
lfa05-oe.pdf
lfa06-lf.pdf
lfa07-ilt.pdf
lfa08-lths.pdf
lfa09-slo.pdf
LINEAR FUNCTIONAL ANALYSIS lfa01.pdf
LINEAR FUNCTIONAL ANALYSIS lfa02.pdf
LINEAR FUNCTIONAL ANALYSIS lfa03.pdf
LINEAR FUNCTIONAL ANALYSIS lfa04.pdf
LINEAR FUNCTIONAL ANALYSIS lfa05.pdf
LINEAR FUNCTIONAL ANALYSIS lfa06.pdf
LINEAR FUNCTIONAL ANALYSIS lfa07.pdf
LINEAR FUNCTIONAL ANALYSIS lfa08.pdf
Linear Functional Analysis.htm
RAO FUNCTIONAL ANALYSIS raoscript_2 p60.pdf
Salamon Functional Analysis – Lecture script p93.pdf

Sasane Functional analysis and its applications p92

SasaneXYZ Functional analysis and its applications p92.pdf
Serfaty Functional_Analysis Notes p66.pdf
Sunder Functional Analysis Spectral Theory p317.pdf

Teschl Nonlinear Functional Analysis p74

Teschl Nonlinear Functional Analysis p68.pdf
Teschl Topics in Real and Functional Analysis p177.pdf
Teschl Topics in Real and Functional p211.pdf
Ward Functional analysis lecture notes p73.pdf

<DIR> de

Albrecht Funktionalanalysis 1 und 2 p224.pdf
Arendt Funktionalanalysis p168.pdf
ArendtYYY Funktionalanalysis p168.pdf
Balser Elemente der Funktionalanalysis p53.pdf
Balser Vorlesungsmanuskript zu Funktionalanalysis p85.pdf
BERGNER NICHTLINEARE FUNKTIONALANALYSIS WS 0708 p101.pdf
braack Angewandte Funktionalanalysis p127.pdf
Brokate Funktionalanalysis_ws01 p82.pdf
Chill Funktionalanalysis p109.pdf
Cooper Funktionalanalysis und Integrationstheorie p72.pdf
de Lellis Funktionalanalysis p199.pdf
Denk Skript zur Vorlesung Funktionalanalysis p103.pdf
Denk Skript zur Vorlesung Funktionalanalysis p120.pdf
DenkYYY Skript zur Vorlesung Funktionalanalysis p120.pdf
Dobrowolski Angewandte Funktionalanalysis p118.pdf
Frehse Einfuhrung in die Funktionalanalysis p141.pdf
FrehseYYY Einfuhrung in die Funktionalanalysis p141.pdf
Grundemann funkanalysis p214.pdf
Haslinger FUNKTIONALANALYSIS I, II Skriptum zur Vorlesung p130.pdf
HaslingerYYY FUNKTIONALANALYSIS I, II Skriptum zur Vorlesung p130.pdf
Hauser Vorlesung Funktionalanalysis p109.pdf
Hoffmann Funktionalanalysis I Operatortheorie p96.pdf
Hoffmann Funktionalanalysis I p87.pdf
Hofmann Funktionalanalysis mit Anwendungen p186.pdf
Hofmann Funktionalanalysis mit Anwendungen p212.pdf
HofmannYYY Funktionalanalysis mit Anwendungen p186.pdf
HofmannYYY Funktionalanalysis mit Anwendungen p212.pdf
Junghanns 2009_Funktionalanalysis_p51.pdf
Junghanns Skript zur Vorlesung Funktionalanalysis p57.pdf
Kaltenback Funktionalanalysis 2 p117.pdf
Ka?mann Funktionalanalysis_SS2011 p93.pdf
Kriegl FUNKTIONALANALYSIS 2 SPEKTRALTHEORIE p166.pdf
Kriegl Funktionalanalysis I p147.pdf
KrieglYYY FUNKTIONALANALYSIS 2 SPEKTRALTHEORIE p166.pdf
Kupper Funktionalanalysis p146.pdf
Leis Funktionalanalysis p233.pdf
Leis Funktionalanalysis-1 p231.pdf
Leis Skript-Funktionalanalysis p236.pdf
LeisYYY Funktionalanalysis-1 p231.pdf
LeisYYY Skript-Funktionalanalysis p236.pdf
Lemmert Funktionalanalysis p126.pdf
Lesky FunkAna-Mitschrieb p143.pdf
LeskyYYY Funktionalanalysis - Mitschrieb p143.pdf
Meise Einfuhrung in die Funktionalanalysis Kapitel III p165.pdf
MeiseYYY Einfuhrung in die Funktionalanalysis Kapitel III p165.pdf
Mugnolo Elemente der Funktionalanalysis p64.pdf
Mugnolo Funktionalanalysis p379.pdf
MugnoloYYY Funktionalanalysis p379.pdf
Oertel-Jager Funktionalanalysis p70.pdf
Plonka-Hoch Funktionalanalysis I p135.pdf
Roch Funktionalanalysis und Integralgleichungen p130.pdf
RochYYY Funktionalanalysis und Integralgleichungen p130.pdf
Ruzicka Nichtlineare Funktionalanalysis p101.pdf
Schatzle Nichtlineare Funktionalanalysis p103.pdf
Scherer Manuskript zur Funktionalanalysis p158.pdf
SchererYYY Manuskript zur Funktionalanalysis p158.pdf
Schick Kurz-Skript zu ”Funktionalanalysis I“ p54.pdf
Schmidt Funktionalanalysis p114.pdf
Schmudgen Funktionalanalysis p94.pdf
Schnaubelt Skriptum zur Vorlesung Funktionalanalysis p89.pdf
Schulz Skript Funktionalanalysis 2006_WS_p108.pdf
Struwe Funktionalanalysis I und II p187.pdf
StruweYYY Funktionalanalysis I und II p187.pdf
Trostorff Grundlagen der Funktionalanalysis p194.pdf
Ulbrich Funktionalanalysis und Anwendungen p115.pdf
Voigt Funktionalanalysis Ip109.pdf
von Wahl funktionalanalysis p265.pdf
Vorlesung Funktionalanalysis I p158.pdf
Vorlesung Funktionalanalysis II p134.pdf
Wagner Skriptum zur Vorlesung FUNKTIONALANALYSIS p116.pdf
Wegert Analysis IV Funktionalanalysis Angewandte Mathematik Analys4 p61.pdf
Weidmann Analysis IV Einfuhrung in die Funktionalanalysis und Lebesgueintegration p182.pdf
WeidmannYYY Analysis IV Einfuhrung in die Funktionalanalysis und Lebesgueintegration p182.pdf
Winklmeier Lecture Notes Analysis 1, 201201, Universidad de los Andes p69.pdf
Wirth Analysis V (Funktionalanalysis) p67.pdf
Wittbold Funktionalanalysis I p227.pdf
Wulkenhaar Einfuhrung in die Funktionalanalysis p102.pdf
YYYVorlesung Funktionalanalysis I p158.pdf
Zehnder Funktionalanalysis I p121.pdf

<DIR> fr

<DIR> gk

FelouzcZZZ Panepist?μio AigaDou GREEK p270.pdf
ShmeiZZZ functional-analysis GREEK p58.pdf

<DIR> ru

AvanacevaZZZ Функциональный анализ p97.pdf
DanilinZZZ functional analysis FA_2011 RUSSIAN p102.pdf
ErmilovZZZ functional analysis RUSS p106.pdf
GanenkovaZZZ Functional analysis Russian p88.pdf
KondakovZZZ Функциональный анализp48.pdf
KopatchevskeeZZZ Функциональный анализ p140.pdf
KutatelazeZZZ Functional analysis Russian p366.pdf
Kytazelatse 000Elementary Funtional p366.pdf
RevinaXXX functional analysis RUSSIAN p110.pdf
АсташоваZZZ Функциональный анализp112.pdf
КадецZZZ Functional_Analysis p616.pdf
СазоновXYZ Функциональный анализ p53.pdf


Geometry

(Computational) Geometry

Africk Elementary College Geometry p374
Henry Africk
13

Audin, Michele: Geometry, May 2002????????? ?10

Barge EOCT Analytic Geometry Study Guide FINAL p215.pdf

Belyaev, Oleg A.: Fundamentals of Geometry, February 28, 2007, p256 ................28

Bredon Topology_and_Geometry p296.pdf

Bruzzo INTRODUCTION TO ALGEBRAIC TOPOLOGY AND ALGEBRAIC GEOMETRY p138.pdf

Chen, Jianer: Computational Geometry - Methods and Applications, Third Edition, 1996, p227??

Coxeter GEOMETRY REVISITED p205.pdf????????

de Berg, Mark et al: Computational Geometry - Algorithms and Applications, Second Edition, Springer, 2000

de Berg, Mark: Computational Geometry - Algorithms and Applications, Third Edition, 2008

Demailly Complex Analytic and Differential Geometry p455.pdf

Demailly Complex Analytic and Differential Geometry p455
Jean-Pierre Demailly

Dolgachev Introduction to Algebraic Geometry p198.pdf

Gathmann Algebraic Geometry p214.pdf

Khudaverdian Riemannian Geometry p107
it is a draft of Lecture Notes of H.M. Khudaverdian

MasonZZZ Geometry For Elementary School Teachers p264.pdf

O'Rourke, Joseph: Computational geometry in C, Cambridge University Press, 2004

Rossmann Lectures on Differential Geometry p221.pdf

Vince Geometry for Computer Graphics p359

Waner Introduction to Differential Geometry General Relativity p138.pdf


Information Theory

Board Foundations and Trends in Communications and Information Theory p116
Volume 1 Issue 4, 2004
Editorial Board

Carter An introduction to information theory and entropy p139
Tom Carter

Chaitin ALGORITHMIC INFORMATION THEORY p236.pdf

Cover, Thomas M. and Thomas, Joy A. :Elements of Information Theory, John Wiley & Sons, Inc., 1991 , p563 .........................104

GrunwaldZZZ Algorithmic Information Theory p37.pdf

Yu Tutorial Information Theory and Statistics p250.pdf


Invariant Theory

okokok Invariant Theory p7

Brassil GEOMETRIC INVARIANT THEORY p65

Crawley-Boevey LECTURES ON REPRESENTATION THEORY AND INVARIANT THEORY p77

Draisma Invariant Theory with Applications p72

Kraft CLASSICAL INVARIANT THEORY A Primer p129


Laplace Equation

Analytic Solutions to Laplace’s Equation in 2-D

Laplace's equation: Complex variables

Laplace equation in a rectangle, Fourier series

Laplace’s Equation

Laplace’s Equation, Analytic and Numerical Solution

LAPLACE’S EQUATION IN SPHERICAL COORDINATES

Numerical Solution of Laplace Equation

Laplace’s Equation

The Planar Laplace Equation

Laplace’s Equation

Laplace’s Equation


Manifold Theory

Petersen Manifold Theory p103

Peter Petersen

Petersen Manifold Theory p103

Peter Petersen


Math4Music

Benson Music A Mathematical Offering p531.pdf
Kung How Music and Mathematics Relate p118.pdf
Shafer The Two-Part and Three-Part Inventions of Bach A Mathematical Analysis p168.pdf
Shah An Exploration of the Relationship between Mathematics and Music p102.pdf
Wright Mathematics and Music p176.pdf


Math4SearchEngines

IpsenYYY The Mathematics Behind Googles PageRank p48.pdf
TordableYYY Mathematics at Google p52.pdf
TordableYYY Mathematics at Google.pdf
TordableYYY Mathematics at Google1 p52.pdf
TordableYYY Mathematics at Google2 p52.pdf
TordableYYY Mathematics at Google3 p52.pdf


mathematical analysis

JOLY Introduction a lanalyse mathematique de la propagation d'ondes en regime harmonique p104

Rudin Principles of mathematical analysis p351

23

Trench INTRODUCTION TO REAL ANALYSIS p586

Zakon Mathematical Analysis p365

Volume I


Mathematical Physics

Agoshkov METHODS FOR SOLVING MATHEMATICAL PHYSICS PROBLEMS p335.pdf
Avramidi Methods of Mathematical Physics0 p173.pdf
Avramidi Methods of Mathematical Physics1 p78.pdf
Govaerts Contemporary Problems in Mathematical Physics p326.pdf
KRASIL0SHCHIK Homological methods in equations of mathematical physics p149.pdf
Li 数学物理方程 p267.pdf
Marsden Lectures on Geometric Methods in Mathematical Physics p134.pdf
Meusburger Concepts and Methods of Mathematical Physics p142.pdf
Plenio Mathematical Physics Theory 2003 p133.pdf
Rybkin Math Physics Lecture Notes p270.pdf
Stone Mathematics for Physics I p459.pdf
Stone Mathematics for Physics II p455.pdf
Stone Methods of Mathematical Physics I p316.pdf


Math General

<DIR> en

GrahamYYY Concrete_Mathematics_A_Foundation_of_Computer_Science_2nd_Edition p690.pdf
GrahamZZZ Concrete Mathematics p640.pdf
HwangZZZ An Introduction to Abstract Mathematics p487.pdf
Marsden Lectures on Geometric Methods in Mathematical Physics p134.pdf

McLennan The Nature and Origins of Modern Mathematics an Elementary Introduction p462.........? 48

Megill Metamath p211.pdf
MeusburgerYYY Concepts and Methods of Mathematical Physics p142.pdf
Polya HowToSolveIt p136.pdf
Shafer The Two-Part and Three-Part Inventions of Bach A Mathematical Analysis p168.pdf
Stone Mathematics for Physics II p455.pdf

<DIR> de

000Mueller angewandte math p257.pdf
Grassmann Ausdehnungslehre_1878 p347.pdf
Ihlenburg Grundlagen der mathematischen Modellierung p72.pdf
Markwig Grundlagen der Mathematik p668.pdf
Mueller angewandte math p257.pdf

<DIR> gk

Πετρ?πουλο?ZZZ Μαθηματικ?ν p193.pdf


Model Theory

Dawar Infinite and Finite Model Theory Part II p67

Anuj Dawar Libkin Elements of Finite Model Theory p326

V??n?nen A Short Course on Finite Model Theory p44

Jouko V??n?nen 5

Weiss Fundamentals of Model Theory p64

William Weiss and Cherie D’Mello


Number theory

Number theory and cryptography (2010-Nov 2013)

Number theory was considered the crown of the mathematics, but I would consider algebra as its crown as number theory of today depends much on how modern algebra develops and provides tools for. Number theory today is very different from number theory of a century ago. I uses the theories and tools of many other maths and in return it also provides mechanism for many other branches of math and other sciences.

Since 2006, after the death of my father, people have persuaded me to do something to contribute to the society and not to waste my talents. Over this time period, I have studied very hard and tried many areas of researches and studies before finally a fixing my research area of computational number theory, particularly primality testing between November 2011 and December 2013.

My research area was number theory, and particularly prime number prove and later integer factorization related to cryptography. I was not born mathematician. It took me a long long way to finally decide to do math. My major was in thermal science and I have been in the energy and power industry since long. Over the past several years since 2007, I have tried various branches of sciences with some sorts of researches and authoring in process.

Although there is no way to enter the academic world except with my own research at hand, yet I am determined to carry out my researches on my own at any cost under any circumstances, how hard my condition may be. Therefore considering all the constraints to research capacity as a solo researcher without the necessary supports and working atmosphere of a well established academic entity, I am determined to reorient myself as a number theorist, in connection with cryptography and Internet security. With my superb math foundation and learning capacity, I can step in the number theory and other math and science areas fairly quickly.

I chose number theory as my future research area because first all my previous attempts in other branches of science were failed and no universities and organizations were willing to support my researches, and second, without good experimental facilities and a good team I am unable to continue most of my research projects. Number theory on other hand depends mainly on my personal talent and intelligence. On other hand, any serious researches on whatever topics you may choose involves lots of math, and sometimes math is a determining tools in researches of other sciences. But I don’t have so much time to cope with both of them. I came to number theory also as a result of my combat to Internet blockade. In 2009 I was determined to work on Internet security in order to ensure my free access to and my security of my identity while using the Internet with various encryption services. I was attracted by the cryptographic technologies, and later it was found the its mathematical foundation is modern algebra (DES) and number theory (RSA). So it was a natural conclusion that these sciences will become parts of my studies objects.

During the first years, I was focusing on prime number testing and integer factorization. But later my researches also extended to other branches of number theory. And finally I wished to join the world mathematician communities again with my researches on number theory, particularly those related to cryptography.

I planed first to propose my own improvements to existing deterministic, unconditional and polynomial time prime number tests – particularly the AKS test and go a step further to figure out my own. My second phase of research would be to benchmark the probabilistic and the deterministic primality tests based on complexity considerations in order to find out the threshold between these two and to put forward criteria of the real world optimal algorithms for various applications. I hoped these studies will contribute to the development of practical cryptographic systems used for Internet security over the next years.

I was doing my researches on my own – that is, I did not work in any university or any math institute in China. I also paid all the expenses in doing the researches, therefore I have to earn money to support my researches. But it was very difficult, if not impossible, to achieve what I have in mind when I continued to do this way, because during the day I have to earn money and only in the evening can I find 1 or 2 hours for number theory, if I still have to study number theory alone.

Therefore I hoped that someone could provide me with some help. I would appreciate it very much if he or she would provide me with a place where I can quietly conduct my researches on number theory and other related topics. It would also greatly help me if he or she could provide me with the recent development of the AKS algorithm.

In order to enable me to pursue a genuine studies, I have been learning and reading a lot of literature of many kinds, amounting to thousands of books and papers. Here below is an incomplete list of readings in areas of Math, IT, Languages and some of the greatest works of the greatest scientistst of the human kind since mid 2010. This is not an exhaustive list, it does not include any books I read before that time and it also not include those outside of these areas.

Upto now, I am not only reading number theory and its sub branches, but also related branches of math - such as complex functions, functional analysis, computational math - and have been compiling some preliminary paper as a result of studies. Although my current studies of math concentrates on mathematics related to information exchange security and cryptography, incl. also number theory, algebra, combinatorics and others.

Primality testing
Primality testing is closely related to cryptography and thus is now one of the basic theoretic foundations for cryptography and encryption. There are many algorithms for testing if a given number is prime or not. They can be categorized into two types - deterministic or probablistic. And they are further divided into several types. How to choose the most appropriate prime number generation algorithm is not an easy task.
My current number theory researches focus on primality, but that can be changed soon. I may turn to integer factorization because prime testing seems a problem largely considered solved as Miller-Rabin probablistic prime test is enough for most uses and AKS as a theoretic foundation for polynomial test algorithm.

AKS primality testing
AKS primality testing is the first and only deterministic, polynomial and non-conditional primality test, developed in 2002 by three Indians. However, until now it is very slow, and thus is not practical. Noone uses it as an actual prime number selection algorithm. To test if a 1024-digit number is prime or not, the most powerful computer needs to run millions of years to get a result. Nevertheless, it is worth trying to improve its complexity and reduce the time and storage requirement for testing.

I used plan to do some indepth researches on AKS, but it was cancelled due to various reasons. Instead this will be part of the primality testing.

My AKS primality testing research plan

?Topics

Comprehensive reviewing of the AKS primality testing and indeep improvement of its algorithm.

Goals & Objectives

Improvement of the AKS primality testing to the complexity level of about log(N)^3, where N is the number to be tested for primality. Current status: log(N)^6.5. Thus this primality testing method can be used for encryption purpose.

Publications as result of research

A book of about 500 pages will be prepared and published, its main content are planned – see the attachment.

Factorization

Algorithms include Fermat’s Method, Quadratic Sieve, Special Number Field Sieve, and General Number Field Sieve.

Fact: Let n be uniformly chosen at random from [1, x]
If testing primality at each stage, it takes O(p+lgn) division, where p is the second-largest prime factor of n.
If ? ? a ? 1, then the probability that the largest prime factor of n is ? xa is approximately 1 + ln a. Thus, the probability that n has a prime factor > sqrt(x) is around 0.69
The probability that the second largest prime factor of n is < x0.2117 is about ?
The expected total number of prime factor of n is ln ln x + O(1)

Baillie-Pomerance-Selfridge-Wagsta test
Block Lanczos Algorithm
Block Wiedemann Algorithm
Brent's Factorization Method
Chinese Remainder Theorem
Class Group algorithm – Shanks???
Class Group Method - Schnorr and Lenstra
class-group method - Schnorr-Lenstra-Shanks-Pollard-Atkin-Rickert
class-group method - Schnorr-Seysen-Lenstra-Lenstra-Pomerance
congruence-combination factorization methods
Continued Fraction Algorithm (CFRAC) - Morrison and Brillhart
continued fraction factoring algorithm
Continued fraction method
continued fraction factoring method - Brillhart
CRAC
Cyclotomic Polynomial Method - Bach and Shallit
Discrete logarithm
Elliptic curve method ?Elliptic curves factoring - Lenstra
Fermat factorization algorithms
hyperelliptic-curve method - Lenstra, Pila, and Pomerance
Lehman’s algorithm
monte carlo
optical Interferometer and Phase Modulation method for prime factorization
p-1 factoring algorithm - Pollard
p + 1 method of factoring? -? Williams
QUADRATIC FORMS
binary quadratic forms
QUANTUM FACTORING ALGORITHM - ?SHOR
RAK factoring algorithm
Random Squares algorithm - Dixon
Random equal Squares algorithm - Dixon
rho method - Pollard
randomized rho method
Sieve methods
generalized sieve methods
General Number Field Sieve
Most efficient known algorithm is General Number Field Sieve.
Number Field Sieve algorithm (NFS) - Pollard et. al.
number-field sieve Pollard-Buhler-Lenstra-Pomerance-Adleman
general number field sieve
GGNFS GGNFS, a GPL implentation of the General Number Field Sieve
special number field sieve factorization
MPGNFS
Lattice sieving
linear sieve
Quadratic Sieve algorithm – Pomerance
Multiple Polynomial Quadratic Sieve algorithm (MPQS) - Montgomery
self-initializing quadratic sieve
Quantum sieve method – Pomerance
Selberg Sieve
sieves using binary quadratic forms
Square Forms Factorization (SQUFOF) algorithm - ?Shanks
Universal Exponent Factorization Method

Quantum Computing Algorithm for factorization
In 1994, Peter Shor invented a Quantum Computing Algorithm for factorization.
Runs in O(b3) time and needs O(b) storage for a b-bit integer.
Tested in 2001 using Quantum Computer with 7 q-bits. Factorized 15 into 3 and 5. ? (Wikipedia)

Why not number theory in China?

China’s education and research segments are currently very corrupted, therefore it is impossible to undertake pure researches without the compromise with this system. And the general trends towards decay of the Chinese society does not allow for genuine researches and studies.

And in general China seems never to turn into a free and democratic country and the general social, political and economical situation is worsening daily so that to conduct my favorite researches or to run my preferred business is barely impossible, and even the survival chance is very rare if I don’t want to cooperate with the corrupted officials and the dictatorship regime. I stayed in China till now because I thought I can always find a compromise between a moderate career and my strongest desire to stay together with my parents. But now, this compromise can never be realized.

Therefore there is only one option to me: to suicide myself in China or to leave China for a new beginning.

That’s why I am now looking for opportunities at your organization at my age.

Letter to Apply for Number Research Position

Dear Prof. COUVEIGNES,

I have read your book and paper in number theoretic topics, as part of my efforts to work indepth on that subject. I request that your books and papers be incorporated into my literature references, as well as all those others you may provide me for further reading later on. Furthermore I would appreciate it very much if you would consider me with an opportunity that I can conduct my researches on number theory and other related topics particularly the primality testing methods (which is my lifetime research area) in your organization. Right now I am doing math out of my own budget, time and initiative.

I had some opportunities for PhD study in several world renown universities in the past, but did not pursue this for personal reasons, instead I have been embarking on a career in industry, but at this point in life, I would like to pursue a academic career in mathematics.

I plan first to propose my own improvements to existing deterministic, unconditional and polynomial time prime number tests – particularly the AKS test and go a step further to figure out my own.

My second phase of research will be to benchmark the probabilistic and the deterministic primality tests based on complexity considerations in order to find out the threshold between these two and to put forward criteria of the real world optimal algorithms for various applications.

And further my research will extend to other branches of the number theory and related math in conjunction with cryptography, because it was cryptography that caught my attention to those maths. I hope these studies will contribute to the development of practical cryptographic systems used for Internet security over the next years.

Finally I am curious to know how number theory is interacted with other maths and even beyond – i.e. physical sciences. That will be much late.

But I do not hurry up for publishing anything – I have merely planned the following: “One word, one theorem, one paper and one book.”, nothing more.

But they shall be of true value. Many have written hundreds, no, thousands of papers, only to be left forgotten in the libraries. I don’t want to follow them.

As I mentioned in my minibio - for more info also refer to my private site of http://www.neolife001.tk? - , if I did not devote my life to the benefits of others, if I did not refuse to yield to the Chinese communists, if my voice was not damaged, if … I would have made great achievement in whatever I choose to do. And now it’s time to do something for myself.

I am unique and unlike others in my ages, who are planning their retirement and designing the future of their kids.. I am 50 years young, young enough to achieve anything I want to do. I have no wife no kids, and my lifestyle keeps the same as a graduate student. My learning capacity has not been worsened – no, on contrary – improved over the years. And what others have to do in months, I in weeks. I can read hundreds of pages of math papers a day, in all languages. I do everything much quicker than most others.?

Therefore if there is someone willing providing a little help in my career, then a great achievement. But if no one can help me then I can make only very limited success and with significant time delay.

Thank you for your reading my letter and the accompanying documents and your kindest consideration of helping my academic career and look forward to hearing from you soon.

Your sincerely,

Chen Minghua
China
P.S.:
The lengthy resume is a bit more useful in evaluating my present capacity while the short one, non-sense as it is but favored by most people, is for your reference only.
Fore yet more info about my researches please refer to this site: http://www.neomath.tk
Right now I have to do some business – refer to these sites : http://www.neotech001.tk? (collection of past business activities) and? http://www.neolingo001.tk (translation and localization services -? in order to survive and support my studies and researches.

Granville BOUNDED GAPS BETWEEN PRIMES p54

ZhangYidang Bounded gaps between primes p56.pdf

<DIR> en

AchterYYY hist num theory p113.pdf

Adleman Algorithmic Number Theory 1994 p168 .....................

AgarwalYYY A Survey of Techniques Used in Algebraic and Number Theoretic Algorithms Kunming Tutorial, May 2005 p307.pdf
AgarwalYYY Two Problems of Number Theory p114.pdf
AGRAWAL PRIMALITY TESTING IN POLYNOMIAL TIME p218.pdf
Agrawal Primality Tests Based on Fermats Little Theorem p106.pdf
AgrawalYYY Is n a Prime Number march 2006 p136.pdf
AgrawalYYY Primality Tests Based on Fermat’s Little Theorem p106.pdf

Allahabad Factoring integers, Producing primes and the RSA cryptosystem p170

Apostol Introduction_To_Analytic_Number_Theory_p350 ....................... 118???????????

Apostol, Tom M.: Introduction to Analytic Number Theory, Springer-Verlag, 1976

Arnoux Factoring and primality testing I p189

ArnouxYYY Factoring and primality testing II p121.pdf

Arnoux Factoring and primality testing III p160

Arun-Kumar Algorithmic number theory (web draft p200

Arun-Kumar Algorithmic number theory (web draft p200.pdf

Arun-KumarZZZ Algorithmic Number Theory p200.pdf

Bach Algorithmic number theory vol 1 Efficient algorithms p516

Baker Algebraic Number Theory2006 p152??????????? 18

Baker, Matthew: Algebraic Number Theory Course Notes (Fall 2006)

Boeyens_Levendis-Number_Theory_and_the_Periodicity_of_Matter p387

BeukersYYY Elementary Number Theory p156.pdf

BOREVITCH Z. I. and CHAFAREVITCH, I. R. Number theory, Academic Press, 1966, p439...............137

$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

Borwein Computational excursions in Analysis and Number Theory p225

BOSMA PRIMALITY PROVING WITH CYCLOTOMY p337

BourkeYYY NumberTheoryApplications p109.pdf

Brent Factoring Integers – an Introduction p99

Bressoud Factorization_and_Primality_Testing p250

BU Primes in Context Using Technology_ Toward a Didactical Model p331

Buhler Algorithmic Number Theory p660

BurtonZZZ Elementary Number Theory p389.pdf

Cameron A Course on Number Theory p139.pdf

CARMICHAEL DIOPHANTINE ANALYSIS p120.pdf

Cassels Algebraic Number Theory p388

Cassels-Frohlich-Algebraic_Number_Theory p192

Clark Algebraic Number Theory II Valuations, Local Fields and Adeles p124.pdf

CLARK GEOMETRY OF NUMBERS WITH APPLICATIONS TO NUMBER THEORY p138.pdf

clarkYYY Elementary Number Theory _book p129.pdf

ClarkYYY Elementary Number Theory fini p129.pdf

clarkYYY elementary num_theory p129.pdf

Clark Number Theory A Contemporary Introduction p259

Cohen A course in computational algebraic number theory p563

Cohen A course in computational algebraic number theory2 p563.pdf

CohenYYY ComputationalAlgebraicNumberTheory p563.pdf

Cohn Advanced Number Theory P283

COMPUTATIONAL NUMBER THEORY s-cnt p126.pdf

Conrad Algebraic Number Theory p255

Conway The Book of Numbers p330

Cormen Introduction_to_algorithms_3rd_edition p1313.pdf

CormenYYY Introduction to Algorithms p984.pdf

CormenYYY Introduction to Algorithms-2nd-edition p1202.pdf

CormenYYY Introduction.to.Algorithms2 p1203.pdf

CrandallPomerance Prime Numbers A Computational Perspective p604

dajani A Short Introduction to Ergodic Theory of Numbers p58

DavidoffZZZ Elementary Number Theory p163.pdf

Duke Analytic Number Theory A Tribute to Gauss and Dirichlet p266

DukeYYY Analytic Number Theory A Tribute to Gauss and Dirichlet p264.pdf

EganSarah-Investigating Polynomial Time Primality Testing2004-5 p151.pdf

Einsiedler Ergodic Theory with a view towards Number Theory p171

FleronYYY Discovering the Art of Number Theory A Topical Guide p108.pdf

Game_Thesis_Binary integer wavelet transform p331

GoldsteinZZZ Analytic Number Theory p151.pdf

Goldstein The_Shaping_of_Arithmetic_after_C.F.Gausss_Disquisitiones_Arithmeticae p596

Gouvea Advances in Number Theory p553

XXXXXXXXXXXXXXXX
Granville BOUNDED GAPS BETWEEN PRIMES p54

Granville Multiplicative number theory p190

Gries Applied number theory in computing and cryptography p112

HackmanYYY Elementary Number Theory p168.pdf

HackmanYYY Elementary Number Theory p411.pdf

Hackman Elementary Number Theory p415

Hammad_Yousef_Bani_Thesis Novel method for primality testing p119.pdf

Hardy An Introduction to the Theory of Numbers p642

HardyRight An introduction to the theory of numbers p438

Harrap Diophantine approximation the twisted, weighted and mixed theories p151.pdf

Hartmann Factoring thesis FnZ p116.pdf

HectepencoZZZ Number theory Russian p293.pdf

Hildebrand Introduction to Analytic Number Theorymain p197

Hoang INTEGER FACTORIZATION WITH THE GENERAL NUMBER FIELD SIEVE p144.pdf

Holden Algebraic Number Theory p341

Holden Number Theory p561

Jia Analytic Number Theory p213

IYANAGA Algebraic Number Theory - Kyoto 1976 p155.pdf

Jean-Pierre Serre - A Course in Arithmetic p129.pdf

Ji Guanghua Algebraic Number Theory p147.pdf

JiaZZZ Analytic Number Theory p213.pdf

JinXYZ Researching and Implementing on AKS Algorithms p126.pdf

Joyanizis linear-programming p149.pdf

Koshy Elementary-Number-Theory-with-Applications p801

KoshyZZZ Elementary-Number-Theory-with-Applications p801.pdf

KumarYYY Algorithmic Number Theory p200.pdf

KumchevZZZ The Distribution of Prime Numbers p123.pdf

Lauridsen integerfactorization p174

Lenstra Computational Methods in Number Theory p213.pdf

LUCAS_BOOK_THEORIE DES NOMBRES p282.pdf

Malisrev Linik ergodic method to nuumber theory p23

MarshallYYY NumberTheoryThrough Inquiry p133.pdf

MartinYYY Number Theory II Spring 2010 Notes p121.pdf

MazurSteinYYY PRIMES January 20 2013 p140.pdf

Michel Analytic Number Theory and Families of Automorphic L-functions p119.pdf

Mihailescu Cyclotomy of Rings and Primality testing p186

Mileti Algebraic Number Theory p142.pdf

Milne Algebraic Number Theory p164

Oggier Introduction to Algebraic Number Theory p95

Milne Algebraic Number Theory2011 p327

Milne Algebraic Number Theory2012 p160.pdf

MILNEYYY ALGEBRAIC NUMBER THEORY1998 p140.pdf

MilneYYY Algebraic Number Theory2008 p163.pdf

MilneYYY Algebraic Number Theory2009 p164.pdf

MilneYYY Algebraic Number Theory2011 p167.pdf

milneYYY Modular Functions and Modular Forms p130.pdf

MINKOWSKI diophantischeapp00minkuoft p260

Montgomery Multiplicative Number Theory I Classical Theory p571

Motohashi Lectures on Sieve Methods and Prime Number Theory p180

Murty Problems In Algebraic Number Theory 2Ed p371

Nathanson Elementary methods in number theory 2000 p518

NathansonZZZ Elementary Methods in Number Theory 2000 p515.pdf

Neukirch Algebraic Number Theory-1 p294

Niven An introduction to the theory of numbers p541

OcunofZZZ Number theory Russian lec p117.pdf

Osserman Algebraic Number Theory p127.pdf

Parshin Number theory II, Algebraic Number Theory (1991, 137s).pdf

Patankar-NHTFF-1980 p205.pdf

PilaudZZZ Introduction a la theorie algebrique des nombres.pdf

PitkanenZZZ TGD as a Generalized Number Theory p129.pdf

Pohst Algorithmic Methods In Algebra And Number Theory p131.pdf

Pollack Not Always Buried Deep p323

PollardZZZ The Theory of algebraic numbers p173.pdf

Pollard The Theory of algebraic numbers p173

RademacherZZZ Lectures on Analytic Number Theory p283

Rademacher Lectures on Analytic Number Theory p283
6

Raji An Introductory Course in Elementary Number Theory p171

Raji An-Introductory-in-Elementary-Number-Theory p171.pdf

Ribenboim My Numbers My Friends p384??????????????? 73

Ribenboim, Paulo: My Numbers, My Friends: Popular Lectures on Number Theory, Springer-Verlag, 2000

Ribenboim The Little Book of Bigger Primes p381

Ribenboim The New Book Of Prime Number Records 3ed p285

Sandor Handbook of number theory, vol.2 p635

Sas primetests_endversion p90.pdf

Savin Numbers Groups and Cryptography p175.pdf

Saxena Is n a prime number p135.pdf

Saxena Primality Testing, Randomness Derandomization p150.pdf

Sedgewick Algorithms 4th edition p969.pdf

Sedgewick An_introduction_to_the_analysis_of_algorithms-Addison-Wesley_Professional(2013) p593.pdf

Sharifi ALGEBRAIC NUMBER THEORY p182

Shoup A Computational Introduction to Number Theory and Algebra ver2 p598

Shoup A Computational Introduction to Number Theory and Algebra2004 p518.pdf

Shoup A Computational Introduction to Number Theory and Algebra2005 p566.pdf

Shoup A Computational Introduction to Number Theory and Algebra2008 p596.pdf

ShoupYYY A Computational Introduction to Number Theory and Algebra ver1 ntb-v1 p533.pdf

ShoupYYY A Computational Introduction to Number Theory and Algebra Ver1 p534.pdf

ShoupYYY A Computational Introduction to Number Theory and Algebra ver2 p598.pdf

Siegel On Advanced Analytic Number Theory p241

SIEGELZZZ Advanced Analytic Number Theory p140.pdf

Stein Elementary Number Theory:Primes, Congruences, and Secrets p172

Stein A Brief Introduction to Classical and Adelic Algebraic Number Theory p190

Stein Algebraic Number Theory a Computational Approach November 14 2012 p215

Stein Algebraic Number Theory a Computational Approach2012 p213

Stein Algebraic Number Theory a Computational Approach2013 p143.pdf

stein an explicit appraoch to elementary number theory54 p168

Stein Elementary Number Theory p182.pdf

SteinYYY A Brief Introduction to Classical and Adelic Algebraic Number Theory p190.pdf
SteinYYY Algebraic Number Theory a Computational Approach2011 p211.pdf
SteinYYY Algebraic Number Theory a Computational Approach2012 p213.pdf
steinYYY algebraic_number_theory2010 p213.pdf
SteinYYY an explicit appraoch to elementary number theory p168.pdf
SteinYYY Elementary Number Theory 2004 p182.pdf
steinYYY Elementary Number Theory 2005 p180.pdf
SteinYYY Elementary Number Theory 20110426 p172.pdf
SteinYYY Elementary Number Theory p172.pdf
SteinYYY elementary_number_theory p180.pdf
SteinYYY Introduction to Algebraic Number Theory2005 p140.pdf
steinYYY-algebraic_number_theory a Computational Approach2010 p209.pdf
steinZZZ an explicit appraoch to elementary number theory54 p168.pdf

SteudingYYY Ergodic Number Theory p134.pdf
Steudling Ergodic Number Theory p133.pdf

Stewart Algebraic number theory and Fermats last theorem 3ed p334

stewartZZZ NATURES NUMBERS p176.pdf

STROMBERGSSON ANALYTIC NUMBER THEORY LECTURE NOTES p295

sujatha Old and New themes in Number Theory p138.pdf

SyzijZZZ Number theory Russian p136.pdf

Tattersall, JAMES J.: Elementary number theory in nine chapters, Cambridge University Press 1999, p417 ........... ok

Venturi Lecture Notes on Algorithmic Number Theory p217.pdf

VINOGRADOVZZZ NUMBER_THEORY Russian p178.PDF

Wedeniwski Primality Tests on Commutator Curves p167.pdf

WEIISSMAN NumberTheory p141.pdf

Wells PRIME NUMBERS The Most Mysterious Figures in Math p291.pdf

Wells PRIME NUMBERS The Most Mysterious Figures in Math p291?????????????? 40

Wells, David: PRIME NUMBERS, The Most Mysterious, John Wiley & Sons, Inc., 2005

Weston Algebraic Number Theory notes p173

Yan Song Y Primality Testing and Integer Factorization p386

YanSongYZZZ Number Theory for Computing p230.pdf

XXXXXXXXXXXXXXX
ZhangYidang Bounded gaps between primes p56

<DIR> de

Bollig Effiziente Algorithmen fur den Primzahltest p71.pdf
Burde Lucas-Lehmer Primzahltest pari_fac.pdf
Cassels Algebraische Zahlentheorie p247.pdf
FermatZahlTest.pdf
FriedlPrimzahltestsFaktorisierungsmethoden p113.pdf
Gramlich Zahlentheorie und Kryptographie Sommersemester 2007 p121.pdf
Hauck Primzahltests p71.pdf
Hauck Primzahltests und Faktorisierungsalgorithmen p71.pdf
Hauck PrimzahltestsSS2007 p64.pdf
Hechle primzahlnachweis diplom p72.pdf
Hensel Zahlentheorie p473.pdf
Hofmeister Zahlentheorie p335.pdf
Moller Elementare Zahlentheorie p254.pdf
Moller Elementare Zahlentheorie und Problemlosen p254.pdf
Ostermeier Primzahltests und Faktorisierung p83.pdf
preuXXX Ein randomisierter Primzahltest.pdf
Rempe Primzahltests fur Einsteiger p64.pdf
Rempe primzahltests fur Einsteiger_leseprobe p43.pdf
SchoenwaelderZZZ Elementare Zahlentheorie p145.pdf
SpindleZZZ Elementare Zahlentheorie p170.pdf
Witt Primzahltests p54.pdf

<DIR> fr

BelabasZZZ L ALGORITHMIQUE DE LA THéORIE ALGéBRIQUE DES NOMBRES p72.pdf
BorevitchZZZ Shafarevich Theorie des Nombres p25.pdf
Chambert-Loir THéORIE DES NOMBRES p146.pdf
CohenXYZ Problèmes ouverts en Théorie des nombres p52.pdf
cohenZZZ Equations Diophantiennes p78.pdf
CohenZZZ Méthodes Expérimentales en Théorie des nombres et en Analyse p86.pdf
DavidZZZ Seminaire de Theorie des Nombres, Paris 1989-1990 p139.pdf
Edixhoven ZZZ Theorie algebrique des nombres 2002 p79.pdf
Edixhoven ZZZ Theorie algebrique des nombres 2004 p85.pdf
EncausseZZZ la_science_des_nombres p150.pdf
ERD?SZZZ QUELQUES PROBLèMES DE THéORIE DES NOMBRES p55.pdf
EZOME Des tests de primalité p44.pdf
GoldensteinZZZ Seminaire de Theorie des Nombres Paris 1986-1987 p243.pdf
GranvilleZZZ Nombres premiers et chaos quantique p16.pdf
Harari Cohomologie galoisienne et theorie des nombres p137.pdf
HuberXYZ Theorie des nombres p42.pdf
jaconXYZ Histoire des nombres premiers p94.pdf
LamboleyZZZ premiers p80.pdf
MartinZZZ FORMES MODULAIRES ET PERIODES p118.pdf
PilaudZZZ Introduction a la theorie algebrique des nombres.pdf
RoyerZZZ Un cours de théorie des nombres p161.pdf
WaldschmidtZZZ Theorie des nombres 12 ects p109.pdf
zagierZZZ_théorie des nombres p13.pdf

<DIR> gk

AntoniatheeZZZ hist number theory Greek p97.pdf
TzanakisZZZ Theory of nymbers Greek p88.pdf
Θεωρ?α Αριθμ?ν p63ZZZ.pdf
ΘΕΩΡΙΑ ΑΡΙΘΜΩΝ p51XYZ.pdf
ΘΕΩΡΙΑ ΑΡΙΘΜΩΝ – ΑΛΓΕΒΡΙΚΕΣ ΔΟΜΕΣ p52ZZZ.pdf
Μαυρογι?ννη?ZZZ numbertheory p89.pdf

<DIR> ru

BOROZZZ Living number RUSS p216.pdf
HectepencoZZZ Number theory Russian p293.pdf
KaracubaZZZ Эйлер и теория чисел.pdf
KUMMERZZZ Mémoire sur la théorie des nombres complexes composés p123.pdf
OcunofZZZ Number theory Russian lec p117.pdf
SyzijZZZ Number theory Russian p136.pdf
ValentsinovitschXYZ Algebraic geometry and number theory Russian.p48.pdf
VINOGRADOVZZZ NUMBER_THEORY Russian p178.PDF
БорисКучинXXX 2005_Primality_tests_survey__Kuchin.pdf
ВоронковZZZ ЭЛЕМЕНТЫ ТЕОРИИ ЧИСЕЛ И КРИПТОЗАЩИТp88.pdf
ВоронковZZZ ЭЛЕМЕНТЫ ТЕОРИИ ЧИСЕЛ И КРИПТОЗАЩИТp96.pdf
РоссиZZZ Аналитическиеp397.pdf
СизыйZZZ Учебное пособие Теория чисел p174.pdf


Numerical analysis

COMPUTATION

Computational Fluid Dynamics software? page
CFD software? page
计算流体力学软件? page
CFD 软件?

CFD page
Computational Fluid Dynamics page
CFD Numerical flow simulation
Numerical simulation of the fluid dynamic

计算流体力学

Numerische Methoden
Analyse mathematique et numerique de la dynamique des fluides
simulation numerique en mecanique des fluides
Mécanique des Fluides Numérique
Methodes numeriques pour la dynamique des fluides

Hémodynamique
Lattice methods, including the lattice-gas method and its derivative, the lattice-Boltzmann method,
Lattice-Boltzmann

有限解析法
边界条件与解得存在唯一性
能力判别法
正则模态分析法
湍流模型没有统一成熟和普遍适用的模型
流体力学基本方程需要什么样的边界条件才能保证界的存在和唯一是一个未解决的问题
向量机
并行计算
通量校正传输
通量分裂
守恒律系单调上风格式 （MUSCL）
总变差减少法? (TVD)
有限元通量校正传输法
活动有限元法
自由拉格朗日法
无结构网络法
谱方法格络法
直接和半直接求解法
反扩散法
无参数无振荡耗散格式 （NND）
Lax有限元-差分混合格式
非线性微分方程的差分格式的稳定性与收敛性至今没有完整的理论

=========================

压缩机、制冷行业

计算流体力学 page
流场的数值模拟
流场的数值计算
流场的数值仿真
CFD page
Computational Fluid Dynamics page
CFD Numerical flow simulation
Numerical simulation of the fluid dynamic

Computational Fluid Dynamics software? page
CFD software? page
计算流体力学软件? page
CFD 软件?

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A list of open source CFD softwares that available through the internet is presented below. Possibly there are still a lot of other open source CFD packages that are not listed in here.
? ADFC
? Applied Computational Fluid Dynamics
? CFD2k
? Channelflow
? Code_Saturne
? COOLFluiD
? Diagonalized Upwind Navier Stokes
? Dolfyn
? Edge
? ELMER
EnSight CFD
? FDS
? Featflow
? Femwater
?http://www.freecfd.com/about/
FreeFEM
? Gerris Flow Solver
? IMTEK Mathematica Supplement (IMS)
? iNavier
? ISAAC
? Kicksey-Winsey
? MFIX
? NaSt2D-2.0
? NEK5000
? NSC2KE
? NUWTUN
? OpenFlower
? OpenFOAM
? OpenFVM
? PETSc-FEM
? PP3D
? SLFCFD
? SSIIM
? Tochnog
? Typhon solver
? PRIN-3D

Abaqus
ACUITIV v3.3(美国Fuel Tech公司开发,用于CFD(Computational Fluid Dynamics计算流体动力学)的后处理和可视化软件
ADAMS
ADINA
AirPak 建筑流体模拟CFD

ANSYS CFX http://www.ansys.com
ANSYS AutoReaGas3.1
AVL FIRE 2008.2.
Barracuda工程软件包是专门模拟流体-颗粒流动及化学反应的商用软件包
Cart3D

Cfdesign
CFdesign 8.0 (CFD分析仿真) 注册破解版
CFD-FASTRAN
CFL3D
CFX
Coolit is an Advanced CFD Thermal Analysis Software for Electronics
Our flagship product, Coolit , has become the CFD software of choice for electronics cooling applications . Daat continues to deliver affordable products ...
www.daat.com

Abaqus
ADINA
Advanced CFD——流体力学模拟计算软件
Airpak
ALGOR
CFD4Aeroelasticity
CFD4Flight
CFD4Vortices
CFD4Rotor
CFD4Turbulence
http://www.cfd4aircraft.com/
CFD++――流体力学计算模拟软件介绍
CFD-ACE+
CFD Software From ACRi -- CFDStudio, ANSWER, PORFLOW, TIDAL and RADM
CFX
COSMOSFloWork
CONVERGE
COVENTOR
cradle CFD 软件
Design Space 7.1
DTFSE
DYNA/USA971
elsA software
EasyCFD_G
ESI CFDRC V2004 (计算流体力学)
Exceed，定位于帮助教授流体力学和运输现象的一个计算流体力学(CFD) 软件包
FACI
FASTRAN
FDS / NIST
FDS (Fire Dynamics Simulator)
FEATFLOW ?http://www.featflow.de ??open-source
FEMLAB / COMSOL ?http://www.comsol.com commercial
FIDAP 基于有限元方法的通用CFD求解器
Fine系列CFD软件
Flexlm
FloEFD，FloEFD.Pro, FloEFD.V5
先进的通用流体软件-FloEFD
全球唯一完全嵌入机械CAD软件中、高度
工程化的通用流体传热T：021-62157100
www.simu-cad.com

FloEMC v5.1 Flomerics
Flotran 7.1
Flotherm v9.1-ISO 1CD(电子电器设备空气流和热传导分析的专用CFD软件)
FLOVENT
FLOW-3D / FLOW-Science
FlowGrid
Flowmaster汽车流体系统仿真…
FLOWNEX – SYSTEMS CFD SOFTWARE FOR THE DESIGN, ANALYSIS AND. OPTIMIZATION OF FLUID FLOW SYSTEMS. Flownex is an integrated systems CFD code used for the ...
www.flowsim.com.au

FLUENT CFD code
Fluent/Gambit
FLUENT / ANSYS-FLUENT
Fluent for CATIA v5 1.0.8
Fluent FloWizard 2.1.8 (计算流体力学软件)
FLUINT/FloCAD
FORMSYS MAXSURF 11 (船舶设计)
Free-Surface DEMO
Fun3D
The GASP CFD package? http://www.aerosft.com/
gridgen
Hoam-OpenCFD 1.7软件
高精度计算流体力学软件Hoam-OpenCFD
ICEM-CFD Icem CFD v5.0 Working 1CD(一个独立的网格处理软件包,允许仿真分析
Icepak
I-Deas-ESC
KIVA-3v
LINFLOW作为一款三维边界元流体动力学计算软件
Marc
Mathematica (Wolfram Research Inc.).
Mechanical 7.1
MFIX / NETL
Mgaero
MicroCFD
MixSim2.0 针对搅拌混合的专用
MoldFlow
Moldlex
MULTIFLO / SwRI
Multiphysics 3.2a / Comsol
Nastran + Heat Transfer Pro
《热流分析软件》(NIKA EFD Pro v8.2)
NSAERO

NUMECA
Numeca.Fine
OpenFOAM
Opera 3D Tempo
Overflow
Patran Thermal 2003
PAM- FLOW—PAM-FLOW|仿真软件
PAM-FLOW是高级计算流体力学(CFD)软件产品
Phoenics
PipeNet v9.0 1CD（复杂管网流体分析软件）
PKPM
POLYFLOW 3.10.2针对粘弹性流动的专用CFD求解器Fluent Polyflow 3.10.4
POWER FLOW
Professional 7.1
PSE: Hybrid Multizonal gPROMS—CFD
PUMPLINX
pyrosim2006
RPCD是散堆填料塔流体力学及传质计算软件的缩写
SC/Tetra
SENGA
simerics_计算流体力学
SPH-Tsunami / SwRI
STACH—3通风空调气流组织计算的CFD软件
STAR-CD or STAR-CCM+
Star-Design v4.14 Linux 64 (计算流体力学):
Storm/CFD2000
Tarsflow
TEACH / Gosman
TEAM
THINFOIL
umoni计算流体力学平台软件1.0
Upfront CFD
USAERO
VSAERO,

前处理
GAMBIT
HyperMesh

前后处理
ACUITIV v3.3(美国Fuel Tech公司开发,用于CFD(Computational Fluid Dynamics计算流体动力学)的后处理和可视化软件
GAMBIT
HyperMesh
TECPLOT

SIMPLE算法(半隐式压力校正解法)

(High Resolution Scheme)高精致格式

(Flux Difference Splitting)通量差分分裂
(Flux Vector Splitting)矢通量分裂
(Total Variation Diminishing，TVD)总变差减小

Jameson格式
(Resisual Smoothing)多层网格与残差光顺加速收敛技术

<DIR> en

Bastian Numerical Computation of Multiphase Flows in Porous Media p236
Peter Bastian

Bastian Numerical Computation of Multiphase Flows in Porous Media p236.pdf
Benzoni-Gavage Analyse mathematique et numerique de la dynamique des fluides compressibles p114.pdf
Deturck Lectures on Numerical Analysis p125.pdf

Deturck Lectures on Numerical Analysis p125
Dennis Deturck and Herbert S. Wilf

FEM_FEPG 基于FEPG的有限元方法 p142.pdf
Feng Boundary Element Methods p501.pdf
Hoffman Computational Thermodynamics1 p217.pdf
Huang 数值计算方法及其程序设计 p445.pdf
KANE ANALYSE MATHéMATIQUE ET SIMULATION NUMéRIQUE DE MODèLES D'éCOULEMENT DE FLUIDES INCOMPRESSIBLES EN SURFACE LIBRE ET MILIEU POREUX DéFORMABLE p119.pdf
Konstantinov FOUNDATIONS OF NUMERICAL ANALYSIS p278.pdf
Krafczyk Lattice Boltzmann methods for CFD p183.pdf

Lantos Advanced Numerical Methods for Option Pricing p126.pdf
Lomax, Harvard and Pulliam,Thomas H., Zingg, David W.: Fundamentals of Computational Fluid Dynamic , August 26, 1999???

Luo LBM for Two Dimensional Hdrofynamics p183.pdf

McDonough COMPUTATIONAL FLUID DYNAMICS of INCOMPRESSIBLE FLOW p155.pdf
McDonoughXXX COMPUTATIONAL FLUID DYNAMICS of INCOMPRESSIBLE FLOW p155.pdf

Mihail Konstantinov
Konstantinov FOUNDATIONS OF NUMERICAL ANALYSIS p278

METIER Modelisation, analyse mathematique et applications numeriques de problemes d'interaction fluid -structure instationnaires p220.pdf
Magnus Analyse numerique 2 p205.pdf

Moser Direct Numerical Simulation of Curved Turbulent Channel Flow p170.pdf

Quarteroni Numerical Mathematics p669
Alfio Quarteroni

Quarteroni Numerical Mathematics p669.pdf

Rojas, An Introduction to Computational Fluid Dynamics p133.pdf
SANTOS Numerical methods for fluid-structure interaction problems with valves p204.pdf

Rung Numerische Methoden der Thermo- und Fluiddynamik p166.pdf
Scheid 全美经典数值分析第二版 p398.pdf
Scott Numerical Analysis p341.pdf

Scott Numerical Analysis p341
L. Ridgway Scott
35

Wei, Liang: Direct Numerical Simulation of Compressible and Incompressible Wall Bounded Turbulent Flows with Pressure Gradients, December 2009, p215................................60??????

Wesseling ELEMENTS OF Computational fluid dynamics p147.pdf

XuDH 偏微分方程数值解法 p441.pdf
Young Introduction to Numerical Methods and Matlab Programming for Engineers p180.pdf

Young Introduction to Numerical Methods and Matlab Programming for Engineers p180
Todd Young and Martin J. Mohlenkamp

<DIR> de

000Grune Numerische Methoden fur gewohnliche Differentialgleichungen p159.pdf
AdamsZZZ Grundlagen der numerischen Stromungsmechanik p154.pdf
ALMBAUERZZZ Numerische Methoden in der angewandten Thermodynamik p72.pdf
Baeker-Numerische_Methoden_Materialwissenschaft p309.pdf
Blobel Statistische und numerische Methoden der Datenanalyse p308.pdf
BrückerZZZ Str?mungsmechanik II_Skript_2007 p178.pdf
B?hrnsen Allgemeine numerische Methoden p152.pdf
B?hrnsenYYY Allgemeine numerische Methoden p152.pdf
Frommer Numerische Methoden der nichtlinearen Optimierung p174.pdf
Grune Numerische Methoden der Finanzmathematik p145.pdf
Grune Numerische Methoden fur gewohnliche Differentialgleichungen p140.pdf
GruneYYY Numerische Methoden der Finanzmathematik p145.pdf
GruneYYY Numerische Methoden fur gewohnliche Differentialgleichungen p140.pdf
GruneYYY Numerische Methoden fur gewohnliche Differentialgleichungen p159.pdf
Heinze Numerische Methoden der Mechanik p96.pdf
Hollig Numerische Methoden der Analysis p128.pdf
HolligYYY Numerische Methoden der Analysis p128.pdf
Jakirli?XXX Numerische Methoden der Aerodynamik p55.pdf
Jakirli?ZZZ Numerische Methoden der Aerodynamik_100211 p54.pdf
Kloeden Numerische Methoden fur Differentialgleichungen p165.pdf
Koch Numerische Methoden numerik_skript p91.pdf
Kressner Numerische Methoden skript_2p p104.pdf
Malcherek Numerische Methoden der Str?mungsmechanik p195.pdf
PantleZZZ Numerische Methoden in der Str?mungstechnik p91.pdf
Peterseim NUMERISCHE METHODEN DER OPTIMIERUNG p74.pdf
Rannacher Numerische Mathematik 2 (Numerik Partieller Differentialgleichungen) p245.pdf
Reichel Numerische Methoden skript_13_07_2011 p110.pdf
Reinhardt Schlecht gestellte Probleme Einfuhrung und numerische Methoden p120.pdf
ReinhardtYYY Schlecht gestellte Probleme Einfuhrung und numerische Methoden p120.pdf
RichterZZZ NumerischeMethoden in der Str?mungsakustik p57.pdf
RungZZZ Numerische Methoden der Thermo- und Fluiddynamik p166.pdf
Schwab Numerische Methoden - Vorlesungs-Script p69.pdf
VerfurthZZZ Numerische Stromungsmechanik SM p162.pdf
Voss Numerische Methoden NMeth_2010 p180.pdf
Wieners Effiziente numerische Methoden in der Elasto-Plastizit?t p28.pdf
Wieners Numerische Methoden für Differentialgleichungen p101.pdf
WienersYYY Numerische Methoden für Differentialgleichungen p101.pdf

<DIR> fr

AlaouiZZZ METHODES NUMERIQUES APPLIQUEES Java p230.pdf
BeckersZZZ Methodes numeriques appliquees `a lenvironnement p104.pdf
DedieuZZZ METHODES NUMERIQUES FONCTIONS DUNE VARIABLE REELLE p96.pdf
DrapierZZZ Méthodes numériques dapproximation et de résolution en mécanique p218.pdf
GILLIZZZ METHODES NUMERIQUES MNE-Cours p132.pdf
Hauret Methodes numeriques pour la dynamique des structures p291.pdf
HauretZZZ Methodes numeriques pour la dynamique des structures p291.pdf
HureZZZ Méthodes numériques CoursMN p110.pdf
KleinZZZ Methodes numeriques pour la physique p63.pdf
LegendreZZZ Méthodes numériques p140.pdf
Louveaux Introduction aux MethodesNumeriques p82.pdf
LOZINSKIZZZ Méthodes numériques et modélisation pour certains problèmes multi-échelles p246.pdf
PironneauZZZ Methodes Numeriques pour les Equations aux Derivees Partielles p81.pdf
PradoZZZ Methode numerique pour le traitement signal p212.pdf
SalmonZZZ Methodes Numeriques pour lElectromagnetisme p142.pdf
ScheidXXX Methodes numeriques pour la dynamique des fluides p123.pdf
VOHRALIK METHODES NUMERIQUES POUR DES EQUATIONS ELLIPTIQUES ET PARABOLIQUES NON LINEAIRES p157.pdf
VOHRALIKZZZ METHODES NUMERIQUES POUR DES EQUATIONS ELLIPTIQUES ET PARABOLIQUES NON LINEAIRES p157.pdf

<DIR> gk

<DIR> ru


OPERATIONS RESEARCH

Boros Pseudo-Boolean Optimization p83

Endre Boros HILLIER INTRODUCTION TO OPERATIONS RESEARCH p1237

Seventh Edition FREDERICK S. HILLIER


Probability Theory

Cameron Notes on Probability p94
Peter J. Cameron

Cameron Notes on Probability p94

ChenYYY Applied Probability Theory p177.pdf

Dekking A Modern Introduction to Probability and Statistics Understanding p483

Dekking A Modern Introduction to Probability and Statistics Understanding p483

17

DurrettYYY Probability Theory and Examples p372.pdf

Durrett, Rick: Probability - Theory and Examples, Fourth Edition, Cambridge University Press, 2010, p440???????????41

Feller, William: An Introduction to probability Theory-and its applications, John Wiley & Sons, 1967, p525..........................130

Grinstead Introduction to Probability p520

Grinstead Introduction to Probability p520

HarPeled Class notes for Randomized Algorithms p126.pdf

Kerns Introduction to Probability and Statistics Using R p412
G. Jay Kerns

Kerns Introduction to Probability and Statistics Using R p412

KingYYY Notes on Probability Theory p124.pdf

Knill Probability and Stochastic Processes with Applications p382.pdf

KrachtYYY Introduction to Probability Theory and Statistics for Linguistics p137.pdf

Larsen Probability Theory Statistics p225.pdf

Meester A natural introduction to probability theory p204.pdf

Montgomery Applied Statistics and Probability for Engineers p976
Third Edition
Douglas C. Montgomery

Montgomery Applied Statistics and Probability for Engineers p976

MovellanYYY Introduction to Probability Theory and Statistics p127.pdf

RomikYYY Probability Theory p111.pdf

Soong FUNDAMENTALS OF PROBABILITY AND STATISTICS FOR ENGINEERS p408

Soong FUNDAMENTALS OF PROBABILITY AND STATISTICS FOR ENGINEERS p408

Steinsaltz, David: Introduction to Probability Theory and Statistics for Psychology and Quantitative Methods for Human Sciences . Lectures notes, 2011-2012, p302?????

Wu, Yaokun: Elementary Probability Theory 2006 p231


Proof Theory

Buss CHAPTER I An Introduction to Proof Theory p78

Restall proof theory and philosophy p168 Tait Lectures on Proof Theory p119


Topology

Dundas Differential Topology p210

Edelsbrunner COMPUTATIONAL TOPOLOGY AN INTRODUCTION p294

15

Guillemin DIFFERENTIAL TOPOLOGY p236

NARASIMHAN ALGEBRAIC TOPOLOGY p49

Renzo Introduction to Topology p118

18


Tensor Analysis

Bowen INTRODUCTION TO VECTORS AND TENSORS p314

Brannon Functional and Structured Tensor Analysis for Engineers p323

Dullemond Introduction to Tensor Calculus p53

Feng The Poor Mans Introduction to Tensors p17

4

FerkinghoBorg Introduction to vector and tensor analysis p61

Flügge Tensor Analysis and Continuum Mechanics p214

Heinbockel Introduction to Tensor Calculus and Continuum Mechanics p373

Marsden Manifolds, Tensor analysis, and Applications p617

MARSDEN MATHEMATICAL FOUNDATIONS OF ELASTICITY p576

Nelson Tensor analysis p138

Shapiro Lecture Notes on Vector and Tensor Algebra and Analysis p88

VANICEK TENSORS p101

Yang 张量 p426

郭日修 弹性力学与张量分析 p287


My Math Research Plan

Since 2006, after the death of my father, people have persuaded me to do something to contribute to the society and not to waste my talents. Over this time period, I have studied very hard and tried many areas of researches and studies before finally and eventually fixing my research area of computational number theory, particularly primality testing in November 2011..

My current and future research area is and will always be number theory, and particularly prime number prove and later integer factorization related to cryptography. I was not born mathematician. It took me a long long way to finally decide to do math. My major was in thermal science and I have been in the energy and power industry since long. Over the past several years since 2007, I have tried various branches of sciences with some sorts of researches and authoring in process.

Although there is no way to enter the academic world except with my own research at hand, yet I am determined to carry out my researches on my own at any cost under any circumstances, how hard my condition may be. Therefore considering all the constraints to research capacity as a solo researcher without the necessary supports and working atmosphere of a well established academic entity, I am determined to reorient myself as a number theorist, in connection with cryptography and Internet security. With my superb math foundation and learning capacity, I can step in the number theory and other math and science areas fairly quickly.

I chose number theory as my future research area because first all my previous attempts in other branches of science were failed and no universities and organizations were willing to support my researches, and second, without good experimental facilities and a good team I am unable to continue most of my research projects. Number theory on other hand depends mainly on my personal talent and intelligence. On other hand, any serious researches on whatever topics you may choose involves lots of math, and sometimes math is a determining tools in researches of other sciences. But I don’t have so much time to cope with both of them. I came to number theory also as a result of my combat to Internet blockade. In 2009 I was determined to work on Internet security in order to ensure my free access to and my security of my identity while using the Internet with various encryption services. I was attracted by the cryptographic technologies, and later it was found the its mathematical foundation is modern algebra (DES) and number theory (RSA). So it was a natural conclusion that these sciences will become parts of my studies objects.

During the first years, I will be focusing on prime number testing and integer factorization. But in my later years my researches will also extend to other branches of number theory. And finally I wish to join the world mathematician communities again with my researches on number theory, particularly those related to cryptography.

I plan first to propose my own improvements to existing deterministic, unconditional and polynomial time prime number tests – particularly the AKS test and go a step further to figure out my own. My second phase of research will be to benchmark the probabilistic and the deterministic primality tests based on complexity considerations in order to find out the threshold between these two and to put forward criteria of the real world optimal algorithms for various applications. I hope these studies will contribute to the development of practical cryptographic systems used for Internet security over the next years.

Currently I am doing my researches on my own – that is, I do not work in any university or any math institute in China. I also pay all the expenses in doing the researches, therefore I have to earn money to support my researches. But it is very difficult, if not impossible, to achieve what I have in mind when I continue to do this way, because during the day I have to earn money and only in the evening can I find 1 or 2 hours for number theory, if I still have to study number theory alone.

Therefore I would hope that someone could provide me with some help. I would appreciate it very much if he or she would provide me with a place where I can quietly conduct my researches on number theory and other related topics. It would also greatly help me if he or she could provide me with the recent development of the AKS algorithm.

2017-02-12


Untitled Document

since 2012-10-1

Graph Theory & Math

Graph Theory | Math
graph_datastructures | general | graph_embedding | tsp |

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Math Studies
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G:\studies\00Math\_Literature

???????????????????????????????????

Arora Computational Complexity A Modern Approach p489

p1.13 (23)

okokok

Diestel Graph Theory2005 p422

???????????????????????????????????

Godsil Algebraic Graph Theory p453

8

Graph Theory

Over the next years I will explore the big topic of graph embedding, and to start with I will first focus on graph representation or graph data structure in computer. I will achieve something like this:

  • types of graph data structures
  • software, programs and codes to handle the computation of graph representation
  • techniques and tools for the input and storage of graph data
  • media for the storage of graph data
  • techniques for manipulating graph data in the computer - display, and other operations
  • improvement of the existing algorithms and codes to speed up the graph data processing in computer

You may find out how far I am doing the research by checking the file below:

Literature and some compilation of different kinds of graph data structures (under frequent updating)

graph_datastructures_representation_snapshot.txt

Software, algorithms and codes of different kinds of graph data structures (under frequent updating)

graph_datastructures_algorithms_codes_snapshot.txt

Software, algorithms and codes of graph operations and theory (under frequent updating)

graph_algorithms_codes_snapshot.txt

Software of graph operations and theory (under frequent updating)

graph_softtools.htm

Generic Graph Theory Literature

I've a great number of literature in my reserve, most of them I will study in details, and I am also trying to find as many books as possible, for I am collecting all kinds of graph theory literature, for future use. Here are two identical listings - one a plain text file and the other a navigatable hypertext document:

graph_snapshot.txt

graph_snapshot.html

My Graph Theory Study Plan and Status

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progress

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graph_datastructures_literatureA

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000Graph Theory, Combinatorics & Optimization

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000graph_datastructures

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graph processing in computers

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New Adjacency List and Multiplicity

geaph data structures

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related sciences

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okokok

000AHUJA Network Flows Theory, Algorithms, and Applications Ch1_3 p103

Bonnington Combinatorial maps and the foundations of Topological Graph Theory 02_whole p228

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软件，算法，程序，代码000graph_algorithms_software

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***************************************

>>>graph_algorithms_codes

>>>ccpp

graph

>>>haskell
fgl-5.6.0.0

>>>java

???????????

BellmanFord

okokok
Graph

>>>lisps

>>>perl

Graph-0.9704.tar

>>>python

okokok
anonym
okokok
Tschacher

>>>ruby

rgl-master

***************************************

????????????????????????

>>>graph_datastructures_algorithms_codes

>>>ccpp

>>>lists

okokok

AhmedUnweightedDirected

okokok

AhmedWeightedDirected

okokok

AhmedWeightedUndirected

okokok

AhmedWeightedUndirected1

okokok

anonym1

okokok

arbhie2581

okokok

Chhabra

okokok

Daal

okokok

Elkan

okokok

ferenczi

okokok

geeksforgeeks

okokok

iokon

okokok

Jamal

okokok

NiclasJonsson

okokok

sanfoundry

okokok

Sangam

okokok

Sonawane

okokok

Wagner

okokok

Wagner1

>>>matrices

adj-matrix-code

????????????????????????

>>>java

>>>lists

okokok
AdjacencyList
okokok
hrishikesh-kumar
okokok
pbesra

>>>javascript

okokok
nivas8292

>>>matlab

okokok
wanirepo

>>>python

>>>lists

okokok

Abiy

okokok

Bradfield

okokok

ed

????????????????????????

interactivepython

okokok

exchez

okokok

Rees

SQLAlchemy

okokok

theGreatWhatever

vevurka

okokok

yang

>>>matrices

okokok

Hagberg

okokok

Toriyama

>>>swift

okokok
larryfox

>>>zzzcomprehensive

okokok
Convert Adjacency List To Adjacency Matrix Java - 2 - codegist.net

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>>>graph_soft

gephi-0.9.2-windows

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000graph_embedding

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000graph_embedding_02synonym

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graph_drawing>>>
===============

BARAHIMI WEB-BASED DRAWING SOFTWARE FOR GRAPHS IN 3D AND TWO LAYOUT ALGORITHMS p72

okokok
Battista Algorithms for Drawing Graphs an Annotated Bibliography p44

Bridgeman Techniques and Tools for Graph Drawing p168
GeomNet - http://loki.cs.brown.edu:8081/geomNet/ The Graph Drawing Server
27
AGD1
GDToolkit2
the Graph Drawing Server3

okokok
Cruz Graph Drawing Tutorial p107

Six Techniques for the Refinement of Orthogonal Graph Drawings p29

graph_generation>>>
=================

graph_layout>>>
==============

???????????????????????????????
???????????????????????????????
Dujmovic Track Layouts of Graphs p160
35

graph_packing>>>
==============

???????????????????????????????
???????????????????????????????
Pantel Graph Packing Problems p86
15

graph_visualization >>>
=================

G:\studies\000Math\000Graph\0000doc\000graph_embedding_02synonym\graph_visualization

G:\4academic\000Graph\0000graph_embedding\synonyms\graph_visualization

Aragón Graph Visualization Tool for Twittersphere users based on a high-scalable Extract, Transform and Load System p28

Beck A Taxonomy and Survey of Dynamic Graph Visualization p28

Boyd InProv: Visualizing Provenance Graphs with Radial Layouts and Time-Based Hierarchical Grouping p59

Carolina Graph Visualization Software for Networks of Characters in Plays p11

CHAPTER 8 Visualization Techniques for Trees, Graphs, and Networks p20

Dujmovic Track Layouts of Graphs p160
91

Epskamp Package qgraph p73

Ersoy Image-Based Edge Bundles: Simplified Visualization of Large Graphs p10

Erten Simultaneous Graph Drawing Layout Algorithms and Visualization Schemes p12

Etemad Node-Ring Graph Visualization Clears Edge Congestion p8

GANSNER An open graph visualization system and its applications to software engineering p29

Hadlak A Survey of Multi-faceted Graph Visualization p20

Herman Graph Visualization and Navigation in Information Visualization: a Survey p21

Hu Visualizing Data with Graphs and Maps p76

Huang Navigating Product Catalogs Through OFDAV Graph Visualization p13

Huang A new algorithm for removing node overlapping in graph visualization p24

Hurter Bundled Visualization of Dynamic Graph and Trail Data p14

Jarukasemratana Recent large graph visualization tools a review p17

Junghans Visualization of Hyperedges in Fixed Graph Layouts p131

Kairam GraphPrism: Compact Visualization of Network Structure p8

Kwon A Study of Layout, Rendering, and Interaction Methods for Immersive Graph Visualization p14

okokok
Razoumov Graph Visualization with Gephi p12

Rodin Visualization of Dynamic Reference Graphs p5

Scalisi Exploiting Interaction in Dynamic Graph Visualization p35

Spanakis Graph Visualization Tool for Vehicular Ad-Hoc Networks p2

Wu Evaluation of Graph Sampling: A Visualization Perspective p10

Zimmer Displaying User Behavior in the Collaborative Graph Visualization System OnGraX p13

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000graph_embedding_03types

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000graph_embedding_11references

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000graph_embedding_basic

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000Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346
2010
83

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00TSP

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Cracknell Simulating and Optimising a Delivery Network of Autonomous Courier Agents p151

Gharan A Randomized Rounding Approach to the Traveling Salesman Problem p65
2011
3

??????????????????????????????????????

Junger THE TRAVELING SALESMAN PROBLEM p117

8

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00tsp_algorithms

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00tsp_variations

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commbinatorial optimization for delivery of goods

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commbinatorial optimization for delivery of goods
operational research for delivery of goods
graph theory optimization for delivery of goods

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Bolhaar Strategic decisions in truck routing for a retail chain p90

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Caric Vehnicle Routing Problem p152
109

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Cracknell Simulating and Optimising a Delivery Network of Autonomous Courier Agents p151

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Leech DELIVERING THE GOODS p31

okokok
Pellonpera Ant colony optimization and the vehicle routing problem p57

Ant Colony Optimization
swarm intelligence algorithms
combinatorial optimization problem
traversing graphs / traversal of graphs
Vehicle Routing Problem
Vehicle Routing Problem with Time Windows.
operations research

Ropke A unified heuristic for a large class of Vehicle Routing Problems with Backhauls p36
3

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Veinott Lectures in Supply-Chain Optimization p261

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0graph_types

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Culler Planar graphs p69

18

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0hypergraph

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>>>hypergraph_partitioning

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000general

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000Bader Graph Partitioning and Graph Clustering p258

???????????????????????
000BangJensen Digraphs Theory algorithms and applications p772.pdf
42

000Berge HYPERGRAPHS Combinatorics of Finite Sets p267.pdf

???????????????????????

000Brouwer Spectra of graphs p229
17

000CHARTRAND Chromatic Graph Theory p498

???????????????????????

Cruz Graph Drawing Tutorial p107

11

000Dasgupta Algorithms p318

000Demaine Graph Algorithms p500

000Dongarra Graph Algorithms in the Language of Linear Algebra p372

000Gallian A Dynamic Survey of Graph Labeling p384

000Golumbic Algorithmic Graph Theory and Perfect Graphs 2ed p338

000Joyner Algorithmic Graph Theory p322

000Marx Algorithmic graph structure theory p255

000Riesen GRAPH CLASSIFICATION AND CLUSTERING BASED ON VECTOR SPACE EMBEDDING p346

000van der Hofstad Random Graphs and Complex Networks. Vo. I p328.pdf

000van der Hofstad Random Graphs and Complex Networks. Vol I p312.pdf

000Wulff-Nilsen Algorithms for Planar Graphs and Graphs in Metric Spaces p230.pdf

Bondy Graph Theory 2008 p654.pdf

Bondy Graph Theory with Applications 1982 p270.pdf

Bondy Graph theory 2008 p666.pdf

Diestel Graph Theory2000 p322.pdf

Diestel Graph Theory2005 p422.pdf

Harary Graph theory p281.pdf

???????????????????????
???????????????????????
???????????????????????

Ray Graph Theory with Algorithms and its Applications p222.pdf

60

?????????????????????????????????????????????????????
Spinrad Graph theory p245.pdf
46

Submodular Function_2ed p881.pdf

???????????????????????
???????????????????????
???????????????????????

Thulasiraman Handbook of Graph Theory Combinatorial Optimization and Algorithms p1217

227

van Steen Graph Theory and Complex Networks p287.pdf

West INTRODUCTION TO GRAPH THEORY 2nd Edition Solution Manual p260.pdf

okokok
Wilson Introduction to Graph Theory p180

???????????????????????
Woeginger Combinatorial Graph Theory p70

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de
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Diestel Graphentheorie II p326.pdf
14

Eidmann Algorithmische Graphentheorie im Unterricht unter Verwendung objektorientierter Datenstrukturen p561.pdf

Graphentheorie p422

Grotschel Graphen- und Netzwerkalgorithmen p218.pdf

Kaderali Graphen Algorithmen und Netze p478

@@@@@@@@@@@@@@@@@@@@@
fr
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Bondy Theorie des Graphes p706.pdf
13

okokok
Bretto éléments de théorie des graphes p380.pdf

??????????????????????????????????
Gournay Théorie des graphes p197
84

okokok
Régin Théorie des Graphes p302

>>>graph_theory

>>> graphtheory_math

>>>0trees

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>>>graph_vlsi

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hypergraphs
graph partitioning
graph drawing
graph and geometric thickness
grid graphs
planar embeddings
geometric graph theory
tree width

okokok
Ellis-Monaghan Graph Theoretical Problems in Next-Generation Chip Design p17

Freeman DUAL EULERIAN GRAPHS WITH APPLICATIONS TO VLSI DESIGN p177

???????????????????????
Galuzzi Graph Theory and Application Specific Processors p7
3

okokok
Gogoi Algorithm for Designing VLSI Floorplan using Planar Triangulated Graph p9

???????????????????????
Lin Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing p4
2

Lin TCG A Transitive Closure Graph-Based Representation for General Floorplans p12

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>>> zzzgraph4ic_research

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0graph_features

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000graph_file_formats

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okokok
Csardi igraph a package for network analysis p70

??????????????????????
Guduru GRAPH DATA CONVERSION AND TREE VISUALIZATION p60

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0graph_operations

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000graph_software_algorithms

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??????????????????????
Kepner Graph Algorithms in the Language of Linear Algebra p372

27

Bonato THE ROBOT CRAWLER GRAPH PROCESS p22
3

Faheem Adaptive Web Crawling Through Structure-Based Link Classification p13

Ntoulas Crawling and Searching the HiddenWeb p262

Pavalam A Survey of Web Crawler Algorithms p5

okokok
Walcott WebCrawling p17

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0graph_theory4webcrawling

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000graph_theory4webcrawling
>>> 000graph_theory4search_engines

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0openproblems

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>>> graphtheory_sciences

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Other Math

Graph theory has lots to do with other maths and sciences. Virtually all of them are related to graph theory development in some degree, therefore I cannot proceed with my graph theory studies without some kind of acquaintances with them. But I must be selective, therefore I have chosen some key desciples to focus on, mainly:

  • combinatorics
  • optimization
  • algebra
  • discrete math
  • number theory
  • numerical computing
  • functional
  • analysis etc

My Math Study Plan and Status

######################################
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Combinatorics
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okokok
Guichard An Introduction to Combinatorics and Graph Theory p153

okokok
Held Combinatorial Optimization in VLSI Design p65

Keller Applied Combinatorics p345
163

okokok
Korte Combinatorial Problems in Chip Design p37

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Schrijver A Course in Combinatorial Optimization p223

okokok
Szeszler Combinatorial Algorithms in VLSI Routing p78

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Optimization
@@@@@@@@@@@@@@@@@@@@@@@@@
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okokok
Pardalos Recent advances and trends in global optimization p106

######################################
Ant Colony Optimization
######################################

######################################
Artificial Intelligence
######################################

Hendler Foundations of Artificial Intelligence p1035
35

######################################
Combinatorial Optimization in VLSI Design
######################################

######################################
Evolutionary
######################################

######################################
Genetic Algorithms
######################################

okokok
Rajappa Solving Combinatorial Optimization Problems Using Genetic Algorithms and Ant Colony Optimization p105

######################################
Gravitational Attraction
######################################

######################################
Linear Programming
######################################

Vanderbei Linear Programming Foundations and Extensions p466
307

######################################
metaheuristics
######################################

######################################
Simulated Annealing
######################################

######################################
Swarm Intelligence
######################################

Kennedy Swarm intelligence p541
32

###########################################################
###########################################################
Operations Research / Operational Research / Operational Analysis
###########################################################
###########################################################

okokok
Commander Chapter 1 Introduction to Operations Research p11

CRAVEN OPERATIONS RESEARCH METHODS:RELATED PRODUCTION, DISTRIBUTION, AND INVENTORY MANAGEMENT APPLICATIONS p52

Fishburn Utility Theory for Decision Making p246

okokok
Geoffrion Prospects for Operations Research in the E-Business Era p31

HILLIER INTRODUCTION TO OPERATIONS RESEARCH p1237

okokok
Lubin Computing in Operations Research using Julia p25

Rasan INTRODUCTION TO OPERATIONS RESEARCH p359

okokok
Santini Operational Research Theory and Applications p100

okokok
Sottinen Operations Research with GNU Linear Programming Kit p201

STACHO Introduction to Operations Research Deterministic Models p121

Taha Operation Research p838

?????????????????????????????????
?????????????????????????????????
Topcu OPERATIONS RESEARCH LECTURE NOTES p101
9

van Hoeve Operations Research Techniques in Constraint Programming p166

van Hoeve Operations Research: Opportunities and Challenges p33

######################################
######################################
Algebra
######################################
######################################

Abstract Algebra: A First Course by Dan Saracino

Abstract Algebra by I. N. Herstein
Contemporary Abstract Algebra by Joseph Gallian
A First Course in Abstract Algebra by John Fraleigh
Abstract Algebra by John A. Beachy and William D. Blair
A Book of Abstract Algebra by Charles C. Pinter

okokok
Howlett An undergraduate course in Abstract Algebra p143

?????????????????????????
LaLonde Notes on Abstract Algebra p151
81

Moorhouse Abstract Algebra I p104.pdf
37

Wallace Beginning and Intermediate Algebra p489
27

######################################
Algebra - boolean, switch
######################################

okokok
Barnett Applications of Boolean Algebra:Claude Shannon and Circuit Design p18
Janet Heine Barnett

okokok
Edwards Fundamentals of Computer Systems Boolean Logic p72
Stephen A. Edwards

okokok
Holton Logic and Boolean algebra p55
Professor Derek Holton, University of Melbourne

okokok
Lebeck Basics of Logic Design:Boolean Algebra, Logic Gates p13
Alvin R. Lebeck

okokok???????????
MENDELSON THEORY AND PROBLEMS OF BOOLEAN ALGEBRA and SWITCHING CIRCUITS p221
BY
ELLIOTT MENDELSON, Ph.D.

okokok
Number System and Boolean Algebra and Switching functions p176

okokok
SQUIRES AN INTRODUCTION TO BOOLEAN ALGEBRA p21
R. J. SQUIRES

okokok
Wahlberg Boolean Algebra p13
kathleen.wahlberg

######################################

geometric algebra

######################################

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

geometric algebra

The tools of geometric algebra (10) provide a useful means of constructing pulse sequences for quantum logic operations from the permutation matrix (note that the systematic derivation of a pulse sequence in this manner is analogous to the work of Briand and Sorensen found in Refs. (19) and (20)). The method is based on the use of primitive idempotents.

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

permutation group

[Price1999]G:\studies\000VLSIChip\NGIPC\_quantum_gates

symmetric group of degree n

######################################
######################################
Tensor/Vector
######################################
######################################

Borisenko Vector and tensor analysis with applications p266

Brannon Functional and Structured Tensor Analysis for Engineers p323

A casual (intuition-based) introduction to vector and tensor analysis with
reviews of popular notations used in contemporary materials modeling
R. M. Brannon

???????????????????????????????????

Grinfeld Introduction to Tensor Analysis and the Calculus of Moving Surfaces p303

PavelGrinfeld

42

######################################
######################################
Probability
######################################
######################################

??????????????????????????????

Cameron Notes on Probability p94

47

######################################
######################################
ComplexityTheory
######################################
######################################

Arora Computational Complexity: A Modern Approach p489
Draft of a book: Dated January 2007
Comments welcome!
Sanjeev Arora and Boaz Barak
Princeton University
complexitybook@gmail.com

????????????????????????????

Aspnes Notes on Computational Complexity Theory p180
CPSC 468/568: Spring 2017
James Aspnes
2017-06-11 11:17

4

Goldreich Computational Complexity: A Conceptual Perspective p649

2006

Jones Computability and Complexity p485
From a Programming Perspective
Neil D. Jones

Trevisan Lecture Notes on Computational Complexity p171
Luca Trevisan
Notes written in Fall 2002, Revised May 2004

######################################
######################################
NumberTheory
######################################
######################################

Cameron A Course on Number Theory p139.pdf
77

okokok
Raji An Introductory Course in Elementary Number Theory p171.pdf

######################################
######################################
Cryptography
######################################
######################################

Goldwasser Lecture Notes on Cryptography p289.pdf
43

Paar Understanding Cryptography p382
76

&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
?????????????????????????????????
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
?????????????????????????????????
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
?????????????????????????????????
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
?????????????????????????????????

######################################
######################################
Numberical Analysis
######################################
######################################

Arnold A Concise Introduction to Numerical Analysis p211
50

???????????????????????????????
LeVeque Finite Difference Methods for Differential Equations p261
15

okokok
McDonough LECTURES IN BASIC COMPUTATIONAL NUMERICAL ANALYSIS p168.pdf

okokok
Young Introduction to Numerical Methods and Matlab Programming for Engineers p193

######################################
######################################
Differentials
######################################
######################################

okokok
Chasnov Introduction to Differential Equations p144

???????????????????
???????????????????
Edwards ELEMENTARY DIFFERENTIAL EQUATIONS p645
119

okokok
Evans Entropy and Partial Differential Equations p213

okokok
Ionascu Ordinary Differential Equations-Lecture Notes p112.pdf

???????????????????
Miersemann Partial Differential Equations Lecture Notes p205
26

okokok
Philip Ordinary Differential Equations p154

XXXXXXXXXXXXXXXX
Simon Differential Equations and Dynamical Systems p189

okokok
Tracy Lectures on Differential Equations p175

######################################
######################################
Discrete_Mathematics
######################################
######################################

okokok
Rosen_Discrete_Mathematics_and_Its_Applications_7th_Edition
12

######################################
######################################
Functional
######################################
######################################

Bass Functional analysis p182
27

######################################
######################################
mathematics for vlsi chip design
######################################
######################################

okokok
Abboud Mathematical methods for physical layout of printed circuit boards an overview p16

okokok
Abdallah Mathematical Model for Multiobjective Synthesis of NoC Architectures p6

okokok
Antoulas Mathematical challenges in VLSI chip design p83

okokok
EKANDARI S-visibility problem in VLSI chip design p16

okokok
Predicting Performance Mathematical Verification of Chips p2

Here below are current compilation of my math literature I am reading form time to time:

  • A text version
  • A html version

An earlier compilation of my math learning agenda dated February 12, 2017 can be found here:

Note: you have to change the page encoding to Chinese to enable correct view in your browser, as I have expereinced.


Untitled Document

Web and IT Technologies

since 1999-1-1

C:\ProgramData\Microsoft\Windows\Start Menu\Programs\StartUp

百度网盘加速

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>>>
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http://jingyan.baidu.com/article/fb48e8be5998136e622e14f5.html
http://pc.poppur.com/notebook/5626.html
http://blog.csdn.net/Rory898863935/article/details/76460883
https://baijiahao.baidu.com/s?id=1578184561327550085&wfr=spider&for=pc
http://jingyan.baidu.com/article/b2c186c8358659c46ff6ff52.html
http://tieba.baidu.com/p/4874816617
https://www.zhihu.com/question/28333225?sort=created
http://www.orsoon.com/news/190627.html
https://baijiahao.baidu.com/s?id=1565542794370555&wfr=spider&for=pc
http://yuan71058.blog.163.com/blog/static/33959508201701084455941
http://www.xiazaiba.com/jiaocheng/3832.html
http://pc.poppur.com/notebook/5626.html
http://blog.csdn.net/Rory898863935/article/details/76460883
http://www.zdfans.com/674.html
http://jingyan.baidu.com/article/90895e0f2f862364ec6b0be2.html
http://www.runningcheese.com/baiduyun
https://www.zhihu.com/question/54357084
https://zhidao.baidu.com/link?url=-31qrRjZ8_6u6s2A9oCK-bl-bYUKO9b2j6TnCq7QmtodGaJpXG7i1eeQRYFF1LxmARHsNJy4ka2V1PbZ9BRDvGqJ3UyB0CTiQpV8ygj6EkC
https://tieba.baidu.com/p/5195229475

ComputerOS

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@@@@@@@@@@@@@@@@@@@@@@@@@

win10删除文件很慢

@@@@@@@@@@@@@@@@@@@@@@@@@

windows下删除大量文件的快速方法
转载 2015年12月14日 22:21:55

专治删除MITK文件多而碎，普通右键删除慢的毛病：

来源：http://lovesoo.org/quickly-remove-large-quantities-of-windows-system-file-method.html

rmdir [drive:]path [/S] [/Q]

del [drive:]path [/S] [/Q]

/S 除目录本身外，还将删除指定目录下的所有子目录和文件

/Q 安静模式，删除时不需要确认

如删除 D:\test\目录下所有文件：
rmdir d:\test\ /S /Q

rmdir bin /S /Q

del d:\test\ /S /Q

推荐使用rmdir，比del效率更高。

干净启动的操作步骤如下：

1） 按“Win+R”打开“运行”窗口， 输入msconfig命令后按回车，弹出系统配置对话框。
2） 切换到“常规”标签页，单击“有选择的启动”，然后单击清除“加载启动项”上面的勾。
3） 切换到“服务”标签页，单击“隐藏所有Microsoft”服务，然后单击全部禁用。
4） 切换到“启动”标签页，点击“打开任务管理器”，点击启动项，然后单击禁用。
5） 单击确定保存后，重新启动系统。

希望以上的信息可以帮助到您。

我不是微软员工，也不在社区工作。
即使您不同意我的观点，也请保持开放和包容的心态参与讨论，并以达成共识为重。

1打开“控制面板”，选择“程序”。
?2.在“程序和功能”下选择“打开或关闭Windows功能”。

3.稍等片刻，出现“Windows功能”选项框，将里面的“远程差分压缩”选项的勾去掉，然后点“确定”，之后重启计算机即可提高文件复制奇慢的问题。

我发现在拷贝慢时，windows defender占用io比较高。

强行关闭后快了很多。

可能是其在扫描识别。

win10开始按钮没反应

步骤如下：

1、按下【windows+R】组合键打开运行，输入【services.msc】点击确定打开服务界面；

2、在右侧双击打开“user manager”服务，将“启动类型”修改为“自动”，点击【应用】—【启动】—【确定】即可。

===================================

方法很简单，一看就会具体如下：

1、右键点击任务栏，然后选择任务管理器或按快捷键Ctrl+Shift+Esc；

2、打开任务管理器后，切换到详细信息模式。在进程中找到“桌面窗口管理器”(英文版系统找Desktop Window Manager)，右键单击“结束任务”。这时会弹出提示窗口，勾选“放弃未保存的数据并关闭”，点击“关闭”。

3、结束进程后，正常情况下，桌面窗口管理器会自动重启，这时候开始菜单也恢复可用了；

4、如果桌面窗口管理器没有恢复，在任务管理器中点击“文件”——“运行新任务”，输入dwm回车即可。

当然还有一些情况是由于用户使用了内置管理员帐户，而没有对策略组进行设置引起，我们可以考参这篇文章来解决：http://www.xitonghe.com/jiaocheng/Windows10-1522.html

===================================

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dreamweaver 打开文件很慢

@@@@@@@@@@@@@@@@@@@@@@@@@

找到问题原因了，在首选参数-》代码提示中，关闭掉代码提示即可

@@@@@@@@@@@@@@@@@@@@@@@@@
将扫描的pdf文件转换成可编辑的文档>>>
@@@@@@@@@@@@@@@@@@@@@@@@@

如何将pdf扫描文件转换成文本文件

如何将扫描的pdf文件转换成可编辑的Word文档

如何将扫描版的pdf文件转成word文档

迅捷pdf转换成word转换器

迅捷PDF编辑器

捷速OCR文字识别软件

Adobe.Acrobat.X.Pro软件

载入该pdf文件后点击： 示图----工具----识别文本----在本文件中。 然后在弹出的对话框中可以设置识别的页面 及编辑是别的语言等项目然后点击确定。待识别结束后，就可复制识别后的文件中的所有内容了，可以将其导出为word文档，或者直接在空白word文档中复制粘贴。 如果待识别的扫描pdf文间是纯英文的文件，则直接点击： 文件----另存为----Microsoft Word 即可以直接识别导出word文档。

ABBYY Finereader

CAJViewer

CAJ浏览器

PDFelement

互盾PDF转换器

尚书OCR软件

清华文通

慧视小灵鼠

汉王文豪

汉王OCR

汉王PDF OCR文字识别软件

蒙怡OCR

丹青OCR

@@@@@@@@@@@@@@@@@@@@@@@@@

如何批量word 转 pdf

@@@@@@@@@@@@@@@@@@@@@@@@@

http://saccohuo.com/several-ways-to-batch-convert-office-documents-to-pdf.html

https://forums.adobe.com/message/7178612#7178612

https://forums.adobe.com/thread/306137

http://www.docufreezer.com/download

DocuFreezer(推荐)

免费版和企业版。免费版个人使用完全免费，但是会在每一页 PDF 下面打上水印，没找到破解版。企业版价格 $19 还可以接受。

Product Overview – DocuFreezer
帖子中的朋友推荐的这个神器

Adobe Acrobat 直接导入（推荐）

具体步骤：

打开 Adobe Acrobat Pro。点击 文件>创建>批量创建多个文件 。

[打开文件]

打开文件

Figure 1: Acrobat 内置文件转换－打开文件
会弹出一个对话框，用来添加待转换的文件。点击 添加文件>添加文件/添加文件夹 ，可以选择直接添加若干个文件还是直接选择整个文件夹，然后点击确定。

[添加文件]

添加文件

Figure 2: Acrobat 内置文件转换－添加文件
会弹出另外一个对话框，可以设置目标文件夹和文件命名方式，并选择是否覆盖重名文件。然后点击确定即可开始转换，现在可以在设置的文件夹中找到相应 PDF 文件。

[输出选项]

输出选项

Figure 3: Acrobat 内置文件转换－输出选项
参考：直接使用 Acrobat 自带的方法快速转换

TODO 修改系统打印机中的 Adobe 虚拟打印机（不推荐）

修改本机的打印机中的 Adobe 虚拟打印机的设置。具体操作可以看下面的链接。

修改本机的 Adobe 虚拟打印机设置 and 需要做的额外设置 （这样可以在文件上面批量右键生成 PDF，但是实测经常失败，因为 Adobe Elements.exe 的不明原因停止响应，这种方法不推荐）
How to batch convert office files like doc to pdf? |Adobe Community

TODO Adobe Acrobat Pro 创建 Action

Acrobat Actions Exchange - Adobe Acrobat
Batch processing metadata in Adobe Acrobat XI Pro |Adobe Community
添加 Action and 在 Action 添加一个 Save 命令来实现 （但是每个文件转换完成后打开下一个文件时会 prompt 你是否保存前一个文件（虽然保存不保存都可以，但是一定会弹窗，比较烦，下文有解决办法））
详细介绍使用 Action 方法实现的过程 （额外打开了“优化PDF”的设置，从而消除了 prompt）

Batch Word to PDF 和 Batch PPT to PDF

每个格式都需要一个转换器，有点麻烦。但是效果比较好，操作方便。 我也找到了比较常用的 Word 和 PPT 转换成 PDF 可用的破解版，在 Dropbox 也共享了出来。

官网：Home - Batchwork? Software
doc2pdf 破解版下载：https://www.dropbox.com/s/69tlvsfx40hpqgp/doc2pdf.exe?dl=0
ppt2pdf 破解版下载：https://www.dropbox.com/s/9b384m2u22k290x/ppt2pdf.exe?dl=0

其他方法

文电通 PDF 转换器 4 和 文电通 PDF 套装版

转换效果不错，而且不需要其他虚拟打印或者 Office 软件作为辅助。安装文件很大（200+M），试用期 30天，购买625元/用户（这价格平民完全买不起，只能找破解版，我没花时间去找，有兴趣可以自己找）。
快刀 Office 批量打印和转 PDF（KDOffice2PDF）

未做测试，没发现绿色版，只找到安装版。
PDF 批量打印工具 PDF Batch Print v1.0 免费版

未做测试。
霄鹞 PDF 文件转换大师 V1.0

软件功能实现的还可以，但是交互性不怎么样，免费版每次只能操作3个文件，收费版每台机器终身45元，定价与软件本身价值很不符，很不值。
Office 打印精灵

无法安装（Win 7 x64）。
SETE 批量打印

效果差，操作麻烦，设置冗余。
BatchOutput Office Suite

Mac 上的 office 批量转 pdf，但是没有 Windows 版。

参考

Convert multiple files (word docs) to multiple pdf |Adobe Community
Batch processing metadata in Adobe Acrobat XI Pro |Adobe Community （看了这个帖子才知道 Acrobat XI 版本里面的 "command" 改成 "Action" 了，难怪找了半天找不到）

# Original # pdf # office # convertion # batch # 批量转换 # file-handling # 文件处理
交叉极化隔离度与交叉极化鉴别率
texlive 2016 被 eu1lmr.fd 卡得像死机一样的解决方案

https://www.douban.com/note/374518671/

pdfcreator

http://www.topdf.de/

@@@@@@@@@@@@@@@@@@@@@@@@@

如何批量word 转 pdf

@@@@@@@@@@@@@@@@@@@@@@@@@

从pdf 文件复制的python代码无法保留缩进格式

从pdf 文件复制的代码格式打乱

从pdf 文件复制的代码缩进消失了

PDF中的代码在复制时无法正确处理缩进

代码本身在PDF中可以正常显示，但复制代码时，所有缩进都丢失

如何将一个PDF文件拆分为几个

https://jingyan.baidu.com/article/ae97a6468f4983bbfd461dff.html

indentation disappeared after copying from pdf file

pythontidy

How Can I Copy Text from a PDF while Preserving the Formatting?

https://www.howtogeek.com/136698/how-can-i-copy-text-from-a-pdf-while-preserving-the-formatting/

The standard solution to your kind of problem is to use Adobe Acrobat Professional (the expensive one, not the free reader) to convert the PDF to HTML. Even that is not going to get perfect results.

How to make listings code indentation remain unchanged when copied from PDF?

Copy code from PDF to text file while Preserving the Formatting

this site is ok !!!!!!!!!!!!!!

http://www.sejda.com/extract-text-from-pdf

@@@@@@@@@@@@@@@@@@@@@@@@@

chm电子书转换html格式的方法??

@@@@@@@@@@@@@@@@@@@@@@@@@

hh -decompile [html保存路径] [chm文件]?
例如 hh -decompile d:\天龙八部.chm?
可以用批处理让这个反编译的操作更加简单。批处理程序如下：?

复制代码
代码如下:

@echo off?
title CHM电子书反编器BAT版?
color a?
echo.?
set /p urlfile=请把要反编的CHM电子书拖进来(再按回车键)：?
copy %urlfile% chmfile.chm > nul?
hh -decompile .\CHM chmfile.chm?
rem del /q chmfile.chm > nul 可以将这句话前面的rem去掉，去掉后反编译成功后则删除chm源文件。?
echo.?
echo 反编文件成功。保存在.\CHM文件夹中，按任意键退出！?
rem pause > nul?
exit?

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Hardware >>>
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LinuxKernel >>>
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the Linux kernel(over seven million lines of code)

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WindowsAPI
@@@@@@@@@@@@@@@@@@@@@@@@@

http://winprog.org/tutorial/message_loop.html

https://www.modula2.org/win32tutor/references.php

>>> APIView >>> 正隆API查看器.exe

Internet

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网络通信工具

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网络通信工具 >>>
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Multimedia

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Multimedia >>>
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VRML

JPEG

MPEG

3dlinks.com

3dml

3DML

3DXML

COLLADA

Direct3D

directX

Flash / Flex

H264

java3d? / Java FX

JOAL, a Java binding for a 3D audio API called OpenAL

JMF: Java Media Framework????

O3D

Opengl

http://www.opengl.org/

(Microsoft) Silverlight

Synchronized Multimedia Integration Language (SMIL)

SVG?

U3D

X3D-Edit for Extensible 3D (X3D) Graphics

X3D, VRML


cracking

Web and IT Technologies

Software Reverse Engineering

since 2015-10

Software Reverse Engineering

Software cracking

http://www.ollydbg.de/

http://www.pediy.com/

https://tools.pediy.com/

www.Tuts4You.com

http://www.accessroot.com/

http://ricardonarvaja.info/

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
软件破解技术
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

?????????????????????????????????????

?????????????????????????????????????

>>>000ARTeam脱壳教程全集>>>

http://www.accessroot.com/

https://www.52pojie.cn/thread-640642-1-1.html

https://bbs.pediy.com/thread-189555.htm

网盘地址如下: http://pan.baidu.com/s/1sjCZLP7 密码: cpl1

有分的捧个分 没分的回复下也是爱啊 密码：pediy

>>>H:\0000Cracking\tutorials\000ARTeam脱壳教程全集

okokok

ASProtect (Analysis of Hardware Breakpoint Clearing)

ASProtect_HW_BP_detection_1

okokok

ASProtect 1.22-1.32 (Unpacking)

okokok

ASProtect 1.23 RC1 (Unpacking)

okokok

ASProtect 1.31 (Unpacking)

okokok

ASProtect 2.0 (Stolen Bytes) ES

okokok

ASProtect 2.0x (Unpacking & Rebuilding IAT)

okokok

ASProtect 2.1x (Advanced Import Protection)

?????????????????????????

ASProtect 2.3 SKE (Bypass HardwareID Lock)

?????????????????????????

ASProtect 2.3 SKE (Virtual Memory Analysis)

?????????????????????????

ASProtect 2.4 SKE (OEP + Advanced Import Protection)

?????????????????????????

ASProtect 2.4 SKE (Stolen OEP)

?????????????????????????

ASProtect 2.13 (Unpacking + All Protections)

?????????????????????????

ASProtect 2.xx (Attack on Activation Key)

?????????????????????????

ASProtect 2.xx (IAT Rebuilding + Stolen Code)

?????????????????????????????????????

ASProtect 2.xx (Unpacking + All Protections)

ASProtect 2.xx eng p60

?????????????????????????

ASProtect SKE 2.3 (OEP + Redirected Imports)

?????????????????????????

ASProtect SKE Unpacking Approach

ASProtect 2.1x SKE

?????????????????????????????????????

?????????????????????????????????????

okokok

>>> 000cxj98 软件加密与解密技术精华合集 2015.08

？？？？？？？？？？？？？？？？？

》》》 算法分析篇

BeyondMe 精华帖

简单搞定Flash Player Pro 3.65

脱壳
? ?? ??? 我们首先来讲如何脱壳。
? ?? ??? 这里给大家三种比较好的方法。
? ?? ??? 第一种，直接使用UPX Shell脱壳。此种方法直接，快速，不会错（暂且假设作为新手的你是不会接受这种虽投机取巧但又是效果最好的方法的）。
? ?? ??? 第二种通过ESP平衡原理，PUSHAD执行后对ESP指向的内存位置下断。F9，直接就能找到OEP。
? ?? ??? 第三种方法是手动查找OEP中最简单的，Ctrl+F，输入popad。根据popod出现在内存中的位置找到OEP。
? ?? ??? 网上关于UPX的壳脱法很多，个人感觉虽能找到，不过难度也可以跟单步跟踪相媲美了小甲鱼虽然告诉我们OD可以自动帮我们脱壳，但如果自动脱壳，那么就不如直接使用第一种方法了。因此还是用我们的手动脱壳吧。

? ?? ??? 已脱壳33%......

? ?? ??? 如果你已经找到了OEP，那么你成功了？嗯，大概成功了1/3。在DUMP时我们遇到了问题，要不要选择重建输入表呢？
? ?? ??? 对于这个程序，我们有两种选择，直接重建输入表。或者选择不重建输入表，然后用LordPE中的RebuildPE修复。这两种方法有什么区别呢？ 重建输入表是在现有程序中加一个新的Section存放输入表。而RebuildPE则是在被破坏的输入表上修复，不会产生新的Section。因此就是 说RebuildPE后的文件体积要小一些，于是我们选择RebuildPE方式。
? ?? ??? 可以看到以前的程序被变成了UPX0和UPX1两个Section。我们是否可以删除掉程序中多余的SFX代码呢？如果我们没有用UPX Shell，这个就相当难，因为UPX将以前的Section都合并到了一起。没法通过删除Section的方式删除SFX代码。通过对比可以发现脱壳前 和脱壳后UPX1的大小没变，是不是说明UPX1存放的就是解压代码。但是此时并不能去掉UPX1，研究后是因为UPX0中的API调用需要用到UPX1 中的数据。至此，我们就暂且认为已经脱完了。

? ?? ??? 已脱壳70%......

? ?? ??? 还没有脱成功吗？程序已经可以打开了，但是我们直接通过OD得不到什么有用的信息。没有了MessageBox，而且查找参考字符串虽然可用，但是代码实在太长了。我们想到了程序脱壳以后是个Delphi程序。如此的话，Dede登场！
? ?? ??? 无奈，Dede没法打开。原因是这个程序可能被压缩了。我们不是都已经脱壳了吗？怎么还会有被压缩的东西？其实我们遗忘了资源文件。UPX这种压缩 壳怎么会放过资源文件。不过这里就有疑问了，我们脱壳成功了，那么资源文件也应该是dump出来的是解压后的版本。有何有解压一说？这里我也没有相同，想 必是水平还不够，暂时留作我们的疑问。我们暂且使用FreeRes将压缩的资源释放出来。这样Dede就可以识别了。

>>>000Feng 从零开始学破解

01初识破解.pdf

02初探暴力破解.pdf

03功能限制初探破除.pdf

04功能限制去除灰色按钮.pdf

05破解知识盘点断点.pdf

07标志位爆破.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

08壳之初体验.pdf

09PEID.pdf

10加密壳.pdf

11工具脱壳.pdf

12OD初级.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

13OD进阶.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

14手动脱壳.pdf- 单步跟踪法与内存断点法 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

15手动脱壳进阶.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

17神秘的注册码.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

18重启验证.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

19自校验.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

20SMC破解.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

21把软件变成注册机.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

22内存补丁.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

23牢牢抓住注册码.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

24做注册机.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

25隐藏的字符串.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

函数API

26自杀代码.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

27万能断点.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

F3:A5 rep movs dword ptr es:[edi], dword p>

win10 万能断点

28消灭软件中的广告.PDF- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!okokok

29VB程序.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!okokok

30附加数据.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!okokok

31IAT修复.pdf- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! okokok

?????????????????????????????????????

?????????????????????????????????????

>>>000Lena151Files>>>

G:\5hobby\000hacking\Cracking\ZZZHtml

XXXXXXXXXXXXXXXXXXXXXXXX
G:\studies\00hacking\Cracking\000Lena151Files\snd-reversingwithlena-tutorials\
difficult to follow

okokok

snd-reversingwithlena-tutorial01.tutorial

use of plugins

okokok

snd-reversingwithlena-tutorial02.tutorial

okokok
snd-reversingwithlena-tutorial03.tutorial

killing nags

okokok
snd-reversingwithlena-tutorial04.tutorial

okokok
snd-reversingwithlena-tutorial05.tutorial

looking for places to patch

????????????????????

okokok
snd-reversingwithlena-tutorial06.tutorial

basic patching

okokok
snd-reversingwithlena-tutorial07.tutorial

okokok
snd-reversingwithlena-tutorial08.tutorial

okokok
snd-reversingwithlena-tutorial09.tutorial

VB

okokok
snd-reversingwithlena-tutorial10.tutorial

VB

okokok
snd-reversingwithlena-tutorial11.tutorial

pane window

okokok
snd-reversingwithlena-tutorial12.tutorial

multiple patching

okokok
snd-reversingwithlena-tutorial13.tutorial

okokok
snd-reversingwithlena-tutorial14.tutorial

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!

snd-reversingwithlena-tutorial15.tutorial

inline patching using a variable pointer

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!
snd-reversingwithlena-tutorial16.tutorial

using progam's resource for reversing

okokok
snd-reversingwithlena-tutorial17.tutorial

keygen

okokok
snd-reversingwithlena-tutorial18.tutorial

diversion code, encryption/decryption, selfmodyfying code, polymorphism

okokok
snd-reversingwithlena-tutorial19.tutorial

anti antidebugging

??????????????????????????????????

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!

okokok
snd-reversingwithlena-tutorial20.tutorial

unpacking

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!

okokok
snd-reversingwithlena-tutorial21.tutorial

unpacking and rebuiding imports IAT

25%

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!

okokok
snd-reversingwithlena-tutorial22.tutorial

unpacking , rebuiding imports IAT , api redirection

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!

okokok
snd-reversingwithlena-tutorial23.tutorial

unpacking , rebuiding imports IAT , stolen bytes

okokok
snd-reversingwithlena-tutorial24.tutorial

runtime patching + protectors

okokok
snd-reversingwithlena-tutorial25.tutorial

runtime patching + protectors armadillo

okokok
snd-reversingwithlena-tutorial26.tutorial

runtime patching + protectors armadillo

okokok
snd-reversingwithlena-tutorial27.tutorial

adv. patching + protectors

okokok
snd-reversingwithlena-tutorial28.tutorial

server checks

okokok
snd-reversingwithlena-tutorial29.tutorial

server checks + packers/protectors

okokok
snd-reversingwithlena-tutorial30.tutorial

packers/protectors + SFX/Run trace of OD

okokok!!!!!!!!!!!!!!!!!!!!!!!!!!!

snd-reversingwithlena-tutorial31.tutorial

delphi using dede

okokok
snd-reversingwithlena-tutorial32.tutorial

packer, dede

okokok
snd-reversingwithlena-tutorial33.tutorial

FPU

snd-reversingwithlena-tutorial34.tutorial

compressed without packing

okokok

snd-reversingwithlena-tutorial35.tutorial

inline compressed, polymorphic

okokok

snd-reversingwithlena-tutorial36.tutorial

keygen

okokok

snd-reversingwithlena-tutorial37.tutorial

unpacking

okokok

snd-reversingwithlena-tutorial38.tutorial

malware debugging

okokok

snd-reversingwithlena-tutorial39.tutorial

dll, inline patching, unpacking, crc,

okokok ???????????????????? ↑

snd-reversingwithlena-tutorial40.tutorial
obfuscation

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?????????????????????????????????????

>>>000Narvaja Introduction to Cracking with OllyDbg from Scratch PDF EN

http://ricardonarvaja.info/

https://foro.elhacker.net/ingenieria_inversa/curso_completisimo_de_cracking_herramientas_para_practicar_de_ricardo_narvaja-t373318.0.html

http://appnee.com/only-best-and-comprehensive-ollydbg-tutorial-in-chm-hd-pdf-and-doc/

G:\studies\000Webit\0000Cracking\000Narvaja Introduction to Cracking with OllyDbg from Scratch PDF EN\AppNee.com.Introduction.to.Cracking.with.OllyDbg.from.Scratch.PDF.EN\Ricardo_tuts_1-42

INTRODUCTION TO CRACKING WITH OLLY 16 ?????????????????????

?????????????????????????????????????

NarvajaPediy 使用OllyDbg从零开始Cracking.CHM

第一章-OD的各个窗口介绍

第二章-数值系统

第三章-寄存器

第4章-汇编指令

第5章-数学指令

第六章-比较和条件跳转

第七章-call和ret

第八章-循环_字符串指令和寻址方式

第九章-基本概念

第十章-断点

第十一章:硬件断点与条件断点

第十二章

消息断点

Understanding the Message Loop

http://winprog.org/tutorial/message_loop.html

https://bbs.pediy.com/thread-207265.htm

第十三章-硬编码序列号寻踪-Part1 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

第十四章-硬编码序列号寻踪-Part2 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

第十五章-硬编码序列号寻踪-Part3- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

第十六章-序列号生成算法分析-Part1 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

第十七章-序列号生成算法分析-Part2 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

第十八章-序列号生成算法分析-Part3 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

第十九章-OllyDbg反调试之IsDebuggerPresent

第二十章-OllyDbg反调试之检测OD进程名?????????????????

第二十一章-OllyDbg反调试之检测OD进程名,窗口类名,窗口标题名

第二十二章-OllyDbg反调试之UnhandledExceptionFilter,ZwQueryInformationProcess

第二十三章-OllyDbg反调试之ProcessHeap,NTGlobalFlag,OutputDebugStringA

第二十四章-OllyDbg反调试之综合练习

第二十五章-异常处理

第二十六章-Visual Basic程序的破解-Part1

第二十七章-Visual Basic程序的破解-Part2

第二十八章-Visual Basic程序的破解-Part3

第二十九章-P-CODE-Part1

第三十章-P-CODE-Part2

第三十一章-脱壳简介

第三十二章-OEP寻踪

第三十三章-神马是IAT,如何修复

第三十四章-手脱UPX,修复IAT

第三十五章-手脱ASPack V2.12

第三十六章-IAT重定向

第三十七章-论IAT重定向之修复

第三十八章-手脱Yoda's Crypter v1.3

第三十九章-何谓stolen bytes

第四十章-OllyDbg脚本的编写

第四十一章-神马是AntiDump

第四十二章-ACProtect V1.09脱壳(寻找OEP,绕过硬件断点的检测,修复Stolen code)

第四十三章-ACProtect V1.09脱壳(编写脚本修复IAT)

第四十四章-ACProtect V1.09脱壳(修复AntiDump)

第四十五章-ReCrypt v0.80脱壳

第四十五章(补充章节)-ReCrypt v0.80脱壳(续)

第四十六章-Patrick的CrackMe-Part1

第四十七章-Patrick的CrackMe-Part2

第四十八章-PeSpin V1.3.04脱壳-Part1

第四十九章-PeSpin V1.3.04脱壳-Part2

第五十章-再谈ReCrypt v.0.80脱壳(调戏OutputDebugString)

okokok

第五十一章-ASProtect v2.3.04.26脱壳-Part1

okokok

第五十二章-ASProtect v2.3.04.26脱壳-Part2

第五十三章-TPPpack脱壳

第五十四章-EXECryptor v2.2.50.a脱壳-Part1

第五十五章-EXECryptor v2.2.50.a脱壳-Part2

第五十六章-EXECryptor v2.2.50.b脱壳

第五十七章-EXECryptor v2.2.50.c.d.e.f.g脱壳

第五十八章-EXECryptor v2.2.50.h脱壳

?????????????????????????????????????

?????????????????????????????????????

ZerBon Email Spider

>>>R4ndom逆向系列教程>>>

RadAsm指南>>>

二进制代码DIY的艺术>>>

其他教程>>>

软件逆向工程入门教程>>>

www.Tuts4You.com

http://thelegendofrandom.com

dede 开始处理 出现 access violation

okokok

R4ndom_tutorial_1

Tutorial #1 : What is Reverse Engineering

R4ndom_tutorial_2

Tutorial #2 : Intro To Olly Debug

R4ndom_tutorial_3

Tutorial #3_ Using OllyDBG_Part 1

R4ndom_tutorial_4

Tutorial #4: Using Olly, Part 2

R4ndom_tutorial_5

Tutorial #5: Our First (Sort Of) Crack

R4ndom_tutorial_6

Tutorial #6: Our First (True) Crack

okokok

R4ndom_tutorial_7

Tutorial #7: More Crackmes

R4ndom_tutorial_8

Tutorial #8: Frame Of Reference

okokok

R4ndom_tutorial_9

R4ndom’s Tutorial #9: No Strings Attached

R4ndom_tutorial_10

R4ndom’s Tutorial #10: The Levels Of Patching

R4ndom_tutorial_11

R4ndom’s Tutorial #11: Breaking In Our Noob Skills

R4ndom_tutorial_12

R4ndom’s Tutorial #12: A Tougher NOOBy Example

R4ndom_tutorial_13

R4ndom’s Tutorial #13: Cracking a Real Program

R4ndom_tutorial_14

R4ndom’s Tutorial #14: NAGS (And I don’t Mean Your Mother)

okokok

R4ndom’s Tutorial #15: Using The Call Stack
push 8f

If the resource was identified by an id instead of a name, we could find it by right-clicking the disassembly
window and selecting “Search for”->”Command”. Then enter into the box ‘PUSH xx” where xx is the ID (in
hex) of the resource. This will take you to the call to the dialog box as well.

okokok

R4ndom_tutorial_16a

R4ndom’s Tutorial #16A: Dealing With Windows Messages

R4ndom_tutorial_16b

R4ndom’s Tutorial #16B: Self Modifying Code

R4ndom_tutorial_16c

R4ndom’s Tutorial #16C: Bruteforcing

okokok

R4ndom_tutorial_17

R4ndom’s Tutorial #17: Working With Delphi Binaries

R4ndom_tutorial_18

R4ndom’s Tutorial #18: Time Trials and Memory Breakpoints

R4ndom_tutorial_19

R4ndom_tutorial_20A

R4ndom’s Tutorial #20B: Working With Visual Basic Binaries, Pt 1

R4ndom_tutorial_20B

R4ndom’s Tutorial #20B: Working With Visual Basic Binaries, Pt 2

R4ndom_tutorial_21

R4ndom’s Tutorial #21: Anti-Debugging Techniques

R4ndom_tutorial_22

R4ndom’s Tutorial #22: Code Caves

okokok

R4ndom_tutorial_23

R4ndom’s Tutorial #23: TLS Callbacks

Call stack of main thread, item 27
Address=0014BE58
Stack=0000040F
Procedure / arguments= age = Notify = MENU/BN_CLICKED... ID = 1039

>>>000Shark恒零基础破解图文教程

?????????????????????????????????????

?????????????????????????????????????

??????????????????????????
okokok
Shark恒零基础破解图文教程电子书（28课全，含附件）

S01E01

S01E02

S01E03

S01E04

S01E05

S01E06

S01E07 ESP 定律 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

S01E08

S01E09

S01E10

S02E01 深入爆破- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

S02E02

S02E03

S02E04

S02E05

S02E06 深入注册码- 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

S02E07 捕风捉影 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

S02E08

S02E09

S02E10

S03E01

S03E02 多处调用 - 很重要 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

S03E03

S03E04

S03E05

S03E06

S03E07

S03E08

>>>ODbgScript

okokok

ODbgScript1831forOD110

>>>OllyDbg帮助

OLLYDBG

OKOKOK
ccdebuger OllyDBG教程.pdf

OKOKOK

OllyDbg 2.0 Brief Help

OKOKOK
OllyDbg入门完全教程.pdf

?????????????????????????????????????

?????????????????????????????????????

>>>ZZZHtml
谈谈字符串那点事

>>>ZZZPDF

okokok

Dang Practical Reverse Engineering p383

okokok

Eagle Reverse Engineering with Ida Pro p282
Chris Eagle

okokok

Eilam Reversing: Secrets of Reverse Engineering p620

Eldad Eilam

okokok

Fotopoulos Reverse Engineering p119

OKOKOK
Pediy看雪 OLLyDbg动态调试技术

okokok

Perry Introduction To Software Reverse Engineering p110

okokok

Romanski Reverse Engineering for Software and Digital Systems p120

DOT/FAA/TC-15/27
Federal Aviation Administration
William J. Hughes Technical Center
Aviation Research Division
Atlantic City International Airport
New Jersey 08405
February

George Romanski1, Mike DeWalt2 for phase 1 – research, and Dewi Daniels3for phase 2 – Validation.

OKOKOK
Sabanal reverse c++.pdf

OKOKOK

Telea REVERSE ENGINEERING – RECENT ADVANCES AND APPLICATIONS p290
Edited by Alexandru C. Telea


cracking

Web and IT Technologies

Software Reverse Engineering

since 2015-10

Software Reverse Engineering

Software cracking

http://www.ollydbg.de/

http://www.pediy.com/

https://tools.pediy.com/

www.Tuts4You.com

http://www.accessroot.com/

http://ricardonarvaja.info/

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
软件破解技术
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

od f9 后 就出现 terminated
OD显示跳转来源??????????????????????????
Ctrl+A.
是在od选项——调试设置——CPU——显示路径

OD断点不起作用
OD 设的断点不起作用
选项->调试设置->安全
载入模块相关信息时
忽略 路径与扩展名
忽略时间标志
忽略代码段的CRC校验
全部勾选上。

载入 - 工具 - strong OD - Options - skip some exceptions的钩去掉 然后 options - 把异常里面的钩都去掉 保存 运行起来下断（我不知道是不是因为程序是崩溃的 如果是 就这样来做）

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

?????????????????????????

000Cracking2脱壳

常用脱壳方法

1 单步跟踪法

（1）用OD载入，点“不分析代码”

（2）.单步向下跟踪F8，实现向下的跳。也就是说向上的跳不让其实现（通过F4）

（3）遇到程序往回跳的（包括循环），我们在下一句代码处按F4（或者右健单击代码，选??????????????????? ?择断点——>运行到所选）

（4）绿色线条表示跳转没实现，不用理会，红色线条表示跳转已经实现

（5）如果刚载入程序，在附近就有一个CALL的，我们就F7跟进去，不然程序很容易跑? 飞，这样很快就能到程序的OEP

（6）在跟踪的时候，如果运行到某个CALL程序就运行的，就在这个CALL中F7进入

（7）一般有很大的跳转（大跨段），比如 jmp XXXXXX 或者 JE XXXXXX 或者有RETN? 的一般很快就会到程序的OEP

注：在有些壳无法向下跟踪的时候，我们可以在附近找到没有实现的大跳转，右键-->“跟随”,然后F2下断，Shift+F9运行停在“跟随”的位置，再取消断点，继续F8单步跟踪。一般情况下可以轻松到达OEP

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实战"单步跟踪法"脱壳?

http://www.aiuxian.com/article/p-211077.html

背景

破解的第一步是判断所要破解的程序是否加壳了，如果程序加壳了，需要将壳脱掉再来破解，所以脱壳是破解的第一步

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实战

1 查壳

用PEID等查壳工具查看所需要破解的程序是否加壳了，加的什么壳。PEID的工作原理大家看看PEID目录下的userdb.txt文件就知道了，PEID通过壳的入口特征码进行辨认程序是加了什么壳

用PEID查壳的结果如下图，可以看出程序加了ASPack2.12的壳

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2 寻找OEP

(1)用OD载入该程序

?（2）使用F8单步补过，在靠近入口处的第一个call（call 0040D00A）使用F7单步步入，? 在call子程序中使用F8单步补过，没有发现有用的信息，在靠近入口的第二个call（call?? 0040D014使用F7单步步入，否则程序会跑飞，下图是刚进入第二个call处的截图

?（3）根据"单步跟踪法"中的原则，一步一步调试，遇到向上跳转，则将鼠标点到该跳转的下一行，然后F4运行到这一行（如果让程序向上跳转，则可能程序往反方向跳转，无休无止，也就找不到OEP），向下跳转则不用处理，需要注意的是绿色线条表示跳转没实现，不用理会，红色线条表示跳转已经实现，在下面的注释窗口会有该提示，下图就是一个没有实现的跳转

?（4）按照步骤（3）中的方式执行很快就会看到下图现象，出现了popad这条指令，然后? push 004010CC，将004010CC这个地址入栈，后面紧跟着一个retn，程序就会返回到? 004010CC这个地址继续执行程序，004010CC与当前地址0040D3BF之间有个很大的跳转，由此可以判断马上将到达程序的OEP，

?（5）在retn上在按下F8单步步过即可到达OEP（OEP地址004010CC）

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3 脱壳（Dump）

（1）在OEP（OEP地址004010CC）处使用OD插件脱壳，在004010CC上点击鼠标右键，? 选择该菜单下的Dump debugged process，会弹出如下对话框，从下图最底Rebuild?? Import选项下可以看出该插件提供了两种脱壳方式

?（2）分别用Method1和Method2脱壳，点击Dump按钮然后选择文件的保存位置即可脱壳

?（3）当然也可以用LordPE来脱壳，选中要脱壳的进程notepad.exe，因为使用OD加载的时候已经启动该进程

?（4）在该进程上右键，选择该菜单下的修正镜像大小，结果如下图

?（5）在该进程上右键，选择该菜单下的完整转存（也有的翻译是完全脱壳），会弹出文件保? 存位置对话框，填好文件名称后保存即可，成功后会弹出如下对话框

?（6）再次用PEID检测unpack1.exe、unpack2.exe、unpack3.exe，会发现程序已经是无壳的

?（7）分别打开已经脱壳完成的unpack1.exe、unpack2.exe、unpack3.exe，会发现unpack3.exe运行后出现如下错误，则在该种情况下需要修复资源

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4 修复

（1）使用到的修复工具是ImportFix，打开ImportFix，打开notepad.exe这个进程，因为用OD载入加壳程序notepad.exe后，会产生notepad.exe这个进程（此时需要OD中将程序调试运行到OEP处，即004010CC处，否则在下面的自动查找IAT会失败）

?（2）将OEP那一栏修改成刚才在OD中找到的OEP地址000010CC，然后点击自动查找? IAT，则RVA和大小这一栏中数据会改变 ?

（3）点击确定后，点击获取输入表按钮，结果如下图，其中找到的输入表函数里面的函数? 是程序运行需要的一些系统API

?（4）点击显示无效函数后，发现没有，在点击修复转存文件按钮，选择要修复的unpack3.exe? 文件

?（5）完成后会在记录这一列表框中显示结果，修复后的文件保存名字为unpack3_.exe

?（6）打开unpack3_.exe，发现程序能正常运行，则修复成功

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2 ESP定律法

?ESP定理脱壳（ESP在OD的寄存器中，我们只要在命令行下ESP的硬件访问断点，就会一下来到程序的OEP了！）

（1）开始就点F8，注意观察OD右上角的寄存器中ESP有没突现（变成红色）（这只是一? 般情况下，更确切的说我们选择的ESP值是关键句之后的第一个ESP值）

（2）在命令行下：dd XXXXXXXX(指在当前代码中的ESP地址，或者是hr XXXXXXXX)，? 按回车

（3）选中下断的地址，断点--->硬件访--->WORD断点

（4）按一下F9运行程序，直接来到了跳转处，按下F8，到达程序OEP

?

实战"ESP定律法"脱壳?

http://www.aiuxian.com/article/p-211078.html

实战

1 查壳

用PEID查壳的结果如下图，可以看出程序加了ASPack2.12的壳

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2 寻找OEP

(1)用OD载入该程序

?（2）按下F8单步步过，发现ESP此时是红色，记下此时ESP寄存器中的值0012FF6C（载入程序处的下一个ESP是红色，当然每个人机器上运行这个值有可能不同）
0014FF80

（3）在命令行下输入dd 0012FF6C，然后按下回车键 ?

（4）选中要下断点的0012FF6C那行，依次选择断点 -> 硬件访问 -> Word?

(5) 在菜单栏调试（D）下的硬件断点（H）下选项下可以看到我们设置的硬件断点 ?

（6）然后按下F9运行程序，运行到程序停止 ?

（7）删除前面下的硬件断点，选择调试（D）下的硬件断点（H），弹出如下对话框，点击? 删除1按钮删除前面下的硬件断点 ?

（8）运用F8很快会到达程序的OEP（此时需要使用F8单步步过）
7760F804

3 脱壳

可以使用OD自带插件，也可以用LordPE，方法和前面"单步跟踪法"中使用方法一样

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4 修复

可以使用ImportFix，方法和前面"单步跟踪法"中使用方法一样

3内存镜像法

（1）用OD打开软件

（2）点击选项——调试选项——异常，把里面的忽略全部√上。CTRL+F2重载下程序

（3）按ALT+M,打开内存镜象，找到程序的第一个.rsrc.按F2下断点，然后按SHIFT+F9运? 行到断点，接着再按ALT+M,打开内存镜象，找到程序的第一个.rsrc.上面的.CODE（也? 就是00401000处），按F2下断点。然后按SHIFT+F9（或者是在没异常情况下按F9），? 直接到达程序OEP

内存镜像E法的步骤

用OD打开软件

点击选项——调试选项——异常，把里面的忽略全部√上。CTRL+F2重载下程序
忽略所有异常

按ALT+M,打开内存镜象，找到程序的第一个.rsrc.
Alt + M打开内存镜像，找到程序的第一个.rsrc.按?
Alt+M?? 打开内存镜像，找到第一个? ”.rsrc“?

按F2下断点，然后按SHIFT+F9运 行到断点，
F2下断点，按下F9运行程序
F2（下断），F9（运行）

接着再按ALT+M,打开内存镜象，找到程序的第一个.rsrc.上面的代码段.text（或者CODE）（也就是00401000处），
再按ALT+M,打开内存镜象，找到程序的第一个代码段.rsrc.上面的.text，
Alt+M?? 打开内存镜像，找到”Code“段；

按F2下断点。然后按SHIFT+F9（或者是在没异常情况下按F9），
按F2下断点，? 按下F9运行程序
F2（下断），Shift+F9【这点一定要记住，切记是 Shift+F9】运行；先按F8，再按下F4，

直接到达程序OEP
直接到达OEP
直接到达OEP

注：有时候在给软件脱壳，千心万苦找到了OEP，却发现不是常见的“push ebp”，而是出 现如下图这种情况，其实这是OD将这段代码当做数据了没有进行反汇编识别，解决方 法是，选中一行右键选择“分析”菜单，选择“分析”下的“分析代码”，OEP就会出 现在眼前了

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实战

1 查壳

用PEID查壳的结果如下图，可以看出程序加了ASPack2.12的壳

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2 寻找OEP

(1)用OD载入该程序 ?

（2）依次选择OD选项（T）下的调试设置（D）子选择，弹出如下对话框，切到异常选项卡，将忽略下的子项全部勾上 ?

（3）Ctrl + F2重新载入要脱壳的程序，Alt + M打开内存镜像，找到程序的第一个.rsrc.按? F2下断点，按下F9运行程序

?（3）再按ALT+M,打开内存镜象，找到程序的第一个代码段.rsrc.上面的.text，按F2下断点，? 按下F9运行程序

?（3）直接到达OEP

注：有时候在给软件脱壳，千心万苦找到了OEP，却发现不是常见的“push ebp”，而是出 现如下图这种情况，其实这是OD将这段代码当做数据了没有进行反汇编识别，解决方 法是，选中一行右键选择“分析”菜单，选择“分析”下的“分析代码”，OEP就会出 现在眼前了

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3 脱壳（Dump）
3 脱壳

可以使用OD自带插件，也可以用LordPE，方法和前面"单步跟踪法"中使用方法一样

（1）在OEP（OEP地址004010CC）处使用OD插件脱壳，在004010CC上点击鼠标右键，? 选择该菜单下的Dump debugged process，会弹出如下对话框，从下图最底Rebuild?? Import选项下可以看出该插件提供了两种脱壳方式

?（2）分别用Method1和Method2脱壳，点击Dump按钮然后选择文件的保存位置即可脱壳 ?

（3）当然也可以用LordPE来脱壳，选中要脱壳的进程notepad.exe，因为使用OD加载的时候已经启动该进程

?（4）在该进程上右键，选择该菜单下的修正镜像大小，结果如下图

?（5）在该进程上右键，选择该菜单下的完整转存（也有的翻译是完全脱壳），会弹出文件保? 存位置对话框，填好文件名称后保存即可，成功后会弹出如下对话框 ?

（6）再次用PEID检测unpack1.exe、unpack2.exe、unpack3.exe，会发现程序已经是无壳的 ?

（7）分别打开已经脱壳完成的unpack1.exe、unpack2.exe、unpack3.exe，会发现unpack3.exe运行后出现如下错误，则在该种情况下需要修复资源

4 修复

4 修复

可以使用ImportFix，方法和前面"单步跟踪法"中使用方法一样

（1）使用到的修复工具是ImportFix，打开ImportFix，打开notepad.exe这个进程，因为用OD载入加壳程序notepad.exe后，会产生notepad.exe这个进程（此时需要OD中将程序调试运行到OEP处，即004010CC处，否则在下面的自动查找IAT会失败）

如何在OD中将程序调试运行到OEP处

（2）将OEP那一栏修改成刚才在OD中找到的OEP地址000010CC，然后点击自动查找? IAT，则RVA和大小这一栏中数据会改变

（3）点击确定后，点击获取输入表按钮，结果如下图，其中找到的输入表函数里面的函数? 是程序运行需要的一些系统API?

（4）点击显示无效函数后，发现没有，在点击修复转存文件按钮，选择要修复的unpack3.exe? 文件

?（5）完成后会在记录这一列表框中显示结果，修复后的文件保存名字为unpack3_.exe

?（6）打开unpack3_.exe，发现程序能正常运行，则修复成功

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4 一步到达OEP

（1）开始按Ctrl+F,输入：popad（只适合少数壳，包括UPX，ASPACK壳），然后按下F2，? F9运行到此处

（2）来到大跳转处，点下F8，到达OEP

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5 最后一次异常法

（1）用OD打开软件

（2）点击选项——调试选项——异常，把里面的√全部去掉！CTRL+F2重载下程序

（3）一开始程序就是一个跳转，在这里我们按SHIFT+F9，直到程序运行，记下从开始按SHIFT+F9到程序运行的次数m

（4）CTRL+F2重载程序，按SHIFT+F9（这次按的次数为程序运行的次数m-1次）

（5）在OD的右下角我们看见有一个"SE 句柄"，这时我们按CTRL+G，输入SE 句柄前的地址

（6）按F2下断点，然后按SHIFT+F9来到断点处

（7）去掉断点，按F8慢慢向下走

（8）到达程序的OEP

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?（这种脱壳方法在我这台电脑上无法演示，可能是因为系统问题吧，不过大家跟着下面的步骤做就可以找到OEP了）
1：用OD打开软件
2：点击选项——调试选项——异常，把里面的勾全部去掉，CTRL+F2重新加载程序
3：在这里我们按SHIFT+F9，直到程序运行，记下从开始按SHIFT+F9到程序运行的次数? 3
4：CTRL+F2重新加载程序，按SHIFT+F9（次数为程序运行的次数-1次）
5：在OD的右下角我们看见有一个SE 句柄，这时我们按CTRL+G，输入SE 句柄前的地址！
6：按F2下断点，然后按SHIFT+F9来到断点处！
7：去掉断点，按F8慢慢向下走
8：到达程序的OEP，脱壳

6 模拟跟踪法

（1）先试运行，跟踪一下程序，看有没有SEH暗桩之类

（2）ALT+M打开内存镜像，找到（包含那一列中出现SFX,imports,relocations或者SFX,输? 入表，重定位）

（3）若地址为00xxxxxx在命令行下输入tc eip<00xxxxxx，回车，提示正在跟踪

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7 SFX法

（1）设置OD，忽略所有异常，也就是说异常选项卡里面都打上勾

（2）切换到SFX选项卡，选择“字节模式跟踪实际入口（速度非常慢）”，确定

（3）重载程序（如果跳出是否“压缩代码？”选择“否”，OD直接到达OEP）

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

寻找真正的入口（OEP）-- 广义ESP定律 2004-09-14

http://www.pediy.com/kssd/pediy06/pediy6083.htm

标 题：【转载】寻找真正的入口（OEP）--广义ESP定律
时 间：2004-09-14,15:43
链 接：http://bbs.pediy.com

寻找真正的入口（OEP）--广义ESP定律

作者：Lenus
FROM: poptown.gamewan.com/bbs
E-MAIL：Lenus_M@163.com

1.前言

在论坛上看到很多朋友，不知道什么是ESP定律，ESP的适用范围是什么，ESP定律的原理是什么，如何使用ESP定律？看到了我在

http://poptown.gamewan.com/dispbbs.asp?boardID=5&ID=54&page=1

调查结果发现,大家对ESP定律很感兴趣，当然因为实在是太好用了，现在我就来告诉大家什么是ESP定律，它的原理是什么！！

BTW：在看完了手动脱壳入门十八篇了以后，再看这篇文章也许会对你更有帮助！

在下面地址下载：

http://soft.winzheng.com/SoftView/SoftView_23125.htm

2.准备知识

在我们开始讨论ESP定律之前，我先给你讲解一下一些简单的汇编知识。

1.call

这个命令是访问子程序的一个汇编基本指令。也许你说，这个我早就知道了！别急请继续看完。

call真正的意义是什么呢？我们可以这样来理解：
1.向堆栈中压入下一行程序的地址；2.JMP到call的子程序地址处。例如：

00401029??? .? E8 DA240A00??? call 004A3508
0040102E??? .? 5A???????????? pop edx
在执行了00401029以后，程序会将0040102E压入堆栈，然后JMP到004A3508地址处！

2.RET
与call对应的就是RET了。对于RET我们可以这样来理解：
1.将当前的ESP中指向的地址出栈；2.JMP到这个地址。

这个就完成了一次调用子程序的过程。在这里关键的地方是：如果我们要返回父程序，则当我们在堆栈中进行堆栈的操作的时候，一定要保证在RET这条指令之前，ESP指向的是我们压入栈中的地址。这也就是著名的“堆栈平衡”原理！

3.狭义ESP定律

ESP定律的原理就是“堆栈平衡”原理。

让我们来到程序的入口处看看吧！

1.这个是加了UPX壳的入口时各个寄存器的值！
EAX 00000000
ECX 0012FFB0
EDX 7FFE0304
EBX 7FFDF000
ESP 0012FFC4
EBP 0012FFF0
ESI 77F51778 ntdll.77F51778
EDI 77F517E6 ntdll.77F517E6
EIP 0040EC90 note-upx.<ModuleEntryPoint>
C 0? ES 0023 32bit 0(FFFFFFFF)
P 1? CS 001B 32bit 0(FFFFFFFF)
A 0? SS 0023 32bit 0(FFFFFFFF)
Z 0? DS 0023 32bit 0(FFFFFFFF)
S 1? FS 0038 32bit 7FFDE000(FFF)
T 0? GS 0000 NULL
D 0
O 0? LastErr ERROR_MOD_NOT_FOUND (0000007E)

2.这个是UPX壳JMP到OEP后的寄存器的值！
EAX 00000000
ECX 0012FFB0
EDX 7FFE0304
EBX 7FFDF000
ESP 0012FFC4
EBP 0012FFF0
ESI 77F51778 ntdll.77F51778
EDI 77F517E6 ntdll.77F517E6
EIP 004010CC note-upx.004010CC
C 0? ES 0023 32bit 0(FFFFFFFF)
P 1? CS 001B 32bit 0(FFFFFFFF)
A 0? SS 0023 32bit 0(FFFFFFFF)
Z 1? DS 0023 32bit 0(FFFFFFFF)
S 0? FS 0038 32bit 7FFDE000(FFF)
T 0? GS 0000 NULL
D 0
O 0? LastErr ERROR_MOD_NOT_FOUND (0000007E)

呵呵~是不是除了EIP不同以外，其他都一模一样啊！

为什么会这样呢？
我们来看看UPX的壳的第一行：

0040EC90 n>? 60?????????????? pushad????? //****注意这里*****
0040EC91???? BE 15B04000????? mov esi,note-upx.0040B015

PUSHAD就是把所有寄存器压栈！我们在到壳的最后看看：

0040EE0F???? 61?????????????? popad????? //****注意这里*****
0040EE10?? - E9 B722FFFF????? jmp note-upx.004010CC?? //JMP到OEP

POP就是将所有寄存器出栈！

而当我们PUSHAD的时候，ESP将寄存器压入了0012FFC0--0012FFA4的堆栈中！如下：

0012FFA4?? 77F517E6? 返回到 ntdll.77F517E6 来自 ntdll.77F78C4E?????????? //EDI
0012FFA8?? 77F51778? 返回到 ntdll.77F51778 来自 ntdll.77F517B5????????? //ESI
0012FFAC?? 0012FFF0??????????????????????????????????????????????????? //EBP
0012FFB0?? 0012FFC4?????????????????????????????????????????????????? //ESP
0012FFB4?? 7FFDF000????????????????????????????????????????????????? //EBX
0012FFB8?? 7FFE0304???????????????????????????????????????????????? //EDX
0012FFBC?? 0012FFB0?????????????? ?????????????????????????????????//ECX
0012FFC0?? 00000000?????????????????????????????????????????????? //EAX

所以这个时候，在教程上面就告诉我们对ESP的0012FFA4下硬件访问断点。也就是说当程序要访问这些堆栈，从而恢复原来寄存器的值，准备跳向苦苦寻觅的OEP的时候，OD帮助我们中断下来。

于是我们停在0040EE10这一行！

总结：我们可以把壳假设为一个子程序，当壳把代码解压前和解压后，他必须要做的是遵循堆栈平衡的原理，让ESP执行到OEP的时候，使ESP=0012FFC4。

4.广义ESP定律

很多人看完了教程就会问：ESP定律是不是就是0012FFA4，ESP定律的适用范围是不是只能是压缩壳！

我的回答是：NO！

看完了上面你就知道你如果用0012FFA8也是可以的，ESP定律不仅用于压缩壳他也可以用于加密壳！！！

首先，告诉你一条经验也是事实---当PE文件运行开始的时候，也就是进入壳的第一行代码的时候。寄存器的值总是上面的那些值，不信你自己去试试！而当到达OEP后，绝大多的程序都第一句都是压栈！（除了BC编写的程序，BC一般是在下面几句压栈）

现在，根据上面的ESP原理，我们知道多数壳在运行到OEP的时候ESP=0012FFC4。这就是说程序的第一句是对0012FFC0进行写入操作！

最后我们得到了广义的ESP定律，对只要在0012FFC0下，硬件写入断点，我们就能停在OEP的第二句处！！

下面我们来举个例子,就脱壳进阶第一篇吧！

载入OD后，来到这里：

0040D042 N>? B8 00D04000????? mov eax,Notepad.0040D000 //停在这里
0040D047???? 68 4C584000????? push Notepad.0040584C
0040D04C???? 64:FF35 00000000 push dword ptr fs:[0]??? //第一次硬件中断，F9
0040D053???? 64:8925 00000000 mov dword ptr fs:[0],esp
0040D05A???? 66:9C??????????? pushfw
0040D05C???? 60 ??????????????pushad
0040D05D???? 50?????????????? push eax

直接对0012FFC0下硬件写入断点，F9运行。（注意硬件中断）

在0040D04C第一次硬件中断，F9继续！

0040D135???? A4?????????????? movs byte ptr es:[edi],byte ptr ds:[esi] //访问异常，不管他 shift+F9继续
0040D136???? 33C9???????????? xor ecx,ecx
0040D138???? 83FB 00????????? cmp ebx,0
0040D13B?? ^ 7E A4??????????? jle short Notepad.0040D0E1

第二次硬件中断。

004058B5?????? 64???????????? db 64???????????????????????????????? //断在这里
004058B6?????? 89???????????? db 89
004058B7?????? 1D???????????? db 1D
004058B8?????? 00???????????? db 00
004058B9?????? 00???????????? db 00

这里也不是，F9继续！

004010CC?? /.? 55???????????? push ebp
004010CD?? |.? 8BEC?????????? mov ebp,esp? //断在这里，哈哈，到了！（如果发现有花指令，用ctrl+A分析一下就能显示出来）
004010CF?? |.? 83EC 44??????? sub esp,44
004010D2?? |.? 56???????????? push esi

快吧！还不过瘾，在来一个例子。

脱壳进阶第二篇

如果按上面的方法断不下来，程序直接运行了！没什么，我们在用另一种方法！

载入后停在这里，用插件把OD隐藏！

0040DBD6 N>^\E9 25E4FFFF????? jmp Note_tEl.0040C000????????????????? //停在这里
0040DBDB???? 0000???????????? add byte ptr ds:[eax],al
0040DBDD???? 0038???????????? add byte ptr ds:[eax],bh
0040DBDF???? A4?????????????? movs byte ptr es:[edi],byte ptr ds:[esi]
0040DBE0???? 54?????????????? push esp

F9运行，然后用SHIFT+F9跳过异常来到这里：

0040D817?? ^\73 DC??????????? jnb short Note_tEl.0040D7F5?????? //到这里
0040D819???? CD20 64678F06??? vxdcall 68F6764
0040D81F???? 0000???????????? add byte ptr ds:[eax],al
0040D821???? 58?????????????? pop eax

在这里对0012FFC0下硬件写入断点！（命令行里键入HW 12FFC0）SHIFT+F9跳过异常，就来到OEP的第二行处：（用CTRL+A分析一下）

004010CC?? /.? 55???????????? push ebp
004010CD?? |.? 8BEC?????????? mov ebp,esp?????????????????????? //断在这里
004010CF?? |.? 83EC 44??????? sub esp,44
004010D2?? |.? 56???????????? push esi
004010D3?? |.? FF15 E4634000? call dword ptr ds:[4063E4]
004010D9?? |.? 8BF0?????????? mov esi,eax
004010DB?? |.? 8A00?????????? mov al,byte ptr ds:[eax]
004010DD?? |.? 3C 22????????? cmp al,22

就这样我们轻松搞定了两个加密壳的找OEP问题！

5.总结

现在我们可以轻松的回答一些问题了。

1.ESP定律的原理是什么？

堆栈平衡原理。

2.ESP定律的适用范围是什么？

几乎全部的压缩壳，部分加密壳。只要是在JMP到OEP后，ESP=0012FFC4的壳，理论上我们都可以使用。但是在何时下断点避开校验，何时下断OD才能断下来，这还需要多多总结和多多积累。欢迎你将你的经验和我们分享。

3.是不是只能下断12FFA4的访问断点？

当然不是，那只是ESP定律的一个体现，我们运用的是ESP定律的原理，而不应该是他的具体数值，不能说12FFA4，或者12FFC0就是ESP定律，他们只是ESP定律的一个应用罢了！

4.对于STOLEN CODE我们怎么办？

哈哈，这正是寻找STOLEN CODE最好的办法！当我们断下时，正好断在了壳处理STOLEN CODE的地方，在F8一会就到OEP了！

6.后话

以上的方法原理都是我自己总结，自己的经验，如果有什么不对的地方，有什么没解释清楚的地方。还请海涵！但是如果觉得我很厉害，那就大可不必，因为ESP定律也是别人教我的，不是我第一个提出来的！我只是个比你们早飞一点的菜鸟罢了^-^

看了上面的文字希望能对你在寻找OEP的时候有帮助，但是别忘了一句话：菜鸟认为找OEP很难，高手认为修复才是最难！ 好了，下一篇应该写IAT的修复原理了！让我们共同努力吧！

最后如果转载注明作者并保持文章的完整, 谢谢你看完

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Ollydbg手动脱壳的几点小结

http://blog.sina.com.cn/s/blog_4b75f26e0100ba1y.html

Ollydbg手动脱壳的几点小结【转看雪论坛2003】 (2008-10-14 18:42:33)

一般认为手动脱壳的关键是找到软件的真正入口OEP，但是用ollydbg脱壳知道软件的真正入口OEP并不能解决问题，因为ollydbg的工作原理和softice、trw2000等的有所不同，在OEP未解压以前是不能在OEP设断上的，因此用ollydbg脱壳的关键是让程序中断在OEP，一旦中断在OEP脱壳就告完成。当然能够用冲击波等软件知道软件的OEP在用ollydbg脱壳中还是有一定帮助的。那么如何让程序中断在OEP呢？这里小结几种方法。

方法一、用ollydbg载入程序，，第1个消息框，点yes，第2个消息框，点no，程序停在入口处EP（注意不是OEP） ctrl+b? Hex中输入壳的入口特征代码（如upx? 61 E9），回车
popad
看到入口点jmp xxxxxx
F2在此行设断（或者将光标移动到这一行上按f4），F9，F8走1-2下，来到入口点，用ollydbg的插件dump选中程序进程dump程序。但此法对于有些入口点附近代码被压缩的程序就无能为力了。对于这种程序有方法二。

方法二、用ollydbg载入程序，，第1个消息框，点yes，第2个消息框，点no，ctrl+b? Hex中输入壳的入口特征代码（如upx? 61 E9），回车，找不到
popad
jmp? xxxxxx
对于这种情况在用ollydbg载入程序，，第1个消息框，点yes，第2个消息框，点no时程序停在入口处EP（注意不是OEP），先用F9，F8走几下，使特征代码解压缩再用上面的方法搜索壳的特征代码。一般都能解决问题。对于那些不知到壳特征代码的那怎么办呢？于是有了方法三。

方法三、用ollydbg载入程序，，第1个消息框，点yes，第2个消息框，点no，程序停在入口处EP（注意不是OEP），一般代码为pushad、? pushfd等。自己用眼睛向下搜索与pushad 、 pushfd对应的popad、popfd 。F2在此行设断（或者将光标移动到这一行上按f4），F9，F8走1-2下，来到入口点，用ollydbg的插件dump选中程序进程dump程序。那么怎么知道找到的popad、popfd是与程序EP对应的popad、popfd呢？一般情况，对于保护不是非常强悍的壳向下找十几行或几十行看到的第一个popad、popfd即为对应的popad、popfd。而且入口点附近popad往往在下面几行还有指令ret。有些壳如PECompact它的入口处EP有? xxxxxxx??? pushad
xxxxxxx??? pushfd

?那么当你看到??????????? xxxxxxx??? popfd
xxxxxxx??? popad??? 就找到了。如果向下找十几行或几十行找不到的popad、popfd那该怎么办呢？于是有了方法四。

对方法三的补充：有些壳如果在ollydbg中找popad是行不通的，因为用ollydbg载入脱壳对象时第1个消息框，点yes，第2个消息框，点no，ollydbg没有中断在pushad上，我曾碰到过用ollydbg载入脱壳对象时第1个消息框，点yes，第2个消息框，点no，ollydbg没有中断在popad上，这样OEP应该在pashad附近，所以应该与之对应pushad。一般这样的壳保护比较弱。很容易脱的。

方法四、用ollydbg载入程序，，第1个消息框，点yes，第2个消息框，点no，程序停在入口处EP（注意不是OEP），一般代码为pushad、? pushfd等。自己用眼睛向下搜索与pushad 、 pushfd对应的popad、popfd。向下找十几行或几十行找不到的popad、popfd那必须先用F9，F8走几下，使特征代码popad、popfd解压缩再搜索popad、popfd。

方法五、对于大量使用SEH，保护非常强悍的壳，如aspr需采用以下方法。
1、使程序运行到最后一次SHE，最后一次SHE如何确定？记下程序运行的shift＋f9次数n，shift＋f9??????????? n－1就是。
2、看堆践处SHE? handle? f2设断，shift＋f9查找popad、popfd即可。
3、如果能够知道OEP，此时步骤2也可用ctrl+g OEP按f4而且有些aspr版本必须用此法，否则非常麻烦

附表：壳名称、版本相应的特征代码
壳名称及版本??? 特征代码
Asprotect? 1.0以下??? EB 02 EB E8 61 EB 01
Asprotect? 1.2??? 61 FF E0
ASPack 2.0以下??? 61 75 08 b8
PECompact 1.33??? 61 9D 50 68
Petite 2.1/2.2??? 61 66 9D 83 C4
PE-pack? all??? 89 44 24 1c 61 FF E0
Armadillo 2.51??? 03 F9 E8 A9 EE FF
Armadillo 2.52??? 03 F9 E8 2D EE FF
VBox 4.6.5??? CD 20 FF E3
ASPack 2.12??? B8 01 00 00 00 C2

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整体程序
首先你要用PEID的V插件查出真正的版本[一般如果你查到的是这样结果很有可能是ASProtect 2.3 版]，然后使用OD载入，如果你还是新手建议使用脚本去脱壳，可以去“看雪”站上下的。脱壳后可能需要修复，【修复工具：ImpotREC_chs】，如果还不能运行，就应该是有效验。

侦壳
用Vera查为：

脱壳机
还有一个就是PEID里面插件的通用脱壳机。貌似是利用堆栈窗口那个的返回的那个原理吧？程序运行之后就可以找到入口点。

我脱ASP都是用这个脱的：DecomAS.exe
用工具DecomAS脱吧.不过要注意,脱壳文件运行之前:一是把程序文件夹内的CheatPainConfig.ini文件和backgrounds文件夹(是隐藏属性)删除后重新让程序自动配置才行;二是脱壳后的文件名最好保证是原文件名;三是对脱壳程序的任何修改并保存后,重复前两个步骤.

脱壳脚本
VOLX大虾的脚本Aspr2.XX_unpacker_v1.0SC.osc可以脱
用Kopia Aspr2.XX_unpacker_v1.15cE.osc? 可以，但有偷代码。

你上面的图，显示你已经跑脚本成功了，按一下确定，再按一下快捷面板上的L，往下拉，看到红色文字，打开ImportREC填入相应的数值就可以修复了。注：在ImportREC填的OEP是相对OEP，IAT是相对IAT
00975728

脚本跑完，看log窗口，脚本会把oep和iat大小位置都写出来，然后用LordPE来dump下，然后ImpREC修复一下就可 ...

有时是暗桩，有时是自效验，总之脚本非万能！
用脚本的前提是排除一些暗桩，自校验等等的东西，这些脚本都是无法预料到的，，遇到这类就要自己手脱慢慢查了。

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脱壳目标文件名：test.exe
加的壳：ASProtect 1.2x - 1.3x [Registered] -> Alexey Solodovnikov [Overlay]

操作步骤：
1。升级OD脚本版本-> 1.53脚本
把此OllyScript.dll复制到OD的Plugin目录下并覆盖原先的OllyScript.dll
2。Asprotect1.2x-1.3x.osc可以放置任一目录。
3。OD载入加壳程序
插件->OllyScript->运行脚本->打开? 找到Asprotect1.2x-1.3x.osc
4。此时OD自行运行。运行完毕后将在加壳程序同目录生成de_test.exe
5。OD 中执行->查看->记录
IAT 的地址 = 004F1190
IAT 的相对地址 = 000F1190
IAT 的大小 = 0000078C
00B90079?? 中断在 00B90079
OEP 的地址 = 004EA024
OEP 的相对地址 = 000EA024
这些数据是关键，下一步要用到。
6。ImportREC修复。
找到test.exe进程?
按此数据填入：
OEP=000EA024（上面的OEP 的相对地址）
RVA=000F1190（IAT 的相对地址）
大小=0000078C（ IAT 的大小）
填写完毕。此时直接点“获取输入表” 。为保险起见点“显示无效的”，一般情况这样子操作后全为有效，最后一步“修复转储文件”
大功告成。。。

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先OD载入吧，使用插件->odbgscript->运行脚本 -> 打开（Aspr2.XX_unpacker_v1.0SC.osc）??
运行脚本过程有『偷窃代码，请查看记录窗口内的IAT数据』点击确定，查看窗口记录，找到如下项??

消息=IAT 的地址 = 006AE1F4?????? IAT 的相对地址 = 002AE1F4?????? IAT 的大小 = 00000A74?????? 断点位于 01140079?????? OEP 的地址 = 0068B8FC?????? OEP 的相对地址 = 0028B8FC? 运行ImportREC

附加脱壳的进程，把od窗口记录里面的 “OEP 的相对地址” 0028B8FC数据填写到oep，? “IAT 的大小”的数据00000A74填写到“ImportREC的大小”，? “IAT 的相对地址”的数据002AE1F4填写到RVA，点击获取输入表->修复转存文件->选择dump的文件? 好了，处理附加数据，发现文件还是不可以使用，就没有处理……不知道怎么回事，请高手指点……详细顶！

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步骤如下：
1。pe查壳为“ASProtect 1.33 - 2.1 Registered -> Alexey Solodovnikov [Overlay] *”
2。ollydbg 打开用 Volx的超强脱壳脚本“Aspr2.XX_unpacker_v1.13SC.osc”提示有偷代码
3。“ALT+L”提示：：IAT 的地址 = 00407000
IAT 的相对地址 = 00007000
IAT 的大小 = 000000C0
OEP 的地址 = 0040389F
OEP 的相对地址 = 0000389F

4。用Import rec? 修正：打开软件，选取文件，在OEP处填“0000389F”按“自动搜索”
RVA 00007000??? SIZE：000000C0?? 再点“获取输入表”--未出现错误? --“修复转存文件”

5.运行文件“de-源文件名-。exe”文件，提示：invalid date in the file

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ASProtect 1.2x-1.3x脱壳方法??

http://bbs.pediy.com/showthread.php?t=89342

2009-05-20, 10:07:59 默认 ASProtect 1.2x-1.3x脱壳方法

rosetta 当前离线
花了一天时间脱这壳没脱成功。。。郁闷之于网上搜搜，发现可以用脚本脱，小菜把这思路整理了下发上。。。文章原创，思路网上找的。
脱壳目标文件名：test.exe
加的壳：ASProtect 1.2x - 1.3x [Registered] -> Alexey Solodovnikov [Overlay]

操作步骤：
1。升级OD脚本版本-> 1.53脚本
把此OllyScript.dll复制到OD的Plugin目录下并覆盖原先的OllyScript.dll
2。Asprotect1.2x-1.3x.osc可以放置任一目录。
3。OD载入加壳程序
插件->OllyScript->运行脚本->打开? 找到Asprotect1.2x-1.3x.osc
4。此时OD自行运行。运行完毕后将在加壳程序同目录生成de_test.exe
5。OD 中执行->查看->记录
IAT 的地址 = 004F1190
IAT 的相对地址 = 000F1190
IAT 的大小 = 0000078C
00B90079?? 中断在 00B90079
OEP 的地址 = 004EA024
OEP 的相对地址 = 000EA024
这些数据是关键，下一步要用到。
6。ImportREC修复。
找到test.exe进程?
按此数据填入：
OEP=000EA024（上面的OEP 的相对地址）
RVA=000F1190（IAT 的相对地址）
大小=0000078C（ IAT 的大小）
填写完毕。此时直接点“获取输入表” 。为保险起见点“显示无效的”，一般情况这样子操作后全为有效，最后一步“修复转储文件”
大功告成。。。

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脱壳步骤:
一用peidy+ver1.5 检测程序壳类型
二载入程序：
OllyDbg载入程序时候，总是提示Protection Erorr，在 插件->HideOD->Option中设置,
即可隐藏OD了
三使用插件->odbgscript->运行脚本 -> 打开（Aspr2.XX_unpacker_v1.14SC.osc）
运行脚本过程无代码偷窃，点击确定，查看窗口记录，找到如下项（用于在ImportREC修改OEP 和RVA，
注意：不要使用自动查找IAT来修复转存储文件，否则有可能造成修改后的文件不能使用）

IAT 的地址 = 00425000
IAT 的相对地址 = 00025000
IAT 的大小 = 000008B0
断点位于 01A40042
OEP 的地址 = 0042501F
OEP 的相对地址 = 0002501F

四运行ImportREC，附加你脱壳的进程，把od窗口记录里面的 “OEP 的相对地址”数据填写到oep，
“IAT 的大小”的数据填写到“ImportREC的大小”，
“IAT 的相对地址”的数据填写到RVA，点击获取输入表->修复转存储->你dump的文件
好了现在你可以测试你使用脚本脱壳的文件了～

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004C536C Conditional pause: eip > 001C1000
Address of IAT = 004CB190
RVA of IAT = 000CB190
Size of IAT = 00000740
001D0042 Breakpoint at 001D0042
Address of OEP = 004C536C
RVA of OEP = 000C536C

001E78A4 Hardware breakpoint 1 at 001E78A4
004C536C Conditional pause: eip > 001C1000
Address of IAT = 004CB190
RVA of IAT = 000CB190
Size of IAT = 00000740
001D0042 Breakpoint at 001D0042
Address of OEP = 004C536C
RVA of OEP = 000C536C

001E621B Breakpoint at 001E621B
001E78A4 Hardware breakpoint 1 at 001E78A4
004C536C Conditional pause: eip > 001C1000
Address of IAT = 004CB190
RVA of IAT = 000CB190
Size of IAT = 00000740
001D0042 Breakpoint at 001D0042
Address of OEP = 004C536C
RVA of OEP = 000C536C

一、运行脚本。

运行VolX大侠脚本Aspr2.XX_IATfixer_v1.02s。
手动找到OEP。
004777D9???? 55??????? push ebp????? ???????????????????????????; OEP!
004777DA???? 8BEC????? mov ebp,esp
004777DC???? 6A FF???? push -1
004777DE???? 68 78604C>push wlexplor.004C6078
004777E3???? 68 60DB47>push wlexplor.0047DB60
004777E8???? 64:A1 000>mov eax,dword ptr fs:[0]
004777EE???? 50 ???????push eax
004777EF???? 64:8925 0>mov dword ptr fs:[0],esp
004777F6???? 83EC 58?? sub esp,58
004777F9???? 53??????? push ebx
004777FA???? 56??????? push esi
004777FB???? 57??????? push edi
004777FC???? 8965 E8?? mov dword ptr ss:[ebp-18],esp
004777FF ????FF15 4C82>call dword ptr ds:[4B824C]?????????????? ; kernel32.GetVersion

OEP=4777D9-400000=777D9

iatstartaddr: 004B8000
iatsize: 00000840

RVA=004B8000-00400000=B8000
Size=840
LordPE--->完整转存--->dumped.exe

ImportREC--->OEP=255E90,RVA=27E258,Size=A14--->获取输入表。
显示未解决的指针1个，右键--->插件跟踪--->ASPRotect 1.22,修复完成。
修复转储文件，得到dumped_.exe。

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修复CRC

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补区段

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Stolen OEP

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Stolen Code

提示：“There are stolen code, check IAT data in log window”

某软件 是ASPR 2.X 的壳,volx的脚本 顺利跑完,并生成DE_XXX.exe 文件 .中间 提示有STOLEN CODE 请问 怎么处理 STOLEN CODE?? 有详细的资料 请留下!谢~

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ASProtect 1.2x - 1.3x脱壳破解

ASProtect 1.23RC1

ASProtect 1.2x - 1.3x脱壳破解
ASProtect 1.2x - 1.3x脱壳脚本
ASProtect 1.2x - 1.3x脱壳工具
最后一次异常加内存镜像手脱了，关键是修复，网上有的是这样的文。

ASProtect 1.2x - 1.3x 没有出现异常

Win Web Crawler

ASprotect ver 2.1 / 2.^ ( www.aspack.com ) - ! Correct version detect only : ASPrINFO v 1.6 Beta 100% detector by nik0g0r 2oo7

try Stripper v2.13 beta 9 by syd or Ollydbg.exe with plugin Aspr2.XX_unpacker_v1.0E by VolX OR DecomAS by PE_Kill 2011.04

ASProtect 2.1x SKE -> Alexey Solodovnikov

OEP: 004C536C

Log data, item 2
Message=Address of OEP = 004C536C
Log data, item 1
Message=RVA of OEP = 000C536C

No stolen code, check IAT data in log window.

thic copy of win web crawler is corrupted

(initial file size do not match)

EP code like Delphi/C++ but different structure

ImportREC 的ASProtect 2.1x SKE 插件

http://beikeit.com/post-582.html

https://bbs.pediy.com/thread-24236.htm

https://www.cnblogs.com/onephp/p/5649779.html

https://www.52pojie.cn/thread-111599-1-1.html

http://blog.sina.com.cn/s/blog_49c240bb0100eqxy.html

http://bbs.dnjc8.net/thread-14152-1-1.html

Aspr2.XX_unpacker_v1.osc

Aspr2.XX_unpacker_v1.osc

Aspr2.XX_unpacker_v1.13SC.osc

用Kopia Aspr2.XX_unpacker_v1.15cE.osc? 可以，但有偷代码。

Volx大侠的asprotect 脚本

ASProtect 2.1x重启验证的脱壳是用IATfixer.1.02.osc脚本

【特别推荐那个叫Asprotect2.XX IAT fixer v2.2S的好东东，似乎是唯一支持1.3以上版本的ASP壳的，其他都止步于1.2版】
ASProtect unpacker by PE_Kill 或 VolX 脚本


cracking

Web and IT Technologies

Software Reverse Engineering

since 2015-10

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问题

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OD运行程序总是显示access violation

如何破解无法通过字符串搜索功能寻找注册关键位的软件
OD找不到关键字怎么破解软件
用OD和CE都搜不出相关字符串
OD里面找不到关键字
查找字符串里面没有关键字怎么办
通过OD找不到关键词
OD里面找不到注册成功关键字
OD解决“超级字符串查找”找不到字符串的方法

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如何破解输入注册信息没有反应的软件
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vb的可以试试按钮事件脚本，或者下“字符串比较”这一类的断点
bpx * 找处理字符串的 vb函数下断看看了
下按钮断点，跟踪，有错误码，说明真码就在附近。

输入错误注册码后F12暂停，查看调用堆栈最下面一个函数，一般是弹出错误提示的函数，右键查看调用call，执行到返回，F8跟进就到领空，上下翻一点，一般这时候就有点思路了

GetWindowText(A/W) GetDlgItemText(A/W) OD插件里面有下断点的，这2个断点可以试下

如何破解没有序列号错误提示的软件
输入注册信息没有反应
如何破解输入注册信息后没有反应的程序
输入错误注册码没有反应怎么入手破解
输入注册码按确认没反应,这种软件应该怎样入手破解
Ollydbg错误注册码输入后毫无反应
输入注册码点击确定没有任何提示，求思路破解它

GetWindowText(A/W) GetDlgItemText(A/W) OD插件里面有下断点的，这2个断点可以试下
看哪种编程语言写的，找对应的按钮事件下断点，按钮按下即可断下。然后跟下去。

如何破解没有注册界面的软件

Microsoft Visual C++ ver 5.0/6.0

API断点
消息断点
bp
bpx
MessageBoxA
GetWindowTextA
GetDlgItemTextA
IsDialogMessageA
GetWindowTextA
GetWindowTextW

注册按钮事件
注册按钮事件下断点
VC 按钮事件断点
vc版本6以后的每个按钮事件处理都不一样

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暂停法
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okokokokokokokokokokokok

暂停加堆栈法破解软件
F12暂停堆栈回溯法
查找字符串加暂停法可以破解软件的成功率居然高达80%

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看上面的堆栈窗口那里，有兴趣的人也可以从最顶上面的那个函数开始慢慢F8跟踪出来，也挺有意思的

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输入错误注册码后F12暂停，查看调用堆栈最下面一个函数，一般是弹出错误提示的函数，右键查看调用call，执行到返回，F8跟进就到领空，上下翻一点，一般这时候就有点思路了

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首先看看搜索的字符串方式对不对，然后搜不到的话在弹窗那一刻暂停，按k，看调用，比如messagebox之类的，然后下断，重载程序运行，一步一步retn出关键call，看看有没有跳转可以跳过这个关键call之类的，先试试看

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方法：OD载入，运行---点注册，出现失败的对话框，然后点 OD上的 K（显示调用），右键---显示调用----来到
004F0371 |. E8 76CCF1FF call <jmp.&user32.MessageBoxW> ; \MessageBoxW
004F0376 |. 8945 F4 mov [local.3],eax
004F0379 |. 33C0 xor eax,eax
向上找到段首，下断，然后再回到程序点注册。（弹出失败提示）。回到Od再用中文搜索就显示出来了
笨方法，勿喷。

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使用F12暂停堆栈法，od出现这个问题，注入代码无法响应 。难道说我的使用WuaiDbg内核调试器。求助高手如何解决
在调试设置那里面 子选项----安全---去掉 在已知的XX地址中注入代码 这个选项的钩

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楼主的od暂停法过程应该是这样--先用od载入，这个貌似不用说了哈，然后正常的运行被破的软件，需要注册的话，先用假的注册码注册，也就是随便写注册码，点击注册。这个时候会弹出一个消息框，说注册失败等信息~ 这个时候就暂停啦，可以用od控件上的暂停按钮，快捷键就是F12，然后再点od菜单上的 调试----执行到用户代码，快捷键是 ALT+F9.然后可以点击那个错误的消息框里的确认按钮，这个时候地址那里会跳转到程序执行错误代码！这貌似是烈日学院那个论坛破解外挂教程常用方法！不过那个论坛不干了！
如果是我那种方法的话！到达错误代码后点击K（或alt*k）然后选择第二个（通常是然后复制留着打樱花补丁）然后显示调用然后搜字符找到登入用户成功字样复制地址…………打字太麻烦了没效果！你可以到56搜索DNF外挂破解教程～烈日学院的！这种方法太古老了！和恒大F12差不多的年龄了！用于有提示框无壳五花无字符加密！

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找到注册失败事件后F8一直走出这个CALL，然后看哪个跳跳到该CALL来了

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既然你要用暂停法，我就简单的描述下
F12暂停后，按ALT+F9 然后点击信息框上的确定，然后一直F8往下，你会发现走着走着就到程序代码段了。

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在MessageBoxExA上右键show call，到retn处下CC，F9运行软件被断，删断Alt+F9即可

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OD破解软件找断点方法系列【调用堆栈法】----秒杀NAG窗口
https://www.52pojie.cn/thread-37749-1-1.html

1.OD载入，F9运行，点击 关闭窗口按钮如图：
2.打开“调试”菜单，点击“暂停”按钮（快捷健F12）如图：
3.打开“查看”菜单，点击“调用堆栈”（快捷健Alt+K）如图：
4.在0012F29C这行右键单击“显示调用”如图：
5.向上找到0040223E处，F2下断，如图：
6.重新载入程序，当点击关闭窗口按钮时，程序就会中断下来。004023B1处反汇编代码JNZ改为JMP，保存，这样就可以去掉这个NAG窗口了。如图：

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OD破解软件找断点方法系列【1】----调用堆栈法
http://wcb0414.blog.163.com/blog/static/449938242010844449631/

1.OD载入，F9运行如图：
2.单击“File”菜单再单击“Register”如图：
3.输入用户名：guapi注册码：123456如图：
4.点击 后如图：
5.打开“调试”菜单，点击“暂停”按钮（快捷健F12）如图：
6.打开“查看”菜单，点击“调用堆栈”（快捷健Alt+K）如图：
7.在0012F9D4这行显示ASCII "Name / Code mis-match. Try again."右键单击“显示调用”如图：
8.在73D498AF这行F2下断点,再F9运行如图：
9.单击“确定”按钮，被断下，如图：
10.F8单步来到004026D5处，如图：
11.往上找，来到断首004025C6处，F2下断，如图：
12.重新载入OD，当输入用户名和注册码点击 就会被断下，这样就可以跟踪算法了。
13.提供一组可用序列号：
用户名：guapi
注册码：6FE7D19E1FF9D4F123252803D8E9D16D
13.软件注册成功原图：
注册信息在注册表中保存位置：HKEY_LOCAL_MACHINE\SOFTWARE\Paul Gerhart Software\URLegal

【经验总结】
调用堆栈法：适用用软件（各种软件比如说："游戏外挂，有NAG窗口软件等等"）破解。

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http://www.xuepojie.com/forum.php?mod=viewthread&tid=32242&from=portal
现学现卖 暂停大法
软件打开会直接跳出注册窗口。直接点击确定 提示“你的授权信息不正确！”
首先惯例查壳，delphi写的。没加壳。
既然没加壳那我们直接OD吧。加载完成后，直接F9运行，注册窗口直接确认弹出错误信息后，不要点确定。
F12暂停一下，然后点击菜单栏 查看 -->调用堆栈，在调用堆栈窗口我们选择WaitMessage这条，
右击这条记录 在弹出的菜单选中 显示调用 我们按F4 再按F8单步
F8单步执行到这后，就一直循环执行 00477572 - 004775B8 之间的指令。

我们在004775BA处下断点 F9，这时点击提示“你的授权信息不正确”提示框，这时会中断在断点处，
我们继续F9，然后点击 授权窗口的 取消 按钮 这时还是会中断在断点处，继续F8单步执行。
到达里后发现注册窗口是从这里进入的，我们试着把这行代码改动下，
0056C7EB . /75 46 jnz short Restorat.0056C833

我们重新加载后 把jnz 改成je后再次运行，发现是可行的。但是注册窗口在主窗口show完后还是会弹出

看样子还是有地方没处理干净，这时直接点击注册窗口取消按钮，会中断在之前的断点处，继续F8。
我们又找到新的一处。同样把jnz 改成je 。重新加载后修改这两处，再F9运行，现在可以完美运行了。
0056D61D . /75 53 jnz short Restorat.0056D672

PS ： 单步的时候很痛苦，没什么经验只能耐着性子慢慢一步一步的跟踪。不过节果还是挺满意的。
另外再提供一方法，我使过可行的。前面我们查壳的时候 发现其是delphi写的，我们可以使用DEDE神器
来分析程序。可以很容易找到突破点，有兴趣的朋友可以试试。分析的对象可在附件中下载。

004C53B1 |. E8 32050000 CALL ZerBon_E.004C58E8

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暂停法 调用堆栈 破解PilotEdit5.9教程 [
https://www.52pojie.cn/thread-227759-1-1.html
暂停法 调用堆栈 破解PilotEdit5.9教程 [复制链接]

暂停法 调用堆栈 破解PilotEdit5.9教程
我是用户的破解过程http://www.52pojie.cn/thread-198203-1-1.html
下面是我的破解过程：
1. 安装，查壳，软件是无壳的，很对我们的胃口。
2. 载入od，如果停在系统领空，shift+f9
3运行，输入用户名和假码。截图

3. 点击ok
4. f12暂停，调用堆栈，
7.点击显示调用，找到段首，显示，本地调用来自 0043D198, 00442A54
分别对0043D198, 00442A54下断，运行后得知调用来自00442A54
8.继续向上找到段首，显示调用来自本地调用来自 00442AC1, 00442ADC分别对00442AC1, 00442ADC下断，运行后得知调用来自00442ADC
9.继续向上找到断首，00442ACF ，下断，运行，停在00442ACF 处，在堆栈中右击，反汇编窗口中跟随，来到0077E983 ，向上看，看见我们的假码了，
0077E8E8 这个是关键跳，改je为jnz即可。
不知道说清楚了没有，第一次做教程啊，我也是菜菜。大家指正啊！

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新手破解——调用堆栈法
http://www.360doc.com/content/11/0505/16/5886952_114583527.shtml
http://www.360doc.com/content/11/0505/16/5886952_114583527.shtml

2011-05-05

好，废话不多说，教程开始。

我们首先查壳，是Aspack的壳，对于这个壳，大家应该很熟了。
查壳.jpg

我已经脱好了壳，再查一下壳，是Dephi的
查壳2.jpg

查壳3.jpg

我们先使用一下软件，详细了解
破解1.jpg

破解2.jpg

很明显，未注册版本不能使用“单人挑战”、“网络挑战”等功能，那么破解就是为了可以使用这些功能。

好，我们用Ollydbg载入软件,这是程序入口
载入.jpg

让软件运行，并点击“单人挑战”，随意选择等级，弹出“未注册”

破解2.jpg

让软件暂停运行，点击 “查看”—“调用堆栈” 弹出堆栈窗口，如图

破解3.jpg

选择最后的一行，右击，选择显示调用，来到弹出窗口的CALL
004C53B1 |. E8 32050000 CALL ZerBon_E.004C58E8
004C53B1 |. E8 32050000 CALL ZerBon_E.004C58E8

破解4.jpg

分析一下，显然00569A7F是跳转的关键。那有朋友要说，不是把那行的“jnz”改为“je”就可以了吗？ 是的，这样确实可以，但因为未注册版本有很多功能无法使用，如果只改这里，那么其他的功能（如网络挑战）还得按照这样的方法修改。这不是很烦吗？所以我们 要找到使这个跳转跳向未注册的关键点

破解5.jpg

我们在这段代码的开头下F2断点，重新运行软件，点击“单人挑战”，随意选择等级，程序马上暂停，Ollydbg提示有 断点。然后一步步分析，发现00569A7C的代码似乎是判断是否注册的关键。单步运行到00569A7C，CPU下方小窗口显示 ds[005731E4]=00,那很显然，只要ds[005731E4]=01，那么程序就是注册的了。我们右击这个提示，选“数据窗口中跟随地址”， 如图
破解6.jpg

如图，将005731E4的数据改为01
破解7.jpg

破解8.jpg

接下来就是要生成破解后的文件，在数据窗口右击，选“复制到可执行文件”，在弹出的窗口右击，选“保存文件”

破解9.jpg

破解10.jpg

我们试用一下破解后的文件，可以了，已经没有限制

完成.jpg

到这里，教程就结束了，大家下去后好好练习下。我修改了一下软件的界面，如图

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暂停法破解里诺仓库管理软件(单机版)

F12暂停法

然后OD加载程序，停在下图处

F9运行，=程序加载完，如下图

然后依次点击暂停，和K（暂停是使程序暂停下来，K是调用堆栈），见下图（为了我的文字显得更清楚，我把文字说明处的图片背景删了）

就到了堆栈窗口，见下图

右键点最下那个，选择显示调用，

到下图你可以在光标那行鼠标左键单击后按F4键，然后进行单步，可以看到在4ABC3A的地方有个向上的跳转，见下图

你就在4ABC3C这行，鼠标左键点击，F4，OD窗口显示运行

此时你的目标就是在程序上操作了，见下两幅图

通过上面对主程序操作后，程序又被断了下来，此时可能大家就继续单步跟踪了吧，但我可以告诉你，这样可能跟踪不到，为什么呢？？？大家想想，上面那个需要注册提示框点了后消失了，然后我们点那个登陆，程序下一步该做什么呢？？？此时程序应该加载主界面了吧，所以你跟踪的话，其实就只有跟踪到程序加载主界面的过程，那怎么办呢，很简单，F9让程序运行起来，再来一次暂停法，操作我就不演示了，大家自己试，我只给大家一张这时的堆栈窗口图，仍然是最后一个右键，显示调用

到下图后向上翻，可以看到3个跳转可以跳过他，我们要找的是它么，大家可以试试，我图中已经说了，注意，可以跳过指的是可以跳过下面那个显示调用OD到这的CALL，

设好断后重新运行，看看，程序被断下来了吧，F8单步跟一下，果然没跳

下面，我们需要重新载入程序（因为刚刚已经比较了，所以不重载入程序的话赋值无效），把他需要和0比较的地方赋值为0，这里有的人很可能会问，为什么会赋值为0呢，大家看消息框，就知道那里现在是1,把1和0比较，肯定不想等，所以跳转不跳，那里改为0就相等，跳转就跳，这样程序就没未注册的框框了，而且程序也会变成注册的了，来试试，赋值的方法我在图中注明

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
中文搜索
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

???????????????????????
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
@@@@@@@@@@@@@@@@
ctrl+g 跳转到00401000 然后再中文搜索

@@@@@@@@@@@@@@@@
od载入，然后点击那个e，双击你的软件名字那段，进入就可以搜索了

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
API函数
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@
找比较函数，用OD的API函数插件
或者载入程序后右键查看当前模块中的所有函数，找到比较函数，下断点；
另外，通常这样的程序都加了反调试手段，注意看有没有重启验证。

@@@@@@@@@@@@@@@@
可以用OD的API函数插件，选择对话框函数，在GetWindowtextA(W)前面小方框内打对勾，确定后F9运行程序,这样就会对所有调用这个函数的Call或者jmp执行普通断点。

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
按钮事件
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@
用工具找按钮事件 比如ＤＥＩＰＦＩ．ＶＣ++程序就可以用dede

@@@@@@@@@@@@@@@@
http://www.52pojie.cn/thread-209823-1-1.html
vc++6.0按钮事件下断（mfc编译）
（转自小生第四课）

小生第四课居然看了2天。刚刚才看明白些，现在把这节课讲到给vc++（mfc编译）程序下按钮事件的方法转录与此：
1、od载入程序，f9运行。

2、alt+e打开模块窗口，在有mfc42.dll行双击。如图：

3、在汇编窗口右击---查找---查找所有命令。输入“sub eax,0a”，确定。如图：

4、在新窗口右击----在所有命令上下断。如图：

5、重新加载程序，f9运行，断下后f2取消断点，f7单步，来到je处，右键---跟随。如图：

6、跟到调转地址f2下断。这就是按钮事件的断点了。

@@@@@@@@@@@@@@@@
你确定是vc++的吗？MFC和vc很像。你可以用按钮事件法
vc：sub eax，0a 跟踪跳转，进call，f8两次
MFC：sub eax，0a 跟踪跳转，进call
你没有追到码是因为没f8两次吧

(ctrl+g ) 跳到00401000,查找命令"sub eax,0a"

@@@@@@@@@@@@@@@@
http://lwglucky.blog.51cto.com/1228348/274478/
各种编程语言查找按钮事件
2010-02-04 20:59:54

四、VC++程序(非MFC程序)

OD载入后,单击鼠标右键,选择"查找",然后是"所有命令"
在弹出的输入框里,写入特征代码"sub eax,0a"

确定后,就来到下面的窗口

在下面的sub eax,0A处,双击进去吧:

来找这里后,在下面的je处跟随过去

跟随来到的这个CALL,就是了,F2下断吧

然后断下后,F7跟进,F8几次,就来到按纽事件了.

@@@@@@@@@@@@@@@@
http://blog.sina.com.cn/s/blog_754e2e010102v06l.html

OllyDBG找到按钮的处理函数 (2014-08-06 15:42:59)

http://hi.baidu.com/tuuboo/blog/item/2c466b8814c284b50e244442.html

首先
1 od 下运行程序，F12 暂停；
2 View菜单中选击Windows项，在打开的窗口中可以从Title栏看到目标按钮，从而找到它的Handle(xxxxxxxx) ;
K000402A6

对不同平台生成的程序，分别处理：

二、VC程序
又分MFC和Win32两种情况，二者相同之处：
3 在IsDialogMessageW入口下条件断点: [[esp+8]]==xxxxxxxx && [[esp+8]+4]==202
[[esp+8]]==K000402A6 && [[esp+8]+4]==202
4 F9继续程序，点击目标按钮，程序中断；
5 Alt+F4，在代码段上下访问断点；
6 F9执行程序，程序中断, 注意这里虽然中断在code段，但却不是处理Button点击事件的代码处
这时：
对Win32程序，只需要按几下F7，当回到User32.dll领空后再重复一次第 5、6步就可以了；
而对于MFC程序，我们不得不多次重复这样的操作：单步回到MFC领空，再第 5、6步。好在已经看到大陆啦！

类比，这就叫IsDialogMessageW条件断点加上code段内存断点法了。


Untitled Document

Web and IT Technologies

Web crawling, data mining

since 2015-01

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Web crawling, data mining
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

CPP

000larbin

?????????????????

000open-source-search-engine

?????????????????

000pavuk

?????????????????

000WIRE

=============================

okokok

F:\Webcrawler\CPP\C#抓取网页Html源码网络爬虫

?????????????????

okokok

F:\Webcrawler\CPP\C++实现网络爬虫

okokok

F:\Webcrawler\CPP\C++网络爬虫的实现WinSock编程

okokok

F:\Webcrawler\CPP\Chilkat

okokok

F:\Webcrawler\CPP\CppMacro

?????????????????

crawler

?????????????????

Crawler1

?????????????????

CSpider

?????????????????

C-Web-Crawler

?????????????????

dataparksearch

okokok

F:\Webcrawler\CPP\gistfile1

?????????????????

methanol

?????????????????

MultiThreadWebCrawler

multithreadcrawler

okokok

F:\Webcrawler\CPP\QImageScraper\QImageScraper-master

okokok

F:\Webcrawler\CPP\SimpleCrawler

?????????????????

spider-cpp

?????????????????

spider

?????????????????

UniWebSpider

?????????????????

WebCrawler

?????????????????

Webcrawler1

?????????????????

web-scraper

okokok

网络爬虫程序源码+c++写的

Java

myjavacrawler

G:\000webcrawlerproject\Java\myjavacrawler

000crawler4j

=================================================

000heritrix

=================================================

=================================================

00000jspider

00000weblech

>>> crawlers

XXXXXXXXXXXXX

>>> 000Acme

编写代码扩展

XXXXXXXXXXXXX

000apache-nutch

XXXXXXXXXXXXX

000bubing

??????????????????????

>>>000crawler

>>> 000crawler_multi

编写代码扩展

??????????????????????????

crawler_multi

okokok

000EmailExtractor

okokok

000Email-Extractor

??????????????????????

000ex-crawler-server

hyperspider

JavaCrawlerMultiThread

okokok

000JavaCrawlerMultiThread

XXXXXXXXXXXXXXX

JavaScraper

jw1101spider

>>>000 java-web-crawler

编写代码扩展

>>>000 jw-1101-spider

可以直接运行，有图形用户界面

G:\000webcrawlerproject\Java\zzz_myjavacrawler\src\myjavacrawler\crawler\jw-1101-spider\jw-1101-spider\Bin>

java -jar SpiderControl.jar

okokok

Mercator

>>> 000multiweb

可以直接运行，命令行运行

java ie.moguntia.webcrawler.PSucker

java ie.moguntia.webcrawler.PSucker
Usage: java PSucker <url> <filenamePrefix> [<maxLevel> [<maxDoc> [<maxThreads>]]]
Crawls the web for jpeg pictures and mpeg, avi or wmv movies.
-1 for either maxLevel or maxDoc means 'unlimited'.

XXXXXXXXXXXXXXXXXXXX

000opensearchserver

??????????????????????

000smartcrawler

??????????????????????

000storm-crawler

??????????????????????

000WebCollector

?????????????????????

webcrawler

??????????????????????

000webharvest

??????????????????????

000webmagic

??????????????????????

000websphinx

??????????????????????

000WPCrawler

WPCrawler_johnhany

>>> parsers

000Parser

EmailExtractor

RegexSelector

RegexUrl

RegularExpressionFilter

okokok

myjavacrawler

NodeJS

F:\000Webcrawler\NodeJS\Spiders\000openwebspider

Python

G:\000webcrawlerproject\Python\000mypythoncrawler

py -3 pythoncrawler.py

????????????? !!!!!!!!!!!!!!!!!!!!!!! okokok

>>> 00comprehensive

XXXXXXXXXXXXXXXXX

>>> crawler

cd G:\000webcrawlerproject\Python\0000MyPythonProjects\000comprehensive\crawler

py -3 test.py

XXXXXXXXXXXXXXXXX

>>> CrawlerSpider

cd G:\000webcrawlerproject\Python\0000mypythoncrawler\comprehensive\CrawlerSpider\CrawlerSpider_master

py -3 main.py

在 link_finder 引入 zzzemailextractor_module 来抽取email

XXXXXXXXXXXXXXX

>>> Crawley

XXXXXXXXXXXXXXXXX

>>> e-mail_crawler

XXXXXXXXXXXXXXXXX

okokok but very slow

>>> email_harvester

XXXXXXXXXXXXXXXXX

okokok but very slow

>>> EmailCrawler

cd G:\000webcrawlerproject\Python\0000MyPythonProjects\00comprehensive\EmailCrawler\EmailCrawler-master

???????????????????????????????????????????????????

XXXXXXXXXXXXXX complicated

>>> grab

cd F:\000Webcrawler\Python\00grab

py -2 test.py

Transport

XXXXXXXXXXXXXXXXX complicated

>>> houndwc

XXXXXXXXXXXXXXXXXXXX

>>> IPProxyPool

XXXXXXXXXXXXXXXXX

>>> my-python-Crawler

cd G:\000webcrawlerproject\Python\0000MyPythonProjects\000comprehensive\my-python-Crawler\my-python-Crawler

py -2 main.py

XXXXXXXXXXXXXXXXX

complicated ???????????????

>>> pyspider

XXXXXXXXXXXXXXXXX

>>> SimpleEmailCrawler

可以使用，但速度较慢，每分钟只有30 至 40 个邮件。 爬行能力似乎不够

XXXXXXXXXXXXXXXX

>>> webcrawler_2_1/>>> Crawler_Parallel_with_PCcrawler

usage is domain-pattern seed-url [max-num-pages-visited]
-w domain-pattern
|
^
Ex: nist.gov http://math.nist.gov 100
-w means to continue from a webcrawl dump (fed into stdin)

py -2 PCcrawler.py -w chinavdma.org chinavdma.org http://www.chinavdma.org 88

protected url

XXXXXXXXXXXX

00xcrawler

>>> 00my_python_scraper_collections

0000my_python_scraper - 副本.py

0000my_python_scraper.py

???????????????????????????????????????????????????

000my_python_scraper_01.py

000my_python_scraper_02.py

000my_python_scraper_03.py

000my_python_scraper_04.py

000my_python_scraper_05.py

000my_python_scraper_06.py

000my_python_scraper_07.py

000my_python_scraper_linkcrawler.py

000my_python_scraper_linkcrawler2.py

000my_python_scraper_linkcrawler3.py

000my_python_scraper_linkcrawler4.py

>>> crawlers

???????????????????????????

crawl

okokok

crawl0

okokok

Crawler2

okokok

pythonlinks

>>> emailextractors

extract_email

okokok

getlinksfromurl

>>> parsers

XXXXXXXXXXXXXXX Old File Systems XXXXXXXXXXXXXXX

>>>crawler

???????????????

Crawler_Alltogether

???????????????

Crawler_Alltogether1

???????????????

Crawler_Alltogether2

Usage: Crawler_py3.py [options] <url>

Options:
--version show program's version number and exit
-h, --help show this help message and exit
-q, --quiet Enable quiet mode
-l, --links Get links for specified url only
-d DEPTH, --depth=DEPTH
Maximum depth to traverse

python Crawler_py3.py -l http://www.changingourworld.com -d 3

???????????????

Crawler01

???????????????

crawler02

???????????????okokok

crawler02_py3

???????????????

Crawler_JamesMills_py2

???????????????

Crawler_JamesMills_py2_1

???????????????

Crawler_JamesMills_py2_2

okokok

Crawler_JamesMills_py3

crawlerpy3_1

tinyDirtyIffyGoodEnoughWebCrawler_thread

>>> Facebook-Crawling-Scripts

>>> pokeycrawl

>>>Web_Crawler

!!!!!!!!!!!!!!!!!!!!!!!! OKOKOK

>>>WebCrawlerPython

>>> emails

email_samir

email_scrape

email_scraper

emailscrape

EmailScraper

email-scrape-sodevious

>>> others

disk_cache

throttle

>>> proxies

okokok

Proxy

proxies1

>>>recursive

>>> doc_crawler

>>> python-web-crawler-guide

crawler_lxml_recursive_py2_1

crawler_lxml_recursive_py2_2

Crawler_recursive_py2_1

Crawler_recursive_py2_2

Crawler_recursive_py2_3

Crawler_recursive_py2_4

Crawler_recursive_py2_5

Crawler_recursive_py2_6

Crawler_recursive_py2_7

Crawler_recursive_py2_8

Crawler_recursive_py2_9

Crawler_recursive_py2_10

Crawler_Recursive_py3_0

Crawler_recursive_py3_1

okokok

Crawler_recursive_py3_2

okokok

Crawler_recursive_py3_3

okokok

getlinksfromurl

>>> scrape_parse

okokok

GetLinks

okokok

get_links1

okokok

get_links2

okokok

get_parser_all

okokok

GetHtml_All

okokok

geturl

okokok

Parser

okokok

scrape

okokok

scrape_callback

okokok

scrape_callback1

okokok

scrape_callback2

okokok

URL_Normalizer

okokok

validateurl

>>> speedup

>>> Asyncio

>>> Concurrent

>>> Multiprocessing

>>> Parallel

okokok

Crawler_Parallel_All

>>> Pipelined

>>> thread

Crawler_Threaded_All

okokok

Crawler_Threaded_All1

okokok

threaded_barbuza

>>> pycos

G:\000webcrawlerproject\Python\0000MyScrapyProjects

More info check this file.


cracking

Web and IT Technologies

黑客技术

since 2011-10-02

Tenable Nessus Home Activation Code

12/30/17 at 4:29 PM More Information

From: Nessus Registration

Thank you for registering your Nessus scanner with Tenable. The Nessus Home subscription will keep your Nessus scanner up to date with the latest plugins for vulnerability scanning.

(Note: If you use Nessus in a professional capacity, you need a Nessus subscription.)

Your activation code for the Nessus Home is
9754-D624-4D15-2237-88B5

This is a one-time code. If you un-install and then re-install Nessus, you will need to register the scanner again and receive another Activation Code.

Activating your Nessus Home Subscription
Activate your subscription by entering the Activation Code using the procedures below:

After the initial installation of Nessus, the final process will load a local configuration page in your default web browser. This page will begin a brief process to set up the scanner including creating an account, registering the scanner with your activation code, specifying a proxy (optional), downloading the plugins, and initializing Nessus for use.

Please consult the Nessus 6 Installation guide located at http://www.tenable.com/products/nessus/documentation for more information on this setup process.

No Internet Access on your Nessus system?
If your Nessus installation cannot reach the Internet, you will need to follow an alternate procedure to get the URL and challenge code for downloading the latest plug-ins. You can find offline registration instructions at:

http://static.tenable.com/documentation/Nessus_Activation_Code_Installation.pdf

Need help or more information?
If you have any questions, visit the Nessus discussion forum at https://discussions.tenable.com/.

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Websources
@@@@@@@@@@@@@@@@@@@@@@@@@@
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@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@
PDF
@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@

@@@@@@@@@@@@@@@@@@@@@ 已阅不过比较重要所以保留
000Sikorski 恶意代码分析实战 p735

okokok

Beaver Hacking For Dummies p387

okokok

Beaver Hacking Wireless Networks For Dummies p387

@@@@@@@@@@@@@@@@@@@@@ 已阅不过比较重要所以保留
Deng 黑客攻防实战编程 p375.pdf
74

okokok

Erickson HACKING THE ART OF EXPLOITATION 2ND EDITION p492

Copyright ? 2008 by Jon Erickson

okokok

Harper Gray Hat Hacking p721

??????????????????????????

Seitz Black Hat Python p193

Python Programming for Hackers and Pentesters
Justin Seitz

codes:

http://nostarch.com/blackhatpython/

https://www.nostarch.com/download/BHP-Code.zip

okokok

Seitz GRAY HAT PYTHON p220

okokok

Stuttard The Web Application Hacker’s Handbook p914
Second Edition
Finding and Exploiting Security Flaws
Dafydd Stuttard
Marcus Pinto

@@@@@@@@@@@@@@@@@@@@@ 已阅不过比较重要所以保留
Wang 走进计算机病毒 p457.pdf
86
Wang 走进计算机病毒 p451

okokok

Weidman Penetration testing p531

Georgia Weidman 2014

Codes

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@@@@@@@@@@@@@@@@@@@@@@@@@@@
木马，蠕虫与病毒
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@@@@@@@@@@@@@@@@@@@@@@@@@@@

Writing anti censorship codes

Writing circumventing codes

Writing gfw bypassing codes

Writing anti gfw codes

developing anti gfw tools

anti gfw codes in python

anti gfw codes in java

网银安全工具套装

百度 p

online banking security toolkit

网银安全软件

百度 p

online banking security software

IBM TRUSTEER RAPPORT

IBM Trusteer Rapport is a FREE security software that protects your online banking communication and is recommended as an additional layer of security to any anti-virus software you currently use.

银行木马

百度 p

bank trojans

木马

Carbanak Carbanak木马

Carberp

Carberp leaks

data-stealing Dridex木马是影响金融业安全的最大威胁

Dridex source code

FlokiBot

https://github.com/vrtadmin/flokibot

ZeuS（宙斯）

逆向勒索软件

技术

内存截取（RAM scraping）

定制的 dropper

stealthy-dropper

混淆技术

脱壳

IDA

IDAPython

ASP

assembly

My first assembly shellcode

BASIC_VisualBasic

okokok

Worm Writing Tutorial

batch_shell

okokok

How to write a Trojan Horse

okokok

How to Write an RFID Worm

okokok

Writing Worms for Fun or Profit

okokok

研究如何制作AUTORUN木马病毒以及扩散方式

ccppcsharp

Trojan in c c++

>>>CinaRAT

>>> SRIKANTH Space_Eater

okokok

SRIKANTH SpaceEater

?????????????????????????

>>>theZoo-master

G:\0000websecurity\ZZZCodes\ccppcsharp\theZoo\theZoo-master\malwares\Source\Original\Carberp

okokok

anti_rapport

BC

》》》》》

BJWJ

BSS

BinToHex

BlackJoeWhiteJoe

bootkit

bootkit.old

BootkitDropper

Demo_Cur2

Demo_Cur3

Demo_cur

DllLoaderHook

DllLoaderHook1

DropSploit

DropSploit1

FakeDllAutorun

GrabberIE_FF

hvnc_dll

igrdemodll

InjectDLL

keys

Locker

Mini

ms0073

NodInject

OCR

OffInet

portforw

rdp xpterm

RemoteCtl

schtasks

sert

SkypeSMS

talk

Worm

okokok

Dvey C++ Very Simple Trojan

okokok

Raju Trojan Programming for beginners in C#

okokok

Ramesh How to Make a Trojan Horse

okokok

Vision 分析一个linux下的蠕虫 1999-8-15

zwclose7 ZeroX virus C

Delphi

Flash

okokok

黑客教你如何制作生成Flash木马程序

Java

Trojan in java

okokok

>>>Trojan-master

Javascript

Objective-C

PHP

Perl

python

Trojan in python

okokok

>>>basicRAT-master

>>>evilBunnyTrojan-master

>>>Placeholder source

>>>placeholder-master

okokok

>>>Python-Virus-master

?????????????????????????

>>>spyrat-master

okokok
decepti0n Python Keylogger.txt

FlokiBot 银行木马详细分析.txt

okokok
How to Make a Simple Computer Virus with Python.txt

okokok
How to write a Linux virus in 5 easy steps.txt

okokok
jain Placeholder Trojan Writing a Malware Software.txt

okokok
Python编写简易木马程序.txt

okokok
Python编写简易木马程序2.txt

okokok
python之键盘监听木马（SMTP信箱收取监听结果、修改注册表自启动）.txt

okokok
trojan horse program.txt

okokok
VortX Python Virus Writing Tutorial.txt

Ruby

Visual Basic Scripting


Untitled Document

Web and IT Technologies

since 2000-1-1

Programming

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Programming >>>
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

@@@@@@@@@@@@@@@@@@@@@@@@@
Assembly >>>
@@@@@@@@@@@@@@@@@@@@@@@@@

>>>masmhelp

okokok
asmintro.chm
okokok
DateTime.chm
okokok
fpuhelp.chm
okokok
hlhelp.chm
okokok
imdialog.chm
okokok
masm32.chm
okokok
masmlib.chm
okokok
opcodes.chm
okokok
qeditor.chm
okokok
topgun.chm
okokok
VKDebug.chm

>>> RadAsm指南 >>>

okokok
RadASM_guide_1

RadASM_guide_2
4
RadASM_guide_3

okokok
RadASM.chm
okokok
RadASM.txt
okokok
RadASM1.chm
okokok
RadASMini.rtf
okokok
ReadMe.txt

okokok
Blum Professional Assembly Language p577.pdf

okokok

Carter PC Assembly Language p174
Paul A. Carter
January 15, 2002

okokok

Dandamudi Introduction to assembly language programming for pentium and RISC processors p701

http://service.scs.carleton.ca/sivarama/asm_book/

http://www.scs.carleton.ca/~sivarama/org_book/

okokok

Duntemann Assembly Language step by step p469

okokok
Duntemann Assembly Language step by step p645
Jeff Duntemann

okokok

Hashmi Computer Architecture and Assembly Language Programming p193

??????????????????????????

??????????????????????????

Hyde The Art of Assembly Language p1426

Randall Hyde

226

okokok

Hyde 汇编语言编程艺术清晰版 p794
21

扫描版，无法复制

okokok

Intel 8080-8085 Assembly Language Programming Manual p224

okokok

Intel 8080-8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL p222

??????????????????????????

??????????????????????????

okokok

IRVINE Assembly Language for x86 Processors p873

Seventh Edition
KIP R. IRVINE

15.1

from end to beggining

okokok

Jorgensen x86-64 Assembly Language Programming with Ubuntu p368

okokok

Kauler WINDOWS ASSEMBLY LANGUAGE & SYSTEMS PROGRAMMING p421
16- and 32-bit low-level programming
for the PC and Windows
2nd edition
bY
Barry Kauler
Lecturer, Edith Cowan University
M.Sc.(EE), C.Eng.

??????????????????????????

Microsoft MASM_Programmers_Guide.chm
Chapter 1
Understanding Global Concepts

okokok

Oracle x86 Assembly Language ReferenceManual p82

March 2010

okokokokokok

Wang王爽 汇编语言_第3版 p354

okokok

Wang王爽 汇编语言_第2版 p351
46

okokok

Wang王爽 汇编语言_第1版 p326

扫描版，无法复制

扫描版，无法复制

okokok

Yang杨季文 80x86 汇编语言程序设计教程 p540

图形缺失，可复制

okokok

汇编语言教程.chm

@@@@@@@@@@@@@@@@@@@@@@@@@
ccpp >>>
@@@@@@@@@@@@@@@@@@@@@@@@@

okokok
cplusplus.com Complete C++ language tutorial p187

?????????????????????????????????

?????????????????????????????????

?????????????????????????????????

okokok

Davis C++ For DUMMIES p435.pdf

356

backward - from end to beggining

okokok
Downey How to think like a computer scientist p189.pdf

okokokokokok

Drozdek Data Structure And Algorithms In C++ p664

okokok

Fundamental Data Structures p376

Goodrich Data Structures and Algorithms in C++ p738

okokok

Halterman Fundamentals of Programming C++ p647.pdf

python.cs.southern.edu/cppbook/progcpp.pdf

http://python.cs.southern.edu/cppbook/

Richard L. Halterman
School of Computing
Southern Adventist University
March 31, 2016

260

okokok
Hekmat C++ Essentials p311.pdf

okokok

Jones The New C Standard p1612.pdf

okokok

Kernighan The C programming Language p295.pdf

okokok
Kirch-Prinz A Complete Guide to Programming in C++ p846.pdf

okokok

Malik Data Structures Using C++ p945

okokok

Morin Open Data Structures (in C++) p336

XXXXXXXXXXXXX

Oualline C++ Hackers Guide p231

Oualline Practical C++ Programming p549.pdf

okokok
PERENS C++ GUI Programming with QT3 p464.pdf

okokok
Perforce CC++ API User Guide p330.pdf

okokok
Rasheed C# School p338.pdf

okokok

Shaffer Data Structures and Algorithm Analysis Edition 3.2 (C++ Version) p613

okokok
Soulié C++ Language Tutorial p144.pdf

???????????????????????????
Valsamma C PROGRAMMING FOR MATHEMATICAL COMPUTING p152

okokok
Vasudevan C++Programming HOW-TO p59

okokok

Weiss Data Structures and Algorithm Analysis in C 1994 p492

Weiss Data Structures and Algorithm Analysis in C++ p654

okokok

Wiegand Teach Yourself C++ in 21 Days p772.pdf

okokok

Wirth Algorithms and Data Structures p179

@@@@@@@@@@@@@@@@@@@@@@@@@
Delphi >>>
@@@@@@@@@@@@@@@@@@@@@@@@@

Delphi 网络爬虫
Delphi web crawler

okokok
>>>DelphiHelper20
Delphi笔记

>>>DelphiProgrammingHelper
需要安装？？？

okokok
>>>Delphi编程技巧
delphis1.chm
delphis2.chm
delphis3.chm
delphis4.chm

okokok
>>>Delphi好帮手

>>>learndelphi
需要安装？？？

huanghw DELPHI编程手册 p6022
39

金石通工作室安世伟 编程魔法师DELPHI 入门实战百例 p297.pdf
101

okokok
李文池 Delphi程序设计基础 p392

刘啸 Delphi高级编程 p376.pdf
192

@@@@@@@@@@@@@@@@@@@@@@@@@
Java >>>
@@@@@@@@@@@@@@@@@@@@@@@@@

http://blog.csdn.net/wusuopubupt/article/details/7539761/
https://zhidao.baidu.com/link?url=cwXCqIGp9eSuoS3boiemC2TlXlfHuWI_OaY28M-nWhgo4AwkRwd0r8OhZGMA0dRU9I5sLT-Rwarda-ALy9lIjq
http://blog.csdn.net/xiaogugood/article/details/17435649

Visual Editor Project(VEP)

如何使用Eclipse开发用户图形界面（类似VC拖放控件功能） Eclipse+WindowBuilder Pro SWT Designer———功能十分强大的Swing图形化编程插件。如果还要想进行Google Web Toolkit开发的化，即GWT Designer。直接到.instantiations.com/下载WindoBuilder Pro，里面包含了SWT Designer,Swing Designer,GWT Designer的所有插件。注意下载的时候要下载跟自己的Eclipse对应版本的WindowBuilder Pro。

Java Workshop
NetBeans
Sun Java Studio 5
Borland 的JBuilder
Oracle 的JDeveloper
IBM的Visual Age for Java
BEA 的 WebLogic Workshop
WebGain 的Visual Cafe for Java
Macromedia的JRUN
JCreator
Microsoft VJ++
IntelliJ

SWT Designer
一直用SWT-Desinger感觉还不错
!!!!!!!!!!!!!!
WindowsBuilder Pro
NaviCoder IDE for Java
建议下载MyEclipse7.0版本的，里边集成了许多常用的开发插件，包括swing的界面开发插件。
在Eclipse中使用SWT进行界面设计

Downey Think Java How to Think Like a Computer Scientist p266
Allen B. Downey

TutorialPoints Java tutorial p549

???????????????????????????????

Weiss Data structures and algorithm analysis in Java p636

16

@@@@@@@@@@@@@@@@@@@@@@@@@
Python >>>
@@@@@@@@@@@@@@@@@@@@@@@@@

python 2 代码 python 3

E:\2Webscripts\python\python360\Tools\scripts\python 2to3.py?

python setup.py install

okokok

Chun Core Python Programming p766

Wesley J. Chun

okokok

Downey Think Python How to Think Like a Computer Scientist p240

okokok

Duffy Learning Penetration Testing with Python p474

okokok

Fangohr Introduction to Python for Computational Science and Engineering p167

okokok

Fredslund Introduction to Python Programming p171

c Jakob Fredslund

okokok

Halterman Fundamentals of Programming Python p669

DRAFT
Richard L. Halterman

okokok

Halterman LEARNING TO PROGRAM WITH PYTHON p283

Richard L. Halterman

okokok

Harrington Hands-on Python Tutorial p191

Release 1.0 for Python Version 3.1+
Dr. Andrew N. Harrington, Loyola University Chicago

okokok

Harrington Hands-On Python p138

okokok

Harrington Hands-On Python p139

okokok

Heinold A Practical Introduction to Python Programming p263

Brian Heinold

okokok

Hetland Beginning Python From Novice to Professional 2nd Edtion p667

http://hetland.org/writing/

okokok

Hetland Python基础教程第2版 p491
51

okokok

Jackson Learning to Program Using Python p215

Cody Jackson

okokok

Kuhlman A Python Book: Beginning Python, Advanced Python, and Python Exercises p278

Author:
Dave Kuhlman
Contact:
dkuhlman@davekuhlman.org
Address:
http://www.davekuhlman.org

okokok

Langtangen A Primer on Scientific Programming with Python p736

Hans Petter Langtangen

okokok

Lott Functional Python Programming p361

okokok

Lusth The Art and Craft of Programming Python Edition p141
John C. Lusth

okokok

Lutz Python学习手册 p689.pdf

122

okokok

Lutz Learning Python 5th Edition 2013 p1594

781

okokok

Lutz Programming Python 4th Edition 2010 p1628

okokok

Matloff Fast Lane to Python p167
A quick, sensible route to the joys of Python coding
Norm Matloff

okokok

Matthes Python Crash Course p562

okokok

python279rc1

??????????????????????????

python364python364

okokok

Rossum Python Tutorial p136
Release 3.2.3
Guido van Rossum
Fred L. Drake, Jr., editor

okokok

Scellato Network Analysis with Python p51

okokok

Severance Python for Everybody p247

Exploring Data Using Python 3

Charles R. Severance

okokok

Shipman A Python 27 programming tutorial p68

okokok

Summerfield Programming in Python 3 p636

A Complete Introduction to the Python Language
Second Edition
Mark Summerfield

okokok

Sweigart Hacking Secret Ciphers with Python p442

okokok

Tutorials Python programming language p443

Wing IDE>>>
okokok
Wing IDE Reference Manual p541
okokok
Introduction for New Users p56
okokok
How-Tos p97

wingide-manual-en-letter

wingide 6 算号代码keygen

http://blog.csdn.net/hutao1101175783/article/details/73009044

http://blog.csdn.net/XiaoYaoLangZhi/article/details/48042183

http://blog.csdn.net/u011128775/article/details/70140255

WingIDE 5 在Python 3.6 上的运行

WingIDE 5 支持Python 3.6 吗

Wing Pro - Version 5.1.12-1 - Released 2016-06-17

Wing supports CPython 2.5 through 3.5, Stackless Python 2.5 through 3.3, and
cygwin Python 2.5 through 2.7.

用wing IDE 总是提示找不到python

Wing 101 - Version 6.0.9-1 - Released 2017-12-13

Wing Personal - Version 6.0.9-1 - Released 2017-12-13

Wing Pro - Version 6.0.9-1 - Released 2017-12-13

Wing IDE 6.0.9-1

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!okokok

Wing ide 6.0 注册 ，python 3.6环境

https://www.cnblogs.com/zhongtang/p/7747032.html

直接切入主题，套路如下：

1、选择手动输入license

license number输入：CN123-12345-12345-12345

2、在下一步中，选择第二项，拷贝的request code

3、运行下述脚本：

其中licenseid 输入：CN123-12345-12345-12345

Request code 输入：第二步获取的值。

得到激活码。

okokok

Zelle Python Programming: An Introduction to Computer Science p261

John M. Zelle, Ph.D.

33

okokok

Ziadé Expert Python Programming p372
Learn best practices to designing, coding, and
distributing your Python software
Tarek Ziadé

PyScripter-Portable>>>

okokok
PyScripter - a Python IDE
okokok
Python for Win32 Extensions Help
okokok
PyScripter.chm

@@@@@@@@@@@@@@@@@@@@@@@@@
VB >>>
@@@@@@@@@@@@@@@@@@@@@@@@@

.NET / Visual Basic

Visual Studio

https://www.visualstudio.com

You can write your .NET apps in C#, F#, or Visual Basic

VB6

VB2015

VB7.0

VB.net

Visual Basic激活：

   序列号: e5kr-jg48a-ab3a3
授权钥匙：.7z-zex

    产品编号：CPE1360CPFS180.BCB_6 C++BUILDER 6 Enterprise

    SN:111-1111111

    S/N:425-0052536


Untitled Document

Web and IT Technologies

翻墙/隐私

since 2009-4-1

IPv6

Bypassing the GFW with IPv6 and proxying all IPv4 traffic

I hope I'm in the right forum for this kind of question. I'm in China and as you're probably all aware, the Great Firewall (GFW) blocks a lot of websites. Surprisingly, when using the IPv6 connection provided by CERNET (academic university network), I can bypass GFW and access blocked websites such as google, youtube, facebook, twitter, ...

Unfortunately, not all websites support IPv6 yet, so disabling IPv4 is not an option as it makes lots of websites inaccessible (also Skype won't work without IPv4).

Is there an easy way to proxy/tunnel/whatever all IPv4 traffic through my IPv6 connection? I found a website, sixxs.net, that kinda does what I'm searching for, but I'd like to have this functionality on an OS-level (like a VPN).

You are asking for how a client which is effectively IPv6-only can connect to IPv4-only sites. NAT64 is designed to allow IPv6-only clients to connect to IPv4-only servers. In order to use NAT64 you also need to use DNS64 and/or 464XLAT. It is possible for 464XLAT to be autoconfigured using information from DNS64.

There are public NAT64 installs in various places around the internet, sometimes these will also provide a public DNS64. The first showing when I did a search was this deploy360 page which lists three DNS64 addresses. Of those 2001:67c:27e4::64 was the only one working for me.

If you configure your device to use 2001:67c:27e4::64 as your DNS server and disable IPv4, you will be able to access IPv4-only sites through the NAT64. You can also do your own search for providers, the one I found is certainly not the only public NAT64+DNS64.

This relies on the client software you use to support IPv6. If you need to use client software without IPv6 support, you need 464XLAT support on your device. 464XLAT will translate IPv4 traffic from the application to IPv6 and send it to the NAT64 which translates it back to IPv4.

There are a number of mechanisms that are designed to ease the transition from IPv4 to IPv6. There is a good explanation of them here on the IPv6 website.

I think that all of the OS's have drivers for all of the main methods that require them. If I look at my own Windows PC network configuration for example using ipconfig /all. I can see both an external and internal ISATAP driver configured.

These work at the OS network driver level and so should be transparent.

One of the oldest IPv6 Tunnel Brokers https://tunnelbroker.net/ also has a description here about using brokers.

Friday, August 01, 2008

Use IPv6 to bypass GFW

First, of course, you have to get IPv6 access and GFW at the same time. The best practice will be to be physically in China. Then no matter where you go, the greatest firewall in the world will protect you from unhealthy sites like wikipedia.org, bbc.co.uk and blogspot.com. The IPv6 access is trickier to obtain. The IPv6 access service from go6.net and the website itself are banned, so you will have to find an IPv6 tunnel broker or VPN service provider yourself. Most of the other providers requires you to register and provide genuine personal and usage information. Sixxs.org even requires you to write a proper article which will be reviewed by human! Among them a good choice will be he.net. Their network is fast and you have about 10 tunnel broker servers to choose from. The registration is relatively simple and get your tunnel right away. The only problem is you have to manually update your IPv4 address if you are using dynamic address.

After you have established the connection to IPv6 network, try access ipv6.google.com. If you see the page, then congratulations and process to the next step. If not, check if your DNS supports resolving IPv6's AAAA records. OpenDNS.com provides free DNS service that is safe for this purpose.

The third step is simple: when you are trying to visit a banned site, add ".sixxs.org" after the domain name in the url and press enter. E.g. change http://bannned.site.xxx/bad.page to http://bannned.site.xxx.sixxs.org/bad.page. The service is reasonably fast and GFW currently does not scan IPv6 traffic.

I have also written an URL script to do this for you:
javascript:var%20loc=document.location;loc.replace(loc.protocol+"//"+loc.hostname+".sixxs.org"+loc.pathname+loc.search)
You can bookmark this url and click it each time you want to go through IPv6.
You can also use the script with Greasymonkey to make the process automatic.

Subscribe to this feed ? Save to del.icio.us ? Digg This! ? Blog This

Posted by Bill Chen at 22:29

Labels: IPv6, Network

Do you ever tried create ipv6 channel behind the ADSL router ?

I tried once on he.net, register account and setup a channel, but it doesn't work while I follow the guide commands on WinXP. Is it possible to do that behind ADSL router? does the WAN address of router should provide for the endpoint address?

Thanks advance if you could provide more tips.

Bypassing the GFW with IPv6 and proxying all IPv4 traffic

Use IPv6 to bypass GFW

https://sixxs.net/

???????????????

http://www.sixxs.org/

???????????????

https://go6.net/

http://www.blogger.com/ipv6.google.com

http://ipv6.com/articles/gateways/IPv6-Tunnelling.htm

http://www.he.net/

https://tunnelbroker.net/

NAT64

DNS64

http://www.internetsociety.org/deploy360/blog/2013/03/open-public-test-of-nat64dns64-at-go6lab/

If you configure your device to use 2001:67c:27e4::64 as your DNS server and disable IPv4, you will be able to access IPv4-only sites through the NAT64. You can also do your own search for providers, the one I found is certainly not the only public NAT64+DNS64.

This relies on the client software you use to support IPv6. If you need to use client software without IPv6 support, you need 464XLAT support on your device. 464XLAT will translate IPv4 traffic from the application to IPv6 and send it to the NAT64 which translates it back to IPv4.

how to connect to ADSL with ipv6

宽带可用ipv6吗

移动宽带可用ipv6吗

移动宽带如何使用ipv6

http://pt.zhixing.bjtu.edu.cn/

http://test-ipv6.com/

http://ipv6.jmu.edu.cn/

http://ipv6test.google.com/

中国电信ipv6怎么开通_电信宽带下连接IPV6的方法

来源：网络整理 作者：2017年12月26日 14:12

电信宽带是中国电信运营商向电信用户提供接入互联网服务的总称，以“天翼宽带”统一的业务品牌向用户呈现，通过统一的天翼宽带客户端，向用户提供无缝覆盖宽带接入服务，并集成统一通讯录、短信、天翼Live、网盘、安全专家、天翼视讯、189 邮箱等简便而实用应用，满足用户高速上网、收发电子邮件、网上炒股、网上购物、视频点播、网络游戏、远程教育、远程医疗、远程办公、家庭办公、电子商务等业务需求。

    接入方式

    有线方式

    1、ADSL

    ADSL（Asymmetric Digital Subscriber Line非对称数字用户线环路）被誉为“现代信息高速公路上的快车”。常用下行速率高达8Mbps，上行速率也达640Kbps，具有速度快、频带宽、性能优、覆盖范围广等特点。

    2、LAN

    采用以太网技术，为用户提供FTTZ（光纤到小区）+LAN 网线到户的宽带接入。基本做到千兆到小区、百兆到居民大楼、十兆到用户。不要使用Modem、可靠性高，仅需一块以太网卡即可轻松接入互联网。

3、互联网专线

    互联网专线接入业务是指为客户提供光纤接入互联网专用链路，直接连接中国电信宽带网络，满足10兆至1000兆速率需求，实现方便快捷的高速互联网上网服务。

    4、光纤接入方式

    光纤接入是直接接入网中传输媒介为光纤的接入网。光纤接入网从技术上可分为两大类：有源光网络（AON，AcTIve OpTIcal Network）和无源光网络（PON，Passive OpTIcal Network）。有源光网络又可分为基于SDH的AON和基于PDH的AON；无源光网络可分为窄带PON和宽带PON。光纤多采用FTTX接入方式，FTTX不是具体的接入技术，而是光纤在接入网中的推进程度或使用策略。其中根据光纤深入用户群的程度，可将光纤接入网分为FTTC（光纤到路边）、FTTZ（光纤到小区）、 FTTB（光纤到大楼）、FTTO（光纤到办公室）和FTTH（光纤到户），它们统称为FTTX。［2］

    光纤接入网，特别是FTTH光纤接入网，具有频带宽、容量大、信号质量好、可靠性高、可以提供多种业务乃至未来宽带交互型业务、是实现B-ISDN的最佳方案等优点，因而被认为是接入网的发展方向。［3］

    无线方式

    无线宽带是中国电信WIFI、天翼3G、CDMA1X网络基础上无线高速上网业务，您可使用电脑上的WiFi网卡和3G数据卡，使用统一的无线宽带客户端软件，选择WiFi、天翼3G、 CDMA1X网络接入互联网，享受高速的无线上网服务及丰富网络服务。

    中国电信ipv6怎么开通

    按组合键win+x

    选择以管理员身份打开命令提示符

    然后依次键入

    netsh

    interface

    ipv6

    isatap

    set router 202.112.26.246

    出现确定字样，可以关掉命令提示符就能使用ipv6服务。

    电信宽带下连接IPV6的方法

    首先进行操作系统下的IPV6配置：

    C：\Documents and SetTIngs\Administrator》netsh（开始》运行》netsh，win7下需管理员身份运行貌似）

    netsh》int

    netsh interface》ipv6

    netsh interface》ipv6》install （WIN7不需要这个步骤，跳过这步 ）

    netsh interface ipv6》isatap

    netsh interface ipv6 isatap》set router isatap.sjtu.edu.cn （此处利用上海交大的IPV6通道，用其他高校通道亦可）

    （上述内容引自网页http://hi.baidu.com/lgibm5/item/09240fe5d68c093e4ddcaf4e）

    附其他高校通道：

    华中大 isatap.hust.edu.cn （218.199.111.9）

    清华 isatap.tsinghua.edu.cn （59.66.4.50）

    上交 isatap.sjtu.edu.cn （202.120.58.150）

    北邮 isatap.bupt.edu.cn （211.68.71.43）

    湖南大学 210.43.96.186 210.43.96.182

    四川大学 isatap.scu.edu.cn （202.115.39.98）

    西安建筑科技大学 isatap.xauat.edu.cn （222.24.128.238）

    平顶山大学 211.69.16.36

    河南工程学院 211.84.0.1

    郑州大学 222.22.32.161

    华南农大 isatap.scau.edu.cn （192.168.253.49）

    中国人民大学 isatap.ruc.edu.cn

    安徽农大 isatap.ahau.edu.cn

    （上述内容引自http://tieba.baidu.com/p/2201769988）

    做了上述配置之后好像还不行，找了个类似代理外挂的东西，Veno：

    下载地址：http://www.veno2.com/downloads/down.php

    不用注册，直接安装就能用默认用户名密码登陆链接。

    然后找个IPV6的网址打开试试，比如

    http://ipv6.tsinghua.edu.cn/resource/

    （打开这个网址，右边栏会提示使用的是IPV4还是IPV6，其他测试IPV6的网址也可以）

    或者北邮人BT：

    http://bt.byr.cn/index.php

    8M的电信宽带，下载速度最大能到600KB。

    也许上述方法弄复杂了，欢迎行家指点高招，此地抛砖。

怎样安装IPV6 进行测试？

我们学校已经在测试IPV6了，想问下怎么在自己机器上安装IPV6协议，还有，安装了怎么才看的到自己是不是IPV6。安装以后有什么好处？

安装IPV6 进行测试的步骤：
    XP下的配置方法与2003下配置方法基本相同。只是XP下必须先安装上IPV6协议，并且至少升级至SP1。配置过程如下：
    1、安装IPV6协议
C:\>ipv6 install
    2 、查看端口信息
首先使用 ipv6 if 指令查看各接口状态，一般情况下，你会看到如下显示：
Interface 4 (site 1): 本地连接
……
Interface 3 (site 1): 6-over-4 Virtual Interface
……
Interface 2 (site 0): Tunnel Pseudo-Interface
……
Interface 1 (site 0): Loopback Pseudo-Interface
……
Interface 4 是本地的实际端口，其他三个都是虚拟端口，值得注意的是 Interface 2 ，它是 Auto-Tunnel 的端口，在接入配置中我们要用到。
3、如果是在纯IPV6网络（或IPV6和IPV4双栈网络）中，你就可以自动获得IPV6地址，可以访问IPV6网站了。
你也可以设置固定的IPV6地址，方法如下：
C:\>netsh
netsh>interface ipv6
netsh interface ipv6>add address "本地连接" fe80:a520:1314::1
/* 设定固定的IPv6地址，“本地连接”是指你的机上建立的某个连接的名称 */
netsh interface ipv6>add dns "本地连接" 2001:251:e101:0::2
/* 设定IPv6 DNS地址 */
4、如果你是在IPV4网络中，你需要与IPV6网络进行隧道连结。需要对端用户的配合来建立隧道，对端可以是网络中心的路由（交换）器，也可以是另一台PC机。无论如何，以下信息都是必须的：
。你的可路由到对端的IPV4地址，假定为 210.35.168.100
。对端的IPV4地址，假定为 210.35.240.24
。对端的IPV6地址，假定为 2001:250:6C01:1000：
    1
。对端分配给你的IPV6地址，假设为 2001：250：6C01：1000：
    2
本端配置如下：
配置隧道： ipv6 ifcr v6v4 210.35.168.100210.35.240.24
为本机配置 ipv6 地址： ipv6 adu 4/2001：250：6c01：100：
    3、注： 第4个Interface端口的地址设为2001:250:6c01:100::2，这种配置的时候，一般指定为实际存在的Interface号，如果只有一块网卡的话，应该是4号Interface。 */
为本机配置路由： ipv6 rtu ::/0
    4、2001:250:6c01:100::1
对端（服务端）如果是网络中心，请看路由器配置。如果对端也是PC机，根据系统不同，按本站所列各操作系统的配置方法配置。
    5、如果要用WindowsXP做路由器, 则还需要打开其他接口的转发功能. 例如, 如果接口4是你的网卡, 你所在的局域网就是挂在这块网卡下的, 那么你还需要打开它的转发功能: ipv6 ifc 4 forwards
根据需要，你可能还愿意打开某些接口的路由广播功能
    6、测试：
ping隧道对端地址，能ping通即配置成功。
ping 2001:250:6c01:100::1
或跟踪一下到www.kame.net的路由，如果出现的是IPV6地址，并能最终到达，即OK
tracert www.kame.net
IE访问www.kame.net时应能看到页面上的乌龟是活动的。如果乌龟不动，说明你走的还是IPV4网络。

烟台移动光纤宽带如何开启IPV6

步骤一：安装IPv6协议：打开控制面板，依次进入“网络和Internet”- “网络连接” - 右击“本地连接”，在弹出的属性对话框中点击安装，然后选择“协议”，点击添加，就可以将IPv6安装到项目列表中。

    步骤二：设置IPv6地址：打开控制面板，依次进入“网络和Internet”- “网络连接” - 右击“本地连接”，在弹出的属性对话框中双击“Internet协议版本6(Tcp/IP)，
在其属性框中选择手动，输入IPv6地址“3FFE:FFFF:7654:FEDA:1245:BA98:3210:4562”(由于IPv6处于测试阶段，因此可以自由输入确定其地址)。

    步骤三：测试IPv6设置：按“Win+R”打开运行对话框。输入CMD，在弹出的MSDOS窗口中输入“ipconfig”命令来查看本地的所有IP地址配置情况。

    步骤四：配置ISATAP隧道，完成后，打开浏览器，输入网址“http://ipv6.jmu.edu.cn/”进行IPv6的测试，在页面上，
如果能够看到一只跳舞的小老虎，则说明以IPv6访问该网页，如果小老虎不跳舞，则是以IPv4访问该网页。

如何使用ipv6上网_ipv6免流上网教程

来源：网络整理 作者：2017年12月26日 10:52

首先来说下怎么确认你是否可以使用ipv6。

    打开网络连接，打开你使用的网络，可以看到ipv6连接的状态，显示Internet，即为可用，那你可以继续往下看了。如果不可用，放弃吧，骚年，找其他途径去吧。

这里在提醒一下，像西电有的宿舍楼是需要宽带拨号后才能连接ipv6的，所以先去拨号。要注意一点，一般校园网都是计算ipv4流量的，拨号后也就是说你的校园网已经登录了，那可以要走流量了，所以注意将ipv4关掉。

    同样打开网络连接，找到宽带拨号打开，显示如上图一样，点击属性，把ipv4协议前面的对勾去掉，ok你的校园网就不会走流量了。

好了来说下免流上网的方法：

    1、校园v6 https://xiaoyuanv6.com/

    这是一个使用ShadowSocks的VPN，每月3G流量，每日可签到，速度还可以，而且是可以翻墙的哦。

    需要下载ShadowSocks，教程比较简单，自己看下就可以了。

    2、马上六 http://www.mashang6.edu.cn/mashang6/MsDownload/

    这个比校园v6要简单，只需要下载客户端注册即可使用，不需要配置什么的。不过网速不稳定，早上用的人少，速度很快，可以下东西；用的人多了就很卡，不过凑合着刷刷网页查查资料还是够用的。

    3、六快拨 http://www.6kuaibo.com/

    和马上六差不多，使用也一样，打开客户端登陆就行，它比马上六的好处在于网速十分稳定，不过不充会员限速50K每秒。很稳定，可以玩LOL，十分推荐。

    另外还可以直接用ipv6上google、youtube什么的，你只要登上校园网有ipv6连接，打开这些网页就行了，都是不走流量的，可以放心的用。

    在查找了各式各样的解决方案后，发现租用VPS搭建shadowsocks server的方案最具有操作性

    实现方法

    这套方案是利用校园网对IPv6流量不计费的特点来实现省流量的目的，但是由于目前支持IPv6的网站太少，无法以IPv6直接访问网站。因此我们需要靠一个中间媒介来帮忙，这就是VPS（虚拟服务器）。需要注意的是，这台VPS是需要支持IPv6的，也就是VPS服务提供商能够分配一个公共的IPv6的地址。VPS以它自身的IPv4地址进行访问，然后通过IPv6与本机进行通信（这部分不计流量），实际上相当于流量统计都转嫁到VPS上面去，而不再计算到校园网的流量上。

    而为了能够从本地主机顺利连接到VPS上，我们还需要使用shadowsocks这个工具。shadowsocks的具体原理就不在此赘述了，有兴趣的朋友可以去wiki了解。

    工具准备

    1. VPS

    市面上有许多服务商提供虚拟服务器的租用，考虑到性价比，IPv6等因素，我将介绍最近比较流行的VPS。榴友可根据自身需要进行选购。

    推荐搬瓦工“Bandwagonhost”

    官网地址：点击进入

    这是小狼强烈建议的一款VPS，除了价格低廉外，它还支持一键式配置shadowsocks server，操作极其方便，很适合对linux不熟悉的人群。不过搬瓦工只有美国节点，对于有多节点需求的用户来说无法满足，同时，美国节点也意味着一定的延迟。

    Pros：1. 价格低，即使是取消了3.99刀年费的套餐，它仍然是三款当中最便宜的。

    2. 支持一键配置和重装，方便初学者。玩坏了马上重装，非常爽。

    3. 一次分配3个IPv6地址。（有些服务器是不提供IPv6的，选购的时候一定要看清楚）

    4.支持支付宝（简直做大死）

    Cons：1. 只有美国节点，多样性差，延迟可能较高

    2. 一键配置省略了很多细节，不利于日后配置（我到现在都不知道配置文件放在哪个目录）

    2. shadowsocks

    shadowsocks是一款基于socks5协议通信的网络传输软件。在VPS和你自己用的电脑上分别部署好ss服务器和ss客户端后，就可以进行代理商网，届时，你的电脑将以VPS的IP地址进行外网访问。

    shadowsocks分服务器版本和客户端版本。这里需要指出的时候，因众所周知的原因，shadowsocks的客户端不容易找到，在这里提供两个方法供读者参考：

    1. 虽然原作者的ss工程已经被清空，但是github上还保存有其他开发者保留下来的版本，其中就包括ss的客户端：https://github.com/shadowsocks/shadowsocks-windows/releases。这个版本的ss客户端是针对windows开发的，目前仍在维护中，笔者也正在使用这套客户端。不过需要注意的是，现在github的下载也是比较神秘，大概率会出现下载失败，更可靠的方法是把项目给clone到本地。

    2. 搬瓦工的一键安装界面上保留有ss原版客户端的下载地址。经过实测还是能下载下来，只不过版本号还停留在2.x，有点老旧了。如果是win10用户可能会出现无法连接的问题，推荐在github找有活跃度的项目。

    工具都介绍完了，接下来详细说一下安装和配置的过程。因为搬瓦工的配置相对简单许多，我先介绍一下搬瓦工从选购，安装OS，安装ss服务器整个过程。digitalocean的安装配置留在日后慢慢更新。

安装与配置

    1.租用VPS

    以搬瓦工为例，我们先登录到搬瓦工的官网

    如下图所示，这是搬瓦工的导航栏，红色标注的是比较常用的几个链接。

进入VPS hosTIng界面后，可以发现搬瓦工提供了不同等级的服务，看上去一大堆参数，不过我们只是搭建ss的话，只需要关心这么几项。一个是内存大小，考虑到以后折腾的需要（比如你哪天想用这个VPS建个个人网站啥的，或者对ss进行加速优化），可以选个大内存的。当然，512MB也足够使用了。

    另一个参数则至关重要，那就是VPS的虚拟化技术，搬瓦工提供KVM和OpenVZ两种方式，目前KVM是不提供IPv6地址的，想要靠IPv6免流，显然要选择OpenVZ的虚拟服务器。

因搬瓦工首页VPS的方案比较少，这里放上搬瓦工官网所有方案链接：

    下面为中文整理好的方案榴友们可以按需选购

    1.搬瓦工OpenVZ架构方案（支持IPv6可以免流）

    2.搬瓦工KVM架构方案（不支持免流，可以一键SS）

    3.搬瓦工CN2线路（不支持免流，可以一键SS）

    点击确认后，将会进入购买页面。再次确认这么几条信息，是否支持IPv6，支付周期（月度，季度，年度），机器地址（如果有多选，说明该VPS支持地点转移，以后被墙了可以换主机地址，当然这是后话了）。确认无误后，点击最下面的add to cart，进入支付界面

搬瓦工支持第一次购买与注册同步进行（真的贴心），意思就是我们可以在完成订单的同时顺便注册好我们的账号。

    注册账号需要填写个人信息，这里介绍一下注意事项。如果你不想暴露过多的个人信息，你只需要保证email，password还有country三个信息是真实的即可。就是图中红圈标出的几项。email是保证你能收到搬瓦工给你发来的服务器相关信息。country就填国内即可。

    虽然信息可以不真实，但是都要填上，而且不要瞎填（比如asdfghjk这种），最好是正确的汉字拼音。除了address2可以不填以外，其他都填上。还需要注意的一点就是支付方式，分别是paypal，alipay（支付宝），credit card（信用卡）。最方便当然是支付宝了，如果你有另外两个支付方式的话也可以选择。正确填写后，选择支付。稍等片刻后，你的邮箱将会收到搬瓦工的提示邮件，你的注册和VPS购买都已经完成，可以进行安装配置了。

2.为VPS配置ss服务端

    注意：一键安装操作只限于CentOS 6操作系统下，当然搬瓦工是默认安装这个系统的。如果榴友有自行配置操作系统的需要，则一键安装不适合你，其他系统的ss server安装过程我将在日后更新。

    在购买了VPS后，我们就可以进入VPS的管理界面了。点击首页的client area，登录刚刚注册的账号，进入账号界面，点击service，选择My Services。进入到VPS的管理界面。可以看到自己已经购买的VPS列表，要对某个VPS进行管理，点击“KiviVM Control Panel”进入。

    下图就是VPS的管理界面，我们在配置免流服务器的时候要使用两个功能，一个是激活IPv6地址，另一个是安装Shadowsocks Server。这两个过程都可以依靠这个控制界面轻松做到

首先我们激活IPv6地址。点击左侧的“IPV6 address”进入地址管理界面，搬瓦工提供三个IPv6地址，点击“random”按钮生成，然后点击“add”将其添加到主机配置中。然后返回到“Main Control”界面，点击“reboot”重启机器，重启后IPv6地址将被激活。可以在windows控制台程序中向地址发包测试连通性。命令格式为：Ping “IPv6地址”。如果收到响应，则说明这个地址已经可以正常使用了。

在激活号IPv6地址后，我们可以开始安装Shadowsocks Server，搬瓦工已经预先配置好了Shadowsocks的安装脚本了，因此shell命令不用咱们自己敲。同样是点击左侧导航栏上的“KiviVM Extras”一栏里的“Shadowsocks Server”。然后点击“Install”，稍等片刻，脚本执行完毕，刷新浏览器，页面将会变成：

可以看到，服务器已经在我们的VPS中运行了。注意到三个参数分别是Shadowsocks server encrypTIon（通信加密方式）， Shadowsocks server port（ss服务器监听的端口），以及Shadowsocks server password（密码），这三个参数非常重要，记下来，待会儿配置客户端要用。

.在客户机上安装并使用ss客户端

    既然已经在VPS部署好了ss服务器端，那么我们接下来进行客户端的安装配置。ss客户端虽然有多个发布源，每个源头又有不同的版本，但是基本的配置都大同小异，这里我就用上文提到的https://github.com/shadowsocks/shadowsocks-windows/releases这个发布者的ss客户端，版本号是4.0.6的这一版来进行演示。客户机的系统是Windows 10 1703版本。

    从github上下载下来后，我们解压，点击Shadowsocks.exe，它可能马上弹出服务器的编辑界面，也有可能最小化到管理区，这时我们在桌面右下方找到蓝色纸飞机的图表，点击右键，选择“服务器”-》“编辑服务器”。出现界面如图：

点击添加，会有一个空白的配置项，我们开始填写。图中红圈中的几个参数对应在搬瓦工VPS中提供的几项，服务器地址填写IPv6地址（有些教程提到IPv6地址左右两端需要加上“［］”，经本人测试，本教程中不需填写）；服务器端口对应填写Shadowsocks server port（一般是443）；密码填写服务器生成的Shadowsocks server password；加密方式选择与服务器一样的方式（默认是aes-cfb-256）。在上述必要的参数填写完后，可以为你的配置添加一个备注方便记住，比如“干死校园网”。除此以外，其他参数在自己不清楚作用的时候尽量不要擅自改动。填写完毕后，选择确认，此时客户端将以当前配置运行。

    为了让我们的网络访问全都依靠VPS，我们再设置一步：右键点击ss图标，选择“系统代理模式”，选择“全局模式”。

    如果配置正常，我们已经顺利连接上了ss服务器，可以以VPS的IP地址进行外网访问了。此时我们打开浏览器（以Chrome为例）。打开百度，输入“IP地址”。如果有如下显示：

说明你已经成功以VPS地址访问外网。实现了免校园网流量的上网行为了。

    如果这时你发现浏览器无法上网，我在此列出几条可能的情况，根据你的情况进行进一步的操作。

    1.查看你的ss客户端日志（ss图标右键-》帮助-》查看日志），看看客户端有没有给你提示错误，如果有，大概率是你的参数填的不对，请仔细核对服务端和客户端的参数是否有出入。

    2.如果你是windows 10用户，且ss客户端报告运行正常（只显示shadowsocks started）但无数据出入。这时候你可能遇到了win10的一些特性问题导致的软件不兼容。本人在遇到这个问题时采取了以下三个措施，从严重程度我分为三级，大家可以视自己的情况进行操作。

    第一级（浏览器或宽带连接设置的问题）：你可能使用的是Chrome浏览器，而chrome浏览器与shadowsocks的全局代理有冲突。这时，你可以选择加装chrome的代理插件，比如SwitchyOmega，相关教程自寻，此处不赘述；或者你使用其他浏览器，比如Edge或火狐。

    另外，值得注意的是，如果你使用的校园网是以拨号连接的方式进行的话，请将你的连接名改为全英文形式。

    第二级（shadowsocks客户端的版本过老）：搬瓦工提供的客户端版本就比较古老，而且已经不提供维护了，出问题在所难免，本例子使用的ss客户端则提供自动更新功能，如果你的版本不是最新的，请尝试更新你的ss版本。总之，保证你的ss客户端软件尽可能的新；

    第三级（可能是Win10的，VPS或其他问题）：如果前两步操作你都尝试过了仍然无法解决，请不要放弃，继续google寻求帮助。在尝试过一切努力后，再考虑将系统装回win7。毕竟重装系统是很大的事情，请不要轻言放弃。或者更换你的VPS服务提供商，比如digitalocean或vultur。这两个服务器的使用方法，我尽量尝试，给大家分享相关的教程。

    最后，如果你想保证你的连接只在IPv6下进行，请对你的宽带连接进行设置，将IPv4的协议关闭掉。这样做可能会导致你的ss代理无法正常工作（取决于DHCP的工作方式），或者是连接经常断开（我自身遇到的情况）。所以，请慎重操作。

    至此，shadowsocks两端的配置都完成了，大家可以尽情享受免流量的网上冲浪了。

    后续问题探讨

    尽管我们完成了免流量的上网操作，但是我们目前仍然有这么几个问题：

    1.除浏览器以外的互联网访问都无法使用shadowsocks代理。即是说其他应用程序任然会产生校园网的流量计费；

    2.各种各样的原因导致VPS的网速较慢，无法看视频；

    3.由于我们以国外IP访问，大部分的国内版权服务我们无法享用，比如网易云音乐、版权视频等。

    对于问题一，可以用proxifier，sockscap64等应用代理软件解决（网上有相应的教程，我也是拾人牙慧，就不单独出教程班门弄斧了）。

    问题二，可能涉及到服务器加速的相关技术，我在日后会进行研究，如果有成果，也会分享出来。

    问题三：版权问题目前来说比较棘手，因为像unblock youku这种插件是适用于肉身fanqiang的伙伴使用的，对于我们这种伪fq的同学并不适用，具体体现为系统代理与unblock youku插件不兼容导致代理失效，变回国内IP，产生流量计费。这个方法有待我继续研究。目前我没啥好的办法。

    小结

    校园本来就是求知的地方，而互联网就是我们探索世界的一个重要工具，校园网高昂的计费政策大大降低了我们探索未知世界的积极性。少年强则国强，年轻人网都上不去，怎么能算是合格的大学生呢？不管出于何种理由，限制上网流量都是既不应该的举措。

    闲话不多说，接下来我将针对目前方案进行完善改进，为各类问题提供解决的方法。也算是给各位在校学生做件好事吧~


Untitled Document

Web and IT Technologies

翻墙/隐私

since 2009-4-1

IPv6

http://www.elecfans.com/news/wangluo/20171226607587_a.html

http://www.360doc.com/content/13/1226/15/11924091_340282268.shtml

http://www.elecfans.com/news/wangluo/20171226607642_4.html

http://www.elecfans.com/news/wangluo/20171226607642_3.html

http://www.elecfans.com/news/wangluo/20171226607642.html

http://www.elecfans.com/news/wangluo/20171226607642_2.html

https://zhidao.baidu.com/question/1991332103430770507.html

https://zhidao.baidu.com/question/583995368.html

http://www.veno2.com/downloads/down.php?lang=cn

markchen@vfemail.net

fgh6r4utyjgj

helioslab@sina.com

http://www.elecfans.com/application/Communication/607717.html

veno 无法登陆

veno登录连接无效

普通非校园网用户如何使用IPV6连接网络？

(2012-04-11 11:14:17)

没试过，留存。

来源：winsoft.com

??? 目前我们使用的第二代互联网IPv4技术，核心技术属于美国。它的最大问题是网络地址资源有限，从理论上讲，编址1600万个网络、40亿台主机。但采用A、B、C三类编址方式后，可用的网络地址和主机地址的数目大打折扣，以至目前的IP地址近乎枯竭。

??? 随着电子技术及网络技术的发展，计算机网络将进入人们的日常生活，可能身边的每一样东西都需要连入全球因特网。在这样的环境下，ipv6应运而生。单从数 量级上来 ?IPv6普及说，IPv6所拥有的地址容量是IPv4的约8×10^28倍，达到2^128（算上全零的）个。这不但解决了网络地址资源数量的问题，同 时也为除电脑外的设备连入互联网在数量限制上扫清了障碍。

???

虽然ipv6在中国也有应用，但主要是存在于大学的校园网。而普通的宽带用户要如何体验ipv6呢？今天小编就给大家带来了几种简单的方法，希望能给大家上网带来便利~~?

第一步：如何安装IPV6。

方法一:（适用于adsl直接拨号上网的方式）

WindowsXp/2003/Vista/7的方法是，点击开始->运行，输入cmd 回车，

然后在弹出的命令框中照下面的样子输入命令，注意，是输入一行回车一下：

C:Documents and SettingsAdministrator>netsh

netsh>int

netsh interface>ipv6

netsh interface>ipv6>install

netsh interface ipv6>isatap

netsh interface ipv6 isatap>set router isatap.sjtu.edu.cn

?

Vista/Win7的方法是鼠标右键点击“开始－>程序－>附件－>命令提示符”，选择“以管理员身份运行”。

在新开启的【命令提示符】窗口中执行以下两条命令：

netsh interface ipv6 isatap set router isatap.sjtu.edu.cn

netsh interface ipv6 isatap set state enabled

执行完命令后，关闭所有浏览器，访问www.ipv6.org 看看你的页面。当你看到 You are using IPv6 from 2001:…… 时，你就已经成功地将你的网络环境改为了IPV6。（但小编后来发现，已经正常启用IPv6并能访问国外网站时，这里也提示的是You are using IPv4，这里原因未知哈。）

我用了上面的命令就已经成功了，记得要重新打开浏览器。

我在XP+ADSL/Win7+路由环境/Linux+路由环境下测试成功。有时候会遇到不成功的情况，请继续执行下面的命令。

C:Documents and SettingsAdministrator>netsh

netsh>int

netsh interface>ipv6

netsh interface>ipv6>install

netsh interface ipv6>6to4

netsh interface ipv6 6to4>set relay 202.112.26.246 enable

执行到这里，如果还没能打开Ipv6，可以尝试将所有域名记录加到本地hosts文件中（嗯……这个自行Google~~）。同时，建议你尝试将dns设置为”8.8.8.8″ 和 “8.8.4.4″。

注意：最好把防火墙、杀毒软件、360那些关掉(否则可能引起连接失败)。

方法二：（适用于各种上网方式）（小编极力推荐~）

这需要安装一个软件gogoCLIENT，下载页面（需注册）：http://gogonet.gogo6.com/profile/gogoCLIENT。这个软件有适用于Windows、Linux、mac各个操作系统使用的版本，根据实际情况下载。一般人的操作系统都是 Windows 32bit的。安装完成后，直接运行程序，所有的设置都用默认的，点connect就行了，连接成功后右下角会弹出一个连接成功的信息。

这个软件的原理是使用该软件的服务器作为中转访问ipv6的网络。我在Windows7/Linux+路由器上网环境下测试成功。能成功使用ipv6网络 后，你就可以用ipv6的方式访问Google了（http://ipv6.google.com/ncr，不加ncr可能会转到google.hk）， 不习惯英文的话，自己设置为简体中文页面，Google.com是多语言版本的。

如果你现在可以正常访问东北大学基于IPv6的BT站：bt.neu6.edu.cn和ipv6.google.com，就说明你现在的网络环境已经支持ipv6了！

第二步：修改Hosts文件。? ? 如果以上步骤不能够使你访问ipv6网络的话，那你还需要修改一下本地的hosts文件。所谓hosts，是一个没有扩展名的系统文件，可以用记事本等工 具打开，其作用就是将一些常用的网址域名与其对应的IP地址建立一个关联“数据库”。当用户在浏览器中输入一个需要登录的网址时，系统会首先自动从 Hosts文件中寻找对应的IP地址，一旦找到，系统会立即打开对应网页，如果没有找到，则系统再会将网址提交DNS域名解析服务器进行IP地址的解析。

当然，hosts文件需要各位看官自行google~（上文说过啦……）

最后为大家提供几个高校的IPV6服务器地址

isatap.tsinghua.edu.cn(清华大学)

isatap.shu.edu.cn (上海大学)

isatap.hust.edu.cn(华中科大)

isatap.sjtu.edu.cn (上海交大)

isatap.hust.edu.cn（中南大学）

???

将gogoCLIENT中的server address地址替换成以上高校地址就行了，然后点apply—— >点connect就替换完成了。（不过小编觉得软件中自带的服务器也很好用，无须修改，只当是备用的就好了）

实战体验：家庭宽带用户通过IPV6+HOSTS直连GOOGLE各项被墙服务[牧师著]

先简单回顾一下自己始自2000年的翻墙生涯，

1、最早翻墙的时候是2000年，那时是通过设置代理服务器的方法翻墙看BBC中文网；

2、不知道从啥时候起出现了WUJIE为首的网络三剑客，自打用了之后就爱不释手，这一情况一直持续到2009年10月WUJIE被功夫网小组破解之后；

3、后来又用过免费的PUFF，但有时能连有时不能连直到后来彻底挂了；

4、鉴于天朝网络形势一天天恶劣，能直接访问而不撞墙的好网站越来越少，牧师于2010年3月开始涉足VPN，一开始本想借此赚点小钱（毕竟功夫网的步步升级造成了网民们对VPN前所未有的市场需求），但很快被无私奉献的技术推感动从而毅然决然地改为努力普及公益性VPN，到目前可以说已经有了点成效。

使用了VPN之后翻墙变得很轻松，但由于流量的限制，看YOUTUBE视频一直是个头痛的问题，而且也会出现访问墙内站点速度慢的情况；

5、进入了2010年4月，经福建大学学生推友 @clientor 的悉心指导，我掌握了一种全新最为时髦的方法（IPV6+HOSTS）来上网，此种方法虽不是翻墙，但却可以让你在不借助任何代理软件和VPN/SSH的情况下，轻松访问被墙的各项GOOGLE服务，包括YOUTUBE，GOOGLE SITES，BLOGGER，PICASA等，而且你也可以享受许多IPV6的资源站点。

以下正文就介绍一下在WIN7操作系统下家庭电信宽带用户如何使用这一方法（IPV6+HOSTS），感谢 @clientor 的耐心指导。

什么是IPV6？说实话我也不知道，具体的可以去WIKI一下，据说这是未来趋势，可以解决IPV4（最普通的网络环境）下IP地址不够用的情况。还听说IPV6只是适用于教育网环境，一直以为IPV6和普通家庭宽带用户是没有关系的，直到在@clientor的指点下才发现原来普通家庭宽带用户也是可以设置成IPV6的，只需在命令符输入以下命令

C:\Documents and Settings\Administrator>netsh
netsh>int
netsh interface>ipv6
netsh interface>ipv6>install???? （经我测试，WIN7不需要这个步骤，跳过这步 ）
netsh interface ipv6>isatap
netsh interface ipv6 isatap>set router isatap.sjtu.edu.cn （此处利用上海交大的IPV6通道，用其他高校通道亦可）

打开命令行窗口，把上面这些命令输进去，然后打开www.ipv6.org 看看你的网络。(当你看到 You are using IPv6 from 2001:…… 时，你就已经成功地将你的网络环境改为了IPV6，从而进入了IPV6的世界）

如果上面的命令不行，用下面的命令? （我本人用了上面的命令就已经成功了，下面这段照发）

C:\Documents and Settings\Administrator>netsh
netsh>int
netsh interface>ipv6
netsh interface>ipv6>install
netsh interface ipv6>6to4
netsh interface ipv6 6to4>set relay 202.112.26.246 enable

接下来我问了 @clientor 两个问题：使用IPV6后对上网有影响吗（对比常规的IPV4环境）；IPV6有什么优点？

以下是他的回答：

1.对你的ipv4环境有一点影响：假如一个网站支持ipv4 和 ipv6 访问，那么将优先考虑使用ipv6 地址去访问该站点，比如你访问 www.ipv6.org ，看到的是你的ipv6 地址而不是 ipv4 地址。在命令行里面 ping www.ipv6.org ，得到的是这个网站的ipv6 地址而不是v4 地址。就这个影响。

2.好处之一是可以享用ipv6网络的资源，比如你在 http://video6.sjtu.edu.cn 这里看电视转播，就必须用ipv6才行；
还有一些高校的PT 站点，比如六维空间? http://bt.neu6.edu.cn ，晨光 http://ipv6.cgbt.cn ，乐乎BT http://bt.shu6.edu.cn 等等都要求ipv6才能访问。
更多的关于ipv6 的内容，你可以去这个论坛看看? http://www.ipv6bbs.com/index.php

3.好处之二是可以用ipv6来翻墙。因为目前ipv6 环境是没有审查的，所以所有支持ipv6 访问的站点都不会被封锁（将来就不知道了），因为Google支持ipv6，所以你ping 一下 ipv6.google.com ，得到Google 的ipv6 地址，然后在hosts 文件里面，将所有Google相关的服务，都用这个地址来解析，就可以通过ipv6 来访问Google 的服务了，包括YouTube，picasa 等等。因为可以通过ipv6 访问GAE ，所以不用怕GAE被封锁，GappProxy配合ipv6 ，无视GFW 的存在

这里有一份 hosts 文件，你自己看看吧

http://docs.google.com/View?id=dfkdmxnt_61d9ck9ffq

在参看了 @clientor 提到上面这个GOOGLE DOC文档后，我在HOSTS（文件位置? C:\Windows\System32\drivers\etc）文件里添加了以下GOOGLE各项服务IPV6地址的内容（分割线以下）。添加完成后的瞬间我发现自己已经可以直接访问YOUTUBE、GOOGLE SITES、BLOGGER、PICASA，使用GOOGLE再搜索任何关键词也不会有撞墙的情况发生，GOOGLE快照也不会再打不开。尽管搜索出的很多不和谐网站不使用翻墙工具是无法访问的，然而通过不再GOOGLE快照和GOOGLE图片依然可以看到好多好多敏感内容，这对于一向和谐的牧师来说真是大吃一惊，原来有真么多真相？！如果你再适时地配合一款VPN，那就基本上到达和牧师一样的翻墙次高境界了（最高境界当然是肉身翻墙）。

至此，实战体验结束，牧师大获成功，感谢国家感谢党感谢功夫网最后隆重感谢 @clientor? ！

家里的电信还没有通IPv6，突然想去六维上面下几部电影（其实想看一下最近的新片出了没有）。

有一些现成的软件就可以使用，但是我总觉的这样不够好，至少要略略知道一点点原理的好。

现成的软件包括

六飞

Veno

http://www.veno2.com/

这两个东西，其实不仅支持在IPv4的环境下访问IPv6的网站而且也支持在IPv6的环境下访问IPv4的网站。

后一半的功能，具体我不知道他们是如何实现的，应该是类似代理之类的。后面这个功能都是要收费的，是在恶心得很。

还是言归正传，现在通过IPv4到IPv6的技术基本上有三种 Teredo isatap 6to4

这三种协议各有有缺，基本的原理都是通过中间一层服务吧IPv6的数据包拆分成IPv4的数据包，然后在网络上跑，最后再并起来。

他们都是作为在IPv4 和IPv6环境过渡中的产物。让几个IPv6的孤岛在IPv4这片大海洋上也能将进行通讯

Teredo

Teredo 叫做 面向 IPv6的IPv4 NAT 网络地址协议穿越，他是这三种协议中唯一支持内网的协议了

它的缺点是，在已知的为数不多几个服务器都在外国，速度很不给力

不过这个时内网条件下的唯一方案，当然有些牛人有比较强大的路由器通过改写iptables，可以强制把isatap的数据都转发进内网，今天暂时不想讨论这个。

下面写具体怎么做

1、用管理员权限运行命令提示符

2、设置服务器地址

  1. netsh?interface?ipv6?set?teredo?client?teredo.ipv6.microsoft.com??

teredo.ipv6.microsoft.com是服务器地址，可以换成其他的服务器

3、设置客户端类型

  1. netsh?interface?ipv6?set?teredo?enterpriseclient??

4、修改主机hosts?文件（c:\WINDOWS\system32\drivers\etc\hosts）

首先添加这2行

  1. 127.0.0.1?localhost??

  2. ::1?localhost??

然后选择行添加一些host，

要访问六维就添加

2001:da8:9000::232 bt.neu6.edu.cn

更多的可以参考

https://docs.google.com/View?id=dfkdmxnt_61d9ck9ffq&pli=1?

这样就惊醒浏览了，下载没有问题，唯一的问题就是太慢了。

下面是一些服务器的地址和所在位置

teredo.remlab.net /?teredo-debian.remlab.net (法国) (Miredo 默认设置)
teredo.autotrans.consulintel.com (西班牙)
teredo.ipv6.microsoft.com (美国 雷蒙德) (Windows XP/2003/Vista/7/2008 系统默认设置)
teredo.ngix.ne.kr (韩国)
teredo.managemydedi.com (美国 芝加哥)

isatap?

ISATAP ( Intra-Site Automatic Tunnel Addressing Protocol，站内自动隧道寻址协议)。这个是现有的最好的方案了，你需要的是一个公网地址。国内好多大学都提供了isatap服务器，速度可以达到本身的快带极限，家里4M网络下载六维也算毫无压力了。

它的原理是在特殊的IPv6地址中内嵌的IPv4地址,这个地址称为ISATAP地址。地址的格式为

::0:5EFE:w.x.y.z

w.x.y.z部分是任意的单播IPv4地址，既可以是私有地址，也可以是公共地址。

内嵌的IPv4地址的作用是:在发往ISATAP地址的IPv6通信流通过隧道跨越了IPv4网络后，可用它来确定IPv4报头中的源IPv4地址或目标IPv4地址。

它的主要缺陷其实是安全问题，这里就不更多讨论了。

使用方法也很简单，也是用管理员权限运行命令提示符执行以下两条命令

  1. netsh?interface?ipv6?isatap?set?router?isatap.sjtu.edu.cn??

  2. netsh?interface?ipv6?isatap?set?state?enabled??

netsh interface ipv6 isatap set router isatap.sjtu.edu.cn
netsh interface ipv6 isatap set state enabled

其中isatap.sjtu.edu.cn是上海交大的地址。

很多国内的大学都有，速度很好。网上随意搜一搜，就有。

就没有必要用一些外国的服务器了。

6TO4

在说这个之前，要回过头说以下以上两个配置后命令提示符不要关闭，关闭了隧道就会断开，有需要的话，可以把配置写死，这样就是重启也可以访问，介于回学校之后就没有这需要了，我就没有进行这样的配置。

6to4这个协议从表面上看和isatap很相似。（数据包格式当然有很大不用）

IPv4兼容iisatap,能够使隧道自动生成。只需要告诉设备隧道的起点，则隧道的终点由设备自动生成。IPv4兼容isatap使用特殊的IPv4兼容IPv6地址：其前缀为0.0.0.0.0.0，最后32位为IPv4地址。而6to4隧道使用特定的6to4地址。

具体的设置就比较麻烦了。

具体可参考

http://blog.csdn.net/ast_224/article/details/4036556

Ecdysis?NAT64 with Unbound DNS64: set your DNS to?2001:67c:27e4::46

Ecdsys NAT64 implementation is running in a virtual container on proxmox server.
NAT64 routed prefix:?2001:67c:27e4:641::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:641::d42c:6c64

PaloAlto Networks Firewall?NAT64 with BIND9.9 DNS64: set your DNS to?2001:67c:27e4::64

NAT64 implementation is running in PAN500 firewall box.
NAT64 routed prefix:?2001:67c:27e4:64::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:64::d42c:6c64

A10 Networks?NAT64 implementation: set your DNS to?2001:67c:27e4:1002::64

NAT64 implementation is running on a A10 AX 3200-12 hw.
NAT64 routed prefix:?2001:67c:27e4:642::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:642::d42c:6c64

To test?different NAT64/DNS64 setups you need to disable IPv4 on your device and set an IPv6 resolving DNS server,?different one for each setup. Please send us your observations, specially about which applications breaks in IPv6-only/NAT64 environment. We would like to build a list of them.

A10 Networks?NAT64 implementation: set your DNS to?2001:67c:27e4:15::6411
NAT64 implementation is running on a A10 vThunder virtual appliance.
NAT64 routed prefix:?2001:67c:27e4:642::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:642::5bef:6015

PaloAlto Networks Firewall NAT64 with BIND9.9 DNS64: set your DNS to?2001:67c:27e4::64
NAT64 implementation is running in PAN500 firewall box.
NAT64 routed prefix:?2001:67c:27e4:64::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:64::5bef:6015

Jool?NAT64 with BIND9?DNS64: set your DNS to?2001:67c:27e4:15::64
 Jool?NAT64 implementation is running in a virtual container on proxmox server.
NAT64 routed prefix:?2001:67c:27e4:1064::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:1064::5bef:6015

Cisco ASR1000?NAT64 with BIND9 DNS64: set your DNS to?2001:67c:27e4::60
NAT64 implementation is running in Cisco ASR1001.
NAT64 routed prefix:?2001:67c:27e4:11::/64
Quick ping6 test if up&running: ping6?2001:67c:27e4:11::5bef:6015

http://ipv6now.com.au/downloads.php 上下个 客户端，然后在http://tb2.ipv6.ascc.net/ 上注册自己的id和password，好了在客户端填上自己的id password 基本就行了，能翻墙，google youtube 没问题 gmail 稍有点问题，但是在linux 下速度杠杠的。自己研究一下，你肯定行。

http://www.polarxiong.com/archives/%E6%90%AD%E5%BB%BAipv6-VPN-%E8%AE%A9ipv4%E4%B8%8

Aipv6-%E4%B8%8B%E8%BD%BD%E9%80%9F%E5%BA%A6%E6%8F%90%E5%8D%87%E5%88%B0100M.html


Untitled Document

Web and IT Technologies

since 2009-4-1

翻墙/隐私

最新翻墙工具

Resilio Sync

Anti DPI Deep Packet Inspection

bypass deep packet inspection

Email Tunneling

TCP into HTTP tunnelling

TCP into HTTPS tunnelling

Socks 2 HTTP

SOCKS2HTTP

Socks to HTTP

Socks via HTTP

TCP into HTTP

TCP to HTTP

TCP 2 HTTP

TCP2HTTP

convert TCP into HTTP

HTTPort等等

convert smtp into HTTP

smtp to HTTP

smtp2HTTP

smtp 2 HTTP

https://www.cloudmailin.com/

http://www.email2http.net/

https://github.com/jsvaughan/emailtohttppost

https://github.com/thingless/mailglove

https://mailnuggets.com/

bypassing proxy restrictions on bulk mailing

bypassing proxy tools' restrictions on smtp

bypassing proxy tools' restrictions bulk mailing

bypassing proxy tools' restrictions port 25

bypassing proxy tools' restrictions on email sending

proxy provider restrictions on email sending

circumvention software restrictions on email sending

circumvention tools restrictions on email sending

anti-censorship tool restrictions on on smtp

代理搜索器

Proxy Searcher

如何冲破代理软件对邮件群发的限制

does psiphon allow mass bulk mailing

using smtp with psiphon

smtp blocked in psiphon

does ultrasurf allow smtp port 25

smtp blocked by ultrasurf

does Lantern allow smtp port 25

smtp blocked by Lantern

smtp blocked by vpn

Email SMTP port blocked by VPN provider

https://www.raymond.cc/blog/how-to-bypass-most-firewall-and-proxy-restrictions/

############

Use socks proxy servers

You can send e-mail using the socks proxy access to a computer on the Internet. This feature enables you to relay e-mail through other servers. When the message is sent using a third-party socks proxy, your IP address does not appear as the source of the message.

The best solution is to connect to your ISP's socks proxy directly if it is provided by the ISP. Some ISPs offer access to their socks proxy server. See if your ISP provides socks proxy access in the support section on their web site. If they do, you can use their socks proxy server address to configure the program to send messages. Their server's (non-dynamic) IP address will be the source of your outgoing messages instead of your dynamic IP address assigned to your computer at the moment your Internet connection is established.

not using SMTP on port 25

Make sure you are not using SMTP on port 25 for outgoing emails as we block it to prevent spamming. You need to switch to an encrypted port, which is usually 465 or 587. Keep in mind, just switching the port from 25 to 465 will not work, you need to adjust the encryption parameters as well. Your mail provider should have these available on their website.

generally you should be fine if you are using 465 or 587, encrypted either by TLS or SSL and authentication is on

Blocking ports 25 and 465

We are blocking the SMTP ports 25 and 465 to avoid spam from our servers. Please check with your email provider if they support other SMTP ports. Most email providers support port 587 which allows TLS encryption for sending emails. Please try to setup your e-mail server to accept outgoing mail from port 587. Also setup your mail client for outgoing mail to use port 587.

TunnelBear

Can I use SMTP to send email while connected to TunnelBear? Yes! TunnelBear does not block SMTP on our network, but we do limit the ports you can use to send email. Port 25 is widely known to be insecure and blocked on most residential ISPs as it’s often used by spammers. Since TunnelBear does not log what you do while you’re connected to our service, we remove the ability for you to send email using port 25. To use SMTP while connected to TunnelBear, you should configure your email client to use port 587 or port 465 for SMTPS.

https://www.tunnelbear.com/download

vpnbook

https://www.vpnbook.com/

vps

get vps / cheap dedicated server and set up smtp relay there. use alternative port for smtp [ in worst case even 443 although traffic you'll sent will be smtp ].

############

????????????????????????

BarbaTunnel

????????????????????????

httptunnel

http://http-tunnel.sourceforge.net/

http://www.httptunnelclient.com/html/

http://www.httptunnelclient.com/

http://www.http-tunnel.com/

????????????????????????

jhttptunnel

????????????????????????

SmtpProxy

java -jar SmtpProxy.jar

sockscap 绿色免安装版

socks2http 绿色免安装版

proxy auto-configration script for socks2http

proxy auto-config url

http://findproxyforurl.com/

socks2http使用代理服务器自动配置脚本

使用代理服务器自动配置教本。这一般是收费代理提供的一个措施，可向相应的代理治理员咨询自动配置脚本的URL。

socks2http配置多个代理

socks2http如何使用PAC

sshtunneling

http://pages.uoregon.edu/miyake/sshtunneling/

XXXXXXXXXXXX????????????????????????

for mobile

TCP Over HTTP Tunnel

????????????????????????

tiny-tunnel

????????????????????????

Xshell Tutorial

Using tunneling service for an email client of POP3 and SMTP protocol

https://www.netsarang.com/tutorial/xshell/2778/Using_tunneling_service_for_an_email_client_of_POP3_and_SMTP_protocol


ComputerOS

ComputerOS.doc
ComputerOS2.doc

os_intro.htm

Kernel.htm

shellbatch.htm

bash_profile.htm

devicedrivers.htm

utility.htm

Mainboard.htm

000WindowsAPI/

APIView/
Kuliniewicz Windows API Guide p1705.pdf
WINDOWS API程序设计参考大全 p750.pdf
Win32 API Reference for HLA p572.pdf
Win32 API大全.chm
Win32.chm
api32.chm
介绍API函数的中文帮助文件.chm

Reinstall/

OSHowto.docx
OSHowto2.docx
Reinstall.docx
Reinstall2.docx
ReinstallDamaged.docx
WORD.pdf
linuxinstall.txt
test.doc
激活.txt

ComputerOS linux

  • linux.htm
  • linux-command.htm
  • linux4win.htm
  • linux4win1.htm
  • linux_win.htm
  • system1.htm
  • system_en1.htm
  • dns.htm
  • sendmail.htm
  • sendmail1.htm
  • wine.htm

000LinuxKernel/

000Linux kernel-api.pdf
000Linux kernel-api54.pdf
Jiong Linux 内核011 详细注释 p487.pdf
Kroah-Hartman Linux Kernel in a Nutshell p197.pdf
Love Linux kernel development p310.pdf
Mauerer Professional Linux Kernel Architecture p1370.pdf
Payberah Linux Kernel Architecture p52.pdf
陈莉君 深入分析Linux内核源代码 p554.pdf


bash_profile

# .bash_profile

# Get the aliases and functions

if [ -f ~/.bashrc ];

then . ~/.bashrc

fi

# User specific environment and startup programs

JAVA_HOME=/usr/local/j2sdk1.4.0

export JAVA_HOME

JRE_HOME=$JAVA_HOME/jre

export JRE_HOME

J2EE_HOME=/usr/local/j2sdkee1.3

export J2EE_HOME

JDBC_HOME=/usr/local/mm.mysql.jdbc-1.2c

export JDBC_HOME

ANT_HOME=/usr/local/ant1.4.1

export ANT_HOME

SERVLETAPI_HONME=/usr/local/jakarta-servletapi

export SERVLETAPI_HOME

#JBOSS_DIST=/usr/local/jboss2.2.2

#JBOSS_DIST=/usr/local/jboss2.4.4-tomcat4.0.1/jboss

#export JBOSS_DIST

#JBOSS_HOME=/usr/local/jboss2.2.2

JBOSS_HOME=/usr/local/jboss2.4.4-tomcat4.0.1/jboss

export JBOSS_HOME

#TOMCAT_HOME=/usr/local/tomcat4.0.2

TOMCAT_HOME=/usr/local/jboss2.4.4-tomcat4.0.1/catalina

export TOMCAT_HOME

#CATALINA_BASE=/usr/local/tomcat4.0.2

CATALINA_BASE=/usr/local/jboss2.4.4-tomcat4.0.1/catalina

export CATALINA_BASE

#CATALINA_HOME=/usr/local/tomcat4.0.2

CATALINA_HOME=/usr/local/jboss2.4.4-tomcat4.0.1/catalina

export CATALINA_HOME

COCOON_HOME=/usr/local/cocoon1.8.2

export COCOON_HOME

PATH=/bin:/sbin:/usr/bin:/usr/sbin:/usr/local/bin:/usr/local/sbin:$PATH:$HOME/bin

PATH=$PATH:$JAVA_HOME/bin:$JRE_HOME/bin:$J2EE_HOME/bin:$ANT_HOME/bin:.

PATH=$PATH:/usr/X11R6/bin

export PATH

CLASSPATH=$JAVA_HOME/lib:$JAVA_HOME/lib/tools.jar:$J2EE_HOME/lib/j2ee.jar:$JDBC_HOME:.

CLASSPATH=$CLASSPATH:$JDBC_HOME/mysql_uncomp.jar:$JDBC_HOME/mysql_comp.jar:.

export CLASSPATH

#JBOSS_CLASSPATH=/usr/local/jboss2.2.2/lib

JBOSS_CLASSPATH=/usr/local/jboss2.4.4-tomcat4.0.1/jboss/lib

export JBOSS_CLASSPATH

BASH_ENV=$HOME/.bashrc

export BASH_ENV

USERNAME="root"

export USERNAME

# .bash_profile

# Get the aliases and functions

if [ -f ~/.bashrc ];

then . ~/.bashrc

fi

# User specific environment and startup programs

JAVA_HOME=/usr/local/j2sdk1.4.0

export JAVA_HOME

JRE_HOME=$JAVA_HOME/jre

export JRE_HOME

J2EE_HOME=/usr/local/j2sdkee1.3

export J2EE_HOME

JDBC_HOME=/usr/local/mm.mysql.jdbc-1.2c

export JDBC_HOME

ANT_HOME=/usr/local/ant1.4.1

export ANT_HOME

SERVLETAPI_HONME=/usr/local/jakarta-servletapi

export SERVLETAPI_HOME

#JBOSS_DIST=/usr/local/jboss2.2.2

#JBOSS_DIST=/usr/local/jboss2.4.4-tomcat4.0.1/jboss

#export JBOSS_DIST

#JBOSS_HOME=/usr/local/jboss2.2.2

JBOSS_HOME=/usr/local/jboss2.4.4-tomcat4.0.1/jboss

export JBOSS_HOME

#TOMCAT_HOME=/usr/local/tomcat4.0.2

TOMCAT_HOME=/usr/local/jboss2.4.4-tomcat4.0.1/catalina

export TOMCAT_HOME

#CATALINA_BASE=/usr/local/tomcat4.0.2

CATALINA_BASE=/usr/local/jboss2.4.4-tomcat4.0.1/catalina

export CATALINA_BASE

#CATALINA_HOME=/usr/local/tomcat4.0.2

CATALINA_HOME=/usr/local/jboss2.4.4-tomcat4.0.1/catalina

export CATALINA_HOME

COCOON_HOME=/usr/local/cocoon1.8.2

export COCOON_HOME

PATH=/bin:/sbin:/usr/bin:/usr/sbin:/usr/local/bin:/usr/local/sbin:$PATH:$HOME/bin

PATH=$PATH:$JAVA_HOME/bin:$JRE_HOME/bin:$J2EE_HOME/bin:$ANT_HOME/bin:.

PATH=$PATH:/usr/X11R6/bin

export PATH

CLASSPATH=$JAVA_HOME/lib:$JAVA_HOME/lib/tools.jar:$J2EE_HOME/lib/j2ee.jar:$JDBC_HOME:.

CLASSPATH=$CLASSPATH:$JDBC_HOME/mysql_uncomp.jar:$JDBC_HOME/mysql_comp.jar:.

export CLASSPATH

#JBOSS_CLASSPATH=/usr/local/jboss2.2.2/lib

JBOSS_CLASSPATH=/usr/local/jboss2.4.4-tomcat4.0.1/jboss/lib

export JBOSS_CLASSPATH

BASH_ENV=$HOME/.bashrc

export BASH_ENV

USERNAME="root"

export USERNAME


device drivers

AlteraZZZ Chapter 7 Developing Device Drivers for the Hardware Abstraction Layer p34.pdf
BaniaZZZ Exploiting Windows Device Drivers p50.pdf
CorbetZZZ LINUX DEVICE DRIVERS p633.pdf
FlieglZZZ Programming_Guide_For_Linux_Usb_Device_Drivers p109.pdf
HydeZZZ Writing Linux Device Drivers in Assembly Language p116.pdf
KenwZZZ COMP755 DeviceDrivers p5.pdf
MicronZZZ Software Device Drivers for Large Page Micron? NAND Flash Memory p21.pdf
OARZZZ BSP and Device Driver Development Guide p106.pdf
OpersysZZZ Linux Device Drivers p688.pdf
RubiniZZZ Linux Device Drivers p573.pdf
TIZZZ DSPBIOS Driver Developers Guide p123.pdf
ZZZLinux Device Drivers & Project3 preview.ppt


Kernel

Bovet, Daniel P.: Understanding the Linux Kernel 3rd Edition, O'Reilly, November 2005

3.4. Creating Processes

the Free Software Foundation: The Linux Kernel API, 2008.

AivazianZZZ Linux Kernel Internals p56.pdf
BovertZZZ Understanding the Linux Kernel 2nd Edition p829.pdf
BovertZZZ Understanding The Linux Kernel p542.pdf
Bovet Understanding the Linux Kernel 3rd Edition p942.chm
BovetZZZ 博韦 深入理解 Linux 内核 p731.pdf
GNUZZZ Linux Kernel API p391.pdf
JionhZZZ Commentted Linux Kernel p652.pdf
Kroah-HartmanZZZ_Linux_Kernel_in_a_Nutshell p197.pdf

Kroah-Hartman, Greg: LINUX KERNEL IN A NUTSHELL, O’Reilly, 2006.

Love, Robert: Linux Kernel Development, 2nd edition, Pearson, 2005

LoveZZZ LINUX内核设计与实现 p310.pdf
LuohandsomeZZZ 读核感悟 p70.pdf
Mauerer Professional_Linux_kernel_architecture p1370.pdf

Mauerer, Wolfgang: Professional Linux kernel architecture, Wiley Publishing, Inc., 2008 .....p1370 ...... 199

Pomerantz, Ori: Linux Kernel Module Programming Guide, 1999

PomerantzZZZ Linux Kernel Module Programming Guide p128.pdf
ProbertXXX.Kernel Architecture p63.pdf
ProbertZZZ Evolution of the Windows Kernel Architecture p30.ppt
ProbertZZZ Windows Kernel Internals p20.pdf
RuslingZZZ The Linux Kernel p212.pdf

Rusling, David A: The Linux Kernel, 1999 .

SalzmanZZZ The Linux Kernel Module Programming Guide p73.pdf

?oltys, Jaroslav: Linux Kernel 2.6 Documentation (Master thesis), 2006
SoltysZZZ Linux Kernel 2.6 Documentation p168.pdf
WolfZZZ Windows Kernel TrueType Font Engine Vulnerability p273.pdf
毛德操Windows 内核情景分析上 p743.pdf

毛德操，Windows 内核情景分析- 采用开源代码ReactOS， 电子工业出版社，2009 .

谭文: 寒江独钓-Windows内核安全编程(完整版)， 电子工业出版社，2009

谭文XXX 寒江独钓-Windows内核安全编程(完整版) p515.pdf
谭文ZZZ 天书夜读-从汇编语言到Windows内核编程 p281.pdf

谭文: 天书夜读-从汇编语言到Windows内核编程， 电子工业出版社，2008


DNS

DNS服务器
如何在Linux上建立DNS服务器

一、 假定

本文假定你已对域名服务器 DNS 有基本的了解，如果不是，请参看相关的文裆。
许多DNS的文章都是从DNS原理开始介绍，本人则从使用的角度出发，为Linux的管理员提供一些简单实用的应用实例。

下面假定我们需要建立一台企业网的DNS主服务器，应用条件如下：

（1） 一个C类网段地址 （本例中假定是192.22.33）

（2）企业域名为 my.com，并已注册 （主域名服务器地址 192.22.33.20，主机名为 linux.my.com）

（3）企业网通过路由器与Internet连接

假如你的应用环境与上述条件不同，也请往下看，本文会在上述例子的基础上针对以下情况作修正：

（1） 多个网段

（2） 封闭的内部网

（3） 只能访问局部公共网的情况（如169网、上海热线等）

二、named、/etc/named.boot 和 ndc

DNS 服务器的主体是域名服务器进程 named ，named 启动后向DNS客户机提供域名解析服务，把域名转换成IP地址。
named 启动时需要读取一个初始化文件，缺省情况下是 /etc/named.boot，所以/etc/named.boot 是 named 的基本配置文件。

虽然启动 named 可直接执行 named，在Linux上我们可以使用一个控制 named 的工具 ndc。ndc 可以用于启动、中止、重启动、刷新DNS数据、输出DNS数据等多种调试功能，我在这里推荐大家用这个工具来帮助 DNS 服务器的调试。

有关 ndc 的详细用法，请参看 Linux 有关文档。

三、建立 named 配置文件 /etc/named.boot

/etc/named.boot 是基本的配置文件，但不包含任何 DNS 数据，针对我们前面的假定，我们先建立以下 /etc/named.boot，其内容如下：
;
; boot file for name server
;
directory /var/named

primary my.com db.my
primary 0.0.127.IN-ADDR.ARPA db.127.0.0
primary 33.22.192.IN-ADDR.ARPA db.192.22.33
cache . db.cache
其中以“；”开头的行是注释行，其他各行含义是
（1）diretory /var/named

指定 named 从 /var/named 目录下读取 DNS 数据文件。这个目录用户可自行指定并创建，指定后所有的DNS 数据文件都存放在此目录下。

（2）primary my.com db.my

指定 named 作为 my.com 域的主域名服务器，db.my 文件中包含所有 *.my.com 形式的域名转换数据。

（3）primary 0.0.127.IN-ADDR.ARPA db.127.0.0

指定 named 作为127.0.0网段地址转换主服务器，db.127.0.0 文件中包含了 127.0.0.* 形式的地址到域名的转换数据。（127.0.0网段地址是局域网接口的内部 loopback 地址）

（4）primary 33.22.192.IN-ADDR.ARPA db.192.22.33

指定 named 作为 192.22.33 网段地址转换主服务器，db.192.22.33 文件中包含了所有 192.22.33.* 形式的地址到域名的转换数据。

（5） cache . db.cache

指定 named 从 db.cache 文件中获得 Internet 的顶层“根”服务器地址

要注意（3）（4）两行中的网段地址是倒写的，另外，各个文件名也是可以自行决定的。

四、建立各个 DNS 数据文件

下一步，要按 /etc/named.boot 中的定义，建立各个 DNS 数据文件。
（1）建立正向域名转换数据文件 db.my

根据 /etc/named.boot 的定义，我们在 /var/named 目录下建立 db.my，其中应该包括所有在 my.com 域内的主机节点。但在机器数量较多时，为了调试方便，建议一开始只把几台节点的数据放入文件，待 named 正常工作后再把其他节点的数据补充进去。下面是 db.my的例子：

@ IN SOA linux.my.com. root.linux.my.com. (
199511301 ; serial, todays date + todays serial #
28800 ; refresh, seconds
7200 ; retry, seconds
3600000 ; expire, seconds
86400 ) ; minimum, seconds
NS linux.my.com.
MX 10 support.my.com.

localhost A 127.0.0.1
linux A 192.22.33.20
support2 A 192.22.33.102
hp712 A 192.22.33.160
support A 192.22.33.100
mail MX 10 support.my.com.
MX 20 support2.my.com.
www CNAME hp712.my.com.
ftp CNAME hp712.my.com.
ns CNAME linux.my.com.
其中第一行是 SOA 记录，定义了域名数据的基本信息，依次是 DNS 服务器名、DNS 管理员邮件地址，括号内的第一个数字是文件版本号，每次本文件内容修改后，必须更改此号。其余数字与DNS服务器直接的数据交换有关，在这里我们不需要改动。
括号后面有一条 NS 记录和一条 MX 记录，定义了域名服务器本身的域名和 username@my.com 形式邮件地址所对应的邮件服务器名字。

在此以下是各种域名/地址转换数据，其中 A 记录是 DNS 域名到 IP 地址的记录，是必须有的，以 hp712.my.com 为例，在 A 记录中域 my.com 被省略，只写成 hp712，named 在处理时会根据 named.boot 中的定义自动加上 my.com，而其对应 IP 地址为 192.22.33.160。

另一种记录是 MX 记录。MX 是邮件地址转换记录，本例中定义了将 username@mail.my.com 的邮件地址转换成 username@support.my.com 或 username@support2.my.com，即实际上真正的邮件服务器是 support.my.com 和 support2.my.com，其中 support.my.com 的优先数为 10，support2.my.com 的优先数为 20，所以通常邮件首先被发往优先数小的主机 support.my.com。

还有一些是为方便提供的 CNAME 记录。CNAME 定义了一些主机的别名，比如我们将 hp712.my.com 作为公司的 www 和 ftp 服务器，所以我们提供了 www.my.com 和 ftp.my.com 作为 hp712.my.com 的别名，用户只需要根据习惯就可以访问公司的 www、ftp 服务器了，如果将来我们换用别的主机作 www 和 ftp 服务器，只需要修改 CNAME 记录就可，对用户没有影响。

注意：MX 和 CNAME 记录最后的带域名的主机名后必须带一个“.”

（2）建立反向 DNS 数据文件 db.127.0.0 和 db.192.22.33

反向 DNS 数据文件用来提供根据 IP 地址查询相应 DNS 主机名，每个网段分别有一个数据文件。

对于内部网段 127.0.0 通常只有一个地址，即 127.0.0.1 loopback 地址，db.127.0.0 内容如下：

@ IN SOA linux.my.com root.linux.my.com. (
1997022700 ; Serial
28800 ; Refresh
14400 ; Retry
3600000 ; Expire
86400 ) ; Minimum
IN NS linux.my.com.

1 IN PTR localhost.
而外部网段的数据文件 db.192.22.33 中包含所有主机 IP 地址到 DNS 主机名的转换数据。db.192.22.33 内容如下：
@ IN SOA linux.my.com. root.pc590.my.com. (
199609206 ; Serial
28800 ; Refresh
7200 ; Retry
604800 ; Expire
86400) ; Minimum TTL
NS linux.my.com.
;
; All hosts
;
20 PTR linux.my.com.
102 PTR support2.my.com.
100 PTR support.my.com.
160 PTR hp712.my.com.
反向 DNS 数据文件中的主要部分是 PTR 记录，PTR 记录中的 IP 地址都只有主机号，named 会根据 named.boot 的定义自动加上前面的网络号，注意后面的主机名要附加一个“.”
（3）获得 db.cache 文件

在 Linux 系统上通常在 /var/named 下已经提供了一个 named.ca，该文件文件中包含了 Internet 的顶层域名服务器，但这个文件通常会发生变化，所以建议最好从 Internic 下载最新的版本。该文件可通过匿名 ftp 从 ftp.rs.internic.net 下载，在 domain 目录下，文件名为 named.root。注意该文件下载后要拷贝到 named 的工作目录并重命名成 named.boot 中指定的文件名，本文中为 db.cache。

五、启动和测试 named

首先，根据先前推荐的方法，用 ndc 启动 named:
ndc start

然后，为了使用和测试 named，要把 Linux 设置在使用 DNS 状态。方法是在 /etc 目录下，创建 resolv.conf 文件。以我们的例子，/etc/resolv.conf 内容为：

search my.com
nameserver 192.22.33.20
然后，我们就可以测试 named 了。
Linux 和其他 Unix 系统均提供了 nslookup 工具，在命令行状态下输入：

nslookup

就进入交换式 nslookup 环境，如果 named 正常启动，nslookup 会显示当前 DNS 服务器的地址和域名，否则表示 named 没能正常启动。下面简单介绍一些基本的 DNS 诊断：

（1）检查正向 DNS 解析

在 nslookup 提示符下输入带域名的主机名，如 hp712.my.com，nslookup 应能显示该主机名对应的 IP 地址，如果只输入 hp712，nslookup 会根据 /etc/resolv.conf 的定义，自动添加 my.com 域名并回答对应的 IP 地址。

（2）检查反向 DNS 解析

在 nslookup 提示符下输入某个 IP 地址，如 192.22.33.20，nslookup 应能回答该 IP 地址所对应的主机名。

（3）检查 MX 邮件地址记录

在 nslookup 提示符下输入：

set q=mx

然后输入某个域名，以本文的例子，输入 my.com 或 mail.my.com，nslookup 应能够回答对应的邮件服务器地址，即 support.my.com 和 support2.my.com。

（4）检查 CNAME 别名记录

在 nslookup 提示符下输入：

set q=cname

然后输入某个别名，如 www.my.com，nslookup 应能回答对应的真实主机名，即 hp712.my.com。

如要退出 nslookup，可输入 exit。

六、修改 DNS 数据

如果要在网络中增加主机，例如要增加一台叫做 pc01.my.com 的 PC 机，管理员要在 db.my 中增加该主机对应的 A 记录，并且要在 db.192.22.33 中增加对应的 PTR 记录，然后用 ndc 更新 named 的数据：
ndc reload

要注意必须同时更改 A 记录和 PTR 记录，许多管理员往往只增加 A 记录而忽略了逆向查询用的 PTR 记录，结果会使许多应用程序不能正常运行。

特别注意，一旦修改了 DNS 数据文件的内容，请务必改动数据文件的版本号（ Serial ）

七、使网络中的其他系统(客户机)使用 DNS 服务器

一旦 DNS 服务器开始工作，就可以配置所有企业网内的主机使用 DNS 服务。
Unix 主机配置的方法，已经在前面说明过，即创建 /etc/resolv.conf 文件，内容见前面第五节。

Windows 95 的配置则是在网卡的 TCP/IP 配置中，选择使用 DNS （enable），然后在配置窗口中分别填入各项参数。以本文的例子，如果运行 Windows95 的主机被命名为 pc01.my.com，则在主机名（Host）一栏中填 pc01，在域名（Domain）一栏中填 my.com，然后把域名服务器 （DNS Server）加入搜索列表中。

Windows NT 节点的配置大致相同。

八、几种不同环境下的修正

（1）如果 IP 网段多于一个
假定现在在 my.com 域中增加一个 IP 网段 192.22.37，则 /etc/named.boot 的内容中就增加一个网段的定义，具体如下：

;
; boot file for name server
;
directory /var/named

primary my.com db.my
primary 0.0.127.IN-ADDR.ARPA db.127.0.0
primary 33.22.192.IN-ADDR.ARPA db.192.22.33
primary 37.22.192.IN-ADDR.ARPA db.192.22.37
cache . db.cache
而反向 DNS 数据文件则增加一个定义 192.22.37 网段的文件 db.192.22.37，其中包括了所有处于 192.22.37 网段中的节点，其格式与 db.192.22.33 类似。
（2）如果企业网是封闭的

如果企业网络不与外界 Internet 直接互连，DNS 服务器就不必关心本企业域以外的域名，所以配置 named 的时候可以不理会 db.cache，我们可以将 /etc/named.boot 中的 cache 行去除。

（3）如果你联入的公共网不能访问 Internet

如果你的内部网接入的公共网只能访问有限的范围，如免费的169网、上海热线等，那么你的 DNS 服务器就不能通过 Internet 的顶层服务器（root server）进行地址解析，所以你必须用你直接能访问到的 DNS 服务器来替代。具体办法是用 forwarders 选项来指定上级 DNS 服务器，以本文为例，named.boot 的内容为：

;
; boot file for name server
;
directory /var/named

primary my.com db.my
primary 0.0.127.IN-ADDR.ARPA db.127.0.0
primary 33.22.192.IN-ADDR.ARPA db.192.22.33
primary 37.22.192.IN-ADDR.ARPA db.192.22.37
forwarders ...
options forward-only
其中、等是你能直接访问到的 DNS 服务器的地址，通常就是你的 ISP （169、上海热线等）的 DNS 服务器的地址，至少要有一个。
通过 forwarders 和 options forward-only 参数的指定，你的企业 DNS 服务器就工作在 forward-only 模式下，所有本地不能解决的名字都被传送到 ISP 的 DNS 服务器上去解析。

九、建立后备 DNS 服务器 （Secondary DNS Server）

通常有一台 DNS 主服务器，网络即可正常工作，但根据 Internic 对域名的管理规范，一个独立的域名必须至少有两台 DNS 服务器，即一台 DNS 主服务器 （ Primary Server ）和一台后备 DNS 服务器（ Secondary Server ），这主要是为 DNS 服务的可靠性考虑，能使 Internet 的性能更为可靠。
现在仍以前面的例子，现在要加入一台运行 Linux 的机器 nspc.my.com，IP 地址为 192.22.33.60。

（1）主服务器上的修改

首先确认 DNS 主服务器工作正常，然后，在主服务器上的正向 DNS 数据文件 db.my 中，加入 nspc.my.com 的有关记录，并增加一个NS记录，使主服务器上的 db.my 成为下列内容：

@ IN SOA linux.my.com. root.linux.my.com. (
199511301 ; serial, todays date + todays serial #
28800 ; refresh, seconds
7200 ; retry, seconds
3600000 ; expire, seconds
86400 ) ; minimum, seconds
NS linux.my.com.
NS nspc.my.com. ; 必须增加的记录
MX 10 support.my.com.

localhost A 127.0.0.1
linux A 192.22.33.20
support2 A 192.22.33.102
hp712 A 192.22.33.160
support A 192.22.33.100
nspc A 192.22.33.60 ; 增加的记录
mail MX 10 support.my.com.
MX 20 support2.my.com.
www CNAME hp712.my.com.
ftp CNAME hp712.my.com.
ns2 CNAME nspc.my.com. ; 增加的记录
ns CNAME linux.my.com.
然后对主服务器上的各个反向 DNS 数据文件做类似的修改，增加有关后备服务器的 NS 记录，然后重新起动 named。
可见，其实在主 DNS 服务器上的改动主要是增加了一条 NS 记录，其余的改动和增加一台普通节点一样，如果是用现有的节点做后备 DNS 服务器，则增加 NS 记录是唯一必须的步骤。

（2）后备 DNS 服务器（secondary server）的配置

需要在后备 DNS 服务器上创建的配置文件只有 named.boot 和 db.cache，格式与主服务器相似，named.boot 内容为：

;
; boot file for secondary name server
;
directory /var/named

secondary my.com 192.22.33.20 db.my
secondary 0.0.127.IN-ADDR.ARPA 192.22.33.20 db.127.0.0
secondary 33.22.192.IN-ADDR.ARPA 192.22.33.20 db.192.22.33
cache . db.cache
其中的三行 secondary 定义，使得 named 从 192.22.33.20，即主服务器上获得各种 DNS 数据，并存在本地的各个数据文件中。本地的数据文件由 named 从主 DNS 服务器的 named 下载后生成，通常与主服务器上的数据文件完全一样，万一后备服务器与主服务器失去连接而不能下载 DNS 数据，后备服务器可利用本地的数据文件工作。
而后备 DNS 服务器的 db.cache 通常由系统管理员从主服务器上拷贝过来即可。

通常，后备 DNS 服务器可以建立在企业网内，也可利用外部的 DNS 服务器充当，如让 ISP 的服务器作为企业的后备 DNS 服务器，这样可以提高 DNS 服务的可靠性。注意，同一台 DNS 服务器可以同时成为多个 DNS 域的服务器，而且可以既作某些域的主服务器，同时又是另一些域的后备服务器。

（3）DNS 客户机端的改动

对于内部网上的 Unix 主机，应该在 /etc/resolv.conf 中增加一行 nameserver 说明，使得系统能够搜索后备 DNS 服务器，以本文的例子，/etc/resolv.conf 的内容为：

search my.com
nameserver 192.22.33.20
nameserver 192.22.33.60
注意，我们可以根据需要决定 /etc/resolv.conf 中所列出的 DNS 服务器的顺序，通常选择访问速度快的服务器在前。
对于 Windows95 和 NT，则是在 DNS 服务器的列表中把后备 DNS 服务器添加进去即可，添加的顺序同样可以决定访问各 DNS 服务器的优先级。


Linux commands

System commands
LINUX

Disk mount & unmount

#mount -t vfat /dev/hdax /mnt/mswin for hard disk - x=1,3,4,5,6,...

#mount -t msdost /dev/fd0 /mnt/floppy for floppy disk

#mount -t iso8890 /dev/cdrom /mnt/cdrom for CD ROM

#umount /dev/hdax ...de-install

Making boot disk

#mkbootdisk --device /dev/fd0 2.4.2-2 （2.4.2-2 is the LINUX kernel version）

ADSL configuration

#adsl-setup

#adsl-status

#adsl-start

#adsl-stop

Check for network status

#netstat -nr

#ifconfig, #ifconfig eth0, ifconfig eth1,..., ifconfig ppp0

RPM - Redhat Package Manager - for software package query, install, deinstall ...

#rpm -ivh xxx.rpm - install

rpm -qa | grep xxx - query

rpm -e xxx 卸载 - deinstall

.tar, .tgz, .gz, .tar.gz, .bz2 - install & deinstall of software

# tar zxvf xxx.tar.gz (xxx.tar, xxx.tgz, xxx.gz, xxx.zip)

(#tar yxvf xxx.tar.bz2 - .bz2 文件)

(#bunzip2 xxx.bz2)

#./config --prefix=/installDir/

#make

#make install

#make clean , #make distclean

#make uninstall 或者 #./uninstall

#rm -rf /installDir/

Find the decompressed directory

#tzvf *.tar.gz/.tgz 或 #tyvf *.bz2 (对于.bz2文件）

Process search

ps -x
Redhat 7.1 - hard disk partitioning scheme for complete installation (2772 MB)
/swap 2x RAM
/ 500 MB
/boot 50 MB
/usr 4 GB
/home 1 GB
/usr/local 4 GB
/var 1 GB
/opt 20 MB
/tmp 1 GB

Redhat 7.1 - pre-configured software installation
Apache
Packages
  • apache
  • apacheconf
  • apache-devel
  • apache-manual
INstall dirs
  • /usr/sbin/httpd
  • /usr/bin/apacheconf
  • /etc/httpd/conf/httpd.conf, srm.cnf, access.cnf
  • /etc/httpd/logs/
  • /etc/httpd/modules/
  • /etc/init.d/htttpd
  • /usr/include/apache/
  • /usr/lib/apache/
  • /var/www/cgi-bin/
  • /var/log/httpd
  • /var/cache/httpd
Executables
#httpd start | apachectl start |
#killall httpd
MySQL
Packages
  • mysql
  • mysql-devel
  • mysql-server
  • mysqlclient9
Install dirs
  • /usr/bin/mysql, mysqladmin, mysqlshow, safe_mysqld ...
  • /usr/include/mysql/
  • /usr/lib/mysql/
  • /usr/libexec/mysql
  • /usr/share/mysql/mysql.server, my_large.cnf, my_huge.cnf, my_medium.cnf, my_small.cnf...
  • /var/lib/mysql/...
  • /etc/my.cnf
Executables
  • #safe_mysqld --user=root &
  • #safe_mysqld --user=mysql &
  • #service mysqld start &
  • #mysql.server start/stop/restart
  • #/usr/libexec/mysqld --user=root
  • #mysqladmin -u root -p shutdown ...
  • #mysqlshow ...
PostgreSQL
Packages
  • postgresql
  • postgresql-server
  • postgresql-jdbc
  • postgresql-odbc
  • postgresql-perl
  • postgresql-python
  • postgresql-tcl
  • postgresql-tk
  • postgresql-devel
INstall dirs
  • /usr/bin/postgres, postgresql-dump,postmaster
  • /usr/lib/pgsql
  • /var/lib/pgsql/...
  • /etc/rc.d/init.d/postgresql
  • /usr/share/doc/postgresql-7.0.3
  • /usr/share/doc/postgresql-python-7.0.3
  • /usr/share/doc/postgresql-tk-7.0.3
Executables
  • #initdb -D /dir/to/your/data/file
  • #postmaster -D /dir/to/your/data/file
  • #createdb dbname
  • #psql dbname (to connect to your database)
  • #dbname->>: select * from xxx...
PHP
Packages
php
php-imap
php-ldap
php-mysql
php-pgsql
php-devel
php-manual
asp2php
asp2php-gtk
INstall dirs
  • /etc/php.ini
  • /usr/bin/php, php-config, phpextdist
  • phpize
  • /usr/include/php/ext,man, regex, Zend
  • /usr/lib/php4/
  • /usr/share/php/
Executables
Perl
Packages
perl
perl-DBI
perl-DBD-MySQL
perl-DBD-Pg
perl-Perl-RPM
perl-File-MMagic
perl-Text-Kakasi
perl-SGMLSpm
perl-NKF
mod-perl
postgresql-perl
openssl-perl
gimp-perl
groff-perl
INstall dirs
  • /usr/bin/perl, perl5.6.0,perlbug,perlcc,perldoc
  • /usr/lib/perl5/5.6.0, man,site_perl, Tesxt
Executables
Python
Packages
python
python-devel
python-xmlrpc
python-tools
pythonlib
python-docs
postgresql-python
rpm-python
openssl-python
mod_python
INstall dirs
  • /usr/bin --> pythn, python1.5
  • /usr/include/python1.5
  • /usr/lib/python1.5
Executables
#python
Java
Packages
  • jikes
  • kaffe
INstall dirs
  • /usr/bin/javac, java,...
  • /usr/include/java
  • /usr/include/gnu/java
  • /usr/lib/linuxconf/java
Executables
  • javac
  • java
  • javadoc
  • keytool

...
Environment variables
Files：
  • ~/.profile
  • ~/.bashrc
  • ~/.bash_profile
  • ~/.cshrc
  • ~/.tcshrc
  • /etc/profile
  • /etc/bashrc
  • /etc/csh.cshrc
  • /etc/shrc
  • /etc/zshenv
  • /etc/rc
  • /etc/rc.sysinit
  • ...
Commands：
  • #CLASSPATH=
  • #export CLASSPATH
Java CLASSPATH (/etc/profile):

JAVA_HOME="/usr/local/java/jdk1.3"
export JAVA_HOME

PATH="$PATH:/usr/local/sbin:/usr/sbin:/bin:/usr/local/java/jdk1.3/bin:/usr/local/java/jdk1.3/jre/bin:."

export PATH

CLASSPATH="/usr/local/java/jdk1.3/lib:/usr/local/java/jdk1.3/jre/lib:."
export CLASSPATH
LINUX resources
  • http://www.linuxbyte.net
  • http://www.linuxaid.com.cn
  • http://www.linuxforum.net
  • http://www.linux-ok.com
  • http://www.linuxeden.com
  • http://www.ChinaLinuxPub.com
  • http://www.eastlinux.com
  • http://linux.ccpi.gov.cn/linux/index.html
  • http://www.RedhatLinux.onchina.net
  • http://www.rpmfind.net/linux/
  • http://badfish.3322.net
  • http://netsword.net
  • http://pro.newsea.net
  • http://www.linux.org/
  • http://cnheasa.org/linux/
  • http://www.gnu.org/
  • http://www.whlug.clinux.org/
  • http://www.freesoft.cei.gov.cn/
  • http://cosoft.org.cn/html/
  • http://www.heylinux.net/
Linux tech applications
How to recompile the Linux kernel ?

1 Install source codes from CD-ROM
cd /usr/src
gzip -cd linux-2.2.XX/tar.gz | tar xfv -

or if from patch（for kernel 2.2.XX), issue
cd /usr/src
gzip -cd patchXX.gz | patch -p0
or
cd /usr/src
bzip2 -cd patchXX.bz2 | patch -p0

2 Go to the source directory
cd /usr/src/linux

3 Delete old files incl. .o
make mrproper

4 Configure Linux kernel

make config or
make menuconfig or
make xconfig （recommended）or
make oldeconfig

5 Renew dependencies
make dep

6 Compile Linux kernel
make zImage
or if kernel too big,
make bzImage

7 Copy the kernel image to boot area
cp /usr/src/linux/arch/i386/

boot/zImage(or bzImage) /boot

8 Modify /etc/lilo.conf
run lilo again
lilo


Linux
如何对Linux的内核进行重新编译
作者：jdeveloper

缺省的Linux内核配置有时并不能满足我们的需要,例如，有时需要从Linux Mount NTFS格式的文件。

此时，需要我们对Linux的内核进行重新编译。其具体步骤如下：

1 首先要安装Linux源代码（从CD-ROM)
cd /usr/src
gzip -cd linux-2.2.XX/tar.gz | tar xfv -
如果是从patch安装（适合2.2.XX版本） 则
cd /usr/src
gzip -cd patchXX.gz | patch -p0
或者
cd /usr/src
bzip2 -cd patchXX.bz2 | patch -p0

2 进入到Linux源代码目录
cd /usr/src/linux

3 删除旧文件包括.o文件和一些依赖关系
make mrproper

4 配置Linux内核
几种方式
make config
make menuconfig
make xconfig （推荐您使用）
make oldeconfig

5 更新依赖关系
make dep

6 编译Linux内核
make zImage
如果内核太大 用
make bzImage

7 把编译后的内核映像(kernel image)拷贝到相应的启动区

cp /usr/src/linux/arch/i386/boot/zImage(or bzImage) /boot

8 修改/etc/lilo.conf
增加了新的启动选项 并注意备份旧的启动选项

重新运行lilo
lilo

结束。


Linux4win

Linux v Windows
在Linux下使用DOS/Windows磁盘

对大多数Linux用户，往往需要在Linux系统下使用DOS/Windows文档，这就涉及到如何在Linux环境下使用DOS/Windows磁盘的问题。下面从如何在Linux下使用DOS/Windows硬盘分区和软盘两个方面对这个问题作一个简单的介绍。

1．在Linux下使用DOS/Windows硬盘分区

    Linux有一个在根目录下启动的文件系统，根目录用一个斜线（/）表示。要在Linux下使用一个物理存储设备（如硬盘分区或CD-ROM）,必须先把该设备安装成为Linux文件系统的一部分。

    可以用mount命令在Linux文件系统的指定目录（安装点）下手工安装设备。比如笔者的机器上安装了一块IDE硬盘，在上面安装有WindowsMe和Linux系统。WindowsMe的主分区（C盘）是该硬盘的第一个分区，也就是Linux下的/dev/hda1。为了在Linux系统下访问WindowsMe的C盘，笔者在Linux的根目录下建立了名为/mswin/c:目录，并用如下的带分区类型选项 -t msdos（WindowsNT/2000的类型选项为 -t ntfs）的mount命令：

    mount -t msdos /dev/hda1 /mswin/c:

    安装该分区。现在WindowsMe的C盘就被映射到了Linux的/mswin/c:目录下，用户可以通过该目录访问WindowsMe的C盘上的数据，并且可以把数据保存到该目录下，以使WindowsMe可以在C盘上访问这些数据，达到在两个系统之间交换数据的目的。

    如果用户经常需要在Linux下访问DOS/Windows分区（笔者在使用Linux时多数情况下都用XMMS听保存在WindowsMe的D盘（/dev/hda5）上的MP3音乐），则可以通过在/etc/fstab文件中添加一行数据，使Linux在启动时自动安装该分区。比如，在笔者系统的fatab文件末尾添加了如下一行：

    /dev/hda5 /mswin/d: msdos defaults 0 0

    其中第一个参数指明了要安装的分区，第二个参数指定了安装点，第三个参数指定了分区类型，第四个参数表示按缺省方式安装。在以后启动Linux后，就可以在目录/mswin/d:下访问WindowsMe的D盘上的数据了。

    笔者曾经试用过几个Linux版本。有的Linux版本的安装程序会提示用户在安装的时候设置需要在Linux下访问的DOS/Windows分区。在使用冲浪Xteam3.0的时候，可以安装FAT32分区和NTFS分区，但是可能是内码不兼容的原因，在Linux下Windows文件的中文名字显示为乱码。更让人难以理解的是，在Redhat Linux 7.0下居然不支持NTFS分区。

2.在Linux下使用DOS软盘

    正如在可以在Linux系统中安装DOS硬盘分区一样，也可以安装DOS软盘。在缺省状态下，Linux定义了通用的软盘设备名：

    /dev/fd0，它是A驱动器（第一个软驱）

    并且系统通常还建立了安装点/mnt/floppy。因此，用如下命令就可以把DOS软盘安装到/mnt/floppy:

    mount -t msDOS /dev/fd0 /mnt/floppy

    安装成功后，就可以用常规的Linux命令访问DOS软盘。当要取出软盘时，首先应该卸载软盘。用umount命令卸载设备，如下所示：

    umount /dev/fd0

    但是，如果要频繁地更换软盘，上面的过程就显得十分繁琐。因此，通常都用mtools软件包来访问软盘。mtools软件包可以执行大多数常用的DOS命令，这些命令名除了要在每个命令前添加m前缀外，与DOS中相同。例如命令

    mdir a:
    mcd "a:\sample"
    mcopy "a:\*.dat" .

    分别列出A盘上的文件、进入A盘的sample目录、将A盘上的所有以.dat为扩展名的文件拷贝到Linux的当前目录下。需要说明的是，上面之所以用到了双引号，是为了避免shell错误地解释通配符"*"和DOS地目录分隔符"/"。

    在Linux下格式化DOS软盘的时候，尽管mtools工具包提供了mformat实用程序，它可以格式化用于DOS的软盘。但是不像DOS的format命令那样，mformat命令需要执行两步过程来准备软盘：用fdformat命令（Linux命令）低级格式化软盘；用mformat a:命令把DOS文件系统放在低级格式化过的软盘上。
沟通Linux和Winodws的Wine

     据Netcraft网站调查，现在互联网上的主机有75％以上采用Linux作为操作系统。作为服务器操作系统，Linux已经站稳了脚步，可是在桌面操作系统上，还是微软的“瘟到死”一支独秀。这倒不是说Linux不好，很大原因我觉得是因为应用程序太少.

     其实Linux开发者们很早就认识到了这点，他们也有针对性地开发了可以在DOS下使用的DosEmu，可以使用Windows软件的Wine（Wine Is Not a Emulator，Wine不仅仅是一个模拟器）。说实话前年我就使用了Wine，可是当时为了使用一下Windows下的“记事本”竟花了我两天的时间，真是苦不堪言。这两天无意识地到了Wine站点逛了一圈，竟发现Wine 1.0发布在即，而且功能也今非昔比:ACDSee、WinAmp、WinZip甚至“星际争霸”都可以玩呢？不信，跟我来看看……

下载安装

     Wine的官方站点是http://www.winehq.com/，虽然你可以在它的官方站点下载源代码，自己配置编译，不过这个过程可是比较繁琐的！如果你和我一样，也是使用基于RPM包安装方式的Linux发行版本（像我们最常见的RedHat和Mandrake都属于该种类型），建议你到CodeWeavers下载一个已经编译好的发行版本，省了编译之苦，何乐而不为呢？

     1.下载Wine
     CodeWeavers Wine的最新版本是Wine 1.0 Preview 2（Wine 1.0的预发行版本2），网址是http://www.codeweavers.com/wine/download.html，下载文件名为codeweavers-wine-20010112-1.i386.rpm。

     2.安装
     以root用户登录，安装Wine，不过安装之前你需要删除以前的版本（我的Linux是RedHat 7.0）:
    rpm -qa |grep wine ;查询以前安装的Linux版本
     如果显示的是wine-xxxxx-xxx（不同的Linux发行版本，显示的可能不一样），则可执行下列命令删除:
     rpm -e wine-xxxxx-xxx
     然后执行下列命令安装新下载的Wine:
     rpm -ivh codeweavers-wine-20010112-1.i386.rpm

     3.加载Windows分区
     执行以下命令将Windows的C分区加载到Linux下的/mnt/dosc目录:
     mkdir /mnt/dosc
     mount -t vfat /dev/hda1 /mnt/dosc

设置Wine

     Wine的设置很简单，窗口模式只用鼠标指指点点就可以完成，你再也不用去设置那个繁琐的wine.conf配置文件了。

   1.进入X Window窗口界面
     startx

  2.执行winesetup打开Wine设置程序
     注意:需要提醒你一句，为了安全起见，Wine不允许以root登录配置Wine，你最好还是建立一个普通用户吧……

  3.选择Windows安装路径
     Wine设置程序会自动查找、设置Windows目录（当然你需要事先将Windows所在的分区加载到Linux分区的某一个目录下边）。

  4.最后的调整
     设置已经结束了，不过为了将来界面更友好一些，你可以在“Basic”/“Look & Feel”/“Windows Version”选项中，将Windows的版本号设置为“Windows 98”。

运行应用程序

     可以通过两种方式运行:

     1.自动运行
     在KDE或者GNOME的文件管理器中切换到应用程序所在目录，单击就可以打开（双击可是打开两个哦！）。虽然程序运行速度十分缓慢，不过聊胜于无，我在RedHat 7.0下可以用FlashGet（是不是受够了Linux下命令行方式的wget）、用WinAmp听音乐，还可以打开“扑克牌”游戏来休闲一下，老比知道了可不要被气死？！

     2.手工运行
     在Console模式下，键入以下命令:
     wine <你想运行的应用程序>
     没有Winodws也可用Winzip
     如果有这么一天，你完全删除了Windows，在硬盘上只装了一个Linux（什么？不可能有这种情况！你不用往下看了），可是还是想用Winzip，怎么办呢？重新安装一个Windows，然后再安装一个Winzip专供Linux调用。其实没有这么麻烦:
     重新运行winesetup，在配置Windows安装路径窗口中，选择“Create a new windows directory（创建一个新的Windows安装目录）”，其它的一切都很简单，在Linux中直接运行Winzip安装文件安装Winzip然后就可以调用了。

注意： wine 目前不支持Windows Nt & Windows 2000


Linux4win

沟通Linux和Winodws的Wine

     据Netcraft网站调查，现在互联网上的主机有75％以上采用Linux作为操作系统。作为服务器操作系统，Linux已经站稳了脚步，可是在桌面操作系统上，还是微软的“瘟到死”一支独秀。这倒不是说Linux不好，很大原因我觉得是因为应用程序太少，不说Linux下没有ACDSee、没有Office、没有Winamp，即使是标榜可以和PhotoShop抗衡的Gimp在我看来也不过如此，更不用那说满天的ICQ克隆，但却没有一个像Windows下的ICQ那样好用！

     其实Linux开发者们很早就认识到了这点，他们也有针对性地开发了可以在DOS下使用的DosEmu，可以使用Windows软件的Wine（Wine Is Not a Emulator，Wine不仅仅是一个模拟器）。说实话前年我就使用了Wine，可是当时为了使用一下Windows下的“记事本”竟花了我两天的时间，真是苦不堪言。这两天无意识地到了Wine站点逛了一圈，竟发现Wine 1.0发布在即，而且功能也今非昔比:ACDSee、WinAmp、WinZip甚至“星际争霸”都可以玩呢？不信，跟我来看看……

     下载安装
     Wine的官方站点是http://www.winehq.com/，虽然你可以在它的官方站点下载源代码，自己配置编译，不过这个过程可是比较繁琐的！如果你和我一样，也是使用基于RPM包安装方式的Linux发行版本（像我们最常见的RedHat和Mandrake都属于该种类型），建议你到CodeWeavers下载一个已经编译好的发行版本，省了编译之苦，何乐而不为呢？

     1.下载Wine
     CodeWeavers Wine的最新版本是Wine 1.0 Preview 2（Wine 1.0的预发行版本2），网址是http://www.codeweavers.com/wine/download.html，下载文件名为codeweavers-wine-20010112-1.i386.rpm。

     2.安装
     以root用户登录，安装Wine，不过安装之前你需要删除以前的版本（我的Linux是RedHat 7.0）:
    rpm -qa |grep wine ;查询以前安装的Linux版本
     如果显示的是wine-xxxxx-xxx（不同的Linux发行版本，显示的可能不一样），则可执行下列命令删除:
     rpm -e wine-xxxxx-xxx
     然后执行下列命令安装新下载的Wine:
     rpm -ivh codeweavers-wine-20010112-1.i386.rpm

     3.加载Windows分区
     执行以下命令将Windows的C分区加载到Linux下的/mnt/dosc目录:
     mkdir /mnt/dosc
     mount -t vfat /dev/hda1 /mnt/dosc

     设置Wine
     Wine的设置很简单，窗口模式只用鼠标指指点点就可以完成，你再也不用去设置那个繁琐的wine.conf配置文件了。

   1.进入X Window窗口界面
     startx
     2.执行winesetup打开Wine设置程序
     注意:需要提醒你一句，为了安全起见，Wine不允许以root登录配置Wine，你最好还是建立一个普通用户吧……

     3.选择Windows安装路径
     Wine设置程序会自动查找、设置Windows目录（当然你需要事先将Windows所在的分区加载到Linux分区的某一个目录下边）。

     4.最后的调整
     设置已经结束了，不过为了将来界面更友好一些，你可以在“Basic”/“Look & Feel”/“Windows Version”选项中，将Windows的版本号设置为“Windows 98”。

     运行应用程序
     可以通过两种方式运行:

     1.自动运行
     在KDE或者GNOME的文件管理器中切换到应用程序所在目录，单击就可以打开（双击可是打开两个哦！）。虽然程序运行速度十分缓慢，不过聊胜于无，我在RedHat 7.0下可以用FlashGet（是不是受够了Linux下命令行方式的wget）、用WinAmp听音乐，还可以打开“扑克牌”游戏来休闲一下，老比知道了可不要被气死？！

     2.手工运行
     在Console模式下，键入以下命令:
     wine <你想运行的应用程序>
     没有Winodws也可用Winzip
     如果有这么一天，你完全删除了Windows，在硬盘上只装了一个Linux（什么？不可能有这种情况！你不用往下看了），可是还是想用Winzip，怎么办呢？重新安装一个Windows，然后再安装一个Winzip专供Linux调用。其实没有这么麻烦:
     重新运行winesetup，在配置Windows安装路径窗口中，选择“Create a new windows directory（创建一个新的Windows安装目录）”，其它的一切都很简单，在Linux中直接运行Winzip安装文件安装Winzip然后就可以调用了。

     战斗于星际
     前几天在国外一个著名的LinuxGames网站看到了一篇文章,介绍如何在Linux下通过Wine加入“星际争霸”Battle.net网络连线对战。想一想，如果和朋友们说你是用Linux和他们连网共战“星际”，他们会如何惊讶！

     不过要想在Linux下战斗于“星际”Bettle.net（网络对战），你需要做一下事情:
     1.到http://wine.dataparty.no/下载一个Wine安装版本，上边我给你介绍的CodeWeavers不能正常运行。
     2.反安装以前版本的Wine，安装从DataParty下载的Wine。
     3.运行“星际”的时候请用全屏幕模式（Full-Screen），如果你使用窗口模式，“星际”可能不能正常运行（不过你可以使用True-type字库，它可以让你运行于窗口模式）。

     如果你原先保留Windows的唯一理由是决战StarCraft，那么现在是你执行Format c:的时候了！


Linux windows

Linux v Windows
Use DOS/Windows hard/floppy disks under Linux

1．Use DOS/Windows hard disks under Linux

     First make a directory for the windows system, let's name it /mswin/c

Then issue this command:

     mount -t msdos /dev/hda1 /mswin/c or mount -t vfat /dev/hda1 /mswin/c or mount -t ntfs /dev/hda1 /mswin/c

where /dev/hda1 is the first partition of the first hard disk where a windows system is installed.

To allow the system auto-mount the windows hard disk, add the following lines to /etc/fstab:

     /dev/hda5 /mswin/d: msdos defaults 0 0

     Currently Redhat 7.0 doesn't support NTFS file system.

2.Use Windows Floppy Under Linux

    Issue the following command:

    mount -t msDOS /dev/fd0 /mnt/floppy

    To de-mount:

    umount /dev/fd0

    If floppy is very often mounted, use the mtools package to access it. For example:

    mdir a: - show directories
    mcd "a:\sample" - make a directory
    mcopy "a:\*.dat" . -copy files

    All commands are equivalent to DOS commands except the extra m letter.


Sendmail
linux邮件系统入门
首先简单的介绍一下邮件系统，主要由两部分组成：smtp协议(简单邮件传输协议) 和pop3(邮局协议version 3)，smtp用于邮件在网络中的传递(mailer),而pop处理客户端邮件的接收。由于pop3的局限，将来肯定要被imap代替，imap有较好的目录服务能力，可以在下载之前看到邮件的主要信息如来源、标题等，还可以远程删除邮件等，但目前ISP还不会轻易用它来替换pop.注意不要与IAP的POP搞混淆了，那是当前接入点的意思(Point Of Present)。学得越多越糊涂:-(最早在Linux传递邮件用的是smtp服务，在/etc/inetd.conf里可以看到这样一行：

现在基本都用sendmail这样功能强大的deamon程序来做(nntp也是如此)。所以sendmail只是邮件传递者(mailer),它把这个主机上的邮件发送到其他地方，注意到配置DNS时有一项MX(Mail eXchang,邮件网关)，使用sendmail在你的网内要有一个DNS服务器。而处理主机上远程客户的邮件服务则要有pop服务，查看inetd.conf有这么几项：

pop-2 stream tcp nowait root /usr/sbin/tcpd ipop2d
pop-3 stream tcp nowait root /usr/sbin/tcpd ipop3d
imap stream tcp nowait root /usr/sbin/tcpd imap

再查看/etc/service就知道它们对应的端口号，用telnet host-name port试试能看到什么？Linux这样的东西通常是用来做服务的，当然有很多人把它用作个人桌面也不错，但是新手就不知道如何去收他们在ISP的邮件了，其实很简单，只需要装个pop/imap的客户端软件就行了，netscape的套件就是很好的选择，KDE带的邮件客户端软件也不错，支持多帐号，就是不直接支持中文(用zhXwin吧)，或者用fetchmail把邮件抓回来转发到本地主机的客户，在本地主机上用mail程序来读。

我感觉mail程序好象是直接处理邮件队列，不知对不对。使用mail程序问得最多的问题是，在输入正文时怎么结束？另起一行输入一个"."就行了！

上面讲的是现在internet上的邮件系统，在internet出现以前电子邮件系统就有了，比如在uucp/BBS上，还有其它类型的网络上，就在internet发达的今天，这样的网络系统仍然与之并存。AOL、赢海威(IHWY)的网络上就不是标准的Internet电子邮件。
我以前就上过电信局的基于X.25网（准确的说应该是中国公用分组交换数据网CHINAPAC)的电子邮件系统，优点是真正的帐号漫游，缺点是速度太慢（至多9600bps,x.25本来就不快)，后来承诺要建一个X.400网关与Internet上的邮件系统转发信件，也不知道后来怎样了，因为我早已不用它，在IP over everthing的今天......

关于mail list功能，可以用sendmail的别名来做，或者用专门的软件majordomo.到中国自由软件库或者swjtu.edu.cn上去可以搜寻到。它的FAQ由barr维护。至于WebMail,可以到www.perl.com上找找有没有现成的CGI.现成的软件其实也很多如WeMail,WebMail Folder,WebMail Module(Roxen),Fetchmail(也可以哟,商业性的)IMP(IMAP WebMail)以及HTMail。

<a href=" http://horde.org/imp/">http ://horde.org/imp/</a> <a href=" http://www.chaotika.net/code/HTMail">http ://www.chaotika.net/code/HTMail</a>

Sendmail 安装指南

一个默认的sendmail.cf文件将被安装在/etc下。该配置文件可工作于仅使用SMTP的站点。而不能工作于UUCP站点；如果您要使用UUCP进行邮件传输就得重新生成一个新的sendmail.cf。这样的话，您就需要安装m4和sendmail的源代码包。请您阅读sendmail 源代码中的README以获取更为详尽的创建snedmail配置文件的方法。也可以看 O'Reilly&Associates出版的一本有关sendmail的不错的参考书（作者：Bryan Costales).

一种常用的sendmail的配置用一台机器作为网络中所有主机的邮件网关。打个比方，在红帽子软件公司我们有一台地址为mail.redhat.com的机器来处理我们所有的邮件。 我们只需简单的将mail.redhat.com要处理邮件的机器的名字加入/etc/sendmail.cw。下面 是该文件的一个例子：

torgo.redhat.com
poodle.redhat.com
devel.redhat.com

同样在torgo,poodle和devel的那些机器中编辑/etc/sendmail.cf，使其象mail.redhat.com 那样发送邮件，转发本地的邮件给redhat.com。 编辑含DH和DM的那些行：

DRmail.redhat.com

DHmail.redhat.com

DMredhat.com

以这种配置，所有发出的邮件都好象是从redhat.com发出的，而任何发往torgo.redhat.com 和其它机器的邮件都将发送给mail.redhat.com

请注意，如果您将您的系统配置为以另一机器身份发送邮件的话，任何以本系统为目的的邮件都将被发送至那台主机。比如，由cron进程定期产生的发网 <a href="mailto: root@poodle.redhat.com "> root@poodle.redhat.com </a> 日志文件都将发送给
<a href="mailto: root@mail.redhat.com "> root@mail.redhat.com </a> 。

E.10.3 我已经升级到 5.0 , sendmail 不再像以前一样传送邮件 .该做什么 ?

由于多方面的电子邮件商使用未知的 Red Hat 系统发送邮件和一些其他问题, 在 5.0 中, 我们将(不作为邮件传递者)作为缺省选项 .

你可以将你允许传递邮件的系统名称加入到文件
/etc/relay_allow

web 站点 <a href=" http://www.informatik.uni-kiel.de/~ca/email/check.html">http ://www.informatik.uni-kiel.de/~ca/email/check.html</a> 将告诉你更多关于这方面的信息 .

如果你希望某些发送垃圾邮件的站点不能访问到你的计算机, 你可以使用 sendmail 的一些新特性拒绝他们的访问. 将这些站点的地址加入到文件 /etc/mail/deny 中, 然后为它生成一个散列表 .

下面的命令可以生成这种散列表 .

makemap -v hash /etc/mail/deny < /etc/mail/deny

sendmail配置入门

学linux久了，也写点东西让大家共享 为了能从网络上接收SMTP电子邮件，我们必须在Linux系统上运行Sendmail守护进程。命令是；

为了方便起见，我们应该使用ntsysv命令把Sendmail守护进程加到引导程序中,在多数情况下，安装时Linux就已经自动将Sendmail包含在引导程序中了。这样每次开机时，Linux都会启动Sendmail守护进程并侦听端口25，处理进入的邮件
。
Sendmail的配置文件是/etc/sendmail.cf文件，它包含大部分的Sendmail配置的信息，包括在用户邮件程序和邮件传输程序之间为邮件选择路由所需的信息。Sendmail.cf文件有三个主要功能：

·定义Sendmail环境。
·按照接收邮件程序的语法重写地址。
·将地址映射成传送邮件所需的指令。
执行所有这些功能需要若干命令。一些宏定义和可选用的命令可定义其环境
，一些重写规则可以重写电子邮件的地址，一些邮件程序定义可定义传送邮件所
必需的指令。

sendmail.cf文件很大，看上去可复杂，但我们需要改动的地方很少。主要在local info中做文章。请在文件中寻找“Cw”，原来产生的cf 文件，Cw应是：

Cwlocalhost

请在localhost之后加上我们那一台机器所有可能用来当收信地址的主机的名字。例如，在局域网络Virtual Brewery中的一台机器叫：vlager.vbrew.com，而且也叫gopher.vbrew.com，而该网络的管理员希望这一台机器的这两个名字都能收信，那么他需要这样修改sendmail.cf文件：Cwlocalhost vlager.vbrew.com gopher.vbrew.com上面只是一种简便的方法，如果系统中运行着DNS，我们可以通过DNS来解析主机别名（如下所示），而不用加上主机别名gopher.vbrew.com。如果没有运行DNS，那么必须将本机器的所有名字都写上。如果用作邮件服务器的主机有多个名字（hostname），例如：
vlager IN A 191.72.1.1
gopher IN CNAME vlager
那么我们可以不必在Cw上标明，系统会透过DNS 找到它的别名如果一台机器有多个名字，但是每一个别名是用A record 建立的，例如：

vlager IN A 191.72.1.1
gopher IN A 191.72.1.1

在这种情况下【一定】要记得在Cw后写上所要收信主机的名字。如果忘记了，那么从外面寄来的以别名为地址的信件将无法正常接收，机器会抱怨：
“Local configuration error”
例如，如果在sendmail.cf中的Cw这行是Cw vlager.vbrew.com，那么局域网Virtual Brewery中的用户将无法使用邮件地址 username@gopher.vbrew.com 而只能用username@ vlager.vbrew.com，否则将出现上述错误。
如果一台机器有多interface，各interface有其本身的名字，而且要收信。这种情况也要在Cw之後写明所有要收信的hostname。
在我们的例子中F命令是作为注释处理的，如果去掉它前面的“sendmail将从/etc/sendmail.cw中读取主机的别名，并将别名储存在类w中。将F命令做注释处理，并让sendmail在内部定义别名这是一种最常用的方法。

打开/etc/mail/access文件时，会看到（注意一些系统的access文件不再/etc/mail下，如找不到请用whereis查找或检查是否安装正常）：

iption

le)

l-doc

localhost.localdomain RELAY
localhost RELAY

如果我们主机的IP地址是191.72.1.1的话，就应该在最后一行加上它的记录项，这样，我们修改后的文件的最后三行应是：

localhost.localdomain RELAY
localhost RELAY
191.72.1.1 RELAY

加上这句话我们就可以用sendmail发送接收mail了。但是如果我们想让别人也可以使用sendmail的话，而他的IP是202.168.25.22，这样就在在最后一行加入 他的主机的记录项，这时文件的最后四行应是：
localhost.localdomain RELAY

localhost RELAY
191.72.1.1 RELAY
202.168.25.22 RELAY

当我们考虑到多用户的时候，sendmail允许我们添入整个B类或C类地址，其格式如下：
localhost.localdomain RELAY
localhost RELAY
191.72 RELAY
202.168.25 RELAY

这样，我们就是把整个网络都加入的sendmail中，这个地址中的用户，如果在我们的系统里有账号的话，可以使用sendmail收发信件了。

Linux还允许我们设置邮局协议（POP）邮件服务器，POP协议分两个版本POP2和POP3，很显然POP3是新版本的邮局协议，现在Internet网上主要是POP3协议。POP3并不需要我们来配置，RedHat已经为我们做好了这一工作。我们只需要修改一下 /etc/inetd.conf文件，确保POP3能正常工作即可：

查找到：

把这一行前面的“

在该文件中查找到

同样，将这一行前面的注释符“netd和sendmail守护进程：

在我们配置完sendmail后，可以运行以下的命令来检查目录的读写权限以检查潜在的安全漏洞。

这时，sendmail将开始初始化alias数据，如果在屏幕上回显：
WARNING: writable directory /etc
WARNING: writable directory /usr/spool/mqueue
那么这个目录列出了不适当的写特权，应该使用chmod和 chown命令以避免多方面的的安全攻击。一般我们需要对如下目录运行chmod和chown命令：

mqueue

mqueue
sendmail 的有一些参数可以用于验证地址处理的结果，以确保其新配置的合理性。一旦认为配置可以正常工作了，我们就可以选择各个站点上的朋友，并将邮件发送给他们。发送时使用-v参数就可以显示邮件传输的各个细节和两个站点之间进行SMTP交换的全过程。下面是一个测试的例子，使用的文件是test.cf，一旦测试成功，我们就可以将这个文件拷贝到/etc下并可以改名为sendmail.cf。

To: lack@vlager.vbrew.com
From:janet
Subject:Test for sendmail

Lack,please reply if you see this,Thanks.

^D
lark@ vlager.vbrew.com…..Connecting to vlager.vbrew.com via t
cp…
Trying 191.72.1.1 ….connected.
220 VLAGER.VBREW.COM on Web, 30 Sep 99 16:23:23 CST
>>> HELLO maths.groucho.edu
250 VLAGER.VBREW.COM is my domain name
>>> MAIL From:< gauss.maths.groucho.edu.>
250 OK
>>> DATE
354 Enter mail body, End by new line with just a ‘.’
>>>.
250 Mail Delivered
>>> QUIT
221 VLAGER.VBREW.COM closing connection
lack@vlager.vbrew.com …sent
我们在CTRL-D之前输入所有的内容，而sendmail则显示^D之后的内容。通过对sendmail的测试，我们就可以发现潜在的配置问题，并使用sendmail提供的一些附加查错工具解决这些问题。

RedHat6.2服务器配置方案 Sendmail

1 简 介

邮件服务是用户所需要的最重要的网络服务。Web的通信量很大，但邮件主要用于个人之间的通信，而人－人的通信是商务的基础。没有邮件服务的网络是不完整的网络。换句话说，如果不能给用户提供完整的TCP/IP下的邮件支持，这样的网络操作系统也不值得信赖。
配置sendmail是一件大而复杂的工作，但也不完全都是这样，与其他一些网络服务器系统只安装SMTP服务器软件的情况相比，Linux已经配置好了多数的设置。在多数系统下，缺省配置都能良好的运行。我将在本章中给出一些配置的建议，主要的一些配置参数建议大家不要随意更改。

2 所需系统资源

2.1 配置文件：
文件　　　　　　　　　　　　　　来源
/etc/sendmail.cf　　　　　　　　sendmail-8.9.3-20.i386.rpm
/etc/sendmail.cw　　　　　　　　sendmail-8.9.3-20.i386.rpm

2.2 相关工具：
文件　　　　　　　　　　　　　　来源
/etc/rc.d/init.d/sendmail　　　 sendmail-8.9.3-20.i386.rpm

3 配置方案

1．/etc/sendmail.cf sendmail的主配置文件
作用：

控制sendmail运行时的配置。完整的sendmail配置应该包括7部分：
Local Info（本地信息）：这部分定义了本地主机的信息
Options（选项）：用来设置定义sendmail环境的选项。
Message Precedence（消息的优先级）：sendmail消息的优先级
Trusted Users（信任用户）：定义发送邮件时允许改变发送地址的用户
Format of Headers（头格式）：定义在sendmail中插入的邮件头信息
Rewriting Rules（改写规则）：这部分保存着改写邮件地址命令使用该命令可以将邮件地址从用户邮件程序的地址形式改写为邮件发送程序所需要的地址形式。
Mailer Definition（邮寄者说明）：定义发送邮件的程序，改写规则是邮件者使用的规则，在本部分定义。
其实，配置一个完整的sendmail服务器是一件极其复杂的工程，然而对于我们所适用的范围来说，很多的功能是没有必要的，所以我想以一个简单的例子来说明我们的配置，也就是说，没有被提出的配置在一般情况下是不需要我们的管理员来考虑的，你按照默认的做就可以了。

实例：

V8/Berkeley
Cwlocalhost
Fw /etc/sendmail.cw
CP.
DYuunet.uu.net
CPUUCP
DS thj.mycompany.com
CO @ % !
C..
C[[
Kmailertable hash -o /etc/mail/mailertable
＃制作db库
Kdomaintable hash -o /etc/mail/domaintable
Kgenerics hash -o /etc/mail/genericstable
Kvirtuser hash -o /etc/mail/virtusertable
Kaccess hash -o /etc/mail/access
Kmxserved bestmx -z: -T<TEMP>
Kresolve host -a<OK> -T<TEMP>
FR-o /etc/mail/relay-domains
DR
DH
Kdequote dequote
CM root
DM thj.mycompany.com
＃设置邮件服务器名称
DnMAILER-DAEMON
CPREDIRECT
DZ8.9.3
O SevenBitInput=False
O EightBitMode=pass8
O AliasWait=10
O AliasFile=/etc/mail/aliases,/etc/mail/majordomo
O MinFreeBlocks=100
＃规定最小空闲块
O MaxMessageSize=1000000
＃指定用户一次最大发送的邮件大小
O BlankSub=.
O HoldExpensive=False
O DeliveryMode=background
O AutoRebuildAliases=true
O TempFileMode=0600
O HelpFile=/etc/mail/sendmail.hf
O SendMimeErrors=True
O ForwardPath=$z/.forward.$w:$z/.forward
O ConnectionCacheSize=2
O ConnectionCacheTimeout=5m
O UseErrorsTo=False
O LogLevel=9
＃记录到日志文件的事件等级
O CheckAliases=False
O OldStyleHeaders=True
O PrivacyOptions=authwarnings,noexpn,novrfy
O QueueDirectory=/var/spool/mqueue
O Timeout.queuereturn=4d
O Timeout.queuewarn=4h
O SuperSafe=True
O StatusFile=/var/log/sendmail.st
O DefaultUser=8:12
O SmtpGreetingMessage=$j Sendmail $v/$Z; $b
O UnixFromLine=From $g $d
O OperatorChars=.:%@!^/[]+
Pfirst-class=0
Pspecial-delivery=100
Plist=-30
Pbulk=-60
Pjunk=-100
Ft -o /etc/mail/sendmail.ct
Troot
Tdaemon
Tuucp
R$* $
＃以上是Linux默认的选项，不允许客户机使用mail服务器收发邮件，如果允许客户机收发的话应将上边一句话改成
R$- $@ok
＃注意：中间是两个tab键
＃一下是邮件头信息
H?P?Return-Path: <$g>
HReceived: $?sfrom $s $.$?_($?s$|from $.$_)
H?D?Resent-Date: $a
H?D?Date: $a
H?F?Resent-From: $?x$x <$g>$|$g$.
H?F?From: $?x$x <$g>$|$g$.
H?x?Full-Name: $x
H?M?Resent-Message-Id: <$t.$i@$j>
H?M?Message-Id: $t.$i@$j
＃以上是邮件头信息

2．管理员需要执行touch /etc/mail/aliases 和 touch /etc/mail/majordomo来创建两个文件，然后重新启动sendmail，利用sendmail.cf里生成db库的配置来生成两个库文件：aliases.db和majordomo.db；当然，管理员也可以通过执行makemap hash mailertable < mailertable来生成新的db，这样可以不重新启动。

4 测试及管理方法

1． 管理员可以通过执行/etc/rc.d/init.d/sendmail restart来使更改的配置生效。
2． 管理员通过执行 fetchmail -u yourname yourserver 来为没有邮件用户制定他们的口令，用户需要在客户端作相应的设置。
3．管理员应该打开pop3服务，即更改配置文件
4．管理员在服务器上可以通过执行 echo test | /usr/sbin/sendmail -v thj@mycompany.com 来测试建立好的邮件用户是否能够正常工作。

Sendmail的配置(行的!)

Sendmail对一般的系统管理者而言，往往是个不敢手的「禁区」 ，因为绝大多数系统的使用者对E-Mail的需求与依赖的程度之高，可说是稍有分毫差错，系统管理者就要准备接受如雪片般飞来的抗议与 抱怨！而Sendmail这个东东的「内函」，似乎又有点不太容易理解： 与设定有关的sendmail.cf 档，如果不是下过一番死功夫，则读起来如同读天书一样，只知道里面有英文字与
数字！所以一般人总是能不 动则不动，只要能用就好。不过，很不幸的，一般跟著机器而来的sendmail总是有著令人心惊胆跳的「附加功能」，就是常常都有一些可以让无聊人士作为侵入路径的BUG 或後门，某些BUG 还可以让侵入 者经由Sendmail而取得最高权限的root！一旦root权限被人拿走了， 那麽这机器就可被人任意屠宰，最恶劣的，还可能破坏系统！

    Sun 在国内的使用人口相当的多，笔者对Sun 也稍微比较熟悉一点。不过，Sun的Sendmail却是令人颇不敢恭维的，几乎可以说：只要还在使用Sun 的Sendmail而没有「常常」patch 的话，那甚麽系统安全都不必谈了，谈了也是白谈；如果还在使用Sun 的Sendmail，那就如果系统抱著一颗不定时炸弹，随时一个不注意，都可能引爆:(。这一点，大家可以翻一翻CERT或8lgm看一看，几乎是只要有sendmail 的问题，Sun 大多跑了....。其他系统的Sendmail也不要偷笑，虽然大家的出场率没有Sun 高，可是也常会问题的。 另一方面，Sendmail 8.6.9与之前的版本最近刚发现有个ident方面的Bug 。如果方便的话，请大家务必换成最新版。如果不方便的话，在v8.6.5之後的版本有个克难式的补救法，即在sendmail.cf 加入这麽一行：
    Orident=0
    表示不作ident 的检查。
    v8.6.5之前的版本就一定要换成最新版。

    本软体在系统安全方面，是目前评价最高的，目前已知的BUG都已经改好了，最主要的原因，当然是要感谢作者Eric Allman ，他(或他们)能作到一发现重大的Bug (如系统安装)就立刻出新版。本软体是一public domain ，可以在网路上各ftp server上找到其source code。由於该软体的发展者把一些必要的设定步骤自动化了，所以，其实安装这个软体并不是想像中那麽样的困难。如果连compile 的时间也算下去，顺利的话，不用半个小时就可以安装完毕！所以，「麦惊」啦！：
）

安装Sendmail

1 下载Sendmail最新版本

    最新版本的Sendmail可以从 http://ftp.sendmail.org/pub/sendmail/ 得到！如 sendmail.8.9.3.tar.gz 这是截止到文章发布的最新版本，size：1068290byte 有关最新版本的发布，请浏览Sendmail的主页 http://www.sendmail.org/

2 安装Sendmail

    用root登陆或su成root后，先把tar.gz的包解开tar fvxz sendmail.8.9.3.tar.gz,用make-f 开始编译

    编译完成后系统会产生系统设定文件，也就是sendmail.cf （一般这个文件都存放在/etc下）

    接下来，这按几步继续安装： (注：～/sendmail为解开后的sendmail目录）

    1.请切换至设定档目录～/sendmail/cf/cf 之下。找一个合适自己系统的XXXX.mc档。笔者一般上是使用tcpproto.mc 这一个不用uucp的档。如果是用tcpproto.mc 这个档，笔者在solaris2.3 试了，得记得在档中要加上一行：
    OSTYPE(solaris2)
    Sun 4.1.3 不必，其他系统就不晓得了。在目录 ～/sendmail/cf/ostype下有几个OSTYPE()可以的 档，只有这个目录有资料的才可能能够OSTYPE()。还有， 如果是 system V的/bin/mail，似乎就得要加OSTYPE()。
    一句老话，详情请看DOCUMENT：～/sendmail/cf/README。这希望有经验的朋友能够补充：）　　如果不小心忘了加上OSTYPE()会怎样？也不会怎样，只会有"unknow mailer error" 的错误，然後信收不到。
    有一点要提醒大家的，就是：在～/sendmail/cf/cf 所看到的各种系统的.mc 档，都是Sendmail 8.6.x的作者 Eric Allman 「演示」给大家看的，所以，可以看到档名都有个"cs"，要是没有修改就用这些档的话，那一定会发生错误的。而要修改，有相当多地方要改，所以，如笔者一般懒的人，用tcpproto.mc 还是比较简单又不会出错:)

    2.好，选定了某一个合意的.mc 档，那接下来可执行m4产生.cf 档。请下指令：

    要是还是不行，那就请去抓新版的m4回来compile （可以在 http://www.gnu.org/ 找到gnu的m4）。

    这个步骤是要把compile好的files, install 到系统上去了。

    罗嗦的我还是得再一次提醒您看看：把旧档案备份好了吗？

    好，假设compile 的结果非常没挑战性的没有任何错误，产生.cf 档过程也没有甚麽值得注意的讯息。所产生的.cf 档 也改好了。而且最重要的：作好旧档的备份（不是我要吓人，这是以防万一）。

    1.挑个老板没有在用mail的时间，快手快脚的切换至目录～/sendmail/src ，下指令：

    系统会把compile出来的～/sendmail/src/sendmail与man document拷贝到它们该有的目录（所以你还如果没有备份/usr/lib/sendmail ，那赶快祈祷待回不要出问题，要不然就赶快准备泪水哭吧！ 因为旧的会被compile 出来的sendmail覆盖）

    2.切换至目录～/sendmail/cf/cf ，把产生出来的YYY.cf档拷贝到本系统sendmail.cf 应该在的地方，如：/etc或 /etc/mail 。

    3.把旧sendmail daemon 的process 杀掉。（这应该不用我罗嗦吧！用ps -ax |grep sendmail |grep -v grep 找出旧daemon的process(或head -1/etc/sendmail.pid　或 head -1/etc/mail/sendmail.pid)，然后用 kill -9 processID干掉它(或直接用 kill -9 `head -1 /etc/sendmail.pid`)。

    4.启动新daemon。例如下指令：
    /usr/lib/sendmail -bd -q30m
    当然，保守一点，看旧的daemon怎麽跑，照旧的来下参数应该是没有问题。
    这时,初步安装就已经完成了，接下来请看设置sendmail

3安装Sendmail注意事项

    如果安装不成功，请参考下面的问题：
    用vi或任一种编辑器，编辑的makefile档，作一点点 必要的修改。所要修改的地方不多，下面是可能要修改的地方：

    1."CC ="如果原档所用的compiler并不是我们系统的，这才要改。

    2.本系统是否有安装Berkerlay 的New database？如果有，跳过本点，到第3点。 如果没有（如：一般SunOS 都没有装），那麽请修改这几 行（下面以Makefile.SunOS为例，但其他系统也类似）：

    A.在 DBMDEF= -DNDBM -DNEWDB -DNIS 一行，请改成： DBMDEF= -DNDBM -DNIS （即去掉-DNEWDB）

    B.把这两行REMARK起来： INCDIRS=-I/usr/sww/include/db -->INCDIRS=-I/usr/sww/include/db
LIBDIRS=-L/usr/sww/lib -->

    C.修改LIBS= -ldb -ldbm -lresolv 这一行成： LIBS= -ldbm -lresolv （即去掉-db ）

    3.把nroff 的"-mandoc "参数改成一般系统可以接受的 "-man"（当然，这得依你的系统而定，如果你是用groff，那就可以很愉快的直接使用，不必改这个参数:)。如果不改也并不会影响sendmail的安装，只是不能看到格式化後的sendmail相关文件罢了。

    关于DIRECTORY PERMISSIONS的问题你需要执行2条命令：

    chmod go-w / /etc /etc/mail /usr /var /var/spool /var/spool/mqueue
    chown root / /etc /etc/mail /usr /var /var/spool /var/spool/mqueue

    许多系统的spool目录使用/usr/spool来代替/var/spool，设置别名的etc/mail取而代之的是/etc,如果你要在sendmail.cf设置RunAsUser许选项，/var/spool/mqueue这个目录需要RunAsUser 用户的权利，ok,这时开始编译Sendmail,执行这条命令

    sendmail -v -bi

    这时，开始初始化alias database. 如果它显示：

    WARNING: writable directory /etc
    WARNING: writable directory /usr/spool/mqueue
    那么这个目录列出了不适当的写特权，应该避免多方面的的安全攻击。

设置Sendmail.cf

    产生出来的YYY.cf一般得要改个地方才能正常的收信。请寻找"Cw"，原来产生的.cf 档，Cw应是：Cwlocalhost请在localhost 之後加上你那一台机器所有可能用来当收信地址的host name 。
    例如我有一台机器叫：ftp.games.net.cn，而且也叫：gopher.games.net.cn，而我希望这一台机器这两个名字都能收信，那我要这么作：
    Cwlocalhost ftp.games.net.cn gopher.games.net.cn

    顺便说一下，Cw之後只能写入本机器的名字，千万不能写入其他机器的名字，否则，甚麽地方都能寄，那被写的就一定不能寄。

    上面其实是简略的说法，如果你对DNS 也熟悉的话，可参考这节来作判断，判断是否须要在Cw之後写入东东。否则请直接跳过这一小节，闭上眼睛把本机器所用的所有名字都写上就是了:)

    1.在一台机器上，如果有多个名字(hostname)，而是用CNAME 建立的，如：
    $ORIGIN games.net.cn
    ftp IN A 140.119.1.2
    gopher IN CNAME ftp

    那麽可以不必在Cw上标明。系统会透过DNS 找到其 Canonical name。

    2.如果一台机器有多个名字，可是，每个名字是用A record 建立的。如：
    $ORIGIN games.net.cn.
    ftp IN A 192.168.25.2
    gopher IN A 192.168.25.2
    这种情况【一定】要记得在Cw後写上你所要收信的名字。如果这个忘了写，会有怎样的问题呢
？
    忘了将会有从外面机器寄信来，没有写上的机器名将却收不到信，机器会抱怨：
    "Local configuration error" 。

    如：我的sendmail.cf中的Cw这行是如下： Cw games.net.cn
    那我将无法使用这个地址：
     username@games.net.cn
    而只能用
     username@ftp.games.net.cn 否则将出现上述错误。

    如果发现了错误，那再加上去也就可以了。

    3.如果一台机器有多interface ，各interface有其本身的名字，且要收信。　　这个情况也要在Cw之後写明所有要收信的hostname。

    ok!一个标准的sendmail.cf文件就设置完了！

设置access

    打开/etc/mail/access，你会看到 （注意一些系统的access文件不再/etc/mail下，如找不到请用whereis查找或检查是否安装正常）

    localhost.localdomain RELAY
    localhost RELAY

    如果您的IP地址是192.168.25.11的话，这样请在最后一行加上192.168.25.11 　　RELAY
    其文件的最后三行应是：

    localhost.localdomain RELAY
    localhost RELAY
    192.168.25.11 RELAY

    加上这句话您就可以用sendmail发送接收mail了！但是如果您想让别人也可以使用sendmail的话，他的IP是202.168.25.22，这样就在在最后一行加入202.168.25.22 　　RELAY
    其文件的最后四行应是：

    localhost.localdomain RELAY
    localhost RELAY
    192.168.25.11 RELAY
    192.168.25.22 RELAY

    我想，您现在一定有个疑问是，如果我想设置50个人用sendmail是不是需要加50个IP啊！？
    嘿嘿，不用啦，是这样，sendmail考虑到多用户的时候，它准许你添入整个C类地址，（B类好像也可以，我没try过！）
    其格式如下：

    localhost.localdomain RELAY
    localhost RELAY
    192.168.25 RELAY

    这样，您就是把192.168.52这整个C都加入的sendmail中，这个C类地址的用户，如果在你的系统里有账号的话，就可以使用sendmail收发信件了！

设置pop3

    如果您需要pop3来接收信件，您需要打开pop3端口，

    vi /etc/inetd.conf 查找到

    把

    vi /etc/services 查找到

    把

    这样，在restart inetd后，pop3 110端口就可以接信了！如果还是不行，请检查是否安装pop3端口！

如何restart sendmail；inetd以及注意事项

    有一点要提醒大家的，要用"kill -9 [pid-of-sendmail]" ，从新启动sendmail 如果用 kill -HUP 是不会发生作用的！ (这是颇多人常遇到的问题，切记！) 在redhat6中用/etc/rc.d/init.d/sendmail restart即可！

    inetd是/etc/rc.d/init.d/inetd restart

sendmail的别名和forward

    (1) 关于直接用IP地址发信

    mail user@[166.111.IP.Address]
    只要用[]将IP地址括起来就行了

    (2) 关于alias

    sendmail在/etc下有两个文件 aliases和aliases.db, 后者是前者用newaliases生成的别名数据库. 你可以手工编辑/etc/aliases, 然后运行newaliases更新数据库(其实newaliases是个到sendmail的 symlink)

    eg: nickname : user@hotmail.com
    alias-name: real-user-account

    则以后mail nickname就可以将信寄到 user@hotmail.com 处而别人寄给 alias-name@your.domain.name 的信就会转给真正的用户real-user-account

    (3) 关于forward

    在你的$HOME目录下面编辑一个.forward文件, 里面写上你要forward的目的e-mail地址或本机的用户名, 就可以自动将信 forward到相应地址

    eg: .forward: user@hotmail.com
    或 other-user-account
    则给此人的e-mail会forward到hotmail或other-user-account处

    (4) 关于vacation

    去找一个vacation包(如RedHat的contrib中有vacation的rpm), 装上后就一个/usr/bin/vacation程序和一个man.
    先运行vacation, 它会让你编辑$HOME/.vacation.msg文件, 就是要发回给对方告诉他你现在不看信的东西啦. 然后编辑$HOME/.forward文件, 写这样一句 \username, "|/usr/bin/vacation username", username 要换回你自己的了然后运行vacation -I建立$HOME/.vacation.db就好了 (看看man更详细)

    (5) 关于sendmail的一些文件

    /var/log/maillog sendmail的log, 分析错误有用
    /var/spool/mail/$USER 进来的信, 每个用户一个文件
    /var/spool/mqueue mail queue, 可以用mailq看队列中待发的信
    (mailq也是 sendmail的symlink了)
    dfxxxxxx 这是信的内容
    qfxxxxxx 这是信的subject和别的信息 (反正每信一个号了, 配对的)
    /etc/sendmail.cf sendmail的配置文件, 改动它可要小心
    /etc/sendmail.cw 假如你的机器有好多alias的话就把名字写在
    这个文件中, 这样写哪个都能收到信

限制邮件的大小

    Modify /etc/sendmail.cf:
    Mlocal, P=/bin/mail, F=lsDFMrmn, S=10, R=20/40,
    Maxsize=1000000,
    A=mail -d $u
    Mprog, P=/usr/local/sendmail/smrsh, F=lsDFMeu, S=10, R=20/40, D=$z:/,
    Maxsize=1000000,
    A=sh -c $u

    This limits incoming mail processed by by smrsh and /bin/mail to 1 million bytes.

    You can do the same with the Mstmp, Mesmtp, and Mrelay statements to limit the
size of outgoing mail as well.
    You can do the same with the Mstmp, Mesmtp, and Mrelay statements to limit the
size of outgoing mail as well.
转自chinaasp

Sendmail 配置

定制mail环境

    在使用mail程序时，系统会检测你的起始目录中的.mailrc文件。你可以根据自己的需要在.mailrc文件中设置不同的环境变量和命令。以下列出了环境变量：
      □
      □alias：设置单个别名或组别名。用法是：alias alias-name address-list
      □set：设置环境变量。用法是：set variable-name或set variable-name=string
    在使用mail时，你还可以在问号（？）提示符下发出以下命令：
      □askcc：在输入消息后提示输入cc:list。默认值是noaskcc
      □asksub：在输入消息前提示输入Subject清单。默认时是提示输入
      □noheader：在启动mail时，不打印可获得的消息的标题信息。默认时是打印标题信息
      □ignore：在输入信息时，忽略中断字符。如果连接的电话或其他通信线路上有“杂音”，这个变量很有用。默认值是noignore
      □metoo：当你的名字在组别名中时，消息通常不发送给你。默认值是nometoo
    以下是一个.mailrc文件的例子：

      set noignore

      set asksub
      set askcc

      alias billy wbracksto
      alias ham <a href="mailto: xiaoniao@linuxaid.com.cn "> xiaoniao@linuxaid.com.cn </a> bbow
      alias me gunter

      alias pirates <a href="mailto: wangtao@linuxaid.com "> wangtao@linuxaid.com </a> bbow
      alias research jones jreynold eackerma
      alias framistan wjones imgood <a href="mailto: linuxcd@linuxaid.net "> linuxcd@linuxaid.net </a> imgood

SMTP协议简介

    SMTP（Simple Mail Transfer Protocol）即简单邮件传输协议，它主要规定基础的电子邮件提交系统怎么传递报文。对于电子邮件系统怎么从用户接受电子邮件，用户接口怎么给用户显示接到的电子邮件，电子邮件如何存储以及电子邮件系统以怎样的频度发送报文等问题却没有作出规定。
    在SMTP中，客户机与服务器之间的通信是由可读文本构成的。开始，客户机通过三次握手与服务器（通常是TCP 25端口）建立一个TCP连接，然后等待服务器发送220 READY FOR MAIL。在收到220报文后，客户机发送HELO命令。之后，电子邮件交互以MAIL命令开始，在MAIL命令中，有一个“FROM：”字段，用于在出错是通知发信人。服务器收到MAIL命令后，发送250 OK作为响应，表示一切正常。MAIL命令成功后，客户方就可以将收信人地址告诉服务器，这是用一连串RCPT命令来实现。服务器接收到每个RCPT命令后，发送250 OK作为响应，表示正确接收；或者发送550 No such user here作为响应，表示没有这个用户。客户方的RCPT命令得到正确响应后，就可以DATA命令发送数据。服务器收到DATA命令后，发送354 Start mail input;end with . 给予响应。其中end with . 规定了用于结束电子邮件报文的五个连续字符，即：回车，换行，圆点，回车，换行，这就是为什么用MAIL发送邮件时，最后只含有一个圆点的行表示结束的缘故。

sendmail简介

    Sendmail是由Eric Allman写的程序，后来经过很多人的贡献，才成为现在的版本。目前几乎所有的Unix/Linux系统都使用sendmail。sendmail的功能非常强大，这就使它的配置文件非常复杂，而且它的规则集非常难看懂。下面就详细介绍一下它的各项配置。

1。 sendmail.cf配置文件

    一般来说不必自己去修改sendmail.cf文件。但是有时你可能想要了解一下sendmail.cf文件的内容。sendmail.cf文件通常由若干个节组成，以下是常见的节名： 节　　名 功　　能
  Local Information 　定义有关个人主机的信息
  General Macros 　定义有关本地网络的宏
  Classes 　定义用于特殊邮件传输程序的主机名群或域名群
  Version Number 　标识sendmail.cf文件的版本号
  Special Macros 　定义由sendmail所用的一些特殊的宏
  Option 　定义sendmail选项
  Message Precedence 　定义sendmail所用的各种消息的优先级值
  Trusted Users 　定义在发送邮件时可忽略发送者地址的用户
  Format of Headers 　定义sendmail插入的邮件首部格式
  Rewriting Rules 　定义用于重写邮件地址的规则
  Mailers 　定义sendmail用来调用邮件传输程序的指令
  Ruleset Zero 　定义一组称为Ruleset Zero的特殊重写规则
  Machine-dependent part 　of Ruleset Zero 　定义与配置相关的Ruleset Zero部分

    sendmail.cf命令从每一行的第一格开始，＃开头的表示注释，第一个字符表示指令，以下是每个指令的意义：
指　　令 说　　　明
Ｖ 　设定组态文件sendmail.cf的版本
Ｍ 　指定一个ＭＴＡ
Ｄ 　定义宏x的值为value
Ｒ 　重写lhs为rhs
Ｓ 　开始一个规则集合
Ｃ 　定义类别宏
Ｆ 　文件定义类别
Ｏ 　设定sendmail.cf选项
Ｈ 　定义标头
Ｐ 　优先权设定
Ｔ 　信任的用户
Ｋ 　具有键值的数据库
Ｅ 　重设环境变量
Ｌ 　扩充负载的支持

    命令D用来定义宏，然后该宏就可以被sendmail.cf文件中的其他配置命令和sendmail程序自身调用。宏的名字可以是任何单个的ASCII字符，以下是sendmail中所有的内部宏： 宏　名 含　　义 在sendmail.cf中定义
a 　RFCs822格式的原始日期
b 　RFCs822格式的当前日期
c 　Hop计数
d 　UNIX格式的日期
e 　SMTP数据项信息
f 　“来自”地址的发送者
g 　相对于接收者的发送者的地址
h 　接收主机
i 　队列标识
j 　节点的正式域名 √
l 　UNIX的行格式 √
n 　用于错误信息中的名字 √
o 　地址中的操作符集合 √
p 　sendmail的PID
q 　默认的发送者地址格式 √
r 　所用的协议
s 　发送者主机名
t 　当前时间的数值表示
u 　接收方用户
v 　sendmail的版本号
w 　该节点的主机名
x 　发送者全名
z 　接收者宿主目录

    命令O给sendmail的选项赋值。赋给选项的值可以是字符，整数，布耳值或时间间隔值。每个选项都在sendmail中进行了定义。以下是sendmail中所有选项的含义和用法： 选项名 用　　法 含　　义
A Afile 　指定别名文件的名字
a aN 　为@:@等待N分钟，然后重建别名文件
B Bc 　定义空代替字符
c c 　将邮件队列排队以等待邮件传输程序
D D 　重建别名数据库
db db 　以后台方式传输
di di 　交互式传输
dq dq 　在下一个队列运行时传输
ee ee 　邮递错误信息，总是返回退出状态0
em em 　邮回错误信息
ep ep 　打印错误信息
eq eq 　仅返回退出状态，无错误信息
ew ew 　写回退出状态
f f 　保持UNIX风格的From行
g gn 　设置邮件传输程序默认的GroupID为n
H Hfile 　定义SMTP帮助文件的名字
I I 　使用BIND名字服务器来解析所用的名字
i i 　忽略入局信息中的点
L Ln 　设置日志级别为n
M Mxval 　设置宏x的值为val
m m 　同时发往自身
N Nnet 　定义宿主网络名
o o 　接受旧格式首部
Q Q 　定义队列目录名
q qn 　定义用于决定何时排队任务的因子n
r rt 　设置用于超时的内部时间间隔t
S Sfile 　定义统计日志文件名
s s 　在试图传输前总是创建队列文件
T Tt 　设置排队超时为t
u un 　设置邮件传输程序默认的UserID为n
v v 　以冗余方式运行
W Wpass 　定义用于远程调试的口令
X X1 　如果平均负载超过１则拒绝SMTP连接
x x1 　如果平均负载超过１则排队邮件
Y Y 　在不同的进程中传输每个排队邮件
y yn 　每个接收者作业时间优先级差为n
Z Zn 　每次运行时减少n个作业优先级
z zn 　同前缀一起决定邮件优先级

2。 sendmail的地址重写规则

    地址重写是sendmail的核心部分，它的作用是分析来自邮件程序的电子邮件的地址，并将它们重写成邮件传输程序所需要的格式。
2.1 规则集
    规则集是一组可以由数字引用的相关重写规则。Sn命令标志一个规则集的开始，其中n是这个规则集的编号，其范围从0～29。其中0～4号规则集是被sendmail直接调用的，它们的说明如下： 编　号 说　　明
0 　在规则集3之后调用，它将生成一个三元组：<传输程序，接收方主机，接　收用户名>
1 　用于消息中所有发送者地址
2 　用于消息中所有接收者地址
3 　最大和最复杂的规则集，也是用于地址的第一个规则集，将地址转化成正　规形式，即： <a href="mailto: local-part@host.domain "> local-part@host.domain </a>
4 　用于消息中所有地址并将内部地址转换成外部地址形式

2.2 重写规则
    地址重写规则由命令R定义，其格式如下：
     Rlhs　　　rhs　　　comment
    lhs，rsh和comment这三个字段之间用tab隔开。重写规则将输入地址与lhs进行匹配，如果成功，就按照rhs进行重写。重写后的结果再次与lhs匹配，如果成功，就再次按照rhs进行重写，直到结果不再与rhs匹配。

3。 使用M4

    如果一行一行输入整个sendmail.cf文件不仅麻烦也容易出错。最简单的方法是用M4处理程序自动产生一个sendmail.cf文件。M4是一种宏前置处理器，用来把组态文件转换成sendmail.cf文件。它的用法很简单，在/etc下面找到sendmail.mc文件，修改后使用：
        $m4 sendmail.mc>sendmail.cf
    将会生成一个sendmail.cf文件。并自动覆盖原来的sendmail.cf文件。以下是sendmail.mc文件中各个指令的意义：
  divert(-1) 　管理输出字符传
  dnl 　在define后通常会自动产生空格，可以用dnl来删除
  include 　包含一个文件
  define arg 1 arg 2 　定义宏argument1设为值argument2
  undifine arg 1 　取消arg1的定义
  OSTYPE('Linux') 　定义操作系统的类型
  FEATURE 　功能选项，对应到/usr/lib/sendmail-cf/feature里面的　文件名称所定义者
  MAILER 　定义所有必要的邮件递送代理程序，MTA
  MASQUERADE_AS 　用来处理多主机名称问题

4 sendmail别名

    别名是sendmail最重要的功能之一。它在aliases中定义。aliases文件的位置由sendmail.cf中的选项A指定，一般位于/etc目录中。aliases是一个文本文件，其中每一行的格式如下：
      alias:recipeint[,recipeint,...]

    其中alias为邮件中地址的名字，recipient为邮件目的地址的名字。邮件目的地址名可以有很多，每个之间用逗号符隔开。下面介绍别名的几种主要用法：
    ◆ 保护登陆帐号
       许多网络黑客进攻网络计算机的第一步是获取目标机上合法用户的帐号，而电子邮件帐号一般和登陆帐号相同，这就使黑客有机可乘。但是可以用别名来保护合法用户的帐号。如一位合法用户的登陆帐号为xiaoniao，而他的电子邮件帐号可以是aaabbb。只要在别名文件中加入“aaabbb:xiaoniao”就可以达到这一目的。
    ◆ 电子邮件转发
       如果想要将发给xiaoniao用户的电子邮件自动转发给root用户，只需在别名文件中加入“xiaoniao:root”。又如用户xiaoniao离开这个单位。从安全角度上讲应该将他的用户帐号删除。但是由于他不可能马上将新的电子邮件帐号通知所有人，所以希望将他原来的电子邮件帐号保留一段时间。这只要在别名文件中加入“xiaoniao:新的电子邮件地址”。
    ◆ 邮件列表的实现
       别名最重要的功能就是实现邮件列表。通过它可以实现填写一个接收者地址而将信发给许多人。例如在主机上设置一个邮件列表xn_group，包括xiaoniao，lyong，twang 和lwang。只需在别名文件中加入：
       xn_group:xiaoniao,lyong,twang,lwang
       owner_xn_group:xiaoniao
    当接收者是xn_group时，信会自动发给xiaoniao，lyong，twang和lwang。当发送邮件给xn_group是如果出错，将把错误信息发给xiaoniao。

5　如何处理垃圾邮件

5.1 什么是垃圾邮件
    电子邮件是当今最先进，最快捷的通讯工具之一，随着她的广泛使用麻烦也随之而来。有时候你会莫名其妙的收到一些来路不明的邮件，它们中最多的就是那些令人生厌的广告。也许有一天，你打开电子邮箱检查邮件时，会看到有成千封E－mail，那么恭喜你,你被炸了。只要你上网，这些事就是无法避免的。垃圾邮件的泛滥，占用了网虫本来就不大的信箱空间，使得真正有用的邮件要么因为信箱已满而进不来，要么淹没在一大堆垃圾邮件中。这使得垃圾邮件被选为1998年国际互联网的十大新闻之一。

5.2 减少垃圾邮件的方法
    ◆ 大多数都使用一种叫"bot"的应用程序来搜索Internet上的各个网址、聊天室、网上讨论区、新闻组、公共讨论区以及其他任何能够充实他们业已庞大的数据库的地方。你可以尽量少在这些地方公布你的电子邮件地址。
    ◆ 如果你需要在某初留下你的电子邮件地址，使用特殊的书写E－mail地址的方法来对抗E－mail地址自动收集机。很多E－mail地址收集机完全依靠关键字母“@"来收集信箱，假设你的信箱地址为 <a href="mailto: xiaoniao@linuxaid.com.cn "> xiaoniao@linuxaid.com.cn </a> ，当你需要在某处留下你的E－mail地址时，如果将你的信箱地址写成xiaoniao AT linuxaid DOT com DOT cn，自动机就识别不出这是个E－mail地址，而稍具常识的网虫却能看懂这个信箱地址。
    ◆ 如果是Unix主机上的sendmail邮件服务器可以通过以下方法来对抗垃圾邮件：
       只允许指定的主机和域转发，首先定义一个文本文件sendmail.cR，文件中的每一行是一台主机的完整域名或一个域。按照以下文件修改sendmail.cf，则sendmail只对发送地址或目的地址是本机或sendmail中定义的主机或域进行中转。
  FR-o/etc/sendmail.cR

  Scheck_rcpt

  R<$+ @$ =w>　　　　$@ OK
  R<$+ @$ =R>　　　　$@ OK
  R<$+ @$*$ =R>　　　$@ OK

  R$*　　　　　$: $(dequote""$&{client_name}$)
  R$=w　　　　　　　 $@ OK
  R$=R　　 　 　　　 $@ OK
  R$* $=R 　 　 　　 $@ OK
  R$=@　　 　 　　　 $@ OK

  R$*　　　　　$

5.3 清除电子邮件炸弹的方法
    如果哪天你的电子邮箱被炸了，可以用如下方法解救：
    ◆ 打电话向你上网的ISP服务商求助，他们就会帮你清除E－mail Bomb。
    ◆ 用软件清除。现在有很多软件可以清楚垃圾邮件，如Spam Exterminator、SpammerSlammer、SpamKiller、Spam Attack Pro、SpamEater Pro、Bounce Spam Mail

Sendmail邮件系统使用初步

一、为网站建立电子邮件帐号，使发往该站点的电子邮件可以收到；

1.1 用netconf命令设置基本邮件系统：
首先保证配置DNS服务时已经将邮件服务器指定（有MX的完整记录），否则退回修改DNS设置，否则会找不到某一个域的邮件服务器及其优先级，该域的信件就无法送达，当然就更谈不到在该域上找相应主机和用户账号。
之后，进入netconf 工具配置服务参数，选择 Mail delivery system (sendmail)，进入后在选择Configure basic information选项，按照下面内容配置：
Present your system as yourdomain.com
[x] Accept email for shung.com
Mail server youmailhost.yourdomain.com
Mail gateway
Mail gateway protocol smtp
------------------------Fatures----------------------------
[x] match full user name
[X] Enable relay control（spammers）
Messages size limit （o) No limit __________
[ ] Don't try to deliver immediatly
Mrocess queue every (minutes) 1
[ ] Use special shell smrsh
Maximum recipients per msg. （o) Defaults __________
------------------------DNS Fatures-------------------------
[x] wait for DNS
[ ] don't use DNS
..... 以下内容略，用默认值即可。

1.2 手工修改/etc/sendmail.cf文件内容，保证配置文件和如下内容相符（Sendmail-8.9.3版本）；

V8/Berkeley

Cw yourdomain.com （否则收发邮件时，邮件地址需要带上主机名，这样实际使用上并不需要）
Cw localhost yourmailhost.yourdomain.com

CV cicoo.com
CV cicro.com
CV hisell.com
CV timic.com （有多少，全部列出）

DMyourdomain.com （否则收发邮件时，邮件地址需要带上主机名，这样实际使用上并不需要）

DSyourmailhost.yourdomain.com （可以空着，需要时添加，用于服务器群集）

DNsmtp

DHyourmailhost.yourdomain.com （可以空着，需要时添加，用于服务器群集）

CLroot

CEroot

Troot
Tdaemon
Tuucp

CD

否则，会因为邮件中继的原因，yourdomain.com域以外的域或处于和服务器不同网段的用户机器无法正常发送和接受正常邮件（用微软IE5.0 附带的OUTLOOK5作为客户端软件，或Foxmail系列）
重新启动服务，使配置文件生效：
kill sendmail ：

Restart sendmail:

（记着开放pop和smtp端口，否则一切白费劲，改/etc/inetd.conf文件）
如果需要使用虚拟主机邮件系统，属于高级使用，大家可以和我交流，我的方法是用用户别名+用户邮件路由的方法。

1.3 使用fetchmail管理多邮件帐户:
    尽管使用pine能非常方便的管理多个POP3或IMAP邮箱，但是如果邮箱主机与当前Linux系统的网络连接很慢，使用pine来阅读这些邮箱中的邮件就非常迟缓。此时更好的办法是先在后台将邮件取到回本地邮箱中，然后使用pine或其他邮件处理程序进行处理。
    fetchmail就是一个非常方便的从远程邮件主机下载邮件的应用软件，它支持pop3、imap，以及对pop3的一些扩展协议。当安装好fetchmail之后，使用者可以直接启动fetchmail，来取得邮件的方法为：
$ fetchmail -p pop3 -u wangb email.online.ha.cn
password for wangb@email.online.ha.cn :
    在输入正确的口令之后，fetchmail将使用pop3协议访问主机email.online.ha.cn，并取回用户wangb的电子邮件，取回的电子邮件将发送到本地邮箱中。也可以用更复杂的方式在后台运行 fetchmail，则需要设置个人目录下的.fetchmailrc文件。
$ cat ~/.fetchmailrc
poll email-wangb via email.online.ha.cn
protocol pop3
authenticate password
username wb here is wangb there
password "1111"
smtphost localhost
pass8bits
stripcr
fetchall
$ chmod 700 ~/.fetchmailrc
    设置文件中第一行poll email-wangb via email.online.ha.cn中设置了要下载邮件的邮件服务器为email.online.ha.cn，其中email-wangb为对应这一个帐号的标签名字，用于区分多个不同的邮箱。然后指定使用的协议为pop3，认证方式为标准的Unix口令认证，然后，定义了远端主机上的邮件帐户名为wangb（用there表示远端主机设置），邮件下载到本地用户wb的邮箱中（使用here 指明本地主机设置）。
    smtphost定义了fetchmail用来转发邮件时使用的smtp主机，passsword定义了远程邮件服务器中帐户的口令，在口令中使用了数字或特殊字符时，就需要使用双引号将口令括起来。pass8bits 允许下载邮件中存在8位字符，stripcr用于过滤额外回车字符，由于DOS和Unix在文本定义上的不同，这一项用于兼容一些不识别这个差异之处的Windows系统的邮件服务器，fetchall表示取回全部邮件，否则就只取回最新的邮件。
    此外，这个文件因为包括了远端服务器的口令，因此必须具备属性700，以避免其他用户能读取这个文件，否则fetchmail不会运行。
    这样，就可以不使用任何命令行参数，直接在后台运行fetchmail了。每个用户可以使用cron来运行自己的fetchmail命令，来管理自己的邮件，而拨号用户可以在拨号后，使用ppp.linkup启动fetchmail ，取回自己的邮件。

1.4 使用Procmail设置邮件过滤:
    由于Internet的使用者不但使用电子邮件和朋友、同事联系，而且还通过maillist与Internet 上的其他使用者讨论共同感兴趣的话题，用户收到的电子邮件越来越多，并且还会受到广告、宣传品等垃圾邮件的骚扰。使用Promail、maildrop等邮件过滤程序就能帮助使用者阻挡这些广告和宣传品，并帮助管理用户接收到的邮件。Procmail就是一个用于过滤用户接收到的电子邮件，并能对其自动分类、处理的一个应用软件。对于每天都会收到大量电子邮件的Internet使用者，这是一个非常有用的工具。
    为了使用Procmail，必须在用户接收到Email时，启动Procmail进行处理。这个任务可以使用两种不同的方式来完成，一个是将Procmail配置为系统的邮件分发代理（Mail Deliery Agent），系统的邮件服务器使用porcmail代替其本身原有的邮件分发功能，来分发用户的邮件。这种方式需要由系统管理员根据邮件服务器的不同，而进行不同的设置。
    另一种方法是使用个人目录下的.forward文件，系统邮件服务器在给某个用户分发邮件的时候，如果发现他的个人目录中存在.forward文件，那么就会按照这个文件中的内容来进行处理。因此就可以在.forward文件中启动procmail处理用户接收到的邮件，与更改系统MDA的设置方式相比，这种方式更为灵活，并且可以由每个用户来决定是否使用这个过滤处理能力。
    .forward文件可以按照需要设置三种不同的处理方式：定义存储邮件的邮箱文件名、进行转发的目的地址或者对电子邮件进行处理的外部应用程序，显然启动Procmail是应使用第三种方法。
    .forward文件应该属于这个用户（或root），并且其权限设置应该为不能被其他或同组用户可写。
$ cat ~/.forward
"|IFS=' '&&exec /usr/local/bin/procmail -f-||exit 75 wb"
    这个.forward的例子里，使用"|"字符设置括号内的参数为一个执行命令，这样 sendmail就能启动一个shell执行设置的命令，并使用管道的方式读取sendail的输出。执行命令中首先定义了IFS环境变量（用于分隔不同的域），然后执行procmail，如果procmail执行失败就执行 exit 75 wb告诉sendmail，邮件分发失败，需要更改wb为使用者自己的登录名。
    procmail使用用户个人目录下的.procmailrc文件，来设置对收到的Email进行处理的过滤规则。最简单的.procmailrc文件为：
:0c:
* ^FROM.*@Linux.org
$HOME/mail.backup
    第一行首先使用冒号开始定义一个过滤规则，紧随其后的应该是一个数字，这个数字规定了这个规则占用的配置行数，一般使用0表示没有限制配置行，此后的c表示复制（copy），表示下面的规则只是用于处理邮件的副本，而邮件本身仍然会被其他的过滤处理规则处理。这一行最后的冒号，用于表示在处理过程中进行加锁，防止同另一个procmail进程处理同一个文件时发生冲突，通常这个机制在存储邮件文件时非常有帮助。
    第二行就开始了一个过滤规则的定义，过滤规则使用*字符开头。一个规则中使用模式匹配来匹配电子邮件信头或内容中的特定行。上面例子里的这个规则匹配所有来自于Linux.org的电子邮件。在第三行定义了对符合上面规则的邮件的处理方法，由于给出了一个文件名mail.backup，因此将所有来自于Linux.org的电子邮件添加到mail.backup文件中保存。如果使用!开头定义规则处理办法，表示进行转发处理，!后面就为进行转发的电子邮件的地址，或者以|开头，表示启动后面的命令进行邮件处理。
    procmail不区分大小写，它使用Unix最常用的模式匹配方式进行匹配特定的邮件。因此使用这些匹配模式和procmail规则，可以定义一个更复杂的.procmailrc：
PATH=$HOME/bin: /usr/bin: /usr/ucb: /bin: /usr/local/bin:.
SHELL=/bin/sh
MAILDIR=$HOME/mail
DEFAULT=$MAILDIR/mailbox
LOGFILE=/dev/null
SENDMAIL=/usr/lib/sendmail
:0:
* ^From.*badguy
/dev/null/
:0c:
* ^(From|Cc|To).*Linux.org
| gzip >> freebsdmail.gz
:0:
* ^From.*@hotmail.com
* ^Subject:.*(joke|funny)
{
:0 c
! friend1@hotmail.com friend2@usa.net
:0
joke
}

:0
* ^Subject:.*order
* !^FROM_DAEMON
* !^X-Loop: marketing@company.com
{
:0 h c
| (formail -r -A"X-Loop: marketing@company.com " ;
cat /market/acknowlegement.txt ) | $SENDMAIL -t
:0 c
! market2@company.com
:0
market
}
  这个配置文件的第一部分中设置了几个环境变量，用于设置procmail的运行环境，其中将 MAILDIR设置为~/mail，与pine使用的目录相同，因此这将使pine能直接读取procmail处理过的邮件。
    第二部分中为邮件定义了三个不同的过滤规则及相应的处理操作，第一个规则将来自badguy 的邮件滤掉（输出到/dev/null）；第二个规则将与Linux.org的通信使用gzip保存到freebsdmail.gz 中，用于保存相应maillist的邮件；第三个规则将某个使用hotmail帐号的朋友，并使用joke或funny标题给自己发送笑话的邮件同时转给其他几个朋友，并同时保存在joke文件夹中；最后一个规则是设置了一个自动回复邮件系统，对于使用order做标题，并且没有FROM_DAEMON行（自动邮件回复程序使用FROM_DAEMON 作标记，通常不需要回复这些的邮件，否则会造成回复循环），并且没有包括X-Loop行的邮件进行处理：
  首先将X-Loop行添加到邮件中（使用formail将它们添加到mail的信封上），以免造成对同一个邮件的循环处理，然后将文件/market/acknowlegement.txt发回给发送者；并以及转发邮件，在market中保存邮件。
    根据这些规则，使用Procmail就能完整的处理各种邮件，减轻电子邮件不断增多而造成的困扰。

二、添加POP账号用户（用户没有login和telnet权限）：

1、userconf命令添加用户：
使用很简单，用root登录，使用userconf命令，找相应选项，添加POP用户。为了管理方便，建议在/home目录下建立popusers目录，以后的pop用户目录全部放在下面。不多罗嗦。
2、添加虚拟主机域：
用root登录，使用mailconf命令，找相应选项，添加虚拟主机域，然后在设置pop账号时，在虚拟主机域pop用户设置中就会出现虚拟主机域的列表，然后选择相应的域就可以添加pop用户了。

中小型企业的Sendmail邮件服务器应用实例

简介:本文旨在介绍如何利用Linux服务器上的sendmail构建中小型企业的邮件服务器。们假定该企业采用专线接入Internet,有两台Linux服务器（Redhat 6.1 ） 一台作为防火墙直接接入Chinanet,是通向Internet的唯一出入口，同时也作为DNS/SMTP 服务器，且申请了域名domain.com,由该防火墙服务器（DNS服务器）对域domain.com进行解析。另一台邮件服务器是在内部网段运行，完全与外部世界无关。作为内部局域网上用户的收/发邮件服务器。

地址：假定防火墙Linux服务器的永久外部地址为a.b.c.d(eth0),内部网卡地址192.168.11.5(eth1),机器名为firewall.domain.com, 内部的邮件服务器地址为192.168.11.1，机器名为mail.domain.com , 且注册域时填写的主机名为dns.domain.com(a.b.c.d) .

思路：先配置DNS服务器，用来解析@domain.com的域名，并指明MX记录到内部邮件主机mail.domain.com. 把这台防火墙仅作为mail relay主机，任何从外部世界发往@domain.com域的邮件均由它处理且relay到内部邮件主机，仅接受@domain.com后缀的邮件进入，这样阻止了spammer发送垃圾邮件。
    在内部邮件服务器上，配置Sendmail的DS部分为firewall.domain.com，任何发往非内部员工的邮件直接送往firewall.domain.com，且设置domain.com为本地域，任何发往@domain.com域的邮件被内部别名处理并送往内部各用户的邮件缓冲池中。

旅行用户的考虑：
    若公司员工出差在外需从公司的服务器接收邮件，一种方法是直接拨当地ISP，然后设置接收邮件服务器为mail.domain.com，但要求mail.domain.com在外地被解析成防火墙的外部永久地址，这样再在防火墙上设置plug-gw代理，代理任何到防火墙外部地址的110端口的请求到内部192.168.11.1的110端口。
    另一种方法，也可以再建一服务器为Linux拨入服务器，直接拨到公司来接收邮件。

重点：Sendmail的各项配置及相关设置

一：防火墙上的Sendmail配置：

    我们采用Redhat Linux 6.1 加 Sendmail 8.9.3作为操作环境：

    安装操作系统和防火墙的配置略，建议采用3c905b或者Intel pro100 的网卡，先配置DNS。设置/etc/named.conf象这样：
============
zone "."{
type hint;
file "named.ca";
};
zone "0.0.127.in-addr.arpa"{
notify no;
type master;
file "127.0.0";
};
zone "11.168.192.in-addr.arpa"{
notify no;
type master;
file "192.168.11";
};
zone "domain.com" {
notify no;
type master;
file "domain.com";
};

文件 192.168.11象下面这样：
@ IN SOA dns.domain.com. root.mail.domain.com. (
1999092201 86400 3600 3600000 86400 )
NS dns.domain.com.
1 PTR mail.domain.com.
5 PTR firewall.domain.com.

文件 domain.com象下面这样：
@ IN SOA dns.domain.com. root.mail.domain.com. (
1999120401 86400 3600 3600000 86400 )
NS dns.domain.com.
A a.b.c.d
MX 10 mail.domain.com.
firewall A a.b.c.d
mail A a.b.c.d
dns A a.b.c.d

加下面的行到/etc/hosts
192.168.11.1 mail.domain.com mail
192.168.11.5 firewall.domain.com firewall
============
下面配置Sendmail,首先要先创建一个用来生成/etc/sendmail.cf的sendmail.mc文件，在Redhat 安装的过程中有一个默认地redhat.mc在/usr/lib/sendmail-cf/cf目录下。
我们修改为如下：
===========
divert(-1)
dnl This is the macro config file used to generate the /etc/sendmail.cf
dnl file. If you modify thei file you will have to regenerate the
dnl /etc/sendmail.cf by running this macro config through the m4
dnl preprocessor:
dnl
dnl m4 /etc/sendmail.mc > /etc/sendmail.cf
dnl
dnl You will need to have the sendmail-cf package installed for this to
dnl work.
include(`../m4/cf.m4')
define(`confDEF_USER_ID',``8:12'')
OSTYPE(`linux')
undefine(`UUCP_RELAY')
undefine(`BITNET_RELAY')
define(`confAUTO_REBUILD')
define(`confTO_CONNECT', `1m')
define(`confTRY_NULL_MX_LIST',true)
define(`confDONT_PROBE_INTERFACES',true)
define(`PROCMAIL_MAILER_PATH',`/usr/bin/procmail')
define(`ALIAS_FILE',`/etc/mail/aliases')
FEATURE(`smrsh',`/usr/sbin/smrsh')
FEATURE(`mailertable',`hash -o /etc/mail/mailertable')
FEATURE(`virtusertable',`hash -o /etc/mail/virtusertable')
FEATURE(`domaintable',`hash -o /etc/mail/domaintable')
FEATURE(redirect)
FEATURE(always_add_domain)
FEATURE(use_cw_file)
FEATURE(local_procmail)
MAILER(procmail)
MAILER(smtp)
FEATURE(`access_db')
FEATURE(`blacklist_recipients')
dnl We strongly recommend to comment this one out if you want to protect
dnl yourself from spam. However, the laptop and users on computers that do
dnl not hav 24x7 DNS do need this.
dnl FEATURE(`accept_unresolvable_domains')
dnl FEATURE(`relay_based_on_MX')
=============
然后用m4 redhat.mc > sendmail.cf生成sendmail.cf放到/etc目录下。且做如下操作：

1. 更改/etc/sendmail.cf中Fw定义为Fw/etc/mail/sendmail.cw
并创建一个空文件sendmail.cw （#touch /etc/mail/sendmail.cw）

2. 更改/etc/mail/mailertable象下面这样：
domain.com relay:[192.168.11.1]
并运行makemap hash /etc/mail/mailertable.db < /etc/mail/mailertable

3. 加下面一行到/etc/mail/access象下面这样：
domain.com relay
并运行makemap hash /etc/mail/access.db < /etc/mail/access
注：你不需要设置/etc/mail/relay-domains,因为你仅仅接受送往@domain.com域的邮件，通过access就可做到这一点，在收到@domain.com后缀的邮件后立即转送到内部主机192.168.11.1

4. 加下面一行到/etc/mail/relay-domains (如无，用vi创建一个）
192.168.11.1
注：仅允许内部网段上的邮件主机mail.domain.com(192.168.11.1)向它发信邮件，不允许内部网段上的用户设置SMTP服务器为firewall.domain.com(192.168.11.5)

二。内部邮件主机mail.domain.com的配置：

    仍然用下面生成的sendmail.cf文件，并做如下设置更改。

1. /etc/hosts
192.168.11.5 firewall.domain.com firewall
192.168.11.1 mail.domain.com mail

2. /etc/resolv.conf
search domain.com
nameserver 192.168.11.5

3. 加下面的行到/etc/mail/relay-domains(如无此文件，则用vi创建一个）
192.168.11
注：允许内部网段上的用户向它发信，且允许防火墙机器向它转送从外面进来的邮件。

4. 加下面的行到/etc/mail/sendmail.cw
domain.com
注：当收到一个从内部网段上发到@domain.com的邮件时被认为是本地主机/域，然后检查/etc/mail/aliases 文件查找别名

5. 设置别名文件/etc/mail/aliases
假设本地网段上有三个用户，邮件帐号分别为jephe,jack,tony.
则设置别名文件如下：
jephe: jephe@mail.domain.com
jack: jack@mail.domain.com
tony: tony@mail.domain.com
注：这样的话，你能在局域网上维护一个共同的地址薄供内部用户每个人采用.地址薄中就可以用jephe@domain.com,jack@domain.com, tony@domain.com。 对外公开的地址也是它们。

6. 设置/etc/sendmail.cf中的DS部分为
DSfirewall.domain.com
注：所有非@domain.com域的邮件都转送至防火墙处理，根据DNS MX查找后直接送到各个地方。

7. 设置/etc/sendmail.cf中的DM部分为DMdomain.com

其他功能：
8. 设置/etc/mail/access文件阻止从某些域/地址发来的垃圾邮件。

9. 设置/etc/mail/domaintable进行某些域转换。如果你的公司域名容易被打错，如某用户常容易错把jephe@domain.com打成jephe@doman.com， 则你可以把doman.com放入domaintable中你可以放下面的行到/etc/mail/domaintable,同样，运行
makemap hash /etc/mail/domaintable.db < /etc/mail/domaintable
-----
doman.com domain.com
-----
    你也可以放doman.com到/etc/mail/sendmail.cw中实现同样的目的这样不管是发到jephe@domain.com或是jephe@doman.com都一样。

三. windows 客户配置

在局域网上的windows客户机都设置发送/接收邮件服务器为mail.domain.com,
DNS服务器为192.168.11.5并使用一个共同的由网管维护的地址薄，其中含有公司
内所有用户的邮件地址。你可以在内部的邮件服务器上设置DHCP服务器自动配置
每台windows客户机的设置。

关于sendmail.cf的简单解释

以下信息主要摘自杜毅编著的《UNIX系统组网技术》，由电子工业出版社出版。这本书主要针对SCO Unix,不过对于Unix世界的初学者它值得一读，既然引用了人家的东西就要为它做的广告:-) 但愿没人找我麻烦。

在整理的过程中，我发现书上所写与TurboLinux带的sendmail略有不同和缺漏，未经作者同意自行加上，文字也不是完全照搬。
sendmail.cf的详细信息，请自己去/usr/doc/sendmail/下找op.ps,其中第5章把下列内容讲得很详细。

关于sendmail.cf的简单解释：
配置文件sendmail.cf中的信息仍旧是以行为单位。如果行首的第一个字符为“#”，则表示该行为注释，如果第一个字符为空格则表示该行为上一行的延续。此外，行首的第一个字符均为命令，但是命令同变量或值之间没有间隔。这种格式便于sendmail进行分析，但令我们很难阅读。下面我们将介绍sendmail.cf配置文件中的命令：

1 D,定义宏

命令D定义宏并为其赋值。当宏被定义之后，它就负责提供提供其存储的值给sendmail.cf文件中其他的命令使用或者直接提供给sendmail使用。宏的名字可以是任何单字符，小写的用于sendmail内部宏，用户创建的宏只能使用大写字母作为名字。一些sendmail的内部宏也在sendmail.cf文件里定义。例如下面两行定义了宏D和内部宏n：
DDcs.mit.edu
DnMAILER-DEAMON
则宏D的值为cs.mit.edu,宏n的值为MAILER-DEAMON.要使用宏的值时，必须在宏的名字前面加上符号"$",以这种形式来引用它的值。例如： #my official host name Dj$w.$D
如果宏w的值为主机名moon,此时宏j的值就为moon.cs.mit.edu,这便是本主机的全称名(FQDN).

2 C与F,定义类

命令C与F都是用来定义sendmail的类。所谓类，实际上就是由处理方式相同的多个变量组成的数组。与宏一样，类也使用单字符名字，大小写规则也一样。类可以定义在一行之中，也可以分多行定义，例如，下面的示范为内部类w赋值为系统的主机名，而系统可以有多个名字：
Cwmoon sun
Cwearth
Cwlocalhost
命令F是从文件中获取类的值，例如，可以把moon,sun,earth保存在sendmail.cw之中，然后用F命令便可以实现同上述命令完全相同的结果：
Fw/etc/sendmail.cw

对类的引用与宏的引用完全一样，事实上宏就是一种类。两者的唯一区别在于，宏只能有一个唯一的值，而类可以有多个值，当然也可以只有一个值。

3 O,设置选项

命令O是为sendmail的选项赋值，赋给选项的值可以是字符串、整数或布尔值，所有的选项值都是直接由sendmail来使用。需要注意的是，这里所说的选项与sendmail使用的命令行参数不一样。通常情况下，不需要修改这些选项。

4 T,定义可信任的用户

命令T用来定义一组用户列表，这组用户可以使用sendmail带-f参数来修改用户发出的邮件地址。一般情况下，包含root,daemon和uucp。管理员最好不要随意添加其他的用户，否则这种权限在某些用户手中可能会对系统安全构成威胁。可信任的用户可以在一行或多行中定义，但是被定义的用户必须是/etc/passwd中的合法用户。缺省是：

Troot
Tdaemon
Tuucp

5 P,设置优先级

sendmail使用命令P定义不同的优先级来处理进入出局缓冲区的电子邮件。命令P定义的值越高，则优先级也越高，缺省的优先级为0。负优先级的电子邮件是不产生错误信息的，因此在批量发送邮件是应该定义较底的优先级。常用的优先级为：
Pfirst-class=0
Pspecial-delivery=100
Plist=30
Pbulk=-60
Pjunk=-100
如果用户在发送邮件是需要指定优先级，则需要在邮件的首部中添加Precedence,例如：
Precedence:bulk

6 K,Key File Declaration

特殊的映射可以定义成：
Kmapname mapclass arguments
mapname是可重写规则中使用这个映射的句柄，mapclass是映射类型的名字，arguments的解释依赖与映射类型，通常是包含映射的文件名。

7 V,Configuration Version Level

提供与老版本配置文件的兼容性能。

8 M,定义邮件传输程序

命令M定义邮件传输程序(mailer)的规格/详细参数，其形式如下：
Mname, {field=value}
sendmail并不是直接发送各种各样的电子邮件，它首先将要发送的邮件分类，然后交给相应的mailer来发送，它本身只发送基于SMTP/TCP/IP的邮件。其中[IPC]表示使用sendmail通过smtp来传送邮件。关于IPC mailer,在sendmail的文档里有一段有趣的特殊
解释：当规则集0解析到IPC mailer时会处理一些特殊的过程。比如直接用IP地址发送邮件可以用[128.32.149.78]的形式，若用[ucbvax.berkeley.edu]将会怎么样呢？它会被作为字符串传递，用这样的方法用户可以构造一个特殊的邮件地址，使自己的邮件按指定的路线发送，而通常用户是不关心也不知道自己的邮件的发送路线的。

9 H,定义邮件的首部格式

命令H定义sendmail插进电子邮件首部的行的格式。

10 R,定义重写规则
重写规则是sendmail配置文件的核心内容，每一重写规则由命令R定义，其形式如下：
Rpattern transformation comment
命令R中的字段由制表符进行分隔，系统处理时忽略注释字段(comment),模式字段(pattern)
与改写字段(transformation)为该命令的核心。
重写规则将输入地址与模式进行匹配，如果匹配，则将该地址用规则中改写字段的规则重写为新的格式。每一规则可以多次处理同一地址，这是因为地址在重写之后，仍要再次同该模式进行匹配，如果仍旧匹配则再次改写，直到不再匹配为止(使用"$:"可以避免无限循环)。
在Linux中格式的表达应该是：
Rlhs rhs comment
lhs--left hand side rhs--right hand side

11 S,设置重写规则集

规则集是一组可以用数字来引用的相关重写规则。命令S是规则集的开始并赋予它一个数字以便由邮件传输程序来调用。规则集可以被看作用来处理电子邮件地址的子程序或函数。具有特殊功能并可由sendmail直接调用的规则集有5个：
规则集3：为最大最复杂的规则集，也是用于地址的第一个规则集。它将地址转化为正规形式如：user@host.domain。
规则集0：应用于传输邮件的地址。必须在规则集3之后使用，并仅用于实际邮件传输中接收者的地址。它可以将地址解析成(mailer,host,user)的形式，由邮件传输者、接收方主机和接收用户的名字组成。

规则集1：应用于消息中所有发送者地址。
规则集2：应用于消息中所有接收者地址。
规则集4：应用于消息中所有地址并将内部地址格式转化为外部地址格式。
下图说明了消息和地址通过这些规则集的流程(原书有误)：

+---+
-->+ 0 +---> resolved address
/ +---+
/
/ +---+ +---+
/ -->+ 1 +-->+ S +---
/ / +---+ +---+ \
+---+ / +---+ / \ +---+
addr --->+ 3 +---->+ D +--- --->| 4 +---> msg
+---+ +---+ \ / +---+
\ +---+ +---+ /
-->+ 2 +-->+ R +---
+---+ +---+
图中，D--sender domain addition
S--mailer-specific sender rewriting
R--mailer-specific recipient rewriting


Sendmail
linux邮件系统入门
首先简单的介绍一下邮件系统，主要由两部分组成：smtp协议(简单邮件传输协议) 和pop3(邮局协议version 3)，smtp用于邮件在网络中的传递(mailer),而pop处理客户端邮件的接收。由于pop3的局限，将来肯定要被imap代替，imap有较好的目录服务能力，可以在下载之前看到邮件的主要信息如来源、标题等，还可以远程删除邮件等，但目前ISP还不会轻易用它来替换pop.注意不要与IAP的POP搞混淆了，那是当前接入点的意思(Point Of Present)。学得越多越糊涂:-(最早在Linux传递邮件用的是smtp服务，在/etc/inetd.conf里可以看到这样一行：

现在基本都用sendmail这样功能强大的deamon程序来做(nntp也是如此)。所以sendmail只是邮件传递者(mailer),它把这个主机上的邮件发送到其他地方，注意到配置DNS时有一项MX(Mail eXchang,邮件网关)，使用sendmail在你的网内要有一个DNS服务器。而处理主机上远程客户的邮件服务则要有pop服务，查看inetd.conf有这么几项：

pop-2 stream tcp nowait root /usr/sbin/tcpd ipop2d
pop-3 stream tcp nowait root /usr/sbin/tcpd ipop3d
imap stream tcp nowait root /usr/sbin/tcpd imap

再查看/etc/service就知道它们对应的端口号，用telnet host-name port试试能看到什么？Linux这样的东西通常是用来做服务的，当然有很多人把它用作个人桌面也不错，但是新手就不知道如何去收他们在ISP的邮件了，其实很简单，只需要装个pop/imap的客户端软件就行了，netscape的套件就是很好的选择，KDE带的邮件客户端软件也不错，支持多帐号，就是不直接支持中文(用zhXwin吧)，或者用fetchmail把邮件抓回来转发到本地主机的客户，在本地主机上用mail程序来读。

我感觉mail程序好象是直接处理邮件队列，不知对不对。使用mail程序问得最多的问题是，在输入正文时怎么结束？另起一行输入一个"."就行了！

上面讲的是现在internet上的邮件系统，在internet出现以前电子邮件系统就有了，比如在uucp/BBS上，还有其它类型的网络上，就在internet发达的今天，这样的网络系统仍然与之并存。AOL、赢海威(IHWY)的网络上就不是标准的Internet电子邮件。
我以前就上过电信局的基于X.25网（准确的说应该是中国公用分组交换数据网CHINAPAC)的电子邮件系统，优点是真正的帐号漫游，缺点是速度太慢（至多9600bps,x.25本来就不快)，后来承诺要建一个X.400网关与Internet上的邮件系统转发信件，也不知道后来怎样了，因为我早已不用它，在IP over everthing的今天......

关于mail list功能，可以用sendmail的别名来做，或者用专门的软件majordomo.到中国自由软件库或者swjtu.edu.cn上去可以搜寻到。它的FAQ由barr维护。至于WebMail,可以到www.perl.com上找找有没有现成的CGI.现成的软件其实也很多如WeMail,WebMail Folder,WebMail Module(Roxen),Fetchmail(也可以哟,商业性的)IMP(IMAP WebMail)以及HTMail。

<a href=" http://horde.org/imp/">http ://horde.org/imp/</a> <a href=" http://www.chaotika.net/code/HTMail">http ://www.chaotika.net/code/HTMail</a>

Sendmail 安装指南

一个默认的sendmail.cf文件将被安装在/etc下。该配置文件可工作于仅使用SMTP的站点。而不能工作于UUCP站点；如果您要使用UUCP进行邮件传输就得重新生成一个新的sendmail.cf。这样的话，您就需要安装m4和sendmail的源代码包。请您阅读sendmail 源代码中的README以获取更为详尽的创建snedmail配置文件的方法。也可以看 O'Reilly&Associates出版的一本有关sendmail的不错的参考书（作者：Bryan Costales).

一种常用的sendmail的配置用一台机器作为网络中所有主机的邮件网关。打个比方，在红帽子软件公司我们有一台地址为mail.redhat.com的机器来处理我们所有的邮件。 我们只需简单的将mail.redhat.com要处理邮件的机器的名字加入/etc/sendmail.cw。下面 是该文件的一个例子：

torgo.redhat.com
poodle.redhat.com
devel.redhat.com

同样在torgo,poodle和devel的那些机器中编辑/etc/sendmail.cf，使其象mail.redhat.com 那样发送邮件，转发本地的邮件给redhat.com。 编辑含DH和DM的那些行：

DRmail.redhat.com

DHmail.redhat.com

DMredhat.com

以这种配置，所有发出的邮件都好象是从redhat.com发出的，而任何发往torgo.redhat.com 和其它机器的邮件都将发送给mail.redhat.com

请注意，如果您将您的系统配置为以另一机器身份发送邮件的话，任何以本系统为目的的邮件都将被发送至那台主机。比如，由cron进程定期产生的发网 <a href="mailto: root@poodle.redhat.com "> root@poodle.redhat.com </a> 日志文件都将发送给
<a href="mailto: root@mail.redhat.com "> root@mail.redhat.com </a> 。

E.10.3 我已经升级到 5.0 , sendmail 不再像以前一样传送邮件 .该做什么 ?

由于多方面的电子邮件商使用未知的 Red Hat 系统发送邮件和一些其他问题, 在 5.0 中, 我们将(不作为邮件传递者)作为缺省选项 .

你可以将你允许传递邮件的系统名称加入到文件
/etc/relay_allow

web 站点 <a href=" http://www.informatik.uni-kiel.de/~ca/email/check.html">http ://www.informatik.uni-kiel.de/~ca/email/check.html</a> 将告诉你更多关于这方面的信息 .

如果你希望某些发送垃圾邮件的站点不能访问到你的计算机, 你可以使用 sendmail 的一些新特性拒绝他们的访问. 将这些站点的地址加入到文件 /etc/mail/deny 中, 然后为它生成一个散列表 .

下面的命令可以生成这种散列表 .

makemap -v hash /etc/mail/deny < /etc/mail/deny

sendmail配置入门

学linux久了，也写点东西让大家共享 为了能从网络上接收SMTP电子邮件，我们必须在Linux系统上运行Sendmail守护进程。命令是；

为了方便起见，我们应该使用ntsysv命令把Sendmail守护进程加到引导程序中,在多数情况下，安装时Linux就已经自动将Sendmail包含在引导程序中了。这样每次开机时，Linux都会启动Sendmail守护进程并侦听端口25，处理进入的邮件
。
Sendmail的配置文件是/etc/sendmail.cf文件，它包含大部分的Sendmail配置的信息，包括在用户邮件程序和邮件传输程序之间为邮件选择路由所需的信息。Sendmail.cf文件有三个主要功能：

·定义Sendmail环境。
·按照接收邮件程序的语法重写地址。
·将地址映射成传送邮件所需的指令。
执行所有这些功能需要若干命令。一些宏定义和可选用的命令可定义其环境
，一些重写规则可以重写电子邮件的地址，一些邮件程序定义可定义传送邮件所
必需的指令。

sendmail.cf文件很大，看上去可复杂，但我们需要改动的地方很少。主要在local info中做文章。请在文件中寻找“Cw”，原来产生的cf 文件，Cw应是：

Cwlocalhost

请在localhost之后加上我们那一台机器所有可能用来当收信地址的主机的名字。例如，在局域网络Virtual Brewery中的一台机器叫：vlager.vbrew.com，而且也叫gopher.vbrew.com，而该网络的管理员希望这一台机器的这两个名字都能收信，那么他需要这样修改sendmail.cf文件：Cwlocalhost vlager.vbrew.com gopher.vbrew.com上面只是一种简便的方法，如果系统中运行着DNS，我们可以通过DNS来解析主机别名（如下所示），而不用加上主机别名gopher.vbrew.com。如果没有运行DNS，那么必须将本机器的所有名字都写上。如果用作邮件服务器的主机有多个名字（hostname），例如：
vlager IN A 191.72.1.1
gopher IN CNAME vlager
那么我们可以不必在Cw上标明，系统会透过DNS 找到它的别名如果一台机器有多个名字，但是每一个别名是用A record 建立的，例如：

vlager IN A 191.72.1.1
gopher IN A 191.72.1.1

在这种情况下【一定】要记得在Cw后写上所要收信主机的名字。如果忘记了，那么从外面寄来的以别名为地址的信件将无法正常接收，机器会抱怨：
“Local configuration error”
例如，如果在sendmail.cf中的Cw这行是Cw vlager.vbrew.com，那么局域网Virtual Brewery中的用户将无法使用邮件地址 username@gopher.vbrew.com 而只能用username@ vlager.vbrew.com，否则将出现上述错误。
如果一台机器有多interface，各interface有其本身的名字，而且要收信。这种情况也要在Cw之後写明所有要收信的hostname。
在我们的例子中F命令是作为注释处理的，如果去掉它前面的“sendmail将从/etc/sendmail.cw中读取主机的别名，并将别名储存在类w中。将F命令做注释处理，并让sendmail在内部定义别名这是一种最常用的方法。

打开/etc/mail/access文件时，会看到（注意一些系统的access文件不再/etc/mail下，如找不到请用whereis查找或检查是否安装正常）：

iption

le)

l-doc

localhost.localdomain RELAY
localhost RELAY

如果我们主机的IP地址是191.72.1.1的话，就应该在最后一行加上它的记录项，这样，我们修改后的文件的最后三行应是：

localhost.localdomain RELAY
localhost RELAY
191.72.1.1 RELAY

加上这句话我们就可以用sendmail发送接收mail了。但是如果我们想让别人也可以使用sendmail的话，而他的IP是202.168.25.22，这样就在在最后一行加入 他的主机的记录项，这时文件的最后四行应是：
localhost.localdomain RELAY

localhost RELAY
191.72.1.1 RELAY
202.168.25.22 RELAY

当我们考虑到多用户的时候，sendmail允许我们添入整个B类或C类地址，其格式如下：
localhost.localdomain RELAY
localhost RELAY
191.72 RELAY
202.168.25 RELAY

这样，我们就是把整个网络都加入的sendmail中，这个地址中的用户，如果在我们的系统里有账号的话，可以使用sendmail收发信件了。

Linux还允许我们设置邮局协议（POP）邮件服务器，POP协议分两个版本POP2和POP3，很显然POP3是新版本的邮局协议，现在Internet网上主要是POP3协议。POP3并不需要我们来配置，RedHat已经为我们做好了这一工作。我们只需要修改一下 /etc/inetd.conf文件，确保POP3能正常工作即可：

查找到：

把这一行前面的“

在该文件中查找到

同样，将这一行前面的注释符“netd和sendmail守护进程：

在我们配置完sendmail后，可以运行以下的命令来检查目录的读写权限以检查潜在的安全漏洞。

这时，sendmail将开始初始化alias数据，如果在屏幕上回显：
WARNING: writable directory /etc
WARNING: writable directory /usr/spool/mqueue
那么这个目录列出了不适当的写特权，应该使用chmod和 chown命令以避免多方面的的安全攻击。一般我们需要对如下目录运行chmod和chown命令：

mqueue

mqueue
sendmail 的有一些参数可以用于验证地址处理的结果，以确保其新配置的合理性。一旦认为配置可以正常工作了，我们就可以选择各个站点上的朋友，并将邮件发送给他们。发送时使用-v参数就可以显示邮件传输的各个细节和两个站点之间进行SMTP交换的全过程。下面是一个测试的例子，使用的文件是test.cf，一旦测试成功，我们就可以将这个文件拷贝到/etc下并可以改名为sendmail.cf。

To: lack@vlager.vbrew.com
From:janet
Subject:Test for sendmail

Lack,please reply if you see this,Thanks.

^D
lark@ vlager.vbrew.com…..Connecting to vlager.vbrew.com via t
cp…
Trying 191.72.1.1 ….connected.
220 VLAGER.VBREW.COM on Web, 30 Sep 99 16:23:23 CST
>>> HELLO maths.groucho.edu
250 VLAGER.VBREW.COM is my domain name
>>> MAIL From:< gauss.maths.groucho.edu.>
250 OK
>>> DATE
354 Enter mail body, End by new line with just a ‘.’
>>>.
250 Mail Delivered
>>> QUIT
221 VLAGER.VBREW.COM closing connection
lack@vlager.vbrew.com …sent
我们在CTRL-D之前输入所有的内容，而sendmail则显示^D之后的内容。通过对sendmail的测试，我们就可以发现潜在的配置问题，并使用sendmail提供的一些附加查错工具解决这些问题。

RedHat6.2服务器配置方案 Sendmail

汤海京 mailto:%20thjthj@netease.com 受欢迎度：45 2001-02-22 10:59:18
6.1 简 介
邮件服务是用户所需要的最重要的网络服务。Web的通信量很大，但邮件主要用于个人之间的通信，而人－人的通信是商务的基础。没有邮件服务的网络是不完整的网络。换句话说，如果不能给用户提供完整的TCP/IP下的邮件支持，这样的网络操作系统也不值得信赖。
配置sendmail是一件大而复杂的工作，但也不完全都是这样，与其他一些网络服务器系统只安装SMTP服务器软件的情况相比，Linux已经配置好了多数的设置。在多数系统下，缺省配置都能良好的运行。我将在本章中给出一些配置的建议，主要的一些配置参数建议大家不要随意更改。

6.2 所需系统资源

6.2.1 配置文件：
文件　　　　　　　　　　　　　　来源
/etc/sendmail.cf　　　　　　　　sendmail-8.9.3-20.i386.rpm
/etc/sendmail.cw　　　　　　　　sendmail-8.9.3-20.i386.rpm

6.2.2 相关工具：
文件　　　　　　　　　　　　　　来源
/etc/rc.d/init.d/sendmail　　　 sendmail-8.9.3-20.i386.rpm

6.3 配置方案

1．/etc/sendmail.cf sendmail的主配置文件
作用：

控制sendmail运行时的配置。完整的sendmail配置应该包括7部分：
Local Info（本地信息）：这部分定义了本地主机的信息
Options（选项）：用来设置定义sendmail环境的选项。
Message Precedence（消息的优先级）：sendmail消息的优先级
Trusted Users（信任用户）：定义发送邮件时允许改变发送地址的用户
Format of Headers（头格式）：定义在sendmail中插入的邮件头信息
Rewriting Rules（改写规则）：这部分保存着改写邮件地址命令使用该命令可以将邮件地址从用户邮件程序的地址形式改写为邮件发送程序所需要的地址形式。
Mailer Definition（邮寄者说明）：定义发送邮件的程序，改写规则是邮件者使用的规则，在本部分定义。
其实，配置一个完整的sendmail服务器是一件极其复杂的工程，然而对于我们所适用的范围来说，很多的功能是没有必要的，所以我想以一个简单的例子来说明我们的配置，也就是说，没有被提出的配置在一般情况下是不需要我们的管理员来考虑的，你按照默认的做就可以了。

实例：

V8/Berkeley
Cwlocalhost
Fw /etc/sendmail.cw
CP.
DYuunet.uu.net
CPUUCP
DS thj.mycompany.com
CO @ % !
C..
C[[
Kmailertable hash -o /etc/mail/mailertable
＃制作db库
Kdomaintable hash -o /etc/mail/domaintable
Kgenerics hash -o /etc/mail/genericstable
Kvirtuser hash -o /etc/mail/virtusertable
Kaccess hash -o /etc/mail/access
Kmxserved bestmx -z: -T<TEMP>
Kresolve host -a<OK> -T<TEMP>
FR-o /etc/mail/relay-domains
DR
DH
Kdequote dequote
CM root
DM thj.mycompany.com
＃设置邮件服务器名称
DnMAILER-DAEMON
CPREDIRECT
DZ8.9.3
O SevenBitInput=False
O EightBitMode=pass8
O AliasWait=10
O AliasFile=/etc/mail/aliases,/etc/mail/majordomo
O MinFreeBlocks=100
＃规定最小空闲块
O MaxMessageSize=1000000
＃指定用户一次最大发送的邮件大小
O BlankSub=.
O HoldExpensive=False
O DeliveryMode=background
O AutoRebuildAliases=true
O TempFileMode=0600
O HelpFile=/etc/mail/sendmail.hf
O SendMimeErrors=True
O ForwardPath=$z/.forward.$w:$z/.forward
O ConnectionCacheSize=2
O ConnectionCacheTimeout=5m
O UseErrorsTo=False
O LogLevel=9
＃记录到日志文件的事件等级
O CheckAliases=False
O OldStyleHeaders=True
O PrivacyOptions=authwarnings,noexpn,novrfy
O QueueDirectory=/var/spool/mqueue
O Timeout.queuereturn=4d
O Timeout.queuewarn=4h
O SuperSafe=True
O StatusFile=/var/log/sendmail.st
O DefaultUser=8:12
O SmtpGreetingMessage=$j Sendmail $v/$Z; $b
O UnixFromLine=From $g $d
O OperatorChars=.:%@!^/[]+
Pfirst-class=0
Pspecial-delivery=100
Plist=-30
Pbulk=-60
Pjunk=-100
Ft -o /etc/mail/sendmail.ct
Troot
Tdaemon
Tuucp
R$* $
＃以上是Linux默认的选项，不允许客户机使用mail服务器收发邮件，如果允许客户机收发的话应将上边一句话改成
R$- $@ok
＃注意：中间是两个tab键
＃一下是邮件头信息
H?P?Return-Path: <$g>
HReceived: $?sfrom $s $.$?_($?s$|from $.$_)
H?D?Resent-Date: $a
H?D?Date: $a
H?F?Resent-From: $?x$x <$g>$|$g$.
H?F?From: $?x$x <$g>$|$g$.
H?x?Full-Name: $x
H?M?Resent-Message-Id: <$t.$i@$j>
H?M?Message-Id: $t.$i@$j
＃以上是邮件头信息

2．管理员需要执行touch /etc/mail/aliases 和 touch /etc/mail/majordomo来创建两个文件，然后重新启动sendmail，利用sendmail.cf里生成db库的配置来生成两个库文件：aliases.db和majordomo.db；当然，管理员也可以通过执行makemap hash mailertable < mailertable来生成新的db，这样可以不重新启动。

6.4 测试及管理方法

1． 管理员可以通过执行/etc/rc.d/init.d/sendmail restart来使更改的配置生效。
2． 管理员通过执行 fetchmail -u yourname yourserver 来为没有邮件用户制定他们的口令，用户需要在客户端作相应的设置。
3．管理员应该打开pop3服务，即更改配置文件
4．管理员在服务器上可以通过执行 echo test | /usr/sbin/sendmail -v thj@mycompany.com 来测试建立好的邮件用户是否能够正常工作。

6.5 本章小节

其实我们只要设置其中的几个地方就可以实现mail服务器的功能，这是因为sendmail有很强的适用性，并且它是在不断更新的。所以现在提供给我们的sendmail的配置方案已经经过实践检验，不需要管理员做太大改动，就可以实现强大的sendmail功能。

Sendmail的配置(行的!)

Sendmail对一般的系统管理者而言，往往是个不敢手的「禁区」 ，因为绝大多数系统的使用者对E-Mail的需求与依赖的程度之高，可说是稍有分毫差错，系统管理者就要准备接受如雪片般飞来的抗议与 抱怨！而Sendmail这个东东的「内函」，似乎又有点不太容易理解： 与设定有关的sendmail.cf 档，如果不是下过一番死功夫，则读起来如同读天书一样，只知道里面有英文字与
数字！所以一般人总是能不 动则不动，只要能用就好。不过，很不幸的，一般跟著机器而来的sendmail总是有著令人心惊胆跳的「附加功能」，就是常常都有一些可以让无聊人士作为侵入路径的BUG 或後门，某些BUG 还可以让侵入 者经由Sendmail而取得最高权限的root！一旦root权限被人拿走了， 那麽这机器就可被人任意屠宰，最恶劣的，还可能破坏系统！

    Sun 在国内的使用人口相当的多，笔者对Sun 也稍微比较熟悉一点。不过，Sun的Sendmail却是令人颇不敢恭维的，几乎可以说：只要还在使用Sun 的Sendmail而没有「常常」patch 的话，那甚麽系统安全都不必谈了，谈了也是白谈；如果还在使用Sun 的Sendmail，那就如果系统抱著一颗不定时炸弹，随时一个不注意，都可能引爆:(。这一点，大家可以翻一翻CERT或8lgm看一看，几乎是只要有sendmail 的问题，Sun 大多跑了....。其他系统的Sendmail也不要偷笑，虽然大家的出场率没有Sun 高，可是也常会问题的。 另一方面，Sendmail 8.6.9与之前的版本最近刚发现有个ident方面的Bug 。如果方便的话，请大家务必换成最新版。如果不方便的话，在v8.6.5之後的版本有个克难式的补救法，即在sendmail.cf 加入这麽一行：
    Orident=0
    表示不作ident 的检查。
    v8.6.5之前的版本就一定要换成最新版。

    本软体在系统安全方面，是目前评价最高的，目前已知的BUG都已经改好了，最主要的原因，当然是要感谢作者Eric Allman ，他(或他们)能作到一发现重大的Bug (如系统安装)就立刻出新版。本软体是一public domain ，可以在网路上各ftp server上找到其source code。由於该软体的发展者把一些必要的设定步骤自动化了，所以，其实安装这个软体并不是想像中那麽样的困难。如果连compile 的时间也算下去，顺利的话，不用半个小时就可以安装完毕！所以，「麦惊」啦！：
）

3.安装Sendmail

3.1 下载Sendmail最新版本

    最新版本的Sendmail可以从 http://ftp.sendmail.org/pub/sendmail/ 得到！如 sendmail.8.9.3.tar.gz 这是截止到文章发布的最新版本，size：1068290byte 有关最新版本的发布，请浏览Sendmail的主页 http://www.sendmail.org/

3.2 安装Sendmail

    用root登陆或su成root后，先把tar.gz的包解开tar fvxz sendmail.8.9.3.tar.gz,用make-f 开始编译

    编译完成后系统会产生系统设定文件，也就是sendmail.cf （一般这个文件都存放在/etc下）

    接下来，这按几步继续安装： (注：～/sendmail为解开后的sendmail目录）

    1.请切换至设定档目录～/sendmail/cf/cf 之下。找一个合适自己系统的XXXX.mc档。笔者一般上是使用tcpproto.mc 这一个不用uucp的档。如果是用tcpproto.mc 这个档，笔者在solaris2.3 试了，得记得在档中要加上一行：
    OSTYPE(solaris2)
    Sun 4.1.3 不必，其他系统就不晓得了。在目录 ～/sendmail/cf/ostype下有几个OSTYPE()可以的 档，只有这个目录有资料的才可能能够OSTYPE()。还有， 如果是 system V的/bin/mail，似乎就得要加OSTYPE()。
    一句老话，详情请看DOCUMENT：～/sendmail/cf/README。这希望有经验的朋友能够补充：）　　如果不小心忘了加上OSTYPE()会怎样？也不会怎样，只会有"unknow mailer error" 的错误，然後信收不到。
    有一点要提醒大家的，就是：在～/sendmail/cf/cf 所看到的各种系统的.mc 档，都是Sendmail 8.6.x的作者 Eric Allman 「演示」给大家看的，所以，可以看到档名都有个"cs"，要是没有修改就用这些档的话，那一定会发生错误的。而要修改，有相当多地方要改，所以，如笔者一般懒的人，用tcpproto.mc 还是比较简单又不会出错:)

    2.好，选定了某一个合意的.mc 档，那接下来可执行m4产生.cf 档。请下指令：

    要是还是不行，那就请去抓新版的m4回来compile （可以在 http://www.gnu.org/ 找到gnu的m4）。

    这个步骤是要把compile好的files, install 到系统上去了。

    罗嗦的我还是得再一次提醒您看看：把旧档案备份好了吗？

    好，假设compile 的结果非常没挑战性的没有任何错误，产生.cf 档过程也没有甚麽值得注意的讯息。所产生的.cf 档 也改好了。而且最重要的：作好旧档的备份（不是我要吓人，这是以防万一）。

    1.挑个老板没有在用mail的时间，快手快脚的切换至目录～/sendmail/src ，下指令：

    系统会把compile出来的～/sendmail/src/sendmail与man document拷贝到它们该有的目录（所以你还如果没有备份/usr/lib/sendmail ，那赶快祈祷待回不要出问题，要不然就赶快准备泪水哭吧！ 因为旧的会被compile 出来的sendmail覆盖）

    2.切换至目录～/sendmail/cf/cf ，把产生出来的YYY.cf档拷贝到本系统sendmail.cf 应该在的地方，如：/etc或 /etc/mail 。

    3.把旧sendmail daemon 的process 杀掉。（这应该不用我罗嗦吧！用ps -ax |grep sendmail |grep -v grep 找出旧daemon的process(或head -1/etc/sendmail.pid　或 head -1/etc/mail/sendmail.pid)，然后用 kill -9 processID干掉它(或直接用 kill -9 `head -1 /etc/sendmail.pid`)。

    4.启动新daemon。例如下指令：
    /usr/lib/sendmail -bd -q30m
    当然，保守一点，看旧的daemon怎麽跑，照旧的来下参数应该是没有问题。
    这时,初步安装就已经完成了，接下来请看设置sendmail

3.3安装Sendmail注意事项

    如果安装不成功，请参考下面的问题：
    用vi或任一种编辑器，编辑的makefile档，作一点点 必要的修改。所要修改的地方不多，下面是可能要修改的地方：

    1."CC ="如果原档所用的compiler并不是我们系统的，这才要改。

    2.本系统是否有安装Berkerlay 的New database？如果有，跳过本点，到第3点。 如果没有（如：一般SunOS 都没有装），那麽请修改这几 行（下面以Makefile.SunOS为例，但其他系统也类似）：

    A.在 DBMDEF= -DNDBM -DNEWDB -DNIS 一行，请改成： DBMDEF= -DNDBM -DNIS （即去掉-DNEWDB）

    B.把这两行REMARK起来： INCDIRS=-I/usr/sww/include/db -->INCDIRS=-I/usr/sww/include/db
LIBDIRS=-L/usr/sww/lib -->

    C.修改LIBS= -ldb -ldbm -lresolv 这一行成： LIBS= -ldbm -lresolv （即去掉-db ）

    3.把nroff 的"-mandoc "参数改成一般系统可以接受的 "-man"（当然，这得依你的系统而定，如果你是用groff，那就可以很愉快的直接使用，不必改这个参数:)。如果不改也并不会影响sendmail的安装，只是不能看到格式化後的sendmail相关文件罢了。

    关于DIRECTORY PERMISSIONS的问题你需要执行2条命令：

    chmod go-w / /etc /etc/mail /usr /var /var/spool /var/spool/mqueue
    chown root / /etc /etc/mail /usr /var /var/spool /var/spool/mqueue

    许多系统的spool目录使用/usr/spool来代替/var/spool，设置别名的etc/mail取而代之的是/etc,如果你要在sendmail.cf设置RunAsUser许选项，/var/spool/mqueue这个目录需要RunAsUser 用户的权利，ok,这时开始编译Sendmail,执行这条命令

    sendmail -v -bi

    这时，开始初始化alias database. 如果它显示：

    WARNING: writable directory /etc
    WARNING: writable directory /usr/spool/mqueue
    那么这个目录列出了不适当的写特权，应该避免多方面的的安全攻击。

4.1 设置Sendmail.cf
    产生出来的YYY.cf一般得要改个地方才能正常的收信。请寻找"Cw"，原来产生的.cf 档，Cw应是：Cwlocalhost请在localhost 之後加上你那一台机器所有可能用来当收信地址的host name 。
    例如我有一台机器叫：ftp.games.net.cn，而且也叫：gopher.games.net.cn，而我希望这一台机器这两个名字都能收信，那我要这么作：
    Cwlocalhost ftp.games.net.cn gopher.games.net.cn

    顺便说一下，Cw之後只能写入本机器的名字，千万不能写入其他机器的名字，否则，甚麽地方都能寄，那被写的就一定不能寄。

    上面其实是简略的说法，如果你对DNS 也熟悉的话，可参考这节来作判断，判断是否须要在Cw之後写入东东。否则请直接跳过这一小节，闭上眼睛把本机器所用的所有名字都写上就是了:)

    1.在一台机器上，如果有多个名字(hostname)，而是用CNAME 建立的，如：
    $ORIGIN games.net.cn
    ftp IN A 140.119.1.2
    gopher IN CNAME ftp

    那麽可以不必在Cw上标明。系统会透过DNS 找到其 Canonical name。

    2.如果一台机器有多个名字，可是，每个名字是用A record 建立的。如：
    $ORIGIN games.net.cn.
    ftp IN A 192.168.25.2
    gopher IN A 192.168.25.2
    这种情况【一定】要记得在Cw後写上你所要收信的名字。如果这个忘了写，会有怎样的问题呢
？
    忘了将会有从外面机器寄信来，没有写上的机器名将却收不到信，机器会抱怨：
    "Local configuration error" 。

    如：我的sendmail.cf中的Cw这行是如下： Cw games.net.cn
    那我将无法使用这个地址：
     username@games.net.cn
    而只能用
     username@ftp.games.net.cn 否则将出现上述错误。

    如果发现了错误，那再加上去也就可以了。

    3.如果一台机器有多interface ，各interface有其本身的名字，且要收信。　　这个情况也要在Cw之後写明所有要收信的hostname。

    ok!一个标准的sendmail.cf文件就设置完了！

4.2 设置access

    打开/etc/mail/access，你会看到 （注意一些系统的access文件不再/etc/mail下，如找不到请用whereis查找或检查是否安装正常）

    localhost.localdomain RELAY
    localhost RELAY

    如果您的IP地址是192.168.25.11的话，这样请在最后一行加上192.168.25.11 　　RELAY
    其文件的最后三行应是：

    localhost.localdomain RELAY
    localhost RELAY
    192.168.25.11 RELAY

    加上这句话您就可以用sendmail发送接收mail了！但是如果您想让别人也可以使用sendmail的话，他的IP是202.168.25.22，这样就在在最后一行加入202.168.25.22 　　RELAY
    其文件的最后四行应是：

    localhost.localdomain RELAY
    localhost RELAY
    192.168.25.11 RELAY
    192.168.25.22 RELAY

    我想，您现在一定有个疑问是，如果我想设置50个人用sendmail是不是需要加50个IP啊！？
    嘿嘿，不用啦，是这样，sendmail考虑到多用户的时候，它准许你添入整个C类地址，（B类好像也可以，我没try过！）
    其格式如下：

    localhost.localdomain RELAY
    localhost RELAY
    192.168.25 RELAY

    这样，您就是把192.168.52这整个C都加入的sendmail中，这个C类地址的用户，如果在你的系统里有账号的话，就可以使用sendmail收发信件了！

4.3 设置pop3

    如果您需要pop3来接收信件，您需要打开pop3端口，

    vi /etc/inetd.conf 查找到

    把

    vi /etc/services 查找到

    把

    这样，在restart inetd后，pop3 110端口就可以接信了！如果还是不行，请检查是否安装pop3端口！

4.4 如何restart sendmail；inetd以及注意事项

    有一点要提醒大家的，要用"kill -9 [pid-of-sendmail]" ，从新启动sendmail 如果用 kill -HUP 是不会发生作用的！ (这是颇多人常遇到的问题，切记！) 在redhat6中用/etc/rc.d/init.d/sendmail restart即可！

    inetd是/etc/rc.d/init.d/inetd restart

5.1 sendmail的别名和forward

    (1) 关于直接用IP地址发信

    mail user@[166.111.IP.Address]
    只要用[]将IP地址括起来就行了

    (2) 关于alias

    sendmail在/etc下有两个文件 aliases和aliases.db, 后者是前者用newaliases生成的别名数据库. 你可以手工编辑/etc/aliases, 然后运行newaliases更新数据库(其实newaliases是个到sendmail的 symlink)

    eg: nickname : user@hotmail.com
    alias-name: real-user-account

    则以后mail nickname就可以将信寄到 user@hotmail.com 处而别人寄给 alias-name@your.domain.name 的信就会转给真正的用户real-user-account

    (3) 关于forward

    在你的$HOME目录下面编辑一个.forward文件, 里面写上你要forward的目的e-mail地址或本机的用户名, 就可以自动将信 forward到相应地址

    eg: .forward: user@hotmail.com
    或 other-user-account
    则给此人的e-mail会forward到hotmail或other-user-account处

    (4) 关于vacation

    去找一个vacation包(如RedHat的contrib中有vacation的rpm), 装上后就一个/usr/bin/vacation程序和一个man.
    先运行vacation, 它会让你编辑$HOME/.vacation.msg文件, 就是要发回给对方告诉他你现在不看信的东西啦. 然后编辑$HOME/.forward文件, 写这样一句 \username, "|/usr/bin/vacation username", username 要换回你自己的了然后运行vacation -I建立$HOME/.vacation.db就好了 (看看man更详细)

    (5) 关于sendmail的一些文件

    /var/log/maillog sendmail的log, 分析错误有用
    /var/spool/mail/$USER 进来的信, 每个用户一个文件
    /var/spool/mqueue mail queue, 可以用mailq看队列中待发的信
    (mailq也是 sendmail的symlink了)
    dfxxxxxx 这是信的内容
    qfxxxxxx 这是信的subject和别的信息 (反正每信一个号了, 配对的)
    /etc/sendmail.cf sendmail的配置文件, 改动它可要小心
    /etc/sendmail.cw 假如你的机器有好多alias的话就把名字写在
    这个文件中, 这样写哪个都能收到信

5.2 限制邮件的大小

    Modify /etc/sendmail.cf:
    Mlocal, P=/bin/mail, F=lsDFMrmn, S=10, R=20/40,
    Maxsize=1000000,
    A=mail -d $u
    Mprog, P=/usr/local/sendmail/smrsh, F=lsDFMeu, S=10, R=20/40, D=$z:/,
    Maxsize=1000000,
    A=sh -c $u

    This limits incoming mail processed by by smrsh and /bin/mail to 1 million bytes.

    You can do the same with the Mstmp, Mesmtp, and Mrelay statements to limit the
size of outgoing mail as well.
    You can do the same with the Mstmp, Mesmtp, and Mrelay statements to limit the
size of outgoing mail as well.
转自chinaasp

Sendmail 配置

saend @ 受欢迎度：104 2000-09-12 09:35:33
3.1 了解电子邮件
    在世界上，数以百万计的计算机用户已经访问过电子邮件。Email已经成为互联网上最重要的服务，你可能没用过ftp，没上过BBS，没有自己的主页，但你应该有一个自己的电子邮件信箱。大量的商业网络或Internet服务提供商（ISP）可以使你在世界范围内访问电子邮件。电子邮件是在单机系统上的或在网络系统上的用户用来发送和接收电子信息的任何程序。它有如下优点：
      □你可以在很短时间内把数据发送到目的地。
      □你不用担心在发送和接收电子邮件的过程中被中断——因为这些都是由计算机系统来控制的。
      □你不必与通信人预约。
      □你可以在任何时间发送和接收电子邮件。
3.2 定制mail环境
    在使用mail程序时，系统会检测你的起始目录中的.mailrc文件。你可以根据自己的需要在.mailrc文件中设置不同的环境变量和命令。以下列出了环境变量：
      □
      □alias：设置单个别名或组别名。用法是：alias alias-name address-list
      □set：设置环境变量。用法是：set variable-name或set variable-name=string
    在使用mail时，你还可以在问号（？）提示符下发出以下命令：
      □askcc：在输入消息后提示输入cc:list。默认值是noaskcc
      □asksub：在输入消息前提示输入Subject清单。默认时是提示输入
      □noheader：在启动mail时，不打印可获得的消息的标题信息。默认时是打印标题信息
      □ignore：在输入信息时，忽略中断字符。如果连接的电话或其他通信线路上有“杂音”，这个变量很有用。默认值是noignore
      □metoo：当你的名字在组别名中时，消息通常不发送给你。默认值是nometoo
    以下是一个.mailrc文件的例子：

      set noignore

      set asksub
      set askcc

      alias billy wbracksto
      alias ham <a href="mailto: xiaoniao@linuxaid.com.cn "> xiaoniao@linuxaid.com.cn </a> bbow
      alias me gunter

      alias pirates <a href="mailto: wangtao@linuxaid.com "> wangtao@linuxaid.com </a> bbow
      alias research jones jreynold eackerma
      alias framistan wjones imgood <a href="mailto: linuxcd@linuxaid.net "> linuxcd@linuxaid.net </a> imgood

3.3　SMTP协议简介
    SMTP（Simple Mail Transfer Protocol）即简单邮件传输协议，它主要规定基础的电子邮件提交系统怎么传递报文。对于电子邮件系统怎么从用户接受电子邮件，用户接口怎么给用户显示接到的电子邮件，电子邮件如何存储以及电子邮件系统以怎样的频度发送报文等问题却没有作出规定。
    在SMTP中，客户机与服务器之间的通信是由可读文本构成的。开始，客户机通过三次握手与服务器（通常是TCP 25端口）建立一个TCP连接，然后等待服务器发送220 READY FOR MAIL。在收到220报文后，客户机发送HELO命令。之后，电子邮件交互以MAIL命令开始，在MAIL命令中，有一个“FROM：”字段，用于在出错是通知发信人。服务器收到MAIL命令后，发送250 OK作为响应，表示一切正常。MAIL命令成功后，客户方就可以将收信人地址告诉服务器，这是用一连串RCPT命令来实现。服务器接收到每个RCPT命令后，发送250 OK作为响应，表示正确接收；或者发送550 No such user here作为响应，表示没有这个用户。客户方的RCPT命令得到正确响应后，就可以DATA命令发送数据。服务器收到DATA命令后，发送354 Start mail input;end with . 给予响应。其中end with . 规定了用于结束电子邮件报文的五个连续字符，即：回车，换行，圆点，回车，换行，这就是为什么用MAIL发送邮件时，最后只含有一个圆点的行表示结束的缘故。
3.4 sendmail
3.4.1 sendmail简介
    Sendmail是由Eric Allman写的程序，后来经过很多人的贡献，才成为现在的版本。目前几乎所有的Unix/Linux系统都使用sendmail。sendmail的功能非常强大，这就使它的配置文件非常复杂，而且它的规则集非常难看懂。下面就详细介绍一下它的各项配置。
3.4.2 sendmail.cf配置文件
    一般来说不必自己去修改sendmail.cf文件。但是有时你可能想要了解一下sendmail.cf文件的内容。sendmail.cf文件通常由若干个节组成，以下是常见的节名： 节　　名 功　　能
  Local Information 　定义有关个人主机的信息
  General Macros 　定义有关本地网络的宏
  Classes 　定义用于特殊邮件传输程序的主机名群或域名群
  Version Number 　标识sendmail.cf文件的版本号
  Special Macros 　定义由sendmail所用的一些特殊的宏
  Option 　定义sendmail选项
  Message Precedence 　定义sendmail所用的各种消息的优先级值
  Trusted Users 　定义在发送邮件时可忽略发送者地址的用户
  Format of Headers 　定义sendmail插入的邮件首部格式
  Rewriting Rules 　定义用于重写邮件地址的规则
  Mailers 　定义sendmail用来调用邮件传输程序的指令
  Ruleset Zero 　定义一组称为Ruleset Zero的特殊重写规则
  Machine-dependent part 　of Ruleset Zero 　定义与配置相关的Ruleset Zero部分

    sendmail.cf命令从每一行的第一格开始，＃开头的表示注释，第一个字符表示指令，以下是每个指令的意义：
指　　令 说　　　明
Ｖ 　设定组态文件sendmail.cf的版本
Ｍ 　指定一个ＭＴＡ
Ｄ 　定义宏x的值为value
Ｒ 　重写lhs为rhs
Ｓ 　开始一个规则集合
Ｃ 　定义类别宏
Ｆ 　文件定义类别
Ｏ 　设定sendmail.cf选项
Ｈ 　定义标头
Ｐ 　优先权设定
Ｔ 　信任的用户
Ｋ 　具有键值的数据库
Ｅ 　重设环境变量
Ｌ 　扩充负载的支持

    命令D用来定义宏，然后该宏就可以被sendmail.cf文件中的其他配置命令和sendmail程序自身调用。宏的名字可以是任何单个的ASCII字符，以下是sendmail中所有的内部宏： 宏　名 含　　义 在sendmail.cf中定义
a 　RFCs822格式的原始日期
b 　RFCs822格式的当前日期
c 　Hop计数
d 　UNIX格式的日期
e 　SMTP数据项信息
f 　“来自”地址的发送者
g 　相对于接收者的发送者的地址
h 　接收主机
i 　队列标识
j 　节点的正式域名 √
l 　UNIX的行格式 √
n 　用于错误信息中的名字 √
o 　地址中的操作符集合 √
p 　sendmail的PID
q 　默认的发送者地址格式 √
r 　所用的协议
s 　发送者主机名
t 　当前时间的数值表示
u 　接收方用户
v 　sendmail的版本号
w 　该节点的主机名
x 　发送者全名
z 　接收者宿主目录

    命令O给sendmail的选项赋值。赋给选项的值可以是字符，整数，布耳值或时间间隔值。每个选项都在sendmail中进行了定义。以下是sendmail中所有选项的含义和用法： 选项名 用　　法 含　　义
A Afile 　指定别名文件的名字
a aN 　为@:@等待N分钟，然后重建别名文件
B Bc 　定义空代替字符
c c 　将邮件队列排队以等待邮件传输程序
D D 　重建别名数据库
db db 　以后台方式传输
di di 　交互式传输
dq dq 　在下一个队列运行时传输
ee ee 　邮递错误信息，总是返回退出状态0
em em 　邮回错误信息
ep ep 　打印错误信息
eq eq 　仅返回退出状态，无错误信息
ew ew 　写回退出状态
f f 　保持UNIX风格的From行
g gn 　设置邮件传输程序默认的GroupID为n
H Hfile 　定义SMTP帮助文件的名字
I I 　使用BIND名字服务器来解析所用的名字
i i 　忽略入局信息中的点
L Ln 　设置日志级别为n
M Mxval 　设置宏x的值为val
m m 　同时发往自身
N Nnet 　定义宿主网络名
o o 　接受旧格式首部
Q Q 　定义队列目录名
q qn 　定义用于决定何时排队任务的因子n
r rt 　设置用于超时的内部时间间隔t
S Sfile 　定义统计日志文件名
s s 　在试图传输前总是创建队列文件
T Tt 　设置排队超时为t
u un 　设置邮件传输程序默认的UserID为n
v v 　以冗余方式运行
W Wpass 　定义用于远程调试的口令
X X1 　如果平均负载超过１则拒绝SMTP连接
x x1 　如果平均负载超过１则排队邮件
Y Y 　在不同的进程中传输每个排队邮件
y yn 　每个接收者作业时间优先级差为n
Z Zn 　每次运行时减少n个作业优先级
z zn 　同前缀一起决定邮件优先级

3.4.3 sendmail的地址重写规则
    地址重写是sendmail的核心部分，它的作用是分析来自邮件程序的电子邮件的地址，并将它们重写成邮件传输程序所需要的格式。
3.4.3.1 规则集
    规则集是一组可以由数字引用的相关重写规则。Sn命令标志一个规则集的开始，其中n是这个规则集的编号，其范围从0～29。其中0～4号规则集是被sendmail直接调用的，它们的说明如下： 编　号 说　　明
0 　在规则集3之后调用，它将生成一个三元组：<传输程序，接收方主机，接　收用户名>
1 　用于消息中所有发送者地址
2 　用于消息中所有接收者地址
3 　最大和最复杂的规则集，也是用于地址的第一个规则集，将地址转化成正　规形式，即： <a href="mailto: local-part@host.domain "> local-part@host.domain </a>
4 　用于消息中所有地址并将内部地址转换成外部地址形式

3.4.3.2 重写规则
    地址重写规则由命令R定义，其格式如下：
     Rlhs　　　rhs　　　comment
    lhs，rsh和comment这三个字段之间用tab隔开。重写规则将输入地址与lhs进行匹配，如果成功，就按照rhs进行重写。重写后的结果再次与lhs匹配，如果成功，就再次按照rhs进行重写，直到结果不再与rhs匹配。
3.4.4 使用M4
    如果一行一行输入整个sendmail.cf文件不仅麻烦也容易出错。最简单的方法是用M4处理程序自动产生一个sendmail.cf文件。M4是一种宏前置处理器，用来把组态文件转换成sendmail.cf文件。它的用法很简单，在/etc下面找到sendmail.mc文件，修改后使用：
        $m4 sendmail.mc>sendmail.cf
    将会生成一个sendmail.cf文件。并自动覆盖原来的sendmail.cf文件。以下是sendmail.mc文件中各个指令的意义：
  divert(-1) 　管理输出字符传
  dnl 　在define后通常会自动产生空格，可以用dnl来删除
  include 　包含一个文件
  define arg 1 arg 2 　定义宏argument1设为值argument2
  undifine arg 1 　取消arg1的定义
  OSTYPE('Linux') 　定义操作系统的类型
  FEATURE 　功能选项，对应到/usr/lib/sendmail-cf/feature里面的　文件名称所定义者
  MAILER 　定义所有必要的邮件递送代理程序，MTA
  MASQUERADE_AS 　用来处理多主机名称问题
3.4.4 sendmail别名
    别名是sendmail最重要的功能之一。它在aliases中定义。aliases文件的位置由sendmail.cf中的选项A指定，一般位于/etc目录中。aliases是一个文本文件，其中每一行的格式如下：
      alias:recipeint[,recipeint,...]

    其中alias为邮件中地址的名字，recipient为邮件目的地址的名字。邮件目的地址名可以有很多，每个之间用逗号符隔开。下面介绍别名的几种主要用法：
    ◆ 保护登陆帐号
       许多网络黑客进攻网络计算机的第一步是获取目标机上合法用户的帐号，而电子邮件帐号一般和登陆帐号相同，这就使黑客有机可乘。但是可以用别名来保护合法用户的帐号。如一位合法用户的登陆帐号为xiaoniao，而他的电子邮件帐号可以是aaabbb。只要在别名文件中加入“aaabbb:xiaoniao”就可以达到这一目的。
    ◆ 电子邮件转发
       如果想要将发给xiaoniao用户的电子邮件自动转发给root用户，只需在别名文件中加入“xiaoniao:root”。又如用户xiaoniao离开这个单位。从安全角度上讲应该将他的用户帐号删除。但是由于他不可能马上将新的电子邮件帐号通知所有人，所以希望将他原来的电子邮件帐号保留一段时间。这只要在别名文件中加入“xiaoniao:新的电子邮件地址”。
    ◆ 邮件列表的实现
       别名最重要的功能就是实现邮件列表。通过它可以实现填写一个接收者地址而将信发给许多人。例如在主机上设置一个邮件列表xn_group，包括xiaoniao，lyong，twang 和lwang。只需在别名文件中加入：
       xn_group:xiaoniao,lyong,twang,lwang
       owner_xn_group:xiaoniao
    当接收者是xn_group时，信会自动发给xiaoniao，lyong，twang和lwang。当发送邮件给xn_group是如果出错，将把错误信息发给xiaoniao。
3.5　如何处理垃圾邮件
3.5.1 什么是垃圾邮件
    电子邮件是当今最先进，最快捷的通讯工具之一，随着她的广泛使用麻烦也随之而来。有时候你会莫名其妙的收到一些来路不明的邮件，它们中最多的就是那些令人生厌的广告。也许有一天，你打开电子邮箱检查邮件时，会看到有成千封E－mail，那么恭喜你,你被炸了。只要你上网，这些事就是无法避免的。垃圾邮件的泛滥，占用了网虫本来就不大的信箱空间，使得真正有用的邮件要么因为信箱已满而进不来，要么淹没在一大堆垃圾邮件中。这使得垃圾邮件被选为1998年国际互联网的十大新闻之一。
3.5.2 减少垃圾邮件的方法
    ◆ 大多数都使用一种叫"bot"的应用程序来搜索Internet上的各个网址、聊天室、网上讨论区、新闻组、公共讨论区以及其他任何能够充实他们业已庞大的数据库的地方。你可以尽量少在这些地方公布你的电子邮件地址。
    ◆ 如果你需要在某初留下你的电子邮件地址，使用特殊的书写E－mail地址的方法来对抗E－mail地址自动收集机。很多E－mail地址收集机完全依靠关键字母“@"来收集信箱，假设你的信箱地址为 <a href="mailto: xiaoniao@linuxaid.com.cn "> xiaoniao@linuxaid.com.cn </a> ，当你需要在某处留下你的E－mail地址时，如果将你的信箱地址写成xiaoniao AT linuxaid DOT com DOT cn，自动机就识别不出这是个E－mail地址，而稍具常识的网虫却能看懂这个信箱地址。
    ◆ 如果是Unix主机上的sendmail邮件服务器可以通过以下方法来对抗垃圾邮件：
       只允许指定的主机和域转发，首先定义一个文本文件sendmail.cR，文件中的每一行是一台主机的完整域名或一个域。按照以下文件修改sendmail.cf，则sendmail只对发送地址或目的地址是本机或sendmail中定义的主机或域进行中转。
  FR-o/etc/sendmail.cR

  Scheck_rcpt

  R<$+ @$ =w>　　　　$@ OK
  R<$+ @$ =R>　　　　$@ OK
  R<$+ @$*$ =R>　　　$@ OK

  R$*　　　　　$: $(dequote""$&{client_name}$)
  R$=w　　　　　　　 $@ OK
  R$=R　　 　 　　　 $@ OK
  R$* $=R 　 　 　　 $@ OK
  R$=@　　 　 　　　 $@ OK

  R$*　　　　　$

3.5.3 清除电子邮件炸弹的方法
    如果哪天你的电子邮箱被炸了，可以用如下方法解救：
    ◆ 打电话向你上网的ISP服务商求助，他们就会帮你清除E－mail Bomb。
    ◆ 用软件清除。现在有很多软件可以清楚垃圾邮件，如Spam Exterminator、SpammerSlammer、SpamKiller、Spam Attack Pro、SpamEater Pro、Bounce Spam Mail

Sendmail邮件系统使用初步

bacycle 奥索网 @ 受欢迎度：49 2000-11-18 11:20:38
一、为网站建立电子邮件帐号，使发往该站点的电子邮件可以收到；
1.1 用netconf命令设置基本邮件系统：
首先保证配置DNS服务时已经将邮件服务器指定（有MX的完整记录），否则退回修改DNS设置，否则会找不到某一个域的邮件服务器及其优先级，该域的信件就无法送达，当然就更谈不到在该域上找相应主机和用户账号。
之后，进入netconf 工具配置服务参数，选择 Mail delivery system (sendmail)，进入后在选择Configure basic information选项，按照下面内容配置：
Present your system as yourdomain.com
[x] Accept email for shung.com
Mail server youmailhost.yourdomain.com
Mail gateway
Mail gateway protocol smtp
------------------------Fatures----------------------------
[x] match full user name
[X] Enable relay control（spammers）
Messages size limit （o) No limit __________
[ ] Don't try to deliver immediatly
Mrocess queue every (minutes) 1
[ ] Use special shell smrsh
Maximum recipients per msg. （o) Defaults __________
------------------------DNS Fatures-------------------------
[x] wait for DNS
[ ] don't use DNS
..... 以下内容略，用默认值即可。

1.2 手工修改/etc/sendmail.cf文件内容，保证配置文件和如下内容相符（Sendmail-8.9.3版本）；

V8/Berkeley

Cw yourdomain.com （否则收发邮件时，邮件地址需要带上主机名，这样实际使用上并不需要）
Cw localhost yourmailhost.yourdomain.com

CV cicoo.com
CV cicro.com
CV hisell.com
CV timic.com （有多少，全部列出）

DMyourdomain.com （否则收发邮件时，邮件地址需要带上主机名，这样实际使用上并不需要）

DSyourmailhost.yourdomain.com （可以空着，需要时添加，用于服务器群集）

DNsmtp

DHyourmailhost.yourdomain.com （可以空着，需要时添加，用于服务器群集）

CLroot

CEroot

Troot
Tdaemon
Tuucp

CD

否则，会因为邮件中继的原因，yourdomain.com域以外的域或处于和服务器不同网段的用户机器无法正常发送和接受正常邮件（用微软IE5.0 附带的OUTLOOK5作为客户端软件，或Foxmail系列）
重新启动服务，使配置文件生效：
kill sendmail ：

Restart sendmail:

（记着开放pop和smtp端口，否则一切白费劲，改/etc/inetd.conf文件）
如果需要使用虚拟主机邮件系统，属于高级使用，大家可以和我交流，我的方法是用用户别名+用户邮件路由的方法。

1.3 使用fetchmail管理多邮件帐户:
    尽管使用pine能非常方便的管理多个POP3或IMAP邮箱，但是如果邮箱主机与当前Linux系统的网络连接很慢，使用pine来阅读这些邮箱中的邮件就非常迟缓。此时更好的办法是先在后台将邮件取到回本地邮箱中，然后使用pine或其他邮件处理程序进行处理。
    fetchmail就是一个非常方便的从远程邮件主机下载邮件的应用软件，它支持pop3、imap，以及对pop3的一些扩展协议。当安装好fetchmail之后，使用者可以直接启动fetchmail，来取得邮件的方法为：
$ fetchmail -p pop3 -u wangb email.online.ha.cn
password for wangb@email.online.ha.cn :
    在输入正确的口令之后，fetchmail将使用pop3协议访问主机email.online.ha.cn，并取回用户wangb的电子邮件，取回的电子邮件将发送到本地邮箱中。也可以用更复杂的方式在后台运行 fetchmail，则需要设置个人目录下的.fetchmailrc文件。
$ cat ~/.fetchmailrc
poll email-wangb via email.online.ha.cn
protocol pop3
authenticate password
username wb here is wangb there
password "1111"
smtphost localhost
pass8bits
stripcr
fetchall
$ chmod 700 ~/.fetchmailrc
    设置文件中第一行poll email-wangb via email.online.ha.cn中设置了要下载邮件的邮件服务器为email.online.ha.cn，其中email-wangb为对应这一个帐号的标签名字，用于区分多个不同的邮箱。然后指定使用的协议为pop3，认证方式为标准的Unix口令认证，然后，定义了远端主机上的邮件帐户名为wangb（用there表示远端主机设置），邮件下载到本地用户wb的邮箱中（使用here 指明本地主机设置）。
    smtphost定义了fetchmail用来转发邮件时使用的smtp主机，passsword定义了远程邮件服务器中帐户的口令，在口令中使用了数字或特殊字符时，就需要使用双引号将口令括起来。pass8bits 允许下载邮件中存在8位字符，stripcr用于过滤额外回车字符，由于DOS和Unix在文本定义上的不同，这一项用于兼容一些不识别这个差异之处的Windows系统的邮件服务器，fetchall表示取回全部邮件，否则就只取回最新的邮件。
    此外，这个文件因为包括了远端服务器的口令，因此必须具备属性700，以避免其他用户能读取这个文件，否则fetchmail不会运行。
    这样，就可以不使用任何命令行参数，直接在后台运行fetchmail了。每个用户可以使用cron来运行自己的fetchmail命令，来管理自己的邮件，而拨号用户可以在拨号后，使用ppp.linkup启动fetchmail ，取回自己的邮件。

1.4 使用Procmail设置邮件过滤:
    由于Internet的使用者不但使用电子邮件和朋友、同事联系，而且还通过maillist与Internet 上的其他使用者讨论共同感兴趣的话题，用户收到的电子邮件越来越多，并且还会受到广告、宣传品等垃圾邮件的骚扰。使用Promail、maildrop等邮件过滤程序就能帮助使用者阻挡这些广告和宣传品，并帮助管理用户接收到的邮件。Procmail就是一个用于过滤用户接收到的电子邮件，并能对其自动分类、处理的一个应用软件。对于每天都会收到大量电子邮件的Internet使用者，这是一个非常有用的工具。
    为了使用Procmail，必须在用户接收到Email时，启动Procmail进行处理。这个任务可以使用两种不同的方式来完成，一个是将Procmail配置为系统的邮件分发代理（Mail Deliery Agent），系统的邮件服务器使用porcmail代替其本身原有的邮件分发功能，来分发用户的邮件。这种方式需要由系统管理员根据邮件服务器的不同，而进行不同的设置。
    另一种方法是使用个人目录下的.forward文件，系统邮件服务器在给某个用户分发邮件的时候，如果发现他的个人目录中存在.forward文件，那么就会按照这个文件中的内容来进行处理。因此就可以在.forward文件中启动procmail处理用户接收到的邮件，与更改系统MDA的设置方式相比，这种方式更为灵活，并且可以由每个用户来决定是否使用这个过滤处理能力。
    .forward文件可以按照需要设置三种不同的处理方式：定义存储邮件的邮箱文件名、进行转发的目的地址或者对电子邮件进行处理的外部应用程序，显然启动Procmail是应使用第三种方法。
    .forward文件应该属于这个用户（或root），并且其权限设置应该为不能被其他或同组用户可写。
$ cat ~/.forward
"|IFS=' '&&exec /usr/local/bin/procmail -f-||exit 75 wb"
    这个.forward的例子里，使用"|"字符设置括号内的参数为一个执行命令，这样 sendmail就能启动一个shell执行设置的命令，并使用管道的方式读取sendail的输出。执行命令中首先定义了IFS环境变量（用于分隔不同的域），然后执行procmail，如果procmail执行失败就执行 exit 75 wb告诉sendmail，邮件分发失败，需要更改wb为使用者自己的登录名。
    procmail使用用户个人目录下的.procmailrc文件，来设置对收到的Email进行处理的过滤规则。最简单的.procmailrc文件为：
:0c:
* ^FROM.*@Linux.org
$HOME/mail.backup
    第一行首先使用冒号开始定义一个过滤规则，紧随其后的应该是一个数字，这个数字规定了这个规则占用的配置行数，一般使用0表示没有限制配置行，此后的c表示复制（copy），表示下面的规则只是用于处理邮件的副本，而邮件本身仍然会被其他的过滤处理规则处理。这一行最后的冒号，用于表示在处理过程中进行加锁，防止同另一个procmail进程处理同一个文件时发生冲突，通常这个机制在存储邮件文件时非常有帮助。
    第二行就开始了一个过滤规则的定义，过滤规则使用*字符开头。一个规则中使用模式匹配来匹配电子邮件信头或内容中的特定行。上面例子里的这个规则匹配所有来自于Linux.org的电子邮件。在第三行定义了对符合上面规则的邮件的处理方法，由于给出了一个文件名mail.backup，因此将所有来自于Linux.org的电子邮件添加到mail.backup文件中保存。如果使用!开头定义规则处理办法，表示进行转发处理，!后面就为进行转发的电子邮件的地址，或者以|开头，表示启动后面的命令进行邮件处理。
    procmail不区分大小写，它使用Unix最常用的模式匹配方式进行匹配特定的邮件。因此使用这些匹配模式和procmail规则，可以定义一个更复杂的.procmailrc：
PATH=$HOME/bin: /usr/bin: /usr/ucb: /bin: /usr/local/bin:.
SHELL=/bin/sh
MAILDIR=$HOME/mail
DEFAULT=$MAILDIR/mailbox
LOGFILE=/dev/null
SENDMAIL=/usr/lib/sendmail
:0:
* ^From.*badguy
/dev/null/
:0c:
* ^(From|Cc|To).*Linux.org
| gzip >> freebsdmail.gz
:0:
* ^From.*@hotmail.com
* ^Subject:.*(joke|funny)
{
:0 c
! friend1@hotmail.com friend2@usa.net
:0
joke
}

:0
* ^Subject:.*order
* !^FROM_DAEMON
* !^X-Loop: marketing@company.com
{
:0 h c
| (formail -r -A"X-Loop: marketing@company.com " ;
cat /market/acknowlegement.txt ) | $SENDMAIL -t
:0 c
! market2@company.com
:0
market
}
  这个配置文件的第一部分中设置了几个环境变量，用于设置procmail的运行环境，其中将 MAILDIR设置为~/mail，与pine使用的目录相同，因此这将使pine能直接读取procmail处理过的邮件。
    第二部分中为邮件定义了三个不同的过滤规则及相应的处理操作，第一个规则将来自badguy 的邮件滤掉（输出到/dev/null）；第二个规则将与Linux.org的通信使用gzip保存到freebsdmail.gz 中，用于保存相应maillist的邮件；第三个规则将某个使用hotmail帐号的朋友，并使用joke或funny标题给自己发送笑话的邮件同时转给其他几个朋友，并同时保存在joke文件夹中；最后一个规则是设置了一个自动回复邮件系统，对于使用order做标题，并且没有FROM_DAEMON行（自动邮件回复程序使用FROM_DAEMON 作标记，通常不需要回复这些的邮件，否则会造成回复循环），并且没有包括X-Loop行的邮件进行处理：
  首先将X-Loop行添加到邮件中（使用formail将它们添加到mail的信封上），以免造成对同一个邮件的循环处理，然后将文件/market/acknowlegement.txt发回给发送者；并以及转发邮件，在market中保存邮件。
    根据这些规则，使用Procmail就能完整的处理各种邮件，减轻电子邮件不断增多而造成的困扰。

二、添加POP账号用户（用户没有login和telnet权限）：
1、userconf命令添加用户：
使用很简单，用root登录，使用userconf命令，找相应选项，添加POP用户。为了管理方便，建议在/home目录下建立popusers目录，以后的pop用户目录全部放在下面。不多罗嗦。
2、添加虚拟主机域：
用root登录，使用mailconf命令，找相应选项，添加虚拟主机域，然后在设置pop账号时，在虚拟主机域pop用户设置中就会出现虚拟主机域的列表，然后选择相应的域就可以添加pop用户了。

关于电子邮件系统的简介

首先简单的介绍一下邮件系统，主要由两部分组成：smtp协议(简单邮件传输协议)和pop3(邮局协议version 3)，smtp用于邮件在网络中的传递(mailer),而pop处理客户端邮件的接收。由于pop3的局限，将来肯定要被imap代替，imap有较好的目录服务能力，可以在下载之前看到邮件的主要信息如来源、标题等，还可以远程删除邮件等，但目前ISP还不会轻易用它来替换pop.注意不要与IAP的POP搞混淆了，那是当前接入点的意思(Point Of Present)。学得越多越糊涂:-(

最早在Linux传递邮件用的是smtp服务，在/etc/inetd.conf里可以看到这样一行：

#smtp stream tcp nowait root /usr/bin/smtpd smtpd

现在基本都用sendmail这样功能强大的deamon程序来做(nntp也是如此)。所以sendmail只是邮件传递者(mailer),它把这个主机上的邮件发送到其他地方，注意到配置DNS时有一项MX(Mail eXchang,邮件网关)，使用sendmail在你的网内要有一个DNS服务器。而处理主机上远程客户的邮件服务则要有pop服务，查看inetd.conf有这么几项：

pop-2 stream tcp nowait root /usr/sbin/tcpd ipop2d
pop-3 stream tcp nowait root /usr/sbin/tcpd ipop3d
imap stream tcp nowait root /usr/sbin/tcpd imap

再查看/etc/service就知道它们对应的端口号，用telnet host-name port试试能看到什么？Linux这样的东西通常是用来做服务的，当然有很多人把它用作个人桌面也不错，但是新手就不知道如何去收他们在ISP的邮件了，其实很简单，只需要装个pop/imap的客户端软件就行了，netscape的套件就是很好的选择，KDE带的邮件客户端软件也不错，支持多帐号，就是不直接支持中文(用zhXwin吧)，或者用fetchmail把邮件抓回来转发到本地主机的客户，在本地主机上用mail程序来读。我感觉mail程序好象是直接处理邮件队列，不知对不对。使用mail程序问得最多的问题是，在输入正文时怎么结束？另起一行输入一个"."就行了！
上面讲的是现在internet上的邮件系统，在internet出现以前电子邮件系统就有了，比如在uucp/BBS上，还有其它类型的网络上，就在internet发达的今天，这样的网络系统仍然与之并存。AOL、赢海威(IHWY)的网络上就不是标准的Internet电子邮件。

我以前就上过电信局的基于X.25网（准确的说应该是中国公用分组交换数据网CHINAPAC)的电子邮件系统，优点是真正的帐号漫游，缺点是速度太慢（至多9600bps,x.25本来就不快)，后来承诺要建一个X.400网关与Internet上的邮件系统转发信件，也不知道后来怎样了，因为我早已不用它，在IP over everthing的今天......

关于mail list功能，可以用sendmail的别名来做，或者用专门的软件majordomo.到中国自由软件库或者swjtu.edu.cn上去可以搜寻到。它的FAQ由barr维护。至于WebMail,可以到www.perl.com上找找有没有现成的CGI.现成的软件其实也很多如WeMail,WebMail Folder,WebMail Module(Roxen),Fetchmail(也可以哟,商业性的)IMP(IMAP WebMail)以及HTMail。

中小型企业的Sendmail邮件服务器应用实例

作者：Jephe Wu [中国Linux论坛]

简介:本文旨在介绍如何利用Linux服务器上的sendmail构建中小型企业的邮件服务器。们假定该企业采用专线接入Internet,有两台Linux服务器（Redhat 6.1 ） 一台作为防火墙直接接入Chinanet,是通向Internet的唯一出入口，同时也作为DNS/SMTP 服务器，且申请了域名domain.com,由该防火墙服务器（DNS服务器）对域domain.com进行解析。另一台邮件服务器是在内部网段运行，完全与外部世界无关。作为内部局域网上用户的收/发邮件服务器。

地址：假定防火墙Linux服务器的永久外部地址为a.b.c.d(eth0),内部网卡地址192.168.11.5(eth1),机器名为firewall.domain.com, 内部的邮件服务器地址为192.168.11.1，机器名为mail.domain.com , 且注册域时填写的主机名为dns.domain.com(a.b.c.d) .

思路：先配置DNS服务器，用来解析@domain.com的域名，并指明MX记录到内部邮件主机mail.domain.com. 把这台防火墙仅作为mail relay主机，任何从外部世界发往@domain.com域的邮件均由它处理且relay到内部邮件主机，仅接受@domain.com后缀的邮件进入，这样阻止了spammer发送垃圾邮件。
    在内部邮件服务器上，配置Sendmail的DS部分为firewall.domain.com，任何发往非内部员工的邮件直接送往firewall.domain.com，且设置domain.com为本地域，任何发往@domain.com域的邮件被内部别名处理并送往内部各用户的邮件缓冲池中。

旅行用户的考虑：
    若公司员工出差在外需从公司的服务器接收邮件，一种方法是直接拨当地ISP，然后设置接收邮件服务器为mail.domain.com，但要求mail.domain.com在外地被解析成防火墙的外部永久地址，这样再在防火墙上设置plug-gw代理，代理任何到防火墙外部地址的110端口的请求到内部192.168.11.1的110端口。
    另一种方法，也可以再建一服务器为Linux拨入服务器，直接拨到公司来接收邮件。

重点：Sendmail的各项配置及相关设置

一：防火墙上的Sendmail配置：
    我们采用Redhat Linux 6.1 加 Sendmail 8.9.3作为操作环境：

    安装操作系统和防火墙的配置略，建议采用3c905b或者Intel pro100 的网卡，先配置DNS。设置/etc/named.conf象这样：
============
zone "."{
type hint;
file "named.ca";
};
zone "0.0.127.in-addr.arpa"{
notify no;
type master;
file "127.0.0";
};
zone "11.168.192.in-addr.arpa"{
notify no;
type master;
file "192.168.11";
};
zone "domain.com" {
notify no;
type master;
file "domain.com";
};

文件 192.168.11象下面这样：
@ IN SOA dns.domain.com. root.mail.domain.com. (
1999092201 86400 3600 3600000 86400 )
NS dns.domain.com.
1 PTR mail.domain.com.
5 PTR firewall.domain.com.

文件 domain.com象下面这样：
@ IN SOA dns.domain.com. root.mail.domain.com. (
1999120401 86400 3600 3600000 86400 )
NS dns.domain.com.
A a.b.c.d
MX 10 mail.domain.com.
firewall A a.b.c.d
mail A a.b.c.d
dns A a.b.c.d

加下面的行到/etc/hosts
192.168.11.1 mail.domain.com mail
192.168.11.5 firewall.domain.com firewall
============
下面配置Sendmail,首先要先创建一个用来生成/etc/sendmail.cf的sendmail.mc文件，在Redhat 安装的过程中有一个默认地redhat.mc在/usr/lib/sendmail-cf/cf目录下。
我们修改为如下：
===========
divert(-1)
dnl This is the macro config file used to generate the /etc/sendmail.cf
dnl file. If you modify thei file you will have to regenerate the
dnl /etc/sendmail.cf by running this macro config through the m4
dnl preprocessor:
dnl
dnl m4 /etc/sendmail.mc > /etc/sendmail.cf
dnl
dnl You will need to have the sendmail-cf package installed for this to
dnl work.
include(`../m4/cf.m4')
define(`confDEF_USER_ID',``8:12'')
OSTYPE(`linux')
undefine(`UUCP_RELAY')
undefine(`BITNET_RELAY')
define(`confAUTO_REBUILD')
define(`confTO_CONNECT', `1m')
define(`confTRY_NULL_MX_LIST',true)
define(`confDONT_PROBE_INTERFACES',true)
define(`PROCMAIL_MAILER_PATH',`/usr/bin/procmail')
define(`ALIAS_FILE',`/etc/mail/aliases')
FEATURE(`smrsh',`/usr/sbin/smrsh')
FEATURE(`mailertable',`hash -o /etc/mail/mailertable')
FEATURE(`virtusertable',`hash -o /etc/mail/virtusertable')
FEATURE(`domaintable',`hash -o /etc/mail/domaintable')
FEATURE(redirect)
FEATURE(always_add_domain)
FEATURE(use_cw_file)
FEATURE(local_procmail)
MAILER(procmail)
MAILER(smtp)
FEATURE(`access_db')
FEATURE(`blacklist_recipients')
dnl We strongly recommend to comment this one out if you want to protect
dnl yourself from spam. However, the laptop and users on computers that do
dnl not hav 24x7 DNS do need this.
dnl FEATURE(`accept_unresolvable_domains')
dnl FEATURE(`relay_based_on_MX')
=============
然后用m4 redhat.mc > sendmail.cf生成sendmail.cf放到/etc目录下。且做如下操作：

1. 更改/etc/sendmail.cf中Fw定义为Fw/etc/mail/sendmail.cw
并创建一个空文件sendmail.cw （#touch /etc/mail/sendmail.cw）

2. 更改/etc/mail/mailertable象下面这样：
domain.com relay:[192.168.11.1]
并运行makemap hash /etc/mail/mailertable.db < /etc/mail/mailertable

3. 加下面一行到/etc/mail/access象下面这样：
domain.com relay
并运行makemap hash /etc/mail/access.db < /etc/mail/access
注：你不需要设置/etc/mail/relay-domains,因为你仅仅接受送往@domain.com域的邮件，通过access就可做到这一点，在收到@domain.com后缀的邮件后立即转送到内部主机192.168.11.1

4. 加下面一行到/etc/mail/relay-domains (如无，用vi创建一个）
192.168.11.1
注：仅允许内部网段上的邮件主机mail.domain.com(192.168.11.1)向它发信邮件，不允许内部网段上的用户设置SMTP服务器为firewall.domain.com(192.168.11.5)

二。内部邮件主机mail.domain.com的配置：
    仍然用下面生成的sendmail.cf文件，并做如下设置更改。

1. /etc/hosts
192.168.11.5 firewall.domain.com firewall
192.168.11.1 mail.domain.com mail

2. /etc/resolv.conf
search domain.com
nameserver 192.168.11.5

3. 加下面的行到/etc/mail/relay-domains(如无此文件，则用vi创建一个）
192.168.11
注：允许内部网段上的用户向它发信，且允许防火墙机器向它转送从外面进来的邮件。

4. 加下面的行到/etc/mail/sendmail.cw
domain.com
注：当收到一个从内部网段上发到@domain.com的邮件时被认为是本地主机/域，然后检查/etc/mail/aliases 文件查找别名

5. 设置别名文件/etc/mail/aliases
假设本地网段上有三个用户，邮件帐号分别为jephe,jack,tony.
则设置别名文件如下：
jephe: jephe@mail.domain.com
jack: jack@mail.domain.com
tony: tony@mail.domain.com
注：这样的话，你能在局域网上维护一个共同的地址薄供内部用户每个人采用.地址薄中就可以用jephe@domain.com,jack@domain.com, tony@domain.com。 对外公开的地址也是它们。

6. 设置/etc/sendmail.cf中的DS部分为
DSfirewall.domain.com
注：所有非@domain.com域的邮件都转送至防火墙处理，根据DNS MX查找后直接送到各个地方。

7. 设置/etc/sendmail.cf中的DM部分为DMdomain.com

其他功能：
8. 设置/etc/mail/access文件阻止从某些域/地址发来的垃圾邮件。

9. 设置/etc/mail/domaintable进行某些域转换。如果你的公司域名容易被打错，如某用户常容易错把jephe@domain.com打成jephe@doman.com， 则你可以把doman.com放入domaintable中你可以放下面的行到/etc/mail/domaintable,同样，运行
makemap hash /etc/mail/domaintable.db < /etc/mail/domaintable
-----
doman.com domain.com
-----
    你也可以放doman.com到/etc/mail/sendmail.cw中实现同样的目的这样不管是发到jephe@domain.com或是jephe@doman.com都一样。

三. windows 客户配置
在局域网上的windows客户机都设置发送/接收邮件服务器为mail.domain.com,
DNS服务器为192.168.11.5并使用一个共同的由网管维护的地址薄，其中含有公司
内所有用户的邮件地址。你可以在内部的邮件服务器上设置DHCP服务器自动配置
每台windows客户机的设置。

关于sendmail.cf的简单解释

以下信息主要摘自杜毅编著的《UNIX系统组网技术》，由电子工业出版社出版。这本书主要针对SCO Unix,不过对于Unix世界的初学者它值得一读，既然引用了人家的东西就要为它做的广告:-) 但愿没人找我麻烦。

在整理的过程中，我发现书上所写与TurboLinux带的sendmail略有不同和缺漏，未经作者同意自行加上，文字也不是完全照搬。
sendmail.cf的详细信息，请自己去/usr/doc/sendmail/下找op.ps,其中第5章把下列内容讲得很详细。

关于sendmail.cf的简单解释：
配置文件sendmail.cf中的信息仍旧是以行为单位。如果行首的第一个字符为“#”，则表示该行为注释，如果第一个字符为空格则表示该行为上一行的延续。此外，行首的第一个字符均为命令，但是命令同变量或值之间没有间隔。这种格式便于sendmail进行分析，但令我们很难阅读。下面我们将介绍sendmail.cf配置文件中的命令：

1 D,定义宏
命令D定义宏并为其赋值。当宏被定义之后，它就负责提供提供其存储的值给sendmail.cf文件中其他的命令使用或者直接提供给sendmail使用。宏的名字可以是任何单字符，小写的用于sendmail内部宏，用户创建的宏只能使用大写字母作为名字。一些sendmail的内部宏也在sendmail.cf文件里定义。例如下面两行定义了宏D和内部宏n：
DDcs.mit.edu
DnMAILER-DEAMON
则宏D的值为cs.mit.edu,宏n的值为MAILER-DEAMON.要使用宏的值时，必须在宏的名字前面加上符号"$",以这种形式来引用它的值。例如： #my official host name Dj$w.$D
如果宏w的值为主机名moon,此时宏j的值就为moon.cs.mit.edu,这便是本主机的全称名(FQDN).

2 C与F,定义类
命令C与F都是用来定义sendmail的类。所谓类，实际上就是由处理方式相同的多个变量组成的数组。与宏一样，类也使用单字符名字，大小写规则也一样。类可以定义在一行之中，也可以分多行定义，例如，下面的示范为内部类w赋值为系统的主机名，而系统可以有多个名字：
Cwmoon sun
Cwearth
Cwlocalhost
命令F是从文件中获取类的值，例如，可以把moon,sun,earth保存在sendmail.cw之中，然后用F命令便可以实现同上述命令完全相同的结果：
Fw/etc/sendmail.cw

对类的引用与宏的引用完全一样，事实上宏就是一种类。两者的唯一区别在于，宏只能有一个唯一的值，而类可以有多个值，当然也可以只有一个值。

3 O,设置选项
命令O是为sendmail的选项赋值，赋给选项的值可以是字符串、整数或布尔值，所有的选项值都是直接由sendmail来使用。需要注意的是，这里所说的选项与sendmail使用的命令行参数不一样。通常情况下，不需要修改这些选项。

4 T,定义可信任的用户
命令T用来定义一组用户列表，这组用户可以使用sendmail带-f参数来修改用户发出的邮件地址。一般情况下，包含root,daemon和uucp。管理员最好不要随意添加其他的用户，否则这种权限在某些用户手中可能会对系统安全构成威胁。可信任的用户可以在一行或多行中定义，但是被定义的用户必须是/etc/passwd中的合法用户。缺省是：

Troot
Tdaemon
Tuucp

5 P,设置优先级
sendmail使用命令P定义不同的优先级来处理进入出局缓冲区的电子邮件。命令P定义的值越高，则优先级也越高，缺省的优先级为0。负优先级的电子邮件是不产生错误信息的，因此在批量发送邮件是应该定义较底的优先级。常用的优先级为：
Pfirst-class=0
Pspecial-delivery=100
Plist=30
Pbulk=-60
Pjunk=-100
如果用户在发送邮件是需要指定优先级，则需要在邮件的首部中添加Precedence,例如：
Precedence:bulk

6 K,Key File Declaration
特殊的映射可以定义成：
Kmapname mapclass arguments
mapname是可重写规则中使用这个映射的句柄，mapclass是映射类型的名字，arguments的解释依赖与映射类型，通常是包含映射的文件名。

7 V,Configuration Version Level
提供与老版本配置文件的兼容性能。

8 M,定义邮件传输程序
命令M定义邮件传输程序(mailer)的规格/详细参数，其形式如下：
Mname, {field=value}
sendmail并不是直接发送各种各样的电子邮件，它首先将要发送的邮件分类，然后交给相应的mailer来发送，它本身只发送基于SMTP/TCP/IP的邮件。其中[IPC]表示使用sendmail通过smtp来传送邮件。关于IPC mailer,在sendmail的文档里有一段有趣的特殊
解释：当规则集0解析到IPC mailer时会处理一些特殊的过程。比如直接用IP地址发送邮件可以用[128.32.149.78]的形式，若用[ucbvax.berkeley.edu]将会怎么样呢？它会被作为字符串传递，用这样的方法用户可以构造一个特殊的邮件地址，使自己的邮件按指定的路线发送，而通常用户是不关心也不知道自己的邮件的发送路线的。

9 H,定义邮件的首部格式
命令H定义sendmail插进电子邮件首部的行的格式。

10 R,定义重写规则
重写规则是sendmail配置文件的核心内容，每一重写规则由命令R定义，其形式如下：
Rpattern transformation comment
命令R中的字段由制表符进行分隔，系统处理时忽略注释字段(comment),模式字段(pattern)
与改写字段(transformation)为该命令的核心。
重写规则将输入地址与模式进行匹配，如果匹配，则将该地址用规则中改写字段的规则重写为新的格式。每一规则可以多次处理同一地址，这是因为地址在重写之后，仍要再次同该模式进行匹配，如果仍旧匹配则再次改写，直到不再匹配为止(使用"$:"可以避免无限循环)。
在Linux中格式的表达应该是：
Rlhs rhs comment
lhs--left hand side rhs--right hand side

11 S,设置重写规则集
规则集是一组可以用数字来引用的相关重写规则。命令S是规则集的开始并赋予它一个数字以便由邮件传输程序来调用。规则集可以被看作用来处理电子邮件地址的子程序或函数。具有特殊功能并可由sendmail直接调用的规则集有5个：
规则集3：为最大最复杂的规则集，也是用于地址的第一个规则集。它将地址转化为正规形式如：user@host.domain。
规则集0：应用于传输邮件的地址。必须在规则集3之后使用，并仅用于实际邮件传输中接收者的地址。它可以将地址解析成(mailer,host,user)的形式，由邮件传输者、接收方主机和接收用户的名字组成。

规则集1：应用于消息中所有发送者地址。
规则集2：应用于消息中所有接收者地址。
规则集4：应用于消息中所有地址并将内部地址格式转化为外部地址格式。
下图说明了消息和地址通过这些规则集的流程(原书有误)：

+---+
-->+ 0 +---> resolved address
/ +---+
/
/ +---+ +---+
/ -->+ 1 +-->+ S +---
/ / +---+ +---+ \
+---+ / +---+ / \ +---+
addr --->+ 3 +---->+ D +--- --->| 4 +---> msg
+---+ +---+ \ / +---+
\ +---+ +---+ /
-->+ 2 +-->+ R +---
+---+ +---+
图中，D--sender domain addition
S--mailer-specific sender rewriting
R--mailer-specific recipient rewriting


Systems

经验点滴
LINUX命令
设备安装与卸载
#mount -t vfat /dev/hda1 /mnt/mswin 硬盘
#mount -t msdost /dev/fd0 /mnt/floppy 软盘
#mount -t iso8890 /dev/cdrom /mnt/cdrom 光驱
#umount /dev/hda1 ...卸载
制作启动盘
#mkbootdisk --device /dev/fd0 2.4.2-2 （2.4.2-2是你的LINUX发行版本号）
ADSL上网配置
#adsl-setup
#adsl-status
#adsl-start
#adsl-stop
网络状态查询
#netstat -nr
#ifconfig, #ifconfig eth0, ifconfig eth1,..., ifconfig ppp0
RPM软件安装，查询与卸载
#rpm -ivh xxx.rpm 安装
rpm -qa | grep xxx 查询
rpm -e xxx 卸载
.tar, .tgz, .gz, .tar.gz, .bz2 软件的安装卸载
# tar zxvf xxx.tar.gz (xxx.tar, xxx.tgz, xxx.gz, xxx.zip)
(#tar yxvf xxx.tar.bz2 - .bz2 文件)
(#bunzip2 xxx.bz2)
#./config --prefix=/installDir/
#make
#make install
#make clean , #make distclean
#make uninstall 或者 #./uninstall
#rm -rf /installDir/
了解解压路径
#tzvf *.tar.gz/.tgz 或 #tyvf *.bz2 (对于.bz2文件）
进程查询
ps -x
Redhat 7.1 完全安装(2772 MB)硬盘分配建议
/swap 2x RAM
/ 500 MB
/boot 50 MB
/usr 4 GB
/home 1 GB
/usr/local 4 GB
/var 1 GB
/opt 20 MB
/tmp 20 MB

Redhat 7.1自带主要软件包分配，安装路径与运行
Apache
包
  • apache
  • apacheconf
  • apache-devel
  • apache-manual
安装路径
  • /usr/sbin/httpd
  • /usr/bin/apacheconf
  • /etc/httpd/conf/httpd.conf, srm.cnf, access.cnf
  • /etc/httpd/logs/
  • /etc/httpd/modules/
  • /etc/init.d/htttpd
  • /usr/include/apache/
  • /usr/lib/apache/
  • /var/www/cgi-bin/
  • /var/log/httpd
  • /var/cache/httpd
命令
#httpd start | apachectl start |
#killall httpd
MySQL
包
  • mysql
  • mysql-devel
  • mysql-server
  • mysqlclient9
安装路径
  • /usr/bin/mysql, mysqladmin, mysqlshow, safe_mysqld ...
  • /usr/include/mysql/
  • /usr/lib/mysql/
  • /usr/libexec/mysql
  • /usr/share/mysql/mysql.server, my_large.cnf, my_huge.cnf, my_medium.cnf, my_small.cnf...
  • /var/lib/mysql/...
  • /etc/my.cnf
命令
  • #safe_mysqld --user=mysql &
  • #mysql.server start/stop/restart
  • #/usr/libexec/mysqld --user=root
  • #mysqladmin -u root -p shutdown ...
  • #mysqlshow ...
PHP
包
php
php-imap
php-ldap
php-mysql
php-pgsql
php-devel
php-manual
asp2php
asp2php-gtk
安装路径
  • /etc/php.ini
  • /usr/bin/php, php-config, phpextdist
  • phpize
  • /usr/include/php/ext,man, regex, Zend
  • /usr/lib/php4/
  • /usr/share/php/
命令
Perl
包
perl
perl-DBI
perl-DBD-MySQL
perl-DBD-Pg
perl-Perl-RPM
perl-File-MMagic
perl-Text-Kakasi
perl-SGMLSpm
perl-NKF
mod-perl
postgresql-perl
openssl-perl
gimp-perl
groff-perl
安装路径
  • /usr/bin/perl, perl5.6.0,perlbug,perlcc,perldoc
  • /usr/lib/perl5/5.6.0, man,site_perl, Tesxt
命令
Python
包
python
python-devel
python-xmlrpc
python-tools
pythonlib
python-docs
postgresql-python
rpm-python
openssl-python
mod_python
安装路径
  • /usr/bin --> pythn, python1.5
  • /usr/include/python1.5
  • /usr/lib/python1.5
命令
#python
Java
包
  • jikes
  • kaffe
安装路径
  • /usr/include/java
  • /usr/include/gnu/java
  • /usr/lib/linuxconf/java
命令
  • javac
  • java
  • javadoc
  • keytool

...
运行问题

jdk1.3的java运行出错

cannot load share object file:libjvm.so，参考sun的install，说要安装compat-libstdc6.21-2.9.0.0.i386.rpm
1。请问可以不装么？
2。这个文件在那里可以找到呢？我在rpmfind.net上只能找到compat-libstdc++-6 的版本，而这个rpm我已经安装了。

答：原来在RH7.1中，/usr/bin/cut被移到了/bin下，java的sh找不到这个程序，就出错了，可以用这个方法解决：
#ln -s /bin/cut /usr/bin/cut
环境变量设置
文件：
  • ~/.profile
  • ~/.bashrc
  • ~/.bash_profile
  • ~/.cshrc
  • ~/.tcshrc
  • /etc/profile
  • /etc/bashrc
  • /etc/csh.cshrc
  • /etc/shrc
  • /etc/zshenv
  • /etc/rc
  • /etc/rc.sysinit
  • ...
命令：
  • #CLASSPATH=
  • #export CLASSPATH
Java CLASSPATH 设置(profile):

JAVA_HOME="/usr/local/java/jdk1.3"
export JAVA_HOME

PATH="$PATH:/usr/local/sbin:/usr/sbin:/bin:/usr/local/java/jdk1.3/bin:/usr/local/java/jdk1.3/jre/bin:."

export PATH

CLASSPATH="/usr/local/java/jdk1.3/lib:/usr/local/java/jdk1.3/jre/lib:."
export CLASSPATH
LINUX资源
  • www.linuxbyte.net
  • www.linuxaid.com.cn
  • www.linuxforum.net
  • www.linux-ok.com
  • www.linuxeden.com
  • www.ChinaLinuxPub.com
  • www.eastlinux.com
  • http://linux.ccpi.gov.cn/linux/index.html
  • www.softhouse.com.cn
  • www.RedhatLinux.onchina.net
  • www.rpmfind.net/linux/RPM
  • www.netease.net/~con/
  • http://badfish.3322.net
  • http://netsword.net
  • http://pro.newsea.net
  • http://clyan.hongnet.com
最重要的公司
www.apache.org
www.w3d.org
www.sun.com, www.javasoft.com
www.xml.org
www.vrml.org
www.oracle.com
www.microsoft.com
www.ibm.com
www.bea.com
www.realnetworks.com
www.apple.com


Systems

Solar Software
Windpower Software
Online Calculation
TIPS
Our services | JAVA | XML | Tips
LINUX命令
设备安装与卸载
#mount -t vfat /dev/hda1 /mnt/mswin 硬盘
#mount -t msdost /dev/fd0 /mnt/floppy 软盘
#mount -t iso8890 /dev/cdrom /mnt/cdrom 光驱
#umount /dev/hda1 ...卸载
制作启动盘
#mkbootdisk --device /dev/fd0 2.4.2-2 （2.4.2-2是你的LINUX发行版本号）
ADSL上网配置
#adsl-setup
#adsl-status
#adsl-start
#adsl-stop
网络状态查询
#netstat -nr
#ifconfig, #ifconfig eth0, ifconfig eth1,..., ifconfig ppp0
RPM软件安装，查询与卸载
#rpm -ivh xxx.rpm 安装
rpm -q -a 查询
rpm -e xxx 卸载
.tar, .tgz, .gz, .tar.gz, .bz2 软件的安装卸载
# tar zxvf xxx.tar.gz (xxx.tar, xxx.tgz, xxx.gz, xxx.zip)
(#tar yxvf xxx.tar.bz2 - .bz2 文件)
(#bunzip2 xxx.bz2)
#./config --prefix=/installDir/
#make
#make install
#make clean , #make distclean
#make uninstall 或者 #./uninstall
#rm -rf /installDir/
了解解压路径
#tzvf *.tar.gz/.tgz 或 #tyvf *.bz2 (对于.bz2文件）
进程查询
ps -x
Redhat 7.1 完全安装(2772 MB)硬盘分配建议
/swap 2x RAM
/ 300 MB
/boot 50 MB
/usr >3 GB -->4 GB
/home >1 GB -->2 GB
/usr/local >200 MB -->1.5 GB
/var >700 MB -->3 GB
/opt 20 MB
/tmp 20 MB

Redhat 7.1自带主要软件包分配，安装路径与运行
Apache
包
  • apache
  • apacheconf
  • apache-devel
  • apache-manual
安装路径
  • /usr/sbin/httpd
  • /usr/bin/apacheconf
  • /etc/httpd/conf/httpd.conf, srm.cnf, access.cnf
  • /etc/httpd/logs/
  • /etc/httpd/modules/
  • /etc/init.d/htttpd
  • /usr/include/apache/
  • /usr/lib/apache/
  • /var/www/cgi-bin/
  • /var/log/httpd
  • /var/cache/httpd
命令
#https start
#killall httpd
MySQL
包
  • mysql
  • mysql-devel
  • mysql-server
  • mysqlclient9
安装路径
  • /usr/bin/mysql, mysqladmin, mysqlshow, safe_mysqld ...
  • /usr/include/mysql/
  • /usr/lib/mysql/
  • /usr/libexec/mysql
  • /usr/share/mysql/mysql.server, my_large.cnf, my_huge.cnf, my_medium.cnf, my_small.cnf...
  • /var/lib/mysql/...
  • /etc/my.cnf
命令
  • #safe_mysqld --user=mysql &
  • #mysql.server start/stop/restart
  • #/usr/libexec/mysqld --user=root
  • #mysqladmin -u root -p shutdown ...
  • #mysqlshow ...
PHP
包
php
php-imap
php-ldap
php-mysql
php-pgsql
php-devel
php-manual
asp2php
asp2php-gtk
安装路径
  • /etc/php.ini
  • /usr/bin/php, php-config, phpextdist
  • phpize
  • /usr/include/php/ext,man, regex, Zend
  • /usr/lib/php4/
  • /usr/share/php/
命令
Perl
包
perl
perl-DBI
perl-DBD-MySQL
perl-DBD-Pg
perl-Perl-RPM
perl-File-MMagic
perl-Text-Kakasi
perl-SGMLSpm
perl-NKF
mod-perl
postgresql-perl
openssl-perl
gimp-perl
groff-perl
安装路径
  • /usr/bin/perl, perl5.6.0,perlbug,perlcc,perldoc
  • /usr/lib/perl5/5.6.0, man,site_perl, Tesxt
命令
Python
包
python
python-devel
python-xmlrpc
python-tools
pythonlib
python-docs
postgresql-python
rpm-python
openssl-python
安装路径
命令
Java
包
安装路径
  • /usr/java/jdk1.3/
  • /usr/bin/jar,java,javac,javadoc,javakey,jikes,javap,jbc-applet,jbibtex,jdb,jed
  • /usr/share/kaffe/com.jar,kjc.jar,Klasses.jar,microsoft.jar,
    • pjava.jar,rmi.jar,servlet.jar,tools.jar
命令
LINUX系统命令
  • #CLASSPATH=
  • #export CLASSPATH
LINUX资源
  • www.linuxbyte.net
  • www.linuxaid.com.cn
  • www.linuxforum.net
  • www.linux-ok.com
  • www.linuxeden.com
  • www.ChinaLinuxPub.com
  • www.eastlinux.com
  • http://linux.ccpi.gov.cn/linux/index.html
  • www.softhouse.com.cn
  • www.RedhatLinux.onchina.net
  • www.rpmfind.net/linux/RPM
  • www.netease.net/~con/
  • http://badfish.3322.net
  • http://netsword.net
  • http://pro.newsea.net
  • http://clyan.hongnet.com
最重要的公司
www.apache.org
www.w3d.org
www.sun.com, www.javasoft.com
www.xml.org
www.vrml.org
www.oracle.com
www.microsoft.com
www.ibm.com
www.bea.com
www.realnetworks.com
www.apple.com


WINE
communicate between Linux and Winodws
more at http://www.codeweavers.com
Installation Instructions

Download the RPM and save it to a temporary directory

Verify the file size is matches the bytes specified above. If it does not, an error occured during the download and it will not install successfully.

Install the package

Using kpackage
· Double click on the rpm file from the file manager.

Manually
· From a console (logged in as root), type: rpm -i codeweavers-wine-20011108-5.i386.rpm

Configure Wine

KDE and Gnome
· From the System menu, choose the WineSetup option.

Manually
· From a console (remember to log out from root), type: winesetup

Run

KDE and GNOME File Managers - · Double click on the Windows program icon from the file manager.

Manually
· From a console prompt, type: wine <program-you-want-to-run> --wine notepad.exe

wine xxx or /../../xxx.exe
Right click - ///


Mainboard

主板

Mainboard
Motherboard
Mainboard design
Motherboard design

主板
主板设计

http://www.enet.com.cn/motherboard/

http://www.motherboards.org/

DEC Digital AXPpci 33 Alpha PC Motherboard OEMDesign Guide p98.pdf
GreenComputeZZZ ATOMSrv_MotheBoard_Spec_V10 Intel Atom主板硬件设计规范 p35.pdf
GuptaZZZ Lecture 14 Main Memory and Virtual Memory p7.pdf
ieeetc97.pdf
IntelZZZ Pentium Processor Flexible Motherboard Design Guidelines p56.pdf

Intel Embedded Pentium Processor with MMX Technology Flexible Motherboard Design Guidelines October 1998 p50

Intel Embedded Pentium Processor with MMX Technology Flexible Motherboard Design Guidelines p50.PDF

JohnZZZ MainMemory p11.pdf
LoongsonZZZ 3A_schematic design guide龙芯3A主板原理图设计指导 p31.pdf
MartinRothZZZ Introduction to Computer Architecture Unit 4 Memory Hierarchy II Main Memory p12.pdf
MSZZZ-6533G Micro ATX Mainboard p65.pdf
NgZZZ Design and Implementation of Reliable Main Memory p132.pdf
OlukotunZZZ Lecture 13 Main Memory and Virtual Memory p16.pdf
Open_Compute_ProjectZZZ_ARM_Server_Motherboard Design Specification_p13.pdf
SilberschatzZZZ ch8-Main_Memory-p11.pdf
SilberschatzZZZ Chapt_08_Memory management p29.pdf
SoltekZZZ Mainboard Series SL-85SD User Manual v10 p131.pdf
SOMUSteiZZZ AD11 MAINBOARD MANUAL p64.pdf
StallingsZZZ Computer Organization and Architecture p72.pdf
TEACZZZ DVD drive spec p33.pdf
TommyZZZ AM37 MAINBOARD MANUAL p54.pdf
WilkinsonZZZ Internal Structure of Computer p106.pdf
YoungZZZ How Computers Work Processor and Main Memory p158.pdf
ZZZch-05 Computer organization.ppt
ZZZChapter07 Memory Management.ppt
ZZZlec_15_MainMemory.ppt
ZZZMain-memory.ppt


os_intro

BhorZZZ Operating System p159.pdf
CobbautZZZ Linux Fundamentals p267.pdf
HoltZZZ WindowsXPUserGuide p27.pdf
Mam?enkoZZZ Operating systems p76.pdf
MatloffZZZ LinuxInstall p26.pdf
RadiSysZZZ IntroducingiRMX Operating Systems p126.pdf
RazaZZZ computing fundamentals p89.pdf
solarisZZZ-on-x86 p192.pdf
WaltonZZZ Computer-Fundamentals p126.pdf
ZZZComputer Fundamentals and Troubleshooting.pdf


shellbatch

000LaurieZZZ The Command Line in Windows p100.pdf
000ValdezZZZ Batch file programming p55.pdf
BARTLETTXXX A Practical Guide to Linux Commands Editors and Shell Programming p1081.pdf
BlumXXX Linux Command Line and Shell Scripting Bible p843.pdf
CatonmatZZZ 最牛B的 Linux Shell 命令 p22.pdf
COTTEVIEILLEZZZ Linux Shell Shell Scripting Basic level p15.pdf
GiteZZZ Linux Shell Scripting Tutorial v1 p46.pdf
GiteZZZ Linux Shell Scripting Tutorial v105 p182.pdf
GiteZZZ Linux Shell Scripting Tutorial v105r3 A Beginners handbook p273.pdf
GiteZZZ Linux Shell Scripting Tutorial v20 p301.pdf
MiloZZZ UNIX and Linux Administration and Shell Programming p261.pdf
ProffittZZZ Simple Windows Batch Scripting for Intrusion Discovery p35.pdf
SteebZZZ Linux Shell Programing and Perl p244.pdf
tigerZZZ Linux Shell 介绍 p40.pdf
VerityZZZ Practical Windows Command Line Basics for IT Auditing p55.pdf
ZZZBash Shell编程 p24.pdf
ZZZbash编程指南 p9.pdf
ZZZWindows Command Reference p42.pdf
ZZZWindows批处理高级教程精选合编 p52.pdf


utility programs

EasterZZZ CHP8 The Operating System and Utility Programs.PPT
GiffordZZZ Chapter8 Operating Systems and Utility Programs.ppt
TANENBAUMZZZ MODERN OPERATING SYSTEMS Chapter 10 Case Study 1 LINUX.ppt
ZZZ06 - Utility Programs.ppt
ZZZch08 Operating Systems and Utility Programs.ppt
ZZZChapter 7 Operating Systems and Utility Programs.pdf
ZZZChapter 8 Operating Systems and Utility Programs.pdf
ZZZChapter 8 Operating Systems and Utility Programs.ppt
ZZZChapter 8 Operating Systems and Utility Programs2.pdf
ZZZChapter 8 Operating Systems and Utility Programs3.pdf
ZZZChapter.05 System Software Operating Systems and Utility Programs.ppt


Cyber Security

Cracking/

000ARTeam脱壳教程全集/

ASProtect (Analysis of Hardware Breakpoint Clearing).rar
ASProtect 1.22-1.32 (Unpacking).rar
ASProtect 1.23 RC1 (Unpacking).rar
ASProtect 1.31 (Unpacking).rar
ASProtect 2.0 (Stolen Bytes).rar
ASProtect 2.0x (Unpacking & Rebuilding IAT).rar
ASProtect 2.13 (Unpacking + All Protections).rar
ASProtect 2.1x (Advanced Import Protection).rar
ASProtect 2.3 SKE (Bypass HardwareID Lock).rar
ASProtect 2.3 SKE (Virtual Memory Analysis).rar
ASProtect 2.4 SKE (OEP + Advanced Import Protection).rar
ASProtect 2.4 SKE (Stolen OEP).rar
ASProtect 2.xx (Attack on Activation Key).rar
ASProtect 2.xx (IAT Rebuilding + Stolen Code).rar
ASProtect 2.xx (Unpacking + All Protections).rar
ASProtect SKE 2.3 (OEP + Redirected Imports).rar
ASProtect SKE Unpacking Approach.rar

000Lena151Files/

Narvaja Introduction to Cracking with OllyDbg from Scratch PDF EN/

Ricardo_tus_56-57_eng.rar
Ricardo_tuts_1-42.rar
Ricardo_tuts_43-46_with_targets.rar
Ricardo_tuts_47-50_eng_inside pass ask in list.zip
parte 58 esen.rar
ricardo tuts 51-53.rar
ricardo tuts 54-55.rar

ODbgScript/

ODbgScript1831forOD110.txt

R4ndom逆向系列教程/

二进制代码DIY的艺术/
其他教程/
软件逆向工程入门教程/

ZZZChm/

NarvajaPediy 使用OllyDbg从零开始Cracking.CHM
OllyDBgPlugins.chm
Pediy看雪 OllyDBg入门教程.chm
Pediy看雪 软件破解技术学习1400篇破解技术.chm
fwnl 软件破解入门教程和解密常用手册.chm

ZZZPDF/

000Pediy看雪 OLLyDbg动态调试技术.pdf
000ccdebuger OllyDBG教程.pdf
CANZANESE A Survey of Reverse Engineering Tools for the 32-Bit Microsoft Windows Environment p25.pdf
Eilam Reversing Secrets of Reverse Engineering p620.pdf
Eilam Reversing Secrets of Reverse Engineering 逆向工程揭密 p621.pdf
Ferrie ANTI-UNPACKER TRICKS p25.pdf
Ferrie The_Ultimate_Anti-Reversing_Reference p154.pdf
Fulop Evaluating and improving reverse engineering tools p169.pdf
HanwenStudio 加密与破解行家一点通 p185.pdf
Lanza Object-Oriented Reverse Engineering p144.pdf
Lenus od内存断点寻找真正的入口(OEP) 内存断.pdf
Systa Static and dynamic reverse engineering p232.pdf
Trew Introduction to Reverse Engineering p36.pdf
Whittaker how_to_break_software.pdf
Whittaker 如何攻破软件 p10.pdf
Yason The art of unpacking p35.pdf
Yurichev Reverse Engineering for Beginners 逆向工程初学入门英文版 p634.pdf
reverse c++.pdf
菜鸟脱壳之脱壳的基础知识（六）手动查找IAT和修复Dump的程序.pdf

Hacking/

ZZZChm/

Zheng曾云好 精通脚本黑客chm无限制版.chm

ZZZExe/

Ada99 hackbook.exe
AdaSky VB黑客编程高手—30天打造黑客程序编写高手.exe
AdaSky 我是黑客我学黑安全篇.exe
AxureRP.exe

ZZZHtml/

Snort中文手册.htm

ZZZPDF/

Beaver Hacking for Dummies p411.pdf
Breaker 利用Metasploit进行渗透测试.pdf
Chen 黑客攻防300招 p380.pdf
Clarke SQL注入攻击与防御 p369.pdf
Collins Hardware Hacking p128.pdf
Cui 黑客攻击与防范技术 p150.pdf
David CAIN使用教程.pdf
Deng 黑客攻防实战入门 p438.pdf
Deng 黑客攻防实战编程 p375.pdf
Edgewave Comprehensive Web Security.pdf
Erickson Hacking The Art of Exploitation p495.pdf
Erickson Hacking the art of exploitation p492.pdf
Erickson 黑客之道 漏洞发掘的艺术 p200.pdf
Fadia Hacking Mobile Phones手机黑客攻防 p241.pdf
GLASGOW SCHOOL INSTALLS BLOXX WEB FILTERING TO COMBAT ANONYMOUS PROXIES.pdf
Graham 黑客与画家 p262.pdf
Grossman Cross-Site Scripting Worms & Viruses p18.pdf
HACKCTO-201312-12 p199.pdf
HackerDefence 黑客防线2015年第1期杂志.pdf
HackerDefence 黑客防线2015年第2期杂志.pdf
Hacking The Next Generation p298.pdf
Hao 黑客Web脚本攻击与防御技术核心剖析 p375.pdf
Hao 黑客远程控制服务攻击技术与安全搭建实战 p363.pdf
Hongyan鸿雁 同网关劫持与不同网关劫持实例.pdf
ISECOM Linux黑客大曝光Linux安全机密与解决方案 p599.pdf
Imperva Detecting and Blocking Site Scraping Attacks p8.pdf
Kaspersky 黑客反汇编揭秘 p462.pdf
Kaspersky 黑客反汇编解密 p536.pdf
Katoch Bypassing ASLR DEP p19.pdf
Kennedy Metasploit渗透测试指南 p313.pdf
Kuskos top-10-web-hacking-techniques-of-2014_final p54.pdf
Li 攻防实战技术完全手册 p351.pdf
LiYuanwang 黑客成长日记 p284.pdf
Lockhart 网络安全HACKS第二版保护隐私的技巧与工具 p464.pdf
Long Google Hacking for Penetration Testers p170.pdf
Luo 黑客攻防实战进阶 p394.pdf
MCCLURE HACKING EXPOSED 6 NETWORK SECURITY SECRETS SOLUTIONS黑客大曝光第六版 p720.pdf
MITNICK The Art of Deception欺骗的艺术 p570.pdf
Mimike秘密客 反追踪黑客指南 p255.pdf
NSFocus 黑客常见攻击技术及防御.pdf
Nmap参考指南(Man Page).pdf
Pan_潘志翔 黑客攻防编程解析 p243.pdf
Proxy_Abuse_Edu_0611.pdf
SANS Detecting and Preventing Anonymous Proxy Usage p49.pdf
Sanders Wireshark数据包分析实战 p279.pdf
Seitz Python灰帽子黑客与逆向工程师的Python编程之道 p209.pdf
ShenlongSun 新编黑客攻防从入门到精通神龙工作室 p389.pdf
Sikorski 恶意代码分析实战 p735.pdf
Silic SQL Injection Base p60.pdf
Singh Metasploit Penetration Testing Cookbook p269.pdf
Singh Metasploit渗透测试手册 p241.pdf
Skoudis 决战恶意代码 p496.pdf
SohuSogou XSS跨站脚本攻击及防范.pdf
Stallings 密码编码学与网络安全原理与实践 p510.pdf
Stuttard The Web Application Hackers Handbook p914.pdf
Stuttard 黑客攻防技术宝典Web实战篇第2版 p644.pdf
Tan谭术 远程控制与攻击技术揭秘 p256.pdf
Wang 走进计算机病毒 p451.pdf
Wang 走进计算机病毒 p457.pdf
Wiley Dust A Blocking-Resistant Internet Transport Protocol.pdf
Winter Measuring and circumventing p163.pdf
Wu 暗战强人黑客及反黑客工具快速精通 p420.pdf
Wu 暗战强人黑客攻防入门全程图解 p415.pdf
Wu 暗战强人黑客攻防实战高级演练 p455.pdf
Wu 黑客攻防实用技巧108招 p384.pdf
Xiao BurpSuite爆破密码.pdf
Xiao NmapMetasploit模拟渗透过程.pdf
Xiao 网站入侵与脚本攻防修炼 p579.pdf
Xu 网络渗透技术 p558.pdf
Yan 防守反击黑客攻击手段分析与防范 p282.pdf
Yang 别碰我的电脑黑客攻防与网络安全 p216.pdf
Yang 无线网络黑客攻防杨哲扫描版 p279.pdf
Yuan APT 高级漏洞利用技术 29.pdf
Yulinmufeng雨林木风 Burp Suite使用说明.pdf
Zabbix使用详解手册 中文版.pdf
Zhang 黑客主流攻击大全 p192.pdf
Zhang 黑客渗透笔记 p254.pdf
Zheng 精通脚本黑客 p751.pdf
colasoft 黑客攻防技术入门之ARP篇.pdf
hongygxiang 渗透那点事儿.pdf
kali-linux中文指南.pdf
netfairy 从零开始学习软件漏洞挖掘系列教程第一篇工欲善其事必先利其器.pdf
rookit msf内网渗透.pdf
shineast 内核漏洞挖掘技术.pdf
xiehb 网络攻防实验手册详细版.pdf
yueyan 渗透突破上传总结.pdf
新手学黑客攻防 p275.pdf
李芸 P2P流量识别与管控技术.pdf
灰帽攻击安全手册 渗透测试与漏洞分析技术.pdf
灰帽黑客_扫描版 p585.pdf
程绍银 恶意代码分析 p160.pdf
网络核心技术内幕网络攻击秘笈 p307.pdf
计算机叛客.pdf
黑客与反黑客.pdf
黑客入侵之原理篇.pdf
黑客入门全程图解 p298.pdf
黑客入门新手特训.pdf
黑客入门超级详细版.pdf

ZZZWord/

McKeague Detecting Anonymous Proxy Usage p100.docx
Wang王隆海 如何进行ARP攻击.doc
ZSS 入侵网站服务器的8种方法.docx
riusksk Perl黑客编程.doc
从零开始学习黑客技术入门教程(基础) p110.doc
黑客技术入门.doc

money/

Anunak_APT_against_financial_institutions.pdf

trojan/

Bourg Placeholder Trojan Writing a Malware Software.pdf
Detoisien Old win32 code for a modern super stealth trojan p43.pdf
Evron 僵尸网络_网络程序杀手 p303.pdf
Fuentes Trojan horses in mobile devices.pdf
Moffie Hunting Trojan Horses.pdf
Ren 网页木马攻防实战 p349.pdf
Skoudis Ch06 Trojan Horses.pdf
Wan 木马攻防全攻略 p354.pdf
Wang A Brief Study of Trojan.pdf
Wise Trojan Horse.ppt
木马查杀深度剖析 p63.pdf
木马病毒分析.pdf

worms/

Bajaj Source Code Analysis of Worms.pdf
Bhandarkar Internet Worms & Buffer Overflow Attacks p36.pdf
Bishop Computer Worms.pdf
COEN Malware Scanners, Sniffers, Viruses, Worms, Mobile Code p254.ppt
Cheng 计算机蠕虫病毒的解析与防范.pdf
Clement CHAPTER 9 Strategies of Computer Worms.pdf
Dabirsiaghi Building and Stopping Next Generation XSS Worms p18.pdf
Faghani Social Networks’ XSS Worms p5.pdf
Fosnock Computer Worms- Past, Present, and Future.pdf
Frederick A Formal Definition of Computer Worms and Some Related Results.pdf
Grossman Computer Worms p3.pdf
Hoffman Analysis of web application worms and viruses p61.pdf
Huang 基于元胞自动机的网络蠕虫病毒传播仿真.pdf
Kolesnikov Advanced Polymorphic Worms Evading IDS by Blending in with Normal Traffic.pdf
Livshits LEC11 WORMS AND SELF-PROPAGATING MALWARE p51.pdf
Methodology_AVER_Introspection_Trilogy_II.pdf
Nazario The Future of Internet Worms.pdf
Nellutla Classification of Different Computer Worms with Dynamic Detection Using Victim Number Based Algorithm.pdf
Nicholas A Taxonomy of Computer Worms.pdf
Qiu 流行蠕虫病毒的防治和快速反应机制 p11.ppt
Rajesh A Survey Paper on Malicious Computer Worms.pdf
SANS Internet Worms Walking on Unstable Ground.pdf
SAUDI A NEW MODEL FOR WORM DETECTION AND RESPONSE 2011 p232.pdf
Sans Beating the Superbug Recent Developments in Worms and Viruses p25.pdf
Shahin Polymorphic Worms Collection in Cloud Computing.pdf
Sharma WORMS attacks, defense and models.pdf
Singh A PHYSIOLOGICAL DECOMPOSITION OF VIRUS AND WORM PROGRAMS p89.pdf
Siraj Web Application Worms p28.pdf
Smith Computer Worms Architectures, Evasion Strategies, and Detection Mechanisms.pdf
Srinivasulu Discrete Mathematical Model of Computer Worm Propagation.pdf
To Internet Worms Methods, Countermeasures and Famous Incidents.ppt
Viruses Trojans and Worms p17.PDF
Worms p46.pdf
Yu Laboratory 9 Virus and Worm Propagation in Networks.pdf
Zhang 蠕虫病毒的传播机制研究.pdf
卿斯汉 即时通信蠕虫研究与发展.pdf
文伟平 网络蠕虫研究与进展.pdf

Writing/

Resources.doc
Resources1.doc

Cracking/

Cracking1.docx
Cracking2脱壳.docx
Cracking3脱壳.docx
Cracking4.docx
Cracking_old.docx
PETools.doc
PETools1.doc

Hacking/

HackerAnonym.docx
HackerGroups.docx
Hacking1.docx
Hackinghowto.docx

objects/

Hackingtarget.docx
air/
car/
物联网.docx

tech/

Hackingtech.docx
botnets僵尸网络/

tools/

HackingTools.docx

viruses/

virus.docx
trojan/
worms

CryptoSecurity/

BrowserSecure.doc
China.doc
CryptoChina.doc
CryptoScience.doc
CryptoScience1.doc
CryptoWorld.doc
Keywords.doc
Keywords1.doc
Liberty1.doc
Liberty2.doc
Liberty3.doc
Liberty4.doc
MessFTPetc.doc
Platforms.doc
Platforms1.doc
Privacy1SettingsOrigin.doc
Privacy1SettingsOrigin2.doc
Privacy2UTM_ADS_IDS_IPS.doc
Privacy2UTM_ADS_IDS_IPS1.doc
Privacy3FirewallVirusARPMon.doc
Privacy3FirewallVirusARPMon1.doc
Protocols.doc
Protocols1.doc
ProxySoftVPN.doc
SSHFreeAccount.doc
SSHFreeAccount2.doc
SSHSetting.doc
TOC.doc
TOC1.doc
Tips.docx
Tips1.docx
Unblock1.docx
Unblock2.docx
UnblockIntro1.docx
UnblockIntro2.docx
UnblockSoft.docx
UnblockSoftP2P.docx
VPN.doc
VPNOld.doc
proxy.docx
riffle.pdf

anonp2p_literature/

anonp2p.htm

anonp2p_ref.htm

Aberer The essence of P2P A reference architecture for overlay networks p10.pdf
Amoretti A Survey of Peer-to-Peer Overlay Schemes Effectiveness, Efficiency and Security p19.pdf
Angskun Binomial Graph A Scalable and Fault-Tolerant Logical Network Topology p12.pdf
Bauer Low-Resource Routing Attacks Against Tor p10.pdf
Beaumont VoroNet A scalable object network based on Voronoi tessellations p10.pdf
Behnel A Specification-to-Deployment Architecture for Overlay Networks p19.pdf
Blanc Designing Incentives for Peer-to-Peer Routing p12.pdf
Borisov Anonymity in Structured Peer-to-Peer Networks p16.pdf
Borisov Anonymous Routing in Structured Peer-to-Peer Overlays p130.pdf
Boutaba Peer-to-Peer Networking p127.ppt
Bredereck The complexity of finding a large subgraph under anonymity constraints p11.pdf
Buford P2P Overlay Design Overview p21.pdf
COPACI THE DESIGN OF RESILIENCE P2P NETWORKS WITH DISTRIBUTED HASH TABLES p6.pdf
Chang Peer-to-Peer Anonymous Networking Using Coding p8.pdf
Chen HORNET High-speed Onion Routing at the Network Layer.pdf
Ciaccio Improving Sender Anonymity in a Structured Overlay with Imprecise Routing p18.pdf
Cutillo Analysis of Privacy in Online Social Networks from the Graph Theory Perspective p5.pdf
El-Ansary Designs and Analyses in Structured Peer-to-Peer Systems p229.pdf
EvansGrothoff2007 Routing in the Dark Pitch Black p15.pdf
Fessi Resilient Application Layer Signaling based on Supervised Peer-to-Peer (P2P) Networks p196.pdf
Fletcher Unstructured Peer-to-Peer Networks Topological Properties and Search Performance p14.pdf
Freedman2002 Tarzan A Peer-to-Peer Anonymizing Network Layer p14.pdf
GIRD Designing Peer-to-Peer Overlays a Small-World Perspective p142.pdf
Goodrich The Rainbow Skip Graph A Fault-Tolerant Constant-Degree Distributed Data Structure p12.pdf
Gupta PEER-TO-PEER NETWORKS AND COMPUTATION CURRENT TRENDS AND FUTURE PERSPECTIVES p36.pdf
Hadaller Necessity of Supernodes Survey p16.pdf
He On the Reliability of Large-Scale Distributed Systems - A Topological View p8.pdf
Khambatti PEER-TO-PEER COMMUNITIES ARCHITECTURE, INFORMATION AND TRUST MANAGEMENT p134.pdf
Kiraly Some Performance and Design Aspects of Overlay Networks p130.pdf
Kong An Identity-free and On Demand Routing Scheme against Anonymity Threats in Mobile Ad-hoc Networks p35.pdf
Kong Formal Notions of Anonymity for Peer-to-peer Networks p20.pdf
Korzun A Diophantine Model of Routes in Structured P2P Overlays p11.pdf
Korzun Local and Global Models for Large-Scale Peer-to-Peer Systems p14.pdf
Krishna Protecting Anonymity in Dynamic Peer-to-Peer Networks p10.pdf
Le A Structured Peer-to-peer System with Integrated Index and Storage Load Balancing p12.pdf
Leong Amorpheus A Proposal for a Self-Organizing Peer-to-Peer Overlay Routing Network p15.pdf
Li Graph-Theoretic Analysis of Kautz Topology and DHT Schemes p8.pdf
Liu Towards Identity Anonymization on Graphs p14.pdf
Locher eQuus A Provably Robust and Locality-Aware Peer-to-Peer System p9.pdf
Loguinov Analysis of Peer-to-Peer Systems A Graph- Theoretic Answer to the Diameter-Degree Tradeoff p14.pdf
Loguinov Graph Graph-Theoretic Analysis of Structured Peer Peer-to to-Peer Systems Routing Distances and Fault Resilience p30.pdf
Loguinov Graph-Theoretic Analysis of Structured Peer-to-Peer Systems Routing Distances and Fault Resilience p12.pdf
Loguinov2003 Graph-theoretic analysis of structured peer-to-peer systems routing distances and fault resilience p14.pdf
Lua A Survey and Comparison of Peer-to-Peer Overlay Network Schemes p22.pdf
Lupu Generic Peer-to-Peer Networks Theory, Implementation and Applications in Image Retrieval Using the Wavelet Transform p176.pdf
Margasiński2008 Anonymous Transport in Peer-to-Peer Overlay Networks p112.pdf
Mittal Preserving Link Privacy in Social Network Based Systems p19.pdf
Mittal ShadowWalker Peer-to-peer Anonymous Communication Using Redundant Structured Topologies p12.pdf
Mohaisen Dynamix Anonymity on Dynamic Social Structures p6.pdf
Nagaraja Anonymity in the wild Mixes on unstructured networks p21.pdf
NegrinAcosta IMPROVING SEARCH IN UNSTRUCTURED PEER-TO-PEER SYSTEMS p86.pdf
Niedermayer Architecture and Components of secure and anonymous Peer-to-Peer Systems p188.pdf
Nobari L-opacity Linkage-Aware Graph Anonymization p12.pdf
Ober Structure and Anonymity of the Bitcoin Transaction Graph p14.pdf
PARK A NEW SOLUTION OF PEER-TO-PEER ANONYMOUS COMMUNICATION p44.pdf
Peer to Peer (P2P) Networking p11.pdf
Qu Cayley DHTs —A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs p13.pdf
Rogers An Adaptive Routing Protocol for Censorship-Resistant Communication p10.pdf
Rogers Private and Censorship-Resistant Communication over Public Networks p132.pdf
SUNG A Survey of Data Management in Peer-to-Peer Systems p50.pdf
Schiller Seminar P2P Selected Topics in P2P Research p28.pdf
Shen Scalable and Secure P2P Overlay Networks p41.pdf
Sirer Eluding Carnivores File Sharing with Strong Anonymity p6.pdf
Skogh Fast Freenet Improving Freenet Performance by Preferential Partition Routing and File Mesh Propagation p8.pdf
Spirakis Dynamic Networks Foundations p95.pdf
Staab Semantic Web and Peer-to-Peer p359.pdf
Tang Group Routing A Reliable mutual anonymous approach in Dynamic Overlay p6.pdf
Tian Hybrid Overlay Structure Based on Random Walks p11.pdf
Wallach A Survey of Peer-to-Peer Security Issues p16.pdf
Wang Peer-to-Peer Overlay Networks A Survey p12.pdf
Wepiwe HiPeer An Evolutionary Approach to P2P Systems p196.pdf
Xiao CayleyCCC A Robust P2P Overlay Network with Simple Routing and Small-World Features p7.pdf
Yu A Graph Theoretic Approach to Ultrafast Information Distribution Borel Cayley Graph Resizing Algorithm p25.pdf
Zeng Optimal Routing in a Small-World Network p14.pdf
Zhou2013 SGor Trust graph based onion routing p23.pdf
qiyan Octopus Anonymous and Secure DHT Lookup p20 .pdf


anon p2p

point (p2p)

2015-2-18

Establish a point to point (p2p) mobile communications system to bypass the central control systems and censoring.


anon p2p literature

Graph Theory and Online Anonymity

'The Net interprets censorship as damage and routes around it'

Internet pioneer John Gilmore

Elmer-DeWitt P. (1993), ‘First nation in cyberspace’, Time, 142(24).

Peer to Peer (P2P) Networking

http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.154.7801

http://www.disi.unige.it/project/neblo/intro.html

http://www.sciencedirect.com/science/article/pii/S1877050913002433

http://ntrg.cs.tcd.ie/undergrad/4ba2.05/group6/

https://books.google.com/books?id=p1i3vR-BYfEC&pg=PA203&lpg=PA203&dq=Anonymous+routing+in+structured+peer-to-peer+overlays&source=bl&ots=f--LWkM8_U&sig=ho8DnBp15KuzAo6DtG47Wh9cRUk&hl=zh-CN&sa=X&ei=CsdRVez0MKLGmQX8zIHIBA&ved=0CEgQ6AEwBTge

https://www.cs.cmu.edu/~chongw/citeulike/docs/doc1359.html

https://www.ideals.illinois.edu/bitstream/handle/2142/28593/octopus_tr.pdf?sequence=3

http://www.peerevaluation.org/read/libraryID:15596

http://www.inf.u-szeged.hu/~jelasity/p2p/

http://people.eng.unimelb.edu.au/aharwood/P2PWWW/

http://scholarsmine.mst.edu/cgi/viewcontent.cgi?article=8314&context=masters_theses

http://www.dmst.aueb.gr/dds/pubs/jrnl/2004-ACMCS-p2p/html/AS04.html

http://ijns.femto.com.tw/contents/ijns-v6-n2/ijns-2008-v6-n2-p201-210.pdf

Amoretti A Survey of Peer-to-Peer Overlay Schemes: Effectiveness, Efficiency and Security p19

Michele Amoretti

Anonymous Routing in the Dark: Pitch Black
Anonymous

ZZZZZZZZZZ

[Bauer2007] Low-Resource Routing Attacks Against Tor p10

Kevin Bauer? Damon McCoy? Dirk Grunwald? Tadayoshi Kohno? Douglas Sicker?
? Department of Computer Science ? Department of Computer Science and Engineering
University of Colorado University of Washington
Boulder, CO 80309-0430 USA Seattle, WA 98195-2969 USA
{bauerk, mccoyd, grunwald, sicker}@colorado.edu yoshi@cs.washington.edu

Berthold The disadvantages of free MIX routes and how to overcome them. In H. Federrath, editor, Proceedings of Designing Privacy Enhancing Technologies: Workshop on Design Issues in Anonymity and Unobservability, pages 30–45. Springer- Verlag, LNCS 2009, July 2000.

Oliver Berthold, Andreas Pfitzmann, and Ronny Standtke.

ZZZZZZZZZZ

[Blanc2004] Designing Incentives for Peer-to-Peer Routing p12

Alberto Blanc1, Yi-Kai Liu2, Amin Vahdat3
1Electrical and Computer Engineering Dept.
2,3Computer Science and Engineering Dept.
University of California, San Diego

1E-mail: alberto@cwc.ucsd.edu.
2E-mail: y9liu@cs.ucsd.edu. Supported by the National Security
Agency (NSA) and Advanced Research and Development Activity (ARDA)
under Army Research Office (ARO) Grant No. DAAD19-01-1-0520.
3E-mail: vahdat@cs.ucsd.edu. Supported by NSF grant ITR-
0082912, NSF CAREER award CCR-9984-328, Hewlett-Packard, IBM, Intel
and Microsoft.

complete bipartite graph

Borisov Anonymity in Structured Peer-to-Peer Networks p16
Nikita Borisov

Borisov Anonymity in Structured Peer-to-Peer Networks p16
?????????????

Borisov. Phd thesis: Anonymous routing in structured peer-to-peer overlays, April 2005.
Nikita Borisov.

Boutaba Peer-to-Peer Networking p127

Dr. Raouf Boutaba, Dr. Keith W. Ross, and Dr. Dan Rubenstein

Bredereck The complexity of finding a large subgraph under anonymity constraints p11

Robert Bredereck1?, Sepp Hartung1, Andre Nichterlein1, and
Gerhard J. Woeginger2??

A. Broder, R. Kumar, F. Maghoul, P. Raghavan, S. Rajagopalan, R. Stat, A. Tomkins, and J. Wiener, “Graph structure in the web,” in Processings of the 9th Int. WWW Conference, Amsterdam, May 15-19 2000.

Boutaba Peer-to-Peer Networking p127

[Buford2005] P2P Overlay Design Overview p21

John Buford, Panasonic Digital Networking Laboratory
IRTF P2P RG Core Subgroup
buford@research.panasonic.com
Keith Ross, Polytechnic University
ross@poly.edu
Presented at IETF P2P-SIP ad hoc November 2005
Updated Dec 2005
Graph embedding

Chang Peer-to-Peer Anonymous Networking Using Coding p8

Christopher S. Chang

David Chaum. Untraceable electronic mail, return addresses, and digital pseudonyms. Communications of the ACM, 4(2), February 1981.

Ian Clarke, Oskar Sandberg, Brandon Wiley, and Theodore Hong. Freenet: A distributed anonymous information storage and retrieval system. In Proceedings of Designing Privacy Enhancing Technologies: Workshop on Design Issues in Anonymity and Unobservability, pages 46–66, July 2000.

ZZZZZZZZZZZ

[Cutillo2007] Analysis of Privacy in Online Social Networks from the Graph Theory Perspective p5

Leucio Antonio Cutillo, Refik Molva, Melek O¨ nen
EURECOM
Sophia-Antipolis, France

social graph

social network graph

graph metrics

node degree

clustering coefficient

mixing time

Random walks in a graph
George Danezis. Mix-networks with restricted routes. In Roger Dingledine, editor, Proceedings of Privacy Enhancing Technologies workshop (PET 2003). Springer-Verlag, LNCS 2760, March 2003.
George Danezis, Roger Dingledine, and Nick Mathewson. Mixminion: Design of a type iii anonymous remailer protocol. In IEEE Symposium on Security and Privacy, pages 2–15, 2003.
Roger Dingledine, Nick Mathewson, and Paul Syverson. Tor: The second generation onion router. In Proceedings of the 13th USENIX Security Symposium, August 2004.

El-Ansary Designs and Analyses in Structured Peer-to-Peer Systems p229
XXXXXXXXXXX

[EvansGrothoff2007] Routing in the Dark: Pitch Black p15

connected graph

Fletcher Unstructured Peer-to-Peer Networks Topological Properties and Search Performance p14
ZZZZZZZZZZZZ

[Freedman2002] Tarzan: A Peer-to-Peer Anonymizing Network Layer p14

Michael J. Freedman
NYU Dept of Computer Science
715 Broadway #715
New York, NY 10003 USA
mfreed@cs.nyu.edu
Robert Morris
MIT Lab for Computer Science
200 Technology Sq. #509
Cambridge, MA 02139 USA
rtm@lcs.mit.edu

Chaumian mix

Internet anonymization

Zero-Knowledge’s Freedom [13]

GIRD Designing Peer-to-Peer Overlays a Small-World Perspective p142 ?????????????????

Gupta PEER-TO-PEER NETWORKS AND COMPUTATION: CURRENT TRENDS AND FUTURE PERSPECTIVES p36 ????????????????

Ankur Gupta
ZZZZZZZZZZZZ

[He2007] On the Reliability of Large-Scale Distributed Systems - A Topological View p8

1Yuan He, 2Hao Ren, 1Yunhao Liu, and 3Baijian Yang
1Hong Kong University of Science
and Technology
{heyuan, liu}@cse.ust.hk
2National University of Defense
Technology
renhao1973@gmail.com
3Ball State University,
U.S.A.
byang@bsu.edu

undirected graph

Khambatti PEER-TO-PEER COMMUNITIES ARCHITECTURE, INFORMATION AND TRUST MANAGEMENT p134 ???????????????

Kiraly Some Performance and Design Aspects of Overlay Networks p130 ?????????????

Ph.D. Thesis
by
Csaba Kiraly
T. Klingberg and R. Manfredi. ”gnutella 0.6”, June 2002.
ZZZZZZZZZZZ

[Kong2005] An Identity-free and On Demand Routing Scheme against Anonymity Threats in Mobile Ad-hoc Networks p35

Jiejun Kong? Xiaoyan Hong? Mario Gerla?
?Scalable Network Technologies, Inc. ?Dept. of Computer Science ?Dept. of Computer Science
6701 Center Drive West, Suite 520 University of Alabama University of California
Los Angeles, CA 90045 Tuscaloosa, AL 35487 Los Angeles, CA 90095
jkong@scalable-networks.com, hxy@cs.ua.edu, gerla@cs.ucla.edu
Kong Formal Notions of Anonymity for Peer-to-peer Networks p20
Jiejun Kong
stationary graph
ZZZZZZZZZZ
[Krishna2008] Protecting Anonymity in Dynamic Peer-to-Peer Networks p10

Krishna P. N. Puttaswamy, Alessandra Sala, Christo Wilson, Ben Y. Zhao
Computer Science Department, University of California at Santa Barbara
{krishnap, alessandra, bowlin, ravenben}@cs.ucsb.edu

Bluemoon graphs

[Leong2001] Amorpheus: A Proposal for a Self-Organizing Peer-to-Peer Overlay Routing Network p15

Ben Leong
benleong@mit.edu

triangulated planar graph

triangulation graph

planar graph

Li Anonymizing Graphs Against Weight-based Attacks with Community Preservation

DOI : 0.5626/JCSE.2011.5.3.197

Li Yidong, Shen Hong Li Yidong; Shen Hong Journal of Computing Science and Engineering Volume 5, Issue3, p197~209, 30 June 2011

http://central.oak.go.kr/journallist/journaldetail.do?article_seq=10856&tabname=abst&resource_seq=-1&keywords=null

L. Li, D. Alderson, R. Tanaka, J. C. Doyle, and W. Willinger, “Towards a Theory of Scale-Free Graphs: Definition, Properties, and Implications
(Extended Version),” Oct. 2005.

ZZZZZZZZZZ

[Liu2008] Towards Identity Anonymization on Graphs p14

Kun Liu
IBM Almaden Research Center
San Jose, CA 95120, USA
kun@us.ibm.com
Evimaria Terzi
IBM Almaden Research Center
San Jose, CA 95120, USA
eterzi@us.ibm.com

graph-anonymization problem

graph k-degree anonymous

set of restricted graph isomorphism problems

graph satisfies k-candidate anonymity

email communication graph

identity anonymization on graphs

graph-anonymization framework

k-degree anonymous graph G
ZZZZZZZZZZZZZ
[Locher2005] eQuus: A Provably Robust and Locality-Aware Peer-to-Peer System p9

Thomas Locher, Stefan Schmid, Roger Wattenhofer
{lochert, schmiste, wattenhofer}@tik.ee.ethz.ch
Computer Engineering and Networks Laboratory (TIK), ETH Zurich, 8092 Zurich, Switzerland

complete graph

!!!!!!!!!!!!!!!!!!!!!

[Loguinov2003] Graph-theoretic analysis of structured peer-to-peer systems: routing distances and fault resilience p14

D. Loguinov, A. Kumar, and S. Ganesh, “Graph-theoretic analysis of structured peer-to-peer systems: routing distances and fault resilience,” in Proceedings of the ACM SIGCOMM, Karlsruhe, Germany, August 25-29 2003, pp. 395–406.
D. Loguinov, A. Kumar, and S. Ganesh, “Graph-theoretic analysis of structured peer-to-peer systems: routing distances and fault resilience,” in Proceedings of the ACM SIGCOMM, Karlsruhe, Germany, August 25-29 2003, pp. 395–406.

optimal-diameter de Bruijn graphs

de Bruijn graphs

  • short average routing distances
  • high resilience to node failure

structured peer-to-peer networks

Chord

CAN

routing performance

graph expansion

clustering properties

bisection width,

path overlap

connectivity

application-layer overlays

star-like trees centralized approaches such as

  • Napster

complex k-node-connected graphs(such as

  • Chord
  • CAN
  • Pastry

???whether there existed fixed-degree graphs with ￡(logN) diameter was believed to be the fundamental question of peer-to-peer research [35], [46].

Thus, the main goal of this work is to find a fixed-degree graph with not only provably minimum diameter, but also maximum connectivity (i.e., fault resilience) among all such graphs.

peer-to-peer graphs

distributed hash tables (DHTs)

prefix-based routin

Tapestry [47]

Bayeux [18], [48]

generalized hypercubes (Pastry)

k-regular graph of diameter logb N and node degree (b ? 1) logb N; b ? 2

Content-Addressable Network (CAN)

d-dimensional Cartesian spac

distributed graph called Chord

digraph (directed graph) of fixed degree

application-layer graph

distributed tries

multicast tree

Censorship Resistant Network

ring-based graphs (such as Chord)

Random Graphs

random DHT graph

random expander graphs

Optimal-Diameter Graphs

Directed de Bruijn graphs

Moore graph

static butterfly graph

Viceroy [27]

Ulysses

k-ary trie

distributed de Bruijn graphs

p4
ZZZZZZZZZZ

[Lua2004] A Survey and Comparison of Peer-to-Peer Overlay Network Schemes p22

Eng Keong Lua

de Bruijn graph [48]

N. D. de Bruijn, “A combinatorial problem,” Koninklijke Netherlands: Academe Van Wetenschappen, vol. 49, pp. 758–764, 1946.

random graph

power-law random graphs

graph expansion and clustering

PEER-TO-PEER (P2P) overlay networks

Distributed Hash Table (DHT)

Napster

selfscaling

Gnutella

Unstructured P2P overlay network

p3

Lupu Generic Peer-to-Peer Networks Theory, Implementation and Applications in Image Retrieval Using the Wavelet Transform p176???????????????/
ZZZZZZZZ

[Margasiński2008] Anonymous Transport in Peer-to-Peer Overlay Networks p112 ?????????????

Igor Margasiński, M.Sc. Eng.

Hypercube graphs

NegrinAcosta IMPROVING SEARCH IN UNSTRUCTURED PEER-TO-PEER SYSTEMS p86 ????????????/

!!!!!!!!!!!!!!!!!!

[Niedermayer2010] Architecture and Components of secure and anonymous Peer-to-Peer Systems p188 ??????????

Heiko Niedermayer

graph embedding

random graph

Butterfly graphs

DeBruijn graphs

Small-World graph

social graph

bootstrap graph

network graph

graph of the Web-of-Trust

trust graph

Mittal Preserving Link Privacy in Social Network Based Systems p19

Prateek Mittal
University of California,
Berkeley
pmittal@eecs.berkeley.edu
Charalampos Papamanthou
University of California,
Berkeley
cpap@eecs.berkeley.edu
Dawn Song
University of California,
Berkeley
dawnsong@cs.berkeley.edu

ZZZZZZZZZZ

[Mittal2009] ShadowWalker: Peer-to-peer Anonymous Communication Using Redundant Structured Topologies p12

Prateek Mittal
Department of Electrical and Computer
Engineering
University of Illinois at Urbana-Champaign
mittal2@illinois.edu
Nikita Borisov
Department of Electrical and Computer
Engineering
University of Illinois at Urbana-Champaign
nikita@illinois.edu
social graph

Mohaisen Dynamix: Anonymity on Dynamic Social Structures p6

Abedelaziz Mohaisen
Verisign Labs, VA, USA
Yongdae Kim
KAIST, Daejeon, South Korea

A. Mohaisen, A. Yun, and Y. Kim, “Measuring the mixing time of social graphs,” 10th USENIX/ACM SIGCOMM Internet Measurement Conference (IMC’10), 2010.

ZZZZZZ

[Nagaraja2007] Anonymity in the wild: Mixes on unstructured networks p21

Shishir Nagaraja

4

Statistical mechanics of complex networks

random graph model for massive graphs

Anonymous routing in structured peer-to-peer overlays

MIX routes

Freenet

Anonymity

Unobservability

Mix-networks with restricted routes

Mixminion

type iii anonymous remailer protocol

Tor: The second generation onion router

key-management scheme for distributed sensor networks

random graphs

random walks on expander graphs

gnutella

scientific collaboration networks

Mixing patterns in networks

pseudonymit

================

decentralized computing

unstructured topologies

mix networks

mix network topologies

unstructured network

social networks

scale-free random networks

LiveJournal friendship network topology

mix-route lengths

expander graphs

anonymization properties

expander graph topologies

onion routing:

low-latency or real time systems primarily for Internet browsing such as onion routing [STRL00]

onion-routing systems such as TOR [DMS04]

complete graph topology

regular graphs

mixminion:

high-latency or non-real time systems such as mixminion [DDM03].

mix network

structured network topologies based on regular graphs.

optimal expansion properties

spectral graph theory

expander graph topologies

De Bruijn graph topology overlay network

deBruijn graph topology

Erdos-Renyi model of random networks

Bernoulli trial

Scale-free networks

heavy tail distribution

A variable X is said to follow a heavy tail distribution if Pr[X > x]  x?k L(x) where k 2 <+ and L(x) is a slowly varying function so that limx!1 L(tx)
L(x) ! 1.

A power-law distribution

is simply a variation of the above where one studies Pr[X = x]  x?(k+1) = x? .

If the degree distribution of a network follows a power-law distribution it is known as a scale-free network

Scale-free random graph topology

massive AT&T call graphs

Klienberg-Watts-Strogatz(KWS) small world topology

‘small-world’ phenomenon.

It is well known that any two people are linked by a chain of half a dozen others who are pairwise acquainted – known as the ‘small-world’ phenomenon.This idea was popularised by Milgram in the 60s [Mil67].

LiveJournal (LJ)

Using a web crawler called touchgraph
(http://www.touchgraph.com)

Expander graphs

“anonymity”

Danezis [SD02], based on the following definition: “Anonymity of a system may be defined as the amount of information the attacker is missing to uniquely identify an actor’s link to an action”.

message receiver anonymity [SD02]:

given a message, the attacker should not be able to determine who sent it to whom, leading to both sender and receiver
anonymity requirements.

Sender anonymity

is determined by the probability that a specific node is the originator of a given message.

Receiver anonymity

also an important requirement in a number real world situations, is the probability that a specific node is the recipient of a given message whose sender is known.

The objective of our analysis is to determine how the topology of a mix network affects the amount of effort on the attacker’s part to uniquely identify communication endpoints using traffic analysis attacks alone.

use Markov chains to model the route selection process

model the route selection process as a random walk on the underlying graph, with the various states of the Markov chain process being the mix nodes of the network.

Markovian random walk

spectral theory of graphs

chernoff bounds

assortativity

intersection attacks

linear preferential attachment

scale-free networks

scale-free random networks

scale-free degree sequence

Klienberg-Watts-Strogatz model of directed social network

ER graph

The ER graph is created with each edge formation as the result of a Poisson distribution of p = 0.0028 with hdi = 14.

constant expander graph

The constant expander graph is created with each node having D = 14 edges.

transition matrix of a constant expander graph

graph sparsity

LiveJournal graph

scale-free random graph topology

KWS topology

expander graph topology

ZZZZZZZZZZ

[Nobari2014] L-opacity: Linkage-Aware Graph Anonymization p12

Sadegh Nobari{ Panagiotis Karrasx HweeHwa Pang{ Stéphane Bressany
{SMU School of Information Systems
Singapore
xRutgers Business School
USA
yNUS School of Computing
Singapore
ZZZZZZZZZZZZ

[Ober2013] Structure and Anonymity of the Bitcoin Transaction Graph p14

Micha Ober 1;2, Stefan Katzenbeisser 1;* and Kay Hamacher 1;2;3;*

Future Internet 2013, 5, 237-250; doi:10.3390/fi5020237

2
ZZZZZZZZZZZ

[PARK2012] A NEW SOLUTION OF PEER-TO-PEER ANONYMOUS COMMUNICATION p44

YANGBAE PARK
Andreas Pfitzmann and Marit Hansen. Anonymity, unobservability, and pseudonymity: A consolidated proposal for terminology. Draft, July 2000.
Matei Ripeanu, Ian Foster, and Adriana Iamnitchi. ”mapping the gnutella network: Properties of large-scale peer-to-peer systems and implications for system design”. IEEE Internet Computing Journal, 6(1), August 2002.
Michael G. Reed, Paul F. Syverson, and David M. Goldschlag. Anonymous connections and onion routing. IEEE Journal on Selected Areas in Communications, 16(4), 1998.
ZZZZZZZZZZZZ

[Rogers2007] An Adaptive Routing Protocol for Censorship-Resistant Communication p10

Michael Rogers

Michael Rogers
University College London, UK
m.rogers@cs.ucl.ac.uk
Saleem Bhatti
University of St Andrews, UK
saleem@cs.st-andrews.ac.uk

peer-to-peer overlays

mobile ad hoc networks

decentralised, adaptive routing protoco

unforgeable acknowledgements (U-ACKs)

dependable routes

ensorship-resistant communication

Erdos-Renyi random graphs

scale-free graphs

Q-routing [4]

AntNet [10]

AntHocNet [11]

MUTE file sharing network [20]

Rogers Private and Censorship-Resistant Communication over Public Networks p132 ???????????

Michael John Rogers
ZZZZZZZZZZZ

[Schiller2011] "Seminar P2P" & "Selected Topics in P2P Research" p28

Seminar Topics
Benjamin Schiller, P2P Networks Group, TU Darmstadt
April 14, 2011

onion routing, VPNs, or proxies

Anonymous Friend-to-Friend (F2F) Networks

Graph Drawing Algorithms

virtualization of a graph

embedding a graph in the 2-dimensional plan

structured P2P networks like, e.g., Chord or Kademlia

unstructured P2P networks like, e.g., Gnutella version 0.4 or Freenet

tracker-based systems like, e.g., BitTorrent or Tribler
Andrei Serjantov and George Danezis. Towards an information theoretic metric for anonymity. In Paul Syverson and Roger Dingledine, editors, Privacy Enhancing Technologies, volume 2482 of LNCS, San Francisco, CA, April 2002.
ZZZZZZZZZZZZ

[Shen2004] Scalable and Secure P2P Overlay Networks p41 ?????????

Haiying Shen, Aharon S. Brodie, Cheng-Zhong Xu, andWeisong Shi
Wayne State University, Detroit, MI 48202

random graph

uniform random graph

random DHT graph

power-law random graph

H-graph

connection graph

De Bruijn graph

continuous graph

Cube-Connected- Cycles (CCC) graph

Random Expander Graphs

Sirer Eluding Carnivores: File Sharing with Strong Anonymity p6

Emin G¨un Sirer

Skogh Fast Freenet: Improving Freenet Performance by Preferential Partition Routing and File Mesh Propagation p8

Hans-Emil Skogh

Spirakis Dynamic Networks Foundations p95

Paul G. Spirakis
joint work with
Othon Michail
Ioannis ChatzigiannakisDynamic Networks Foundations
Paul G. Spirakis
joint work with
Othon Michail
Ioannis Chatzigiannakis

Staab Semantic Web and Peer-to-Peer p359 ???????????

[SUNG2005] A Survey of Data Management in Peer-to-Peer Systems p50

L. G. ALEX SUNG, NABEEL AHMED, ROLANDO BLANCO, HERMAN LI,
MOHAMED ALI SOLIMAN, and DAVID HADALLER
School of Computer Science, University of Waterloo
Peer

random graphs

deBruijn graph

semantic graph

skip graphs
Paul Syverson, Gene Tsudik, Michael Reed, and Carl Landwehr. Towards an Analysis of Onion Routing Security. In H. Federrath, editor, Proceedings of Designing Privacy Enhancing Technologies: Workshop on Design Issues in Anonymity and Unobservability, pages 96–114. Springer-Verlag, LNCS 2009, July 2000.
ZZZZZZZZZZ

[Tang2009] Group Routing: A Reliable mutual anonymous approach in Dynamic Overlay p6

Peng Tang
Vidalia (Tor/Privoxy) Protecting Your Privacy Online, Anonymously By Sean KernerJanuary 28, 2008 3:20 PM
http://www.tomsguide.com/us/security-online-privacy,review-1055-4.html
https://blog.torproject.org/comment/reply/998/92061
Wallach A Survey of Peer-to-Peer Security Issues p16

Dan S. Wallach
dwallach@cs.rice.edu
Rice University, Houston, TX 77005, USA

Wepiwe HiPeer An Evolutionary Approach to P2P Systems p196 ?????????????

ZZZZZZZZZZZZZZ

[Zhou2013] SGor: Trust graph based onion routing p23

Peng Zhou a,?, Xiapu Luo a, Ang Chen b,1, Rocky K.C. Chang a
a The Hong Kong Polytechnic University, Hong Kong
b University of Pennsylvania, United States

Computer Networks 57 (2013) 3522–3544
Contents lists available at ScienceDirect Computer Networks
journal homepage:

www.elsevier.com/locate/comnet
Keywords:
Trust graph
Anonymity
Onion routing

Corresponding author. Tel.: +852 62134272.

E-mail addresses:

cspzhouroc@comp.polyu.edu.hk (P. Zhou)

csxluo@comp.polyu.edu.hk (X. Luo)

angchen@cis.upenn.edu (A. Chen)

csrchang@comp.polyu.edu.hk (R.K.C. Chang)

1 This work was done when the co-author was with The Hong Kong Polytechnic University.

Trust-based onion routing

Onion routing networks

malicious onion routers

correlation- like attacks

adversaries’ routers

onion circuits

Tor network

trust-based onion routing

trust graph based onion routing


Database Development
Databases are where critical enterprise or personal information are safeguarded. In its broad meaning, all kinds of information are data: texts, numeric data, documents/files, images/pictures, photo, animation, audio, video, drawings, and they are now kept in thousands of formats, from well-known Microsoft Office family programs (Word, Excel, Outlook, PowerPoint, Frontpage, Publish...) to native Chinese software such as WPS 2000. Graphic applications such as Photoshop, 3D MAX, Authoware are also software for handling and saving image data.

In its narrow definition of database, we are talking about those application which process only the structured data, such as records during a production process, sales records, whether forecast etc. No images, no multimedia, only plain texts and numeric.

Prevalent software of databases include Microsoft SQL Server, Oracle, DB2, Sybase, Informix etc.Using these databases you can store, process and output your data and keep them for long use in a variety of environment - from standalone computer to Internet use.

And now solaires, as a web-based company, helps companies and individuals to deploy their locally maintained to Internet/Intranet or Extranet over TCP/IP. You probably want to publish some of your products info, prices info to your clients/suppliers/partners, and you also want to synchronize your data in your own office with those of your websites. And solaires makes your dream become true.

With up-to-date web data broadcasting technologies, we can publish your data to any of your websites, in any platforms, and of any data type in any databases,incl.:

  • Platforms: Windows 2000/NT/98/95, Unix, Linux, Solaris ...
  • Databases:
    • SQL Server,
    • Oracle,
    • Informix,
    • DB2,
    • PowerBuilder,
    • Delphi,
    • VisualFoxpro,
    • LotusNotes,
    • Jasmine,
    • mSQL,
    • mySQL,
    • postgreSQL,
    • Access,
    • Excel,
    • iBASE,
    • DM2
    • and plain text formats (notepad or wordpad)
  • Data type: records, texts, images, animation and multimedia, just name a few...
Contact solaires for a consultation, our technical experts will answer all your questions and give suggestions of your data publishing plan.

  • Platforms: Windows 2000/NT/98/95, Unix, Linux, Solaris ...
  • Databases:
    • SQL Server,
    • Oracle,
    • Informix,
    • DB2,
    • PowerBuilder,
    • Delphi,
    • VisualFoxpro,
    • LotusNotes,
    • Jasmine,
    • mSQL,
    • mySQL,
    • postgreSQL,
    • Access,
    • Excel,
    • iBASE,
    • DM2
    • and plain text formats (notepad or wordpad)
  • Data type: records, texts, images, animation and multimedia, just name a few...
Contact solaires for a consultation, our technical experts will answer all your questions and give suggestions of your data publishing plan.
Databases
  • http://www.mysql.com/
  • http://www.gbnis.com
  • http://www.pconline.com.cn/pcedu/empolder/db.htm
  • http://www.19do.com/
  • http://clyan.hongnet.com/

How to run mysql with non-root user ?

#adduser mysqld
#passwd mysqld
#chown -R mysqld /path/to/mysql/var/*
#/path/to/mysql/bin/safe_mysqld -O options --user=mysqld &

for install and cofigure
PostgreSQL
for install and cofigure
Informix

http://www.informix.com
Informix information management solutions are open, scalable, manageable, and fully extensible — providing the kind of flexibility that is essential for growing organizations. From data warehousing, analysis and decision support, to Web content delivery, Informix products are engineered to enable today's businesses to efficiently manage any kind of information, anywhere, and at any time.

Informix Dynamic Server (IDS)
Best-of-breed, general purpose, mission-critical OLTP database for e-business

Informix OnLine 5
Easy OLTP for small to mid-size businesses

Informix SE
Zero-admin, embeddable, multiuser DBMS

Informix C-ISAM
Fast and cost-effective file management technology

Informix Extended Parallel Server (XPS)
Enterprise data warehousing

Red Brick Warehouse
Online data warehousing

Informix is now part of IBM.
DBServers Oracle8i
Oracle9i
AppSerers Oracle Application Server4.0
DevTools Oracle Designer
Oracle Developer
Oracle JDeveloper
Oracle Reports
Resources
  • http://www.oraclefan.net/
  • http://oracle.myrice.com/
  • http://www.linuxforum.net/forum/postlist.php?
  • Cat=&Board=oracle
  • http://ocp.6to23.com/
  • -http://www.orafaq.com/faq.htm
  • http://www.oradb.net/
  • http://www.oracle.com/
for install and cofigure
Sybase

http://www.sybase.com.cn/
DB2

http://www-4.ibm.com/software/data/db2/

SQL Server 2000

http://www.microsoft.com
Others

Delphi

http://www.sybase.com

VisualFoxpro

http://www.microsoft.com

Pervasive.SQL

http://www.yida.com.cn/ PervasiveSQL,Tango

Jasmine

http://www.ca.com

mSQL
  • http://www.hughes.com.au/
  • http://ftp.cdut.edu.cn/pub2/linux/system/database/msql/faq.html The mSQL FAQ

Access

http://www.microsoft.com

InterBase

    • http://www.borland.com/interbase/
    • http://www.3asoft.com/

InstantDB

SAPDb

Solid

hsql db (Hypersonic)

Cloudscape

velocis

filepro

iODBC

Adabas

dBase

FrontBase

Empress

Unix dbm

Ingres
Databases - China
IBase

http://www.ibase.com.cn/

OpenBASE
http://www.commerceware.com.cn/
  • OpenBASE Mini
  • OpenBASE Secure
  • OpenBASE
  • Open Miner
Data Bridge
http://www.dtbridge.com
http://www.pandadb.com/

KingBase
http://www.kingbase.com.cn/ Embedded database

DM3

http://www.dm2.com.cn/

DataAnyWhere
http://www.szhzz.com/
  • DATA SOURCE CONNECTER
  • DATA MAPPER
  • SQL EDITTER
  • XML ENGINE
  • DATA DISTRIBUTER
  • WATCH DOG
  • DOCUMENT PROCESSER

http://www.xnodes.com

Others

DBFT

http://dbft.top263.net/

HYSQL

http://www.huayisoft.com/

EasyWeb

http://www.xinhong.net/

DfDraw

http://www.doublefox.com/prod02.htm

DIPS

http://www.info-quick.com.cn/

Visual DBTOOLS

http://www.infolight.com.cn/

DBTools

http://dbtools.myrice.com

EGrid 2000

http://www.egrid2000.com/

DBMaker

http://www.dbmaker.com.tw/DBMaker

Visual dBASE

http://www.sinter.com.tw/vbc.htm

ReadSoft

http://www.readsoft.com.cn
GenSQL

http://www.coinfosoft.com

More Info

Database.doc

Database2.doc

Database china

  • danywhere.htm
  • danywhere_en.htm
  • dbridge.htm
  • dbridge_en.htm
  • dm3.htm
  • dm3_en.htm
  • jox.htm
  • jox_en.htm
  • kingbase.htm
  • kingbase_en.htm
  • others.htm

Database world

  • db2.htm
  • db2_en.htm
  • ibase.htm
  • ibase_en.htm
  • informix.htm
  • informix1.htm
  • informix_2.htm
  • informix_en.htm
  • lotus.htm
  • lotus_en.htm
  • mssql.htm
  • mssql_en.htm
  • mysql-jdbc.htm
  • mysql.htm
  • mysql1.htm
  • mysql_2.htm
  • mysql_en.htm
  • openbase.htm
  • openbase_en.htm
  • oracle-install-log.html
  • oracle-install.htm
  • oracle-install1.htm
  • oracle.htm
  • oracle1.htm
  • oracle2.htm
  • oracle_2.htm
  • oracle_en.htm
  • others_en.htm
  • postgrsql.html
  • psql.htm
  • psql_en.htm
  • sybase.htm
  • sybase_en.htm

网络数据库

国内主要数据库 | 国外主要数据库 | 其他数据库

业务范围
数据库存放着企业或个人的关键数据。广义来说，所有信息都是数据：文本，数字，文件，图像，照片，动画，声音，影像，图纸。这些数据以很多种不同形式存在，从微软的办公系列软件(Word, Excel, Outlook, PowerPoint, Frontpage, Publish...) 本地化的中文软件如 WPS 2000. 绘图软件如 Photoshop, 3D MAX, Authoware 则是处理图像数据的软件。.

狭义的数据库是指结构化的数据，例如生产过程的数据，销售记录，天气预报等。没有图像，没有多媒体，只有简单的文本和数字。

目前流行的数据库软件包括 Microsoft SQL Server, Oracle, DB2, Sybase, Informix 等.利用这些数据库应用系统您能够存储，处理和输出您的数据，长期保存 - 可以是单机，页可以是局域网。

时力公司作为一个网络技术服务商，帮助企业和个人建置从独立PC机， Internet，Intranet 到Extranet 采用 TCP/IP协议的各种数据应用. 或许您准备将您的某些产品/价格信息发布到您的客户/供应商/合作伙伴，您也许希望使您在办公室的业务数据与您的网站数据库保持同步。时力将使您的梦想成真。

借助最新的数据广播技术，我们能够将您的数据发布到任何网站，在任何的平台上，采用任何数据库，包括：
  • 平台: Windows 2000/NT/98/95, Unix, Linux, Solaris ...
  • 数据库:
    • SQL Server,
    • Oracle,
    • Informix,
    • DB2,
    • LotusNotes,
    • mySQL,
    • Sybase
  • 数据形态: 数字记录, 文本, 图像, 动画和多媒体, ..
请与时力联系，我们的 技术专家 会回答您所有的问题，提供您关心的数据发布问题的答案。


DataAnyWhere

网络数据库
DataAnyWhere
http://www.szhzz.com/
  • DATA SOURCE CONNECTER ：数据资源连接器---利用ODBC标准接口连接不同应用系统，接受多种报文
  • DATA MAPPER：数据映射器----图形化数据对应关系设置
  • SQL EDITTER：SQL 编辑器-----SQL语句处理数据
  • XML ENGINE：XML引擎-----XML进行数据解析和翻译
  • DATA DISTRIBUTER：数据分发器----用EMAIL、FTP等分发和接收数据
  • WATCH DOG：自动值守器-----自动执行已定义任务实现无人值守
  • DOCUMENT PROCESSER：报文-报文处理器----进行报文—报文处理


DataAnyWhere

Web databases
DataAnyWhere
http://www.szhzz.com/
  • DATA SOURCE CONNECTER ：数据资源连接器---利用ODBC标准接口连接不同应用系统，接受多种报文
  • DATA MAPPER：数据映射器----图形化数据对应关系设置
  • SQL EDITTER：SQL 编辑器-----SQL语句处理数据
  • XML ENGINE：XML引擎-----XML进行数据解析和翻译
  • DATA DISTRIBUTER：数据分发器----用EMAIL、FTP等分发和接收数据
  • WATCH DOG：自动值守器-----自动执行已定义任务实现无人值守
  • DOCUMENT PROCESSER：报文-报文处理器----进行报文—报文处理


Data Bridge

网络数据库
Data Bridge
http://www.dtbridge.com

Data Bridge 通过异构环境下企业不同数据库或同种数据库之间关键业务数据的实时或批量方式单向或双向复制或数据同步检查，从而实现数据的高可用性，立即存取，有效维护。同时，Data Bridge允许在一对一、一对多、多对多的环境下复制数据，从而最大限度实现企业数据的共享和系统资源负荷的平衡。不管企业是何种性质，金融（银行、证券、保险）非金融（制造、流通、邮电、通讯等），只要企业信息系统涉及到数据的转换、复制、迁移、备份等都可应用本产品


DM3

网络数据库
DM3
IBase
Kingbase
OpenBase
PandaSQL
DM3

华中达梦数据库有限公司 - http://www.dm2.com.cn/ 分布式数据库管理系统。

达梦数据库多媒体技术研究所成立于1992年，是国内成立最早的数据库研究所。在此基础上成立的武汉华工达梦数据库有限公司位于武汉东湖之滨的东湖新技术开发区。

达梦公司的拳头产品“分布式多媒体数据库管理系统DM3”，在国民经济许多领域得到良好应用，取得了显著的社会效益和经济效益。

DM3的优势

DM3拥有在中国市场上的国外商用DBMS所不具备的独特优势：

1。功能上的优势：

*数据类型和存储结构支持GIS（地理信息系统）空间数据的处理。

*数据类型、数据模型和存储结构支持多媒体数据管理。

*安全级别达到国际标准B1级，而在中国市场上的国外DMBS安全级别最高为C2级。

*实现了异构系统的互连互访（不同硬件、不同操作系统、不同的数据库管理系统）。

2。系统集成与扩充方便：

DM3是自主开发的DBMS，有源代码，系统集成和扩充十分方便，可以满足特定用户的特殊需求。

3。价格优势： DM3的价格相当于和国外DBMS同类产品价格的1/3。

4。资源充分利用：

国内一些用户盲目跟踪国外DBMS的最新版本，但据一项统计调查其功能利用率平均不到50%，大部分用户属于超前消费，达梦系统提供系列产品，可以满足不同需求的各类用户，使系统资源得到充分利用。

5。技术培训：

达梦有一支实力较强的培训和售后服务专业队伍。


DM3

Web databases
DM3
IBase
Kingbase
OpenBase
PandaSQL
DM3

http://www.dm2.com.cn/

English available soon !
达梦数据库多媒体技术研究所成立于1992年，是国内成立最早的数据库研究所。在此基础上成立的武汉华工达梦数据库有限公司位于武汉东湖之滨的东湖新技术开发区。

达梦公司的拳头产品“分布式多媒体数据库管理系统DM3”，在国民经济许多领域得到良好应用，取得了显著的社会效益和经济效益。

DM3的优势

DM3拥有在中国市场上的国外商用DBMS所不具备的独特优势：

1。功能上的优势：

*数据类型和存储结构支持GIS（地理信息系统）空间数据的处理。

*数据类型、数据模型和存储结构支持多媒体数据管理。

*安全级别达到国际标准B1级，而在中国市场上的国外DMBS安全级别最高为C2级。

*实现了异构系统的互连互访（不同硬件、不同操作系统、不同的数据库管理系统）。

2。系统集成与扩充方便：

DM3是自主开发的DBMS，有源代码，系统集成和扩充十分方便，可以满足特定用户的特殊需求。

3。价格优势： DM3的价格相当于和国外DBMS同类产品价格的1/3。

4。资源充分利用：

国内一些用户盲目跟踪国外DBMS的最新版本，但据一项统计调查其功能利用率平均不到50%，大部分用户属于超前消费，达梦系统提供系列产品，可以满足不同需求的各类用户，使系统资源得到充分利用。

5。技术培训：

达梦有一支实力较强的培训和售后服务专业队伍。


JOX

网络数据库

http://www.xnodes.com

现有的大型数据都是采用原有的数据核心，然后在外层加上一接口层，以支持XML数据结构，但由于中间的转换过程使效率很低。 针对中小型事务的要求，我们推出一套从核心层支持XML的小型数据库系统。

JOX 特性：

缓存：JOX数据组织在页结构中，每个页包含有128个可变长度DOM结点，当通过W3C-DOM标准方法访问JOX结点数据时，包含数据的页面装入主缓存。缺省的缓存大小装入100个页面，并且大小是可调的。但它不能低于20个页面。推荐使用的缓存大小为全部加载而不用使用特殊的交换技术。这种交换技术是为了支持小容量缓存设备而开发的。缓存技术可以让相同的JOX核心数据结构的不同实现而打开的所有JOX文件共享缓存空间。它使用"最近最少使用"原则。

数据空间整理：当一个结点进行了插入、更新、删除操作时，含有这个结点的页就被标为"脏页"。当这些页从缓存中被替换时，已修改过的页就加入JOX文件末尾。因此写操作后JOX文件就会增大，因为这些无效的页所占的空间不是被自动清除或重新使用。当然在读和查询操作后，JOX文件不会改变大小。
JOX文件通过指定的操作在任何时候删除没用的页而被整理。当仅包含有效数据页的临时文件创建，然后已整理的JOX文件取代未整理的文件拷贝。在这些操作中还能存放指定临时文件的目录。空闲的比率（就是物理文件中无用空间的百分比）能被用户应用程序所访问。这个数字采用0到1之间的双精度格式。如果空闲超出指定的比率，用户应用程序就能开始自动整理文件。

碎片收集：数据空间整理是以单个页为基础而不是被废弃的结点空间。为释放这此结点空间，必须有一套完整的碎片收集功能。

提交点：在任何时间内用户应用程序在JOX上进行的更新、删除、插入操作能同时决定提交JOX当前的状态信息，在提交的操作中，主文件的索引、在主存贮器中的正常维护信息都被写进磁盘。如果因为"磁盘满"错误而产生了用户应用程序崩溃，在重新打开文件时，JOX将会立即进入最后一次成功提交作业前的状态。即使发生了崩溃后，也能尽量保证文件的一致性。无论如何，当提交作业中用户程序崩溃也有一个补救破坏的文件的机会。

压缩存贮：JOX文件可以用gzip的压缩算法压缩。这能就会减小文件，通常能压缩一半。空间的效率通常提高速度。压缩后的文件能提高读写页速度的20%。压缩只是在生成JOX文件时进行一次，文件在以后不能进行压缩。打开JOX文件操作会自动识别压缩并进行相应的处理。当删除已存在的JOX文件时用户程序不用考虑或了解有关压缩的问题。

多线程的访问：并行处理问题时同一文件可被不同的线程读取，不同线程的更新操作，块读写操作。在JOX文件上的所有自动操作都是线程安全的。不仅如此，组合更新操作（如读出一个结点，修改后又写回JOX）更是所知的操作难点。保持组合更新操作的原子性，应用程序必须同步JOX文档对象的代码块。


JOX

Web databases

http://www.xnodes.com

现有的大型数据都是采用原有的数据核心，然后在外层加上一接口层，以支持XML数据结构，但由于中间的转换过程使效率很低。 针对中小型事务的要求，我们推出一套从核心层支持XML的小型数据库系统。

JOX 特性：

缓存：JOX数据组织在页结构中，每个页包含有128个可变长度DOM结点，当通过W3C-DOM标准方法访问JOX结点数据时，包含数据的页面装入主缓存。缺省的缓存大小装入100个页面，并且大小是可调的。但它不能低于20个页面。推荐使用的缓存大小为全部加载而不用使用特殊的交换技术。这种交换技术是为了支持小容量缓存设备而开发的。缓存技术可以让相同的JOX核心数据结构的不同实现而打开的所有JOX文件共享缓存空间。它使用"最近最少使用"原则。

数据空间整理：当一个结点进行了插入、更新、删除操作时，含有这个结点的页就被标为"脏页"。当这些页从缓存中被替换时，已修改过的页就加入JOX文件末尾。因此写操作后JOX文件就会增大，因为这些无效的页所占的空间不是被自动清除或重新使用。当然在读和查询操作后，JOX文件不会改变大小。
JOX文件通过指定的操作在任何时候删除没用的页而被整理。当仅包含有效数据页的临时文件创建，然后已整理的JOX文件取代未整理的文件拷贝。在这些操作中还能存放指定临时文件的目录。空闲的比率（就是物理文件中无用空间的百分比）能被用户应用程序所访问。这个数字采用0到1之间的双精度格式。如果空闲超出指定的比率，用户应用程序就能开始自动整理文件。

碎片收集：数据空间整理是以单个页为基础而不是被废弃的结点空间。为释放这此结点空间，必须有一套完整的碎片收集功能。

提交点：在任何时间内用户应用程序在JOX上进行的更新、删除、插入操作能同时决定提交JOX当前的状态信息，在提交的操作中，主文件的索引、在主存贮器中的正常维护信息都被写进磁盘。如果因为"磁盘满"错误而产生了用户应用程序崩溃，在重新打开文件时，JOX将会立即进入最后一次成功提交作业前的状态。即使发生了崩溃后，也能尽量保证文件的一致性。无论如何，当提交作业中用户程序崩溃也有一个补救破坏的文件的机会。

压缩存贮：JOX文件可以用gzip的压缩算法压缩。这能就会减小文件，通常能压缩一半。空间的效率通常提高速度。压缩后的文件能提高读写页速度的20%。压缩只是在生成JOX文件时进行一次，文件在以后不能进行压缩。打开JOX文件操作会自动识别压缩并进行相应的处理。当删除已存在的JOX文件时用户程序不用考虑或了解有关压缩的问题。

多线程的访问：并行处理问题时同一文件可被不同的线程读取，不同线程的更新操作，块读写操作。在JOX文件上的所有自动操作都是线程安全的。不仅如此，组合更新操作（如读出一个结点，修改后又写回JOX）更是所知的操作难点。保持组合更新操作的原子性，应用程序必须同步JOX文档对象的代码块。


KingBase

网络数据库
DM3
IBase
Kingbase
OpenBase
PandaSQL
KingBase
北京人大金仓信息技术有限公司 - http://www.kingbase.com.cn/ 小金灵嵌入式移动数据库及相关数据库产品

移动数据库软件--"小金灵"嵌入式移动数据库

小金灵嵌入式移动数据库系统（kingbase lite）是人大金仓的核心产品，由于本产品的独特性及技术的领先性，"小金灵"在 国内同类产品中居于领先地位。

其技术特点包括：

    适应多种平台，支持WindowsCE、PalmOS、Hopen、Linux等多种操作系统；
    微小内核，初始占用内存不超过100K；
    数据库的自由定制，能够根据具体应用或行业特点定制系统功能；
    方便的查询功能，支持SQL查询语句；
    强大的数据管理功能，支持SQL标准的子集，提供库管理、表管理等功能；
    操作简单方便，提供简明的API接口，可在高级语言中方便调用；
    组件式体系结构，数据库可自由定制，多种数据同步方式等；
    可广泛应用于移动商务，信息采集，野外作业等。
    嵌入式开发工具--"小金灵"数据库系统开发构件库

    "小金灵"数据库系统开发构件库将数据库应用编程接口封装在不同的类中，并以类库的形式提供给应用开发人员直接使用。当用户利用"小金灵"数据库系统进行掌上电脑的应用程序开发时，可以直接使用这些构件类，而不需重新编写API使用代码，从而简化了应用开发过程、缩短了应用开发的时间、节省了开发人员的工作量，提高系统开发效率。

数据传递软件--嵌入式后台同步服务器软件

同步服务器（Kingbase Syncserver）作为小金灵移动数据库系统三层体系结构中的中间层，为嵌入式数据库（KingbaseLite）和远程主数据库（RDB）之间的双向数据交换搭起了桥梁。
    主要特点：
    *支持上载、下载、混合等多种同步方式。
    *支持数据同步对象。
    *采用表的垂直和水平混合分片模式。
    *支持事务性同步，具有恢复功能。
    *提供了简单灵活的冲突解决方案。
    *支持多种通讯协议等。

数据管理软件--DB Center数据库管理中心

小金灵DB Center是小金灵嵌入式移动数据库的数据管理中心，它在台式PC机运行，实现小金灵数据库的创建和删除、表的创建、修改、删除操作以及掌上电脑通讯，提供上下载数据库的功能。

并行数据库软件--PBase并行数据库系统

包括Pbase/1、Pbase/2、Pbase/3。可在SMP、MPP、Cluster等多种硬件平台上运行，如曙光一号、曙光天阔多CPU并行机、曙光天演机群、曙光2000并行计算机等。支持的操作系统平台包括AIX、Windows NT和Windows98。从而由下至上建成了一个跨多种软、硬件平台的并行数据库系统PBase系列，形成了完整的并行化处理体系，同时保持了系统良好的可扩展性和可伸缩性。


KingBase

Web databases
DM3
IBase
Kingbase
OpenBase
PandaSQL
KingBase
http://www.kingbase.com.cn/

移动数据库软件--"小金灵"嵌入式移动数据库

小金灵嵌入式移动数据库系统（kingbase lite）是人大金仓的核心产品，由于本产品的独特性及技术的领先性，"小金灵"在 国内同类产品中居于领先地位。

其技术特点包括：

    适应多种平台，支持WindowsCE、PalmOS、Hopen、Linux等多种操作系统；
    微小内核，初始占用内存不超过100K；
    数据库的自由定制，能够根据具体应用或行业特点定制系统功能；
    方便的查询功能，支持SQL查询语句；
    强大的数据管理功能，支持SQL标准的子集，提供库管理、表管理等功能；
    操作简单方便，提供简明的API接口，可在高级语言中方便调用；
    组件式体系结构，数据库可自由定制，多种数据同步方式等；
    可广泛应用于移动商务，信息采集，野外作业等。
    嵌入式开发工具--"小金灵"数据库系统开发构件库

    "小金灵"数据库系统开发构件库将数据库应用编程接口封装在不同的类中，并以类库的形式提供给应用开发人员直接使用。当用户利用"小金灵"数据库系统进行掌上电脑的应用程序开发时，可以直接使用这些构件类，而不需重新编写API使用代码，从而简化了应用开发过程、缩短了应用开发的时间、节省了开发人员的工作量，提高系统开发效率。

数据传递软件--嵌入式后台同步服务器软件

同步服务器（Kingbase Syncserver）作为小金灵移动数据库系统三层体系结构中的中间层，为嵌入式数据库（KingbaseLite）和远程主数据库（RDB）之间的双向数据交换搭起了桥梁。
    主要特点：
    *支持上载、下载、混合等多种同步方式。
    *支持数据同步对象。
    *采用表的垂直和水平混合分片模式。
    *支持事务性同步，具有恢复功能。
    *提供了简单灵活的冲突解决方案。
    *支持多种通讯协议等。

数据管理软件--DB Center数据库管理中心

小金灵DB Center是小金灵嵌入式移动数据库的数据管理中心，它在台式PC机运行，实现小金灵数据库的创建和删除、表的创建、修改、删除操作以及掌上电脑通讯，提供上下载数据库的功能。

并行数据库软件--PBase并行数据库系统

包括Pbase/1、Pbase/2、Pbase/3。可在SMP、MPP、Cluster等多种硬件平台上运行，如曙光一号、曙光天阔多CPU并行机、曙光天演机群、曙光2000并行计算机等。支持的操作系统平台包括AIX、Windows NT和Windows98。从而由下至上建成了一个跨多种软、硬件平台的并行数据库系统PBase系列，形成了完整的并行化处理体系，同时保持了系统良好的可扩展性和可伸缩性。


其他

网络数据库
其他
国内

DBFT数据通

数据通dbft http://dbft.top263.net/ - 通用数据库管理工具

JBase

JBase 数据库系统 - JBase 数据库系统，纯 Java 编写，标准 SQL 语法，标准 JDBC 接口.

HYSQL

华易软件有限公司 -http://www.huayisoft.com/ 华易网络数据库HYSQL。

EasyWeb

东方新宏科技发展有限公司 - http://www.xinhong.net/ EasyWeb数据库

DfDraw 双狐数据图形软件 DfTask 双狐数据库集成软件

双狐数据库集成应用软件 - http://www.doublefox.com/prod02.htm 融合数据库、图形、地理信息系统、数据处理为一体的软件

DIPS

北京新星快威数码技术有限公司 - http://www.info-quick.com.cn/ 以图文库技术为核心、让用户在互联网上建立数字文献全文数据库检索系统的通用开发平台--数字文献处理系统（DIPS) 。

Visual DBTOOLS

上海讯光科技系统有限公司 - http://www.infolight.com.cn/ - 数据库开发工具--Visual DBTOOLS

DBTools-至嘉通用信息管理系统 2.1专业版共

http://dbtools.myrice.com

易表2000

http://www.egrid2000.com/

DBMaker

http://www.dbmaker.com.tw/DBMaker 最佳中文資料庫管理系統
專屬 DBMaker 的產品單元，在其中為您介紹所有和 DBMaker 相關的資訊．包括特色功能．對產品的疑難排解．和各種相關的資訊詳盡的呈現其中，讓您能對DBMaker有更進一步的了解．歡迎進入DBMaker 的世界。

Visual dBASE

http://www.sinter.com.tw/vbc.htm

瑞软全文及多媒体资料管理系统

http://www.readsoft.com.cn
通用SQL数据查询系统

http://www.coinfosoft.com

Data Anywhere

Data Bridge

JOX
国外

Delphi

http://www.sybase.com

VisualFoxpro

http://www.microsoft.com

Pervasive.SQL

北京亿达公司 - http://www.yida.com.cn/ PervasiveSQL数据库、Tango

Jasmine

http://www.ca.com

mSQL
    • http://www.hughes.com.au/
    • http://ftp.cdut.edu.cn/pub2/linux/system/database/msql/faq.html The mSQL FAQ

postgreSQL

http://www.pgsql.com.tw/

Access

http://www.microsoft.com

InterBase

    • http://www.borland.com/interbase/
    • http://www.3asoft.com/龙豪软件工作室

InstantDB

SAPDb

Solid

hsql db (Hypersonic)

Cloudscape

velocis

filepro

iODBC

Adabas

dBase

FrontBase

Empress

Unix dbm

Ingres
CloudScape


db2

网络数据库
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
DB2

http://www-4.ibm.com/software/data/db2/
DB2成为第一个获得微软高级认证的数据库

IBM公司日前宣布，IBM DB2通用数据库成为第一个获得微软高级认证的数据库。这进一步证明了IBM出类拔萃的技术实力。IBM成为微软的高级合作伙伴，使它的客户和业务伙伴有理由相信DB2能够在Windows 2000服务器环境下正常运行。

要成为微软的高级合作伙伴，获得Windows 2000的认证就显得尤为重要。IBM DB2于7
月28日成功获取该认证，从而成为第一个获得微软认证的数据库。DB2 7.2版已经通过了三种Windows 2000服务器的标识认证，它们分别是:服务器、高级服务器和数据中心服务器。目前，Oracle还没有获得Windows 2000的认证。随着微软操作系统的不断更新，IBM将会不断推出相应的DB2版本。

据最新的Gartner Dataquest数据库市场份额报告显示，2000年DB2在Windows NT环境下的销售额提高了63%，比业界平均增长速度快3倍。Oracle在Windows NT环境下的市场份额已连续3年呈负增长。

Gartner集团还认为，使用Windows 2000支持的应用程序可以增强系统的稳定性，并大大降低总的企业购买成本。

Lotus Domino增强与WebSphere和DB2的集成

IBM公司的全资子公司，Lotus软件公司日前宣布，Lotus Domino与WebSphere应用服务器、DB2通用数据库之间将实现更深入的集成。新版的Lotus Domino(代码为“Rnext")中将使在同一个应用环境下利用三项不同技术创建应用程序变得更容易。新的集成还将使客户顺利地将市场领先的协同作业、数据管理和交易管理能力很好地融入他们的软件解决方案中。

Lotus Domino的开发者不但可以利用DB2的数据库管理能力，而且能够通过WebSphere分享Java Server Page(JSP)的功能。DB2和WebSphere的开发者们还将能够轻松地将合作成果加入B2B数据应用中去。因而，端到端的解决方案把企业的数据处理与企业的人员和知识结合在一起，在改善客户关系的同时提高了生产力。

当今的业务环境要求企业在业务流程中能够分享数据，解决问题及快速协作。因此就需要采取新的方式来使企业能够保持对客户需求的快速响应能力，从而有效地提高竞争力。与IBM相应基础架构软件之间新的集成则大大提升了Lotus Domino客户的电子商务表现。
IBM发布DB2数据仓库管理器7.2版

近日，IBM公司推出了新版数据仓库管理器(DB2 Warehouse Manager)。该产品将进一步推进数据集成化的发展，保证用户实现多渠道的源数据复制。同时，在IBM MQSeries扩展版的支持下，用户从i2、SAP和Web上获取数据将变得更加快捷、方便。

DB2 Warehouse Manager可以自动创建、扩充和更新数据库和数据中心的信息，这使IBM商业智能的用户获取最精确的客户信息，从而在适当的时间和地点做出最佳的决定。例如
，如果某位顾客在银行贷款或存入10,000美元，每个应用程序都会相应地进行修改。而通过DB2 Warehouse Manager，银行还可以对最新的数据进行自动整理，以便日后随时查看客户的最新信息。

新版数据仓库管理器的功能还可以为商业智能应用增加运用i2、SAP等业界一流应用的数据的功能。IBM对这些应用程序提供自动的数据映射，将有效地减少数据映射过程中的人员成本，降低风险。据IBM估计，自动映射i2、SAP和Web数据的时间只是手动映射的十分之一。

目前，IBM已经同许多业务伙伴建立了合作关系，进一步增强DB2 Warehouse Manager的功能。例如，为了确保名称和地址的准确性，IBM与Trillum、Evoke和Vality合作，增加了名称、地址和数据的净化功能。此外，ETI、Business Objects、Cognos和Brio等企业也分别与IBM展开了不同领域的合作。

IBM DB2全面启动电子商务解决方案

IBM公司8月3日在北京拉开了“DB2新产品发布及应用展示会全国巡展”的帷幕。在会上，IBM公司详细介绍了IBM DB2的产品策略及其解决方案，并且对应用解决方案进行了现场展示。在此后的一个月中，IBM公司还将在上海、广州、沈阳、西安、重庆、武汉、深圳等城市举行此项活动。

据介绍，数据库作为成功电子商务的动力源泉和核心部件，正在成为企业竞争制胜的法宝。在这方面，DB2通用数据库一直占据着业界主导地位。1998年，DB2通用数据库以32.3%的市场占有率居全球首位。目前，全球有超过4000万的用户和超过22.5万的公司正在使用IBM的数据管理系统。全球80%的大型数据库运行在DB2之上；70%的关键数据正由DB2进行管理。IBM新推出的DB2 6.1版进一步加强了产品的伸缩性、稳定性、可扩展性、可访问性及可管理性，成为全球唯一做到通用的数据库系统。

新版DB2通用数据库提供了从优化运行、跨越平台到移动计算的先进性能，为用户的电子商务应用提供了更全面、更强大的支持。一方面，它提供了优异的跨平台整合性，实现了对PC 平台、UNIX、Linux、Windows NT等二十余种主要操作平台的全面支持，使处于不同平台上的的数据库无须转换便可轻松共享。另一方面，它将对象关系模型、Java技术进一步扩展到OS/390、O S/400平台上，使数据在大型机上实现了真正的通用性，从而使数据信息的管理和使用更加方便。

在保持高端产品优势的同时，IBM又推出了适用于移动办公用户的DB2卫星版及漫游版，从而将其应用拓展至Palm OS或Win dows CE等移动计算平台，使企业的电子商务应用推广到移动计算领域。

目前，IBM公司与全球的合作伙伴、独立软件开发商(ISV)以及业界流行的电子商务解决方案提供商密切合作，已经开发出一万多种电子贸易、客户关系管理(CRM)、企业资源规划(ERP)、供应链管理(SCM)、网上自助服务(WESS)以及商业智能(BI)应用，这一数字还在以每年50%的速度增长。


db2

Web databases
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
DB2

http://www-4.ibm.com/software/data/db2/
As the foundation for e-business, DB2 product family software is the industry's first multimedia, Web-ready relational database management system, strong enough to meet the demands of large corporations and flexible enough to serve medium-sized and small e-businesses. DB2 product family software together with Internet technology makes information easily accessible, available, secure across diverse platforms. There are more than 60 million DB2 users from over 300,000 companies worldwide relying on IBM data management solutions.


ibase

网络数据库
DM3
IBase
Kingbase
OpenBase
PandaSQL
IBase

北京国信贝斯软件有限公司 -http://www.ibase.com.cn/ 非结构化网络数据库
iBASE核心技术优势

--------------------------------------------------------------------------------

领先的非结构化数据库

采用自主知识产权的非结构化数据库技术，支持重复字段与子字段，数据变长存储管理；
支持字符、数值、模式等多种数据类型，支持数据库外挂文件(TXT、HTML、XML、RTF、WORD、EXCEL、Powerpoint、PDF等格式)全文检索；
便于数据交换，可通过ISO2709、CNMARC、USMARC、文本、TFORM文件等与其它系统交换数据；
支持从传统关系型数据库到iBASE非结构化数据库的数据转换和数据同步

智能化的全文搜索引擎

采用先进的B* 树索引算法，支持多种可选字段索引方式，支持对字段内容的索引表达式编程和索引预处理，索引方式灵活高效；
支持字段级和数据库级的全文检索，支持基于布尔逻辑检索表达式的全文检索，适合不同检索需求；
检索功能强大，支持各种成熟的检索方式，检准、检全率高，海量数据检索秒级响应；
支持词表管理功能，支持同义词、相关词及下位词的全文检索扩展，实现智能化全文检索；
支持按检索词词频对检索结果进行相关度排序，支持多种用户自定制的检索结果排序方式。

高效率的组件化、模板化的开发技术

支持微软ActiveX标准的iBASE OCX非结构化数据库开发控件，封装了完整的非结构化数据库管理及全文检索的属性和方法；
支持微软分布式COM/COM+标准的iBASE AIDB非结构化数据库中间件，使用户在ASP中可像调用ADO数据库一样调用iBASE非结构化数据库；
iBASE EJB(Enterprise Java Beans)中间件开发接口提供了用户在JAVA开发环境中访问iBASE非结构化数据库和进行跨平台应用开发的能力；
iBASE ICP编程标本语言，使用户可在iBASE WEB的应用开发中方便操纵和维护iBASE非结构化数据库；
各种用户可定制参数的DLL组件调用，封装了iBASE非结构化数据库维护和数据库全文检索的典型功能，用户无需编程，只需传递相应参数，即可构建各种简单的iBASE数据库的维护和全文检索应用；
灵活的格式化语言使用户能够方便地定制各种检索结果输出模板，大大提高应用开发编程的效率。

集成的知识管理和内容管理解决方案

实现iBASE非结构化数据库、各种主流关系数据库、各种格式文档的集成管理、发布，提供基于知识和内容的强大的全文搜索引擎，方便用户从大量离散信息中快速检索到所需要的针对性信息；
提供集成的对于各种信息资源(包括iBASE非结构化数据库、各种关系数据库、各种文档)的等级访问权限控制，确保系统信息资源的保密安全；
提供基于用户自定制的个性化信息服务，用户可在权限范围内配置自身的信息访问页面，在第一时间获取到最感兴趣的信息；
实现对于各种关系数据库的自动数据同步、对于各种格式文档的自动索引更新，确保系统对外发布信息的时效性，保证用户获取或检索到系统最新信息；
提供基于用户定制的各种信息资源订阅和邮件自动回复，实现系统信息服务方式的扩展。

::::企业级产品::::

iBASE IGF

iBASE WEB

iBASE Daemon

iBASE Index System

::::桌面产品::::

iBASE iMail

iBASE CD_Pub

::::开发工具::::

iBASE OCX


ibase

Web databases
DM3
IBase
Kingbase
OpenBase
PandaSQL
IBase

http://www.ibase.com.cn/

non-structured database
iBASE核心技术优势

--------------------------------------------------------------------------------

领先的非结构化数据库

采用自主知识产权的非结构化数据库技术，支持重复字段与子字段，数据变长存储管理；
支持字符、数值、模式等多种数据类型，支持数据库外挂文件(TXT、HTML、XML、RTF、WORD、EXCEL、Powerpoint、PDF等格式)全文检索；
便于数据交换，可通过ISO2709、CNMARC、USMARC、文本、TFORM文件等与其它系统交换数据；
支持从传统关系型数据库到iBASE非结构化数据库的数据转换和数据同步

智能化的全文搜索引擎

采用先进的B* 树索引算法，支持多种可选字段索引方式，支持对字段内容的索引表达式编程和索引预处理，索引方式灵活高效；
支持字段级和数据库级的全文检索，支持基于布尔逻辑检索表达式的全文检索，适合不同检索需求；
检索功能强大，支持各种成熟的检索方式，检准、检全率高，海量数据检索秒级响应；
支持词表管理功能，支持同义词、相关词及下位词的全文检索扩展，实现智能化全文检索；
支持按检索词词频对检索结果进行相关度排序，支持多种用户自定制的检索结果排序方式。

高效率的组件化、模板化的开发技术

支持微软ActiveX标准的iBASE OCX非结构化数据库开发控件，封装了完整的非结构化数据库管理及全文检索的属性和方法；
支持微软分布式COM/COM+标准的iBASE AIDB非结构化数据库中间件，使用户在ASP中可像调用ADO数据库一样调用iBASE非结构化数据库；
iBASE EJB(Enterprise Java Beans)中间件开发接口提供了用户在JAVA开发环境中访问iBASE非结构化数据库和进行跨平台应用开发的能力；
iBASE ICP编程标本语言，使用户可在iBASE WEB的应用开发中方便操纵和维护iBASE非结构化数据库；
各种用户可定制参数的DLL组件调用，封装了iBASE非结构化数据库维护和数据库全文检索的典型功能，用户无需编程，只需传递相应参数，即可构建各种简单的iBASE数据库的维护和全文检索应用；
灵活的格式化语言使用户能够方便地定制各种检索结果输出模板，大大提高应用开发编程的效率。

集成的知识管理和内容管理解决方案

实现iBASE非结构化数据库、各种主流关系数据库、各种格式文档的集成管理、发布，提供基于知识和内容的强大的全文搜索引擎，方便用户从大量离散信息中快速检索到所需要的针对性信息；
提供集成的对于各种信息资源(包括iBASE非结构化数据库、各种关系数据库、各种文档)的等级访问权限控制，确保系统信息资源的保密安全；
提供基于用户自定制的个性化信息服务，用户可在权限范围内配置自身的信息访问页面，在第一时间获取到最感兴趣的信息；
实现对于各种关系数据库的自动数据同步、对于各种格式文档的自动索引更新，确保系统对外发布信息的时效性，保证用户获取或检索到系统最新信息；
提供基于用户定制的各种信息资源订阅和邮件自动回复，实现系统信息服务方式的扩展。

::::企业级产品::::

iBASE IGF

iBASE WEB

iBASE Daemon

iBASE Index System

::::桌面产品::::

iBASE iMail

iBASE CD_Pub

::::开发工具::::

iBASE OCX


informix

网络数据库
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
Informix

http://www.informix.com
Informix information management solutions are open, scalable, manageable, and fully extensible — providing the kind of flexibility that is essential for growing organizations. From data warehousing, analysis and decision support, to Web content delivery, Informix products are engineered to enable today's businesses to efficiently manage any kind of information, anywhere, and at any time.

Informix Dynamic Server (IDS)
Best-of-breed, general purpose, mission-critical OLTP database for e-business

Informix OnLine 5
Easy OLTP for small to mid-size businesses

Informix SE
Zero-admin, embeddable, multiuser DBMS

Informix C-ISAM
Fast and cost-effective file management technology

Informix Extended Parallel Server (XPS)
Enterprise data warehousing

Red Brick Warehouse
Online data warehousing

Informix is now part of IBM.


informix

二、Online的安装

---- （一）Online的安装

---- 下面将详细介绍Informix-Online数据库服务器在Red Linux上的安装。

---- 首先，从网站上下载Informix的压缩包并放在Web服务器上，经解压后生成RPM包。然后使用RPM命令安装软件包。软件包一般安装在/opt/informix目录下，而且必须以超级用户的身份进行安装；随后，按以下步骤进行安装。

---- 1．创建Informix环境 在安装Online之前必须首先创建Informix用户组和Informix用户。建立Informix用户之后，设置Informix的一些环境变量，比如INFORMIXDIR、PATH、INFORMIXSERVER和ONCONFIG等等。INFORMIXDIR用于指定要将Online软件安装在什么目录。PATH变量用于指定在查找可执行文件时要搜索的目录。PATH变量应包含$ INFORMIXDIR/bin目录，以使root用户能方便地找到Online可执行文件。INFORMIXSERVER用于指定数据库服务器的名称。ONCONFIG表示数据库的日志名称。通常，在Red Hat Linux上进入到目录/opt/informix下，修改.bash_profile文件，可将其中的参数按下面的例子进行设置。

如：INFORMIXDIR=/opt/informix

ONCONFIG=onconfig.cai

INFORMIXSERVER=onlinux

PATH=$PATH:$HOME/bin:$INFORMIXDIR/etc:$INFORMIXDIR/bin

---- 2．将Online软件拷贝到$INFORMIXDIR目录 在进入$INFORMIXDIR目录后，使用适当的操作系统命令将安装介质上的内容拷贝到该目录中。接着在当前目录下，执行第三步。

---- 3．运行./installonline，安装Online installonline是安装程序，它将会修改Online文件的owner、group和mode属性。在该脚本中还将提示用户输入系列号和系列码。请注意输入的系列码必须为大写字母。如果中间出现错误，必须重新检查上面的步骤，并重新在$INFORMIXDIR目录下运行./installonline。

---- （二）配置Online

---- 需要说明的是，在安装好Online后，必须经过正确配置之后才能将Online服务器启动。配置的过程包括为Online分配磁盘空间（用于存贮数据库数据等信息），然后给Online规定运行时的参数等。

---- 配置Online是至关重要的。配置的好坏直接决定了Online运行的效率和性能。没有合理地配置Online，就可能形成事务处理的瓶颈，致使系统对用户的响应时间特别长。配置Online的过程主要是修改Online的配置文件。在Online 7.1中，必须配置的文件有2个，一个文件是由环境变量ONCONFIG指定的，所有的配置参数都在该变量所指定的文件中予以指定。$INFORMIXDIR/etc/onconfig.std文件是所有ONCONFIG文件的模板文件。用户可以根据实际需要并依照模板文件来生成新的配置文件，但不要直接修改或删除onconfig.std文件。另一个必须配置的文件是sqlhosts文件，它也在$INFORMIXDIR/etc目录下。该文件是通讯配置文件，包含着客户应用与任何数据库服务器连接的信息。所有用户和Online实例都使用同一个通讯配置文件，即sqlhosts。

---- 配置Online通常有下面几个步骤。

---- 1． 以Informix用户注册设置环境变量 在以Informix用户注册后，验证一下是否正确设置了如下4个环境变量：INFORMIXDIR、PATH、ONCONFIG和INFORMIXSERVER。如果没有正确设置，需重新设置。

---- 2． 分配磁盘空间 在启动并初始化Online之前，至少应为Online分配一块磁盘空间。分配的磁盘空间可以是Linux文件或原始磁盘设备。使用原始磁盘设备的运行效率要高些，不过在一开始就要考虑好原始磁盘的大小，因为对原始磁盘空间容量的修改比对Linux文件的修改要复杂。

---- 3． 准备ONCONFIG配置文件 如果用编辑器修改ONCONFIG配置文件，应先对onconfig.std文件做一个复制，然后在编辑新的ONCONFIG文件时修改相应配置参数值。或者在Linux系统提示符下键入Onmonitor命令，出现Onmonitor菜单后，选择"Parameters"*"Initialize"，根据提示，输入需要的ONCONFIG配置参数。

---- 4． 准备通讯配置文件sqlhosts 通讯配置文件sqlhosts在$INFORMIXDIR/etc目录中。对于初始化Online以及对客户应用和Informix数据库服务器的连接来说，sqlhosts是必须设置的。sqlhosts文件中包括4个字段: 数据库服务器名称（dbservername）、网络类型（nettype）、主机名（hostname）和服务器名（servicename）。

---- 5． 启动Online并初始化磁盘空间 第一次启动Online必须初始化分配给Online的磁盘空间，可以使用oninit -i命令来执行，该命令将破坏Online磁盘空间中所有原已存在的数据。当完成初始化任务后，Online将处于联机工作。

---- 6． 执行管理工作 如果Online已经处于联机状态，用户就可以在Linux提示符下键入dbaccess命令对数据库进行管理操作了。

---- 就安装的难易程度来看，免费的数据库软件MySQL的安装要复杂一些，Informix的安装相对容易。

---- （作者地址: 云南大学科学馆310室CERNET云南网络中心，650091）


Informix
Online的安装

（一）Online的安装

下面将详细介绍Informix-Online数据库服务器在Red Linux上的安装。

首先，从网站上下载Informix的压缩包并放在Web服务器上，经解压后生成RPM包。然后使用RPM命令安装软件包。软件包一般安装在/opt/informix目录下，而且必须以超级用户的身份进行安装；随后，按以下步骤进行安装。

1．创建Informix环境 在安装Online之前必须首先创建Informix用户组和Informix用户。建立Informix用户之后，设置Informix的一些环境变量，比如INFORMIXDIR、PATH、INFORMIXSERVER和ONCONFIG等等。INFORMIXDIR用于指定要将Online软件安装在什么目录。PATH变量用于指定在查找可执行文件时要搜索的目录。PATH变量应包含$ INFORMIXDIR/bin目录，以使root用户能方便地找到Online可执行文件。INFORMIXSERVER用于指定数据库服务器的名称。ONCONFIG表示数据库的日志名称。通常，在Red Hat Linux上进入到目录/opt/informix下，修改.bash_profile文件，可将其中的参数按下面的例子进行设置。

如：INFORMIXDIR=/opt/informix

ONCONFIG=onconfig.cai

INFORMIXSERVER=onlinux

PATH=$PATH:$HOME/bin:$INFORMIXDIR/etc:$INFORMIXDIR/bin

2．将Online软件拷贝到$INFORMIXDIR目录 在进入$INFORMIXDIR目录后，使用适当的操作系统命令将安装介质上的内容拷贝到该目录中。接着在当前目录下，执行第三步。

3．运行./installonline，安装Online installonline是安装程序，它将会修改Online文件的owner、group和mode属性。在该脚本中还将提示用户输入系列号和系列码。请注意输入的系列码必须为大写字母。如果中间出现错误，必须重新检查上面的步骤，并重新在$INFORMIXDIR目录下运行./installonline。

（二）配置Online

需要说明的是，在安装好Online后，必须经过正确配置之后才能将Online服务器启动。配置的过程包括为Online分配磁盘空间（用于存贮数据库数据等信息），然后给Online规定运行时的参数等。
配置Online是至关重要的。配置的好坏直接决定了Online运行的效率和性能。没有合理地配置Online，就可能形成事务处理的瓶颈，致使系统对用户的响应时间特别长。配置Online的过程主要是修改Online的配置文件。在Online 7.1中，必须配置的文件有2个，一个文件是由环境变量ONCONFIG指定的，所有的配置参数都在该变量所指定的文件中予以指定。$INFORMIXDIR/etc/onconfig.std文件是所有ONCONFIG文件的模板文件。用户可以根据实际需要并依照模板文件来生成新的配置文件，但不要直接修改或删除onconfig.std文件。另一个必须配置的文件是sqlhosts文件，它也在$INFORMIXDIR/etc目录下。该文件是通讯配置文件，包含着客户应用与任何数据库服务器连接的信息。所有用户和Online实例都使用同一个通讯配置文件，即sqlhosts。

配置Online通常有下面几个步骤。

1． 以Informix用户注册设置环境变量 在以Informix用户注册后，验证一下是否正确设置了如下4个环境变量：INFORMIXDIR、PATH、ONCONFIG和INFORMIXSERVER。如果没有正确设置，需重新设置。

2． 分配磁盘空间 在启动并初始化Online之前，至少应为Online分配一块磁盘空间。分配的磁盘空间可以是Linux文件或原始磁盘设备。使用原始磁盘设备的运行效率要高些，不过在一开始就要考虑好原始磁盘的大小，因为对原始磁盘空间容量的修改比对Linux文件的修改要复杂。

3． 准备ONCONFIG配置文件 如果用编辑器修改ONCONFIG配置文件，应先对onconfig.std文件做一个复制，然后在编辑新的ONCONFIG文件时修改相应配置参数值。或者在Linux系统提示符下键入Onmonitor命令，出现Onmonitor菜单后，选择"Parameters"*"Initialize"，根据提示，输入需要的ONCONFIG配置参数。

4． 准备通讯配置文件sqlhosts 通讯配置文件sqlhosts在$INFORMIXDIR/etc目录中。对于初始化Online以及对客户应用和Informix数据库服务器的连接来说，sqlhosts是必须设置的。sqlhosts文件中包括4个字段: 数据库服务器名称（dbservername）、网络类型（nettype）、主机名（hostname）和服务器名（servicename）。

5． 启动Online并初始化磁盘空间 第一次启动Online必须初始化分配给Online的磁盘空间，可以使用oninit -i命令来执行，该命令将破坏Online磁盘空间中所有原已存在的数据。当完成初始化任务后，Online将处于联机工作。

6． 执行管理工作 如果Online已经处于联机状态，用户就可以在Linux提示符下键入dbaccess命令对数据库进行管理操作了。

就安装的难易程度来看，免费的数据库软件MySQL的安装要复杂一些，Informix的安装相对容易。


informix

Web databases
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
Informix

http://www.informix.com
Informix information management solutions are open, scalable, manageable, and fully extensible — providing the kind of flexibility that is essential for growing organizations. From data warehousing, analysis and decision support, to Web content delivery, Informix products are engineered to enable today's businesses to efficiently manage any kind of information, anywhere, and at any time.

Informix Dynamic Server (IDS)
Best-of-breed, general purpose, mission-critical OLTP database for e-business

Informix OnLine 5
Easy OLTP for small to mid-size businesses

Informix SE
Zero-admin, embeddable, multiuser DBMS

Informix C-ISAM
Fast and cost-effective file management technology

Informix Extended Parallel Server (XPS)
Enterprise data warehousing

Red Brick Warehouse
Online data warehousing

Informix is now part of IBM.


lotus

LotusNotes/Domino
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase

Lotus Notes/Domino与办公自动化

Lotus Notes/Domino是业界公认的群件“鼻祖”和事实标准。自1989年12月发布第1.0版以来，已具备11年的发展历史，积累了丰富的经验。在电子邮件与群件市场，拥有最大的客户群或最大的市场份额。累计到1998年第一季度末，全世界已有三千万个客户使用Lotus Notes/Domino，与去年同期比较，增长率是80%。

Lotus公司在电子邮件市场拥有丰富的经验，其拥有的另外一项著名产品是Lotus cc:Mail。cc:Mail在全球的用户数达到一千二百万，是基于局域网的电子邮件系统产品之冠。Lotus正在将其在优点推广到基于广域网的邮件、群件产品的开发与推广之中，其中以Lotus Notes/Domino为代表，继续保持了在这一领域的领先地位。目前，国内许多政府机关和企事业单位都采用Lotus Notes/Domino作为办公自动化系统的基础平台。

Lotus Notes/Domino是电子邮件、文档数据库、快速应用开发技术以及Web技术为一体的电子邮件与群件平台。其目的是跨越地域、部门之间的界限，使得各行各业的工作人员传递、共享信息与知识，从而提高群组的工作效率。

Lotus Notes/Domino的主要功能

电子邮件与报文传递； 文档数据库系统；交互式的服务器； 网络应用开发工具、集成工具与实施工具

利用Domino/Notes建立的办公信息系统具的特点

集成性；开发快捷、实施容易；管理容易、机制完整；保有费用低；适应大规模、跨企业和机关部门的应用；开放性；可以获得厂商的丰富经验与支持。

办公自动化系统的应用

电子邮件和文件传输,综合信息服务 ,综合办公系统,Internet连接


lotus

LotusNotes
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
Lotus Notes R5 is the leading integrated e-mail and e-business software for the Internet and corporate intranets. An intuitive, Web-inspired environment, Notes integrates your highest priority information sources, including e-mail, calendaring, group scheduling, to do list and more. Notes users can exchange messages via the Internet, work with any Web application, read and post topics to Internet newsgroups, search Web directories, and use X.509 certificates for security. Notes even lets you access your e-mail and other applications while you're off-line -- with full fidelity -- and gives you the option to synchronize your work later.

Notes R5 also makes it easy for you to get started. Wizards automate the installation process, even creating dial-up networking entries. Users can choose from among pre-set setup configurations like Office and Home to get up and running in minutes. Familiar Web metaphors and an award-winning interface minimizes training costs while boosting users' productivity.

Tight integration with the Lotus Domino R5 Server makes Notes R5 the most powerful e-business client available, delivering unmatched functionality, security and customization options. Notes enables organizations to maximize the value of their Domino infrastructure -- from standards-based messaging to built-in collaborative applications like discussions and document libraries, to the unlimited potential of Domino-based e-business solutions. Together, Notes and Domino enable organizations to lower the total cost of a messaging and collaboration infrastructure, while enhancing users' productivity and reducing administrative overhead.

Key Features and Benefits

Much more than mail. Notes integrates your most important information sources -- e-mail, calendar, address book, to do list, the Web and e-business applications -- and lets you seamlessly access them on-line or off-line.

Instant e-business. The customizable Welcome Page presents the at-a-glance info you need including today's appointments, action items, key URLs and new e-mails.

Keeps it together. Notes offers a single, integrated in-box for Notes mail and Internet mail, from Internet Service Providers (ISPs).

New-instant messaging! Now with Lotus Sametime integration, Notes lets you see who's on-line, send them instant messages and even chat in real-time to get answers fast.

Features Overview

The Power of Integration with a Browser's Ease of Use.

Welcome Page. Like a home page for your personal information, the Welcome Page appears first when you launch Notes. In it, you can display your choice of up to five different information sources, including your e-mail in-box, your calendar, to do's, any Web page, and more. Companies can create their own Welcome Page with a standard look-and-feel, including logos, graphics and even dynamic information feeds for important news.

Window Tabs. To switch between information sources in Notes, just click the Window Tabs at the top of your screen.

Navigation Bar. Like the "Forward" and "Back" buttons on a Web browser, Notes gives you convenient tools for navigating your personal information. Click Refresh to update your view with the latest data; click Search to find information or Stop to cancel an action. To go to a Web page, just enter a URL.All without leaving Notes!

Advanced search. With Notes you can search your desktop, your company network and the Web. If you don't know the precise information you're looking for, Notes can find the closest match. Search summaries let you preview a document's contents before you open it.

Desktop directory. Notes lets you put the entire corporate Domino directory right on your desktop, in a highly compressed format. So you always have access to your colleagues' e-mail addresses, along with convenient features like type-ahead addressing.

Integrated Features for Information Management.

Get all your e-mail in one place. Support for Web standards make Notes R5 the one place in which to receive and manage all your e-mail, including Notes mail and mail from Internet Service Providers (ISPs). No more switching between in-boxes to find your new mail!

Convenient group scheduling. The new Group Calendar view allows you to see the free and busy time slots of your whole team at once (given appropriate access permission). And the details of each person's calendar are just a click away. So it's easy to manage multiple calendars and schedule appointments -- or delegate that responsibility. Calendar printing lets you create a hard copy of your schedule, in popular formats like daily, weekly, Daytimer and Franklin Planner styles.

The most secure e-business client. Full support for X.509 certificates and S/MIME let Notes users send and receive signed and/or encrypted messages via the Internet. Notes Execution Control Lists limit the actions that active Web content like Java applets and JavaScripts can perform on users' desktops. Just-in-time encryption lets you encrypt messages when off-line, without the need to store security information locally.

Actioneer integration. Developed by Actioneer, Inc., Actioneer for Notes R5 is an intelligent interface that simplifies and speeds up information entry and retrieval. Whether you're working in Notes or another application, Actioneer is always available to interpret simple phrases and automatically create entries in your Notes calendar, to do list and journal.

Wisdom for Notes Integration. Developed by Neural Solutions Pty. Ltd., Wisdom for Notes R5 determines a user's action and then provides context-sensitive help across the Notes Welcome Page, mail, calendar, replication and more. Wisdom for Notes is a learning tool that enables rapid productivity.

Accessibility. Software accessibility options built into Notes R5 enable all members of your team, whether abled or disabled, to be equally effective and productive.

Comprehensive Standards Support.

Mail standards. Full support for Internet mail, including POP3, IMAP4 and LDAP V3.s MIME, S/MIME, HTML, NNTP, Java, JavaScript and X.509 certificates.

Multi-platform support. Notes R5 runs on Windows 95, Windows 98, Windows 2000, Windows NT 4.0 Workstation; and Mac PowerPC 7.6 and 8.5.


SQL Server

网络数据库
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase

SQL Server 2000

http://www.microsoft.com
Microsoft SQL Server 2000

Overview
Microsoft SQL Server 2000 Enterprise Edition is the complete database and analysis offering for rapidly delivering the next generation of scalable e-commerce, line-of-business and data warehousing solutions.

Benefits
Fully Web-Enabled...Query, analyze and manipulate data over the Web. Use Extensible Markup Language (XML) in SQL Server 2000 to exchange data between loosely coupled systems. Access data easily and securely from a browser, through firewalls, and perform fast full-text searches of formatted documents. Analyze and link online analytical processing (OLAP) cubes, even over the Web. Perform clickstream analysis to learn about your Web customers.

Highly Scalable and Reliable...Grow without limits with enhanced scalability and reliability features. Partition your database workload to achieve scale-out of applications. Take full advantage of Symmetric Multiprocessing (SMP) hardware, and, with the Microsoft Windows 2000 Datacenter. Server operating system, support up to 32 CPUs and 64 GB of RAM.

Fastest Time-to-Market...Rapidly build, deploy, and manage e-commerce, line-of-business, and data warehousing solutions. Perform sophisticated data mining on customer and financial data. Reduce development time with the integrated T-SQL debugger, and develop your own functions that can be reused in different applications. SQL Server 2000 provides the fastest route to Web application development.

Record Benchmark

SQL Server 2000 posted world-record benchmarks that eclipsed the competition on multiple platforms. For details on the benchmarks, visit http://www.microsoft.com/sql/worldrecord


SQL Server

Web databases
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase

SQL Server 2000

http://www.microsoft.com
Microsoft SQL Server 2000

Overview
Microsoft SQL Server 2000 Enterprise Edition is the complete database and analysis offering for rapidly delivering the next generation of scalable e-commerce, line-of-business and data warehousing solutions.

Benefits
Fully Web-Enabled...Query, analyze and manipulate data over the Web. Use Extensible Markup Language (XML) in SQL Server 2000 to exchange data between loosely coupled systems. Access data easily and securely from a browser, through firewalls, and perform fast full-text searches of formatted documents. Analyze and link online analytical processing (OLAP) cubes, even over the Web. Perform clickstream analysis to learn about your Web customers.

Highly Scalable and Reliable...Grow without limits with enhanced scalability and reliability features. Partition your database workload to achieve scale-out of applications. Take full advantage of Symmetric Multiprocessing (SMP) hardware, and, with the Microsoft Windows 2000 Datacenter. Server operating system, support up to 32 CPUs and 64 GB of RAM.

Fastest Time-to-Market...Rapidly build, deploy, and manage e-commerce, line-of-business, and data warehousing solutions. Perform sophisticated data mining on customer and financial data. Reduce development time with the integrated T-SQL debugger, and develop your own functions that can be reused in different applications. SQL Server 2000 provides the fastest route to Web application development.

Record Benchmark

SQL Server 2000 posted world-record benchmarks that eclipsed the competition on multiple platforms. For details on the benchmarks, visit http://www.microsoft.com/sql/worldrecord


MySQL JDBC

MySQL
安装MySQL

假设你把所有必须的源码或者包都放在了/tmp下。如果你下载的是RPM包的话，那比较简单；如果你下载的是二进制包（你没有rpm程序或者你想自定义的话），那么会稍微麻烦一点。

RPM包安装

你必须成为root用户才能使用rpm安装程序，以下是安装过程：

$ cd /tmp
    $ su
    # rpm -Uvh MySQL*(安装和MySQL相关的所有包）

这将安装你下载的所有3个MySQL包。如果你的系统是RedHat Linux的话，建议使用RPM安装方式，因为所有的工作都由rpm程序帮你搞好了。

源码安装

相对于用RPM安装来讲，用二进制源码安装是稍微麻烦了点。但是我们可以在安装脚本中可以自定义安装的相关参数，而不用象rpm方式只能安装默认的来安装。

安装二进制源代码

如果你下载的是二进制源代码，它的名字类似于： mysql-3.22.21-pc-linux-gnu-i686.tar.gz。你必须成为root用户，然后解压到 /usr/local目录，操作步骤如下：

$ cd /usr/local
    $ su
    # tar -zxvf /tmp/mysql-3.22.21-pc-linux-gnu-i686.tar.gz

在所有文件解压完后，一个名字叫mysql-3.22.21-pc-linux-gnu-i686的目录将被创建出来。我们为这个目录做个符号链接，并给它一个更友好的名字mysql （免得叫mysql-3.22.21-pc-linux-gnu-i686这么长）：

# ln -s mysql-3.22.21-pc-linux-gnu-i686 mysql

如果以后有新版本的MySQL的话，你可以仅仅将源码解压到新的路径，然后只需要做个符号链接就可以了。这样非常方便，数据也更加安全。

建立一个MySQL 用户

好，现在我们将建立一个能运行MySQL守护程序的用户帐号，并且所有MySQL文件都归此帐户拥有。使用 Linuxconf或者useradd命令去添加一个叫 mysql 的帐号，在添加之前，确保没有人注册了这个帐户，还要暂时禁止login功能（不过一般都是在没有其他人登陆的情况下调试机器，因此这个步骤可免）

为MySQL做准备

首先让我们将MySQL目录和文件的拥有权改成 mysql 用户和root组：

# cd /usr/local
    # chown -R mysql:root mysql-3.22.21-pc-linux-gnu-i686 mysql

然后运行一个小脚本程序，以建立初始化的MySQL数据库。请以一个mysql 用户的身份完成这个任务，这也是我们能够直接使用这个帐户的唯一机会。

# su mysql
    $ cd mysql
    $ scripts/mysql_install_db
    $ exit

如果没有任何出错信息显示的话，那就可以了。

自动运行MySQL

在MySQL二进制包里面，有一个叫myslq.server的启动脚本程序。把它复制到/etc/rc.d/init.d目录里面：

# cd /etc/rc.d/init.d
    # cp /usr/local/mysql/support-files/mysql.server mysql

接着把它的属性改为“x”（executable，可执行）

# chmod +x mysql

最后，运行chkconfig把MySQL添加到你系统的启动服务组里面去。

# /sbin/chkconfig --del mysql
    # /sbin/chkconfig --add mysql

测试MySQL

MySQL里面有一个简单的数据库例子test ，而且它的内部数据库一直保持对权限和帐户的监视，因而先运行mysql看看是否可以工作。

首先启动MySQL：

# /etc/rc.d/init.d/mysql start

如果一切正常，你将看到以下的信息出现：

Starting mysqld daemon with databases from /var/lib/mysql

如果你安装的是RPM包，那么程序大都安装在/usr/local/mysql/bin。在此目录下运行客户端程序：

# mysql

然后你可以看到屏幕显示出以下信息：

Welcome to the MySQL monitor. Commands end with ; or \g.

Your MySQL connection id is 2 to server version: 3.22.21

Type 'help' for help.

mysql>

接着，用show databases命令可以将安装的数据库列出来：

mysql> show databases;

你就可以看到：

+----------+

| Database |

+----------+

| mysql |

| test |

+----------+

2 rows in set (0.00 sec)

如果一切正常的话，那说明MySQL可以完全工作了!恭喜你！如果要退出程序，输入：exit

mysql> exit;

Bye

更改管理员密码

在一切正常后，要做的第一件事情是更改管理员的密码。你可以运行mysqladmin （请注意，此命令不一定在你的path中，所以最好是转到此命令的目录中直接执行）： # mysqladmin -u root password newpassword

此命令把root用户的口令变成newpassword。当然你可以把口令换成其它，因为这个很容易破解。

MySQL的安装

---- 我们先介绍一下怎样安装MySQL数据库软件。

---- MySQL是近几年来非常流行的一个数据库软件，它的免费性和开放性特别适合于一些中小企业使用，人们可以到网站上下载免费的MySQL压缩文件（笔者下载的是mysql-3.22.21.tar文件）。下载之后，将该文件传输到装有Red Hat Linux的服务器上，再将文件上传到 /var/lib目录下，然后可以执行如下命令进行安装MySQL。

---- 1. tar -xvf mysql-3.22.21.tar （将文件解压到目录mysql-3.22.21下）

---- 2. cd /var/lib/ mysql-3.22.21 （进入MySQL的源文件目录）

---- 3. ./configure-prefix=/usr/local/mysql （运行配置文件，强制安装程序，并在后面的安装过程中使用/usr/local/mysql作为MySQL的安装目录）

---- 4. make （编译MySQL）

---- 5. make install （安装MySQL，该安装过程稍长，请耐心等待。如果在安装过程中出现错误提示，请重新安装）

---- 6. echo "/usr/local/mysql/lib/mysql" >> /etc/ld.so.conf （将MySQL库所在的目录添加进配置文件中。这样，当Linux启动或者执行ldconfig命令时，将会在该配置文件中的目录里搜索库文件）

---- 7. ldconfig -v|grep libmysqlclient （ldconfig命令能读取/etc/ld.so.conf文件列出的目录，并在那些目录里对找到的库文件进行缓冲。grep命令在ldconfig命令的大量输出结果中查找MySQL库文件）

---- 8. echo "/usr/local/mysql/bin/safe-mysqld" >/dev/null>> /etc/rc.d/rc.local （将MySQL启动指令添加到/etc/rc.d/rc.local文件中，这样每次启动Linux后就会自动运行MySQL）

---- 9. ./scripts/mysql_install_db （初始化数据库）

---- 10. /usr/local/mysql/bin/safe_mysqld> /dev/null& （启动MySQL服务器作为后台程序，为了测试安装，必须启动MySQL）

---- 下一步，我们需要测试MySQL是否安装成功。MySQL带有许多有用的工具，这里我们仅使用mysqladmin和mysqlshow命令来进行测试。mysqladmin的作用是建立和删除数据库、检查SQL的状态以及其他一些用途。首先，通过检查版本号确认是否已经正确安装了MySQL。

# cd /usr/local/mysql/bin

# ./mysqladmin version

运行结果如下：

./mysqladmin Ver 7.11 Distrib 3.22.21, for pc-linux-gnu on i586

TCX Datakonsult AB, by Monty

Server version 3.22.21
Protocol version 10
Connection Localhost via UNIX socket
UNIX socket /tmp/mysql.sock
Uptime: 64 days 9 min 27 sec

Threads: 1 Questions: 4 Slow queries: 0 Opens: 6Flush tables:
1 Open tabl2
其次，使用mysqlshow 命令列出数据库、表和字段名，结果如下：
+-----------+
| Databases |
+-----------+
| mysql |
| test |
+----------- +
---- 如果计算机能执行上面的2条命令，并能正确地显示结果，说明MySQL已经安装成功，接下来就可以使用它开始工作了。

JDBC 安装
Q： 我安装mysql的jdbc driver包mm.mysql....,并且已在CLASSPATH中包含了包所安装的目录，还把该包中的jar文件复制到TOMCAT_HOME目录下的classes，server.xml也加了相应的设置：

<RequestInterceptor
className="org.apache.tomcat.request.jdbcRealm"
debug="99"
driverName="org.gjt.mm.mysql.Driver"
connectionURL="jdbc:mysql://localhost/authority"
connectionName="root"
connetcionPassword="123456"
/>
但启动tomcat.sh start时仍然报错，信息如下：
FATAL:java.lang.RuntimeException: jdbcRealm.checkConnection: java.lang.ClassNotFoundException: org.gjt.mm.mysql.Driver

求教如何解决呢？

A： CLASSPATH要指到.jar, 而不能仅仅是.jar的目录

如果是解压开的，比如一个org目录，那CLASSPATH指到这个路径的上级； 如果是没有解压的jar，那要指到这个jar文件
Q： 我的环境为：
FreeBSD4.2
Tomcat4.0
linux-jdk1.3.1
Mysql-3.23
mm.mysql.jdbc-1.2c
我设置好了jdbc的CLASSPATH：
CLASSPATH=/usr/local/linux-jdk1.3.1/lib:/usr/local/linux-jdk1.3.1/jre/lib:/var/jakarta-tomcat-4.0/lib/mm.mysql.jdbc-1.2c

用以下代码测试没问题：
============================
<%@ page language="java" contentType="text/html;charset=gb2312" import="java.sql.*" %>
<%
out.println("test！");

try {
Class.forName("org.gjt.mm.mysql.Driver").newInstance();

}
catch (Exception E) {
out.println("Unable to load driver.");

}

但我用以下测试就有问题：
================================
<%@ page language="java" contentType="text/html;charset=gb2312" import="java.sql.*" %>
<%
out.println("test！");

try {
Class.forName("org.gjt.mm.mysql.Driver").newInstance();

}
catch (Exception E) {
out.println("Unable to load driver.");

}

try {
Connection C = DriverManager.getConnection("jdbc:mysql://localhost/tttt?user=root&password=&useUnicode=true&characterEncoding=8859_1");
Statement s=C.createStatement(ResultSet.TYPE_SCROLL_SENSITIVE,ResultSet.CONCUR_READ_ONLY);
ResultSet rs=s.executeQuery("select * from tttt");
out.println("<table border=1>");
int i=1;
for (i=10;i<20;i++)
{
if (rs.absolute(i))
{
out.println("<tr><td>");
out.println(rs.getString(1));
out.println("</td>");
out.println("<td>");
out.print(rs.getString(2));
out.println("</td>");
out.println("<td>");
out.print(rs.getString(3));
out.println("</td></tr>");
}
else
{
break;
}

}
out.println("</table>");
rs.close();
s.close();
C.close();

}
catch (SQLException E) {
out.println("SQLException: " + E.getMessage());
out.println("SQLState: " + E.getSQLState());
out.println("VendorError: " + E.getErrorCode());
}

%>

出错信息如下：
test！ SQLException: Server configuration denies access to data source SQLState: 08001 VendorError: 0

我的用户名和密码没问题。不知错在哪？
如果你是在tomcat下用jdbc, 把相应的.jar文件放在$TOMCAT_HOME/lib目录下就行了. tomcat在启动时会自动将该目录下的所有.jar文件加入CLASSPATH.

你究竟是作什么用, 如果是普通java application, 需将.jar文件设置到CLASSPATH中, 注意, 不是你下载的.jar, 下载的.jar解开后里面还有一个.jar
以我的配置为例:
我是从网上下的mm.mysql-2.0.6.1.jar, 将这个文件解开后, 里面有一个mm.mysql-2.0.6.jar, 设置为:
export CLASSPATH=$MMMYSQL_HOME/mm.mysql-2.0.6.jar:$CLASSPATH


MySQL

网络数据库
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
MySQL是一个真正的多用户、多线程SQL数据库服务器。SQL（结构化查询语言）是世界上最流行的和标准化的数据库语言。MySQL是以一个客户机/服务器结构的实现，它由一个服务器守护程序mysqld和很多不同的客户程序和库组成。

SQL是一种标准化的语言，它使得存储、更新和存取信息更容易。例如，你能用SQL语言为一个网站检索产品信息及存储顾客信息，同时MySQL也足够快和灵活以允许你存储记录文件和图像。

MySQL 主要目标是快速、健壮和易用。最初是因为我们需要这样一个SQL服务器，它能处理与任何可不昂贵硬件平台上提供数据库的厂家在一个数量级上的大型数据库，但速度更快，MySQL就开发出来。自1996年以来，我们一直都在使用MySQL，其环境有超过 40 个数据库，包含 10,000个表，其中500多个表超过7百万行，这大约有100 个吉字节(GB)的关键应用数据。

MySQL建立的基础是业已用在高要求的生产环境多年的一套实用例程。尽管MySQL仍在开发中，但它已经提供一个丰富和极其有用的功能集。
  • http://www.mysql.com/
  • http://www.gbnis.com 金桥信息服务网
  • http://www.pconline.com.cn/pcedu/empolder/db.htm 太平洋电脑网
    http://www.phpbible.com PHP宝典网
  • http://www.19do.com/技术联盟
  • http://clyan.hongnet.com/ SQL中文网


MySQL
安装MySQL

假设你把所有必须的源码或者包都放在了/tmp下。如果你下载的是RPM包的话，那比较简单；如果你下载的是二进制包（你没有rpm程序或者你想自定义的话），那么会稍微麻烦一点。

RPM包安装

你必须成为root用户才能使用rpm安装程序，以下是安装过程：

$ cd /tmp
    $ su
    # rpm -Uvh MySQL*(安装和MySQL相关的所有包）

这将安装你下载的所有3个MySQL包。如果你的系统是RedHat Linux的话，建议使用RPM安装方式，因为所有的工作都由rpm程序帮你搞好了。

源码安装

相对于用RPM安装来讲，用二进制源码安装是稍微麻烦了点。但是我们可以在安装脚本中可以自定义安装的相关参数，而不用象rpm方式只能安装默认的来安装。

安装二进制源代码

如果你下载的是二进制源代码，它的名字类似于： mysql-3.22.21-pc-linux-gnu-i686.tar.gz。你必须成为root用户，然后解压到 /usr/local目录，操作步骤如下：

$ cd /usr/local
    $ su
    # tar -zxvf /tmp/mysql-3.22.21-pc-linux-gnu-i686.tar.gz

在所有文件解压完后，一个名字叫mysql-3.22.21-pc-linux-gnu-i686的目录将被创建出来。我们为这个目录做个符号链接，并给它一个更友好的名字mysql （免得叫mysql-3.22.21-pc-linux-gnu-i686这么长）：

# ln -s mysql-3.22.21-pc-linux-gnu-i686 mysql

如果以后有新版本的MySQL的话，你可以仅仅将源码解压到新的路径，然后只需要做个符号链接就可以了。这样非常方便，数据也更加安全。

建立一个MySQL 用户

好，现在我们将建立一个能运行MySQL守护程序的用户帐号，并且所有MySQL文件都归此帐户拥有。使用 Linuxconf或者useradd命令去添加一个叫 mysql 的帐号，在添加之前，确保没有人注册了这个帐户，还要暂时禁止login功能（不过一般都是在没有其他人登陆的情况下调试机器，因此这个步骤可免）

为MySQL做准备

首先让我们将MySQL目录和文件的拥有权改成 mysql 用户和root组：

# cd /usr/local
    # chown -R mysql:root mysql-3.22.21-pc-linux-gnu-i686 mysql

然后运行一个小脚本程序，以建立初始化的MySQL数据库。请以一个mysql 用户的身份完成这个任务，这也是我们能够直接使用这个帐户的唯一机会。

# su mysql
    $ cd mysql
    $ scripts/mysql_install_db
    $ exit

如果没有任何出错信息显示的话，那就可以了。

自动运行MySQL

在MySQL二进制包里面，有一个叫myslq.server的启动脚本程序。把它复制到/etc/rc.d/init.d目录里面：

# cd /etc/rc.d/init.d
    # cp /usr/local/mysql/support-files/mysql.server mysql

接着把它的属性改为“x”（executable，可执行）

# chmod +x mysql

最后，运行chkconfig把MySQL添加到你系统的启动服务组里面去。

# /sbin/chkconfig --del mysql
    # /sbin/chkconfig --add mysql

测试MySQL

MySQL里面有一个简单的数据库例子test ，而且它的内部数据库一直保持对权限和帐户的监视，因而先运行mysql看看是否可以工作。

首先启动MySQL：

# /etc/rc.d/init.d/mysql start

如果一切正常，你将看到以下的信息出现：

Starting mysqld daemon with databases from /var/lib/mysql

如果你安装的是RPM包，那么程序大都安装在/usr/local/mysql/bin。在此目录下运行客户端程序：

# mysql

然后你可以看到屏幕显示出以下信息：

Welcome to the MySQL monitor. Commands end with ; or \g.

Your MySQL connection id is 2 to server version: 3.22.21

Type 'help' for help.

mysql>

接着，用show databases命令可以将安装的数据库列出来：

mysql> show databases;

你就可以看到：

+----------+

| Database |

+----------+

| mysql |

| test |

+----------+

2 rows in set (0.00 sec)

如果一切正常的话，那说明MySQL可以完全工作了!恭喜你！如果要退出程序，输入：exit

mysql> exit;

Bye

更改管理员密码

在一切正常后，要做的第一件事情是更改管理员的密码。你可以运行mysqladmin （请注意，此命令不一定在你的path中，所以最好是转到此命令的目录中直接执行）： # mysqladmin -u root password newpassword

此命令把root用户的口令变成newpassword。当然你可以把口令换成其它，因为这个很容易破解。

一、MySQL的安装

---- 我们先介绍一下怎样安装MySQL数据库软件。

---- MySQL是近几年来非常流行的一个数据库软件，它的免费性和开放性特别适合于一些中小企业使用，人们可以到网站上下载免费的MySQL压缩文件（笔者下载的是mysql-3.22.21.tar文件）。下载之后，将该文件传输到装有Red Hat Linux的服务器上，再将文件上传到 /var/lib目录下，然后可以执行如下命令进行安装MySQL。

---- 1. tar -xvf mysql-3.22.21.tar （将文件解压到目录mysql-3.22.21下）

---- 2. cd /var/lib/ mysql-3.22.21 （进入MySQL的源文件目录）

---- 3. ./configure-prefix=/usr/local/mysql （运行配置文件，强制安装程序，并在后面的安装过程中使用/usr/local/mysql作为MySQL的安装目录）

---- 4. make （编译MySQL）

---- 5. make install （安装MySQL，该安装过程稍长，请耐心等待。如果在安装过程中出现错误提示，请重新安装）

---- 6. echo "/usr/local/mysql/lib/mysql" >> /etc/ld.so.conf （将MySQL库所在的目录添加进配置文件中。这样，当Linux启动或者执行ldconfig命令时，将会在该配置文件中的目录里搜索库文件）

---- 7. ldconfig -v|grep libmysqlclient （ldconfig命令能读取/etc/ld.so.conf文件列出的目录，并在那些目录里对找到的库文件进行缓冲。grep命令在ldconfig命令的大量输出结果中查找MySQL库文件）

---- 8. echo "/usr/local/mysql/bin/safe-mysqld" >/dev/null>> /etc/rc.d/rc.local （将MySQL启动指令添加到/etc/rc.d/rc.local文件中，这样每次启动Linux后就会自动运行MySQL）

---- 9. ./scripts/mysql_install_db （初始化数据库）

---- 10. /usr/local/mysql/bin/safe_mysqld> /dev/null& （启动MySQL服务器作为后台程序，为了测试安装，必须启动MySQL）

---- 下一步，我们需要测试MySQL是否安装成功。MySQL带有许多有用的工具，这里我们仅使用mysqladmin和mysqlshow命令来进行测试。mysqladmin的作用是建立和删除数据库、检查SQL的状态以及其他一些用途。首先，通过检查版本号确认是否已经正确安装了MySQL。

# cd /usr/local/mysql/bin

# ./mysqladmin version

运行结果如下：

./mysqladmin Ver 7.11 Distrib 3.22.21, for pc-linux-gnu on i586

TCX Datakonsult AB, by Monty

Server version 3.22.21
Protocol version 10
Connection Localhost via UNIX socket
UNIX socket /tmp/mysql.sock
Uptime: 64 days 9 min 27 sec

Threads: 1 Questions: 4 Slow queries: 0 Opens: 6Flush tables:
1 Open tabl2
其次，使用mysqlshow 命令列出数据库、表和字段名，结果如下：
+-----------+
| Databases |
+-----------+
| mysql |
| test |
+----------- +

---- 如果计算机能执行上面的2条命令，并能正确地显示结果，说明MySQL已经安装成功，接下来就可以使用它开始工作了。

---- MySQL是一个很好的数据库软件，但是它的许多性能比起大型的数据库软件Informix来说不够完善。Informix采用了动态可伸缩体系结构作为其核心系统，做到了系统核心的并发处理，能充分利用硬件的性能，并具有极大的可伸缩性。为了适应电子商务的发展，Informix公司将从数据库解决方案平滑地过渡到基于数据库技术的电子商务和商务智能领域。


MySQL
Installing MySQL rpms:

install as root:

#rpm -ivh MySQL-3.22.32-1.i386.rpm

#rpm -ivh MySQL-client-3.22.32-1.i386.rpm

#rpm -ivh MySQL-devel-3.22.32-1.i386.rpm

#rpm -ivh MySQL-shared-3.22.32-1.i386.rpm

Start MySQL

# scripts/mysql_install_db //init database

# service mysqld start/stop

#/usr/local/mysql/bin/safe_mysqld --user=root &

#/usr/local/mysql/bin/mysqladmin -u root -p password yourpass //change your password

# mysql -u root -p mysql

#password //input your password

Welcome to the MySQL monitor. Commands end with ; or \g.

Your MySQL connection id is 2 to server version: 3.22.21

Type 'help' for help.

#mysql>

#mysql> show databases;

+----------+

| Database |

+----------+

| mysql |

| test |

+----------+

2 rows in set (0.00 sec)

#mysql> exit;

Bye
JDBC drive
add your drive files (ending with .jar or .bin) to your classpath
test code
================================
<%@ page language="java" contentType="text/html;charset=gb2312" import="java.sql.*" %>
<%
out.println("test！");

try {
Class.forName("org.gjt.mm.mysql.Driver").newInstance();

}
catch (Exception E) {
out.println("Unable to load driver.");

}

try {
Connection C = DriverManager.getConnection("jdbc:mysql://localhost/tttt?user=root&password=&useUnicode=true&characterEncoding=8859_1");
Statement s=C.createStatement(ResultSet.TYPE_SCROLL_SENSITIVE,ResultSet.CONCUR_READ_ONLY);
ResultSet rs=s.executeQuery("select * from tttt");
out.println("<table border=1>");
int i=1;
for (i=10;i<20;i++)
{
if (rs.absolute(i))
{
out.println("<tr><td>");
out.println(rs.getString(1));
out.println("</td>");
out.println("<td>");
out.print(rs.getString(2));
out.println("</td>");
out.println("<td>");
out.print(rs.getString(3));
out.println("</td></tr>");
}
else
{
break;
}

}
out.println("</table>");
rs.close();
s.close();
C.close();

}
catch (SQLException E) {
out.println("SQLException: " + E.getMessage());
out.println("SQLState: " + E.getSQLState());
out.println("VendorError: " + E.getErrorCode());
}

%>


MySQL

Web databases
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase

The MySQL database server is the world's most widely used open source database. Its ingenious software architecture makes it extremely fast and easy to customize. Extensive reuse of code within the software and a minimalistic approach to produce functionally rich features have resulted in a database management system unmatched in speed, compactness, stability and ease of deployment. The unique separation of the core server from the table handler makes it possible to run MySQL under strict transaction control or with ultrafast transactionless disk access, whichever is most appropriate for the situation.

from www.mysql.com
MORE ...
  • http://www.mysql.com/
  • http://www.gbnis.com
  • http://www.pconline.com.cn/pcedu/empolder/db.htm
    http://www.phpbible.com
  • http://www.19do.com/
  • http://clyan.hongnet.com/


OpenBASE

网络数据库
DM3
IBase
Kingbase
OpenBase
PandaSQL
OpenBASE
东方软件有限公司商用中间件技术公司 -http://www.commerceware.com.cn/
  • OpenBASE Mini 嵌入式数据库系统

  • OpenBASE Secure 安全数据库系统

  • OpenBASE多媒体关系数据库管理系统

  • Open Miner 数据挖掘工具


OpenBASE

Web databases
DM3
IBase
Kingbase
OpenBase
PandaSQL
OpenBASE
http://www.commerceware.com.cn/

OpenBASE is the first database management system with a Chinese copyright. It provides the same capabilities as other popular database management system at a very competitive price. OpenBASE is a high-performance tool that satisfies the data management needs of a wide variety of online transactions. It can be used to develop many applications including MIS, OA, GIS, Internet/Intranet. It is designed especially for the domestic market and has great potential for use in industry and government.

Features:
Multi-layer architecture fits Internet/Intranet applications
Reliable transaction processing insures the integrity and security of data
Powerful real-time processing ability
Fits many kinds of OLTP
Supports ODBC and JDBC, and has reliable interfacing
Wide variety of application programming interfaces
Advanced solutions for Web applications

Typical applications:
"SEAS" Super Electronic Archive System
"OpenVideo" Video-on-demand System
"HIS" Hospital Information System
"CREPS" Realty Management Information System
Marketing Intranet for ChongQing TaiJi Group
Public Multimedia Service System for ZheJiang XiaoShan
Multimedia Video-on-demand for WeiHai CATV
Multimedia Teaching System for PanJin High School


ORACLE
RedHat7.0, Redhat Linux 7.1
Oracle8iR2(oracle8.1.6), Oracle 8i(8.1.5)企业版
1.机器配置：

内存是关键，最好128M以上。

硬盘分区
Oralcel建议SWAP交换分区为400M或2倍于当前使用的系统物理内存，当然越大越好。
分区时划定两个安装点，/u01(用于安装ORALCE软件)和/u02（用于存放数据库数据），/u01分区的大小:
典型安装 750MB
最小安装650MB
自定义安装 1000MB

这两个安装点可以在安装时划定或完成系统安装后在"/"目录或别的目录下建立

安装必须具备：（安装RedHat7.0时选择完全安装）
1.X Windows
2.Development packages(c,gcc等)

2.安装所需软件

Oracle8161_tar.gz（275M，文件较大，下载前做好心理准备，我第一次花了一整天弄下来却是个坏的，展不开，差点气死！只好又下载了一次，还不如去买张盗版光盘呢）。下载网址：
ftp://166.111.136.3/pub/DataBase/Oracle/oracle8161.tar.gz（清华酒井）
http://technet.oracle.com/software/products/oracle8i/software/index.htm

http://technet.oracle.com/software/products/oracle8i/software_index.htm

glibc2.1版本（GNU C Library，18M）下载地址：
ftp://ftp.kernel.org/pub/software/libs/glibc/hjl/sdk/2.1/i386-glibc-2.1-linux.tar.gz
http://ftp.valinux.com/pub/support/hjl/glibc/sdk/2.1/i386-glibc-2.1-linux.tar.gz

下载后都放到了/backup目录

???

我在这个帖子里没有提设DISPLAY变量的问题，其实如果在本机的X下安装oracle，会有默认设置的，根本不需要自己再设了。
如果runInstaller报DISPLAY出错的话，就自己设一下好了，无非就是
export DISPLAY=192.168.0.1:0.0 （假设IP是192.168.0.1）

如果这样做了，联接系统库的时候还报make错误的话（我是从来没有遇到这样的make error问题，所以没有办法测试），可能就不是glibc的问题，而是ld这些命令的版本问题了。我建议如果出现这种错误的话，试试这个方法，就是再降级binutil。

先下载binutils-2.10.0.18-1.i386.rpm(下载网址：http://rpmfind.net/linux/RPM/redhat/7.0/i386/binutils-2.10.0.18-1.i386.html，或者在google上搜索一下）
rpm -Uvh binutils-2.10.0.18-1.i386.rpm --force --nodeps

然后再runInstaller。
又或者虽然出现make error，但是毕竟可以拷贝文件安装过去的话，也可以试试这个方法：

在安装文件完成以后，会先后出现配置Net8和出现数据库助手创建数据库的过程。
（如果配置Net8出错的话，可以就这样退出，自己手工修改$ORACLE_HOME/network/admin下的listener.ora和tnsnames.ora。）
在出现数据库助手创建数据库的时候，不要创建数据库，退出。因为此时联接的可执行程序有问题，不能正确创建数据库。
到Oracle网站，在下载Oracle8.1.7的地方，可以找到一个glibc的patch：
http://download.oracle.com/otn/linux/oracle8i/glibc-2.1.3-stubs.tar.gz
把它下载，放到$ORACLE_HOME下，解压缩，
cd $ORACLE_HOME
tar xvfz glibc-2.1.3-stubs.tar.gz
./setup_stubs.sh
然后再
dbassist
启动数据库创建助手，创建数据库。

附件是我的/etc/profile和oracle的.bash_profile，请参考

3.Glibc

本质来说，RedHat7.1的glibc2.2库和其他相关工具对于Oracle8i来说，是有一点高了。所以一般都要用RedHat7.1自带的兼容RedHat6.2的库替换一下，也就是glibc2.1.3。
我自己的经验是只要正确替换了glibc，就一定可以安装成功，不用做别的工作。一定要把那几个compat的rpm软件包安装好，正确替换，再用gcc -v试试，确定是在用compat glibc2.1.3，再开始安装。

RPM 包

首先要安装RedHat7.1安装光盘上的几个以compat开头的rpm包，它们是：
compat-glibc-6.2-2.1.3.2.i386.rpm
compat-egcs-objc-6.2-1.1.2.14.i386.rpm
compat-egcs-6.2-1.1.2.14.i386.rpm
compat-libs-6.2-3.i386.rpm
可以把：
compat-libstdc++-6.2-2.9.0.14.i386.rpm
compat-egcs-c++-6.2-1.1.2.14.i386.rpm
也安装上。

因为这几个软件包之间有依赖关系，如果安装顺序不对，会报错的，无法安装。一般来说应该先安装第一张上的两个，再安装第二张上面的四个。

如果这样做也报错，安装不上，可以先把这6个软件包拷贝到一个目录下，然后再一起安装，这样就不用怕它们之间的依赖关系，一定可以安装成功了。例如：
rpm -ivh compat-glibc-6.2-2.1.3.2.i386.rpm compat-egcs-6.2-1.1.2.14.i386.rpm compat-libs-6.2-3.i386.rpm compat-egcs-c++-6.2-1.1.2.14.i386.rpm compat-egcs-objc-6.2-1.1.2.14.i386.rpm compat-libstdc++-6.2-2.9.0.14.i386.rpm

TAR。GZ包

以root帐号登录
[root@only_you /root] cd /
[root@only_you /] tar zxvf /backup/i386-glibc-2.1-linux.tar.gz
隐藏/usr/bin 目录下的gcc,cc,ld，避免被Oracle installer使用
[root@only_you /] cd /usr/bin
[root@only_you bin] mkdir saved
[root@only_you bin] mv gcc cc ld saved
[root@only_you bin] ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-gcc gcc
[root@only_you bin] ln -s gcc cc
[root@only_you bin] ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-ld ld
隐藏/usr/lib目录下的libc.so,libdl.so,libm.so和libpthread.so文件，避免被Oracle installer使用
[root@only_you bin] cd ../lib
[root@only_you lib] mkdir saved
[root@only_you lib] mv libc.so libdl.so libm.so libpthread.so saved
[root@only_you lib] mv libc.a libdl.a libm.a libpthread.a saved

安装相应的egc包。

假定安装光盘mount在/mnt/cdrom上，用命令modprobe isofs使操作系统能处理光盘的文件系统，然后运行mount －t iso9660 /dev/cdrom /mnt/cdrom，如在安装后修改了/etc/fstab，可不进行这一步操作。进入相应的RPMS目录，安装以egc开始的包，采用的安装命令为rpm －ivh <包名>。

4. 系统用户和安装目录的建立

在Oracle的技术文档中建议为数据库建立两个组——oinstall、dba，但在实际使用中笔者发现只要建一个dba组就可以顺利安装Oracle，而不影响系统的使用；需要为数据库增加一个用户oracle，它属于dba组；再建立/u01/app/oracle/8.1.6目录，并把它的所有者设为oracle.dba。

创建用户和组

groupadd dba
useradd oracle -g dba
passwd oracle (设密码)
Oracle安装文档上说，要创建两个组，oinstall和dba，oracle用户主属组是oinstall，从属组是dba，其实只用dba就好了，不要那么麻烦。

###################建立二个组##############################################################
以root帐号登录,开启一个terminal窗口,创建oinstall和dba组
[root@rh70 /root]groupadd oinstall
[root@rh70 /root]groupadd dba
创建oracle帐号,以oinstall为primary组，dba为secondary组
[root@rh70 /root]useradd oracle -g oinstall -G dba
[root@rh70 /root]passwd oracle (设置oralce帐号的密码)

##########################################################################################
创建Oracle软件安装目录

[root@rh70 /root]mkdir /u01/app/oracle/product/8.1.6
修改所创建目录的所属组及拥有者
[root@rh70 /root]chown -R oracle:dba /u01/app/oracle/product/8.1.6
[root@rh70 /root]chown -R oracle:dba /u02

5.设置oracle环境和数据文件目录

使用oracle帐号登录，开启terminal窗口
利用umask指令查看umask是否为022，若不是022，则需要把指令umask 022加到/home/oracle/.bash_profile文件中。
[oracle@rh70 oracle]umask

可以将要设的环境变量放在oracle用户主目录下的.bash_profile中，也可以放在/etc/profile中，对所有的用户可见，我建议放在/etc/profile中，因为凡是在本机运行的程序读写本机的Oracle数据库，一般都需要设Oracle的环境变量，否则无法连接数据库。
我可以举一个例子：
如果你的WEB Server，例如Apache，需要读写数据库，提供网页的动态内容，假设用PHP或者JSP，又或者Perl等等来写ServerAPI或者CGI，因为Apache是以root启动一个进程，这个进程再fork若干子进程以nobody用户运行，响应80端口的http请求，所以如果在root读不到Oracle环境变量，Web程序根本无法读写数据库。只要root读到oracle环境变量，fork子进程的时候，复制了父进程的数据空间，也继承了父进程的环境变量，所以可以读到oracle变量，就可以读写oracle数据库了。

打开终端窗口，以oracle账号登录
使用文本编辑器打开/home/oracle/.bash_profile,加入如下环境变量的设置行：
#ORA_NLS=/u01/app/oracle/product/8.1.6/ocommon/nls/admin/data
#export ORA_NLS
#NLS_LANG="simplified chinese"
#export NLS_LANG
ORACLE_BASE=/u01/app/oracle
export ORACLE_BASE
ORACLE_HOME=/u01/app/oracle/product/8.1.6
export ORACL_HOME
ORACLE_SID=ora1 (自定义，最好不要超过四个字符)
export ORACLE_SID
CLASSPATH=/u01/app/oracle/product/8.1.6/jdbc/lib/calsses111.zip
export CLASSPATH
LD_LIBRARY_PATH=/u01/app/oracle/product/8.1.6/lib
export LD_LIBRARY_PATH
USERNAME="oracle"
PATH=$PATH:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/dbs
PATH=$PATH:/bin:/usr/bin:/usr/sbin:/usr/local:/usr/local/bin:/usr/bin/X11:/usr/X11R6/bin
Log out,重新以oracle帐号登录，开启terminal窗口，键入env指令查看刚才设置的环境变量。

其中$ORACLE_BASE,$ORACLE_HOME指定安装目录，$ORACLE_SID是oracle数据库的SID，$ORA_NLS是字符集目录，$NLS_LANG是字符集，$CLASSPATH是Java程序读写数据库需要的JDBC的class，前面加个点号是先搜当前目录的意思。$LD_LIBRARY_PATH是Oracle的C库函数和头文件的位置，对于OCI8，PROC和JDBC的OCI连接是必须的。

注销再登录，或者不用注销，执行下一行的命令，直接读一下/etc/profile
. /etc/profile

再
env|grep oracle
看看oracle的变量是否都设置正确。

    ＃ /etc/profile

    ＃ System wide environment and startup programs

    ＃ Functions and aliases go in /etc/bashrc

    JAVA—HOME=/usr/local/jdk1.1.3

    SYBASE=/opt/sybase－11.9.2

    DSQUERY=SYBASERDBMS

    ＊PATH=＄PATH:＄JAVA—HOME/bin:/usr/X11R6/bin:/home/oracle/product/8.0.5/bin

    PS1=″u@h:w＄″

    ulimit －c 1000000

    if [ ′id －gn′ = ′id －un′ －a ′id －u′ －gt 14 ]; then umask 002

    else umask 022

    fi

    USER=′id －un′

    LOGNAME=＄USER

    MAIL=″/var/spool/mail/＄USER″

    CLASSPATH=/usr/local/jdk1.1.3/lib:＄HOME/bin

    HOSTNAME=′/bin/hostname′

    HISTSIZE=1000

    HISTFILESIZE=1000

    export JAVA—HOME CLASSPATH SYBASE DSQUERY

    export PATH PS1 HOSTNAME HISTSIZE HISTFILESIZE USER LOGNAME MAIL

    ＊ORACLE—HOME=/home/oracle/product/8.0.5

    ＊ORACLE—BASE=/home/oracle

    ＊ORACLE—OWNER=oracle

    ＊ORACLE—SID=oracle8

    ＊ORACLE—TERM=386

    ＊LD—LIBRARY—PATH=/home/oracle/product/8.0.5/lib

    ＊TMPDIR=/var/tmp

    ＊export ORACLE—HOME ORACLE—BASE ORACLE—OWNER ORACLE—SID ORACLE—TERM

    export LD—LIBRARY—PATH TMPDIR

    for i in /etc/profile.d/.sh ; do

     if [ －x ＄i ]; then . ＄i

     fi

    done

    unset i

6.解压缩oracle8161_tar.gz 软件包(275M)

以Root用户登录进入系统，创建用户oracle和组dba，这是Oracle默认的安装用户。创建安装用户后，用tar －xvzf 将压缩文件解压到一个指定的目录，本文假定为/oracle，因为tar进行数据归档与用户本机的用户ID、组ID不同，所以要运行chown －R oracle:dba 以更改文件属性。

假如我把oracle8iR2放在/home/test下面,以root身份登录
生成Oralce8iR2目录，内含解包后的文件，并让oracle账号可访问。
---------------------------------------------------------------
[root@xinli test]tar zxvf oracle8161_tar.gz
[root@xinli test]chown oracle test
---------------------------------------------------------------

8.系统内核的修改
由于Oracle本身对共享段的要求，用户必须重新手工生成核心，以便共享段的设定满足安装要求。为生成核心，用户应当安装Linux操作系统的源代码，编辑/usr/src/linux/include/shmparam.h，将＃define SHMMAX 0x002000000一行的0x002000000(32MB)改为256MB以上，然后在/usr/src/linux下运行make dep、make clean、make bzImage生成核心，使用linuxconf命令将新核心设为启动核心。这一步一定要做，如果生成的新核心有错，可以用原来的核心启动计算机。可用ipc －ml查看共享段的设置是否满足要求。当共享段大于2GB时，查看到的值是负数。
系统内核的修改

    对/usr/src/linux/include/asm/hmparam.h文件作如下修改：

被修改量 修改后数值
shmmax 内存大小*0.5
shmmin 1
shmmni 100
shmseg 10

    对/usr/src/linux/include/linux/sem.h文件作如下修改：

被修改量 修改后数值
semmni 100
semmsl processes参数+10
segmns 所有数据库processes参数总和+10

semopm 100
semvmx 32767

    参数修改完后，用“make dep”、“make clean”、“make bzImage”命令重新编译内核，并用新内核启动计算机。

命令ipcs -al可以查看共享内存参数，命令ipcs查看共享内存使用情况。

修改内核参数可以修改内核源码再重新编译内核，这个方法有点麻烦，关于共享内存的参数在源码目录下的include/linux/下的shm.h和sem.h文件中。

另一个简单的办法是直接修改内核参数，即修改/proc下的文件，立即生效。
可以修改/proc/sys/kernel下的shmmax和sem
shmmax是以字节记的共享内存段的最大尺寸，
shmmni是共享内存段的最大数量
shmmax是共享内存总共最大容量（shmmax*shmmni)
sem是信号量参数，msgmax，msgmnb，msgmni是消息队列的参数。

我改动如下：

echo 134217728 > /proc/sys/kernel/shmmax （SGA最大为128M）
echo -e "250\t32000\t100\t128" > /proc/sys/kernel/sem
（其实也不用改这项，只是将max ops per semop call改大了，这是Oracle的安装文档上写的，我就这么做了，不过我试过，不改也没事，其他都保持原来的，没有改）

总结如下：改一项必须的shmmax，其他的我在使用过程中，参数都够大了，不需要再调整。

9.安装oracle软件

在服务器上打开一个终端窗口（默认root身份）
---------------------------------------------------------------

设置xhost

开启一个新的terminal窗口
[oracle@only_you oracle]su - (输入root密码)
[root@only_you /root] xhost +
保留此窗口

[root@xinli /root]xhost +
---------------------------------------------------------------
再在服务器上打开另一个终端窗口
---------------------------------------------------------------
[root@xinli /root]su – oracle
[oracle@xinli /ora8]cd /home/test/Oracle8iR2
[oracle@xinli Oralce8iR2]./runInstaller
---------------------------------------------------------------

有的时候runInstaller，安装界面不出来，这主要还是因为Oracle的字符集设为了简体中文，但OS是英文的，所以有时候出不来，用Java写的程序经常出现字符集的问题。此时临时销毁$NLS_LANG变量，Java会用默认的字符集，就好了。所以：

unset $NLS_LANG

也可以试试

unset $LANG
× 其实dbassist也是有时候出不来的，这样做就可以出来了，但是netasst始终出不了，不清楚为什么，不过可以自己修改lisener.ora和tnsnames.ora，所以netasst也不是必须的。

另一个可能的原因就是glibc没有替换好，我发现直到JDK1.3.1_01，才支持glibc2.2，之前的版本，包括JDK1.3.0都不支持glibc2.2，只要在glibc2.2下运行，就会出现没有任何反应，进程好像死亡了一样的毛病，Oracle安装程序用的还是JRE1.1.8，所以只要glibc用的还是2.2版的，安装窗口总不会出来的。

此时弹出oracle的安装界面，按照提示一步步next下去即可。

注意：
在File Locations界面上，检查Destination Path为/ora8

在提示输入global database name时编一个名字如xinli， ORACLE_SID为ora8（与.bsah_profile相同）

提示输入db files localtion,输入/oradata

在Unix Group Name窗口中，键入"db"

当弹出提示要求以root身份运行/ora8/orainstRoot.sh 时，
切换到刚才保留的root用户窗口
---------------------------------------------------------------
[root@xinli /root] cd /ora8
[root@xinli ora8]./orainstRoot.sh
---------------------------------------------------------------
然后返回刚才弹出的窗口，点击Retry。

到选择安装“服务器”，“网络管理工作站”，“客户端”的时候，选择“服务器”
安装好以后，可以再回到这个画面来选择别的没有安装的组件，也随时可以启动runInstaller来安装别的组件。
另外有人提到没有安装PORC的选项，其实PROC是在“客户端”的选项里安装的。

然后选择“定制安装”，不要选择典型安装，因为典型安装会安装Oracle Jserver，实际上不太用到Jserver，而且安装Jserver是在SGA里要启动一个Java虚拟机，非常消耗资源（Java的东西总是很吃资源的），而且安装的时候创建Jserver的过程非常的漫长，一度令我怀疑死机了。

出现选择安装组件的列表，可以自己增删一些组件，我不需要oracle的Apache Server，准备自己从源码安装，所以就勾掉了。如果要安装Apache Server的选项话，要预先安装Java，并设置$JAVA_HOME变量，虽然要求的是jdk1.1.8，不过用jdk1.3也完全可以安装成功，运行Apache也没有什么问题，至于会不会因为jdk的版本不同导致一些程序运行结果的差异，我就没有测试过了。

还是选择安装组件的列表这个界面，有个选择语言的按钮，增加“简体中文”

询问是否创建数据库，“是”，添上安装数据库的SID，我的是“orcl”，数据库数据文件的存放目录，我的是“/u02“。

开始安装Oracle，安装程序拷贝文件。
有很多人说，拷贝文件完后，联接系统库函数的时候，出现make错误，我想这多半还是替换glibc不成功导致的吧，我安装的时候确实没有出现过这样的问题。我想按照我写的步骤来，应该不会出现这样的问题的。

完成后，提示以root运行root.sh。
Oracle8.1.7有两个版本，一个是Oracle8.1.7.0.0，另一个是Oracle8.1.7.0.1，这个版本带OPS，而且Oracle提供了一个glibc2.2的patch，不过在Redhat7.1上，按照上面方法做了以后，实际上不需要打补丁的。这个Oracle8.1.7.0.1的版本此时的root.sh有个bug，应该在第156行，如下：
RUID=`/usr/bin/id|$AWK -F\( '{print $2}'|$AWK -F\) '{print $1}`
在最后少写个‘
应该改为：
RUID=`/usr/bin/id|$AWK -F\( '{print $2}'|$AWK -F\) '{print $1}'`

运行它，生成/etc/oratab。

自动启动netasst，配置监听器，一般如果为了省事，选典型配置就可以了，只不过典型配置打开了一个2481端口，是JServer用的，如果不用JServer的话，也可以不要它，现在可以不用管它，回头再改listener.ora好了。

自动启动dbassist，安装数据库，按照提示做就是了，根据自己的情况可以适当的调整安装数据库时的参数，最后开始创建数据库，此时也可以选择先保存创建的脚本，再退出dbassist，单独运行创建脚本，这样更灵活一些，可以自己改创建脚本，也可以自己研究一下脚本，会有收获的。

19.安装后配置

1、以root登录，修改/etc/oratab，将最后的：
orcl:/u01/app/oracle/product/8.1.7:N
改为：
orcl:/u01/app/oracle/product/8.1.7:Y
这样就可以用dbstart和dbshut来启动和关闭数据库了，不用自己写脚本调svrmgrl。

2、将数据库启动命令和修改内核命令放在系统启动脚本中

修改/etc/rc.d/rc.local,加入：

#modify kernel parameter
echo 134217728 > /proc/sys/kernel/shmmax
echo -e "250\t32000\t100\t128" > /proc/sys/kernel/sem

#start Oracle8.1.7
su - oracle -c 'lsnrctl start'
su - oracle -c 'dbstart'

我比较懒，没有另外写脚本联接进rc3.d,rc0.d.rc5.d,rc6.d了，而是直接放在rc.local中了，呵呵
注意的是修改内核参数必须在启动数据库实例之前，启动数据库后，用ipcs 命令看看共享内存的使用情况，如果没有分段就行了。

另外一个特别要说明的事情是一定要注意，凡是读写数据库的进程，必须取得oracle的环境变量，否则无法联接数据库。
上面的脚本中su - 中的这个"-"非常讲究，它的意思是切换到oracle用户，并取得oracle的环境变量。
再例如，如果还要启动apache来读写数据库的话，rc.local加入的命令就一定要这样写：
#start apache httpd server
. /etc/profile
/usr/local/apache/bin/apachectl start

因为我把oracle的环境变量放在/etc/profile里了，在启动apache之前要先强制它读/etc/profile，取得oracle的环境变量，这样apache的ServerAPI程序就可以读写数据库了。

3、修改Net8配置，可以用netca，或者自己修改$ORACLE_HOME/network/admin下的listener.ora和tnsnames.ora，netasst好像出不来。

4、如果创建第二个实例，用dbassist就好了，如果dbassist出不来的话，临时销毁$LANG,$NLS_LANG
unset $NLS_LANG
unset $LANG
就可以出来了。

11.安装完成后会有两个缺省的数据库管理员用户：

ｓｙｓ，口令是ｃｈａｎｇｅ＿ｏｎ＿ｉｎｓｔａｌｌ；ｓｙｓｔｅｍ，口令是ｍａｎａｇｅｒ。从系统安全的角度考虑，建议用户要做的第一件事就是更改这两个用户的口令，方法是启动数据库后在ＳＱＬＰｌｕｓ中修改，具体方法后面会提到。

12.用svrmgrl管理或用其他在windows下的管理工具测试管理。

要用客户机登录，就要设置好listener.ora,可参考其他文档。
Svrmgrl要求对命令比较了解才行，不太方便。
Oracle8 client软件（windows下的）中的Oracle Enterprise Manager挺不错的，全是交互式图形化管理界面，很容易操作。Oracle8 client可到
http://download.oracle.com/otn/nt/oracle8i/win817client.zip下载（213M,好大，还须先注册otn账号才行）。
[以上为本人实际经验，参照其他网友文章所写，水平有限，错误之处，在所难免，欢迎指正]

[oracle@only_you oracle] svrmgrl
Oracle Server Manager Release 3.1.6.0.0 - Production
Copyright (c) 1997, 1999, Oracle Corporation. All Rights Reserved.
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SVRMGR>connect internal
Connected.
SVRMGR> shutdown
Database closed.
Database dismounted.
ORACLE instance shut down.
SVRMGR>startup
ORACLE instance started.
Total System Global Area 56012784 bytes
Fixed Size 69616 bytes
Variable Size 38993920 bytes
Database Buffers 16777216 bytes
Redo Buffers 172032 bytes
Database mounted.
Database opened.
SVRMGR> quit
Server Manager complete.

不错，看来可以正常工作了。再用sqlplus试试

[oracle@only_you oracle]$ sqlplus
SQL*Plus: Release 8.1.6.0.0 - Production on Sun Apr 15 09:20:12 2001
(c) Copyright 1999 Oracle Corporation. All rights reserved.
Enter user-name: scott
Enter password: tiger
Connected to:
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SQL> select * from emp
应该出来一堆数据，有14条，看来没问题了。
SQL>quit

如果用户是在客户端对数据库进行操作的话事情会稍微麻烦一些：首先数据库服务器端要对端口进行监听，收到请求后客户端才能与服务器端建立连接，服务器端监听的方法是运行下面命令：lsnrctl start；然后客户端用户要通过NET8建立一个服务名称，用来与服务器端进行连接；最后才能通过客户端软件，比如客户端SQLPlus对数据库进行操作。

任何事情只要你掌握了它的关键也就不会觉得难了。笔者认为在安装Oracle数据库的过程中关键是准备工作阶段，准备工作做好了安装过程其实很简单。

13．恢复以前的glibc

[root@only_you oracle] cd /usr/bin
[root@only_you bin] rm –f gcc cc ld
[root@only_you bin] mv ./saved/* .
[root@only_you bin] rmdir saved
[root@only_you bin] cd /usr/lib
[root@only_you lib] mv ./saved/* .
[root@only_you lib] rmdir saved


ORACLE
RedHat7.0, Redhat Linux 7.1
Oracle8iR2(oracle8.1.6), Oracle 8i(8.1.5)企业版
1.机器配置：
内存是关键，最好128M以上，其他无苛刻要求。
4. 开始安装
A． 硬盘分区
1． Oralcel建议SWAP交换分区为400M或2倍于当前使用的系统物理内存，当然越大越好。
2． 分区时划定两个安装点，/u01(用于安装ORALCE软件)和/u02（用于存放数据库数据），/u01分区的大小，
典型安装 750MB
最小安装650MB
自定义安装 1000MB
这两个安装点可以在安装时划定或完成系统安装后在"/"目录或别的目录下建立
B.安装必须具备：（安装RedHat7.0时选择完全安装）
1.X Windows
2.Development packages(c,gcc等)
本质来说，RedHat7.1的glibc2.2库和其他相关工具对于Oracle8i来说，是有一点高了。所以一般都要用RedHat7.1自带的兼容RedHat6.2的库替换一下，也就是glibc2.1.3。
我自己的经验是只要正确替换了glibc，就一定可以安装成功，不用做别的工作。一定要把那几个compat的rpm软件包安装好，正确替换，再用gcc -v试试，确定是在用compat glibc2.1.3，再开始安装。
我在这个帖子里没有提设DISPLAY变量的问题，其实如果在本机的X下安装oracle，会有默认设置的，根本不需要自己再设了。
如果runInstaller报DISPLAY出错的话，就自己设一下好了，无非就是
export DISPLAY=192.168.0.1:0.0 （假设IP是192.168.0.1）
如果这样做了，联接系统库的时候还报make错误的话（我是从来没有遇到这样的make error问题，所以没有办法测试），可能就不是glibc的问题，而是ld这些命令的版本问题了。我建议如果出现这种错误的话，试试这个方法，就是再降级binutil。
先下载binutils-2.10.0.18-1.i386.rpm(下载网址：http://rpmfind.net/linux/RPM/redhat/7.0/i386/binutils-2.10.0.18-1.i386.html，或者在google上搜索一下）
rpm -Uvh binutils-2.10.0.18-1.i386.rpm --force --nodeps
然后再runInstaller。
又或者虽然出现make error，但是毕竟可以拷贝文件安装过去的话，也可以试试这个方法：
在安装文件完成以后，会先后出现配置Net8和出现数据库助手创建数据库的过程。
（如果配置Net8出错的话，可以就这样退出，自己手工修改$ORACLE_HOME/network/admin下的listener.ora和tnsnames.ora。）
在出现数据库助手创建数据库的时候，不要创建数据库，退出。因为此时联接的可执行程序有问题，不能正确创建数据库。
到Oracle网站，在下载Oracle8.1.7的地方，可以找到一个glibc的patch：
http://download.oracle.com/otn/linux/oracle8i/glibc-2.1.3-stubs.tar.gz
把它下载，放到$ORACLE_HOME下，解压缩，
cd $ORACLE_HOME
tar xvfz glibc-2.1.3-stubs.tar.gz
./setup_stubs.sh
然后在
dbassist
启动数据库创建助手，创建数据库。

附件是我的/etc/profile和oracle的.bash_profile，请参考

2.安装所需软件

Oracle8161_tar.gz（275M，文件较大，下载前做好心理准备，我第一次花了一整天弄下来却是个坏的，展不开，差点气死！只好又下载了一次，还不如去买张盗版光盘呢）。下载网址：
ftp://166.111.136.3/pub/DataBase/Oracle/oracle8161.tar.gz（清华酒井）
http://technet.oracle.com/software/products/oracle8i/software/index.htm

glibc2.1版本（GNU C Library，18M）下载地址：
ftp://ftp.kernel.org/pub/software/libs/glibc/hjl/sdk/2.1/i386-glibc-2.1-linux.tar.gz
下载后都放到了/backup目录

Oracle8161_tar.gz下载地址：
http://technet.oracle.com/software/products/oracle8i/software_index.htm
glibc2.1版本（GNU C Library）下载地址：
http://ftp.valinux.com/pub/support/hjl/glibc/sdk/2.1/i386-glibc-2.1-linux.tar.gz

1、替换glibc
Oracle8.1.7使用的是glibc2.1.3，而RedHat7.1是用的glibc2.2.2，不兼容，所以要替换glibc才能成功安装。
首先要安装RedHat7.1安装光盘上的几个以compat开头的rpm包，它们是：
compat-glibc-6.2-2.1.3.2.i386.rpm
compat-egcs-objc-6.2-1.1.2.14.i386.rpm
compat-egcs-6.2-1.1.2.14.i386.rpm
compat-libs-6.2-3.i386.rpm
可以把：
compat-libstdc++-6.2-2.9.0.14.i386.rpm
compat-egcs-c++-6.2-1.1.2.14.i386.rpm
也安装上。
因为这几个软件包之间有依赖关系，如果安装顺序不对，会报错的，无法安装。一般来说应该先安装第一张上的两个，再安装第二张上面的四个。
如果这样做也报错，安装不上，可以先把这6个软件包拷贝到一个目录下，然后再一起安装，这样就不用怕它们之间的依赖关系，一定可以安装成功了。例如：
rpm -ivh compat-glibc-6.2-2.1.3.2.i386.rpm compat-egcs-6.2-1.1.2.14.i386.rpm compat-libs-6.2-3.i386.rpm compat-egcs-c++-6.2-1.1.2.14.i386.rpm compat-egcs-objc-6.2-1.1.2.14.i386.rpm compat-libstdc++-6.2-2.9.0.14.i386.rpm

3.安装glibc 2.1包
RedHat7.0安装的是glibc2.2。Oracle 8I不能使用glibc 2.2进行编译，而需要glibc2.1的SDK。
以root帐号登录
[root@only_you /root] cd /
[root@only_you /] tar zxvf /backup/i386-glibc-2.1-linux.tar.gz
隐藏/usr/bin 目录下的gcc,cc,ld，避免被Oracle installer使用
[root@only_you /] cd /usr/bin
[root@only_you bin] mkdir saved
[root@only_you bin] mv gcc cc ld saved
[root@only_you bin] ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-gcc gcc
[root@only_you bin] ln -s gcc cc
[root@only_you bin] ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-ld ld
隐藏/usr/lib目录下的libc.so,libdl.so,libm.so和libpthread.so文件，避免被Oracle installer使用
[root@only_you bin] cd ../lib
[root@only_you lib] mkdir saved
[root@only_you lib] mv libc.so libdl.so libm.so libpthread.so saved
[root@only_you lib] mv libc.a libdl.a libm.a libpthread.a saved

RedHat7.0安装的是glibc2.2。Oracle 8I不能使用glibc 2.2进行编译，而需要glibc 2.1的SDK。
[root@rh70 /root]cd /
[root@rh70 /]tar zxvf /usr/src/i386-glibc-2.1-linux.tar.gz
隐藏/usr/bin 目录下的gcc,cc,ld，避免被Oracle installer使用
[root@rh70 /]cd /usr/bin
[root@rh70 bin]mkdir saved
[root@rh70 bin]mv gcc cc ld saved
[root@rh70 bin]ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-gcc gcc
[root@rh70 bin]ln -s gcc cc
[root@rh70 bin]ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-ld ld
隐藏/usr/lib目录下的libc.so,libdl.so,libm.so和libpthread.so文件，避免被Oracle installer使用
[root@rh70 bin]cd ../lib
[root@rh70 lib]mkdir saved
[root@rh70 lib]mv libc.so libdl.so libm.so libpthread.so saved
[root@rh70 lib]mv libc.a libdl.a libm.a libpthread.a saved

2.redhat linux 7.1配置：
glibc2.1兼容，在linux安装光盘上找到如下与6.2兼容的rpm包，并安装好。
compat-glibc-6.2-2.1.3.2.rpm
compat-libs-6.2-3.rpm
compat-egcs-6.2-1.1.2.14.rpm
1、安装glibc兼容包，找到以下rpm文件安装
compat-glibc-6.2-2.1.3.2.rpm
compat-libs-6.2-3.rpm
compat-egcs-6.2-1.1.2.14.rpm
3.安装相应的egc包。假定安装光盘mount在/mnt/cdrom上，用命令modprobe isofs使操作系统能处理光盘的文件系统，然后运行mount －t iso9660 /dev/cdrom /mnt/cdrom，如在安装后修改了/etc/fstab，可不进行这一步操作。进入相应的RPMS目录，安装以egc开始的包，采用的安装命令为rpm －ivh <包名>。
2. 系统用户和安装目录的建立

    在Oracle的技术文档中建议为数据库建立两个组——oinstall、dba，但在实际使用中笔者发现只要建一个dba组就可以顺利安装Oracle，而不影响系统的使用；需要为数据库增加一个用户oracle，它属于dba组；再建立/u01/app/oracle/8.1.6目录，并把它的所有者设为oracle.dba。

2、创建用户和组
groupadd dba
useradd oracle -g dba
passwd oracle
Oracle安装文档上说，要创建两个组，oinstall和dba，oracle用户主属组是oinstall，从属组是dba，其实只用dba就好了，不要那么麻烦。
chown -R oracle.dba /u01
chown -R oracle.dba /u02

3.建立oracle帐号和组
可用xwindow的用户管理程序添加oracle用户和oracle组，用户shell 选bash;也可以root身份打开终端窗口，输入
---------------------------------------------------------------
[root@xinli /root]#useradd oracle
[root@xinli /root]#passwd oracle (设密码)
---------------------------------------------------------------

以root帐号登录,开启一个terminal窗口,创建oinstall和dba组
[root@rh70 /root]groupadd oinstall
[root@rh70 /root]groupadd dba
创建oracle帐号,以oinstall为primary组，dba为secondary组
[root@rh70 /root]useradd oracle -g oinstall -G dba
[root@rh70 /root]passwd oracle (设置oralce帐号的密码)

F.创建Oracle软件安装目录
[root@rh70 /root]mkdir /u01/app/oracle/product/8.1.6
修改所创建目录的所属组及拥有者
[root@rh70 /root]chown oracle:dba /u01/app/oracle/product/8.1.6
[root@rh70 /root]chown oracle:dba /u02

4.设置oracle环境和数据文件目录

使用oracle帐号登录，开启terminal窗口
利用umask指令查看umask是否为022，若不是022，则需要把指令umask 022加到/home/oracle/.bash_profile文件中。
[oracle@rh70 oracle]umask

2、修改你的.bash_profile加入以下两行
export LD_ASSUME_KERNEL=2.2.5
. /usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh

打开终端窗口，以oracle账号登录
[oracle@xinli /ora8]$vi .bash_profile
在后面加入（假定oracle安装在/ora8）如下几行：
---------------------------------------------------------------
ORACLE_HOME=/ora8; export ORACLE_HOME
LD_LIBRARY_PATH=/ora8/lib; export LD_LIBRARY_PATH
ORACLE_BASE=/ora8; export ORACLE_BASE
ORACLE_SID=ora8; export ORACLE_SID
ORA_NLS33=/ora8/ocommon/nls/admin/data; export ORA_NLS33
NLS_LANG=american_america.zhs16cgb231280;export NLS_LANG
export LD_ASSUME_KERNEL=2.2.5
. /usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh
umask 022
---------------------------------------------------------------
存盘退出。
Log out,重新以oracle帐号登录，键入env指令查看刚才设置的环境变量。
[oracle@only_you oracle]env

使用文本编辑器打开/home/oracle/.bash_profile,加入如下环境变量的设置行：
#ORA_NLS=/u01/app/oracle/product/8.1.6/ocommon/nls/admin/data
#export ORA_NLS
#NLS_LANG="simplified chinese"
#export NLS_LANG
ORACLE_BASE=/u01/app/oracle
export ORACLE_BASE
ORACLE_HOME=/u01/app/oracle/product/8.1.6
export ORACL_HOME
ORACLE_SID=ora1 (自定义，最好不要超过四个字符)
export ORACLE_SID
CLASSPATH=/u01/app/oracle/product/8.1.6/jdbc/lib/calsses111.zip
export CLASSPATH
LD_LIBRARY_PATH=/u01/app/oracle/product/8.1.6/lib
export LD_LIBRARY_PATH
USERNAME="oracle"
PATH=$PATH:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/dbs
PATH=$PATH:/bin:/usr/bin:/usr/sbin:/usr/local:/usr/local/bin:/usr/bin/X11:/usr/X11R6/bin
Log out,重新以oracle帐号登录，开启terminal窗口，键入env指令查看刚才设置的环境变量。

3、设环境变量
可以将要设的环境变量放在oracle用户主目录下的.bash_profile中，也可以放在/etc/profile中，对所有的用户可见，我建议放在/etc/profile中，因为凡是在本机运行的程序读写本机的Oracle数据库，一般都需要设Oracle的环境变量，否则无法连接数据库。
我可以举一个例子：
如果你的WEB Server，例如Apache，需要读写数据库，提供网页的动态内容，假设用PHP或者JSP，又或者Perl等等来写ServerAPI或者CGI，因为Apache是以root启动一个进程，这个进程再fork若干子进程以nobody用户运行，响应80端口的http请求，所以如果在root读不到Oracle环境变量，Web程序根本无法读写数据库。只要root读到oracle环境变量，fork子进程的时候，复制了父进程的数据空间，也继承了父进程的环境变量，所以可以读到oracle变量，就可以读写oracle数据库了。
所以我这样设置，在/etc/profile中添加如下行：
ORACLE_BASE=/u01/app/oracle
ORACLE_HOME=/u01/app/oracle/product/8.1.7
ORACLE_SID=orcl
ORA_NLS=/u01/app/oracle/product/8.1.7/ocommon/nls/admin/data
NLS_LANG="SIMPLIFIED CHINESE"
CLASSPATH=.:/u01/app/oracle/product/8.1.7/jdbc/lib/classes111.zip
LD_LIBRARY_PATH=/u01/app/oracle/product/8.1.7/lib
PATH=$PATH:$ORACLE_HOME/bin:$ORACLE_HOME/dbs:/etc
export ORACLE_BASE ORACLE_HOME ORACLE_SID ORA_NLS NLS_LANG LD_LIBRARY_PATH PATH

其中$ORACLE_BASE,$ORACLE_HOME指定安装目录，$ORACLE_SID是oracle数据库的SID，$ORA_NLS是字符集目录，$NLS_LANG是字符集，$CLASSPATH是Java程序读写数据库需要的JDBC的class，前面加个点号是先搜当前目录的意思。$LD_LIBRARY_PATH是Oracle的C库函数和头文件的位置，对于OCI8，PROC和JDBC的OCI连接是必须的。

注销再登录，或者不用注销，执行下一行的命令，直接读一下/etc/profile
. /etc/profile

再
env|grep oracle
看看oracle的变量是否都设置正确。

4、临时更改glibc
将
. /usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh
export LD_ASSUME_KERNEL=2.2.5

加入oracle主目录(/home/oracle)下的.bash_profile，注销再以oracle登录，或者不用注销，执行下一行的命令，直接读一下.bash_profile
. /home/oracle/.bash_profile

再看看是否已替换
gcc -v
替换之前是：
Reading specs from /usr/lib/gcc-lib/i386-redhat-linux/2.96/specs
gcc version 2.96 20000731 (Red Hat Linux 7.1 2.96-81)
替换之后是：
Reading specs from /usr/i386-glibc21-linux/lib/gcc-lib/i386-redhat-linux/2.96/specs
gcc driver version 2.96 20000731 (Red Hat Linux 7.1 2.96-81) executing gcc version egcs-2.91.66

设定安装的环境变量

    安装前，应该设定相应的环境变量。修改用户Oracle的.bash—profile文件，设定相应的环境变量。由于安装系统时需要Root用户，也要有这些环境变量，故将其放在/etc/profile内，加＊号为Oracle专有的环境变量，示例如下：

    ＃ /etc/profile

    ＃ System wide environment and startup programs

    ＃ Functions and aliases go in /etc/bashrc

    JAVA—HOME=/usr/local/jdk1.1.3

    SYBASE=/opt/sybase－11.9.2

    DSQUERY=SYBASERDBMS

    ＊PATH=＄PATH:＄JAVA—HOME/bin:/usr/X11R6/bin:/home/oracle/product/8.0.5/bin

    PS1=″u@h:w＄″

    ulimit －c 1000000

    if [ ′id －gn′ = ′id －un′ －a ′id －u′ －gt 14 ]; then umask 002

    else umask 022

    fi

    USER=′id －un′

    LOGNAME=＄USER

    MAIL=″/var/spool/mail/＄USER″

    CLASSPATH=/usr/local/jdk1.1.3/lib:＄HOME/bin

    HOSTNAME=′/bin/hostname′

    HISTSIZE=1000

    HISTFILESIZE=1000

    export JAVA—HOME CLASSPATH SYBASE DSQUERY

    export PATH PS1 HOSTNAME HISTSIZE HISTFILESIZE USER LOGNAME MAIL

    ＊ORACLE—HOME=/home/oracle/product/8.0.5

    ＊ORACLE—BASE=/home/oracle

    ＊ORACLE—OWNER=oracle

    ＊ORACLE—SID=oracle8

    ＊ORACLE—TERM=386

    ＊LD—LIBRARY—PATH=/home/oracle/product/8.0.5/lib

    ＊TMPDIR=/var/tmp

    ＊export ORACLE—HOME ORACLE—BASE ORACLE—OWNER ORACLE—SID ORACLE—TERM

    export LD—LIBRARY—PATH TMPDIR

    for i in /etc/profile.d/.sh ; do

     if [ －x ＄i ]; then . ＄i

     fi

    done

    unset i

建立数据文件目录，我把数据文件放在/oradata下,以root用户建立
---------------------------------------------------------------
[root@xinli /]#mkdir /oradata
---------------------------------------------------------------

7.创建oracle数据文件目录
我想把数据文件放在/home/oracle/data目录下，于是
[oracle@only_you oracle] mkdir data

5.解压缩oracle8161_tar.gz
以root帐号登录，执行：
[root@only_you /root] cd /backup
[root@only_you /backup] tar zxvf oracle8161_tar.gz
在/backup/目录下生成Oralce8iR2目录，内含解包后的文件

1.以Root用户登录进入系统，创建用户oracle和组dba，这是Oracle默认的安装用户。创建安装用户后，用tar －xvzf 将压缩文件解压到一个指定的目录，本文假定为/oracle，因为tar进行数据归档与用户本机的用户ID、组ID不同，所以要运行chown －R oracle:dba 以更改文件属性。

5.解压缩oracle8161_tar.gz 软件包(275M)
假如我把oracle8iR2放在/home/test下面,以root身份登录
生成Oralce8iR2目录，内含解包后的文件，并让oracle账号可访问。
---------------------------------------------------------------
[root@xinli test]tar zxvf oracle8161_tar.gz
[root@xinli test]chown oracle test
---------------------------------------------------------------

2.由于Oracle本身对共享段的要求，用户必须重新手工生成核心，以便共享段的设定满足安装要求。为生成核心，用户应当安装Linux操作系统的源代码，编辑/usr/src/linux/include/shmparam.h，将＃define SHMMAX 0x002000000一行的0x002000000(32MB)改为256MB以上，然后在/usr/src/linux下运行make dep、make clean、make bzImage生成核心，使用linuxconf命令将新核心设为启动核心。这一步一定要做，如果生成的新核心有错，可以用原来的核心启动计算机。可用ipc －ml查看共享段的设置是否满足要求。当共享段大于2GB时，查看到的值是负数。
1. 系统内核的修改

    对/usr/src/linux/include/asm/hmparam.h文件作如下修改：

被修改量 修改后数值
shmmax 内存大小*0.5
shmmin 1
shmmni 100
shmseg 10

    对/usr/src/linux/include/linux/sem.h文件作如下修改：

被修改量 修改后数值
semmni 100
semmsl processes参数+10
segmns 所有数据库processes参数总和+10

semopm 100
semvmx 32767

    参数修改完后，用“make dep”、“make clean”、“make bzImage”命令重新编译内核，并用新内核启动计算机。

5、修改内核参数
Oracle数据库运行的时候，用共享内存来实现Oracle的SGA，所以要调整一下Linux的内核参数来适应Oracle的SGA的要求，这个方面到底要调整到多少才适合，可以参考Oracle官方的安装文档。一般而言，主要就是共享内存段最大尺寸要调整，Linux内核默认共享内存段最大尺寸是32M，如果Oracle SGA开的大于32M（一般商业运行，肯定大于32M），SGA就会分段，占据几个不连续的共享内存段，造成Oracle的性能下降。
命令ipcs -al可以查看共享内存参数，命令ipcs查看共享内存使用情况。
修改内核参数可以修改内核源码再重新编译内核，这个方法有点麻烦，关于共享内存的参数在源码目录下的include/linux/下的shm.h和sem.h文件中。
另一个简单的办法是直接修改内核参数，即修改/proc下的文件，立即生效。
可以修改/proc/sys/kernel下的shmmax和sem
shmmax是以字节记的共享内存段的最大尺寸，
shmmni是共享内存段的最大数量
shmmax是共享内存总共最大容量（shmmax*shmmni)
sem是信号量参数，msgmax，msgmnb，msgmni是消息队列的参数。

我改动如下：

echo 134217728 > /proc/sys/kernel/shmmax （SGA最大为128M）
echo -e "250\t32000\t100\t128" > /proc/sys/kernel/sem
（其实也不用改这项，只是将max ops per semop call改大了，这是Oracle的安装文档上写的，我就这么做了，不过我试过，不改也没事，其他都保持原来的，没有改）

总结如下：改一项必须的shmmax，其他的我在使用过程中，参数都够大了，不需要再调整。

6.安装oracle软件
在服务器上打开一个终端窗口（默认root身份）
---------------------------------------------------------------

（5）设置xhost

开启一个新的terminal窗口
[oracle@only_you oracle]su - (输入root密码)
[root@only_you /root] xhost +
保留此窗口

[root@xinli /root]xhost +
---------------------------------------------------------------
再在服务器上打开另一个终端窗口
---------------------------------------------------------------
[root@xinli /root]su – oracle
[oracle@xinli /ora8]cd /home/test/Oracle8iR2
[oracle@xinli Oralce8iR2]./runInstaller
---------------------------------------------------------------

有的时候runInstaller，安装界面不出来，这主要还是因为Oracle的字符集设为了简体中文，但OS是英文的，所以有时候出不来，用Java写的程序经常出现字符集的问题。此时临时销毁$NLS_LANG变量，Java会用默认的字符集，就好了。所以：

unset $NLS_LANG

也可以试试

unset $LANG
× 其实dbassist也是有时候出不来的，这样做就可以出来了，但是netasst始终出不了，不清楚为什么，不过可以自己修改lisener.ora和tnsnames.ora，所以netasst也不是必须的。

另一个可能的原因就是glibc没有替换好，我发现直到JDK1.3.1_01，才支持glibc2.2，之前的版本，包括JDK1.3.0都不支持glibc2.2，只要在glibc2.2下运行，就会出现没有任何反应，进程好像死亡了一样的毛病，Oracle安装程序用的还是JRE1.1.8，所以只要glibc用的还是2.2版的，安装窗口总不会出来的。

此时弹出oracle的安装界面，按照提示一步步next下去即可。
注意：
在File Locations界面上，检查Destination Path为/ora8
在Unix Group Name窗口中，键入"oracle"
    ● 在Unix Group Name 字段中添入“dba”；
当弹出提示要求以root身份运行/ora8/orainstRoot.sh 时，
切换到刚才保留的root用户窗口
---------------------------------------------------------------
[root@xinli /root] cd /ora8
[root@xinli ora8]./orainstRoot.sh
---------------------------------------------------------------
然后返回刚才弹出的窗口，点击Retry。

● 选择“Oracle8i Enterprise Edition”；

    ● 安装类型选择“Custom”；

    ● 建议安装内容中不要选择Intermedia，有些技术资料介绍说这个软件运行不太稳定，我们又何必自找麻烦呢！

    ● 在询问是否在安装时建立数据库时，选择“No”，因为我们要用Oracle提供的专门工具建立数据库；

    ● 在安装过程中需要以Root身份执行两个文件——只要用su命令进行一下身份转换就行了。

3、到选择安装“服务器”，“网络管理工作站”，“客户端”的时候，选择“服务器”
安装好以后，可以再回到这个画面来选择别的没有安装的组件，也随时可以启动runInstaller来安装别的组件。
另外有人提到没有安装PORC的选项，其实PROC是在“客户端”的选项里安装的。

4、然后选择“定制安装”，不要选择典型安装，因为典型安装会安装Oracle Jserver，实际上不太用到Jserver，而且安装Jserver是在SGA里要启动一个Java虚拟机，非常消耗资源（Java的东西总是很吃资源的），而且安装的时候创建Jserver的过程非常的漫长，一度令我怀疑死机了。

5、出现选择安装组件的列表，可以自己增删一些组件，我不需要oracle的Apache Server，准备自己从源码安装，所以就勾掉了。如果要安装Apache Server的选项话，要预先安装Java，并设置$JAVA_HOME变量，虽然要求的是jdk1.1.8，不过用jdk1.3也完全可以安装成功，运行Apache也没有什么问题，至于会不会因为jdk的版本不同导致一些程序运行结果的差异，我就没有测试过了。

6、还是选择安装组件的列表这个界面，有个选择语言的按钮，增加“简体中文”

7、询问是否创建数据库，“是”，添上安装数据库的SID，我的是“orcl”，数据库数据文件的存放目录，我的是“/u02“。

8、开始安装Oracle，安装程序拷贝文件。
有很多人说，拷贝文件完后，联接系统库函数的时候，出现make错误，我想这多半还是替换glibc不成功导致的吧，我安装的时候确实没有出现过这样的问题。我想按照我写的步骤来，应该不会出现这样的问题的。

在出现的"Available products"窗口上选择"Oracle8I enterprise edition8.1.6.1.0"
安装类型可选Typical
在提示输入global database name时编一个名字如xinli， ORACLE_SID为ora8（与.bsah_profile相同）
提示输入db files localtion,输入/oradata
最后的Summary窗口上，点击Install
视机器速度，我的机器约10几分钟就完成了。之后，弹出一个窗口要求运行root.sh，切换到另一个窗口，
---------------------------------------------------------------
[root@xinli ora8]./root.sh
---------------------------------------------------------------
在询问local bin directory时按下回车键即可 ，返回刚才的窗口上，点击OK
然后又越10机分钟Oracle Database Configuration Assistants结束后，点击OK ，在End of Installation画面上，点击Exit ，在弹出的Do you reallywant to exit?窗口上点击yes， Oralce 8i Enterprise就安装好了！

、完成后，提示以root运行root.sh。
Oracle8.1.7有两个版本，一个是Oracle8.1.7.0.0，另一个是Oracle8.1.7.0.1，这个版本带OPS，而且Oracle提供了一个glibc2.2的patch，不过在Redhat7.1上，按照上面方法做了以后，实际上不需要打补丁的。这个Oracle8.1.7.0.1的版本此时的root.sh有个bug，应该在第156行，如下：
RUID=`/usr/bin/id|$AWK -F\( '{print $2}'|$AWK -F\) '{print $1}`
在最后少写个‘
应该改为：
RUID=`/usr/bin/id|$AWK -F\( '{print $2}'|$AWK -F\) '{print $1}'`

运行它，生成/etc/oratab。

10、自动启动netasst，配置监听器，一般如果为了省事，选典型配置就可以了，只不过典型配置打开了一个2481端口，是JServer用的，如果不用JServer的话，也可以不要它，现在可以不用管它，回头再改listener.ora好了。

11、自动启动dbassist，安装数据库，按照提示做就是了，根据自己的情况可以适当的调整安装数据库时的参数，最后开始创建数据库，此时也可以选择先保存创建的脚本，再退出dbassist，单独运行创建脚本，这样更灵活一些，可以自己改创建脚本，也可以自己研究一下脚本，会有收获的。

三、安装后配置

1、以root登录，修改/etc/oratab，将最后的：
orcl:/u01/app/oracle/product/8.1.7:N
改为：
orcl:/u01/app/oracle/product/8.1.7:Y
这样就可以用dbstart和dbshut来启动和关闭数据库了，不用自己写脚本调svrmgrl。

2、将数据库启动命令和修改内核命令放在系统启动脚本中

修改/etc/rc.d/rc.local,加入：

#modify kernel parameter
echo 134217728 > /proc/sys/kernel/shmmax
echo -e "250\t32000\t100\t128" > /proc/sys/kernel/sem

#start Oracle8.1.7
su - oracle -c 'lsnrctl start'
su - oracle -c 'dbstart'

我比较懒，没有另外写脚本联接进rc3.d,rc0.d.rc5.d,rc6.d了，而是直接放在rc.local中了，呵呵
注意的是修改内核参数必须在启动数据库实例之前，启动数据库后，用ipcs 命令看看共享内存的使用情况，如果没有分段就行了。

另外一个特别要说明的事情是一定要注意，凡是读写数据库的进程，必须取得oracle的环境变量，否则无法联接数据库。
上面的脚本中su - 中的这个"-"非常讲究，它的意思是切换到oracle用户，并取得oracle的环境变量。
再例如，如果还要启动apache来读写数据库的话，rc.local加入的命令就一定要这样写：
#start apache httpd server
. /etc/profile
/usr/local/apache/bin/apachectl start

因为我把oracle的环境变量放在/etc/profile里了，在启动apache之前要先强制它读/etc/profile，取得oracle的环境变量，这样apache的ServerAPI程序就可以读写数据库了。

3、修改Net8配置，可以用netca，或者自己修改$ORACLE_HOME/network/admin下的listener.ora和tnsnames.ora，netasst好像出不来。

4、如果创建第二个实例，用dbassist就好了，如果dbassist出不来的话，临时销毁$LANG,$NLS_LANG
unset $NLS_LANG
unset $LANG
就可以出来了。

四、废话

我没有足够的硬件条件来安装OPS，所以安装Oracle8.1.7的时候不选OPS的；也没有硬件条件安装Oracle9i，所以不知道RedHat7.1来安装Oracle9i如何。不过用过一下SuSE7.1，印象很好，既然Oracle官方推荐是SuSE的话，还是用SuSE来安装Oracle9i吧，这样兼容性比较好，也省事。
如果我写的安装方法有什么谬误的地方，请大家指点一下，谢谢！
我的联系方法：
E-mail: fankai@adbobo.com
QQ: 14477412

Good Luck to you

安装完成后会有两个缺省的数据库管理员用户：ｓｙｓ，口令是ｃｈａｎｇｅ＿ｏｎ＿ｉｎｓｔａｌｌ；ｓｙｓｔｅｍ，口令是ｍａｎａｇｅｒ。从系统安全的角度考虑，建议用户要做的第一件事就是更改这两个用户的口令，方法是启动数据库后在ＳＱＬＰｌｕｓ中修改，具体方法后面会提到。
7.用svrmgrl管理或用其他在windows下的管理工具测试管理。
要用客户机登录，就要设置好listener.ora,可参考其他文档。
Svrmgrl要求对命令比较了解才行，不太方便。
Oracle8 client软件（windows下的）中的Oracle Enterprise Manager挺不错的，全是交互式图形化管理界面，很容易操作。Oracle8 client可到
http://download.oracle.com/otn/nt/oracle8i/win817client.zip下载（213M,好大，还须先注册otn账号才行）。
[以上为本人实际经验，参照其他网友文章所写，水平有限，错误之处，在所难免，欢迎指正]

[oracle@only_you oracle] svrmgrl
Oracle Server Manager Release 3.1.6.0.0 - Production
Copyright (c) 1997, 1999, Oracle Corporation. All Rights Reserved.
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SVRMGR>connect internal
Connected.
SVRMGR> shutdown
Database closed.
Database dismounted.
ORACLE instance shut down.
SVRMGR>startup
ORACLE instance started.
Total System Global Area 56012784 bytes
Fixed Size 69616 bytes
Variable Size 38993920 bytes
Database Buffers 16777216 bytes
Redo Buffers 172032 bytes
Database mounted.
Database opened.
SVRMGR> quit
Server Manager complete.

不错，看来可以正常工作了。再用sqlplus试试

[oracle@only_you oracle]$ sqlplus
SQL*Plus: Release 8.1.6.0.0 - Production on Sun Apr 15 09:20:12 2001
(c) Copyright 1999 Oracle Corporation. All rights reserved.
Enter user-name: scott
Enter password: tiger
Connected to:
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SQL> select * from emp
应该出来一堆数据，有14条，看来没问题了。
SQL>quit

2. 开始工作

    如果用户是在服务器端使用数据库，那么可以用Oracle提供的SQLPlus进行数据库操作，假设要更改用户口令，可以这样做：

    sqlplus user/password

    sql>alter user sys identified by new_password;

    sql>exit

    如果用户是在客户端对数据库进行操作的话事情会稍微麻烦一些：首先数据库服务器端要对端口进行监听，收到请求后客户端才能与服务器端建立连接，服务器端监听的方法是运行下面命令：lsnrctl start；然后客户端用户要通过NET8建立一个服务名称，用来与服务器端进行连接；最后才能通过客户端软件，比如客户端SQLPlus对数据库进行操作。

    任何事情只要你掌握了它的关键也就不会觉得难了。笔者认为在安装Oracle数据库的过程中关键是准备工作阶段，准备工作做好了安装过程其实很简单。

10．恢复以前的glibc

[root@only_you oracle] cd /usr/bin
[root@only_you bin] rm –f gcc cc ld
[root@only_you bin] mv ./saved/* .
[root@only_you bin] rmdir saved
[root@only_you bin] cd /usr/lib
[root@only_you lib] mv ./saved/* .
[root@only_you lib] rmdir saved


ORACLE

网络数据库
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
数据库服务器 Oracle8i Oracle8i是一个面向Internet计算环境的数据库，它改变了信息管理和访问的方式。Oracle8i将新的特性融入到了传统的Oracle服务器之中，从而成为一个面向Web信息管理的数据库。Oracle8i支持Web高级应用所需要的多媒体数据，支持Web繁忙站点不断增长的负载需求。Oracle8i是唯一一个拥有集成式Web信息管理工具的数据库。
Oracle正在推动Java成为下一代应用的标准，它在各个层次，包括Oracle8i服务器内的JavaVM，均支持Java。Oracle8i将强大的新型功能引入到了联机事务处理(OLTP)和数据仓库应用之中。Oracle8i还对Oracle数据服务器的几乎所有方面都给予了增强，全面改进了质量、可用性、性能、可管理性、多媒体数据类型支持和复制功能
Oracle9i
Oracle9i是业界第一个完整、简单的用于互联网的新一代智能化的、协作各种应用的软件基础架构。
应用服务器 Oracle Application Server4.0
Oracle应用服务器提供了一个开放的标准架构，是开发部署Web上的应用的理想平台。它的伸缩性，分布架构和高度数据库集成是支持关键事务，交易型应用的基础，通过采用Netscape和MicrosoftHTTP服务器，提供了易于使用的界面，并为Oracle方案提供了简易的升级方法。
开发工具 Oracle Designer
一个基于共享信息仓储的建模和生成工具、设计和建立应用与数据库定义的高效开发环境。
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一个用于建立企业级客户/服务器和Web数据库应用的、易于使用的集成式快速应用开发环境。
Oracle JDeveloper
一个利用Java来建立基于部件的数据库应用的最具生产力的开发环境。
Oracle Reports
一个用于发布和报告的解决方案，部门可以利用它在其企业内部网或Internet上动态地发布信息。
资源
  • Oracle爱好者之家 http://www.oraclefan.net/- ORACLE DBA论坛、开发者论坛，工作论坛、新技术论坛、OCP论坛
  • oracle讨论组 - http://oracle.myrice.com/ oracle技术讨论组。集聊天室、BBS论坛、网络社区和电子邮件为一体
  • Oracle DBA园地(论坛) - http://www.linuxforum.net/forum/postlist.php?Cat=&Board=oracle 中国Linux论坛之Oracle DBA论坛
  • IT开发认证网 - http://ocp.6to23.com/ ORACLE、Microsoft、Cisco、UNIX/Java、Novell认证资?/font>
  • ORACLE FAQS(英文) -http://www.orafaq.com/faq.htm 有关ORACLE的知识库，有FAQ和论坛
  • Oracle技术网 - http://www.oradb.net/ 介绍各种Oracle知识
  • Oracle公司 - http://www.oracle.com/


ORACLE
Oracle安装
Oracle8iR3(8.1.7)+PHP4+Apache在RedHat7.1上的安装

一．Oracle8iR3的安装

1． 准备安装环境

在http://www.oracle.com 上下载最新的Oracle8iR3版for linux的数据库linux81701.tar。

需要的glibc兼容包都在RedHat7.1的两张安装盘上：

  • compat-glibc-6.2-2.1.3.2.rpm
  • compat-libs-6.2-3.rpm
  • compat-egcs-6.2-1.1.2.14.rpm

(glibc2.1版本（GNU C Library）下载地址：
http://ftp.valinux.com/pub/support/hjl/glibc/sdk/2.1/i386-glibc-2.1-linux.t
ar.gz )

安装glibc 2.1包

RedHat7.0安装的是glibc2.2。Oracle 8I不能使用glibc 2.2进行编译，而需要glibc 2
.1的SDK。
[root@rh70 /root]cd /
[root@rh70 /]tar zxvf /usr/src/i386-glibc-2.1-linux.tar.gz
隐藏/usr/bin 目录下的gcc,cc,ld，避免被Oracle installer使用
[root@rh70 /]cd /usr/bin
[root@rh70 bin]mkdir saved
[root@rh70 bin]mv gcc cc ld saved
[root@rh70 bin]ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-gcc g
cc
[root@rh70 bin]ln -s gcc cc
[root@rh70 bin]ln -s /usr/i386-glibc-2.1-linux/bin/i386-glibc21-linux-ld
ld
隐藏/usr/lib目录下的libc.so,libdl.so,libm.so和libpthread.so文件，避免被Oracl
e installer使用
[root@rh70 bin]cd ../lib
[root@rh70 lib]mkdir saved
[root@rh70 lib]mv libc.so libdl.so libm.so libpthread.so saved
[root@rh70 lib]mv libc.a libdl.a libm.a libpthread.a saved

将以上的软件包以root的身份正确安装。

到http://www.blackdown.org/ 上下载Oracle创建数据库时用到的JDK，文件名称为：jdk118_v3-glibc-2.1.3.tar.bz2 不要下载最新的jdk包，只有此包能够支持Oracle8iR3。将文件下载到/usr/local目录下，并解压此文件：
# tar xvlf jdk118_v3-glibc-2.1.3.tar.bz2
#ln –s /usr/local/jdk118_v3 /usr/local/java
这样安装Oracle8i的软件环境已经准备好了。

2．建立安装组和帐号
以root身份登录到系统中：

在虚拟终端窗口,添加用户组 :oinstall组用来安装软件,dba是你的数据库管理员组，oper是你的管理组。

# groupadd oinstall
# groupadd dba
# groupadd oper

建立安装帐号:用oinstall作为主要组来创建一个用户，dba 和 oper作为次要组
# useradd oracle -g oinstall –G dba,oper
# passwd oracle (设置密码)

创建oracle8i的安装点
mkdir /u01 (You can also fake the OFA-compliancy
（你也可以通过mkdir /u01, /u02, /u03 and /u04来伪装。。。。 ）

改变安装点的属主和属性
# chown oracle.dba /u01
# chmod 755 /u01

退出登陆。

3．修改安装帐户的运行环境

以oracle帐户登录到系统中，如果你还没有打开一个虚拟终端窗口，现在就打开它.

通过键入umask [enter]来验证umask为022。如果是，好。如果不是你将把它放到.bash_profile里,下一步我们将编辑它。

用你喜爱的编辑器在你的oracle帐号的home目录(home/oracle)编辑 .bash_profile文件，在这个文件中写入下面这些行：

ORACLE_BASE=/u01/app/oracle; export ORACLE_BASE
ORACLE_HOME=$ORACLE_BASE/product/8.1.7; export ORACLE_HOME
ORACLE_SID=orcl; export ORACLE_SID
USERNAME="oracle"; export USERNAME
PATH=$PATH:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/dbs
PATH=$PATH:/bin:/usr/bin:/usr/sbin:/usr/local:/usr/local/bin:/usr/bin/X11
:/usr/X11R6/bin
export PATH
CLASSPATH=.:$ORACLE_HOME/jdbc/lib/classes111.zip; export CLASSPATH
LD_LIBRARY_PATH=$ORACLE_HOME/lib; export LD_LIBRARY_PATH
ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data; export ORA_NLS33
NLS_LANG=AMERICAN.AMERICA.UTF8; export NLS_LANG
LD_ASSUME_KERNEL=2.2.5; export LD_ASSUME_KERNEL

umask 022 (仅当umask不为022时选择写入这一行)

. /usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh

注销oracle帐号并重新登录，用env检查环境变量是否正确。

NLS_LANG=NLS_LANG value:

Language---- NLS_LANG value

US English ----american
Arabic---- arabic
Brazilian Portugese ----"brazilian portugese"
Canadian French---- frc
Czech---- czech
Danish ----danish
Dutch ----dutch
Finnish---- finnish
French ----french
German ----german
Hungarian---- hungarian
Icelandic ----is
Italian ----italian
Japanese---- japanese
Korean---- korean
Lithuanian---- lt
Mexican Spanish---- esm
Norweigan---- norweigan
Polish---- polish
Portugese---- portugese
Russian---- russian
Simplified Chinese---- "simplified chinese"
Slovak---- slovak
Swedish---- swedish
Thai ----th
Traditional Chinese ----"traditional chinese"
Turkish ----turkish

如果虚拟终端窗口没有打开，再次打开它，键入env查看是否所有以上变量现在出现在你的环境中。

同样都确信下面的路径都在你的path statement中,在你以上指定的路径中增加Oracle路径: /bin, /usr/bin, /usr/local/bin。

4．解压Oracle8iR3的安装程序

以root身份登录，将Oracle安装包linux81701.tar拷贝到/usr/src目录并解包
# tar xvf linux81701.tar
在/usr/src目录下生成Disk1子目录，退出。

5．安装Oracle8iR3

以oracle用户身份登录，运行Oracle Universal Install
$ cd /usr/src/Disk1
$ ./runInstaller
此时会出现图形窗口,单击Next按钮,检查Source path是否为/usr/src/Disk1/stage/products.jar,
而目的路径是否为上文中定义的$ORACLE_HOME环境值,再单击Next按钮;
在Unix Group Name中填入oinstall,单击Next按钮;
此时会弹出一个对话框提示需要运行orainstRoot.sh脚本,
打开新的terminal窗口
su root
(输入root口令)
cd $ORACLE_HOME
./orainstRoot.sh

暂时不关闭此窗口;
回到刚才的弹出对话框,单击Retry按钮;
选择Oracle 8i Enterprise Edition 8.1.7.0.1,单击Next按钮;

选择Typical,单击Next按钮;

此时安装程序提示输入global database name(全局数据库名),由用户自己定义;
检查ORACLE_SID是否与上文中环境参数中定义的值一致,单击Next按钮;
接下来提示输入数据库文件的位置,可以输入/u01,单击Next按钮;
此时安装程序提示确定JDK home directory,检查是否为/usr/local/java,单击Next按钮;
然后出现汇总窗口,单击Install按钮,软件正式开始安装;

当文件拷贝连接完成后,会弹出对话框要求运行root.sh,
回到刚才打开的terminal窗口,仍以root身份运行

cd $ORACLE_HOME
./root.sh

提示输入Path to your local bin directory时按Enter键即可;

exit (退出root权限)
exit (关闭terminal窗口)

返回对话框并单击OK按钮;

Oracle Net8 Configuration开始运行,选择"Perform typical configuration"并单击Next按钮;
Database Configuration Assistant开始运行,当数据库创建完成时单击OK按钮;
Oracle会启动7777端口的webserver,无需干预;
出现End of Installation屏幕时单击exit按钮,安装过程结束.

重要内容!默认密码

Oracle为管理数据库安装了两个帐号。
下面是他们的名字和密码：
sys - change_on_install
system - manager

6. 试运行

在terminal中运行
1)启动TNS Listener服务进程

lsnrctl start

2)加载并运行数据库实例

svrmgrl
SVRMGR>connect internal
SVRMGR>connected.
SVRMGR>startup
......
SVRMGR>quit

3)查询示例数据库

sqlplus scott/tiger@orcl
select * from emp;
......

二．PHP4的安装

从http://www.php.net 下载最新的源程序包：php-4.0.6.tar.gz 到/usr/local/src目录并解包：
# tar zxvf php-4.0.6.tar.gz

修改编译时要用到的库文件libpthread.so.0
# cd /lib
# rm libpthread.so.0
# ln –s /usr/i386-glibc21-linux/lib/libpthread-0.8.so libpthread.so.0

开始配置PHP4的编译参数：
# cd /usr/local/src/php-4.0.6
# ./configure –prefix=/usr --with-config-file-path=/etc --disable-debug --enable-inline-optimization --without-mysql --with-oci8=/u01/app/oracle/8.1.7 --enable-sigchild --with-apxs

当程序自动配置完成后，就可以编译程序了
#make

如果编译没有问题，就可以安装了
#make install
#cp php.ini-dist /etc/php.ini

重新启动apache，用下面的文件在浏览器中检测是否安装成功。

<? phpinfo() ?>

你的系统一切都OK了吗？
记得把改过的库文件再改回去，以免出现编译程序的错误。
# rm /lib/libpthread.so.0
# ln -s /lib/libpthread-0.9.so /lib/libpthread.so.0

Linux9i_Disk1.cpio.gz 的安装：

1. Run "gunzip filename" on all the files. - Eg.: gunzip Linux9i_Disk1.cpio.gz

2. Extract the cpio archives with the command "cpio -idcmv filename - Eg.: cpio -idcmv Linux9i_Disk1.cpio.gz

Oracle Database 9i 在Linux 下的安装

01-7-25 下午 02:07:16

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Oracle9i 2000 年 10 月在 Oracle Open World 上发布，为 Oracle 数据库、应用服务器和开发工具引进了许多新功能。Oracle9i是业界第一个完整、简单的用于互联网的新一代智能化的、协作各种应用的软件基础架构。Oracle9i 实际上是指 Oracle9i Database, Oracle9i Application Server 和Oracle9i Developer Suite的完整集成。随着软件逐渐开始转变为一种托管服务（ hosted services）， 具有internet上的高伸缩性能的、智能化的、和可靠的Oracle9i 将成为高质量的电子商务服务实现的关键软件。

本文将介绍Oracle Database 9i在Linux下的安装过程，如果你是有过安装Oracle的经验本安装过程可以权当快速安装手册；如果你以前从未在Linux下安装过Oracle数据库，那我们就从这篇文章开始熟悉oracle的安装过程。

系统要求：
以下的系统要求适用于典型的Oracle安装和创建简单数据库的方式。

内存：
安装Oralce 9i软件至少需要512M内存，用以下命令可以查看机子的内存大小：
grep MemTotal /proc/meminfo
MemTotal: 900252 kB
900252kB就是你系统的内存大小。

交换区：
交换区的大小一般要求是内存的两倍，至少要求达到400M以上，当然是越大越好，用以下的命令可以查看系统交换区的大小：
/sbin/swapon -s
Filename Type Size Used Priority
/dev/sda6 partition 105221 686976 -1

其中105221就是系统交换区的大小。

光驱：
如果你使用光盘安装Oracle9i则你的机子上需要8速以上的CDROM，如果你是下载了oracle9i的包文件，则不需要使用的CDROM。

硬盘空间：
安装Oracle9i数据库至少要有2.5GB以上的剩余空间。

临时硬盘空间：
Oracle安装程序在安装过程中需要400M以上的临时硬盘空间，建议使用/tmp文件夹作为零时文件夹，如果/tmp文件没有足够的硬盘，可以新创建一个文件夹作为安装的临时目录，之后设置环境变量TEMP和TMPDIR指向相应的位置，例如：
使用bash
mkdir /home/temp
TEMP=/home/temp ; export TEMP
TMPDIR=/home/temp ; export TMPDIR

使用csh
mkdir /home/temp
setenv TEMP /home/temp
setenv TMPDIR /home/temp

操作系统：
Oracle公司官方公布的资料指出Oracle 9i只在安装SuSuSe 7.1, 内核 2.4.4 和glibc2.2的系统上测试通过，经过本人的测试，Oracle在Linux Mandrake release 8.0，内核2.4.3-20和glibc-2.2.2的版本上也可以顺利安装，本文将以Linux Mandrake8.0为例介绍Oracle9i的安装过程。

虚拟x-windows软件：
这个软件不是必要的！所谓虚拟x-windows软件指的是可在远程终端允许服务器x-windows的虚拟软件，现在流行的x-windows软件有exceed、x-win32等软件，如果你嫌在控制台安装oracle系统麻烦，可以使用虚拟x-windows软件在远程终端在图形界面下安装oralce9i，本文将以x-win32 5.0为例介绍用虚拟x-windows安装oracle9i的过程。
JDK
如果你要安装Oracle HTTP Server还需要用到blackdown的JDK1.3.1，请到以下地址下载ftp://ftp.progsoc.uts.edu.au/pub/Linux/java/JDK-1.3.0/i386/rc1/j2sdk-1.3.0-RC1-linux-i386.tar.bz2

配置内核参数
oracle9i使用Linux的共享内存、交换区等资源进行工作，如果你的内核参数设置不能满足oracle的要求，那在安装oracel9i或使用过程就会频频出现问题，因此配置系统内核的参数就显得尤为重要和关键了。

内核参数的配置一般在/proc文件夹下配置：
1. 以root用户允许以下命令；
2. 进入目录/proc/sys/kernel；
3. 用cat命令或more命令查看semaphore当前参数的值：
cat sem
命令运行后将会出现如下的结果：
250 32000 32 128
其中, 250 是参数SEMMSL的值,32000是参数SEMMNS的值, 32是参数SEMOPM的值，而128则是参数SEMMNI的值。
4. 用以下的命令可以对上述参数进行修改
echo SEMMSL_value SEMMNS_value SEMOPM_value SEMMNI_value > sem
其中SEMMSL_value、SEMMNS_value、SEMOPM_value、SEMMNI_value分别用相应的值进行替换，并且这些值的顺序不能调换

5. 设置共享内存大小，共享内存大小一般设为物理内存的一半，在这里我们假设物理内存为512M则共享内存的值4294967295以此类推，如果你的物理内存是1G则这里的值则是8589934590：
echo 4294967295 > shmmax
添加用户
Oracle在安装和使用中需要用特定用户（非root用户），按照oracle的标准说明是需要添加三个专门用户和用户组，为了简便大家的安装和使用我们把oracle的安装和使用归到一个特定用户来完成。
首先创建oracle用户组，我们架设这个用户组命名为dba：
以root用户登陆系统；
运行groupadd dba命令添加dba用户组；

添加oracle用户：
以root用户登陆系统；
运行useradd –g dba –p password –d /oracle –s /bin/bash oracle
运行后系统创建了一个属于dba用户组的用户oracle，密码为password，主目录为/oracle使用bash

这个用户将作为系统的安装和使用指定用户，因此要妥善保存好！
创建安装点(mount point)
oracle9i的典型安装需要至少两个安装点：一个安装基本的运行程序，要求至少要有850M的硬盘空间；一个为存放数据库，至少要求有450M的硬盘空间。为了简化安装我们可以把运行程序和数据库装在同一个安装点下。
在你的文件系统上找到有足够空间的分区，在分区下创建文件夹，我们假设这个文件夹为/oracle。
配置系统环境变量
很多网友安装oracle失败都是因为环境变量没有配置正确，环境变量的配置直接影响到以后oracle9i的安装和配置，在配置的时候要尤为小心！
配置x-windows变量
确认oracle9i在安装过程中是否使用本地x-windows安装还是远程虚拟x－windows安装，如果需要远程x-windows安装，则需要配置DISPLAY变量，这个变量用于告诉系统屏幕的图形将输出到什么位置，默认情况下是本机，如果你使用虚拟x－windows进行安装，则在这里指明远程终端的显示情况，比如你远程终端的IP地址是xxx.xxx.xxx.xxx则DISPLAY的变量应设为“xxx.xxx.xxx.xxx:0”后面的“:0”表示该终端的第一个显示器。
确定安装临时目录
前面我们提到过oracle9i的安装需要一个临时的可写空间，我们在这里把/tmp作为临时的可写目录。如果你不是使用/tmp作为临时可写目录则需要配置相应的值TMPDIR=/path。
配置oracle的环境变量

下面提供一个例子可以供大家参照使用
export DISPLAY="192.9.200.24:0.0"
export BASH_ENV=$HOME/.bashrc
ORACLE_HOME=/oracle/product/9.0.1; export ORACLE_HOME
ORACLE_SID=oracle; export ORACLE_SID
ORACLE_TERM=xterm; export ORACLE_TERM
TNS_ADMIN=/home/oracle/config/9.0.1; export TNS_ADMIN
NLS_LANG=american_america.ZHS16GBK; export NLS_LANG
ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data; export ORA_NLS33
LD_LIBRARY_PATH=$ORACLE_HOME/lib;export LD_LIBRARY_PATH
PATH=$PATH:/bin:/usr/bin:/usr/sbin:/etc:/opt/bin:
/usr/ccs/bin:/usr/openwin
PATH=$PATH:/opt/local/bin:/opt/NSCPnav/bin:$ORACLE_HOME/bin
PATH=$PATH:/usr/local/samba/bin:/usr/ucb:
export PATH
CLASSPATH=$ORACLE_HOME/JRE:$ORACLE_HOME/jlib:
$ORACLE_HOME/rdbms/jlib
CLASSPATH=$CLASSPATH:$ORACLE_HOME/network/jlib
TMPDIR=/tmp;export TMPDIR
umask 022

其中：
ORACLE_HOME为系统软件的安装目录；
ORACLE_SID 为数据库的SID，这里可以自行设置；
NLS_LANG 为数据库的字符集，为了保证数据库能够输出输入数据库，我们需要在这里把字符集设为american_america.ZHS16GBK，其中american_america英文字符集，ZHS16GBK为中文字符集。

以oracle用户登陆系统，
vi $HOME/.bash_profile
把以上环境变量的设置粘贴到文件中，确认相应的内容并修改，存盘退出。
重新登陆oracle用户
使用set|more命令查看oracle用户的环境变量是否生效
CLASSPATH=/oracle/product/9.0.1/JRE:/oracle/product/9.0.1/jlib:
/oracle/product/9.0.1/rdbms/jlib:
/oracle/product/9.0.1/network/jlib
DISPLAY=192.9.200.24:0.0
LD_LIBRARY_PATH=/oracle/product/9.0.1/lib:/lib:/usr/lib:
NLS_LANG=american_america.ZHS16GBK
ORACLE_HOME=/oracle/product/9.0.1
ORACLE_SID=oracle
ORACLE_TERM=xterm
ORA_NLS33=/oracle/product/9.0.1/ocommon/nls/admin/data
OSTYPE=linux-gnu
PATH=/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/usr/games:
/bin:/usr/bin:/usr/sbin:/etc:/opt/bin:/usr/ccs/bin:/usr/openwin:
/opt/local/bin:/opt/NSCPnav/bin:
/oracle/product/9.0.1/bin:/usr/local/samba/bin:/usr/ucb:
TNS_ADMIN=/home/oracle/config/9.0.1
仔细检查一下以上的几项，确保都设置正确了。

安装Oralce9i
安装JDK1.3.1
把下载的j2sdk-1.3.0-RC1-linux-i386.tar.bz2文件上传到服务器的/usr/local/目录下，以root用户登陆，用bzip –d j2sdk-1.3.0-RC1-linux-i386.tar.bz2命令先把文件解成tar格式，再使用tar xvf j2sdk-1.3.0-RC1-linux-i386.tar.bz2解压出来，为了便于操作可以把文件夹名改成jdk.。
配置x-windows
oracle9i的安装几乎支持所有的x-windows，也支持远程的虚拟x－windows安装，如果你要在本机安装在控制台上以我们先前创建的oracle用户登陆（注意要先设置好环境变量，并把DISPLAY的值设为空export DISPLAY=””）运行startx命令进入x-windows。
如果需要在远程终端使用虚拟x-windows进行安装，需要在客户端先安装x-win32软件，x-win32的安装过程我们就不多介绍了，安装完成后运行x－win32命令在你的任务栏会出现一个x的标致。使用neterm等终端攻击以oracle用户登陆系统确认环境变量都已经生效并且DISPLAY变量的值为你终端机的IP地址，运行startkde命令启动x-windows，运行完毕后系统会出现一大堆的出错信息，忽略不管，过了几秒后在你的远程终端上会出现Linux的kde界面。
下载Oracle安装软件
Oracle网站（http://otn.oracle.com）现在提供Oracle9i for Linux软件下载，在下载前请仔细阅读他的Licence，这样在今后的使用中才不会有版权问题。在下载前你需要一个otn的账户，申请是免费的，只要简单回答几个问题就可以，oracle9i的安装程序共有三个文件包分别是：
Linux9i_Disk1.cpio.gz (412,092kb)
Linux9i_Disk2.cpio.gz (638,547kb)
Linux9i_Disk3.cpio.gz (82,956kb)
下载完这三个文件后，把这三个文件上传到服务器/oracle目录下，并保证这三个文件的属主是oracle用户。如果你有Oracle9i的安装CD那就可以省下大把下载时间了。

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安装Oracle 9i 数据库
以oracle用户登陆系统，启动本地x-windows或虚拟x-windows，打开一个控制台窗口，进入到刚才存放oracle文件的目录下，分别使用
gunzip Linux9i_Disk1.cpio.gz
cpio -idmv
gunzip Linux9i_Disk2.cpio.gz
cpio -idmv
gunzip Linux9i_Disk3.cpio.gz
cpio -idmv
命令解包，把三个文件包解压缩成三个安装文件夹分别为Disk1、Disk2、Disk3。
进入Disk1目录
cd Disk1
在控制台窗口敲入
./runInstaller &
运行后会出现一个OUI的图形界面，如下图所示：

中间绿色的窗口就是oracle的安装图形界面了。
下面我们来进行oracle9i最基本的安装，在进入安装界面后点Next进入下一步：

Source指的是包含Oracle产品信息的文件，一般情况下他会自动识别到，如果找不到可以用Browse按钮来手工指定路径。
Destination指的是9i将要安装的路径这里就是我们在环境变量里设的$ORACLE_HOME，如果这一栏里是空白的则要重新检查环境变量中各值的设定是否有误。确认正确后按Next进行下一步：

这一步有三个安装选项供选择：
Oracle9i Database 9.0.1.0.0，安装oracle9i的数据库服务器版本、管理工具、网络服务以及基本的客户端软件；
Oracle9i Client 9.0.1.0.0 ，企业版的客户端软件，网络服务以及开发工具等。
Oracle9i Mangement and Integration 9.0.1.0.0，安装Management Server，管理工具Oracle的网络目录、综合服务、网络服务以及基本的客户端软件。
我们选第一项安装Oracle9i数据库服务其，接着安Next按钮；

这一步是选择Oracle安装的类型，有三个类型供选择Enterprise Edition，企业版，Standstard Edition标致版，Custom自定义安装，我们选择企业版的安装，如果你对Oracle这一系列的产品比较熟悉的化可以选择Custom自定义安装，按自己的需求选择组件进行安装，确认后安Next进入到下一步；

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这里可以选择一种适合你的数据库模版，一般我们选第一种通用的数据库模版，如果你需要使用数据仓库，则可以使用选择数据仓库的模版进行安装。确认后按Next进入下一步；

这一步是确认Oracle9i的SID和全局数据库的名字，SID的值我们在环境变量中已经设好了，所以这里就自动显示了，全局数据库名（Global Database Name）我们可以也指定成和SID的值相同，确认后按Next进入下一步；

前面我们提到了，数据库的字符类型在数据库超作中是很关键的，这一步就是设置数据库的字符集，前面我们设置的是NLS_LANG=american_america.ZHS16GBK，所以我们选择Simplifiled Chinese ZHS16GBK，按Next进入下一步；

因为我们在前面选择了Enterprise的版本进行安装，系统会安装Oracle Web Server，安装Oracle Web Server需要使用JDK，我们使用Browse按钮把前面安装JDK的目录指定好以便系统能在安装过程中找到需要的应用程序，确认按Next进入下一步；

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进行完所有选择后，系统会给出一个安装概要，这里列举了你选择安装的组件，确认你要安装的东西都在列表内后，安Install钮进行安装，如果不需要安装其它的程序，则按Exit退出安装界面。

Oracle的安装速度视服务器的性能一般来说需要装30分钟的时间，在安装过程中可能会有对话框弹出，对话框内会有一些需要root运行的命令要求你执行，这时候另外开一个控制台窗口，su成root并运行提示框内的命令，运行完毕后按确定继续安装；

安装完数据库后系统会运行配置工具对系统进行网络和数据库的配置。配置完成后，系统会自动启动数据库，并开启Oracle Web Server。所有配置完后，按Next完成安装。

如果一切正常，OUI会出现The Installation Of Oracle9i Database Was successful.的字样，这表明你的Oracle9i数据库安装正常了，如果需要安装其它的内容按Next Install钮进行其它内容的安装，否则按Exit退出安装。

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使用Oracle 9i 数据库
安装完毕后Oracle数据库会自动启动，下面我们用实际超作来说明一下Oracle 9i数据库的启动和关闭。
以oracle用户登陆数据库，开个控制台窗口；
关闭Oracle 9i 数据库
[oracle@wing /oracle]$ sqlplus " / as sysdba" //以sysdba用户登陆数据库

SQL*Plus: Release 9.0.1.0.0 - Production on Wed Jul 11 15:35:31 2001

(c) Copyright 2001 Oracle Corporation. All rights reserved.
Connected to:
Oracle9i Enterprise Edition Release 9.0.1.0.0 - Production
With the Partitioning option
JServer Release 9.0.1.0.0 - Production
运行shudown命令关闭数据库
SQL> shutdown
Database closed.
Database dismounted.
ORACLE instance shut down.
SQL>
启动Oracle 9i 数据库
[oracle@wing bin]$ sqlplus " / as sysdba"

SQL*Plus: Release 9.0.1.0.0 - Production on Wed Jul 11 16:00:59 2001

(c) Copyright 2001 Oracle Corporation. All rights reserved.

Connected to an idle instance.

SQL> startup
ORACLE instance started.

Total System Global Area 336356520 bytes
Fixed Size 279720 bytes
Variable Size 268435456 bytes
Database Buffers 67108864 bytes
Redo Buffers 532480 bytes
Database mounted.
Database opened.
SQL>

启动Oracle 9i监听程序
Oracle的监听程序主要是为客户端的连接提供接口
[oracle@wing bin]$ lsnrctl

LSNRCTL for Linux: Version 9.0.1.0.0 - Production on 11-JUL-2001 16:12:17

Copyright (c) 1991, 2001, Oracle Corporation. All rights reserved.

Welcome to LSNRCTL, type "help" for information.

LSNRCTL> start
Starting /oracle/product/9.0.1/bin/tnslsnr: please wait...

TNSLSNR for Linux: Version 9.0.1.0.0 - Production
System parameter file is /oracle/product/9.0.1/network/admin/listener.ora
Log messages written to /oracle/product/9.0.1/network/log/listener.log
Listening on: (DESCRIPTION=(ADDRESS=(PROTOCOL=ipc)(KEY=EXTPROC)))
Listening on: (DESCRIPTION=(ADDRESS=(PROTOCOL=tcp)(HOST=wing)(PORT=1521)))

Connecting to (DESCRIPTION=(ADDRESS=(PROTOCOL=IPC)(KEY=EXTPROC)))
STATUS of the LISTENER
------------------------
Alias LISTENER
Version TNSLSNR for Linux: Version 9.0.1.0.0 - Production
Start Date 11-JUL-2001 16:12:58
Uptime 0 days 0 hr. 0 min. 0 sec
Trace Level off
Security OFF
SNMP OFF
Listener Parameter File /oracle/product/9.0.1/network/admin/listener.ora
Listener Log File /oracle/product/9.0.1/network/log/listener.log
Listening Endpoints Summary...
(DESCRIPTION=(ADDRESS=(PROTOCOL=ipc)(KEY=EXTPROC)))
(DESCRIPTION=(ADDRESS=(PROTOCOL=tcp)(HOST=wing)(PORT=1521)))
Services Summary...
Service "PLSExtProc" has 1 instance(s).
Instance "PLSExtProc", status UNKNOWN, has 1 handler(s) for this service...
Service "oracle" has 1 instance(s).
Instance "oracle", status UNKNOWN, has 1 handler(s) for this service...
The command completed successfully
LSNRCTL>

关闭Oracle 9i监听程序
[oracle@wing bin]$ lsnrctl

LSNRCTL for Linux: Version 9.0.1.0.0 - Production on 11-JUL-2001 16:12:17

Copyright (c) 1991, 2001, Oracle Corporation. All rights reserved.

Welcome to LSNRCTL, type "help" for information.
LSNRCTL> stop
Connecting to (DESCRIPTION=(ADDRESS=(PROTOCOL=IPC)(KEY=EXTPROC)))
The command completed successfully
LSNRCTL>

关闭Oracle Web Server
cd $ORACLE_HOME/Apache/Apache/bin
./stopJServ.sh
/oracle/product/9.0.1/Apache/Apache/bin/apachectl stop: httpd stopped

启动Oracle Web Server
cd $ORACLE_HOME/Apache/Apache/bin
[oracle@wing bin]$ ./startJServ.sh
/oracle/product/9.0.1/Apache/Apache/bin/apachectl start: httpd started
启动Oracle Web Server后默认的端口号是7777
在客户端浏览器地址栏输入http://xxx.xx.xxx.xxx:7777/
如果浏览器出现以下界面则表示Oracle Web Server运行正常。
Q: Can Oracle9.01 install on Redhat 7.1 ?

I had failed many times to install oracle 9.01 on RedHat 7.1 . Would you help me ?
I had go to oracle web site , It said "
Installs on SuSe 7.1 Linux distribution only, Kernel version 2.4.4, and glibc version 2.2 "
would you tell me about SuSe 7.1 Linux ?

A:首先装RedHat7.1选择完全安装，因为它要安一些兼容的6.2包，选择完全就一定安上去。
创建Oracle用户,在.profile中加入
export LD_ASSUME_KERNEL=2.2.5
/usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh
安上IBMjdk1.1.8
这样就可以起动runInstaller,一直到建立数据库链接程序时，才会出问题。

再从OTN上下一个patch,将它打上，它解决链接问题。

--------------------------------------------------------------------------------
计算机世界网上有一篇文章, 去看看 http://www.ccw.com.cn/htm/app/linux/develop/01_7_25_3.asp

Q: 安装过程到link enterprise managers时，多项relink以.mk结尾的文件不成功，忽略后继续安装到配置net 8 时提示找不到libclntsh.so.8.0和libnjni8.so。什么原因?愁死我啦！请问哪位能拔刀相助！
Please check you gcc . I have same problem
on installing Oracle 8.1.7 once. and I find it is the gcc version cause at last .


ORACLE

ORACLE 8.1.6
Installing on Redhat Linux 7.1
JAVA
You need JDK118 version 3, suppose you install in /usr/local/jdk118_v3
Glibc

to make sure you're using compat-glibc2.1.3. check your glibc by issue command : gcc -v.

If not, copy and install the following in the same order:
compat-glibc-6.2-2.1.3.2.i386.rpm
compat-egcs-objc-6.2-1.1.2.14.i386.rpm
compat-egcs-6.2-1.1.2.14.i386.rpm
compat-libs-6.2-3.i386.rpm
compat-libstdc++-6.2-2.9.0.14.i386.rpm
compat-egcs-c++-6.2-1.1.2.14.i386.rpm

Accounts
you need at least one group and one user:

groupadd dba
useradd oracle -g dba
passwd oracle

Install directories

[root@rh70 /root]mkdir /usr/local/oracle

[root@rh70 /root]mkdir /usr/local/oracle/ora817

[root@rh70 /root]mkdir /usr/local/oracle/data
[root@rh70 /root]chown -R oracle:dba /usr/local/oracle
Oracle environment variables

login as oracle, type
umask to see if umask is 022, if not append umask 022 to /home/oracle/.bash_profile
[oracle@rh70 oracle]umask

Modify/home/oracle/.bash_profile:
#ORA_NLS=/home/oracle/ocommon/nls/admin/data
#export ORA_NLS
#NLS_LANG="simplified chinese"
#export NLS_LANG
ORACLE_BASE=/usr1/local/oracle
export ORACLE_BASE
ORACLE_HOME=/usr1/local/oracle/ora817
export ORACL_HOME
ORACLE_SID=ora1
export ORACLE_SID
CLASSPATH=$ORACLE_HOME/jdbc/lib/calsses111.zip
export CLASSPATH
LD_LIBRARY_PATH=$ORACLE_HOME/lib
export LD_LIBRARY_PATH
USERNAME="oracle"
PATH=$PATH:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/dbs
PATH=$PATH:/bin:/usr/bin:/usr/sbin:/usr/local:/usr/local/bin:/usr/bin/X11:/usr/X11R6/bin

ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data; export ORA_NLS33
NLS_LANG=AMERICAN.AMERICA.UTF8; export NLS_LANG
LD_ASSUME_KERNEL=2.2.5; export LD_ASSUME_KERNEL

umask 022 (only if umask is not 022)

. /usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh

Log out,login again with oracle, and type env to see the environement variables

Decompress Oracle8171_tar.gz

login as root, type:
---------------------------------------------------------------
[root@xinli test]tar zxvf oracle8161_tar.gz
[root@xinli test]chown oracle test
---------------------------------------------------------------
Install Oracle

very important, otherwise there will be character problems:
Change the locale:

export LANG=en_US and optionally export NLS_LANG=american

---------------------------------------------------------------
open another shell:
---------------------------------------------------------------
[root@xinli /root]su – oracle
[oracle@xinli /ora8]cd /home/test/Oracle8iR2
[oracle@xinli Oralce8iR2]./runInstaller
---------------------------------------------------------------

ollow the install instructions
Post-install

1.login as root, modify /etc/oratab, change the last line from
orcl:/uar/local/oracle/ora8.1.7:N
to:
orcl:/usr1/local/oracle/ora8.1.7:Y
So you can use dbstart and dbshut to start and stop the database, not the complicated svrmgrl scripts.

2.Write the startup commands to the system startup script:

modify /etc/rc.d/rc.local, add:

#modify kernel parameter
echo 134217728 > /proc/sys/kernel/shmmax
echo -e "250\t32000\t100\t128" > /proc/sys/kernel/sem

#start Oracle8.1.7
su - oracle -c 'lsnrctl start'
su - oracle -c 'dbstart'

if you want to start Apache at system boot, add:
#start apache httpd server
. /etc/profile
/usr/local/apache/bin/apachectl start

3. Modify Net8 - use netca or change listener.ora and tnsnames.ora under $ORACLE_HOME/network/admin

4. If setup 2nd database instance, use dbassist. If dbassist doesn't come out, temporarily disable $LANG,$NLS_LANG
unset $NLS_LANG
unset $LANG

Test using svrmgrl
[oracle@only_you oracle] svrmgrl
Oracle Server Manager Release 3.1.6.0.0 - Production
Copyright (c) 1997, 1999, Oracle Corporation. All Rights Reserved.
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SVRMGR>connect internal
Connected.
SVRMGR> shutdown
Database closed.
Database dismounted.
ORACLE instance shut down.
SVRMGR>startup
ORACLE instance started.
Total System Global Area 56012784 bytes
Fixed Size 69616 bytes
Variable Size 38993920 bytes
Database Buffers 16777216 bytes
Redo Buffers 172032 bytes
Database mounted.
Database opened.
SVRMGR> quit
Server Manager complete.

sqlplus

[oracle@only_you oracle]$ sqlplus
SQL*Plus: Release 8.1.6.0.0 - Production on Sun Apr 15 09:20:12 2001
(c) Copyright 1999 Oracle Corporation. All rights reserved.
Enter user-name: scott
Enter password: tiger
Connected to:
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SQL> select * from emp
SQL>quit
Oracle configuration file

# .bash_profile

# Get the aliases and functions

if [ -f ~/.bashrc ];

then . ~/.bashrc

fi

# User specific environment and startup programs

JAVA—HOME=/usr/local/jdk118_v3

export JAVA_HOME

JSDK_HOME=/usr/local/j2sdkee1.3

export JSDK_HOME

# ORACLE—TERM=386

# ORACLE_TERM=ansi

# Oracle_TERM=xterm

# export ORACLE_TERM

# export DISPLAY="169.254.37.140:0.0"

ORACLE_BASE=/usr/local/oracle

export ORACLE_BASE

ORACLE_HOME=$ORACLE_BASE/ora817

export ORACLE_HOME

ORACLE_SID=oral

export ORACLE_SID

USERNAME="oracle"

export USERNAME

ORACLE—OWNER=oracle

export ORACLE_OWNER

ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data

export ORA_NLS33

# NLS_LANG=AMERICAN.AMERICA.UTF8

# NLS_LANG=american_america.zhs16cgb231280

# NLS_LANG=american_america.ZHS16GBK

NLS_LANG=chinese_china.zhs16cgb231280

export NLS_LANG

TNS_ADMIN=/home/Oracle/config/8.1.7

export TNS_ADMIN

LD_LIBRARY_PATH=$ORACLE_HOME/lib

export LD_LIBRARY_PATH

LD_ASSUME_KERNEL=2.2.5

export LD_ASSUME_KERNEL

PATH=$PATH:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/dbs PATH=$PATH:/bin:/usr/bin:/usr/sbin:/usr/local:/usr/local/bin:/usr/bin/X11:/usr/X11R6/bin PATH=$PATH:/JAVA_HOME/bin:JSDK_HOME/bin:.

export PATH

CLASSPATH=.:$ORACLE_HOME/jdbc/lib/classes111.zip

export CLASSPATH

#umask 022 (仅当umask不为022时选择写入这一行)

. /usr/i386-glibc21-linux/bin/i386-glibc21-linux-env.sh

TMPDIR=/tmp

export TMPDIR

BASH_ENV=$HOME/.bashrc

export BASH_ENV

unset USERNAME


ORACLE

Web databases
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
Oracle database server

Oracle8i

Oracle9i

Oracle application server

Oracle Application Server4.0

Development tools

Oracle Designer

Oracle Developer

Oracle JDeveloper

Oracle Reports

Resources
  • http://www.oraclefan.net
  • http://oracle.myrice.com/
  • http://www.linuxforum.net/forum/postlist.php?Cat=&Board=oracle
  • http://ocp.6to23.com/
  • http://www.orafaq.com/faq.htm
  • http://www.oradb.net/
  • http://www.oracle.com/


Others

Web databases
Others
China

DBFT

dbft http://dbft.top263.net/

JBase

HYSQL

http://www.huayisoft.com/

EasyWeb

http://www.xinhong.net/

DfDraw, DfTask

http://www.doublefox.com/prod02.htm

DIPS

http://www.info-quick.com.cn/

Visual DBTOOLS

http://www.infolight.com.cn

DBTools

http://dbtools.myrice.com

EGrid?000

http://www.egrid2000.com/

DBMaker

http://www.dbmaker.com.tw/

Visual dBASE

http://www.sinter.com.tw/vbc.htm

RedSoft

http://www.readsoft.com.cn
GenSQL

http://www.coinfosoft.com

Data Anywhere

Data Bridge

JOX
International

Delphi

http://www.sybase.com

VisualFoxpro

http://www.microsoft.com

Pervasive.SQL

http://www.yida.com.cn/

Jasmine

http://www.ca.com

mSQL
  • http://www.hughes.com.au/
  • http://ftp.cdut.edu.cn/pub2/linux/system/database/msql/faq.html The mSQL FAQ

postgreSQL

http://www.pgsql.com.tw/

Access

http://www.microsoft.com

InterBase

    • http://www.borland.com/interbase/
    • http://www.3asoft.com

InstantDB

SAPDb

Solid

hsql db (Hypersonic)

Cloudscape

velocis

filepro

iODBC

Adabas

dBase

FrontBase

Empress

Unix dbm

Ingres


PostgreSQL

Create database
    create database owner - postgres

# groupadd postgres
＃useradd postgres -g postgres
＃passwd postgres
＃chown postgres.postgres -R /var/lib/pgsql

#chmod +x /var/lib/pgsql

Initiate database:
    #initdb －D /var/lib/pgsql/data -t /usr/lib/pgsql/

Use PostgreSQL

    #postmaster －i －D /var/lib/pgsql/data＆

    #createdb mydb
    #psql mydb

    mydb=>

    mydb=>create table test (id int2, name varchar(10), income int4);

...

Links

http://postgresql.gnuchina.org/

http://www.postgresql.org/


PandaSQL

网络数据库
DM3
IBase
Kingbase
OpenBase
PandaSQL
http://www.pandadb.com/

熊猫数据库管理系统是一套基于WEB和WAP的SQL数据库应用开发平台 (Application Development Platform)。它为数据表提供了增加/删除/更改/查找的WEB介面。并且内建独立的高级用户管理系统 (Advance User Permission System)， 用户访问记录系统，基于用户群组的电子邮件群发系统, 独立的用户自动注册系统, 所见即所得的 HTML 模板编写工具，插件开发系统 (Advance Plug-ins Development System)和中华商业网络的通用开发模组工具库 ( China Commercial Net Perl Development Module Library) 等。

熊猫数据库管理系统主要用于建构基于WEB和WAP的企业管理应用系统、大型的人才配对系统和大型的企业对企业(B to B)电子商务平台。

熊猫数据库管理系统特点

客户端：

客户端无须安装任何软件即可操作。意即用户可于世界任何一个角落或任何一台电脑访问数据库。

由于客户端介面完全由HTML模板生成，管理员只须使用WML设计模板，用户即可通过无线通讯设备利用WAP访问数据库。

每个数据表可独立设置使用不同的用户介面模组。

每个用户拥有独立的用户权限，包括： 增加/更改/删除/查询/管理。

拥有管理权限的用户可以增加/更改/删除用户。

每个数据表可独立设置成 允许/不允许用户通过自动注册生成。

每个数据表可独立设置自动注册用户的预设权限。

每个数据表可独立设置成用户只能更改/删除自己增加的记录。拥有管理权限的用户可更改/删除所有记录。

每个数据表可独立设置成用户只能查询自己增加的记录。拥有管理权限的用户可查询所有记录。

管理端：

管理员的每项工作都可通过基于WEB的管理介面完成，无须使用其他辅助工具(如: FTP 工具，HTML设计工具和基层SQL服务器管理工具等)。

管理员可通过管理介面直接创建/设计/设置数据表。

管理员可通过管理介面直接设置数据表的用户权限。

管理员可通过管理介面直接删除数据表。

管理员可通过管理介面直接在线导入任何拥有互联网连接或企业网连接的SQL数据库服务器内的数据表。

管理员可通过内建的SQLAdmin (中华商业网络的MySQL 数据库管理工具)进行高级数据库管理。

管理员可通过管理介面直接向SQL数据库发出SQL查询 (如: SELECT SUM(Quantity), ProductName FROM Inventory GROUP BY ProductName; )

管理员可通过访问记录浏览器检查每个数据表的使用纪录，纪录内容包括用户名/访问时间/访问时的IP地址/操作明细。

管理员可通过管理介面使用所见即所得HTML编辑工具直接编写数据表的外观模版。

管理员可通过管理介面向预设的用户群组发送电子邮件。

管理员可通过管理介面设置电子邮件群发列表。 管理员可通过插件开发精灵(Plugin Wizard)创建并编写外挂插件，用以加强熊猫SQL数据库管理系统功能。

管理员可通过插件管理员工具(Plugin Manager)安装/卸载/下载插件。

管理员可使用中华商业网络的通用开发模组工具库 (China Commercial Net Perl Development Module Library)，通过插件(Plugin)的方式，开发出千变万化的应用平台。


PandaSQL

Web databases
DM3
IBase
Kingbase
OpenBase
PandaSQL
http://www.pandadb.com/

熊猫数据库管理系统是一套基于WEB和WAP的SQL数据库应用开发平台 (Application Development Platform)。它为数据表提供了增加/删除/更改/查找的WEB介面。并且内建独立的高级用户管理系统 (Advance User Permission System)， 用户访问记录系统，基于用户群组的电子邮件群发系统, 独立的用户自动注册系统, 所见即所得的 HTML 模板编写工具，插件开发系统 (Advance Plug-ins Development System)和中华商业网络的通用开发模组工具库 ( China Commercial Net Perl Development Module Library) 等。

熊猫数据库管理系统主要用于建构基于WEB和WAP的企业管理应用系统、大型的人才配对系统和大型的企业对企业(B to B)电子商务平台。

熊猫数据库管理系统特点

客户端：

客户端无须安装任何软件即可操作。意即用户可于世界任何一个角落或任何一台电脑访问数据库。

由于客户端介面完全由HTML模板生成，管理员只须使用WML设计模板，用户即可通过无线通讯设备利用WAP访问数据库。

每个数据表可独立设置使用不同的用户介面模组。

每个用户拥有独立的用户权限，包括： 增加/更改/删除/查询/管理。

拥有管理权限的用户可以增加/更改/删除用户。

每个数据表可独立设置成 允许/不允许用户通过自动注册生成。

每个数据表可独立设置自动注册用户的预设权限。

每个数据表可独立设置成用户只能更改/删除自己增加的记录。拥有管理权限的用户可更改/删除所有记录。

每个数据表可独立设置成用户只能查询自己增加的记录。拥有管理权限的用户可查询所有记录。

管理端：

管理员的每项工作都可通过基于WEB的管理介面完成，无须使用其他辅助工具(如: FTP 工具，HTML设计工具和基层SQL服务器管理工具等)。

管理员可通过管理介面直接创建/设计/设置数据表。

管理员可通过管理介面直接设置数据表的用户权限。

管理员可通过管理介面直接删除数据表。

管理员可通过管理介面直接在线导入任何拥有互联网连接或企业网连接的SQL数据库服务器内的数据表。

管理员可通过内建的SQLAdmin (中华商业网络的MySQL 数据库管理工具)进行高级数据库管理。

管理员可通过管理介面直接向SQL数据库发出SQL查询 (如: SELECT SUM(Quantity), ProductName FROM Inventory GROUP BY ProductName; )

管理员可通过访问记录浏览器检查每个数据表的使用纪录，纪录内容包括用户名/访问时间/访问时的IP地址/操作明细。

管理员可通过管理介面使用所见即所得HTML编辑工具直接编写数据表的外观模版。

管理员可通过管理介面向预设的用户群组发送电子邮件。

管理员可通过管理介面设置电子邮件群发列表。 管理员可通过插件开发精灵(Plugin Wizard)创建并编写外挂插件，用以加强熊猫SQL数据库管理系统功能。

管理员可通过插件管理员工具(Plugin Manager)安装/卸载/下载插件。

管理员可使用中华商业网络的通用开发模组工具库 (China Commercial Net Perl Development Module Library)，通过插件(Plugin)的方式，开发出千变万化的应用平台。


Sybase

网络数据库
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
Sybase

Sybase中国 - http://www.sybase.com.cn/
数据仓库及商务智能

利用集成的数据仓库技术，与合作伙伴的应用相结合，为客户提供开发所需的集成的数据仓库解决方案。

Sybase Warehouse Studio

是一套端对端的产品集，以其卓越的性能，数据集成以及对计算机资源的利用，在客户分析，市场划分和财务规划方面提供了专门的分析解决方案。最新推出的

Industry Warehouse Studio 3.2

是适合不同行业商业智能与分析型客户关系管理的最佳数据仓库解决方案。产品高度集成了分析型应用模板、数据模型、原型开发方法及在数据仓库设计与元数据管理方面的领先工具。广泛应用于多个行业，包括零售业、银行业、财产与人寿保险业、信用卡业务、医疗保健业、电信业及资本市场等。

Adaptive Server IQ

（为简单计，在本文以下的介绍中将简称为Sybase IQ，甚至更简单地称为IQ）首次正式发布是在1996年2月，第一个目标环境是Sun的UNIX，同年秋季一个增强了的版本即可运行于几乎所有主要的UNIX平台上了。1997年，IQ不但实现了对Windows NT的支持，而且同时完成了对能有效地处理关系型星型模式的IQ优化器的改进。到1997年底，该产品在功能上进一步有大的增强，即实现了IQ表与由 Sybase Adaptive Server Enterprise （ASE） 所管理的表的透明连接。1998年年中所发布的11.5.2版，补充和强化了一系列旨在提高性能的新特性。IQ的最新版（Release 12）是去年10月发布的，从1999年一季度开始已正式进入市场。这一版为提高性能，伸缩能力及互操作性而在体系结构上有一系列重大变化，因而是该产品发展过程中的一个新的里程碑。与前一版相比，最新版的IQ在查询和加载效率上提高了30%到300%不等，具体的量级因应用类型的不同而会有所不同。为了增强伸缩能力，最新版具备了新的多线索结构和对多处理机的支持能力。经由一个整合在IQ中的中间件界面，最新版的IQ现在不仅对Sybase数据库用户极具吸引力，而且也越来越多的吸引着非Sybase数据库的广大用户群。另一个重要的变化，是IQ的最新版拥有自己的目录系统，从而使它不再依赖于Sybase 的其他数据库产品

Data warehousing 本质上是一个寻求完整解决方案的过程。但是，由于这一领域的专业经验不足，有时由于需求的误导，在经历了几个月甚至几年的工作之后，所得到的结果仍然差强人意。针对这种情况，Sybase推出了

Industry Warehouse Studio，

一个元数据驱动的框架。从某种意义上说，它是提交商业智能解决方案的一个指南性的设施。诚如旅游者借助于旅行指南能够快速地从一地赶往另一地一样，Industry Warehouse Studio对不同的行业提供建立数据仓库的指导性建议，旨在通过对应用、数据模型和支持工具的高度集成，为商业智能与客户关系分析管理提供数据仓库解决方案，与此同时提高投资回报和降低商业风险。Sybase运用Industry Warehouse Studio所针对的行业包括：零售业、银行业、财产与人身意外保险、信用卡业务、医疗保健业、电信业、人寿保险以及资本市场。

Industry Warehouse Studio 充分利用了Warehouse Studio在数据仓库设计与元数据分析管理方面的一批在业界领先的工具。Industry Warehouse Studio在数据模型、元数据和工具方面都是开放的，全部支持Oracle , Microsoft , Informix和IBM 的关系数据库管理系统。另外，Industry Warehouse Studio还拥有Warehouse Studio的可任选的ETL（抽取/转换/加载）功能和高速大量数据存储功能。Industry Warehouse Studio的核心是一组集成化的商业智能应用，内容涉及商业战役分析、销售分析、客户兴趣分析、客户构成分析以及客户忠诚性分析等。支撑这些商业智能应用的，是一组集成化的逻辑数据模型与物理数据模型。这些模型是从关键性业务功能中归纳和提炼出来的，其内容涉及到促销与活动、客户关系、客户联络、销售以及赢利等。

元数据管理是企业级数据仓库中的关键组件。用户需要对所收到数据的历史进行了解，如从哪里来？流通时间有多长？对它已经进行了哪些计算、转换和筛选等等。通过对元数据仓库的集中管理，Sybase的

Warehouse Control Center

提供了数据仓库解决方案的保证技术。从设计和开发到实现到最终用户访问，由工具和数据库产生的对元数据的密集型集成和管理保证了真正企业级数据仓库的建立。Warehouse Control Center是基于Intellidex技术的为数据仓库开发人员提供的数据仓库元数据管理工具，能够在数据仓库环境下进行数据采集、捕捉、存储、管理和发布逻辑的、物理的以及上下文相关的信息，而不用去管它的物理存储位置是在联合数据仓库上、分布式数据仓库上还是二者兼有。业务用户可以浏览根据其需求而生成的元数据对象，甚至可以使用发布和登记性能请求或选择附加性能。

在整个数据仓库环境中，Warehouse Control Center可以从关键数据仓库组件中收集元数据，以便向业务用户传递正确的信息。它采集、集成和描述元数据的范围十分广泛，可以在设计和建模过程中，可以从抽取和转换过程中，也可以从数据移植和移动过程，可以从数据库/数据存储组件，也可以从最终用户工具。从面向主题的数据集市到企业范围的数据仓库环境，这种中心数据同步是保证Sybase数据仓库平台可扩展性的关键因素。

企业核心系统解决方案

交付公司运营系统所需的产品和专业服务。包括数据管理、应用开发、复制和集成解决方案。产品的研究和开发包括企业级数据库，数据复制和数据访问。主要产品有：Sybase 的旗舰数据库产品

  • Adaptive Server Enterprise，
  • EnterpriseConnect，
  • Replication Server

及异构数据库互连选件。

该部门在全球发布了业界第一个"永不停顿"的企业门户产品，在网上实现企业的商业运作环境，为用户提供个性化的门户服务。

电子商务计算在降低成本、提高电子化商务处理和数据的价值的同时，也提出了对支持特定的电子商务功能的关系数据库管理系统(RDBMS)的需求。Sybase公司借助于

Adaptive Server Enterprise (ASE) 12.5

的发布正好满足了这一需求。Adaptive Server Enterprise (ASE) 12.5是Sybase公司永不停顿的高性能企业智能型关系数据库管理系统的最新版本，它所提供的许多先进特性使其成为支持联机商务处理的先锋，尤其是它为传统的企业迁移到电子商务环境提供了一条快速而正确的途径。

ASE是一个深受用户欢迎的高性能数据库，它具有一个开放的、可扩展的体系结构，易于使用的事务处理系统，以及低廉的维护成本。这一点对于利润率很低的联机商务运作尤其关键。而且在最近进行的Transaction Processing Council-C (TPCC) 性能测试中已被证明，ASE所消耗的内存、外存储器和CPU资源要比其它的关系数据库管理系统低得多。ASE 12.5版本正是在ASE的这些强大的基础之上创建的， 它通过提供一系列先进的、具有创新性的功能，大大地拓展了ASE的基础，从而也使它成为用于智能电子商务部署最引人注目的选择。

例如，ASE 12.5提供了对Java存储过程的支持、支持Java用户自定义函数和数据类型，支持在服务器上通过Java访问远程服务器，所有这一切将快速应用开发推进到一个新的高度。通过提供对扩展标记语言（XML）搜索的支持，其功能得到了进一步的增强。支持扩展标记语言（XML）搜索是一个创新，它允许用户无需编写自定义代码就可搜索XML文档。ASE 12.5在数据服务器中部署Enterprise JavaBean (EJB)组件的能力提高了数据的安全性，并使性能得到了优化。基于行的安全特性和连接层加密确保了数据的安全性和可靠性。一系列的功能增强 - 从使用第三方的工具进行系统参数的动态配置到优化性能 - 进一步确保了电子商务的动态性能。

由于ASE 12.5是在与诸如EMC、Veritas、Embarcadero Technologies以及其它提供补充解决方案的供应商进行紧密合作下而开发的，因而它使得企业的电子商务应用开发和部署变得更快捷、更简便。

Sybase的

Enterprise Connect

为用户需要的能用于所有数据库互联与复制的软件提供了一份易于安装、易于维护的解决方案，而不需考虑采用了多少不同的数据库。把Repliaction Server、Replication Agent、Jconnect、OpenServer/OpenClient、OmniConnect和DirectConnect等产品的技术集成在一起，Enterprise Connect提供了在异构数据源中进行分布式事务复制、位置透明、与应用独立的进行数据存取等功能。

Sybase Replication Server

突破了分布式数据库的限制，为实际商业需求提供了一种非常灵活的系统框架。老的分布式数据库框架依赖于两阶段提交，而这种方式系统开销很高，并且常常由于任何节点的失败而导致整个系统的停顿。另外也可采用单纯的表快照机制，但这种方式并不以事务为基础，因此缺乏基本的事务完整性与一致性。

Replication Server可以在client/Server网络中对不同平台的数据进行复制。它提供了极高的OLTP性能，同时可以避免OLTP和DSS操作的冲突。

Replication Server 提供高级别的本地自治功能。远端可以使用安全远程更新模式修改数据。可以采用不同的计划、数据格式和命名转换来传递数据，从而同步数据库。灵活的事件触发机制可以使每一个节点都能根据本地需求来做出响应。

Replication Server 被设计成为一种支持"fail-through"方式的应用结构，使得当系统某节点失败时，用户可以不间断他们的工作。当失败的节点修复时，Replication Server可以自动地将积压的数据续传。

电子商务
该部门是在收购企业应用集成软件公司NEON后建立的。利用公司在企业门户、Internet应用和企业集成方面的专业技术，为市场提供最完整、最具竞争力的企业级电子商务套装软件。解决方案包括所有NEON产品，权威的企业门户产品（Enterprise Portal），屡获殊荣的应用服务器EA Server以及优秀的应用开发工具PowerDesigner、PowerJ。将增强Sybase作为电子商务基础架构供应商的实力。

Sybase EAServer 3.6新特性
应用服务器是建立N层应用系统的核心，许多厂商都推出了应用服务器产品，作为全球著名的软件厂商，Sybase很早就认识到了应用服务器的重要性，并且早在1997年就推出了企业级的应用服务器EAServer 1.0（当时称为Jaguar 1.0），在以后的几年中，Sybase陆续推出了新的版本，并且始终是业界的领先者，目前，EAServer的最高版本是3.6，本文将介绍EAServer 3.6版本的新的技术特性。

完全支持J2EE 平台
    Java 2 Enterprise Edition (J2EE) 平台日益成为一个重要的中间层商业逻辑的体系结构标准。Sybase EAServer从3.5版本开始就支持J2EE的大多数功能，在3.6版本中，对此做了进一步的增强，从而可以全面支持J2EE。

Enterprise JavaBean 增强
    EAServer 3.6 实现了最新的Enterprise JavaBeans 1.1 版本的标准。EJB 1.1 模型与EJB 1.0在软件上不兼容。EAServer 支持这两个版本，与EAServer 3.5 和 EJB 1.0 服务器保持向后兼容性，这是通过用户在组件属性中设置EJB 版本来实现的。

Java Servlet 支持的增强
    J2EE中最新的Java Servlet 2.2 版本标准包括了许多新特性，包括请求发送（request dispatching）、 响应缓冲以及与Web应用模型的集成用于标准化的设置和提交。EAServer 3.6 可支持Java Servlet 2.2 版本。

支持Java Server Page
    Java Server Page (JSP)是一个 包含Java 代码的HTML 文件，可生成动态内容。JSP 编程模型允许用户完成绝大多数Java servlet 模型可以完成的工作，并且更简单而且更易学。EAServer 实现了1.1 版本的JSP标准，允许用户设置和提交一个JSP 作为Web 应用的一部分。

支持Web 应用
    一个Web 应用是相关的Web 内容、JavaServer Pages (JSPs)和Java servlet 的一个提交的单元。Web 应用包含静态文件 、servlet 和 JSP 实现的类以及一个描述文件，EAServer 3.6可支持Web 应用。

J2EE 应用支持
    一个 J2EE 应用是一个Web 应用和Enterprise JavaBean 组件的提交单元。应用内容可以被归档在一个 Enterprise application Archive (.ear) 文件中，以便于在不同的服务器上安装和设置。

    为了支持J2EE 应用，EAServer 3.6 引入了应用的概念，在EAServer中， 一个应用是相关的web文档的打包， 用户可以将一个应用输出为 标准的J2EE .ear文件 格式， 同时也可以将J2EE 的 .ear文件引读入到EAServer 之中。

支持Java 后端 API标准

    依照 J2EE 平台标准， EAServer 支持如下的后端API：
    ● JDBC 和 事务支持的增强
     EAServer 3.6 支持在JDBC 2.0指定的标准 JDBC 连接缓冲模型。如果你有一个JDBC 2.0 驱动器 , 你可以使用此模型取代EAServer的 Java Connection Manager (JCM) API。EAServer也实现了在J2EE和EJB 1.1标准中指定的事务功能。

    ● Java Naming and Directory (JNDI)支持的增强
     Java servlets、JSP 和 EJB 组件现在可以使用JNDI 别名指向 EJB home interfaces、数据库连接和 JavaMail 服务器。通过在Web 和 EJB 组件中使用别名可以简化重新设置，例如，当组件提交到另一个服务器，无需改变源代码，只需修改组件的外部设置即可。 　　 ● 支持JavaMail
     JavaMail 是Java API标准。在 EAServer 3.6中，你可以使用 JavaMail 从一个Java 组件、 JSP或 servlet 中发送邮件。例如， 可以在一个联机订单应用中发送确认的电子邮件。

ActiveX 支持的增强

    在EAServer 3.6中，ActiveX 现在可以支持更多的IDL数据类型，包括IDL typedef、IDL enumeration和IDL union。此外，现在可以使用 try/catch意外处理功能来处理非关键性的错误，就像Java 或 C++ 语言一样，这样做的一个好处就是可以简化处理可恢复错误的代码。

异步消息支持
     EAServer 3.6 包括一个消息服务，可用于异步的事件通知。消息服务是通过一个EAServer 组件来实现的，它可被所有的客户和组件使用。消息服务提供了短暂和长期的消息存储，消息可被发送到特定的队列中，或按照特定的主题发布信息，所有的消息队列都可以获得。通过消息服务，用户可以接到用户通知，同时也可以发布消息给指定的用户。

显式的服务器线索支持
     EAServer 3.6 包括一个 Thread Manager 组件，可用于产生、延缓和停止执行一个组件实例的线索。通过线索，你可以实现必须与客户端请求的执行无关的服务器端的处理。Thread Manager 增强了对EAServer 服务组件的已有的支持，有更好的灵活性。

与高可用性数据库的集成
     Sybase Adaptive Server Enterprise 12.0 的高可用性可以保证在一个数据库服务器发生故障时，另外一台服务器接替它的工作，在EAServer 3.6中，与数据库的JDBC连接可以支持Sybase Adaptive Server Enterprise 12.0的高可用性功能，实现数据库连接的高可用性和失败转移，从而提高对数据库访问的可靠性。

结论

    Sybase的EAServer 3.5已经是业界领先的企业级应用服务器，它可以支持业界主流的Corba, Com 和EIB组件标准，同时还支持高可用性和负载均衡，并且提供非常好的安全保障，正因为如此，今年的1月EAS 3.5获得了PCWEEK 分析家选择奖，EAServer 3.6的推出，则必将进一步巩固Sybase在应用服务器市场的领先地位。

Enterprise Portal
诠释企业门户新概念 --Sybase EP2.0

随着信息技术的飞速发展，企业正在逐步向网络商务时代登临。在演进商务形式的过程中，企业门户（Enterprise Portal，EP）技术应运而生。这种技术允许用户通过网络访问个性化的界面和应用来实现商务活动，将客户、雇员、合作伙伴或供应商的业务流程直接连接，并且不需要繁琐的、深入的了解就可以进行自我服务，从而帮助企业达到节约资源、拓展市场的目的。

然而，环境的发展带来了新的挑战，那就是新的应用层出不穷，而原有的企业门户形式如何才能支持这些新型应用呢？无庸置疑，现实呼唤功能更全面的企业门户产品，以便使企业能够驾驭ERP和CRM系统等新时代的企业业务应用。在支持这些应用的同时，新的企业门户产品还应该在可管理性、安全性和可靠性方面提供更令人满意的设计理念，以充分满足全面的应用需求，并适合未来的应用潮流。正是基于上述认识，著名的独立软件开发商、电子商务基础架构提供商Sybase公司在原有产品EP1.0的基础上推出了升级产品--EP2.0，为企业带去更强大、更全面的门户功能选择。

【概述】
Sybase Enterprise Portal (EP) 对于门户和电子商务应用的开发和提交提供了集成和统一的电子商务基础架构。Sybase EP1.0提供了门户的基础架构;统一的系统管理；端对端的安全架构；内容管理；服务的个性化和集成服务。它是建立在企业平台的连续可用性和对互联网不可预测需求进行处理的伸缩能力之上的。在此基础上，Sybase EP 2.0 扩展了许多功能，尤其在以下方面：

通过增强的门户服务实现集成和统一的电子商务基础架构。
B2B扩展实现自动B2B交易和交易市场的集成。
移动和无线扩展集成了企业内部移动和无线设备。
实现可扩展电子商务基础架构支持新的和不断发展的电子商务应用。
有效利用现有IT资产的企业集成服务。

New Era of Networks
New Era of Networks 公司主要产品简介
为加强在电子商务解决方案市场的领先地位，Sybase公司日前宣布，以3.73亿美元的价格收购New Era of Networks 公司。New Era of Networks 公司（New Era of Networks）为应用至应用（A2A）领域提供完整的企业应用集成产品系列及服务。New Era of Networks 的主要产品包括New Era of Networks Process Server、New Era of Networks e-Biz Integrator和预打包解决方案--New Era of Networks 转换器，适用于各种现有应用和标准。利用New Era of Networks 转换器，用户可以方便地集成最先进的ERP，CRM，供应链管理和来自SAP，Siebel，i2和BroadVision的商业应用

PowerBuilder
Sybase Power Designer 7
第一个真正的对象/关系分析和设计解决方案

PowerDesigner 7简介

无论是对象还是数据库设计人员都一直希望能够将对象设计、数据库设计和关系数据库生成无缝地集成起来。Sybase为此提供了一个功能强大的解决方案 ? 即业界第一个集成的面向对象和数据库建模工具PowerDesigner 7.0，它在一个界面中集成了面向对象的分析与设计功能和数据库建模(概念和物理数据模型)功能。在PowerDesigner 7.0中， 可生成 Java 和 PowerBuilder 源代码。

PowerDesigner 7.0不仅仅是一个数据建模工具，它为企业提供了一个完整的建模软件解决方案。 PowerDesigner 7 是业界第一个同时提供数据库设计开发及应用开发的建模环境的软件，通过PowerDesigner 7，复杂的分布式应用可以更快速和方便的开发，从而使企业在新的Internet 时代具有竞争优势。

PowerJ
PowerJ是业界领先的标准的企业分布式应用开发工具，是一个基于组件的、高效率开发环境，并且多次获得优选开发工具奖。它支持各种JDK版本，支持JavaBeans、ActiveX和CORBA等组件标准，体现了真正的开放性。它与PowerBuilder和Enterprise Application Server紧密集成，可以对应用服务器端的逻辑组件方便快捷地进行创建、打包、提交和调试。

PowerJ的主要特点：
工具的扩展

包含了PowerSite：PowerJ包含了性能优异的PowerSite，一个用来建立、管理和提交Web应用的完整的RAD环境，增强了WEB页面的开发能力、提交能力和版本控制能力；
包含了PowerDesinger AppModeler：PowerJ包含了基于物理模型生成Web应用对象和数据敏感组件的AppModeler，为用户应用系统的设计提供方便。
能够访问多种组件模式

Jaguar CTS的体系结构是由多种组件模式构成的，应用系统可以同时执行任何组件标准如J2EE， CORBA；
PowerJ建立的Applets可以透明地调用Jaguar CTS中的各种组件并返回数据。
可与Jaguar CTS无缝集成

PowerJ可以很容易的创建EJB组件和Java类，然后把它们提交到中间层。PowerJ的生成向导能够快速地建立Jaguar CTS服务器组件；
为建立真正的薄客户端的数据库应用，PowerJ的查询对象可以很容易地从Jaguar CTS中返回结果集；
查询对象可由PowerJ中的组件向导进行生成，无需手工编程既可建立。
能够集成CORBA对象

PowerJ可以非常容易地建立和集成CORBA对象，只需通过编辑IDL文件就可以自动完成；
PowerJ根据IDL文件的设置信息调用IDL-to-Java编译器建立Java Stub，Stub可与ORB上运行的对象进行通讯；
开发者可以把这些对象增加到PowerJ的组件控制板中，并且可以通过参考卡查看这些对象的所有方法。
扩展了可伸缩Web服务器

PowerJ可以快速地进行Web应用的开发、调试和提交，它支持ISAPI,NSAPI,CGI等Web服务器，可以与它们进行交互操作，测试和修改Web应用。
增强的Web Client/Server应用开发

PowerJ可以利用强大的数据敏感型EJB组件建立复杂的数据库应用，包括列表、文本框、表格和数据导航控制等；
著名的DataWindow技术，包括ActiveX和纯Java组件的DataWindow，具有灵活的表现风格，丰富的表格形式和图形。
具有丰富的表格组件

PowerJ提供了强大的Java方式的表格显示和处理数据方式，如文本格式化、行和列的大小变化、排序、高亮条的搜索、列的拖拽排序、间隔选择等；
在数据单元格中可以放入任何Java组件，如List Boxes, Radio buttons, Images,Picture Buttons甚至可以放入表格（Grid）；
数据单元格可以与数据库查询绑在一起，以便于报表和编辑。
通过jConnect for JDBC进行高效数据访问

PowerJ包括开发版的Sybase jConnect for JDBC，它由纯Java写成，完全符合JDBC标准，它可以使开发者在多层的、异构的环境中植入数据库访问功能；
JConnect可以高速地访问Sybase数据库，并且通过Directconnect和OmniConnect访问其他25种以上的数据源；
JConnect可以为薄客户的Java应用提供占用资源很小的（small footprint）数据库连接方案。
强大的基于组件的开发和提交能力

PowerJ可以用拖拽的编程方式进行Java应用开发，通过强大的参考卡和参数化的编程向导可以充分发挥出Java的优点;
PowerJ对EJB、ActiveX和CORBA组件具有很强的支持能力，在所有EJB组件和包（Package）中都可以建立纯Java应用，运行在Java VM平台上;
PowerJ的组件重用性可以方便地在客户端、服务器端和中间层服务器上创建、测试和提交新的EJB组件;
PowerJ可以把第三方的ActiveX和EJB组件无逢地集成到PowerJ环境中。
全面的开发和调试

PowerJ提供了一个强大的工具集，几乎包括了开发人员所需要的一切：程序代码编辑器、集成化的调试器、菜单和工具条的编辑器、完备的文档和例子程序；
l PowerJ的上下文调试器不但能够灵活地操作，而且调试器和程序编辑器之间有很密切的联系，错误信息能够显示在编辑栏中，便于立刻修改程序代码。
容易创建JavaBean组件

PowerJ可以通过简单的点击方式创建标准的EJB组件，使用类向导可以快速地建立组件和增加或修改类、属性、方法和事件；
PowerJ为增加开发效率，每个组件都可以自动生成出参考卡，开发者可以通过拖拽方法进行编程操作；
PowerJ可以生成Jframes、Japplets、Jdialogs、Jpanel、Jwindows、JMenu和JtabbedPane等全部JFC类；
新版PowerJ更新了Chart Lite、Table Lite和BWT组件的Swing版本
创建DataWindow JavaBeans组件

DataWindow的Java版本现在已经成为PowerJ中的一个组件，这是用Java实现的PowerBuilder DataWindow。
使用与PB 6 和PB7相同的PBL、PBD和PSR格式。可以支持所有的表现风格，除了图形、Rich文本和OLE，但是在DataWindow中增加了对AWT和JFC（Swing）的支持，就如同支持不可视数据存储组件一样。
完整的Web解决方案

PowerJ提供灵活的提交方式，提交的目标代码的类型可以是.JAR、.CAB和.ZIP文件，这样可以把几个完成的应用放在一个文件中，便于分布地提交到其他站点；
PowerJ可以对Applets、Servlets和整个应用进行严格地调试。
支持团队开发

PowerJ为项目组提供了ObjectCycle 2.0，一个强大的应用对象控制工具。
PowerJ支持全面的Intersolv PVCS、MKS RCS、MKS 源代码完整性集成化版本控制界面；
PowerJ支持Microsoft的SCC。
全面支持开放标准

支持全部JDK 1.1x、JDK 1.2和JDK 1.0.2
支持JFC/Swing组件
支持JavaSoft和Microsoft VM
支持JavaBeans、ActiveX和CORBA等组件模式
支持Jaguar组件模式

支撑平台

主机：Pentium 75 MHz 以上，CD-ROM 驱动器l
内存：32 MB
占用硬盘：标准安装需230 MB
操作系统：Windows 95，Windows NT


Sybase

Web databases
DB2
Informix
Lotus
MS SQL
MySQL
Oracle
Sybase
Sybase

http://www.sybase.com.cn/, http://www.sybase.com

Here below is just a (non-complete) listing of Sybase's products related to databases and enterprise applications. For details please visit Sybase's website or consult with one of their experts.
Data warehouses & business intelligence
Sybase Warehouse Studio

Industry Warehouse Studio 3.2

Adaptive Server IQ

Industry Warehouse Studio

Warehouse Control Center
Enterprise core system solution

Adaptive Server Enterprise (ASE) 12.5

Enterprise Connect

Sybase Replication Server

E-business

Sybase EAServer 3.6

Sybase Enterprise Portal (EP)
New Era of Networks
PowerBuilder

PowerJ


industry software

Indsoft.doc
SCM.doc
hydro.doc
powersoft.doc
qualitysoft.doc
solar.doc
tradesoft.doc
wind.doc

comp.htm

crm.htm

erp.htm

mis.htm

net.htm

oa.htm

plc.htm

proj.htm

scm.htm


公司

电力企业信息化
呼叫中心 | CRM | ERP | MIS | OA | SCM | 网络构建 | 项目信息 | 公司
业界翘楚

东软

电力行业管理信息系统整体解决方案

东软软件电力系统解决方案

金蝶

金蝶K3系统完善东方电机交直流公司基础

金蝶K3系统在广东火电工程总公司的应用

康柏

康柏电力行业

电力行业信息系统解决方案

郎新

办公自动化

电力Intranet应用

电力调度管理信息系统

电力市场技术支持系统

调度SCADA系统

客户服务系统

配电管理系统（DMS）

生产管理系统

营销系统

朗新成功建设浙江省电力营销管理信息系统

优达

优达IBM助力宁夏电力信息化

易普软件

北京江河瑞通技术发展有限公司

上海司普计算机技术有限公司

OA（办公自动化）产品、规划计划业务软件等相关产品

光华电力

光华电力营销系统(县市版)(农村供电所版)

新华控制工程有限公司

管理信息系统MIS

郑州安通信息有限公司

电厂生产信息管理系统


CRM

电力企业信息化
呼叫中心 | CRM | ERP | MIS | OA | SCM | 网络构建 | 项目信息 | 公司
CRM - 客户关系管理

国内现有CRM产品类型分析

电力企业客户关系管理系统

http://www.mycrm.com.cn/

联成互动MyCRM - 联成互动作为国内CRM（客户关系管理）软件与应用服务提供商，专注于CRM领域，为中小企业用户提供CRM解决方案和专业服务。

http://www.turbocrm.com/

TurboCRM - 客户关系管理（CRM）应用方案供应商，可提供软件及在线使用。

http://www.sellwell.com.cn/

sellwell客户关系管理（crm）系统网站 - 介绍国内第一套中文版，本地化客户关系管理系统软件。适合在国内开展业务的中小型企业使用。

http://www.powercrm.com.cn/

PowerCRM客户关系管理网 - CRM的相关资讯、知识，跟踪国内外的发展动态，进行有关CRM的技术交流服务。

销售套件：

客户关系与联系人管理
销售机会管理
销售活动管理
销售时间表管理
待办事宜与工作流
产品配置与报价
销售渠道管理
销售合同管理
网上定购
销售预测预报表
客户信息与消费分析
竞争对手跟踪

市场营销套件：

市场预算欲收入跟踪管理
市场活动管理
市场活动反响跟踪
促销内容管理
市场宣传资料
工作流自动化
任务管理
市场衡量指标
时间表管理
电话促销管理
邮件促销管理
WEB促销管理

服务套件：

客户和联系人信息
统一标准答案于解决方案
服务跟踪与外勤服务
服务订单
产品维修
管理
任务管理
待办事宜与工作流
产品投诉跟踪
客户建议与提案
WEB资料库与客户资助
服务分析

电子服务套件：

网上订单
渠道关系管理
WEB资料库与自助服务
Call Center
Email Center
Web Center
Up-selling&Cross-selling
PowerCRM平台
组织机构与人员管理
权限管理
工作流管理
系统配置
系统外部接口


ERP

电力企业信息化
呼叫中心 | CRM | ERP | MIS | OA | SCM | 网络构建 | 项目信息 | 公司
ERP/MRP II

四通摩天ESRP解决方案
ERP在电力企业管理中的应用

http://www.superdata.com.cn/shop/sd3000.asp

速达3000 - 以业务为基础，财务为核心。包括进货管理、销售管理、仓库管理、帐务系统、工资管理等子系统。繁简版自选安装、使用大型数据库interbase5.0，数据安全性更高。

http://www.platsoft.com.hk/

白金中国 - 财务软件，考勤，生产管理，远程数据库访问，ERP系统及电子商务的开发和方案。

http://www.vems.net/

中小型企业管理软件展示网 - 计算机进销存，财务，商务软件，提供免费下载和咨询。

安易2000ERP www.anyi.com.cn

东软金算盘www.gasoft.com.cn
www.imarket.com.cn

www.cssoft.com.cn

www.citystar.net.cn
中国erp软件网 - http://www.chinaerpsoft.com 介绍提供企业财务管理，人力资源管理，电子商务，客户关系管理等软件。
杭州新中大软件有限公司 - http://www.ngsoft.com.cn/ - 从事企业管理软件的研究和开发，主要软件产品包括：新中大财务软件、PowerERP、信贷管理系统和房产销售管理系统。
北京和佳软件技术有限公司 - http://www.hjsoft.com.cn/ - 从事ERP、出版、办公、人事、财务、零售等计算机软件产品的开发和实施服务。


网络构建

电力企业信息化
呼叫中心 | CRM | ERP | MIS | OA | SCM | 网络构建 | 项目信息| 公司
网络设计

CA方案

Turbolinux IA架构解决方案： 电力电子商务解决方案

抚顺供电公司网络管理系统解决方案

汉江集团公司信息管理系统网络设计及实施

火电厂计算机集成过程系统

辽宁电力企业内部网络

网络助推电力行业


OA

电力企业信息化
呼叫中心 | CRM | ERP | MIS | OA | SCM | 网络构建 | 项目信息| 公司
OA-办公自动化，包括局域网，互联网，广域网

电力企业办公自动化管理系统的设计与应用

大坝发电厂办公自动化的设计和实现

常德电业局MIS数据浏览系统

E捷办公电力版

湖南电力广域网OA系统正式运行

http://www.beibang.com/

E-OFFICE - 一套基于互联网的办公自动化系统，是针对中小型企业，为提高员工工作效率、节省日常开资而设计的。

http://www.sunwayworld.com/matrix/oa_about.htm - SuperOA.Matrix全球办公系统(办公自动化) - 以开发办公自动化系统、工业控制软件和石化企业CMIS软件为主。

北京惠讯锐达软件公司（原北京锐步管理软件公司） - 专业软件开发，提供基于domino/notes平台的办公自动化（oa）、数据接口、数据采集软件

http://www.zrjinma.com.cn/

北京中软金马计算机系统技术有限公司 - 核心产品:OA、智能报表系统、工程项目管理MIS系统、工作流中间件系统、邮政综合网中心局、支局生产作业系统、邮资票品管理系统、邮政综合代收代缴系统、电话银行系统、中软金马邮政递送管理与服务系统

http://www.919.com.cn/

北科奔腾电子技术公司， 奔腾2000网络公管理平台，公文处理系统，

http://www.bysoft.net/

红禾工作室 - 政府通用OA系统,企事业单位通用OA系统,大型电厂电力调度OA系统,电视台新闻稿件管理系统,房地产信息发布系统

http://www.springflute.com.cn/

基于Web的企业内部网办公软件 - 基于内部网站的办公管理软件

http://www.eesys.com.cn/

亿赛网上办公系统 - eOffice网上办公系统完全基于“浏览器/服务器”方式，由收文管理、发文管理和档案管理组成的文档一体化系统。

http://www.itkey.net/
WinStar OA 2000: 0571-8512 4723 Ms Hu

http://cos.nihao.net/　－　协同办公系统 - 由你好万维网开发，该系统是基于 Intranet 的 Web 技术，完全采用B/S体系结构的内联网办公系统

http://www.ioffice2000.com.cn/　i-Office网络办公自动化 - i-Office软件产品是全面使用互联网，JAVA技术，采用了浏览器/Web服务器的B/S构架的新一代网络办公系统。

http://webmail.jindizi.com/

企业办公管理平台 - 基于WEB的企业协同办公管理系统。

http://www.hotoa.com/

火焰山网络办公自动化软件 - 完全基于浏览器，拥有通用的工作流，支持在线租用。

http://202.104.128.213/

倍邦网络智能办公系统 - 一套基于互联网的网络办公系统，是针对中小型企业，为提高员工工作效率、节省日常开资而设计的。

http://www.standsoft.com/ - 办公之星

http://www.aredian.com.cn/ -

http://oa.joy63.com/ - 泽悦自动化办公系统 - 泽悦高效率的无纸化办公系统，功能实用，操作简单。

http://www.officeweb.com.cn/ - 龙盟网上办公/龙盟科技公司 - 提供网上办公自动化软件。


PowerNet

Intro
eMarketing
WebTech
Translation
Other
Prices
ChinaReporting
SpecialOffers
overview news laws products projects software shows newspaper magazines firms stocks links

foreword
solar
wind
online calculation
Linux Systems
Server
Programming
Databases
Multimedia
NetCommunications
PLC
PowerNet

http://www.rwe-powerline.de/

German utility giant RWE said on Monday it had launched its powerline technology service which delivers high-speed Internet access by sending data through electricity cables.

RWE hopes for rapid expansion of the new product, called RWE PowerNet, now that Germany has passed new laws setting out the framework for the use of the technology.

“We aim to win 20,000 customers by year-end,” Michael Laskowski, managing director of RWE Powerline GmbH told Reuters in an interview.

He said RWE PowerNet was launched on Sunday in Muehlheim and in RWE's home town of Essen, in Germany's industrial heartland, or Ruhr region. It would be offered in more Ruhr cities in the region in the second half of this year and in the Bonn area. Besides using existing electric plug sockets, powerline promises speeds of up to two million bytes per second, or more than three times the speed of latest phone connections promoted by Deutsche Telekom.

RWE Powerline, a unit of RWE distribution arm RWE Plus, planned to offer the technology over the next three years across its distribution region in west Germany, Laskowski said.

RWE Powerline spokesman Andreas Preuss said 7,000 customers in Essen and Muehlheim had already registered their interest and Cologne was the next city to be targeted.

The company has a target of signing up 100,000 powerline customers in 2002, he added.

PRICE COMPETITION WITH BROADBAND ADSL SERVICES

Advances in the technology over the last few years had been slow, yet analysts think if successful, it might change the telecommunications landscape to the benefit of utilities.

Germany's parliament in March approved three laws setting out the conditions for powerline operations which come into force July 1.

They ensure, for example, that the system does not interfere with electrical appliances or radio frequencies needed for emergency services.

RWE charges customers according to the amount of data they receive, ranging between 49 and 249 marks a month.

For the entry level price of 49 marks per month, users may download 250 Megabytes of data. A typical picture sent via email uses around 0.5 Megabytes.

The utility will compete with other high-speed internet connections to the home such as television cable and super-charged copper telephone wires known as asymmetric digital subscriber lines (ADSL).

Deutsche Telekom in March said it had sold 850,000 broadband ADSL lines and installed 400,000, with subscribers paying 65 marks a month.

Laskowski dismissed concerns over possible hardware shortages which have been mentioned by analysts.

Switzerland's Ascom (ASCZ.S) will provide the modem needed inside a consumer's home to get the signals from the electricity cable into the computer.

Laskowski also said RWE was testing powerline in a field trial in Brazil.

Manufacturers

US/Canada

Cisco

HP

Intel

Advanced Micro Devices(AMD)

Conexant Systems

Enikia

Intellon- PowerPacketSSC-P300

Motorola- cable Modem

S3-Diamond Multimedia

Tandy/RadioShack

Texas Instruments

3Com

Compaq

Phonex Broadband - powerline transformer

Sonicblue -powerline MP3 player

Inari

Leviton
Northern Telecom
Norweb Communications

Nortel

National Semiconductors - LM1893

Thomson Consumer Electronics
Japan

Sony

Sharp

Panasonic

Hitachi

Mitsubishi

Toshiba
Europe

Siemens

UK nSine - “nPlug”

SGS Thomson - ST7536

Spain -DS2(http://www.ds2.es)
ASCOM in China / Hong Kong

Ascom Asia Pacific Ltd.
Room 705-6, 7th Floor
151 Gloucester Road
Wanchai
Hong Kong China

Phone: +852 28 30 98 11
Fax: +852 28 95 45 58
mchung@ascomhk.com

Ascom Energy Systems Ltd.
Units 1-4 20th floor New Trend Center
704 Prince Edward Road East
San Po Kong Kowloon
Hong Kong China

Phone: +852 2306 1234
Fax: +852 2353 6981

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AGARWAL WEB GRAPH BASED SEARCH BY USING DENSITY OF KEYWORD AND AGE FACTOR p5.pdf
Bhawnani Mathematics at Google p15.pdf
Brin The Anatomy of a Large-Scale Hypertextual Web Search Engine p20.pdf
Broder Graph structure in the web p15.pdf
Deo Graph-theoretic analysis of the world wide web new directions and challenges p21.pdf
Giatsidis Search in BigData - When Big Text meets Big Graph p5.pdf
Húsek2005 DATA CLUSTERING FROM DOCUMENTS TO THE WEB p31.pdf
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My Diary and Blogs

I used to maintain a presence in some of the most popular social networking sites, but I later found out that some of them are not very user friendly - I mean they sometimes don't allow me to publish certain posts as they declared that they are in violation of their policies. And to publish my contents, I need to conform with their formats, thus disabling me to use my own preferences of text, image and media formats if I would like to use. There are risks when these sites might be closed for various reasons, and then my investment will all be gone. The local authorities might block the access to a number of Internet surfers particularly those from the People's Republic of China. In one word, it is very inconvenient to use a third party site to publish my contents.

In addition, I have found out that my sites in the social networking sites were not much useful to promote my business and social contacts and thus I will never open accounts in any third sites and I will only rely on my own sites to expose myself to the world, partly also because I own enough skills to develop a well designed website for myself, whatever technologies are available(:

Hence I have withdrawn from all the social network sites and disappeared for a number of years. And now it's time to come up again and tell the world what I am doing and what I have done. This site and several other sites I am maintaining are still in preparation and therefore there are contents mixed up or very disorderly organized. I hope sooner or later the situation will be improved.

My Dairy:

Here below I will publish my diary on monthly basis:
  • Nov 2014
  • Dec 2014
  • Jan 2015
  • Feb 2015

More info:

2014

2014nov.htm

000private_lifehuzhou2015.doc
Diary.html


Diary

别了，我的德语！别了，我的法语！别了我的希腊语！。。。永别了，我的芯片！

今天， 2015年11月24日星期二， 对我是一个很重要的日子，也是一个很凄凉的日子。 因为，在经历了11 年无数次的考虑， 无数次的反复后， 终于决定彻底放弃除了英语以外的所有其它语言（德语，法语，俄语，希腊语，拉丁语以及世界语）。在2004年公历年底，在从浙江苍南返回的路途（当时是去苍南-有说是中国的耶路撒冷- 参与宗教活动）中， 我跟一个同道说，要考虑是否保持我的多门外语之事（当时我还不会希腊语和拉丁语），从那时起，我时常在想，有没有必要维护那么多外语。 过去，我的外语水平发挥了极大用处， 在德国，法国，英国和美国公司如鱼得水。 如今，在杭州这个省会城市，基本没有用途，英语除外，因为我还需要跟世界各国的学者，商人及其它各色人等通讯，阅读英文的各种资料，书刊等。 在杭州我没有固定工作，因为没有一个公司跟我的背景相匹配。所以，外语基本没有用处。 然而，我的特殊的外语才能，强烈的兴趣，无法使我下的了决心放弃哪怕是其中一门。 犹犹豫豫了11年之久，今天终于决定彻底放弃。

而要说清楚为何要如此“绝情”，恐怕又需要许多的笔墨。 最主要的原因， 是我恨透了上述国家以及他们虚伪的真面目。他们使我伤心至极。 过去，我对西方各国还抱有好感。在1992年间， 我还获得上述多个国家的名校攻读博士的机会， 只是因为一个女人之故而未成行。 我在那年轻轻松松考取雅思7分， 其中口语达到9分。英国人以为我的英语接近他们的水准。 我写英语无须通过中文， 直接写， 不打草稿， 不用翻译， 而且不比写中文慢（也许更快）。 我已经很少读中文，更少写中文。英语是我的工作语言。 1992年我在广东核电时， 就可以随随便便写个几十页的英文报告。 我在西方跨国公司工作时， 是何等的受到宠爱， 溺爱！西方人是何等的尊重我！因为我的外语水品几乎无人可敌， 我的专业也非常有竞争力， 况且我跟其他中国人不同的是， 我的工作能力，敬业认真，思考问题的系统性逻辑性，很少有人具备。 可以毫不夸张地说， 那时的我，根本不把谁放在眼里，当然包括西方人。

在外语上耗费了我不知多少时光，才华！我的同学都知道我的这个特点。 但如今，现实如此残酷，光阴如此暗淡，除了放弃， 别无它途！ 眼下，生存如此不易，一个豺狼当道，劣币驱逐良币，邪恶战胜善良，权利确定一切的社会，除了金钱和权利以外，没有什么其它的东西能保证你的生活体面，安全。没有人在乎你会多少外语，但非常在乎你住什么样的房子，开什么样的车子，玩什么样的婊子。

别了，我的德语！别了，我的法语！别了我的希腊语！。。。

以此同时，也决定放弃芯片技术的研究， 只保留图论的研究。 我原先的想法是研究我们这个时代最重要的科学相关的数学。而显然， 最重要的是芯片技术，它是我们当今文明的基石。 没有它， 就没有计算机和自动控制系统，就没有一切的现代技术。 所以，理所应当地研究芯片技术及其相关的数学。芯片设计中非常重要的是芯片的布线routing，而布线最重要的是图论的理论，和算法。 我开始先进入传统的硅CMOS芯片的物理设计，主要是布线，后来转向新一代芯片技术的研发，有几十种之多，包括量子芯片，DNA芯片等。 然而， 由于种种原因， 也得放弃。以我目前的生活状况，已经无力再继续学习研究下去了。

永别了，我的芯片！

这样， 我就只能做些纯粹的图论研究（目前是graph embedding and TSP – Traveling Salesman’s Problem）， 以及维持一点英文水准。 只有这样， 我才能腾出手来处理业务（例如本博客涉及的软件破解以及我的本行电力设备的贸易咨询等）， 否则我只得喝西北风了。

有得必有舍，所谓舍得。必须壮士断腕，否则， 被一些毫无用处的学习耗尽年岁， 到头来，一场虚空。 不过， 话说回来， 人生本是虚空。 试问这个地球上， 有几个人真的活得有价值？ 迄今，人类尚未找到人生的真正意义。 所有的人都舍本逐末。所有的人都是一场悲剧。耶稣也没有找到答案。


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网站名称及网址 |  | pacoffice.com亚太办公在线
 | 注册信息 | 管理员：cmhpaco,620721 团队：zhangming,admin@softhousing.com 采购小组：zhangming
网站名称及网址 |  | ego800.com
 | 注册信息 |
网站名称及网址 |  | 正广和85818.com.cn
 | 注册信息 |
网站名称及网址 |  | 壹元网1-yuan.com
 | 注册信息 |
网站名称及网址 |  | 索宝searchbuy.com.cn
 | 注册信息 |
网站名称及网址 |  | eachnet.com
 | 注册信息 | cmh_2000,92259694
网站名称及网址 |  | coolbid.com.cn
 | 注册信息 | cmh,620721
网站名称及网址 |  | yabuy.com
 | 注册信息 | cmhyabuy,620721
网站名称及网址 |  | ebid.com.cn
 | 注册信息 | cmhebid,464111
网站名称及网址 |  | fm365.com
 | 注册信息 | cmhfm365,620721
网站名称及网址 |  | 中国电子交易网chinaedeal.com
 | 注册信息 |
网站名称及网址 |  | 中国电子元器件交易网chinaecnet.com
 | 注册信息 | cmhecnet,100230
网站名称及网址 |  | aladeng.com阿拉灯
 | 注册信息 |
网站名称及网址 |  | 百特商厦byteplaza.com
 | 注册信息 |
网站名称及网址 |  | 美中通联uslinkcn.com
 | 注册信息 | cmhuslinkcn,620721
网站名称及网址 |  | www.lalasho.com拉拉手
 | 注册信息 | 公司：cmh@softhousing.com,620721 个人：sales@softhousing.com
网站名称及网址 |  | 中国食品网echinafood.com
 | 注册信息 |
网站名称及网址 |  | 100ok.com
 | 注册信息 | 个人用户cmh100ok IT企业用户cmh100ok1 非IT企业用户cmh100ok2
网站名称及网址 |  | 西单商场(http://www.xdsc.com.cn )
 | 注册信息 | 电子商务顾客号:1659, 密码:620721
网站名称及网址 |  | SurplusGlobal
 | 注册信息 | cmh@softhousing.com,620721
网站名称及网址 |  | sinobnet.com慧聪
 | 注册信息 | cmhsinobnet,620721
网站名称及网址 |  | Works.com
 | 注册信息 | cmhworks,620721
网站名称及网址 |  | ecplaza.net
 | 注册信息 | cmhecplaza,620721
网站名称及网址 |  | china-net.de
 | 注册信息 | 620721, solaires@21cn.com
网站名称及网址 |  | chinabig.com
 | 注册信息 | cmhbig,620721
网站名称及网址 |  | securetenders.com
 | 注册信息 | solaires@sohu.com
能源电力网站
网站名称及网址 |  | power66.com
 | 注册信息 | cmhpower,cmh620721, solaires@sohu.com
网站名称及网址 |  | cec.org.cn
 | 注册信息 | cmhcec,cmh620721, solaires@sohu.com
网站名称及网址 |  | ccspc.com.cn
 | 注册信息 | cmhccspc,cmh620721, solaires@sohu.com
网站名称及网址 |  | grchina.net
 | 注册信息 | cmhgrchina,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://wires0.ises.org/wirereg.nsf/Database?Open
 | 注册信息 | cmhiseswire,cmh620721, solaires@sohu.com
 |  | password: yle646
网站名称及网址 |  | powerproduct.com
 | 注册信息 | cmhpower,cmh620721, solaires@sohu.com
网站名称及网址 |  | chinadian.net
 | 注册信息 | cmh,620721, solaires@sohu.com
网站名称及网址 |  | powerec.com.cn
 | 注册信息 | cmhpower,620721, solaires@sohu.com
网站名称及网址 |  | sinoepower.com
 | 注册信息 | cmhsino,cmh620721, solaires@sohu.com
网站名称及网址 |  | chinapower.com.cn
 | 注册信息 | cmhchinapower,cmh620721, solaires@sohu.com
网站名称及网址 |  | crein.org.cn
 | 注册信息 | cmhcrein,cmh620721, solaires@sohu.com
网站名称及网址 |  | solarinfo.de
 | 注册信息 | ID: 36077115, PIN: 32169190, solaires@sohu.com
网站名称及网址 |  | nicepower.com
 | 注册信息 | cmh620721, solaires@sohu.com
网站名称及网址 |  | ep.net.cn
 | 注册信息 | cmhep,rb5n6ajg, solaires@sohu.com
网站名称及网址 |  | shp.com.cn
 | 注册信息 | cmhshp,cmh620721, solaires@sohu.com
网站名称及网址 |  | top50-solar.de
 | 注册信息 | cmhpower,cmh620721, solaires@sohu.com
网站名称及网址 |  | buyenergyhere.com
 | 注册信息 | solaires,cmh620721, solaires@sohu.com
 |  | acc/code: solaires, company ID: 429
搜索引擎
网站名称及网址 |  | sohu.com
 | 注册信息 | 1)姓名：陈明华, solaires@21cn.com 2)softhousing@21cn.com
 |  | 时力(solaires)新能源与信息技术有限公司 网站设计,网页制作,网络多媒体,网络通讯,太阳能软件,风力发电软件 推荐的栏目： 首页＞计算机与互联网＞网络/通讯 首页＞公司企业＞计算机与互联网＞因特网服务＞网络电话及传真 首页＞计算机与互联网＞多媒体 首页＞公司企业＞计算机与互联网＞多媒体 首页＞计算机与互联网＞互联网＞网页制作和发布 首页＞公司企业＞计算机与互联网＞因特网服务＞网页制作服务 首页＞公司企业＞计算机与互联网＞因特网服务＞企业上网服务 首页>国家与地区>浙江>城市/地区/县>杭州市>公司/企业>能源/动力 首页>国家与地区>浙江>公司企业>能源/动力 首页>公司企业>能源/动力>太阳能
网站名称及网址 |  | sina.com.cn
 | 注册信息 | 1) name:陈明华, solaires@21cn.com 2)contact person: henry chen/chen minghua, cmh@softhousing.com 3) cmh, sales@softhousing.com 4)free mail: cmhclub, 620721, 14478227, 971197244 5)cmh, chen_minghua68@hotmail.com 6）chen minghua, solaires@sohu.com 新浪首页＞搜索首页＞计算机与互联网＞通讯与网络 新浪首页＞搜索首页＞计算机与互联网＞多媒体 新浪首页＞搜索首页＞计算机与互联网＞网上教程＞网页制作 新浪首页＞搜索首页＞商业经济＞公司＞基础设施＞能源
网站名称及网址 |  | netease.com
 | 注册信息 | 1)chen_minghua68@hotmail.com 2)solaires@sohu.com,站点ID： 1001993552
 |  | 时力(solaires)新能源与信息技术有限公司 时力新能源信息技术研究室为国内外客户提供网站设计,网页制作,电子商务咨询,数据库开发,网络多媒体制作,网络通讯,新能源(太阳能,风力发电)软件开发与应用，翻译等服务
网站名称及网址 |  | 263.net
 | 注册信息 | chen_minghua68@hotmail.com
网站名称及网址 |  | fm365.com
 | 注册信息 | chen_minghua68@hotmail.com
网站名称及网址 |  | tom.com.cn
 | 注册信息 | chen_minghua68@hotmail.com
网站名称及网址 |  | msn.com
 | 注册信息 | 1)http://www.solaires.com/ENGLISH/index_en.htm,solaires@sohu.com
网站名称及网址 |  | aol.com
 | 注册信息 |
网站名称及网址 |  | lycos.com
 | 注册信息 | 1)http://www.solaires.com/ENGLISH/index_en.htm,solaires@sohu.com
网站名称及网址 |  | excite.com
 | 注册信息 | 1)http://www.solaires.com/ENGLISH/index_en.htm,solaires@sohu.com
网站名称及网址 |  | infoseek.com,go.com
 | 注册信息 |
网站名称及网址 |  | web.de
 | 注册信息 | solaires@sohu.com
 |  | solaires - Ihrer Internet-Zugan nach China Solaires ist eine Internet-basiert Firma in Hangzhou, schoene Stadt Chinas. Wir bieten Webdesign ...
网站名称及网址 |  | altavista.com
 | 注册信息 |


网络通讯

网站注册信息
网络通讯
网站名称及网址 |  | dotdialer | pc to phone
 | 注册信息 | ID: 53752575
网站名称及网址 |  | netmeeting
 | 注册信息 | solaires@21cn.com
网站名称及网址 |  | OICQ
 | 注册信息 | Tiger2001,ID: 81518186, cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | ICQ2000
 | 注册信息 | Tigerchen,ID: 120700927, cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | AOL Instant
 | 注册信息 | cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | Sohu
 | 注册信息 | SOQ: 123960
网站名称及网址 |  | Yahoo!Messengaer
 | 注册信息 | 1)chen_minghua,, cmh620721 2)minghua_chen2000, 620721
网站名称及网址 |  | mediaring.com
 | 注册信息 | ID: 1160 0678, cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | 网络观察
 | 注册信息 | cmhphone,620721
网站名称及网址 |  | phonefree.com
 | 注册信息 | 1)ID: 4793275, 620721, solaires@21cn.com 2)ID: 4865259, chen_minghua68@hotmail.com, cmh620721
网站名称及网址 |  | v2tec
 | 注册信息 | ID: 715851
网站名称及网址 |  | MSN
 | 注册信息 | ck18ml9qxu, chen_minghua68@hotmail.com
网站名称及网址 |  | myfree ID (sumavoice)
 | 注册信息 | cmhsuma,ID: 487797, chen_minghua68@hotmail.com
网站名称及网址 |  | pc2call
 | 注册信息 | cmhpc2call,PIN: 1752040436874521, cmh620721,chen_minghua68@hotmail.com
网站名称及网址 |  | net2phone
 | 注册信息 | PIN: 62072, chen_minghua68@hotmail.com
网站名称及网址 |  | phonehog.com
 | 注册信息 | 1-800-382-9980,PIN: 4306566529, chen_minghua@yahoo.com
网站名称及网址 |  | trulyglobal.com
 | 注册信息 | cmh,ID: c77183
网站名称及网址 |  | faxwave.com
 | 注册信息 | cmh620721, chen_minghua68@hotmail.com
网站名称及网址 |  | conflab.com
 | 注册信息 | cmh620721, chen_minghua68@hotmail.com
网站名称及网址 |  | wangdynasty
 | 注册信息 | cmhdynasty,ID: 487797, chen_minghua@yahoo.com
网站名称及网址 |  | komini.com
 | 注册信息 | cmh620721, sex you, 8214735, solaires@sohu.com
网站名称及网址 |  | vseeu.com
 | 注册信息 | cmh620721, 陈明华,solaires@sohu.com
网站名称及网址 |  | messenger asap
 | 注册信息 | cmh2001,620721, chen_minghua68@yahoo.com
网站名称及网址 |  | sohu exchange net
 | 注册信息 | chen_minghua,cmh620721, soq*: 123960,chen_minghua68@yahoo.com
网站名称及网址 |  | deltathree
 | 注册信息 | UID: 44313787,0721, chen_minghua@yahoo.com
网站名称及网址 |  | hottelephone.com
 | 注册信息 | acc no.: 196207219,cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | dialpad
 | 注册信息 | cmhdial,cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | buddyphone
 | 注册信息 | chen_minghua@yahoo.com
网站名称及网址 |  | sina.com.cn
 | 注册信息 | chen_minghua2001,cmh620721, #2663 8654
网站名称及网址 |  | cuseeme
 | 注册信息 | chen_minghua@yahoo.com
网站名称及网址 |  | 8dcall
 | 注册信息 | cmh8d,cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | iSpQ videochat
 | 注册信息 | cmh620721, chen_minghua@yahoo.com
网站名称及网址 |  | netsprite
 | 注册信息 | cmhnetsprite,12552 03743
网站名称及网址 |  | NICQ
 | 注册信息 | cmhnicq,cmh620721
网站名称及网址 |  | odigo
 | 注册信息 | chen_minghua,cmh620721, 4915142
网站名称及网址 |  | TomQ
 | 注册信息 | cmhtom,cmhtom,620721, ID: cmhtom1103
网站名称及网址 |  | trillion
 | 注册信息 | cmhtri
网站名称及网址 |  | poptel
 | 注册信息 | cmhpop,cmh620721, chen_minghua@yahoo.com, cmh@poptel.com
网站名称及网址 |  | hotvoice.com
 | 注册信息 | mailbox: 86*194593, pass: 26462071, email: solaires@cn.hotvoice.com
网站名称及网址 |  | http://www.247fax.com
 | 注册信息 | solaires, cmh620721,solaires@sohu.com,solaires@247fax.com
 |  | fax server nubmer in the US 1-213-688-1488
电子邮件
网站名称及网址 |  | citiz.net
 | 注册信息 | 1)solaires@citiz.net,cmh620721
 |  | 2)021-88912373,620721, 您的全球ID号是：88802188912373 您的电话端密码是：620721 你所在地区的服务电话号码是：16008888 ( 限上海本地使用 )
网站名称及网址 |  | hotmail.com
 | 注册信息 | 1.solaires@sohu.com, cmh620721
 |  | 2.chen_minghua68@hotmail.com, ck18ml9qxu
网站名称及网址 |  | solaires.com
 | 注册信息 | 1)solaires@sohu.com, uj80e4, w6g2d5w7, solaires.com
 |  | 2)cmh@solaires.com, uj80e2, m6v9c3y6
网站名称及网址 |  | 21cn.com
 | 注册信息 | solaire@21cn.com, cmh620721
网站名称及网址 |  | sohu.com
 | 注册信息 | 1)chen_minghua2001@sohu.com, cmh620721, pop.sohu.com, smtp.sohu.com
 |  | 2)solaires, cmh620721, pop3.sohu.com
 |  | 3)nickname: solaires_new
网站名称及网址 |  | 163.com
 | 注册信息 | solaires@163.com, cmh620721, pop.163.com, smtp.163.com
网站名称及网址 |  | 163.net
 | 注册信息 | chen_minghua2001@163.net, 620721, pop.163.net, smtp.163.net
网站名称及网址 |  | fm365.com
 | 注册信息 | 1)chen_minghua2001@fm365.com, cmh620721, mail.fm365.com, mail.fm365.com
 |  | 2)solaires@fm365.com,cmh620721
网站名称及网址 |  | etang.com
 | 注册信息 | 1)chen_minghua99@sohu.com, cmh620721, pop.etang.com, smtp.etang.com
 |  | 2)solaires,cmh620721
网站名称及网址 |  | 263.net
 | 注册信息 | 1)solaire, 620721, 263.net, smtp.263.net
网站名称及网址 |  | usa.com
 | 注册信息 | solaires@usa.com, cmh620721
网站名称及网址 |  | mail.com
 | 注册信息 | solaires@mail.com, cmh620721
网站名称及网址 |  | unicum.de
 | 注册信息 | solaires@unicum.de, cmh620721
网站名称及网址 |  | msn.com
 | 注册信息 | solaires@msn.com, cmh620721
网站名称及网址 |  | lycos.de
 | 注册信息 | solaires@lycos.de, cmh620721


电子邮件

网站注册信息
电子邮件
网站名称及网址 | citiz.net
注册信息 | 1)solaires@citiz.net,cmh620721

2)021-88912373,620721,

您的全球ID号是：88802188912373

您的电话端密码是：620721

你所在地区的服务电话号码是：16008888 ( 限上海本地使用 )
网站名称及网址 | hotmail.com
注册信息 | 1.solaires@sohu.com, cmh620721
2.chen_minghua68@hotmail.com, ck18ml9qxu
网站名称及网址 | solaires.com
注册信息 | 1)solaires@sohu.com, uj80e4, w6g2d5w7, solaires.com
2)cmh@solaires.com, uj80e2, m6v9c3y6
网站名称及网址 | 21cn.com
注册信息 | solaire@21cn.com, cmh620721
网站名称及网址 | sohu.com
注册信息 | 1)chen_minghua2001@sohu.com, cmh620721, pop.sohu.com, smtp.sohu.com
2)solaires, cmh620721, pop3.sohu.com
3)nickname: solaires_new
网站名称及网址 | 163.com
注册信息 | solaires@163.com, cmh620721, pop.163.com, smtp.163.com
网站名称及网址 | 163.net
注册信息 | chen_minghua2001@163.net, 620721, pop.163.net, smtp.163.net
网站名称及网址 | fm365.com
注册信息 | 1)chen_minghua2001@fm365.com, cmh620721, mail.fm365.com, mail.fm365.com
2)solaires@fm365.com,cmh620721
网站名称及网址 | etang.com
注册信息 | 1)chen_minghua99@sohu.com, cmh620721, pop.etang.com, smtp.etang.com
2)solaires,cmh620721
网站名称及网址 | 263.net
注册信息 | 1)solaire, 620721, 263.net, smtp.263.net
网站名称及网址 | usa.com
注册信息 | solaires@usa.com, cmh620721
网站名称及网址 | mail.com
注册信息 | solaires@mail.com, cmh620721
网站名称及网址 | unicum.de
注册信息 | solaires@unicum.de, cmh620721
网站名称及网址 | msn.com
注册信息 | solaires@msn.com, cmh620721
网站名称及网址 | lycos.de
注册信息 | solaires@lycos.de, cmh620721
邮件列表
网站名称及网址 | Bodachina.com
注册信息 | cmhboda,cmhbodaemail,620721
邮件清单 | cmhbodaemail,620721, softhousing,softhousing
网站名称及网址 | http://www.exp.com.cn/
注册信息

注册名：solaires, 密码：cmh620721, solaires@hotmail.com

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名称： solaires-solar@exp.com.cn
描述： information about solar industry and technologies
类型： 公共的
订阅方式： 任何人都可以加入
发送方式： 经你批准后才能发送
主页地址： http://www.solaires.com
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发行周期: once two week
允许停发时间: 30
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名称： solaires-wind@exp.com.cn
描述： News and technologies about wind power
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注册信息 | 1)solaires, cmh620721,solaires@hotmail.com, (Password: 7545093,) RenewablesChina
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2)solaires,cmh620721,solaires@sohu.com, RenewablesChina

<!-- Begin ListPower Member Join Box -->
<form target=_top action="http://www.listpower.com/cgi-bin/lp-memjoin.cgi" method="POST">
<input type="hidden" name="lid" value="377035">
<table border=0 bgcolor=#000066><tr><td>
<table border=0 bgcolor=white>
<tr><th bgcolor=DarkBlue><font color=white face=Arial size=2>
SUBSCRIBE TO MY MAILING LIST</font></th></tr>
<tr><td><blockquote><font face=Arial size=2><table border=0><tr><td>
<table border=0>
<tr><td><b><font color=black>Name</font></b></td><td><input type=text name="sname" size=10
maxlength=120></td></tr>
<tr><td><b><font color=black>Email</font></b></td><td><input type=text name="semail" size=10
maxlength=100></td></tr></table>
</td><td><input type=image src="http://www.listpower.com/images/join/lp_join.gif" border=0>
</td></tr></table>
<font size=-2 color=black>Powered by <a href="http://www.listpower.com/list.owners/376430/" target=_top>ListPower</a><br>
<a href="http://www.listpower.com/list.owners/376430/" target=_top><b>Webmasters</b></a>! Start your own email lists and make money!
</td></tr></table></td></tr></table>
</form>
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网站名称及网址 | http://www.messagebot.com/
注册信息 | cmh,RenewablesChina,solaires@hotmail.com, cmh620721
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<FORM ACTION="http://MessageBot.com/cgi-bin/list/add.cgi">
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网站名称及网址 | http://www.pread.net
注册信息 | solaires@hotmail.com, cmhsolar,RenewablesChina
邮件清单 <input type="hidden" name="ListCode" value="325">
<input type="hidden" name="DelListCodes" value="325">
<table>
<tr>
<td colspan="1" valign="top" height="14">
<div align="left" ><font size="2">请输入您的EMail地址：</font></div>
</td>
</tr>
<tr>
<td height="31"><font size="2">
<input type="text" name="MailName" size="10" maxlength="20" style="height:15pt">
@
<input type="text" name="MailHost" size="15" maxlength="50" style="height:15pt">
</font></td>
</tr>
<tr>
<td height="31"><font size="2"> </font>
<input type="button" name="Submit" value=" 加入 " style="font-size:9pt"
onClick="javascript:return CheckInput(document.ListForm, 1);">
<input type="button" name="Submit2" value=" 退订 " style="font-size:9pt"
onClick="javascript:return CheckInput(document.ListForm, 0);">
</td>
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</table>
</form>
</body>
</html>
<script Language=Javascript>
<!--
function CheckInput(form, func)
{
var str;
if(emailcheck(form.MailName.value+'@'+form.MailHost.value) == false)
{
form.MailName.select();
return false;
}

if(func == 1)
str = 'http://www.pread.net/joinlist.asp?Flag=1&MailName='+form.MailName.value
+'&MailHost='+form.MailHost.value+'&ListCode='+form.ListCode.value;
else
str = 'http://www.pread.net/leavelist.asp?Flag=1&MailName='+form.MailName.value+
'&MailHost='+form.MailHost.value+'&DelListCodes='+form.DelListCodes.value;

window.open(str);
return true;

}

function emailcheck (emailStr) {
/* The following pattern is used to check if the entered e-mail address
fits the user@domain format. It also is used to separate the username
from the domain. */
var emailPat=/^(.+)@(.+)$/

/* The following string represents the pattern for matching all special
characters. We don't want to allow special characters in the address.
These characters include ( ) < > @ , ; : \ " . [ ] */
var specialChars="\\(\\)<>@,;:\\\\\\\"\\.\\[\\]"

/* The following string represents the range of characters allowed in a
username or domainname. It really states which chars aren't allowed. */
var validChars="\[^\\s" + specialChars + "\]"

/* The following pattern applies if the "user" is a quoted string (in
which case, there are no rules about which characters are allowed
and which aren't; anything goes). E.g. "jiminy cricket"@disney.com
is a legal e-mail address. */
var quotedUser="(\"[^\"]*\")"

/* The following pattern applies for domains that are IP addresses,
rather than symbolic names. E.g. joe@[123.124.233.4] is a legal
e-mail address. NOTE: The square brackets are required. */
var ipDomainPat=/^\[(\d{1,3})\.(\d{1,3})\.(\d{1,3})\.(\d{1,3})\]$/

/* The following string represents an atom (basically a series of
non-special characters.) */
var atom=validChars + '+'

/* The following string represents one word in the typical username.
For example, in john.doe@somewhere.com, john and doe are words.
Basically, a word is either an atom or quoted string. */
var word="(" + atom + "|" + quotedUser + ")"
// The following pattern describes the structure of the user
var userPat=new RegExp("^" + word + "(\\." + word + ")*$")

/* The following pattern describes the structure of a normal symbolic
domain, as opposed to ipDomainPat, shown above. */
var domainPat=new RegExp("^" + atom + "(\\." + atom +")*$")

/* Finally, let's start trying to figure out if the supplied address is
valid. */

/* Begin with the coarse pattern to simply break up user@domain into
different pieces that are easy to analyze. */
var matchArray=emailStr.match(emailPat)
if (matchArray==null) {
/* Too many/few @'s or something; basically, this address doesn't
even fit the general mould of a valid e-mail address. */
alert("抱歉，您的email地址似乎不正确 (请检查 @ and .)")
return false
}

var user=matchArray[1]
var domain=matchArray[2]

// See if "user" is valid
if (user.match(userPat)==null) {
// user is not valid
alert("抱歉，您的email地址用户名不正确.")
return false
}

/* if the e-mail address is at an IP address (as opposed to a symbolic
host name) make sure the IP address is valid. */
var IPArray=domain.match(ipDomainPat)
if (IPArray!=null) {
// this is an IP address
for (var i=1;i<=4;i++) {
if (IPArray[i]>255) {
alert("抱歉，您的email地址IP地址不正确.")
return false
}
}
return true
}

// Domain is symbolic name
var domainArray=domain.match(domainPat)
if (domainArray==null) {
alert("抱歉，您的email地址域名不正确.")
return false
}

/* domain name seems valid, but now make sure that it ends in a
three-letter word (like com, edu, gov) or a two-letter word,
representing country (uk, nl), and that there's a hostname preceding
the domain or country. */

/* Now we need to break up the domain to get a count of how many atoms
it consists of. */
var atomPat=new RegExp(atom,"g")
var domArr=domain.match(atomPat)
var len=domArr.length
if (domArr[domArr.length-1].length<2 ||
domArr[domArr.length-1].length>3) {
// the address must end in a two letter or three letter word.
alert("抱歉，您的email地址缺少最后三位顶级域名或最后两位国家代码.")
return false
}

// Make sure there's a host name preceding the domain.
if (len<2) {
var errStr="抱歉，您的email地址缺少主机名."
alert(errStr)
return false
}

// If we've gotten this far, everything's valid!
return true;
}
-->
</script>
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能源与电力网站-中国
太阳能相关网站 主要的网站
网站名称及网址 |  | http://www.newenergy.org.cn
 | 注册信息 | 本网络是在国家科技部、国家经贸委、中国科学院共同指导下、由广州能源研究所建设的新能源和可再生能源领域内的综合性信息网络。
网站名称及网址 |  | http://www.chinasolar.net/ - 中国太阳能 - 太阳能技术、推广、应用、企业介绍、最新动态
 | 注册信息 |
网站名称及网址 |  | http://www.cn-solar.com
 | 注册信息 |
网站名称及网址 |  | 福州亚文能源科研所[http://www.yawen-power.com/] 主要从事新能源生产技术开发，并研究能源（柴油）降低污染问题。
 | 注册信息 |
网站名称及网址 |  | 中国能源市场[http://www.energymarket.com.cn/] 周刊，每周一出版，提供煤炭、焦炭、原油、成品油、燃料油、电力、节能与新能源等能源产品的最新市场行情和价格信息。
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
其他网站
网站名称及网址 |  | http://setc-gef.newenergy.org.cn
 | 注册信息 |
网站名称及网址 |  | http://www.CREIA.net
 | 注册信息 |
网站名称及网址 |  | http://www.ccre.com.cn
 | 注册信息 |
网站名称及网址 |  | http://www.crein.org.cn 中国可再生能源网
 | 注册信息 | cmhcrein,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.coolsolar.com
 | 注册信息 |
网站名称及网址 |  | http://www.efchina.org/ch/index.cfm, http://www.ef.org/
 | 注册信息 |
电力网站
网站名称及网址 |  | http://www.chinapoweronline.com,http://www.vertinfo.com/poweronline/index.htm
 | 注册信息 |
网站名称及网址 |  | http://www.cepn.sp.com.cn 中国电力新闻网
 | 注册信息 |
网站名称及网址 |  | http://www.pps.com.cn/电力产品搜索网
 | 注册信息 |
网站名称及网址 |  | http://www.power66.com
 | 注册信息 | cmhpower,cmh620721, solaires@sohu.com
 |  | 注册复杂，需要正式手续
网站名称及网址 |  | http://www.cec.org.cn
 | 注册信息 | cmhcec,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.ccspc.com.cn
 | 注册信息 | cmhccspc,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.powerproduct.com
 | 注册信息 | cmhpower,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.chinadian.net
 | 注册信息 | cmh,620721, solaires@sohu.com
网站名称及网址 |  | http://www.powerec.com.cn
 | 注册信息 | cmhpower,620721, solaires@sohu.com
网站名称及网址 |  | http://www.sinoepower.com
 | 注册信息 | cmhsino,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.chinapower.com.cn
 | 注册信息 | cmhchinapower,cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.nicepower.com
 | 注册信息 | cmh620721, solaires@sohu.com
网站名称及网址 |  | http://www.energy-china.com
 | 注册信息 |
网站名称及网址 |  | http://www.sdlinfo.com/
 | 注册信息 |
网站名称及网址 |  | http://www.i-power.com.cn
 | 注册信息 |
网站名称及网址 |  | http://www.cep2000.com
 | 注册信息 |
网站名称及网址 |  | http://www.epunn.com.cn/ 电力联报网
 | 注册信息 |
网站名称及网址 |  | http://www.sp.com.cn
 | 注册信息 |
网站名称及网址 |  | http://www.chinaer.org/中国电力可靠性
 | 注册信息 |
网站名称及网址 |  | http://www.dls.org.cn/中国电力标准化
 | 注册信息 |
网站名称及网址 |  | http://www.cpsi.com.cn/中国供电信息网
 | 注册信息 |
网站名称及网址 |  | http://www.cseht.com
 | 注册信息 |
网站名称及网址 |  | http://www.china5e.com中国能源网
 | 注册信息 |
网站名称及网址 |  | http://www.power-show.com/网上电力展
 | 注册信息 |
网站名称及网址 |  | http://cpi.topcool.net
 | 注册信息 |
网站名称及网址 |  | http://autoage.home.chinaren.com/电力系统自动化时代
 | 注册信息 |
网站名称及网址 |  | http://www.asianet-energysaving.com/亚太节电网
 | 注册信息 |
网站名称及网址 |  | http://www.electric-china.com
 | 注册信息 |
网站名称及网址 |  | http://www.cpeinet.com.cn
 | 注册信息 |
网站名称及网址 |  | http://www.cept.com.cn, http://www.cept.net/ 中国电力技术网.
 | 注册信息 |
网站名称及网址 |  | http://www.depwell.com
 | 注册信息 |
网站名称及网址 |  | http://www.dldj.org
 | 注册信息 |
网站名称及网址 |  | http://www.ceppic.com/电力自动化产品信息
 | 注册信息 |
网站名称及网址 |  | http://www.chinaej.com/
 | 注册信息 |
网站名称及网址 |  | http://www.china-heating.org.cn/
 | 注册信息 |
网站名称及网址 |  | http://www.diesel-china.net/
 | 注册信息 |
网站名称及网址 |  | http://www.cepp.com.cn/中国电力出版社
 | 注册信息 |
网站名称及网址 |  | http://www.chinaboiler.com.cn/
 | 注册信息 |
网站名称及网址 |  | http://limin.www3.cn4e.com/ 新在线
 | 注册信息 |
网站名称及网址 |  | http://www.cepee.com/
 | 注册信息 |
网站名称及网址 |  | http://www.lodestar.com.cn/北极星电力电信网站
 | 注册信息 |
网站名称及网址 |  | http://www.hypowertec.com/华英电力科技网
 | 注册信息 |
网站名称及网址 |  | http://www.5e.net.cn/
 | 注册信息 |
网站名称及网址 |  | http://www.yi-tao.com.cn/
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
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网站名称及网址 |  |
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网站名称及网址 |  |
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网站名称及网址 |  |
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网站名称及网址 |  |
 | 注册信息 |
环境保护网站
网站名称及网址 |  | http://www.secidc.org.cn国家经贸委节能信息传播中心
 | 注册信息 |
网站名称及网址 |  | http://www.enviroinfo.org.cn , http://www.ied.ac.cn/ “天地人和” 环境与发展研究所
 | 注册信息 |
网站名称及网址 |  | http://greenpower.grchina.net
 | 注册信息 |
网站名称及网址 |  | http://www.grchina.net
 | 注册信息 | cmhgrchina,cmh620721, solaires@sohu.com
网站名称及网址 |  | http;//www.ep.net.cn
 | 注册信息 | cmhep,rb5n6ajg, solaires@sohu.com
网站名称及网址 |  | http://www.zhb.gov.cn/国家环保总局信息中心
 | 注册信息 |
网站名称及网址 |  | https://www.chinah2o.com
 | 注册信息 | solaires, solaires@hotmail.com,Your password is Xb7OPyyqhQ
网站名称及网址 |  | http://www.shp.com.cn
 | 注册信息 | cmhshp,cmh620721, solaires@sohu.com
风力发电相关网站
网站名称及网址 |  | 全国风力发电信息中心 - http://wpic.topcool.net/index.html
 | 注册信息 |
网站名称及网址 |  | 中国新能源网 - http://www.newenergy.org.cn/
 | 注册信息 |
网站名称及网址 |  | 新风网 - http://www.xjwind.com/
 | 注册信息 |
网站名称及网址 |  | 汕头电力 http://step.stinfo.net/index2/fn.html
 | 注册信息 |
网站名称及网址 |  | 清洁能源网- http://cenergy.greendo.com.cn/ - 地热能利用,海洋能,风能
 | 注册信息 |
网站名称及网址 |  | 中国可再生能源网 - http://www.crein.org.cn/
 | 注册信息 |


能源与电力网站-国际

网站注册信息
国际
太阳能行业网站
网站名称及网址 | http://www.solid.de/ solarenergie informations- und demonstrations zentrum
注册信息

网站名称及网址 | The Iowa Energy Center http://www.energy.iastate.edu/
注册信息

网站名称及网址 | NASA Scientific and Technical Information Program http://gopher.sti.nasa.gov/
注册信息

网站名称及网址 | The Energy Outlet http://www.energyoutlet.com/ 这是个有关电能保存的资源站点
注册信息

网站名称及网址

The solar Energy Network http://www.solarenergy.net/
注册信息

网站名称及网址

Global Environment Facility http://www.gefweb.org/
注册信息

网站名称及网址 | World Energy Council http://www.worldenergy.org/wec-geis/
注册信息

网站名称及网址

World Bank Rural and Renewable Energy http://www.worldbank.org/html/fpd/energy/ruralenergy.htm
注册信息

网站名称及网址

PMA Online Energy Information Resources http://www.powermarketers.com/info-lnk.htm
注册信息

网站名称及网址

Solar Energy International http://www.solarenergy.org/
太阳能，风能，和水能的实际应用。出售有关可再生能源和可行的建筑技术的书，录象带和软件。
注册信息

网站名称及网址 Solar Energy http://solstice.crest.org/renewables/re-kiosk/solar/index.shtml
It includes introduction to solar physics,solar thermal energy and photovotics.
注册信息

网站名称及网址 Tom Elliot's Alternative Energy Information Center http://www.wagonmaker.com/
an online tour of a PV powered home, plus extensive information on solar energy and links to other sites.
注册信息

网站名称及网址 Solar In The Sunshine State http://www.flasolar.com/
information on proven, currently available technologies, installation techniques, and the economics of installing solar pool heaters, solar water heaters, and solar electric (PhotoVoltaics).
注册信息

网站名称及网址 | http://www.solarbuzz.com/
注册信息

网站名称及网址 | http://www.solar-news.de
注册信息

网站名称及网址 | http://www.ise.fhg.de
注册信息

网站名称及网址 | http://www.iea.org
注册信息

网站名称及网址

Million Solar Roofs Initiative
President Clinton's Initiative operated by DOE

注册信息

网站名称及网址

Solar Energy Industries Association
Industry Information on Solar Systems & Directories of Manufacturers
注册信息

网站名称及网址 | http://www.caddet-re.org/
注册信息

网站名称及网址 | http://www.cordis.lu
注册信息

网上黄页
网站名称及网址 | http://www.top50-solar.de
注册信息

cmhpower,cmh620721, solaires@sohu.com
网站名称及网址 Solar Energy applications http://www.ecn.nl/main.html
网站上有太阳能活动(单元和模块，系统技术)，太阳能应用设备，还有一些有关太阳能的文章。
注册信息

网站名称及网址

http://www.energyweb.net
注册信息

solaires, solaires@hotmail.com, cmh620721

Rates for your Company or Organisation to be listed in EnergyWeb's International Supply Source Directory & Search Engines

EnergyWeb.net's International Supply Source Directory is the most comprehensive directory of Energy Sector Companies, Organisations, Products and Services on the Internet.

Not only is it an ideal place to advertise and find new international sales leads, members have access to a wide range of value added features and services, including the ability to post Press Releases directly on the EnergyWeb Portal and receive Sales and Technical information requests.

You cannot get better value for money on the Internet or from traditional media - EnergyWeb.net receives around 25,000 hits every day from over 90 countries. Employees from most of the world's largest Energy Sector Operators search EnergyWeb's International Supply Source Directory at least once per week.

Select which of our services best meet you needs:

Free Listing Silver Listing Gold Listing

FREE US$ 100 US$ 500

Cost per additional energy sector FREE US$ 25 US$ 50
网站名称及网址 | http://www.eurorosolar.org
注册信息

网站名称及网址

http://www.pvportal.com/ $ 250/year
注册信息

网站名称及网址 | http://www.apctt.org/
注册信息

网站名称及网址 | http://www.eco-web.com/The Global Directory for Environmental Technology - register free
注册信息

网站名称及网址

http://www.photon.de/ DM120/a+DM40/additional entry(email etc)
注册信息

网站名称及网址 | http://www.agores.org
注册信息

网站名称及网址 | http://www.solarportal24.de
注册信息

网站名称及网址 | http://www.jxj.com
注册信息

网站名称及网址 | PV Power Resource Site http://www.pvpower.com/ 太阳能光伏资源站。
注册信息

网站名称及网址 | http://www.lior-int.com
注册信息

网站名称及网址

Solarinfo: http://www.solarinfo.de
注册信息

ID: 36077115, PIN: 32169190, solaires@sohu.com
网站名称及网址 | http://www.solaraccess.com/
注册信息

网站名称及网址 | http://www.energielinks.de
注册信息

网站名称及网址

BOXER - Infodienst: Regenerative Energie http://www.boxer99.de/ DM 60/year
注册信息

Eintrag in das Firmenverzeichnis
- f黵 nur 60,- DM pro Jahr -

网站名称及网址 | Windmesse: windmesse
注册信息

网站名称及网址 | Energy Technology Data Exchange http://www.etde.org/ 能源技术数据交换中心。收集和交流能源方面的研究和技术信息。
注册信息

网站名称及网址 | The IEA GREENTIE Directory http://www.greentie.org/
注册信息

Registration in the GREENTIE Directory is free of charge for all organisations, companies, consultants, etc. provided they:

have expertise in one (or more) greenhouse gas mitigating technologies
offer this expertise internationally
are located in a GREENTIE participating or affiliated country

网站名称及网址

Environmental Organization WebDirectory http://www.webdirectory.com/

注册信息

网站名称及网址 | http://energy.sourceguides.com/index.shtml
注册信息

Free Text-Only Business Listing
We provide a free text-only business listing for all renewable energy related businesses. The free listing includes your business name, product or service types, business type, address and phone. Please use our business listing submission form to submit your business information. If your browser does not support forms, you may email your business information to energy@sourceguides.com.
--------------------------------------------------------------

Linked Listing
We can refer hundreds of new customers to your business web site and multiple sales leads to your business email address every month by including a link to your business web site and email address in your business listing. Our Linked Listing service is the most cost-effective method for reaching new customers and increasing your sales.

Annual Fee: $120

--------------------------------------------------------------

Descriptive Listing
Add a description of your products and services to your business listing to highlight your business and receive more targeted sales leads.

Annual Fee: $120

--------------------------------------------------------------

Logo Listing
Get preferential listing placement and attract thousands of new customers by adding a full-color logo to your business listing. Your logo can be a graphic logo, picture of your business, or a picture of one of your products. To add a logo to your listing please email your logo file to energy@sourceguides.com or mail your printed logo to: Momentum Technologies LLC, 650 Castro Street, Suite 120/281, Mountain View, CA 94041.

Annual Fee: $300

--------------------------------------------------------------

Banner Advertisements
We can place a banner advertisement for your business at the top of any page in the Source for Renewable Energy. This allows you to target customers looking for particular products, services, or businesses in a specific region. For maximum effectiveness we allow only one advertisement per page. Call for details (408) 241-4209 or email us at energy@sourceguides.com.

Monthly Fee: starting at $50 per month

网站名称及网址 | http://www.solar-welt.de
注册信息

网站名称及网址 | http://www.energie-server.de/
注册信息

100 DM/y
网站名称及网址 | Alliance to Save energy http://www.ase.org/
注册信息

网站名称及网址 | http://www.solarserver.de
注册信息

网站名称及网址

Clean Energy http://www.cleanenergy.de/ 清洁能源
注册信息

You can register your company (organization, institute) at CleanEnergy for free by filling out the following form and subsequent submitting. Your data will be accepted at the next Update of CleanEnergy and shown in the alphabetical directory.

Extended companies entry
For better presentention in the CleanEnergy directory we offer for registered companies (organizations, institutes) an extended entry. The extended entry includes an extended companies description, the companies logo, and a classification according to countries, products, and business types. Also you can deposit your homepage and product pages to our server, with links to them from the relevant pages.

Offer Price
Classification according to countries, products, and sphere of activity including an extending companies description and logo. 80 USD / year
Your own homepage 100 USD / year
Layouting of a homepage according to your pattern 80 USD
Layouting of a homepage without a pattern 165 USD
Your own productpage 100 USD / year
Layouting of a productpage according to your pattern 80 USD
Participation in Online-Shopping It isn't indroduced yet

网站名称及网址 | http://wire0.ises.org/wire/wire.nsf
注册信息 | cmhiseswire,cmh620721, solaires@sohu.com
password: yle646
网站名称及网址 | http://emsolar.ee.tu-berlin.de/adress/Worldwide address list of organisations and research institutes, architects, enterprises, etc.
注册信息

网站名称及网址 | http://www.crest.org/gem.html
注册信息

网上商店
网站名称及网址 | http://www.huttonsolar.com/
注册信息

网站名称及网址 | http://www.greenpagesstore.com/ $50/year
注册信息

网站名称及网址 | http://www.ecomall.com/
注册信息

网站名称及网址 | http://www.cetsolar.com/
注册信息

网站名称及网址 | http://www.bigfrogmountain.com
注册信息

网站名称及网址

altenergystore: http://www.altenergystore.com/ The on-line store for Solar and Wind Energy Goods Offering Solar Panels, Windmills, Inverters, Batteries, Refrigerators, Charge Controllers, Panel Mounts, Meters, and much more...
注册信息

网站名称及网址 | http://www.altestore.com/ PV, Wind, SolarThermal
注册信息

网站名称及网址 | http://www.aerosunenergy.com/ PV, Wind
注册信息

网站名称及网址

http://www.solarkaufhaus.de
注册信息

网站名称及网址 | RealGoods: http://www.realgoods.com
注册信息

网站名称及网址 | http://www.greenmarketplace.com
注册信息

网站名称及网址 | http://www.majorpower.com
注册信息

网站名称及网址

Mr. Solar http://www.mrsolar.com/
注册信息

网站名称及网址 | http://www.solarshop.net
注册信息

网站名称及网址 | http://www.solarsense.com
注册信息

网站名称及网址 | http://www.solarwebb.com
注册信息

网站名称及网址 | http://www.solar-electric.com/
注册信息

网站名称及网址

http://www.nooutage.com/
注册信息

网站名称及网址 | http://www.windsun.com/
注册信息

网站名称及网址 | http://www.gotsolar.com/
注册信息

网站名称及网址 | SOLARONSALE.COM: http://www.solaronsale.com/
注册信息

网站名称及网址

Solardepot.com http://www.solardepot.com/
wholesale distributor of solectrogen solar electric generators and related solar thermal systems and products.
注册信息

网站名称及网址 | http://www.buyenergyhere.com
注册信息 | solaires,cmh620721, solaires@sohu.com
acc/code: solaires, company ID: 429
网站名称及网址 | http://www.solarsales.oz.nf/
注册信息

网站名称及网址 | http://www.solarenergy.com/
注册信息

网站名称及网址 | http://buy-solar.com/
注册信息

网站名称及网址 | http://www.jademountain.com
注册信息

Over 4000 Alternative Energy products... Worldwide
网站名称及网址 | http://www.aaasolar.com/
注册信息

网站名称及网址 | http://www.ajlsolarelectric.com/
注册信息

网站名称及网址 | http://www.solarelectric.com
注册信息

网站名称及网址 | http://www.solarenergy-alt.com
注册信息

网站名称及网址 | http://www.pvcell.com
注册信息

网站名称及网址 | http://www.aapspower.com
注册信息

网站名称及网址 | http://www.solarroofs.com
注册信息

网站名称及网址
注册信息

网站名称及网址
注册信息

网站名称及网址
注册信息

网站名称及网址
注册信息

网站名称及网址
注册信息

软件信息网站
网站名称及网址

Internationales Wirtschaftsforum Regenerative Energien http://www.uni-muenster.de/Energie/solar/erricht/edv-so.html

WWW-Server zu Bauphysik & Solarenergie
注册信息

网站名称及网址

Renewable Resource Data Center http://rredc.nrel.gov/

注册信息

网站名称及网址

Energy Efficiency and Renewable Energy Network (EREN) of the U.S. Department of Energy: http://www.eren.doe.gov/buildings/tools_directory/
注册信息

网站名称及网址 | http://www.solarserver.de
注册信息

网站名称及网址

http://www.mauisolarsoftware.com
注册信息

网站名称及网址 | World-wide Information System for Renewable Energy (WIRE) http://wire0.ises.org/wire/Publications/resoft.nsf?OpenDatabase
注册信息

网站名称及网址 | http://www.energie-online.de
注册信息

网站名称及网址 | http://www.energiesimulation.de
注册信息

网站名称及网址 | http://www.physik.uni-oldenburg.de/ehf/insel/index_d.html
注册信息

网站名称及网址

http://buran.fb10.tu-berlin.de/Energietechnik/EVT_KT
注册信息

网站名称及网址 | http://www.solarenergie.com
注册信息

网站名称及网址
注册信息

风力发电相关网站
网站名称及网址 Eole
http://www.eole.org/
注册信息

网站名称及网址

Wind Power
http://solstice.crest.org/renewables/re-kiosk/wind/index.shtml
网站包括对风能的综合观点、风能理论、风能应用、实例研究、环境、风能历史和经济。

注册信息

网站名称及网址 National Wind Technology Center
http://nwtc.nrel.gov/
美国国家风能技术中心，提供有关风能技术的资料，包括网站导游，录象，可下载的设计代码，对风能的测试和文献表单。
注册信息

网站名称及网址

Windenergy in the Netherlands http://home.wxs.nl/~windsh
荷兰网站，有关荷兰风能的信息，新闻，和统计资料。

注册信息

网站名称及网址

Danish Windpower http://www.windpower.dk/
丹麦风力发电。网站有风能资源、风力涡轮技术、经济和风能环境方面的旅游指南的资料。

注册信息

网站名称及网址

windkraft

Utility Wind Interest Group http://www.uwig.org/
UWIG 是一个促进风能效益和提供信息及支援与风能有关的效用的非赢利组织。

注册信息

网站名称及网址 | Windpower Online: windpoweronline
注册信息


搜索引擎
网站名称及网址 |  | sohu.com
 | 注册信息 | 1)姓名：陈明华, solaires@21cn.com 2)softhousing@21cn.com
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网站名称及网址 |  | sina.com.cn
 | 注册信息 | 1) name:陈明华, solaires@21cn.com 2)contact person: henry chen/chen minghua, cmh@softhousing.com 3) cmh, sales@softhousing.com 4)free mail: cmhclub, 620721, 14478227, 971197244 5)cmh, chen_minghua68@hotmail.com 6）chen minghua, solaires@sohu.com 新浪首页＞搜索首页＞计算机与互联网＞通讯与网络 新浪首页＞搜索首页＞计算机与互联网＞多媒体 新浪首页＞搜索首页＞计算机与互联网＞网上教程＞网页制作 新浪首页＞搜索首页＞商业经济＞公司＞基础设施＞能源
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 | 注册信息 | 1)chen_minghua68@hotmail.com 2)solaires@sohu.com,站点ID： 1001993552
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网站名称及网址 | x | 263.net
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网站名称及网址 |  | infoseek.com,go.com
 | 注册信息 |
网站名称及网址 |  | web.de
 | 注册信息 | solaires@sohu.com
 |  | solaires - Ihrer Internet-Zugan nach China Solaires ist eine Internet-basiert Firma in Hangzhou, schoene Stadt Chinas. Wir bieten Webdesign ...
网站名称及网址 |  | altavista.com
 | 注册信息 |


婚嫁交友
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 | 注册信息 | chen_minghua, chen_minghua@yahoo.com, 46245


虚拟主机，免费空间
网站名称及网址

net.cn
注册信息

(old): cmh2001, 620721, uj80e1, e5s8y2x8, http://uj80e1.chinaw3.com

(new): cmh2001, cmh620721; ftp: uj80e1, cmh620721, http://www.solaires.com:881

网站名称及网址

webappcabaret.com
注册信息
  • solaires@sohu.com,
  • database driver: org.gjt.mm.mysql.Drivers,
  • url: jdbc:mysql://mysql.webappcabaret.com/
  • solaires?user=solaires&password=6vorPJ,
  • SMTP access: mail.webappcabaret.com
域名交易
易域网 | cmh, 620721 | http://www.eachnic.com
中易网 | http://www.sale-domainname.com
域名专家网 | http://www.260e.com
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商易域名交易网 | http://www.domainb2s.com
商务域名拍卖 | http://maidedao.at.china.com
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全球中文域名注册中心 | http://www.yesdo.com
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爱科图普网络 | http://www.ectob.com
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软件，应用服务与学习网站

网站注册信息
软件，应用服务与学习网站
网站名称及网址

Javasoft.com
注册信息 | cmh2001, cmh620721, solaires@sohu.com
网站名称及网址

borland.com
注册信息

cmh, solaires@21cn.com, JBuilder Foundation code:

serial: xa22-?dma6-33stk, key: 444-5pu
网站名称及网址

bea.com
注册信息 | softhousing@21cn, 620721

weblogic:

admin domain name: solaires; server name: WebLogic

listen port: 7001, ssl listen port: 7002

user name: system, password: cmh620721
网站名称及网址

silverstream.com
注册信息

AA0825 0000 0000 2D45 5D05 985160

AA0825 0000 0000 2D45 5D79 915120
网站名称及网址

allaires.com
注册信息 | cmhallaires, 620721
网站名称及网址

ihtml.com
注册信息 | cmhihtml, 620721, cmh@solaires.com
网站名称及网址

cult3d.com
注册信息 | chen_minghua, F1008 102F 3A009
网站名称及网址

oracle.com
注册信息

global name: solaires, SID: solaires, SYS-> change_on_install, SYSTEM->manager, INTERNAL->oracle

administrator: system, password: oem_temp(old), cmh620721

user: cmh1, pass: 620721

service: cmh1:1521:solaires
JAVA
网站名称及网址

jspchina.com
注册信息

justpi,solaires@sohu.com
网站名称及网址

devunion.org
注册信息

cmhdevunion,cmh620721solaires@sohu.com
网站名称及网址

jsp001.org
注册信息

cmh001,cmh620721solaires@sohu.com
网站名称及网址

http://www.ChinaJavaWorld.com, jdeveloper.6to23.com
注册信息

cmhjdev,cmh620721solaires@sohu.com
网站名称及网址

javaxforum.com
注册信息

cmhjavaxforum,cmh620721solaires@sohu.com
网站名称及网址

apusic.com
注册信息

apulove,cmh620721solaires@sohu.com
虚拟主机，免费空间
网站名称及网址

net.cn
注册信息

(old): cmh2001, 620721, uj80e1, e5s8y2x8, http://uj80e1.chinaw3.com

(new): cmh2001, cmh620721; ftp: uj80e1, cmh620721, http://www.solaires.com:881

网站名称及网址

webappcabaret.com
注册信息
  • solaires@sohu.com,
  • database driver: org.gjt.mm.mysql.Drivers,
  • url: jdbc:mysql://mysql.webappcabaret.com/solaires?user=solaires&password=6vorPJ,
  • SMTP access: mail.webappcabaret.com
商务应用网站
网站名称及网址 | Bodachina.com
注册信息 | cmhboda,cmhbodaemail,620721
邮件清单 | cmhbodaemail,620721, softhousing,softhousing
网站名称及网址

上海数字认证中心SHECA:
注册信息 | 认证过的电子邮件地址:chen_minghua@263.net 密码:99551710
网站名称及网址 | sheca.com
注册信息

cmh@softhousing.com, register password: 68982866,login password:620721

sales@softhousing.com, register password: 27479618,login password:620721
网站名称及网址 | hitrust.com
for digital ids for my emails 注册信息

first name: minghua, last name: chen, email: cmh@softhousing.com, password: ktwyluh

personal identity no: 814755442;

export digital id file: password: 620721,name: cmh@softhousing.com

first name: minghua, last name: chen, email: sales@softhousing.com, password: xlgwcde

personal identity no: 811755743

export digital id file: password: 620721,name: sales@softhousing.com
网站名称及网址 | east.net.cn
注册信息

info2.east.net.cn, login: softss, pasword: ss1199
网站名称及网址

万维应用服务网(www.5v.com)注册:
注册信息 | chenminghua,620721
网站名称及网址 | 中国新网chinadns.com
注册信息 | cmhnet,620721
BBS
网站名称及网址

yesite.com
注册信息

1) solaires, solaires, cmh620721, solaires@sohu.com

2) cmhyesite, cmhyesite, cmh620721, solaires@sohu.com

3) cmhyesite2001, cmhyesite2001, cmh620721, solaires@sohu.com
网站名称及网址

beseen.com
注册信息

acc/no: c58736, pass: 863Send,Planet: plutosolaires@sohu.com
网站名称及网址

http://sitelevel.whatuseek.com/join.cgi
注册信息

pass: azwu-zi, solaires@sohu.com
网站名称及网址

betbig.com
注册信息

solaires, cmh620721, code: 13918, solaires@sohu.com
网站名称及网址 | http://www.wenzhai.com/gb/
注册信息 | solaires,cmh62072,solaires@sohu.com
网站名称及网址 | http://www.elecity.net/guestbook/gbsign.html
注册信息 | solaires,cmh62072,solaires@sohu.com
网站名称及网址 | http://www.hesee.com/guestapply.htm
注册信息 | solaires,cmh62072,solaires@sohu.com
网站名称及网址 | http://www.guestbook.de
注册信息 | solaires,cmh62072,solaires@sohu.com
Your User-ID:538129-ming
Your password:cmh620721

网站名称及网址 | http://www.freeguestbooks.com/
注册信息 | solaires,cmh62072,solaires@sohu.com
银行与支付机构
网站名称及网址 | 招商银行一网通
注册信息 | 帐号: 密码: 304758,支付卡号:21 81 00 11 36
人力资源
网站名称及网址

jobchina.net:
注册信息 | chen_minghua, 620721
网站名称及网址

china-hr.com:
注册信息 | minghua, 620721; cmh, 620721
网站名称及网址

fescochina.com:
xxx | 注册信息 | cmh, 620721
网站名称及网址

asia-net.com:
注册信息 | softhousing@21cn.com
网站名称及网址

51job.com:
注册信息

注册会员：cmh51job, cmh620721
网站名称及网址

strongnet.com:
注册信息 | cmh, 620721
网站名称及网址 | monster.com
注册信息 | freiheit2001,620721, solaires@sohu.com
网站名称及网址 | jobs.com
注册信息

user name: softhousing@21cn.com, password:620721

网站名称及网址 | zjrc.com
注册信息 | cmh2001,620721
上网赚钱
网站名称及网址 | 1stBanner.com:
注册信息 | softhousing, 620721
网站名称及网址

Gotoworld.com:
注册信息

UserID: 1059411132

pass: lovedongfang
网站名称及网址

Cashlink.co.kr:
注册信息

login name: cls159h

logid: cmh123

password: 1234

refid: ioe-321
网站名称及网址

spedia.net:
注册信息

ref no: 1304766

pass: 1234

login name: cls159h
网站名称及网址

Bepaid.com:
注册信息

pwd: 620721

ID: 11019637
网站名称及网址

Desktopdollars.com:
注册信息

refid: ok-year2000@hanmail.net

email: softhousing@21cn.com

pwd: 620721
婚嫁交友
网站名称及网址 | www.i.com.cn
注册信息 | cmhihw,620721
网站名称及网址 | love.com.cn
注册信息 | cmhlove,620721,编号：120168639,密码：0
网站名称及网址 | sina.com.cn
注册信息

1)cmhsino,620721,madmanyou_cn

2)cmhclub_cn,620721
网站名称及网址 | http://www.germanfriendfinder.com
注册信息 | chen_minghua, chen_minghua@yahoo.com, 46245
域名交易
易域网 | cmh, 620721 | http://www.eachnic.com
中易网 | http://www.sale-domainname.com
域名专家网 | http://www.260e.com
域名交易网 | cmh, 620721 | http://www.namedealing.com
商易域名交易网 | http://www.domainb2s.com
商务域名拍卖 | http://maidedao.at.china.com
世纪中国网 | cmh,620721 | http://www.21sino.com
全球中文域名注册中心 | http://www.yesdo.com
环球域名交易网 | cmh,620721 | http://www.wwwiso.com
爱科图普网络 | http://www.ectob.com
易名网 | cmh,620721 | http://www.domainpricing.com


人力资源
网站名称及网址 |  | jobchina.net:
 | 注册信息 | chen_minghua, 620721
网站名称及网址 |  | china-hr.com:
 | 注册信息 | cmh, 620721
网站名称及网址 |  | fescochina.com:
xxx | 注册信息 | cmh, 620721
网站名称及网址 |  | asia-net.com:
 | 注册信息 | softhousing@21cn.com
网站名称及网址 |  | 51job.com:
 | 注册信息 | 注册会员：cmh51job, cmh620721
网站名称及网址 |  | strongnet.com:
 | 注册信息 | cmh, 620721
网站名称及网址 |  | monster.com
 | 注册信息 | freiheit2001,620721, solaires@sohu.com
网站名称及网址 |  | jobs.com
 | 注册信息 | user name: softhousing@21cn.com, password:620721
网站名称及网址 |  | zjrc.com
 | 注册信息 | cmh2001,620721
网站名称及网址 |  | http://www.asiadragons.com/china/employment/
 | 注册信息 |
网站名称及网址 |  | http://www.zhaodaola.com.cn/english/categories/careers_hr/index.html
 | 注册信息 |
网站名称及网址 |  | http://www.overseasjobs.com/
 | 注册信息 |
网站名称及网址 |  | http://www.recruitex.com/
 | 注册信息 |
网站名称及网址 |  | http://www.asia-links.com/asia-jobs
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |


网络营销

网站注册信息
网络营销
网站名称及网址 |  | http://www.wisecast.com/
 | 注册信息 |
网站名称及网址 |  | http://www.marketingbetter.com/
 | 注册信息 |
网站名称及网址 |  | http://www.enetmaker.net
 | 注册信息 |
网站名称及网址 |  | http://www.etop2000.com/
 | 注册信息 |
网站名称及网址 |  | http://www.chinaemarketing.com/
 | 注册信息 |
网站名称及网址 |  | http://www.webpromote.com.cn/
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |
网站名称及网址 |  |
 | 注册信息 |


银行与支付机构
网站名称及网址 |  | 招商银行一网通
 | 注册信息 | 帐号: 密码: 304758,支付卡号:21 81 00 11 36
上网赚钱
网站名称及网址 |  | 1stBanner.com:
 | 注册信息 | softhousing, 620721
网站名称及网址 |  | Gotoworld.com:
 | 注册信息 | UserID: 1059411132 pass: lovedongfang
网站名称及网址 |  | Cashlink.co.kr:
 | 注册信息 | login name: cls159h logid: cmh123 password: 1234 refid: ioe-321
网站名称及网址 |  | spedia.net:
 | 注册信息 | ref no: 1304766 pass: 1234 login name: cls159h
网站名称及网址 |  | Bepaid.com:
 | 注册信息 | pwd: 620721 ID: 11019637
网站名称及网址 |  | Desktopdollars.com:
 | 注册信息 | refid: ok-year2000@hanmail.net email: softhousing@21cn.com pwd: 620721


Network

LaneZZZ foundations p48.pdf
NoubirZZZ Fundamentals of Computer Networks p40.pdf
SinghZZZ Paper Name Internet Fundamentals p163.pdf
YangZZZ Fundamentals on Computer Networks and Wireless Networks p33.pdf
ZZZFundamentals of Web Technology p87.pdf


网站维护

http://www.net.cn

网站维护

FTP：管理员登录名：uj80e1,密码：新cmh620721，老：e5s8y2x8

FTP站点：solaires.com
主机域名：www.solaires.com
主机IP地址：210.192.102.31

看看安装程序都帮您做了什么?

--------------------------------------------------------------------------------
创建安装BBS的目录bbs，并在此目录下创建名为“bbsindex.html”的BBS主文件的data.txt的日志文件。
在你的cgi-bin目录下创建一个名为“wwwboard.pl”的CGI程序。
在BBS的目录bbs下创建一个名为“messages”的子目录，用于存放BBS上发表的信息。

建议你快把以上说明内容拷贝下来，以便今后灵活修改！

看看安装程序都帮您做了什么?

--------------------------------------------------------------------------------
创建你欲安装GuestBook的目录guestbook，并在此目录下创建名为“guestbook.html”的留言板文件。
在你的cgi-bin目录下创建一个名为“guestbook.pl”的CGI程序。

建议你快把以上说明内容拷贝下来，以便今后灵活修改！

创建你欲安装Feedback的目录feedback，并在此目录下创建名为“feedback.html”的反馈表文件。
在你的cgi-bin目录下创建一个名为“feedback.pl”的CGI程序。

建议你快把以上说明内容拷贝下来，以便今后灵活修改！
计数器
<tr>
<td colspan="3" height="18"> <div align="center"><font face="Geneva, Arial, Helvetica, san-serif"><img src="http://www.hichina.com/cgi-bin/Count.
cgi?ft=3&dd=A&df=solaires.com-1.dat" width="110" height="15"></font></div></td>
</tr>
面板维护：
http://www.solaires.com:881 （原）http://uj80e1.chinaw3.com
登录名：uj80e1,密码：新cmh620721，老：e5s8y2x8
用户信息与帐号管理

用户ID：cmh2001

您的数字ID: 10163724

密码：新：k2y5l3， 老2：620721；老1：cmh620721

请使用上面的数字ID和密码登录!

中国万网国际英文域名续费通知

--------------------------------------------------------------------------------

尊敬的中国万网客户：cmh2001
    您好！首先，感谢您选用中国万网的服务！

    您通过我公司注册的国际英文域名将要到期，为了不影响继续您使用域名，不影响到您的网站访问，请您于收到此信10日内向我公司办理域名续费事宜。

您的业务情况如下：
业务跟踪号 　 　 域名 　　 到期时间
200103070600010 solaires.com 2002-03-07

续费操作步骤如下：
    您可以直接进入 http://www.net.cn，请输入您在我公司注册的用户ID及密码 -> 在页面左部选择 “续租业务”, 并选择您要续费的业务，点击“提交”按钮 ->选择续费年限后点击“提交”按钮->系统提示后再点击“提交”按钮->根据系统提示付款即可完成续费手续。
如果您以上的操作不能正常进行或您要续费的业务不在“续租业务”内，请您将此续费业务传真到我公司续租部，我们会为您及时处理。

付费方式：
   银行电汇：

开户银行： 中信实业银行富华大厦支行
开户名称： 北京万网网络技术有限责任公司
帐号： 71103-1-01-823-000740-18
行号 624

    邮局汇款：

通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层
邮政编码： 100027
请写明您续费的域名或新的业务跟踪号

    直接付款：
公司地址： 北京市东城区朝阳门北大街8号富华大厦C座13层
（地铁东四十条站东南出口，港澳中心中心向南200米富华大厦）

    如果您是使用预付款续费或用招商银行一网通付费：
    可以直接将款项付入到您在我公司注册的ID号下的预付款内，并发传真给我们说明您的款项是付哪笔业务。

特别提示：
    （1） 为了及时准确地办理您的业务，请您汇款至我公司时在附言中注明续租业务，并将汇款凭证传真至010-65542354，请务必在传真中注明“续租”字样及您要续费的域名。
    （2） 如果您未能及时缴纳域名费用，贵公司的宝贵域名将会被internic（国际互联网络信息中心）视为自动放弃而删除该域名，在此情况下，我公司将无法为您提供任何帮助。如有特殊情况请您与我部门及时联系。
    （3） 如果您的联系方式有改变，请您登录我公司网站 www.net.com 录入您的用户名及密码，进入会员信息区，点击“改变会员信息”项，将您新的联系方式重新录入。这样可使我们保持联系，不至使您的域名丢失，并谢谢您的合作。
    再次感谢您对中国万网的支持与厚爱，并衷心地希望我公司能长久地为您提供服务！ 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　中国万网续租部
                                                                          2002-02-05

--------------------------------------------------------------------------------

=============================================================
全国免费电话： 800-810-8500
北京联系电话： (010) 65546191
公 司 传 真： 010-65542377/65542394
电 子 邮 件： renew@hichina.com
=============================================================

网站上显示的域名注册到期日-2002。3。7-与实际到期日-2002。3。14 -不符请更正。

2002.2.7.
尊敬的客户 陈明华 ：

您好！感谢您选择中国万网服务，并感谢您对我公司的信任和大力支持！

您在我公司续租申请的业务如下：

新业务跟踪号：200202070600038

域名：solaires.com 注册期限：12 个月 到期时间：2003-03-07 续费价格 100

请您将以上费用按以下付款方式至我公司：
----------
付款方式：
----------
1、银行电汇：
收款人名称： 北京万网网络技术有限责任公司
开户银行：中信实业银行富华大厦支行
帐 号： 7110310182300074018

2、邮局汇款：
收款人名称： 北京万网网络技术有限责任公司
收款人地址：北京市东城区朝阳门北大街8号富华大厦C座13层
邮政编码： 100027
附言中请注明续租业务及用户自助服务系统用户ID。

3、直接到我公司付费：
公司地址：北京市东城区朝阳门北大街8号富华大厦C座13层
（地铁东四十条站港澳中心方向出口向南200米）

4、预付款及一卡通付费：
您可以直接将款项付入您ID下的预付款，发传真给我们说明您的款项付哪笔业务并加盖公章
(个人用户请附身份证复印件)即可。
或者您可以直接进入 http://bips.hichina.com 点击“客户服务系统” 输入用户ID及密码
-〉在页面底部单选“续租业务”，并点击“查看业务清单”按钮 -〉选择续租项目，填写
相关信息-〉完成递交-〉用一卡通付款。

---------
特别提示：
---------
为使您的业务及时处理，请您在汇款之后务必进入
http://bips.hichina.com，输入您在我公司自助服务系统用户
ID: cmh2001 及密码后，点击“用户管理”中的“汇款登记”，按照表格
要求填写完整后按提交键即可，或者将您的汇款凭证传真至我部门并在
传真中注明续租字样及写明您所要续租的域名、主机管理员用户名等详
细信息。

如在域名或主机到期的十个工作日内未收到您的汇款或汇款凭证传
真（传真上请注明续费并写明要续费的域名、用户自助系统用户ID或主
机管理员用户名），我公司将不会对您的域名向域名注册机构续费，关
闭您已到期的主机，我公司将不负任何法律责任，如有特殊情况请您与
我部门及时联系。

再次感谢您对中国万网的支持和厚爱，祝您工作愉快！

--------------------------------------------------------------
中国万网客户关系部
联系电话： 010-65547878－8214、8209、8215、8205、8206
传真： 010-65542354
Email: renewal@hichina.com
尊敬的中国万网用户 cmh2001：
您好！

首先，感谢您选择中国万网，为了方便、及时地和您沟通，跟进双方的业务处
理情况，中国万网专设了我们这个特别的部门--服务支持部，我们相信，在这神奇的
Internet上，通过我们的努力，中国万网和您是没有隔阂的，衷心希望通过我可以
将你我的距离拉的更近，衷心希望今后能更好为您服务！

其次，这封信主要是为了通知您，您在我们客户数据系统中的联系信息如下：

单位/个人名称： 陈明华
用户单位/个人地址： 文华路西天河西苑14幢中2-502室
地址邮编： 300012
收信人： 陈明华

我们将在三周内按以上信息，以挂号方式为您邮寄：

发票金额： 100元的信件寄出，请收到此邮件后认真核对地址，
如果有错误请您在两个工作日内登陆您在中国万网自助系统
http://bips.hichina.com/maindoc/usr/update_password/update_reginfo1_1.php3下，
更改您的联系方式。

如确认以上信息无误，我们将按您注册ID信息邮寄发票。

顺祝！
商祺！

如果有任何疑问请直接与我们联系，感谢您的信任与支持！

中国万网 服务支持部
Email: ss@hichina.com

Feb 19, 2002
管理员登录名：uj80e1
登录名：
新密码：
确认新密码：

主机域名：www.solaires.com
主机IP地址：210.192.102.31
续租完成

原跟踪号为200103070600007
新业务跟踪号为200204030600037
请您从即日起两周内办理续费手续，主机"万网明星A方案主机"今年的续费价格为320.00元(没有额外初装费)。我们在保留原有主机后续服务的同时，现行推出的明星、皓月、旭日三种系列品牌分别为针对不同需求的客户提供一系列低价格，高品质的整体服务。高速的网络带宽，高端数据库、数据加密、在线交易、视频音频在线播放，让您的网站在此得到最完美的体现。我们提供的网络营销服务，充分体现贵网站的的潜在价值，从而吸引成千商上万的商业用户访问您的站点。为了及时准确地办理您的业务，请您在汇款之后务必将汇款凭证传真至010-65542354，传真中注明续租字样及业务跟踪号。
单位名称： 北京万网网络技术有限责任公司
联系电话： 010-65547878
公司传真： 010-65542354
开户银行： 中信实业银行富华大厦支行
帐 号： 7110310182300074018
通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层
邮政编码： 100027

尊敬的客户 陈明华 ：

您好！感谢您选择中国万网服务，并感谢您对我公司的信任和大力支持！

您在我公司续租申请的业务如下：

新业务跟踪号：200204030600037

主机类型：万网明星A方案主机 租用期限：12 个月 到期时间：2003-04-14 续费价格
320.00

请您将以上费用按以下付款方式至我公司：
----------
付款方式：
----------
1、银行电汇：
收款人名称： 北京万网网络技术有限责任公司
开户银行：中信实业银行富华大厦支行
帐 号： 7110310182300074018

2、邮局汇款：
收款人名称： 北京万网网络技术有限责任公司
收款人地址：北京市东城区朝阳门北大街8号富华大厦C座13层
邮政编码： 100027
附言中请注明续租业务及用户自助服务系统用户ID。

3、直接到我公司付费：
公司地址：北京市东城区朝阳门北大街8号富华大厦C座13层
（地铁东四十条站港澳中心方向出口向南200米）

4、预付款及一卡通付费：
您可以直接将款项付入您ID下的预付款，发传真给我们说明您的款项付哪笔业务并加盖公章
(个人用户请附身份证复印件)即可。
或者您可以直接进入 http://bips.hichina.com 点击“客户服务系统” 输入用户ID及密码
-〉在页面底部单选“续租业务”，并点击“查看业务清单”按钮 -〉选择续租项目，填写
相关信息-〉完成递交-〉用一卡通付款。

---------
特别提示：
---------
为使您的业务及时处理，请您在汇款之后务必进入
http://bips.hichina.com，输入您在我公司自助服务系统用户
ID: cmh2001 及密码后，点击“用户管理”中的“汇款登记”，按照表格
要求填写完整后按提交键即可，或者将您的汇款凭证传真至我部门并在
传真中注明续租字样及写明您所要续租的域名、主机管理员用户名等详
细信息。

如在域名或主机到期的十个工作日内未收到您的汇款或汇款凭证传
真（传真上请注明续费并写明要续费的域名、用户自助系统用户ID或主
机管理员用户名），我公司将不会对您的域名向域名注册机构续费，关
闭您已到期的主机，我公司将不负任何法律责任，如有特殊情况请您与
我部门及时联系。

再次感谢您对中国万网的支持和厚爱，祝您工作愉快！

--------------------------------------------------------------
中国万网客户关系部
联系电话： 010-65547878－8214、8209、8215、8205、8206
传真： 010-65542354
Email: renewal@hichina.com
尊敬的客户：cmh2001
您好，您于2002年04月08日在中国万网自助服务专区预付款申请页面注入的预付款已经得到
中国万网确认，金额为：320元。
有了此预付款，您就可以在中国万网自助服务专区办理国际域名实时注册、国内域名注册、
网站寄放申请等业务（业务费用在预付款金额之内），处理速度更快、办理结果即时有效。
如果您申请的业务已经全部提交上来，您的汇款也已到帐，但由于您申请的业务较多，我们
不能确定您需要交费的业务，所以只能暂时将您的费用录入到您的ID号下做预付款，
这时，您需要进入用户自助服务系统平台的用户管理中进行用户自助结算，确认并提交您需
要付费的业务，这样您申请的业务才会得到进一步的处理。

如有任何问题，请随时与我公司联系。谢谢您对我们的信任与支持！
===========================================================================
中国万网票据部
公司名称： 北京万网网络技术有限责任公司
全国免费电话： 800-810-8500
联系电话： (010) 65546191 (呼叫中心)
公司传真： (010) 65542377
通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层
邮政编码： 100027
开户行： 中信实业银行富华大厦支行
帐号： 7110310182300074018
普通联络： sales@hichina.com
网址： http://www.net.cn或 http://www.hichina.com
===========================================================================
客户:cmh2001 您目前的预付款余额为:0元
下面列出您的未付款业务,你可以使用您的预付款支付
状态为未结算的业务表示此域名申请需要您付款方可生效('.中国','.网络','.公司'的中文域名除外)
中国企业电子商务工程卡用户可以点这里对工程卡主机进行续费
2002-4-9
尊敬的中国万网客户：陈明华
    您好！首先，感谢您选用中国万网的服务！
    您通过我公司申请的主机solaires.com将于2002-4-14到期，为了防止丢失您
宝贵的域名，不影响您网站的正常访问请您在域名到期前10个工作日内向我公司办理域名续费事宜。

您的业务情况如下：
      业务跟踪号　 　 　 业务内容 　　　续费金额
      200103070600007 　 　 solaires.com 　　　320元/年

办理续费方法一：
1、 登陆万网网站，输入您在万网注册的用户ID和密码进入用户电子商务平台。
2、 点击页面左上方功能列表中的"续租业务"，会显示出您ID中需要续费的全部业务，请选择需要续费的业务点
击"提交"按钮进行提交。
3、 选择续费年限后点击"提交"按纽进行提交，同时会出现系统提示页面，请再次确认并点击"提交"按纽进行提
交，同时系统生成跟踪号
4、 通过各种方式办理汇款支付续租费用。
5、 将汇款底单传真至010-65542394或010-65542377续租部收（请在传真上注明您的用户ID、续租业务明细，并注明"续租"字样）。

办理续费方法二：
1、 通过各种方式办理汇款支付续租费用。
2、 将汇款底单传真至010-65542394或010-65542377续租部收（请在传真上注明您的用户ID、续租业务明细及您的
要求，并注明"续租"字样）。
3、 相关操作由万网工作人员代替您完成。

特别注意提示：
1、为了及时准确地办理您的业务，请您汇款至我公司时在附言中注明续租业务，并将汇款凭证传真至续租
部，并务必在传真中注明“续租”字样及您要续费的域名。
2、如果您未能及时缴纳域名费用，贵公司的宝贵域名将会被internic（国际互联网络信息中心）视为自动
放弃而删 除该域名，在此情况下，我公司将无法为您提供任何帮助。如有特殊情况请您与我部门及时
联系。
3、如果您的联系方式有改变，请您登录我公司网站 www.net.com 录入您的用户名及密码，进入会员信息
区，点击“更改会员信息”项，修改您的联系方式。以便我们可以及时的联系到您，不至使您的域名丢
失，我们非常感谢您 对我们的大力支持与合作。
付款方式：

----- 银行电汇 -----
开户名称：北京万网网络技术有限责任公司
开户银行：中信实业银行富华大厦支行
帐　　号：7110310182300074018

----- 邮局汇款 -----
汇款地址： 北京市东城区朝阳门北大街8号富华大厦C座13层
收款单位： 北京万网网络技术有限责任公司
邮政编码： 100027 （附言中请注明续租业务详情）

----- 直接付费 -----
欢迎客户直接到我公司13层业务厅办理支票或现金付款手续
公司地址：北京市东城区朝阳门北大街8号富华大厦C座13层
（地铁东四十条站东南出口，港澳中心向南200米富华大厦）

    再次感谢您对中国万网的支持与厚爱，并希望您能对我们的工作提出宝贵的意见，以便改进我们的服务，同时为您提供更多的方便，并衷心地感谢您选择我公司长久地为您提供服务！

使用……网站推广……提高网站的的知名度和访问量！
企业或个人建立网站后，都希望自己的网站能被更多的人访问，尤其是被自己的潜在客户浏览，这样才有可能让客户详细地了解自己，从而进行在线订购、网上支付等活动。 要实现这一目标，有效地实施网上营销策略，就显得非常重要。

中文搜索引擎基本加注
中文搜索引擎排名保证
英文搜索引擎基本加注
英文搜索引擎快速加注
营销软件购买

企业E化……为您量身订制个性化互联网应用解决方案！
    详细信息>>

                                                                    中国万网续租部
                                                                     2002-04-08

尊敬的客户：
您好！首先，感谢您选用中国万网的服务，并感谢您长期以来对我们的信任和支持！

我们已经接收到您的主机续费升级申请，并已经为您办理完毕。

现您升级的主机信息如下：

域名：solaires.com

IP地址：不变

跟踪号：200204030600037

服务期限：12

到期日：2003-04-14

主机登陆名：不变

密码：不变

另外，很荣幸地通知您,为了使您也能享受我们提供的一系列高品质的整体服务

我公司推出了针对不同需求客户的多品牌系列建站服务―明星系列、皓月系列和

旭日系列,如您感兴趣敬请您浏览请见我公司网站：http://www.net.cn

再次感谢您对中国万网的支持与厚爱，并衷心地希望我公司能长久地为您提供服
务！

如有任何问题，请随时与我公司联系。谢谢您对我们的信任与支持！

===========================================================================
公司名称： 创联万网国际信息技术（北京）有限公司
全国免费电话： 800-810-8500
联系电话： (010) 65546191 (呼叫中心)
公司传真： (010) 65542377
通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层
邮政编码： 100027
开户行： 招商银行朝阳门支行
帐号： 2180477710001
普通联络： sales@hichina.com
网址： http://www.net.cn或 http://www.hichina.com
===========================================================================

2002-4-15
2002-9-30 16:30 call Net.cn, told the guy my password.
中国万网系统迁移通知

--------------------------------------------------------------------------------

尊敬的中国万网用户10163724：

您好！

为了能给您提供更加优质的网络应用服务，经过慎重考察及周密的技术调研评估，中国万网郑重选择中国网通作为自己的合作伙伴，并成为中国网通的一级客户。

中国万网同中国网通的强强合作，将使中国万网的用户可以充分利用中国网通提供的强大带宽优质服务，以独有千兆光纤接入中国ChinaNET骨干网络，并享有独立的国际出口。这不仅能提高国际域名注册服务的响应速度和可靠性，并使所有的虚拟主机用户在国外的用户访问更快。最终使中国万网对用户的服务
基础上升到一个新的档次，继续提高行业领先的优质服务品质。

目前我们定于从2002年12月11日开始到2002年底，将所有服务器按计划分批次陆续搬迁到中国网通提供的新的服务地点。为了最小程度的影响您的网站或其他服务运行，每次迁移的时间会安排在一般访问量最小的凌晨0:00-4:00时段内，以下先将近日与您相关的具体迁移说明通告如下，请您务必认真阅读，尽量避免出现一些问题和不必要的损失，以便最快最好的完成这次迁移工作。

一、调整相关信息：

1、 调整操作时间： 2002年12月13日0:00--4:00

2、 您的虚拟主机域名：solaires.com

3、 您的虚拟主机管理员名：uj80e1

4、 您的虚拟主机管理员密码：不变

5、 您的虚拟主机旧IP地址：210.192.102.31

6、 迁移后您的虚拟主机新IP地址：211.151.25.76

二、万网通告与建议：

1、 如您的虚拟主机域名解析现在是由中国万网做解析指向，即您域名的DNS记录的域名服务器为，“DNS1.HICHINA.COM；DNS2.HICHINA.COM”的我们将为您做更改解析指向工作，而且迁移行动都安排在凌晨期间的访问低谷时间进行，并且调整期间您的虚拟主机所有服务都将会暂时中断，请您提前做好相关工作准备。不过中断时间我们将会控制在四至六个小时之内，请不必担心；

2、 但如您的域名解析不是由中国万网做解析指向，我们无法控制您主机在此迁移过程的服务中断时限，请您尽快提前与您的域名解析服务提供商联系，建议最好在我们调整开始的时间左右，在您的域名服务器上将您的相关域名解析中原来指向为旧IP地址的都指向到迁移后的虚拟主机新IP地址上，并刷新DNS记录，这样可以尽量缩短服务中断的时间，然后在我们调整完成后，当您修改的域名解析记录已经在全球正式生效，则您的网站将恢复正常；

3、 我们的自动备份系统已经对您的数据做了不间断定时备份，但为防止极端意外情况发生，以及保证能随时可以恢复出最新数据，建议您最好在我们调整行动之前将您网站的数据库及网页数据都备份到您的本地机器硬盘上；

4、 如您的邮件联系不能中断，请您在此次调整期间务必采用其他免费邮箱或其他方式替代进行邮件联系同时尽量将您保留在服务器端的邮件收取到本地，不要将邮件保存在服务器上；

5、 在此次迁移期间，为避免您的更新数据丢失或冲突，请您暂停您网站内容的更新和其他控制面板等设置操作；

6、迁移完成之后，可能由于全球各地网络服务商的域名服务器（DNS）更新时间频率有所不同，可能会导致您的网站出现无法访问等由于域名解析延迟导致的故障，如访问您的网站，域名仍是指向旧的IP地址等，如果这种情况出现，您可以再耐心等待一段，一般在24小时之内所有的确的域名解析一定可以完成更新，您的网站服务将恢复正常；

7、另外，提醒您如果您的程序或任何应用中有使用虚拟主机IP地址的地方，为了保证迁移后仍运转正常，请记着将程序中IP地址更新为现在迁移后的虚拟主机新IP地址，并且，如果您除本次通知中标明的域名之外，仍有其他域名通过IP地址指向您的此虚拟主机，请自行修改其DNS解析将其旧IP地址替换为新的IP地址，否则通过这些域名可能将无法正常访问；

8、 由于网络迁移调整期间会有一些用户来电咨询了解情况，将会造成电话线路繁忙的现象，为使您能更快了解到迁移改造的相关信息及我们的一些通告，请您随时留意我公司技术支持网站上的通告及我们发给您的通知邮件。

三、万网特别声明：

如果您的域名不是中国万网负责解析服务的，我们无法直接进行操作和修改，所以特此请您积极按照以上的第2条建议配合此次调整工作；另外您自己程序中、或者任何涉及到您虚拟主机原IP地址的地方，也请您按照以上的第7条建议自行修改，希望在大家共同的努力下能够圆满的完成这次调整，另外，如果由于您没有准确按照以上步骤进行操作，导致您的网站出现的一切后果和损失由您自负，这一点请您理解并支持我们的工作，当然，请相信，最终实现圆满的调整而争取尽量少影响您一秒钟的使用，是我们共同的目标和心愿，衷心希望能在您和我们的积极配合下顺利实现，在此感谢您的理解和帮助！

为了和您一同保障迁移改造的顺利进行，我们已经安排和组织了精湛的工程师队伍负责此次迁移行动，请记住，万网一直在您身边，如您在迁移期间遇到什么问题，都可以随时和我们联系，我们承诺将保持中国万网最好的服务品质，并尽最大的努力帮助您解决问题，敬请放心。另外，对于迁移期间给您带来的所有不便之处，在此也希望能得到您的谅解和支持，谢谢！

如果您有任何问题需要我们的帮助，请勿直接回复此信，而通过我们规范的问题在线处理系统进行递交：

http://www.net.cn/HAS_Client/cbssclient/online_question.asp

再次感谢您对中国万网的支持与信任，让我们携手明天，共创辉煌！！！

此致

敬礼!

中国万网

--------------------------------------------------------------------------------

=============================================================
通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层 邮政编码： 100027
客户服务专线：010-65546191 开户行 : 中信实业银行富华大厦支行 帐号: 7110310182300074018
网址： http://www.net.cn
=============================================================

兹证明 chen minghua 申请的 域名solaires.com 已由我公司在 2002年2月19日为您注册成功，域名的有效期至2003年3月14日。
                                                            特此证明。
注：
1.对于您注册成功的域名与任何第三方的权利发生冲突的情况，我公司都将不予介入。
2.对由于您注册的域名因侵犯第三方权利而被管理机关暂停、注销或者以其他任何方式剥夺您对此域名所有权的情况，我公司将不负任何责任。
3.对由于域名管理机构的政策或技术性原因而对您的域名所产生的一切影响，我公司将不承担任何责任。
4.域名证书的解释权在创联万网公司。


万网上海分公司乔迁帐号变更

http://www.net.cn

万网上海分公司乔迁帐号变更！

亲爱的客户您好！

---万网上海分公司已经于2003年1月25日乔迁新址，银行帐号已经变更为：

公司名称：北京万网网络技术有限责任公司上海分公司

开 户 行：上海银行徐家汇支行

帐 号：316926－00005213004

请上海、江苏、浙江、三地客户注意请将您的款项汇到新的帐号上，以免延误

您正常的业务申请

地址及联系方式变更如下：

新 址： 上海市漕溪北路18号 实业大厦4楼A2 邮编： 200030

咨询电话：021－64410556

传 真： 021－64279660

特别提示通过邮局汇款的客户请注意新的汇款地址

非常感谢的支持和配合！

中国万网--

2003/1/27--
中国万网续费通知（第一次）
尊敬的10163724陈明华
您好！首先，感谢您选用中国万网的服务！

    现将您用户ID中距到期还有45天的业务清单提供给您，请您核对，以便及时安排续费等相关事宜。续费业务清单：

★续租产品：
产品类型 产品名称 产品内容 续租产品 续租价格 产品数量 续租金额 服务开始日 服务到期日 服务年限
域名 国际英文域名注册 solaires.com 国际英文域名注册
130元/1年
1 130元/1年
2002-02-19 2003-03-14 1
合计 130元

另，如果您收到我们的平信催费函，费用与此信中的费用不同，请已此封信为准。

续租办理步骤

特别提示：
请您在域名服务期限届满之前至少15天以书面形式通知万网续费并保证万网在收到您的书面通知之前收到您按照万网所公布的收费标准提交的续费款项，否则，将不能保证您的域名能够续费成功。

再次感谢您对中国万网的支持与厚爱，并希望您能对我们的工作提出宝贵的意见，以便改进我们的服务，

同时为您提供更多的方便，并衷心地感谢您选择我公司长久地为您提供服务！

联系电话： (010) 65546191

公司传真： (010) 65542377

通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层邮政编码： 100027

开户行 : 中信实业银行富华大厦支行帐号: 7110310182300074018

开户名称: 北京万网网络技术有限责任公司

续租部信箱： renew@hichina.com

网址： http://www.net.cn 或 http://www.hichina.com

如果您有任何问题，欢迎拨打我公司24小时热线服务电话01065546191，或通过
http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

中国万网续费通知（第二次）
尊敬的10163724陈明华
您好！首先，感谢您选用中国万网的服务！

    现将您用户ID中距到期日36天的业务清单提供给您，请您核对，以便及时安排续费等相关事宜。请您在业务到期前10个工作日办理您的续租业务，续费业务清单如下：

★续租产品：
产品类型 产品名称 产品内容 续租产品 续租价格 产品数量 续租金额 服务开始日 服务到期日 服务年限
域名 国际英文域名注册 solaires.com 国际英文域名注册
130元/1年
1 130元/1年
2002-02-19 2003-03-14 1
合计 130元

另，如果您收到我们的平信催费函，费用与此信中的费用不同，请已此封信为准。

续租办理步骤

特别提示：
请您在域名服务期限届满之前至少15天以书面形式通知万网续费并保证万网在收到您的书面通知之前收到您按照万网所公布的收费标准提交的续费款项，否则，将不能保证您的域名能够续费成功。

再次感谢您对中国万网的支持与厚爱，并希望您能对我们的工作提出宝贵的意见，以便改进我们的服务，

同时为您提供更多的方便，并衷心地感谢您选择我公司长久地为您提供服务！

联系电话： (010) 65546191

公司传真： (010) 65542377

通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层邮政编码： 100027

开户行 : 中信实业银行富华大厦支行帐号: 7110310182300074018

开户名称: 北京万网网络技术有限责任公司

续租部信箱： renew@hichina.com

网址： http://www.net.cn 或 http://www.hichina.com

如果您有任何问题，欢迎拨打我公司24小时热线服务电话01065546191，或通过
http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

万网续租部,

我已将人民币130元续租费通过邮局于今天汇出，请收到后及时确认和办理续租事宜。

相关信息如下：
汇票号码：330010123000038315
域名：www.solaires.com
用户ID： 10163724
订单号：2200302160409143
业务跟踪号： 4200302160369192

陈明华
杭州市文华路西天河西苑14幢中二单元502室
电话：0571-88912373
邮编：310012

2003。2。16

尊敬的10163724陈明华
您的款项我们已收到，并已录入您的会员id:10163724中，您可以登录会员自助服务系统查询。如果您已提交业务，我们将按照您所选择的结款方式为您办理结款业务。 最后提醒您如选择了自助结算，请您务必登录会员自助服务系统自行结算。

录款编号 录款类型 录款方式 录款金额 发票编号 录款日期
200302180200092 汇款 信汇 130 2003-2-18

回复人:bill@hichina.com

注：如果您的联系方式或邮寄有变化，请务必及时更新您的信息，这样可以使我们更方便地与您联系或邮寄发票。另外如果您还没有提交业务，请您别忘了登陆万网会员区申请业务。 如果您有任何问题，欢迎拨打我公司24小时热线服务电话01065546191，或通过http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

北京万网网络技术有限责任公司
全国免费电话： 800-810-8500(需购买星级服务包或购买标准企业型以上机型)
联系电话： (010) 65546191 (客户服务中心)
公司传真： (010) 65542377
通信地址： 北京市东城区朝阳门北大街8号富华大厦c座13层邮政编码： 100027
开户行 : 中信实业银行富华大厦支行帐号: 7110310182300074018
普通联络： sales@hichina.com
网址： http://www.net.cn或 http://www.hichina.com
2003.2.20

尊敬的陈明华 10163724:
感谢您选择中国万网的服务，现高兴地通知您，您申请的域名业务：

产品类型 产品名称 产品内容 成功日期 服务到期日 服务年限
域名 国际英文域名注册 solaires.com 2003-2-21 2004-3-14 3:22:18 12月

注册申请已经获得注册机构的批准，您的域名已经正式申请成功。您的域名注册的详情可以通过访问我们网站的首页http://www.net.cn/，通过域名查询处验证。(由于全球域名数据库全部更新需要24小时，所以您收到此信时，在验证区不一定查到，请您于24小时后再试即可查询成功。)
在您成功地注册您的域名之后，您将获得中国万网以下的服务：
1、 dns解析服务
2、 url转发
3、 email转发
4、 自行设置、修改域名指向

以上服务您均可登陆会员区已付款产品管理中的域名附加服务中进行管理

为了方便我们与您更好的沟通，请您及时更新您在会员区中的联系方式（特别是您的email地址）。

另：此信为自动回复函，请不要回复此信，如果有任何疑问请点击这里，提交您的问题，我们会在最快的时间解决您的问题 。

--------------------------------------------------------------------------------

北京万网网络技术有限责任公司
全国免费电话： 800-810-8500(需购买星级服务包或购买标准企业型以上机型)
电话： (010) 65546191 (客户服务中心)
传真： (010) 65542377
地址： 北京市东城区朝阳门北大街8号富华大厦c座13层(100027)
网址： http://www.net.cn

尊敬的10163724陈明华
您好！首先，感谢您选用中国万网的服务！

    现将您用户ID中距到期还有45天的业务清单提供给您，请您核对，以便及时安排续费等相关事宜。续费业务清单：

★升级续租产品：
产品类型 产品名称 产品内容 续租产品 续租价格 产品数量 续租金额 服务开始日 服务到期日 服务年限
主机 万网明星A方案主机 solaires.com 专业个人型主机
320元/1年
1 320元/1年
2002-04-15 2003-04-14 1
原产品已不可续租，但您可以自行选择升级方案

另，如果您收到我们的平信催费函，费用与此信中的费用不同，请已此封信为准。

续租办理步骤

特别提示：
请您在域名服务期限届满之前至少15天以书面形式通知万网续费并保证万网在收到您的书面通知之前收到您按照万网所公布的收费标准提交的续费款项，否则，将不能保证您的域名能够续费成功。

再次感谢您对中国万网的支持与厚爱，并希望您能对我们的工作提出宝贵的意见，以便改进我们的服务，

同时为您提供更多的方便，并衷心地感谢您选择我公司长久地为您提供服务！

联系电话： (010) 65546191

公司传真： (010) 65542377

通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层邮政编码： 100027

开户行 : 中信实业银行富华大厦支行帐号: 7110310182300074018

开户名称: 北京万网网络技术有限责任公司

续租部信箱： renew@hichina.com

网址： http://www.net.cn 或 http://www.hichina.com

如果您有任何问题，欢迎拨打我公司24小时热线服务电话01065546191，或通过
http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

你好，万网，

我于昨天（2003。3。9）已经将续费RMB 294元通过邮政汇款汇到贵公司，具体信息如下：

汇票号码：330010123000040671
业务跟踪号：4200303060406073。

请查收。

陈明华
杭州时力电力信息技术研究所
2003。3。10
杭州
----- Original Message -----
From: renew@hichina.com
To: solaires@gmx.net ; solaires@gmx.net
Sent: Monday, March 10, 2003 5:26 AM
Subject: 中国万网续费通知（第二次）

尊敬的10163724陈明华
您好！首先，感谢您选用中国万网的服务！

    现将您用户ID中距到期日36天的业务清单提供给您，请您核对，以便及时安排续费等相关事宜。请您在业务到期前10个工作日办理您的续租业务，续费业务清单如下：

★升级续租产品：
产品类型 产品名称 产品内容 续租产品 续租价格 产品数量 续租金额 服务开始日 服务到期日 服务年限
主机 万网明星A方案主机 solaires.com 专业个人型主机
320元/1年
1 320元/1年
2002-04-15 2003-04-14 1
原产品已不可续租，但您可以自行选择升级方案

另，如果您收到我们的平信催费函，费用与此信中的费用不同，请已此封信为准。

续租办理步骤

特别提示：
请您在域名服务期限届满之前至少15天以书面形式通知万网续费并保证万网在收到您的书面通知之前收到您按照万网所公布的收费标准提交的续费款项，否则，将不能保证您的域名能够续费成功。

再次感谢您对中国万网的支持与厚爱，并希望您能对我们的工作提出宝贵的意见，以便改进我们的服务，

同时为您提供更多的方便，并衷心地感谢您选择我公司长久地为您提供服务！

联系电话： (010) 65546191

公司传真： (010) 65542377

通信地址： 北京市东城区朝阳门北大街8号富华大厦C座13层邮政编码： 100027

开户行 : 中信实业银行富华大厦支行帐号: 7110310182300074018

开户名称: 北京万网网络技术有限责任公司

续租部信箱： renew@hichina.com

网址： http://www.net.cn 或 http://www.hichina.com

如果您有任何问题，欢迎拨打我公司24小时热线服务电话01065546191，或通过
http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

尊敬的10163724陈明华
您的款项我们已收到，并已录入您的会员id:10163724中，您可以登录会员自助服务系统查询。如果您已提交业务，我们将按照您所选择的结款方式为您办理结款业务。 最后提醒您如选择了自助结算，请您务必登录会员自助服务系统自行结算。

录款编号 录款类型 录款方式 录款金额 发票编号 录款日期
200303100224254 汇款 信汇 294 2003-3-10

回复人:bill@hichina.com

注：如果您的联系方式或邮寄有变化，请务必及时更新您的信息，这样可以使我们更方便地与您联系或邮寄发票。另外如果您还没有提交业务，请您别忘了登陆万网会员区申请业务。 如果您有任何问题，欢迎拨打我公司24小时热线服务电话01065546191，或通过http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

北京万网网络技术有限责任公司
全国免费电话： 800-810-8500(需购买星级服务包或购买标准企业型以上机型)
联系电话： (010) 65546191 (客户服务中心)
公司传真： (010) 65542377
通信地址： 北京市东城区朝阳门北大街8号富华大厦c座13层邮政编码： 100027
开户行 : 中信实业银行富华大厦支行帐号: 7110310182300074018
普通联络： sales@hichina.com
网址： http://www.net.cn或 http://www.hichina.com
2003.3.12

尊敬的陈明华 10163724:
感谢您选择中国万网的服务，现高兴地通知您，您的主机升级业务

老主机：产品类型 产品名称 产品内容 服务开始日 服务到期日 服务年限
主机 万网明星A方案主机 solaires.com 2002-4-15 2003-4-14 12月
新主机：产品类型 产品名称 产品内容 服务开始日 服务到期日 服务年限 总空间
主机 Ⅰ型空间 solaires.com 2003-3-12 2004-3-6 12月 100

经过我们的调试，已经完成。

请您注意以下相关事项 ：

1、如果您收到的通知中新主机登录名与原主机登录名不同，则请尽快将原网页内容上传至新主机，并且把您的域名重新指向到我们给您的新的ip地址，旧主机将于七天后删除。

2、您的邮件系统需要升级到企业邮局，申请步骤如下：

请进入我们的主页http://www.net.cn—>会员登录——>输入用户名、密码 登陆-->到您的自助服务系统——>已付款产品管理——>进入相应主机的“订单详情”——>赠送产品——>申请赠送企业邮局。

3、您的企业邮局升级后原email信箱将在30天后关闭，请用原主机ip地址备份原来主机上附带的邮件。

4、关于企业邮箱使用和设置方法，请参看我们的《企业邮箱使用手册》

注：查询虚拟主机详细情况，请您登录我们的自助服务系统－＞已付款产品管理＞相应主机业务->使用方法->查看详情

为了方便我们与您更好的沟通，请您及时更新您在会员区中的联系方式（特别是您的email地址）。

另：此信为自动回复函，请不要回复此信，如果有任何疑问请点击这里，提交您的问题，我们会在最快的时间解决您的问题 。

提示：根据政府管理部门规定，建立网站的用户必须到当地通信管理部门办理网站许可登记(icp证书)，请您务必及时办理。

--------------------------------------------------------------------------------

北京万网网络技术有限责任公司
全国免费电话： 800-810-8500(需购买星级服务包或购买标准企业型以上机型)
电话： (010) 65546191 (客户服务中心)
传真： (010) 65542377
地址： 北京市东城区朝阳门北大街8号富华大厦c座13层(100027)
网址： http://www.net.cn

2003.3.13

敬的陈明华 10163724:
感谢您选择中国万网的服务，现高兴地通知您，您在线提交的“企业邮箱业务”已经开通，详细信息如下:

产品类型 产品名称 产品内容 成功日期 服务到期日 服务年限 管理员登陆名 管理员密码
主机 企业邮箱Ⅰ型 solaires.com 2003-3-13 2004-3-6 12月 postmaster@solaires.com 620721(q4x2l6f7)

Q: what you like most

A: sex and girls

如果您作为邮箱后缀的域名的dns解析是由中国万网提供的，则我们已为您做好了相应的解析工作。如果您的域名dns解析不是由中国万网提供的，则请您通知您的域名注册商将您的mail.域名和域名的mx记录解析到在以上成功通知书中提供的ip地址，然后才能正常使用。

关于企业邮箱使用和设置方法，请参看我们的《企业邮箱使用手册》

如果您以前使用我公司的email转发功能，则现在该域名下的email转发功能即时失效，不再继续使用。 如果您使用该域名申请过主机业务，则该主机上附带的邮箱也即时失效，但不影响您的网站正常浏览。总之，有关该域名下的一切与邮件有关的功能都已转移到新的企业邮局中，谢谢您的使用。

为了方便我们与您更好的沟通，请您及时更新您在会员区中的联系方式（特别是您的email地址）。

另：此信为自动回复函，请不要回复此信，如果有任何疑问请点击这里，提交您的问题，我们会在最快的时间解决您的问题 。

--------------------------------------------------------------------------------

北京万网网络技术有限责任公司
全国免费电话： 800-810-8500(需购买星级服务包或购买标准企业型以上机型)
电话： (010) 65546191 (客户服务中心)
传真： (010) 65542377
地址： 北京市东城区朝阳门北大街8号富华大厦c座13层(100027)
网址： http://www.net.cn

1)solaires@gmx.net, uj80e1, cmh620721, solaires.com

--1)uj80e1@solaires.com,uj80e1,cmh620721

--2)postmaster@solaires.com, uj80e1, (q4x2l6f7) 620721

--3)ceo@solaires.com, ceo, 620721

--4)cto@solaires.com,cto, 620721

--5)cmo@solaires.com,cmo, 620721

--6)cpo@solaires.com, 620721
关于预防互联网有害信息的函

尊敬的客户：

为进一步清除有害信息，维护互联网安全环境，北京市通信管理局于2003年7月25日召开了“关于清除互联网有害信息有关问题的通知”的会议，会议强调各公司要对有害信息给予充分的重视，并加强自查、自纠的能力。为了积极配合这次会议的精神，我公司已于近期组织大规模的清查行动，并希望在此项工作中能得到您的大力支持与配合，并就我们在工作中总结出来的一些容易受到有害信息侵蚀的环节供您参考，建议您有针对性地加强管理：

一、 加强您公司网站所有内容的检查、管理，尤其是加强其中有关论坛、留言板/簿等有害信息易发板块的查管力度，对论坛、留言板/簿等内的信息做到先审后发，将有害信息堵在源头。

二、 加强您公司网站中所链接的其它网站、广告内容等的监审工作，以免有害信息渗入。

三、 加强您公司网站专管人员对于有害信息的防范意识教育，提高自查、自纠的能力。

四、 请及时更新您公司网站专管人员在我公司的注册联系信息，以便与相互沟通。

五、 加强对您公司所有员工的关于互联网有害信息的普及教育，以防祸起萧墙。

为了保障您及我公司还有其他客户的利益，共同维护网络安全的大好局面，真诚地希望我们的工作能得到您的积极配合，对您的理解与支持，谨以我公司名义表示真挚地感谢！

致

礼！

中国万网

2003年8月28日

※参考信息：

一、根据《互联网信息服务管理办法》（中华人民共和国国务院令第292号，于2000年9月20日国务院第31次常务会议通过，现已经公布实施）。

第十五条之规定：互联网信息服务提供者不得制作、复制、发布、传播含有下列内容的信息：

（一）反对宪法所确定的基本原则的；
（二）危害国家安全，泄露国家秘密，颠覆国家政权，破坏国家统一的；
（三）损害国家荣誉和利益的；
（四）煽动民族仇恨、民族歧视，破坏民族团结的；
（五）破坏国家宗教政策，宣扬邪教和封建迷信的；
（六）散布谣言，扰乱社会秩序，破坏社会稳定的；
（七）散布淫秽、色情、赌博、暴力、凶杀、恐怖或者教唆犯罪的；
（八）侮辱或者诽谤他人，侵害他人合法权益的；
（九）含有法律、行政法规禁止的其他内容的。

二、中国万网网站寄放服务条款的相关规定：

2-1 用户的权利和义务

2-1-4 用户不得利用本网站或者万网服务器上传（Upload）、下载（Download）、储存、发布如下信息或者内容：违反国家法律法规政策的任何内容（信息）；违反国家规定的政治宣传和/或新闻信息；涉及国家秘密和/或安全的信息；封建迷信和/或淫秽、色情、下流的信息或教唆犯罪的信息；博彩有奖、赌博游戏；违反国家民族和宗教政策的信息；防碍互联网运行安全的信息；侵害他人合法权益的信息和/或其他有损于社会秩序、社会治安、公共道德的信息或内容。用户同时承诺不得为他人发布上述不符合国家规定和/或本服务条款约定的信息内容提供任何便利，包括但不限于设置URL、BANNER链接等。用户承认万网有权根据万网自己谨慎的判断来决定用户发布的内容是否构成违反服务条款或者国家的有关规定。用户承诺在接到万网的通知后会调整用户网站上的内容以符合国家规定或者本服务条款约定，否则万网有权终止本服务条款项下的服务。同时，对于用户将服务器用于虚拟主机或磁盘空间出租服务的，用户应要求租用其空间的客户不得进行上述活动。万网发现用户或者用户的客户从事上述活动的，万网有权随时终止服务；因用户从事上述给万网带来任何损失或者不利影响的，用户应承担赔偿责任；因用户的客户从事上述而给万网带来任何损失或不利影响的，用户应与其客户承担连带赔偿责任。

2-2-4 保留因用户违反2-1-3、2-1-4、2-1-5、2-1-7和/或2-1-8而终止用户网站运行的权利。同时万网对用户进行或违反2-1-3和/或2-1-4的行为所产生的后果及对用户自行安装的软件和进行的操作所引起的问题及对所发布信息的内容所产生的影响、后果不承担责任。
2003-12-12
尊敬的中国万网用户10163724：

    您好！

    众所周知，质量是一点一滴不断改善和努力的结果，中国万网在2003年通过ISO9001国际质量管理体系认证、全面提升服务质量之后，决定进一步投资IDC以改善用户的虚拟主机及其它各项业务应用环境。为了能给您提供更加优质的网络服务，经过慎重考察及周密的技术调研评估，中国万网决定选择中国电信作为自己的合作伙伴，全面启用位于中国电信的万网专用IDC机房。

    万网服务器群迁入中国电信后，用户可以充分利用中国电信提供的优质网络资源，以独有千兆光纤接入中国ChinaNET骨干网络，并享有独立的国际出口。这不仅能提高国际域名注册服务的响应速度和可靠性，并将提升虚拟主机站点在国内外的访问速度。最终使中国万网对用户的服务上升到一个新的档次，继续提高万网行业领先的优质服务品质。

    中国万网定于2003年12月4日开始，将包括虚拟主机和各项业务主机在内的服务器群陆续迁入到新的中国电信提供的服务地点，以保证您在2004年度中享受到更好的服务。IDC迁移工作将于2003年年底前按计划、分批次进行，为了最大限度的减小迁移期间对您的网站或其它各项服务的影响，我们会将迁移的时间安排在日访问量最小的凌晨0:00-4:00时段内。

    每次迁移行动的正式通知，我们将会提前三天发送到您在我公司注册用户时的联系人电子邮件信箱，其中将有详细的迁移信息和说明，请您注意查收，或上www.net.cn网站您的数字ID帐号内查看您的信息。 以下就是最近一次迁移中与您相关的信息，请您务必认真阅读，尽量避免出现一些问题和不必要的损失，以便我们最快最好的完成这次升级改造工作。

一、调整相关信息：

1、 调整操作时间： 2003年12月16日23点

2、 您的虚拟主机域名：solaires.com

3、 您的虚拟主机管理员名：uj80e1

4、 您的虚拟主机管理员密码：不变

5、 您的虚拟主机旧IP地址：210.192.102.31

6、 迁移后您的虚拟主机新IP地址：218.30.100.29

二、万网通告与建议：

1、 如您的虚拟主机域名解析现在是由中国万网做解析指向，即您域名的DNS记录的域名服务器为，“DNS1.HICHINA.COM；DNS2.HICHINA.COM”或“DNS7.HICHINA.COM；DNS8.HICHINA.COM”的我们将为您做更改解析指向工作，而且迁移行动都安排在凌晨期间的访问低谷时间进行，并且调整期间您的虚拟主机所有服务都将会暂时中断，请您提前做好相关工作准备。不过中断时间我们将会控制在四至六个小时之内，请不必担心；

2、 但如您的域名解析不是由中国万网做解析指向，我们无法控制您主机在此迁移过程的服务中断时限，请您尽快提前与您的域名解析服务提供商联系，建议最好在我们调整开始的时间左右，在您的域名服务器上将您的相关域名解析中原来指向为旧IP地址的都指向到迁移后的虚拟主机新IP地址上，并刷新DNS记录。这样可以尽量缩短服务中断的时间，然后在我们调整完成后，当您修改的域名解析记录已经在全球正式生效，则您的网站将恢复正常；

3、 我们的自动备份系统已经对您的数据做了不间断定时备份，但为防止极端意外情况发生，以及保证能随时可以恢复出最新数据，建议您最好在我们调整行动之前将您网站的数据库及网页数据都备份到您的本地机器硬盘上；

4、 非万网企业邮局用户，如您的邮件联系不能中断，请您在此次调整期间务必采用其他免费邮箱或其他方式替代进行邮件联系同时尽量将您保留在服务器端的邮件收取到本地，不要将邮件保存在服务器上；

5、 在此次迁移期间，为避免您的更新数据丢失或冲突，请您暂停您网站内容的更新和其他控制面板等设置操作；

6、迁移完成之后，可能由于全球各地网络服务商的域名服务器（DNS）更新时间频率有所不同，可能会导致您的网站出现无法访问等由于域名解析延迟导致的故障，如访问您的网站，域名仍是指向旧的IP地址等，如果这种情况出现，您可以再耐心等待一段，通常情况下在24小时之内所有域名解析一定可以完成更新，您的网站服务将恢复正常；

7、另外，提醒您如果您的程序或任何应用中有使用虚拟主机IP地址的地方，为了保证迁移后仍运转正常，请记着将程序中IP地址更新为现在迁移后的虚拟主机新IP地址，并且，如果您除本次通知中标明的域名之外，仍有其他域名通过IP地址指向您的此虚拟主机，请自行修改其DNS解析将其旧IP地址替换为新的IP地址，否则通过这些域名可能将无法正常访问；

8、 由于网络迁移调整期间会有一些用户来电咨询了解情况，将会造成电话线路繁忙的现象，为使您能更快了解到迁移改造的相关信息及我们的一些通告，请您随时留意我公司技术支持网站上的通告及我们发给您的通知邮件。

三、万网特别声明：

如果您的域名不是中国万网负责解析服务的，我们无法直接进行操作和修改，所以特此请您积极按照以上的第2条建议配合此次调整工作；另外您自己程序中、或者任何涉及到您虚拟主机原IP地址的地方，也请您按照以上的第7条建议自行修改，希望在大家共同的努力下能够圆满的完成这次调整。另外，如果您没有准确按照以上步骤进行操作，我们将无法保证您的网站在迁移后仍能够正常访问，这一点请您理解并支持我们的工作，当然，请相信，最终实现圆满的调整而争取尽量少影响您一秒钟的使用，是我们共同的目标和心愿，衷心希望能在您和我们的积极配合下顺利实现，在此感谢您的理解和帮助！

为了和您一同保障迁移改造的顺利进行，我们已经安排和组织了精湛的工程师队伍负责此次迁移行动，请记住，万网一直在您身边，如您在迁移期间遇到什么问题，都可以随时和我们联系，我们承诺将保持中国万网最好的服务品质，并尽最大的努力帮助您解决问题，敬请放心。另外，对于迁移期间给您带来的所有不便之处，在此也希望能得到您的谅解和支持，谢谢！

如果您有任何问题需要我们的帮助，请勿直接回复此信，而通过我们规范的问题在线处理系统进行递交：
http://www.net.cn/HAS_Client/cbssclient/online_question.asp

再次感谢您对中国万网的支持与信任，让我们携手明天，共创辉煌！！！

此致

敬礼!

中国万网

通信地址： 北京市东城区鼓楼外大街27号万网大厦3层 邮政编码： 100011
客户服务专线：010-64242266 开户行 : 中信实业银行富华大厦支行 帐号: 7110310182300074018
网址： http://www.net.cn


万网上海分公司乔迁帐号变更

2004.2.5
尊敬的客户：
您好!
您的汇款底单传真件我们已收到，但实际款项还未到账，待款到后会按照您传真中的ID为您录入的。谢谢！有问题欢迎和我们联系。
创联万网需要您一如既往的支持！
【财务部】 创联万网
=================================================
北京万网网络技术有限责任公司
----中国最大的域名和网站寄放服务提供商。
=================================================
地址: 北京市东城区鼓楼外大街27号万网大厦3层
邮编:100011
全国长途受付业务服务电话: 800-810-8500
电 话: 86-10-64242299
传 真: 86-10-64254247
电子邮件: sales@hichina.com
网 站: http://www.net.cn/
尊敬的客户10163724：

您好!
您的此次汇款的帐户名称填写错误，请您查实，重新办理汇款，谢谢您的合作，我们收到您的款项后会及时和您联系的。您可以把款汇到上海分公司，详细信息您可以查看http://www.net.cn/static/contactus/

2004.2.6
尊敬的陈明华 10163724

您的款项我们已收到，并已录入您的会员id:10163724中，您可以登录会员自助服务系统查询。如果您已提交业务，我们将按照您所选择的结款方式为您办理结款业务。 最后提醒您如选择了自助结算，请您务必登录会员自助服务系统自行结算。

录款编号 录款类型 录款方式 录款金额 发票编号 录款日期
200402060623343 汇款 电汇 820 2004-2-6

回复人:bill@hichina.com

注：如果您的联系方式或邮寄有变化，请务必及时更新您的信息，这样可以使我们更方便地与您联系或邮寄发票。另外如果您还没有提交业务，请您别忘了登陆万网会员区申请业务。 如果您有任何问题，欢迎拨打我公司24小时热线服务电话010-64242266，或通过http://cbss.hichina.com/maindoc/bips_daili_online/login.php3在线提交您的问题。

--------------------------------------------------------------------------------

北京万网新兴网络技术有限公司
全国免费电话： 800-810-8500(需购买星级服务包或购买标准企业型以上机型)
售前电话：010-64242277
售后电话：010-64242266
传真： 010-64254247
地址： 北京3050信箱(100011)
网址： http://www.net.cn

北京万网新兴网络技术有限公司上海分公司
联系电话：（021）64410556
传　　真：（021）64279660
通信地址：上海市漕溪北路18号 实业大厦4楼a2 （200030）
开户行 ：上海银行徐家汇支行
账 号：316926-00005240809

北京万网新兴网络技术有限公司广州分公司
联系电话：(020) 38795151
传　　真：(020) 38795152
通信地址：广州市体育西路109号高盛大厦18楼b座（510620）
开 户 行：广州市商业银行水荫支行
帐　　号：0019-707-2-219-8099158-76

2004-2-6
您的成功业务:
产品包名称 产品包内容 应收金额 实收金额 推荐按钮 续费按钮 升级按钮 赠送按钮 结算日期 成功日期 服务期限(月) 到期日期
国际英文域名注册 solaires.com 500.00 500.00 推荐 续费 升级 赠送 2004-2-6 2004-2-6 60 2009-3-14
专业个人型主机 solaires.com 320.00 320.00 推荐 续费 升级 赠送 2004-2-6 2004-2-6 12 2005-3-6
明星A方案 solaires.com 320.00 320.00 推荐 续费 升级 赠送 2001-3-13 2001-3-14 13 2002-4-14
尊敬的陈明华10163724：
     您好，感谢您选择中国万网的服务，我们高兴地通知您，您申请的国际英文域名续费业务已经成功。您的业务详情如下：

产品类型 产品名称 产品内容 成功日期 服务到期日 服务年限
域名 国际英文域名注册 solaires.com 2004-2-6 2009-3-14 3:22:18 60月

您的域名详情可以通过访问我们网站的首页http://www.net.cn/，在域名查询处查询验证。(由于全球域名数据库全部更新需要24小时，所以您收到此信时，在验证区不一定查到，请您于24小时后再试即可查询成功。)
您可以继续享受中国万网以下的服务：
1、 dns解析服务
2、 url转发
3、 email转发
4、 自行设置、修改域名指向
以上服务您均可通过登陆万网自助服务会员区，选择“已付款产品管理”中的“域名附加服务”功能进行管理

为了方便我们与您更好的沟通，请您及时更新您在会员区中的联系方式（特别是您的email地址）。

此信为自动回复函，请不要回复此信，如果您有任何问题，我们也非常愿意听到您的声音，欢迎拨打我公司24小时热线服务电话010-64242266，或点击这里在线提交您的问题，我们会在最快的时间内解决您的问题 。

04-02-06
尊敬的陈明华 10163724:

您的业务已经成功，详细信息及资料如下：详情

产品类型 产品名称 产品内容 成功日期 服务到期日 服务年限 管理员登陆名 管理员密码
主机 企业邮箱Ⅰ型 solaires.com 2004-2-6 2005-3-6 12月 postmaster@solaires.com q4x2l6f7

提示：根据政府规定，建立网站的用户必须到当地通信管理部门办理网站许可登记(icp证书)，请您务必及时办理。

04-02-06
尊敬的陈明华 10163724:
感谢您选择中国万网的服务，现高兴地通知您，您的主机续租业务

产品类型 产品名称 产品内容 成功日期 服务到期日 服务年限 管理员登陆名 管理员密码 主机IP 临时域名
主机 Ⅰ型空间 solaires.com 2004-2-6 2005-3-6 12月 uj80e1 e5s8y2x8 218.30.100.29 uj80e1.chinaw3.com

经过我们的调试，已经完成。

请您注意以下相关事项 ：

1、如果您收到的通知中新主机登录名与原主机登录名不同，则请尽快将原网页内容上传至新主机，并且把您的域名重新指向到我们给您的新的ip地址，旧主机将于七天后删除。

2、您的邮件系统需要升级到企业邮局，申请步骤如下：

请进入我们的主页http://www.net.cn—>会员登录——>输入用户名、密码 登陆-->到您的自助服务系统——>已付款产品管理——>进入相应主机的“订单详情”——>赠送产品——>申请赠送企业邮局。

3、您的企业邮局升级后原email信箱将在30天后关闭，请用原主机ip地址备份原来主机上附带的邮件。

4、关于企业邮箱使用和设置方法，请参看我们的《企业邮箱使用手册》

提示：根据政府规定，建立网站的用户必须到当地通信管理部门办理网站许可登记(icp证书)，请您务必及时办理。

04-02-06


My Website
I have registered the www.solaires.com domain name and purchased the 100 MB virtual hosting services with static HTML parsing functions - no database driven, no interactivity - at a combined price of about RMB 500 a year for three years now. The service provider is located in Beijing and is boosted of the no. 1 in China. I was unsatisfied during the first 1.5 years then it gets better. At the earlier time, I have very often difficulties downloading or uploading files for maintenance. Duo to no sufficient income, I am unable to purchase more functions, more space for better services - such as online information feedback and I am also unable to design a better looking site for the same reason.
Over the last three or four years this site has been undergoing drastic changes.
The first site, with a domain name of softhousing.com, was full of information about website design technologies, solutions and related software and web application technology introductions. At the peak time, it has a volume of ca 600 pages, with four language versions - Chinese, English, German and French.
Since coming to Hangzhou, the first version of www.solaires.com still centered on web technologies. However, from 2002 on, it gradually turns to a information portals for the chinese power industry - first solar energy and windpower software, then the solar energy and windpower industry as general, then joins other power sectors such as biomass, geothermal, hydropower, ocean power, tidal power, fossil and nuclear, city waste incineration - in one word, all power generation activities.
In May this year, I determined to give up the power business and focus exclusively on the language service - including document translation and software localization and globalization - that's what you see know. During the May - August period, I maintained a English-German-French trilingual version, but found out to be too tired to keep all the three versions current, therefore I decided to keep only the English version.
I wish this is the last design.

Business websites

To better understand my pst businesses, you may have a look at some of the following websites. These are the 50+ sites out of hundreds I have developed over the last decade for my business. Officially I have registered three domain names: softhousing.com in 2000-2003, solaires.com in 2003-2008 and then helioslab.org from 2009 till 2014. But the helioslab.org domain was abandoned in 2010 after only one years operation due to the worsening of the Internet atmosphere in China and hence I have never been operating my own domains and sites. Instead I am switching from one free host to another over the last 4 years and thus I am completely lost out of the Internet presence. The shutting down of my once populous site of solaires.com has also caused me tremendous economic as well as image damages and losses since 2006 and since then I can never been fully recovering myself. Solaires.com was once the most populous English language site about the Chinese solar industry and market on the Internet and was once highly evaluated by investors and industry insiders alike.

These sites are arranged in alphabetical order and some of them are not always working properly, so that I have to move their hosts from time to time. Also note that all of them were outdated and will never be maintained.

They are now moved to a collective site for internal use only.

我的网站

自2000年起，为了配合我的业务， 学习研究， 职业和生涯发展， 我开发和运行了数亿百计的网站， 其中还有50来个目前还在挂着。 我为着自己的业务， 业和生涯发展， 我付出了无数心血， 结果一无所获，真是旷世奇闻。

目前我还在维护的是一个自己过去经历的网站， 一个目前正在进行中各项研究和业务的网站， 一个发电设备贸易的网站， 再有就是这个博客了。

My Websites

Over the last years (2000-2015) , I have developed hundreds of websites for my business, studies and career. Among them the following are still alive (those marked red are not available). I have, as clear from these sites, spent incredible amount of time and efforts on developing my businesses, conducting my researches, and improving my career and quality of life, only to bring no results at all.

I guess there is no such a failure rate in human history and I have reached the throttle where any human can endure the failure in his life. I will no more continue my pursuit of academic career, and instead, I will try to earn some small money and continue with my mountaneerng to make me strong.

?
?

Personal Site addresses

The following sites contain much private and privacy information. (They are previously only available for my closest friends.)

Mark Chen 2016-3-5 2016-9-23

markchen.scienceontheweb.net

Mark Chen 2016

markchen8.scienceontheweb.net

https://sites.google.com/site/markchenstudio/

minghua 2014 XXXXX

http://minghua.scienceontheweb.net

neolingo.medianewsonline.com

==========================================

neolife2 - NeoLife - 2013

Http://mingstudio.atwebpages.com

neolife3 - MyLife - 2012 ???

neolife4 - MyLife - 2012 okokok

http://mylife.atwebpages.com

neolife5 - CMH - 2010 okokok

@@@@@@@@@@@@@@@@@@@@@

Solaires at angelfire - my only surviving online bilingual CV since 2001 ???

http://www.angelfire.com/linux/solaires/index.htm

http://www.iwr.de/guest/jobo.html~

https://code.activestate.com/lists/perl-modules/11728/

http://webmail.dev411.com/t/perl/modules/025yhp74xs/career-development

NeoSciences - my websites for studies and researches

Math4Chip - at scienceontheweb.net - 2014 okokok

http://math4chip.scienceontheweb.net

neosciences - NeoSciences - 2013 ???

mingstudio - MingStudio - 2011 okokok

Http://mingstudio.atwebpages.com

Business websites

Advancedpower 2015

http://advancedpower.atspace.cc/

advancedpower 2016

http://advancedpower.getenjoyment.net/

advancedpower.mypressonline.com

advancedpower.scienceontheweb.net

http://advancedpower.eu.pn/

========================================

Advanced Power Technologies Ltd. (APT)

http://advancedchip.en.ec21.com/

Advanced Power Technologies Ltd. (APT)

http://solaires.en.ecplaza.net/

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

power1 - MingPower - 2007 nonono okokok

http://powerchina.atwebpages.com

power2 - SPC - 2006 okokok

http://powerchina.mypressonline.com

power3 - SPI - 2005 okokokok

2016 SPI

http://www.solaires.tk

http://power001.atwebpages.com

power4 - SPI - 2005

####################################

Languages - translations, globalization, internationalization and localization

2015-9-25

neolingo.atspace.eu

http://neolingo.atwebpages.com

http://neolingo7.atwebpages.com

neolingo.batcave.net

http://neolingo.co.nf/

http://neolingo.eu.pn/

http://neolingo.myartsonline.com

http://neolingo.mygamesonline.org/

http://neolingo.mypressonline.com/

http://neolingo3.mypressonline.com/

http://neolingo.mywebcommunity.org

http://neolingo9.mywebcommunity.org/

http://neolingo.scienceontheweb.net/

http://neolingo5.scienceontheweb.net/

http://neolingo.sportsontheweb.net/

==========================================

redirected to NeoLingo 2015 okokok

http://neolingo.scienceontheweb.net/

NeoLingo 2015

@@@@@@@@@@@@@@@@@@@@@@@@

lang0 - NeoGlossa - 2013 okokok

http://neoglossa.atwebpages.com

lang2 - STS - 2003 Englsh, German and French okokok

http://neolingo.atwebpages.com

lang3 - STS - 2003 okokok

lang3 - STS - 2003 okokok

http://neolingo.mywebcommunity.org

####################################

Aviation - Chinese business aviation consulting

aviation1 - AAA - 2012 okokok

http://aaa.co.nf/

http://aerochina.getenjoyment.net

aviation1 - AAA - 2012 okokok

http://aerobiz.me.pn

aviation1 - AAA - 2012 okokok

http://aviation.eu.pn

aviation2 - AAA - 2012

aviation3 - XMAir - 2007

aviation3 - XMAir - 2007

http://aviation.myartsonline.com

Business consulting for Hangzhou

bizhangzhou - SBI - 2004 okokok

http://bizhangzhou.atwebpages.com

Cancer prevention consulting

cancer - CCC - 2007

Chip Design and consulting

ACT at allalla - 2014 (under development)

IT - IT technology services

My once most informative IT site - softhousing.com - was lost. It was then considered as one of the most comprehensive IT sites in China by IT insiders.

it1 - Solaires - 2002

it2 - Solaires - 2002

it3 - Solaires - 2002

it4 - Solaires - 2001

it5 - Softhousing.com + DataNet were lost

Lux consulting

luxchina - LuxChina - 2010 okokok

http://luxchina.batcave.net

NeoTech - comprehensive information about my past businesses

HeliosLab HeliosLab20111006 / HeliosLab20111006_1- at neotechchina.tk directed to co.nf - 2011

neotech1 - NTC - 2013 ???

neotech2 - HeliosLab - 2011 ???

HeliosLab HeliosLab20111006 / HeliosLab20111006_1- at co.nf - 2011 okokok

http://neotech.co.nf

HeliosLab HeliosLab20111006 / HeliosLab20111006_1- at MZZHost 2011

HeliosLab okokok

http://neotech.atspace.cc

=============================

CSC20110916

HeliosLab20120420

HeliosLab20120508

HeliosLab20120508_1

Helioslab_CN20090712

Helioslab_ENCN20090707

NeoTech20130127

NeoTech20130703

NeoTech20130703_1 okokok

Real estates - Chinese real estates industry consulting

AlphaPropperties-English 2017

http://castlesland.tekcities.com/

AlphaPropperties-Chinese 2017

http://castles.ultimatefreehost.in/

AlphaPropperties20141031 - Castles worldwide consulting okokok

AlphaPropperties20140628 - Castles worldwide consulting okokok

Alpha20120208 = realestates1 - APC - 2011

REChina20110614 = realestates2 - REChina - 2010 okokok

Alpha20110716

REChina20100510

okokok

Security - Telecommunications, information and network security technology services and consulting

security1 - BIST - 2013 okokok

http://secuweb.atwebpages.com

security2 - HeliosLab - 2011

security3 - CryptoBASE - 2010

Solar - Chinese solar energy industry consulting

solar01 - HeliosLab - 2009 my most favorite site

solar02 - HeliosLab - 2009

solar03 - HeliosLab - 2009 okokok

http://solarchina.sportsontheweb.net

solar04 - HeliosLab - 2008 okokok

http://solar.mypressonline.com

solar05 - HeliosLab - 2008 okokok

http://solartrends.atwebpages.com

http://solartrends.atwebpages.com/index.html

solar06 - HeliosLab - 2008 okokok

http://solar.batcave.net

http://solar.batcave.net/index.html

solar07 - HeliosLab - 2007 okokok

http://solar1.myartsonline.com

http://solar07.myartsonline.com

solar08 - HeliosLab - 2007 okokok

solar09 - SPI - 2004 okokok

http://solarnow.mypressonline.com

solar10 - SPI - 2004

solar11 - SPI - 2004 okokok

http://solarchina.mywebcommunity.org

solar12 - SBI - 2004

okokok

http://solarchina.onlinewebshop.net

Thermal - Thermal technology consulting

thermal1 - CATT Chinese/English - 2011

thermal2 - CATT - 2011 okokok

http://thermal.atwebpages.com

thermal3 - CATT - 2011 okokok

thermal4 - ThermodynamicsToday - 2008

Yachts - Chinese yacht industry consulting

yachts1 - NeoYacht - 2013

yachts2 - NeoYacht - 2011 okokok

http://yachtchina.myartsonline.com

yachts3 - YachtsChina - 2010 okokok

http://yachts.scienceontheweb.net


My Website

我的网站

自2000年起，为了配合我的业务， 学习研究， 职业和生涯发展， 我开发和运行了数亿百计的网站， 其中还有50来个目前还在挂着。 我为着自己的业务， 业和生涯发展， 我付出了无数心血， 结果一无所获，真是旷世奇闻。

目前我还在维护的是一个自己过去经历的网站， 一个目前正在进行中各项研究和业务的网站， 一个发电设备贸易的网站， 再有就是这个博客了。

My Websites

Over the last years (2000-2015) , I have developed hundreds of websites for my business, studies and career. Among them the following are still alive (those marked red are not available). I have, as clear from these sites, spent incredible amount of time and efforts on developing my businesses, conducting my researches, and improving my career and quality of life, only to bring no results at all.

I guess there is no such a failure rate in human history and I have reached the throttle where any human can endure the failure in his life. I will no more continue my pursuit of academic career, and instead, I will try to earn some small money and continue with my mountaneerng to make me strong.

Personal Site addresses

The following sites contain much private and privacy information. (They are previously only available for my closest friends.)

Mark Chen 2015

https://sites.google.com/site/markchen0088/

Mark Chen 2015

https://markchen9.blogspot.com

directed to

Mark Chen 2015

http://markchen.mipropia.com

@@@@@@@@@@@@@@@@@@@@@

minghua 2014

http://minghua.scienceontheweb.net

neolife1 - NeoLife - 2013

http://neolife.mipropia.com

neolife2 - NeoLife - 2013

http://neolife.1-ws.com

neolife3 - MyLife - 2012 ???

http://mylife.allalla.com/

neolife4 - MyLife - 2012

http://mylife.atwebpages.com

neolife5 - CMH - 2010

http://minghua.5gbfree.com

Solaires at angelfire - my only surviving online bilingual CV since 2001 ???

http://www.angelfire.com/linux/solaires/index.htm

http://www.iwr.de/guest/jobo.html~

https://code.activestate.com/lists/perl-modules/11728/

NeoSciences - my websites for studies and researches

2015

https://sites.google.com/site/markchenstudio/

#########################

Math4Chip - at scienceontheweb.net - 2014

http://math4chip.scienceontheweb.net

neosciences - NeoSciences - 2013 ???

http://neosciences.fun2pk.com/

mingstudio - MingStudio - 2011

Http://mingstudio.atwebpages.com

Business websites

Power, Electricity and Energy

Advancedpower 2015

https://sites.google.com/site/advancedpowerchina/

Advanced Power China at Google Blog - 2015

https://advancedpowerchina.blogspot.com/

Advanced Power Tech at Google Blog - 2014

https://advancedpowertech.blogspot.com

directed to - temporary

http://power001.atwebpages.com

Advancedpower 2015

http://www.advancedpower.tk/

Advancedpower 2015

http://graphembedding.0fees.us

Advanced Power Technologies Ltd. (APT)

http://advancedchip.en.ec21.com/

Advanced Power Technologies Ltd. (APT)

http://solaires.en.ecplaza.net/

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

Advanced Power Tech 2014 ??????????

http://thermal.br0s.info/

power1 - MingPower - 2007 nonono

http://powerchina.atwebpages.com

power2 - SPC - 2006 okokok

http://powerchina.mypressonline.com

power3 - SPI - 2005 okokokok

http://power001.atwebpages.com

power4 - SPI - 2005 okokok

http://power.free-hoster.net

####################################

Languages - translations, globalization, internationalization and localization

NeoLingo 2015

https://sites.google.com/site/neolingo888/

NeoLingo 2015

https://neolingo.blogspot.com

redirected to NeoLingo 2015

http://neolingo.scienceontheweb.net/

http://neolingo.freeforums.org/

NeoLingo 2015

http://www.neolingo.tk

redirected to

http://neolingo.scienceontheweb.net/

@@@@@@@@@@@@@@@@@@@@@@@@

NeoLingo 2003 ???

http://neolingo.fun2pk.com/

lang0 - NeoGlossa - 2013

http://neoglossa.atwebpages.com

lang1 - STS - 2003 ????????/

http://neolingo.0zed.com

lang2 - STS - 2003 Englsh, German and French

http://neolingo.atwebpages.com

lang3 - STS - 2003

http://neolingo.getenjoyment.net

lang3 - STS - 2003

http://neolingo.mywebcommunity.org

####################################

Software Reverse Engineering

http://blog.sina.com.cn/solaires

####################################

Aviation - Chinese business aviation consulting

aviation1 - AAA - 2012 ??????????

http://aviation.freehostingchamp.com/

aviation1 - AAA - 2012

http://aerochina.getenjoyment.net

aviation1 - AAA - 2012

http://aerobiz.me.pn

aviation1 - AAA - 2012

http://aviation.eu.pn

?????????

http://aerochina.mobhost.in

aviation2 - AAA - 2012

http://aaa.co.nf/

aviation3 - XMAir - 2007 ?????????

http://aviation.holdonhosting.net/

http://aviation.myartsonline.com

Business consulting for Hangzhou

bizhangzhou - SBI - 2004

http://bizhangzhou.atwebpages.com

Cancer prevention consulting

cancer - CCC - 2007 ?????????

http://cccchina.5gbfree.com:

Chip Design and consulting

ACT at Voila - 2014 (under development)

http://advancedchip.voila.net/

ACT at allalla - 2014 (under development) ?????????

http://advancedchip.allalla.com/

IT - IT technology services

My once most informative IT site - softhousing.com - was lost. It was then considered as one of the most comprehensive IT sites in China by IT insiders.

it1 - Solaires - 2002

http://itservices.mmkfc.com/

it2 - Solaires - 2002

http://itservices.hostkart.net

it3 - Solaires - 2002

http://itcomputer.byethost15.com

it4 - Solaires - 2001

http://itcomputer.mmkfc.com

it5 - Softhousing.com + DataNet were lost

Lux consulting

luxchina - LuxChina - 2010

http://luxchina.batcave.net

NeoTech - comprehensive information about my past businesses

HeliosLab HeliosLab20111006 / HeliosLab20111006_1- at neotechchina.tk directed to co.nf - 2011

neotech1 - NTC - 2013 ???

http://neotech.atwebpages.com/

neotech2 - HeliosLab - 2011 ???

http://neotech.binhoster.com/

HeliosLab HeliosLab20111006 / HeliosLab20111006_1- at co.nf - 2011

http://neotech.co.nf

HeliosLab HeliosLab20111006 / HeliosLab20111006_1- at MZZHost 2011

http://neotech.mzzhost.com/

HeliosLab

http://neotech.atspace.cc

=============================

CSC20110916

HeliosLab20120420

HeliosLab20120508

HeliosLab20120508_1

Helioslab_CN20090712

Helioslab_ENCN20090707

NeoTech20130127

NeoTech20130703

NeoTech20130703_1

http://neotech.allalla.com

Real estates - Chinese real estates industry consulting

AlphaPropperties20141031 - Castles worldwide consulting

http://castles.myartsonline.com

AlphaPropperties20140628 - Castles worldwide consulting

Alpha20120208 = realestates1 - APC - 2011

http://realestates.mywebcommunity.org

REChina20110614 = realestates2 - REChina - 2010

http://real.myartsonline.com

Alpha20110716

REChina20100510

http://real.sportsontheweb.net

Security - Telecommunications, information and network security technology services and consulting

security1 - BIST - 2013

http://secuweb.atwebpages.com

security2 - HeliosLab - 2011 ???

http://secunet.atwebpages.com

security3 - CryptoBASE - 2010

http://security.free-hoster.net

Solar - Chinese solar energy industry consulting

solar01 - HeliosLab - 2009 my most favorite site

http://solarchina.eu5.org

solar02 - HeliosLab - 2009 ???

http://solar.freevar.com

solar03 - HeliosLab - 2009

http://solarchina.sportsontheweb.net

solar04 - HeliosLab - 2008

http://solar.mypressonline.com

solar05 - HeliosLab - 2008

http://solartrends.atwebpages.com

http://solartrends.atwebpages.com/index.html

solar06 - HeliosLab - 2008

http://solar.batcave.net

http://solar.batcave.net/index.html

solar07 - HeliosLab - 2007

http://solar07.myartsonline.com

solar08 - HeliosLab - 2007

http://solartoday.myartsonline.com

http://solartoday.myartsonline.com/index.html

solar09 - SPI - 2004

http://solarnow.mypressonline.com

solar10 - SPI - 2004

http://solarchina.byethost15.com

solar11 - SPI - 2004

http://solarchina.mywebcommunity.org

solar12 - SBI - 2004

http://solar.scienceontheweb.net

http://solarchina.onlinewebshop.net

Thermal - Thermal technology consulting

thermal1 - CATT Chinese/English - 2011

http://thermal.hostkart.net

thermal2 - CATT - 2011

http://thermal.atwebpages.com

thermal3 - CATT - 2011

http://thermal.mypressonline.com

thermal4 - ThermodynamicsToday - 2008

http://thermal.1-ws.com

Yachts - Chinese yacht industry consulting

yachts1 - NeoYacht - 2013 ???????

http://neoyacht.pagi0.com/

yachts1 - NeoYacht - 2013 ???

http://yacht9.uhostfull.com/

yachts2 - NeoYacht - 2011

http://yachtchina.myartsonline.com

yachts3 - YachtsChina - 2010 ???

http://yachts.scienceontheweb.net


My Website

My Websites
Meanwhy Zen
Meanwhy Zen - Minghua Chen - 陈明华

Emails:

contact@minghua-chen.tk

minghua.chen888@gmail.com
I am currently living in my home village about 200 km southwest to Shanghai, a village named Xinghuo Cun, of Donglin Town, Wuxing District, Huzhou city, Zhejiang province. You may find my humble home from google map. It is a small - according to Chinese criteria - village of about 5000 people, half industrialized. It is a place full of water, but be careful, they are all not clean.

PhD candacy of the following universities

  • University of Glasgow (PhD for gas turbine combustion research)
  • Université de Pierre et Marie Curie in Paris (University of Paris VII), (DEA de Cinétique Chimique Appliquée, option catalyse, Laboratoire de Réactivité de Surface et Structure, 1991),?
  • Université Laval (Doctorat en Genie Mecanique, Faculte des Sciences et de Genie, 1992, Canada),
  • Université de Provence (Formation Doctorale et DEA de Mecanique Energetique et Transferts Thermiques et Combustion, 1991),
  • Universit?t Gesamthochschule Essen (Maschinenbau, H?hreres Semester, Germany, 1992), after a German test

    MPA (Master of Public Administration) candidacy

    • Harvard, applications near completion in 1996 but vetoed by the then employer in Shanghai.

Master of Engineering

(1986-1989) Master degree of thermophysics from Tongji University, Shanghai, China.

Bachelor of Engineering or Sciences

(1978-1983) Bachelor degree of thermal power machines, also Tongji University, Shanghai, China.

To understand me better, you may have a look at some of the following websites. These are the 50+ sites out of hundreds of websites I have developed over the last decade for my business as well as my private life and studies. Officially I have registered three domain names: softhousing.com in 2000-2003, solaires.com in 2003-2008 and then helioslab.org from 2009 till 2014. But the helioslab.org domain was abandoned in 2010 after only one years operation due to the worsening of the Internet atmosphere in China and hence I have never been operating my own domains and sites. Instead I am switching from one free host to another over the last 4 years and thus I am completely lost out of the Internet presence. The shutting down of my once populous site of solaires.com has also caused me tremendous economic as well as image damages and losses since 2006 and since then I can never been fully recovering myself. Solaires.com was once the most populous English languages Chinese solar site on the Internet and was once highly evaluated by investors and industry insiders alike.
Note:
The following links may be in frequent changes.

Life

NeoLife - my private life informaiton

The following sites are purposely left out as they contain too much private and privacy information. They are only available for my closest friends.

neolife0

http://minghuaxxxxxxxxxx

neolife1

http://xxxxxxxxxxxxxxxxxxxxxx

neolife2

http://xxxxxxxxxxxxxxxxxxxxxx

neolife3

http://xxxxxxxxxxxxxxxxxxxxxx

neolife4

http://xxxxxxxxxxxxxxxxxxxxxx

Science

NeoSciences - my studies and researches

neosciences

http://minghua-chen.tk/neosciences/index.html

mingstudio

http://chinastrategy.gofreeserve.com/mingstudio/index.html

http://minghua-chen.tk/mingstudio/index.html

Business

Arranged in alphabetical order

Aviation - Chinese business aviation consulting

aviation1

http://neotech9.t15.org/

aviation2

http://cryptoage.atwebpages.com

aviation3

http://neotech.batcave.net

Business consulting for Hangzhou

bizhangzhou

http://neotech.atspace.cc

Cancer prevention consulting

cancer

http://multilingo.foreverhost.us/

IT - IT technology services

My once most informative IT site - softhousing.com - was lost. It was then considered as one of the most comprehensive IT sites in China by IT insiders.

it1

http://mypastdays.neq3.com/

it2

http://neocrypt.scienceontheweb.net

it3

http://aaa.co.nf/

it4

http://neodream.scienceontheweb.net

Languages - translations, globalization, internationalization and localization

Currently valid site:

http://neolingo.voila.net/

or

http://www.neolingo.tk

lang0

http://neotech.3owl.com/

lang1

http://neotech.3owl.com/lang1/index.htm

lang2

http://neotech.3owl.com/lang2/index.htm

lang3

http://neotech.3owl.com/lang3/index.htm

Lux consulting

luxchina

http://chinastrategy.gofreeserve.com/luxchina/index.html

NeoTech - comprehensive information about my past businesses

neotech1 ????? unstable

http://helioslab.hourb.com/neotech1/index.html

neotech2 ????? unstable

http://helioslab.hourb.com/neotech2/index.html

neotech3 ????? unstable

http://helioslab.hourb.com/

Power - Chinese power industry consulting

power1

http://aviation.eu.pn

power2

http://neolingo.mywebcommunity.org

power3

http://neotech.capnix.com/power3/index.htm

power4

http://neotech.capnix.com/

Real estates - Chinese real estates industry consulting

realestates1

http://neotech.capnix.com/realestates1/index.html

realestates2

http://neotech.capnix.com/realestates2/index.html

Security - Telecommunications, information and Network security technology services and consulting

security1

http://secuweb.fhero.net/

http://neotech.fun2pk.com/security1/index.html

security2

http://security.free-hoster.net

http://neotech.fun2pk.com/security2/index.html

security3

http://secunet.clanmark.com/

http://neotech.fun2pk.com/

Solar - Chinese solar energy industry consulting

solar1

http://neotechchina.atwebpages.com

solar2

http://neolingo.atwebpages.com

solar3

http://helioslab.atwebpages.com

solar4

http://thermalchina.onlinewebshop.net

solar5

http://neotech.hostingsiteforfree.com/

solar6

http://solar1.myartsonline.com

http://solar1.myartsonline.com/index.html

solar7

http://neotech.atwebpages.com/

http://neotech.atwebpages.com/index.html

solar8

http://lingo.fhost.us/

solar9

http://solarchina.eu5.org

solar10

http://lingo.mypressonline.com

solar11

my most favorite site

http://joggers.sportsontheweb.net

solar12

http://chinastrategy.leadhoster.com/solar12/index.htm

Thermal - Thermal technology consulting

thermal1

http://thermal.br0s.info/

http://neobiz.scienceontheweb.net

thermal2

http://thermal.binhoster.com

http://lingos.x90x.net/

thermal3

http://thermal.404host.info/

http://number.myartsonline.com

thermal4

http://thermal.1-ws.com

with ads

http://neocrypt.favcc1.com/

Yachts - Chinese yacht industry consulting

yachts1

http://yachts.0usa.com

http://cryptoserv.0usa.com/

yachts2

http://yachts.0zed.com

http://neolingo.0zed.com

yachts3

with ads

http://yachts.5gbfree.com

http://minghua.5gbfree.com


Netcomm

0NetcommBack.doc

others.doc

chat.htm

email.htm

EmailAccountsChinaInvalid1.doc
EmailAccountsWorldInvalid1.docx
EmailCodesJava.doc
EmailCodesPHP.doc
EmailSecure1.doc
EmailSecureClients.doc
EmailSecureSoft.docx
EmailSecureWebmail.docx
EmailSenders.doc
EmailSenders.txt
EmailServers.doc
EmailServers.txt
EmailSettings.docx
Smtpservices.docx
emailsearch.txt

FTP.docx

mobile-message.htm

messaging.doc

tel.htm

Telcalls.doc
TelcallsGoogle.docx
TelcallsGoogleNow.docx
TelecomSecure.docx
Telnumbers.doc

webfax.htm

webfax.doc


网络通讯-网站聊天系统

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络通讯-网站聊天系统

国外
名称 | 语言 | 说明
ChatPOP | 英文 | 3D graphical animation chatting service. To get started, just download the freeware chat client and select your "avatar" to represent you.This program even comes with a "scene editor," that lets you design your own custom "home." ChatPOP is available in English, Korean and Japanese. (For Windows 98/95 and NT).
Yahoo语音 | 英文 | chat.yahoo.com!!! Voice chatting
国内
名称 说明
多来米聊天室

Lycos语音聊天室

 Lycos语音聊天室的二把门锁：
1.选择下面的爱好频道中的一个点击,然后再选择具体房间。
2.确认你的音箱或耳机打开，并且麦克风插好后进入，按提示操作，请说普通话。

http://cn.tom.com/chat/

语音聊天测试中

浙江省数据通信局 http://chat.zj.cninfo.net/
http://www.sinov.net.cn
聊聊语音聊天网
         http://www.liaoliao.com
九聊语音聊天网 http://www.9liao.com

We See You

VCU 网中人

http://www.vseeu.com/

浏览量不断上升，但是网站带来的业务量却不见提高，这可能是大多数网络服务商目前所面临的问题！
如何使您不再错过访问您网站的浏览者呢？
如何让您有机会与浏览者进行更加直接的交流呢？
一致沟通公司的的We see you - VCU可以帮助您做到！

We see you - VCU可以让您的网页浏览者与那些同在一页或同在一个网站的其他浏览者之间进行文字交流和网页导航。
We see you - VCU同样可以使您的网站管理员能够直接与浏览者进行文字交流和网页导航！

We see you - VCU 把实时传信（Instant Messaging ）的功能带给了每个网页，她把我们熟悉的网络页面变成了一个活跃的互动交流的场所，这是网络互动时代的一次革命。
这是因为单纯的浏览行为已经很难给网站有效的增加利益，同时也限制了浏览者更好的使用网络服务商提供的全部服务。
We See You - VCU这个嵌在网页里的通讯终端可以帮助网站解决这些问题！
网镜

http://www.ngsoft.net/

可使在访问同一页面（网站）的人进行即时交流，并包含好友交流的各种功能


Emails

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

Emails
I have collected and I am still collecting millions of emails to send to my potential clients, but mostly they ignore me.
网络通讯-网站多媒体电子邮件系统
247Fax
http://www.247fax.com/

Email Manage your email, voicemail and fax in one convenient web based email account

Support multilingual and attachment
Provide you with online address book and folder utility for easy contact and file management

Provide you with limited free Email to Fax service
Capability to forward all of your email to your another personal email account

Retrieve your other pop3 email accounts directly

Free !!!


网络通讯-网络与手机和呼机的通讯技术

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络通讯-网络与手机和呼机的通讯技术
第一页
第二页
寻呼软件
Air Message Pro 3.8.3
向呼机或手机上发送信息
CellBuddys v0.9b
给手机发信息
Clickatell
发送信息给你朋友的手机。
COLIAS Messenger v1.03
COLIAS 能够让你通过网络给移动电话发送信息，你可以通过它把信息发给你不在的同事或朋友。感谢它创新的功能，能够让同事之间的沟通变的更加紧密。
gcall2000
超级寻呼通 2000 《大众软件》特别版 1.0 超级寻呼通2000是全新融合互联网与电信技术的通讯软件，它可以通过网络直接向各种无线寻呼机（目前支持种类包括中国联通、国信、润讯、中北等近十家全国连网寻呼台，500余个分台）发送中文或数字信息，覆盖用户人数超过1000万。
GSM助手
通过笔记本电脑（或有红外接口的PC）的红外接口与手机联系，发送中文短消息。
Internet Email Forward V1.05.00
http://www.devnetsoft.com/
Internet Email 转发软件，可以将 email 转发到传呼机、手机或其它 email 帐号，可以设置过滤器。
LightningSMS 0.1.3
只能发送短讯给中国移动通讯用户的手机！ 版本： V 0.0.3 (2000/10/10) ·发送过程中“立即发送”按键不能继续按，避免连发。 ·只有填写所有内容后，“立即发送”按键点击。
Mobile Instant Messenger
http://www.web2mobile.com/
Mobile Instant Messenger 2.0.通过这个软件，你可以向世界上的任何一个移动电话发送短消息。
MsgQ 2.6 网上通
短消息是数字移动电话的业务之一,可向用户手机每次发送160字节的信息,当用户未开机或离开服务区时, 短消息会被存储在服务系统,当用户开机或进入服务区时,短消息立刻送入用户的手机中,因此它跟传呼相比较下有它的优势,中文手机可以支持中 文短信息，非常方便中国人使用. 网上通(MsgQ)是一个可以向中国移动手机用户发送短消息的免费软件，只要对方的手机支持短消息的收发，您就可以通过网上通给他（她）发送短消息。本版本支持中英文的短消息，以及地址簿的功能。
Pager Center 7.02.8
向手机发送文本文件或音频文件
SMPP 1.01
向中国电信的手机发送短消息
短信息发送大师SMS Sender 1.16
功能最为强大的中文短信息发送程序，通过internet直接向GSM手机发送中文短信息。一般发送后5秒左右能够收到，支持电话本、定时发送、历史记录等等，使用极为方便，并且完全免费！
SayaSMS Sender(短信息发送程序) 1.11
你在用电话上网别人找你怎么办？你在上网想找别人联系怎么办？手机一族应充分用好自己的通讯工具，收发短信息让你享受很大便利，因为短信息通信方式的优点：不必担心机主是否方便：即使机主正在开会、通电话，都能够悄悄接收到信息；需要告诉对方的资料，例如电话号码、账号、地址、约会时间等，发送到对方手机上，对方任何时候都能够查看。SayaSMS Sender能让你在网上办到，它还可以定时发送，有历史记录，电话本，队列等。
SmartSMS 3.5
SmartSMS可以让你把图片和铃声文件发送到你的Nokia手机上。 只要用调制解调器连接到支持UCP协议的拨号SMS服务器上，你就可以很方便地把铃声文件和开机画面（BMP、 GIF、JPG、NGG、NOL格式）发送到你的诺基亚手机上
短讯精灵 v1.3.2.9
专为网上发送短讯息而设计，包含了几个不同地域的移动局发送网站。如果某个网站不能发送讯息，只需用鼠标轻轻一点，即可选用另一网站。从网上发送短讯息，惯常的操作是：先上有发送短讯息功能的网站，然后逐层进入发送页面，才能发送。讯息发送后，如果想再发送另外一条讯息，还要返回发送页面。
手机伴侣 v1.8
杨永宏http://www.mmailto.com/
手机伴侣(MMail)是一个可以向国内移动手机用户发送短消息的共享软件， 只要对方的手机支持短消息的收发，您就可以通过手机伴侣给他（她）发送短消息。 本版本支持中英文的短消息，以及地址簿的功能。手机伴侣能同时向中国移动及中国联通用户发送短讯，还可自动发送股票行情，新闻，奥运快讯等等，而且所有收发信息完全免费！几大功能：同时支持中国移动及中国联通用户；自动接收实时股票行情；自动接收各类新闻；支持多用户，个人设置灵活多样；长短语自动分割发送；所有信息完全免费！新版本修改了发送BUG，支持群发，信息自动发送，但本网站的自动发送信息依然停播。
短信息发送程序 1.20
你在用电话上网别人找你怎么办？你在上网想找别人联系怎么办？手机一族应充分用好自己的通讯工具，收发短信息让你享受很大便利，因为短信息通信方式的优点：不必担心机主是否方便：即使机主正在开会、通电话，都能够悄悄接收到信息；需要告诉对方的资料，例如电话号码、账号、地址、约会时间等，发送到对方手机上，对方任何时候都能够查看。SayaSMS Sender能让你在网上办到，它还可以定时发送，有历史记录，电话本，队列等。
网上通2.67英文版
短消息是数字移动电话的业务之一,可向用户手机每次发送160字节的信息,当用户未开机或离开服务区时, 短消息会被存储在服务系统,当用户开机或进入服务区时, 短消息立刻送入用户的手机中,因此它跟传呼相比较下有它的优势,中文手机可以支持中 文短信息，非常方便中国人使用. 网上通(MsgQ)是一个可以向中国移动手机用户发送短消息的免费软件，只要对方的手机支持短消息的收发，您就可以通过网上通给他（她）发送短消息。本版本支持中英文的短消息，以及地址簿的功能
掌信通
http://www.95068.com
短消息发送软件",该软件精巧使用，功能强大，支持客户端发送手机短信给中国移动和中国联通手机用户，及通讯簿导入功能，既将用户存储在OUTLOOK中的联系人信息，导入到掌信通自带的地址簿里。同时该软件还支持用户查询历史信息。
华语网呼 2000 V1.0
http://vchot.topcool.net/
通过网络直接呼叫手机呼机，支持上百家寻呼台，可在线升级，速度快，成功率高（与寻呼内容长度，及网络状况有关）。
超级寻呼通 2000
http://renliang.yeah.net/
超级寻呼通，支持中国联通，国信寻呼，润讯寻呼，万声寻呼，中铁寻呼，斯壮寻呼，万立通寻呼，深圳邮联，手机短讯等众多国内寻呼台及手机短讯。可以直接通过Internet向以上寻呼机或手机发送中文短讯息，界面美观，操作简便。完全免费，中文绿色软件。
综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络通讯--网络寻呼与短信息服务
第一页
第二页
短信息服务

腾讯公司

http://www.tencent.com/

移动QQ服务

  • 手机-QQ
  • QQ-手机
  • QQ-寻呼
  • WAP-QQ
  • QQ讲故事

网易短信中心

http://gsm.163.com/

短信服务

  • 言语传情
  • 铃声传情
  • 传情LOGO
  • 自写短信发送

搜狐短信中心

http://sms.sohu.com/

  • 个人助理
  • 短信发送
  • 短信订阅
  • 手机点播
  • 短信游戏

国浩电信

http://www.wocall.com/

  • E-mail到达手机
  • E-mail到达BP机通知
  • 网络寻呼

掌门网

http://newplat.byair.com.cn/

网络短信息发布

因特国风

http://www.letscard.com/

手机名片

·登录网站，选择或输入留言，发送短消息给朋友，支持群组狂发！
·无须上网，使用手机就可以查找名片，将自己的名片发送给亲朋好友！

中国短信息服务网

http://www.smschina.com/

短信发送：
SmsChina提供网上发送手机短信息功能。

短信传情：
SmsChina提供丰富多采的定制短信息发送功能。千言万语化作漫漫的真情传递到您的手中……

信息订阅：
SmsChina提供股票、彩票、天气、电视、黄历等信息点播服务，为您的生活提供方便。

森泰克短信网

http://www.cctk.net/

  • 信息点播
  • 网上GIS中心
  • 网上发短信


网络通讯-网站电话

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络通讯-网站电话
名称 | 说明

21cn 世纪龙

www.21cn.com

全免费拨打到广东省长途电话，普通电话可以接收。
21CN最新推出，但你需要参加他的调查活动，提交调查表后，会弹出新窗口显示
拨打电话的帐号和密码，每个帐号和密码可以打30分钟电话，音质一般。

www.dialpad.com

 不用安装软件，只须注册时要下载一个JAVA程序，可能要等十几分钟。

Effective May 15, 2001, the following changes were made to our service:

PC-to-phone calls to the United States from all international locations except Canada are no longer free.

The dialing code for international calls to the United States has changed. The new dialing code is 011 1 + area code + phone number.

As an alternative, dialpadworld is offered. With dialpadworld, calls to the U.S. are as low as US2.9 cents per minute. For more information and to purchase dialpadworld, click here >>

The following aspects of service will remain the same:

  • PC-to-phone calls within the United States will remain free
  • PC-to-phone calls from Canada to the United States will remain free
  • PC-to-PC calls from anywhere to anywhere in the world will remain free
  • Toll-free calls from outside the United States will remain free
go2call

http://www.go2call.com

Go2Call is the leading international PC-to-phone provider. Use your PC to make calls to more than 200 countries around the world.

US/Canada: 2￠ Argentina: 17￠ Italy: 6￠ India: 29￠ China: 9￠ Pakistan: 47￠

需要予付
HotTelephone

http://www.hottelephone.com

Make up to 2 hours of free calls per month to more than 25 countries

In order to use the new FREE PC2Phone service, members will be required to register with www.HotTeleLink.com and deposit a minimum of US$14.95 into their account.

Although the service provided by HotTelephone is free of charge, it is necessary to have a minimum of two dollars (2.00 US$) in your HotTeleLink account in order to use the service.

Hottelephone升级，免费PC To Phone范围达到30个国家与地区。

经过验证，已经得到使用密码，但等待密码时间比较长，并且你需要用非免费信
箱去注册才可以被接受。通话音质较好。需要下载一个815K的软件。

免费拨打国家包括：
Australia　Austria　Belgium　Canada　China(Shanghai)　Denmark　England
France　Germany　Hong Kong　Iceland　Ireland　Italy　Japan Korea(South)
Leichtenstein　Netherlands　New Zealand　Norway Russia(Moscow)　Scotland
Singapore　Spain(Madrid)　Sweden　Switzerland　Taiwan(Taipei)　UnitedStates　US Virgin Islands　Wales　Finland等30个国家和地区
sumavoice

http://www.sumavoice.com/

PC to Phone 美国 & 英国 & 法国

Destination Countries | Rate per Minute *
France | US$0.045
Germany | US$0.048
Hong Kong | US$0.048
Israel | US$0.085
Japan | US$0.07
Switzerland | US$0.045
Taiwan | US$0.075
United Kingdom | US$0.039
United States | US$0.039
phonehog

http://www.phonehog.com/

免费10分钟打到世界各地长途电话（用普通电话打）

Phonehog提供免费每个Email 10分钟可以拨打世界各地的电话卡，国内使用可以采
用net2phone、dialpad或MediaRing拨打其1-8886425127号码后输入在该站注册获得
的Pin而后输入　1+国家代码+地区代码＋电话号码　即可通话。多获时间可以参
考下面的“两步曲”的方法。

每介绍一个朋友（提供朋友名字和电子邮件地址即可）获得10分钟打电话的帐号。但条件是，被推荐的人必须在网站上注册。

限于美国国内用户

PopTel

http://www.poptel.com

免费打往美国的网络电话提供网站

注册后获得5分钟的权利。系统（网站）目前在维护中，不能打。
e001.com

E001最新提供全免费打国际长途到新加坡与香港(PC To Phone)！
(！！e001网站暂时停止该服务！！)

5月4日验证，不需要下载软件，直接拨打！立即注册立即可以使用。可能由于没
有广告通话音质甚至比普通电话还要好。
但第一次登录使用需要等待大约15分钟时间下载插件(自动下载，结束时会提示
是否安装，选择是即可)，以后再用登录后不需要等待就可以直接拨打。

亲亲抱抱我

语音聊天室

http://www.77885.com

国际国内免费电话.... 　国内已开通(网络较忙,需多拨打几次,或换别电话房间)

北京丨广州丨上海丨天津丨重庆丨沈阳丨南京丨武汉丨成都丨石家庄丨郑州丨大连丨长春丨济南丨杭州丨福州丨厦门丨长沙丨深圳丨珠海丨肇庆丨中山丨昆明

国际已开通 美国与加拿大
WowRing
www.sundial.com | for wireless
免费 PC to Phone

http://www.tadatel.co.jp/

这个刚刚开通的日本首家可打网络电话的网站，从国内打到日本可以用，不过要按你点击广告的此数给你通话时间。打电话的连接可能是 http://www.tadatel.co.jp/mem/i_default.asp?

rurl=dialer/newdial_index.asp

PC2call

http://www.pc2call.com/

http://www.hit2call.com/

http://www.vectone.com/

PC to Phone 英国/Voice Chat

Hit2Call is revolutionary new technology that will change the way you do business with your customers. It is simply a link embedded on your web pages that does not require installation or changes to your existing system.

Hit2Call enables voice communication and allows your customers to call you while browsing your web site. It adds a human relationship between your customers and a designated representative of your company, giving life to your web site and confidence to your customers.

Why Do I Need a Tool Like This? Online businesses depend on the relationships formed with their customers and Hit2Call is the tool best suited to help you manage these online relationships. 63% of people online say they won't buy anything (online) until there is more human interaction involved (Yankelovich Partners). Customers are still wary of making purchases on the Internet, what's more are very reluctant to provide purchase and personal details over the Internet. If customers can't get hold of you or your representatives to confirm the purchase, they will go somewhere else and you have lost a sale!! At Vectone we have identified the potential of this 'lost' market and have developed Hit2Call, the solution to meet your needs.

mediaring.com

PC to Phone (US,Ca,Cn)

MediaRing最新提供全免费拨打电话到国内14个城市！(PC-Phone)不需要下载软件，直接拨打！立即注册立即可以使用，界面与dailpad差不多，只是它的 Initializing...相思泪等了一个多小时才流到嘴边(56k Modem)，广告倒是Load的挺快(刷新了200多次)，不是为了测试真是....性急者勿用！

(范围包括：北京,天津、上海、广州、石家庄、深圳、南京、杭州、福州、厦门、济南、郑州、长沙、武汉)。

在IP800用hotmail信箱申请的帐号已经一个月，还没有收到注册密码。对它彻底失望
补充：在国内用这些来打国内长途很不合算，除非是从国外往中国拨。

TrulyGlobal (beta)

http://www.trulyglobal.com/

A VocalTec Communications Business

PC to PC

PalTalk

http://www.paltalk.com/

PC to PC

Paltalk is the total Internet communications solution that combines the best of a instant messaging and internet telephony. Paltalk offers a wide range of features that allows users to communicate with each other anywhere in the world at any time - all for free.

Paltalk offers the following services.

  • Voice calls
  • Video conferencing
  • Group Voice conferencing
  • Instant messaging
  • Group text chat
  • Voice mail File Transfer

Visitalk.com

http://www.visitalk.com/

PC to PC

Monthly Subscription $3.50

WhoIsIt?

http://www.whoisit.com/

Internet Call Waiting

$4.95 per month

CallWave

http://www.callwave.com/

Internet Call Waiting

Conflab.com

http://www.conflab.com/

Web based Conference Calling

uReach.com

http://www.ureach.com/

Voice Mail, eMail & Call Forwarding (US)

BuzMe

http://www.buzme.com/

Internet Call Waiting & Voicemail

Enhanced Service, Free 7-day Trial

Sign up and download BuzMe's Internet Call Waiting and Voicemail and never miss phone calls while online again! With BuzMe you will... Receive and respond to phone calls while online Save the cost of an extra phone line Save the cost of for-pay voicemail services Never miss an important call again BuzMe Internet Call Waiting & Voicemail only $5.95/month!

Service Features:

Works with your existing phone line, using your existing phone number. There may be a small setup and monthly charge from your phone company for the necessary forwarding features that enable the BuzMe software and services to work with your existing phone line/number.

Internet Call Waiting complete with Real Time Pop-Up Call Notification & Caller ID for when you're online.

Personal "Web-Based" Messages Page (Voice messages are stored as streaming audio files that you can actually hear!)

Real Time Call Control allows you to respond to incoming calls in the following four ways: Ability to "Reject" Ability to "Send to Voicemail" Ability to "Reply": when you receive a call while online, you can reply to the caller. Use one of the pre-recorded BuzMe replies like "I will call you back in 5 minutes" or type in your custom reply which is spoken back to the caller. Ability to "Take Call": 60 included minutes of talk time when you click on "take call". Extra minutes of "take call" talk time can be purchased in blocks of minutes.

Complete Voicemail online or off - you'll no longer need an answering machine or costly telephone company voicemail services. Still want to use your answering machine for when you are off-line? Simply set it to pick up calls on 2-3 rings. However, using BuzMe's voicemail gives you the ability to check Voicemail instantly via the web. Very cool!

Free Basic Service

While you're online and a call comes in, the call will automatically be routed into your BuzMe voicemail box. After a new Voicemail message has been left by your caller, the BuzMe client will notify you that a message has been left, as well as the ID of the caller. The client includes a "Messages" button, which is your direct link into your messages page. If you select email notification, BuzMe will send you an email every time a caller leaves you a Voicemail message. To cover the expenses of running this FREE internet voicemail service, we've rounded up sponsors who are willing to help offset the costs of the service, in exchange for displaying advertising on BuzMe's voicemail notification window. We have designed the voicemail notification software to remain open on your screen while you are online and rotate ads from our sponsoring partners.

To minimize the intrusion of the BuzMe software, we have programmed it to "dock" at the top or bottom of your screen out of the way of other windows. You will be required to keep the call control software open while you are on the Internet. If you close the call control software while online, the BuzMe Internet Voicemail service will be disabled and callers will hear a busy signal. When you shut down your Internet connection, the voicemail notification software will automatically shut down and disappear from your screen.

Please Note: Although our free Internet Voicemail still helps to solve the problem of missing phone calls while online, it does not provide complete online call control. To actually receive and respond to phone calls in real time while online, check out our full featured Enhanced Service.

Take Call Packages

Need more than 60 minutes worth of "Take Call" talk time each month? Additional minutes are available, at an additional charge, for Enhanced Service users. Unused minutes carry over each month to a maximum of 12 months. Additional minutes are a one-time purchase. You will not be automatically billed for them monthly.

40 minutes = 40 minutes for $4.95

120 minutes = 80 minutes + 40 bonus minutes for $9.95

260 minutes = 160 minutes + 100 bonus minutes for $19.95

700 minutes = 400 minutes + 300 bonus minutes for $49.95

myTalk

http://www.mytalk.com/

eMail by Phone (US)

MailAndNews.com

http://www.mailandnews.com/

http://www.InfiniteVoice.com

eMail by Phone (US) uid:38139; pass:3823

This service will allow you to access your e-mail account via the telephone using state of the art text-to-speech technology.

To access your mailbox toll-free via the telephone, dial 1-800-245-4000. For regular long distance or local access, dial +1-410-559-2187.

Note: Phone access is automatically limited to 60 minutes per month.

Press the * key, and then login with your user information (user id and password)

Note that you can read (hear), reply to, forward or delete any text or voice message in your inbox with this service. You can also originate voice messages to anyone in your personal address book. The service is provided without charge or advertisement for your convenience.

This service is made possible through the use of the Infinite Voice product. For more information on running your own copy of Infinite Voice, please visit http://www.InfiniteVoice.com.

福龙网通

http://pguops.top263.net

交友服务，语音聊天+汉字聊天，免费长途电话室


网络通讯-网站传真

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网络通讯-网站传真
eFax
http://www.efax.com/
To Send Faxes on the Web
You can send faxes to a single recipient from the web. You can include a cover page and attach up to 3 documents, such as Microsoft Word or Excel files.

In order to send faxes you must have the following:

An eFax Plus account. If you do not have one click here to sign up now.
Netscape 3.0x or later or Microsoft Internet Explorer 3.02 or later. If you have a different browser or an earlier version of Netscape or Internet Explorer, see Browser Issues.
To send a fax, follow these steps:

Step 1: Type an address or select a previous fax number.
Click Next.
Step 2: Type a subject and cover page message.
Then click Next to attach a document(s).
Step 3: Click the Browse button and select file(s) to attach.
After you have attached the documents that you want to send, click Next.
Step 4: Make sure the fax information is correct.
If it is, click Send Fax.
If you want to change something, use the Back button in your browser to go back and make the change.

247Fax
http://www.247fax.com/

Fax

Send your fax to any fax machine from your 247fax.com email account. No need to print out your document or use a fax machine
Send fax to your friend's fax number in your online personal Address Book
Support fax attachment in the following formats: English/Chinese, MS-Word, MS-Excel, image file (JPG,BMP,TIF,GIF,PCX)

Fax Forward

Forward by email: your received fax in your 247fax.com email account can be forwarded to any fax machine worldwide
Forward by phone/fax request: your received fax can be forward to any fax machine in the country you registered

Broadcast

You can broadcast a fax from your 247fax.com email account to as many fax machines as you like with a single mouse click
Manage and group your customer's fax number list in your personal online Address Book· Save your time and increase your productivity
Save your money on expensive fax broadcast equipment or expensive outsourcing

Fax on Demand

Special service for your business web site! We provide CGI code which looks like a banner on your web site
The banner is linked to our global fax network
Your customers can request any information (your product information, catalogue, quotation etc.) stored in our fax server to be sent to their fax machine

Faxaway
http://www.faxaway.com

Faxaway Corporate Program

Faxaway offers a program to benefit corporate customers who need to receive a monthly bill for Faxaway services. Faxaway's technology can be scaled to fit any size company, from one person to thousands, allowing each authorized employee to take advantage of the complete range of Faxaway features. Faxaway's domestic and international rate structures provide low-cost solutions to your company's telecommunication needs. Your employees can choose from any of the following suite of functions.?

  • A simple email-to-fax service that requires no special software or system configurations.
    Our email-to-fax service provides your employees with on-demand Internet faxing using your company's email application. Using this service you can customize cover sheets with corporate logos, attach a wide variety of supported graphic and file formats, and receive instant confirmations of all faxes sent by your employees.
  • A web-based fax-back service that you can integrate into your Web site or intranet almost effortlessly.
    Store frequently used corporate literature on Faxaway's server and distribute it to a customer or client upon request. Faxaway's fax-back service also allows employees to fax stored documents to as many destinations as necessary by issuing a simple email command.

  • A broadcast faxing service that puts the power of sophisticated corporate telecommunications delivery systems on every employee's desktop.
    Faxaway enables employees to distribute information to hundreds or thousands of fax recipients in one step. Simple commands allow users to maintain and update distribution lists on Faxaway's servers for easy access and efficient transmissio

Send Faxes From Your Website!
Faxaway Works from your Website!
-Visitors to your website fax themselves important information from your website - applications, user's guides and other documents.
-Visitors to your website fax your company important information or other requests from your website.

Web Developer requirements

-Your web server is capable of sending and receiving e-mail.
-Set up a Faxaway account.
If you are already a Faxaway user, add a sub-account to your existing faxaway account using the email address from which your web server will be sending mail.
-Your WEB server will be the user of Faxaway.
-The Faxaway email is located in the "from" field of the messages. -Faxaway will only send messages from registered users.

Form Requirements

-The From: field and To: field in the email messages received is what Faxaway reads.
-The Faxaway address (faxnumber@faxaway.com) must include country code, area/city code and local fax number (even if it is a local number).
The relevant information from the form is placed into the body of the email message as plain text, or attached in one of our supported document formats.
-The email message is sent to our servers from your web site and we send it as a fax.

EXAMPLE:
Let's say that you're hosting a WEB site for Harry's Hardware Store. Harry doesn't have e-mail at his hardware store, but Harry does have a fax machine.

Harry's Hardware Store fax is 206-555-1212. You have assigned the email address harry@yourdomain.net for Harry's form on the web site you host for him.

Your form should resemble this:
From: harry@yourdomain.net
To: 12065551212@faxaway.com
Body: insert the text from your form OR send it as an attached file.
(when attaching files the word FAXDOC must appear in the subject line)

CONFIRMATIONS ARE SENT FOR EACH MESSAGE

Confirmation messages (indicating an 'end result') are sent to the email address that sent the message.
Confirmations include: time received and transmitted, the cost, the fax number dialed and subject.
Confirmations are also sent for Rejected or Failed transmissions.

FaxMailer
http://www.easylink.com

FaxMailer uses your existing e-mail system and network technology to send faxes over the Internet. There ’s no hardware to deploy,software to install,or training to conduct.By leveraging your existing network infrastructure,you can merge Internet fax with e-mail in one system – providing the lowest cost of faxing imaginable.

What it is

FaxMailer is an e-mail-based Internet fax service that enables an unlimited number of users to send faxes right from their PC ’s by addressing an e-mail to the recipient ’s fax number.Most types of documents or files can be sent,including MS Office,MS Project,Lotus SmartSuite, Corel,Visio,HTML,RTF,TIFF,PDF,PostScript and more.

Easy to Outsource

All document conversion and delivery is handled within the Mail.com Global Internet Document Delivery (IDD) Network.This makes it easy for IT departments to completely outsource their fax applications and slash messaging costs by freeing the enterprise from purchasing,deploying, and managing its own costly fax infrastructure.

So simple,

you can start faxing immediately Because FaxMailer works with your existing technology, there ’s no client or server software to install or hardware to deploy.Further,your users already know everything they need to start faxing immediately.If they can send an e-mail,they can send a fax.

So efficient,

you can deploy it enterprise-wide You already have the infrastructure you need to deploy desktop faxing enterprise-wide.Simply by registering user e-mail addresses with Mail.com,you can bring up entire workgroups or locations anywhere in the world – in a matter of minutes,not months. ?

How It Works

To send a fax from an e-mail account,simply:

1.Create an e-mail message,which becomes the fax cover sheet.

2.Address the message to the recipient ’s fax number @faxmail.com.

3.Attach the document(s)and hit send.

The e-mail attachment gets delivered as a fax on the recipient ’s fax machine anywhere in the world.The user then receives an e-mail confirming the document ’s delivery.
Free Fax Number
http://www.callwave.com/faxwave/
With FaxWave, you no longer need a dedicated fax line. We give you your very own, private fax number that you can publish on your business cards and stationery. Sending a fax to this number is no different than sending a fax to a standard fax machine. FaxWave automatically routes your faxes to your e-mail inbox as an e-mail attachment that you can view with standard viewing applications. Now you can receive your faxes at the same time that you check your e-mail - which means you can now receive faxes from anywhere you can connect to the Internet!

With FaxWave, you no longer have to use the same line for voice calls and faxes. That means you can stop worrying about whether or not your computer or fax machine was turned on when someone tried to send you a fax. Just like e-mail, FaxWave is always on.

With FaxWave, you won't have to worry about busy signals any more. That's because twenty people could be faxing you at the EXACT SAME MOMENT and you'll receive each and every fax document! With FaxWave, everyone in the company can have their own, PRIVATE fax number - no more worrying about sensitive documents sitting in the public fax machine! You can view FaxWave faxes with Windows Imaging, an application that comes pre-installed on most Windows 95 computers and ALL Windows 98 machines. Best of all, it's FREE!

ICOM/fax to fax
www.brightsys.com

IComFax网络传真服务与同类服务相比，具有费用更低、发送范围更广、效率更高、使用更方便等特点：

  • 费用更低
    与同类产品（如FaxSav）的最低费率相比，普遍较低。
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Webfaxer

WebFaxer工作室

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Tel: (020) 3889 8209 Fax: (020) 3889 8209
E-mail: info@yaha.net

YAHA网络传真系统是广东九方网络系统有限公司与香港中建电讯集团有限公司合作，于2000年正式推出，这项服务融合最新的科技咨询，提供一项崭新的互联网通讯服务。YAHA网络传真系统的全球网络覆盖范围包括美国、香港、英国、亚洲和中国大陆等地，与互联网相连，可以把信息综合储存，并且以经济的途径，把传真、电子邮件及语音信息传送到世界各地。能为国内用户提供完善及时的服务。

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服务范围：美国、香港、英国、亚洲和中国大陆


netmedia

3d.doc
IP-video.doc
Netmedia.doc
Netmedia_Intro.doc
Netmedia_OnlineTV.docx

netmedia authoring

  • 3DDreams.htm
  • 3danywhere.htm
  • 3dcreate.htm
  • 3dexplore.htm
  • 3dmodelswork.htm
  • 3dvista.htm
  • EONReality.htm
  • activeworlds.htm
  • adobe.htm
  • albatross.htm
  • alice.htm
  • amiravis.htm
  • anarkmedia.htm
  • anfyteam.htm
  • atomic3d.htm
  • authoring.htm
  • authoring1.htm
  • authoring2.htm
  • authoring3.htm
  • authoring4.htm
  • autodesk.htm
  • b3d.htm
  • bangspace.htm
  • behere.htm
  • blaxxun.htm
  • burozicht.htm
  • cai.htm
  • cryonetworks.htm
  • cycore.htm
  • cylpan.htm
  • duran.htm
  • eovia.htm
  • eyematic.htm
  • geometra.htm
  • glviewer.htm
  • hypercosm.htm
  • ibm.htm
  • iceriver.htm
  • imoveviewer.htm
  • intervista.htm
  • ipix.htm
  • jausoft.htm
  • marlinstep.htm
  • metacreations.htm
  • metacreations1.htm
  • mgisoft.htm
  • mitsubishi.htm
  • modelworks.htm
  • nemo.htm
  • neo3d.htm
  • octree.htm
  • olivertravel.htm
  • openworlds.htm
  • other.htm
  • others.htm
  • oz.htm
  • panavue.htm
  • panofac.htm
  • parallal.htm
  • pixaround.htm
  • pulse.htm
  • pulse3d.htm
  • sense8.htm
  • sgip.htm
  • shellsinteractive.htm
  • sumea.htm
  • tgs.htm
  • ualberta.htm
  • ulead.htm
  • urstudio.htm
  • vecta3d.htm
  • viewpoint.htm
  • virtual3d.htm
  • viscape.htm
  • visviva.htm
  • vrinteractive.htm
  • wildtangent.htm

netmedia avi

  • 3cx.htm
  • LiveTV.htm
  • accord.htm
  • channel.htm
  • cisco.htm
  • ezenia.htm
  • ibm.htm
  • inetcam.htm
  • ipresenter.htm
  • openvideo.htm
  • optibase.htm
  • oracle.htm
  • quicktime.htm
  • radvision.htm
  • real.htm
  • redspider.htm
  • rhythem.htm
  • sgi.htm
  • smil.htm
  • solution.htm
  • techsummery.htm
  • topskys.htm
  • v2tech.htm
  • vcon.htm
  • videojet.htm
  • vtel.htm

netmedia tech

  • 3dml-tut.htm
  • 3dml.htm
  • directx.htm
  • editor.htm
  • editor1.htm
  • jpeg2000.htm
  • jpeg20002.htm
  • opengl.htm
  • svg.htm
  • tech.htm
  • x3d.htm


3DAnywhere

3DAnywhere Monfort Software Engineering Ltd

VRML 2.0

3DAnywhere is the ultimate tool for building web catalogs and 3D presentation over the Internet FREE DOWNLOAD

    Platforms:
    • PC


3D Create

VRML 1.0

Create a 3D Avatar from any image file. Attach 3D accessories and select from 100 motion files. Includes mesh deformation and 3D Paint.

    Platforms:
    • Windows95


3D Dreams
http://www.doitin3d.com

3DDreams (aka Spike) is a plugin for Director that can be viewed with Shockwave. If you go to a site with Spike content, the plugin downloads automatically.

Lingo as scripting language


3D Exploration

它可以使您浏览最常见的3D图形文件如3D Studio, LightWave, Caligari, Direct X, AutoCAD


3D ModelWORKS
http://www.3dmodelworks.com
3D Viewer
The 3D Viewer allows you to view the 3D models on this site (http://www.3dmodelworks.com) quickly and reliably. By downloading the Viewer, you will be able to see all aspects of a model before purchasing it.


3DVista

3DVista Ltd.
www.3dvista.com
3Dvista Studio V1.7

Create incredible interactive virtual tours by using 3Dvista Studio software, and bring your website to life!

3DVista studio is ideal for any kind of web developer and is perfect for real estate, tourism and corporate use.

100% plug-in-free!

3Dvista Studio is so easy….all it takes is three simple steps….

1.Photography
Take a series of overlapping pictures with any digital camera

2. Stitch
Use 3Dvista Studio to stitch your pictures to create a seamless panorama

3. Present
Publish the panoramas on a webpage or email a postcard with 3Dvista Studio

Developer's Add-ons

Xtra For MacroMedia Director

You can export 3DVista Virtual Tours to MacroMedia Director, using the 3DVista Xtra. Click on the link above to download the free Xtra, and then follow the instructions within.

SmartPanorama Converter

Use the Smart Converter to import panoramas from other stitching programs to 3DVista Studio. Click above to download the free program.


Active Worlds

www.ActiveWorlds.com

World Servers

The Active Worlds Servers series gives you the tools to express your creativity and build your own world with all the freedom of 3D and all the functionality of 2D. Activeworlds.com's unique approach to the web offers developers a host of server configurations. Whether you just need a spot called your own or a showcase for your work, we have a version for you.

All configurations include:

  • Open or restricted access
  • Web address designation for custom content
  • WWW file retrieval for images, sounds, and music
  • Use of the original textures, models, sounds, music and avatars
  • Free registered citizen numbers
  • Newsgroup user support
Universes & Galaxies
Universes and Galaxies
Designed for the business that requires its World(s) stand-alone and separate from the Active Worlds Universe of Worlds. These products give the administrator full control over the Worlds.

Configurable for both Internet and Intranet applications.

All configurations include:

  • All server component software
  • Access to the Activeworlds.com, Inc. content libraries
  • Remote setup support
  • Limited, upgradeable licensing agreement
  • HTML, FAQ, and help documentation
  • Technical support documentation
  • 1 year free upgrades

Galaxervers
UniServers


Adobe
3D Anarchy
www.attitudesoftware.com/, www.worldsonline.com
3d Anarchy technology has been acquired by Adobe Systems.


Albatross

Albatross Design Group, Inc
www.albatrossdesign.com
ADG　Panorama Tools
ADG　Panorama Tools 是一个非常直观的软件，可生成360度网络全景照片，无需插件，HTML或Java编程。这个软件工具具有许多功能如自动缝合，自动融合，网页自动生成，真实圆柱景物和输出图像过滤。这个演示版本如用于非商业用途则完全免费。


Alice
http://www.alice.org

Overview

Alice is a 3D Interactive Graphics Programming Environment for Windows 95/98/NT built by the Stage 3 Research Group at Carnegie Mellon University. The Alice project is a public service to the wider computing and artistic communities; our hope is to make it easy for novices to develop interesting 3D environments and to explore the new medium of interactive 3D graphics. The current version of Alice authoring tool is free to everyone and runs on computers that are commonly available for reasonable prices. Worlds created in Alice can be viewed and interacted with inside of a standard web browser once the Alice plug-in has been installed.

Alice is primarily a scripting and prototyping environment for 3D object behavior, not a 3D modeler; this makes Alice much more like LOGO than AutoCAD. By writing simple scripts, Alice users can control object appearance and behavior, and while the scripts are executing, objects respond to user input via mouse and keyboard.

Alice is not a 3D modeling program, but it does read many common 3D file formats including .DXF and .OBJ formats. Objects can be converted to Alice format from .3DS format using a special 3D Studio Max plug-in. The Alice core distribution includes a large library of textured models. The Alice plug-in does not allow authoring, but does allow viewing of any Alice world.

What is the Alice Plug-in?
If you'd like an easy way of viewing Alice worlds created by others, download and install the Alice plug-in here. The plug-in enables users of Netscape and Microsoft Internet Explorer to view Alice worlds inside their browser.

What Comes With the Alice Authoring Tool?
The Alice Development Environment
A Collection of 3D Objects and Textures
The Alice authoring tool doesn't require any special graphics boards, input devices, or hardware acceleration. All you need to run Alice is a computer running Windows 95/98 or NT 4.0.

What Software Does Alice Use?
The Python Programming Language
Microsoft's Direct-3D Library
Visual Basic

What Do I Need to Run Alice?
Alice doesn't need any special 3D hardware to run, though Alice will take advantage of any 3D board that accelerates Microsoft Direct3D if one is present in your machine.

To run Alice you must have:

Windows 95/98 or NT 4.0
a VGA graphics card capable of high (16 bit) color
If installing on Windows 95/98 you need Microsoft's Direct-3D Library (Direct X).
If installing on Windows NT 4.0 you need Microsoft's Service Pack 3.
In addition, you should have the following:

A Pentium running at 90 Mhz or better
Fast VGA graphics. WRAM is better than VRAM which is better than DRAM.
16 megs of RAM
A Soundblaster-compatible sound card


Amira
www.amiravis.com
Wherever 3-dimensional data sets need to be processed, for example in medicine, biology, and engineering, amira offers fascinating new opportunities.
State-of-the-art visualization techniques allow you to gain detailed insight into your data. Graphics hardware is efficiently utilized to display large data sets at interactive speed.

Powerful automatic and interactive segmentation tools support processing of 3D image data. Innovative, fast, and robust reconstruction algorithms make it easy to create polygonal models from segmented objects.

In addition, true volumetric tetrahedral meshes can be generated, suitable for advanced finite element simulations. Simulation results as well as other data defined on a variety of different grids can be investigated using a large set of powerful visualization methods.

Who uses amira?
R&D groups working with 3D image data, e.g. in biology, medicine, material science, quality control, physics or geophysics.
R&D groups performing numerical simulations like finite element analysis, computational fluid dynamics ,or physics simulations.
R&D groups working in chemistry and biochemistry.


ANARK
http://www.anarkmedia.com/
Emotion 3D
Emotion 3D: Web Edition 1.5 delivers unmatched animation features with a wide variety of special effects, behaviors, and powerful compression technologies. Anark's proprietary AniMesh animation engine gives users of all levels the power to create professional GIF animations, JavaScript rollover buttons, and more for use on Web sites and PowerPoint presentations. Now images can be imported from scanners, digital cameras, and other image capture devices via TWAIN. With a wide range of import and export formats and an intuitive interface, users of all levels can create professional quality animations in seconds.

One-Click Animation Emotion 3D provides you with over 60 behavioral animations, such as rotate, spin, bend, ripple, and more. These animations can be applied to almost any 2D or 3D object to create a virtually unlimited number of unique animations. Emotion 3D uses an advanced proprietary procedural animation technology called AniMesh to wrap a selected animation around your artwork, recreating in seconds what would take a professional 3D animator hours to create. With the click of a button selected effects are automatically applied to all frames of the animation while taking into account pixel-perfect masks.
Easy Wizard-Style Interface

The intuitive wizard-style interface guides users through the program and provides detailed instructions for each step of the process, ensuring that even beginners can quickly create professional, high quality animations. Additionally, the unique menu system allows users to access any portion of the program ensuring maximum flexibility.

Outstanding CompressionEmotion 3D allows users to compress images and animations for use on the Web. This helps to shrink the file size and decrease loading time of finished animations, while still retaining the best image quality.

Expansive Import/Export OptionsEmotion 3D lets you import a wide variety of standard file formats, such as BMP, JPEG, PNG, TIFF, GIF files, 3DS, DirectX, and more. Once you're animation is complete, you can choose from a number of export options, such as Animated GIF, JavaScript Rollover, AVI, PNG, BMP, JPEG, TIFF, WMF, and more.

With Emotion 3D, anyone from a beginner to a professional Web developer can build professional, unique GIF animations and JavaScript buttons in minutes. To create your own professional animations download the fully functional 15-day trial.
Anark Media Platform
The Anark Media Platform allows Web/digital media developers and integrators, ISP's, hosting companies and corporations to create, repurpose and stream interactive television-quality content, while providing the flexibility, control and management that digital media professionals depend on. Anark is the only platform that answers the specific needs of the Web designer/developer as well as the system administrator responsible for setting up and maintaining streaming and HTTP Web servers.

The Anark Media Platform provides a new benchmark for integrated rich media experiences. These software products can be used individually or as a powerful collective solution. This platform consists of Anark Client, Anark Studio and Anark Server.

Anark Studio
Anark Studio is a powerful content authoring solution that integrates 3D and 2D graphics, video, audio, text and data into a streamed, interactive real-time experience using drag-and-drop based effects.

Anark Studio enables developers to author and repurpose content and develop television-quality interactive applications in a layered media environment. Applications include Web sites, distance learning, computer-based training, interactive advertising, IP-based iTV and other immersive interactive applications.
These television-quality presentations can now be delivered over the Web, intranets, kiosks, CD-ROMs and other distribution channels that weren't practical with previous software tools.
Benefits:
Maintain visual depth of content without the need to flatten files or convert 3D objects into vector graphics
Use video as a design element by mapping it onto 3D objects
Apply, preview and create powerful script behaviors through drag-and-drop based effects or create custom behaviors using the power of JavaScript

Anark Server
Anark Server is powerful and efficient server software that enables high-performance streaming of Anark content to Anark Client. Anark Server is designed for enterprise, e-businesses and service providers. It controls the quality of service (QoS) of the integrated media transmissions within an Anark content stream, providing the highest quality end user experience possible in all network conditions.

Anark media can be delivered using existing HTTP Web servers. However, using Anark Server to stream Anark media results in faster, more reliable service, dramatically increasing the quality of an end user's experience.

Benefits:
Allows a user to view and interact with Anark media as it's being delivered
Active Stream Control allows Anark Client to moderate the bit rate and content of a stream while it is being delivered from Anark Server based on a variety of criteria, including end user interactivity
Dramatically improved network efficiency with Multiplexed Streaming allows Anark media to be delivered more efficiently over narrow band connections, while maximizing the broadband experience

Anark Client
Anark Client is a highly advanced free Web browser plug-in that renders interactive integrated Anark media - composed of 3D and 2D graphics, video, audio, text and data - within the end user's browser in real time. Anark Client can also be integrated directly into a Web page containing Flash or HTML content.

Anark Client displays Anark media directly in the end user's browser without the need to open a separate player or additional window. In addition, Anark Client is scalable so the media can be displayed in the entire browser window or a portion of it.
View sample content!
Benefits:
Real-time rendering on the client system yields smaller file size
Faster download time
Increased level of interactivity


Anfy 3D
http://www.anfyteam.com/

Anfy 3D is the fastest interactive 3d renderer with shading available, using Java technology today.

It is both available as shareware program for web masters, and as Anfy3dAPI library for Java(tm) programmers.
You can create your own animations importing from VRML, or using the Anfy 3D Editor, which include Undo/Redo and Boolean operations.


Atomic 3D
http://www.atomic3d.com/
Atomic3D developed highly flexible proprietary technology,which delivers the ability to quickly produce fully lip-synched 2D/3D animation. Our unique, edgy animated content can be produced 4 to 10 times faster and at least two-thirds the cost of conventional methods.

Atomic3D is capable of delivering our animated content in formats such as Bata Sp., Digital Video (DV),
Sequential Image Files, AVI, QuickTime, MPEG, and of course in Atomic3D's own Internet streaming format.


应用产品

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
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常见问题
本站新闻
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基础技术
应用产品
0-9-A-B
C-H
I-O
P-T
U-Z
公司
产品
编辑工具
浏览器/插件
图象插件
其他
详细信息
3DDreams | 3DDreams | details>>>
3DGroove | 3DGroove | details>>>
3dexploration | 3dexploration | details>>>

3dmeanNow

 details>>>
3dmodelswork | 3d viewer | details>>>
3dvista | 3dvista tools | details>>>
active worlds | World Servers | details>>>
Galaxervers
UniServers
Adobe | 3DAnarchy | details>>>
Albatross | ADG　Panorama Tools | details>>>
alice | Alice | details>>>
Alice plugin
Amiravis | Amira | details>>>
Anarkmedia | emotion3d | details>>>
Anark Media Platform
Anark Studio
Anark Server
Anark Client
AnfyTeam | anfy3d | details>>>
atomic3d | atomic3d | details>>>
autodesk | kinetix | details>>>
lightscape
b3d | brilliant | details>>>
b3d Studio Pro

b3d Studio
b3d Exporter
b3d Installer
b3d Projector
Madcap Studios
bangspace | bangspace | details>>>
behere | behere | details>>>
blaxxun | blaxxun3d | details>>>
Virtual Worlds Platform
buro zicht | buro zicht | details>>>


应用产品

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体--3D与虚拟现实技术
基础技术
应用产品
0-9-A-B
C-H
I-O
P-T
U-Z
公司 | 产品 | 编辑工具 | 浏览器/插件 | 图象插件 | 其他 | 详细信息
CAI-SGI | cosmoplayer | details>>>
Caligari | truespace | details>>>

cryo networks
SCS
 details>>>
E-Maginer
SCOL
cyberworld | CYBERWORLD Browser | details>>>
CYBERWORLD Professional Edition
CYBERWORLD Studio Edition
CYBERWORLD's Builder
CYBERWORLD personal products family
cycore | Cult3D Export pulgin | details>>>
Cult3D Designer
Cult3D Viewer pulgin
cylpan | cylpan | details>>>
duran duboi | Mendel 3D | details>>>

EONReality

 EONViewer details>>>
What is EON Studio
What is EON Server
What is EON Immersive
EON SDK
EON Plug-ins

eovia

 amapi details>>>
Eyematic Interfaces | shout3d | details>>>

geometra

 geometra details>>>
GLViewer | GLViewer | details>>>

hypercosm

 hypercosm details>>>


应用产品

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体--3D与虚拟现实技术
基础技术
应用产品
0-9-A-B
C-H
I-O
P-T
U-Z
公司 | 产品 | 编辑工具 | 浏览器/插件 | 图象插件 | 其他 | 详细信息

iceriver

 iceriver details>>>

IBM

 3DGraph details>>>
ImoveViewer | ImoveViewer | details>>>
InterVista | worldviewer | details>>>

ipix

 Rimfire details>>>
iPIX immersive

jausoft

 GL4Java details>>>

jpeg2000

 jpeg2000 details>>>
macromedia
 flash details>>>

marlinstep

 marlinstep details>>>
metacreatoins

canoma

 details>>>
MgiSoft

RealiStudio

 details>>>
PhotoVista
MGIvideowaveIII

Mitsubishi

 schmoozer details>>>

modelworks

sitepad

 details>>>

nemo

 NEMO-RMFPlayer details>>>
NEMO SoundPlayer

neo3d

 neo3D Component Library details>>>
Component
VRML97 / X3D Suite
XML Suite
Spatial Audio
Database Suite
DirectInput
Music-Synch
neo3D Viewer Toolkit
neo3D IDE

octree

 octreeAuthor details>>>
Octree View
TrueSolid

olivertraveller

 olivertraveller details>>>

openworlds

Merchant-WZTM VRML 97 Loader details>>>
OpenWorlds Merchant-SZTMVRML 97 loader
OpenWorlds Horizon-WZTM
OpenWorlds Horizon-NGTM
OpenWorlds Horizon-HGTM

OZ

 :fluid3d details>>>


应用产品

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体--3D与虚拟现实技术
基础技术
应用产品
0-9-A-B
C-H
I-O
P-T
U-Z
公司 | 产品 | 编辑工具 | 浏览器/插件 | 图象插件 | 其他 | 详细信息
panavue | PanaVue Image Assembler | details>>>
ParallelGraphics | Cortona | details>>>
Cortona Software Development Kit
Internet Space Builder
Internet Scene Assembler
Internet Character Animator
Internet Model Optimizer
VrmlPad
Extrusion Editor
pixaround | PixMaker | details>>>
PixScreen
PixScreen PDA Lite
PixScreen WinCE Lite
ptviewer | ptviewer | details>>>
Panorama Tools
PTStitcher
pulse3d | Pulse Player | details>>>
Pulse Creator
Pulse Producer
pulse network | pulse entertainment | details>>>
Sense8 | :worldup | details>>>
Indy3D
WorldToolKit
OpenVRTM
World2World
SGIP | sgigl | details>>>
sgip
shellsinteractive | Shells Server | details>>>
Shells 3D Author
Smoky City Design | panoramafactory | details>>>

sumea
sumea
 details>>>
TGS | OpenInventor | details>>>


应用产品

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体--3D与虚拟现实技术
基础技术
应用产品
0-9-A-B
C-H
I-O
P-T
U-Z
公司 | 产品 | 编辑工具 | 浏览器/插件 | 图象插件 | 其他 | 详细信息

UAlberta
mrtoolkit
 details>>>

ULead
photovista
 details>>>
Ulead Cool 360

Ur Studio

urstudio
 details>>>
GEL

vecta3d
vecta3d
 details>>>

viewpoint
Scenebuilder
details>>>
Mtx2Html
Stream Turning Studio
Viewpoint Media Player
Enhance iPIX Panoramas
Viewpoint 3D Photo Studio
Real3D
cinema4d
metastream

Virtual3D
Virtue3D Optimizer
details>>>

Virtue3D Max Plug-in

Virtue3D Dreamweaver Extension

Virtue3D Player
Virtue3D Room Designer
Virtue3D's SDK
Virtuoso

Virtus
openspace3d
 details>>>
Viscape | Viscape | x | details>>>
e-Visualizer
I3D

visviva
Visviva Authoring Studio
 details>>>
ScriptV

vr360
vr360
 details>>>
VR Interactive | Surround Photo V2.0 | details>>>

wild tangent

Web Driver 2.0 SDK Full
details>>>
Web Driver 2.0 SDK Base
Web Driver 2.0 Training Package
Multiplayer 1.0 Toolkit
WTStudio Beta 4
3ds Max Exporter 2.1
Maya Exporter 1.1
WildCompress
Packager
Web Driver Media Viewer
MapStreamTM
<


AutoDesk

AutoDesk, LightScape, Discreet, Kinetix...
Lightscape VRML
Lightscape是有名的建筑和装修动画制作软件公司，这里有制作相当精良室内建筑装修的VRML模型。其中不仅有逼真的材质，也有各种灯光效果。是很值得一看和下载的网站。 http://www.lightscape.com/VRML/, http://www.autodesk.com/
Kinetix
动画制作软件3DS 和3D MAX就是该公司的产品。现在的 3D MAX 2.0就支持VRML 2.0标准。它支持符合VRML 2.0标准的wrl文件的输出。使用3D MAX您就可以制作VRML模型。 http://www.ktx.com/ , http://www.discreet.com


B3D

Brilliant Digital Entertainment (B3D)

www.multipathmovies.com/html/developer/index.html

www.b3d.com

http://www.brilliantdigital.com

b3d Studio is the leading editing package for internet-delivered 3D animations. It collects animation, audio, gestures, effects and interactivity, all together in one scene timeline.

You can create multiscene, multipath movies – including 3D banner ads, web videos, multi-episode web movies, and CD-ROM training.

b3d Studio gives you compression, streaming, and caching options that optimize your movie for internet delivery. People view the b3d files in the free, downloadable b3d Projector.

b3d Studio Pro
b3d Studio Pro offers everything b3d Studio does, and more. With it you can run multiple simultaneous users and get all the teamwork and productivity benefits of networked creation and layup. Three seats, ready to use. And ready to produce professional 3D content.

You can rely on b3d Studio Pro to manage your users and file access ?so you can manage the project instead of letting it manage you.

network for better work. every time. Reliable. On time. It抯 what you want for big projects. Proven on long-run webisodes like Xena and Superman, b3d Studio Pro allows big teams to work together without version and control issues.

And without worrying about what models are current, or whether the software is going to hold you up. Studio Pro does the job.
reuse and share your resources

b3d Studio抯 unique library system lets you reuse your resources卬ow with b3d Studio Pro, you can also have controlled team access to bitmap, sound, text, model, and scene resources.

Reuse your work, squash your files, improve collaboration and productivity卆nd get things done cheaper and faster.

video and b3d from one laid up file

Multiuser and multi-output. With Studio抯 unique model scalability, you can layup and animate your scenes once, then output multiple versions.

Use low-polygon models for your internet streaming, and high-res for made-for-TV versions, and do it all from the one b3d project.
threesomes are cheap Buy the three seats in b3d Studio Pro and save $490. That抯 half the cost of a single b3d Studio seat.

You know you抮e going to use more than one copy, so why put it off. Save the money now, and use it for something else.

b3d Exporter
b3d Exporter is a fast and easy way to convert your 3ds max? and Maya animations into b3d format – a format ready to play in any freely available b3d Projector.

Using a straightforward plug-in export dialog, you can specify what object and compression features you want, and then click a button.

And your animation is ready for the web.

It’s the quick way to create anything from standalone movies to 3D banner ads and web videos.

b3d Installer
A one-click, smart install in-browser, with no virus or trojan risk. No leaving to get the plugin. Good look. High security. Small and update-only downloads. Why bother with anything else?

b3d Projector
The b3d Projector is a free viewer that plays the b3d animations created through b3d Exporter and b3d Studio.

Available as a plug-in for Internet Explorer or Netscape Navigator, or as a self-contained installation for CD distribution, the b3d Projector plays b3d files streamed over the Internet or distributed on CD-ROM. Your movies will stand out with:

full screen playback
1024x768 or greater resolution
24bit color
stereo sound
multi-language and multi-rating support
interactive branching.

Madcap Studios
Madcap Studios (located in Sydney, Australia), performs optical motion capture for 3D animation, across a range of animation projects. Specializing in creating motion capture for use with 3d studio max, their services also extend to include other popular animation packages such as Maya, Softimage, and Lightwave. With one of the largest capture floors in the world, Madcap Studios' state-of-the-art technology allows for faster and more complex captures including fight scenes, dramatic performances, medical analysis, gymnastics and much, much more.


BangSpace
--http://this.is/bang/-

Bang is an Open Source 3D MOO game engine with support for 3D virtual worlds and avatars. It is built using Java3D, Jini and IP-Multicasting. Enables persistent multi-user community.

Bang features multi-user chat, voice recognition and navigation, object authoring and exchange.

Content can be written using VRML97 and/or native Java3D. Anybody can write plug-ins and user interface features to customize their client experience.


Behere

www.Behere.com
http://www.Behere.com
The Be Here TotalView Broadcast System offers directors of sports and other television events a unique and compelling technology with the allure of both cost-savings and innovation. With the Be Here TotalView Broadcast System, the camera “sees” and records everything; the broadcasters’ “cameraman” can be everywhere at once. On instant replay, any portion of the navigable view from the Be Here Totalview Broadcast System can be culled out to cover action that was initially missed in the live coverage. This presents the broadcaster with a unique opportunity: nothing is ever missed by the camera. Multiple fields of view can be chosen retrospectively, and remotely -- from the control booth or the broadcast center. This revolutionary advance also offers programmers the opportunity to develop unparalleled interactive library content. The system provides standard SDI-formatted, NTSC quality output from every "virtual camera" view.

With the rollout of advanced television set-top box equipment, Be Here's TotalView navigable content technology has the potential to allow home viewers to independently control an on-screen view of up to 360o via remote control. As interactive television technology standards emerge, Be Here Technologies will continue to develop and tailor products and services to help its broadcast and interactive clients achieve their goals.


Blaxxun

Blaxxun Interactive
http://www.blaxxun.com
blaxxun x3d Blaxxunx3d的三维制作软件
blaxxun interactive offers you cutting edge chat technology and award-winning 3D viewers.
blaxxun3D is a small Java-applet which displays three dimensional content on the Internet. As such, it is platform independent and easy to integrate into any website. blaxxun3D is automatically loaded for the visitor and requires neither an extra plug-in nor separate installation.
blaxxun Contact is the free client product with which users can interact with internet multimedia communication applications such as virtual stores, 3D chat rooms, online cities, interest communities, virtual shareholder meetings, and online events.
Virtual Worlds Platform 5.1

We offer the blaxxun Virtual Worlds Platform in 4 modular product packages. You choose the customized solution which best suits your business model and budget.

Basic Community

Basic Community enables the implementation of a complete and stable Community on the Internet. In particular: Member Management Places Profile Management Communication - Synchronous Communication - Asynchronous Collaboration

Advanced Community

Advanced Community includes Basic Community (above) and, in addition, offers our complete suite of features for text-based Communities (HTML, Java): Basic Community Interest Clubs Personal Homes Objects Agents Agent API Server API

Basic Virtual World

Basic Virtual World consists of Basic Community (above) and the additional possibility of offering these features in a 3D environment: Basic Community 3D Avatars 3D Places Audio-/Video-Streaming Text-to-Speech

Advanced Virtual World

Advanced Virtual World comprises all packages above but also possesses the full performance range of Virtual Worlds Platform 5.1: Advanced Community Basic Virtual World 3D Clubs 3D Personal Homes 3D Objects 3D Agents Detailed information about the Virtual Worlds Platform 5.1 including white papers and brochures can be downloaded as a pdf. If you are interested in prices, please fill out our contact form.


Buro Zicht
--http://www.zicht.nl/ --
has a demo of a 3D anaglyph viewer (that you view with red-green glasses). No idea about the underlying technology or when it might be for sale.


Cosmo Player

CAI-SGI
Cosmo Player： SGI：http://www.cai.com/cosmo/-这是一家很有名的3D图形公司，它参与并领导了VRML标准的制定。这里有Cosmo Player可以下载，也有wrl文件的制作工具。 http://www.sgi/com 、 http://vrml.sgi.com/


CryoNetworks
by Cryo Networks -http://techno.cryonetworks.com/Main.htm
SCS
SCS is professional web creation software ideal for building graphically-rich multimedia virtual worlds where multi-user real time interaction is a reality. With SCS, the sky’s the limit. Design your next 3D environment, chat zone or business interface simply by linking various available features chosen from more than 100 ready-made modules.
E-Maginer
E-Maginer is an easy-to-use website toolkit for generating your own 3D worlds using up to 14 different pre-loaded 3D virtual universes such as Business, Sport, and Animation. Invite online users to chat, play games, shop, or simply listen to music.
SCOL

Fast and extremely light, SCOL technology permits the creation of multi-user sites with very different appearances. In a SCOL site, you can meet and interact directly with the other visitors. This site can be accessed in different formats: real time 3D (video game quality), a rich 2D interface, sound, streaming video and even telephone (GSM quality).
Multi-platform itself (Windows NT, UNIX, Linux and shortly Mac), SCOL also interfaces with the existing technology such as SQL, JAVA, HTML, or C.

In the current Internet applications, such as electronic mail and the Web, the method of communication is broadcasting. The basic concept is that of the 'document': the server stores a large number of documents and restricts itself to answering clients' requests and transmitting documents in response to requests. This method of communication is unsuitable for sites where visitors can meet and interact; for this type of site, the idea of a document no longer makes any sense.

SCOL therefore proposes a different approach, in which the server and the client communicate in a symmetrical fashion and send messages whenever necessary, and not solely to request information. The concept of a document is succeeded by one of the event. The sole difference between client and server is in the initiation of the connection, and it is the client who initiates the communication. As with the telephone, there is the caller and the party called, but once the contact is established, the communication is symmetrical. Cryonetworks has the goal of establishing SCOL as the multimedia applications standard for multi-users.


Cycore
www.cult3d.com, www.cycore.com/ , www.worldof3d.com

三维网络技术最主要的三个发展方向是电子商务（包括B2B和B2C),电子化教育和网络娱乐。Cult3D 是一种崭新 3D 网络技术，它让你把高质量和快速度的交互的实时的物体送到所有的因特网用户手上，是全新的Web3D技術，一个跨平台的3D引擎，其目的是在网页上建立互动的3D物件。利用Cult3D技術可以让网页设计师制作出3D立体的产品，利用Cult3D可以以视觉的方式呈現不同的事件和功能的互动性，並且放置在网页中。可以旋转，放大，縮小，体现真实的物体属性。

Cult3D　作为一种电子商务方案，让你创造出能随时随地在网上触摸，感觉并且试一试的产品，甚至和其他人一起玩令人激动的网上游戏。三维网络技术使用户可以非常真实的体验设计，定制和量化自己的产品。通过Cult3d的在线3D技术，使电子商务，企业新产品等实现更生动的在线推广，也使网络开发者和3D动画师们都可以利用这种深层的技术来更好的完成他们的工作。
CULT3D 制作工具

＊ 3DMeNow Lite----------三维头像在线演示，在3DMeNow中用两张照片即可做一个完全立体的三维头像！

＊ CULT3D DesignerPack V5.2 ----------　CULT3D的设计包，里面包含了主要的设计软件--Designer v5.2、浏览CULT3D的Netscape、IE和Acrobat的插件。用Designer对.c3d文件进行互动设计，最后出Internet的.co文件。

CULT3D 3DMaxPlugs ----------　在3DMax中制作三维模型输出为CULT3D的.c3d文件所必需的插件，安装时选择相应的3DMax版本号。
Cult3D制作步骤：

Cult技术是一个纯软件的环境的引擎，也就是说你不需要任何的三维加速卡就可以表现完美的网络三维技术。Cult3D技术支持 ActiveX和Adobe的 Arcobat 的PDF文件格式，只需要安装一个插件就可以在包括 Marcosoft的Powerpoint、以及Arcobat 等软件中应用Cult3D,享受Cult3D带给你的三维的感受！新版本的Cult3D View引擎更比原来的执行速度上提高了到原来的150%，而且增加了对 Nvidia 系列显卡三维加速的硬件支持。

Cult3D包括三个组成部分：

1． Cult3D Export pulgin: 这个插件是针对 3DMAX、MAYA等三维软件的，你可以通过这个插件将3D模型输出成 Cult3D Design的C3D格式。

2． Cult3D Designer: 这主要是Cult3D的制作工具，你可以通过他，将你的模型加上，旋转、缩放、移动等交互性的特性。

3． Cult3D Viewer pulgin:这是一个针对其他软件的插件，你必须安装他以后才可以在 IE、Netscape 、Arcobat 、Office等软件中看到Cult3d的模型。

制作你的第一个Cult3D的作品:

1． 首先你可以使用一个你以前做的三维模型道入3DMAX中。这里你要记住的是，因为最后的作品是要用来在网络上浏览，你必须在模型的细节、真实度上下点工夫，尽量用最经济的面来做模型，以控制好文件的大小，太多的面不仅会加长网络传送的时间，更是对浏览者机器的考验，因为Cult3D的模型是在客户机上即时渲染的。一般说来一个30000个面的模型加上贴图在塞扬550 128MB内存的机器上可以很流畅的浏览。

2． 第二步将你的模型从3DMAX里导出，安装完Cult3D Export pulgin以后在MAX的Export里将多一个 .c3d的文件格式。选择保存后会出来一个对话框，在这里你可以预览模型，还有很多输出的参数，可以调整模型材质的压缩比例。

3． 第三步打开Cult3D Design 将你刚才保存的文件导入，这里主要工作是将你的模型加入互动效果，事件和声音。Cult3D Design 已经将很多基本的命令模块化，就算你不懂编程语言你也可以很方便的制作你想要的效果，如果你精通JAVA的话还可以自己编写脚本。在这里你可以将文件保存成.c3p的格式，以便以后的修改。

4． 最后一步，导出Internet文件，在Cult3D Design的file下面选择 Save Internet file 然后就是选择压缩方式了，在这里你何以给模型的每一个物件，贴图和材质以及声音进行压缩，有不同的压缩方式给你选择，但是记住了不要压缩的太厉害，这样会导致模型的面破损和贴图的位置偏移。一般说来一个30000个面左右的模型加上简单的贴图，最后的文件大小在100K左右。 这样一个Cult3D的作品就诞生了!

在WEB上发布Cult3d作品:

1)Add a new mime-type on your webserver Adding the mime-type is necessary for any plug-in or fileformat that isn't standard and default for the server.

The mime-type for Cult3D is:

application/x-cult3d-object and the default suffix is .co

2)代码式，进行以下步骤： 在网页中增加一段特殊的代码，把Cult3D的文件嵌入到页面中

3)插件式： 你可以下载CULT3D官方网站公布的Dreamweaver Object插件，利用它你可以很方便地把CULT3D作品插到你的网页上：

国内合作伙伴或代理

  • http://pingsoft.com.cn/
  • http://www.dspace.com.cn
  • http://www.bamboonetworks.com
  • http://www.all-v.com/
  • http://www.5dmedia.com/


Cylpan

Cylpan 360
Co-written by Terry Thrift of Thrift.com, and incorporating portions of nemeng java code from the now discontinued nemMap2 and panoScrl2, CylPan allows you to play 360° or partial panoramic images with full cylindrical distortion correction, sophisticated hotspot & cursor support and browser frame targetting all packed into a single class/jar file.

Please note that CylPan is a player applet only, you will have to first create the 360° or partial panoramic image yourself using other 3rd party software!


Duran

Duran Duboi
www.duran-duboi.com
www.mendel3d.com
Con?ue et développée par le groupe Duran Duboi, leader européen dans la post-production pour le cinéma et la télévision, Mendel 3D est une technologie révolutionnaire dans le domaine de l'animation d'objets ou de personnages 3D en temps réel.

La technologie Mendel 3D est révolutionnaire à deux titres :

Issue de la théorie des splines inventée par le mathématicien francais Pierre Bézier, elle permet de créer des objets de 10 à 100 fois plus légers - donc plus faciles à animer et plus rapides à afficher - que ceux générés par les solutions 3D traditionnelles.

De plus, les fonctionnalités dynamiques propres à Mendel 3D confèrent à ces objets virtuels - y compris les plus complexes - un rendu optimal, très proche de la réalité.

Fort de cette technologie et de ses nombreuses applications, le groupe Duran Duboi, à travers Mendel 3D, bénéficie d'un avantage concurrentiel dans les métiers du cinéma et de la télévision pour lesquels des outils spécifiques sont créés.
Parallèlement à ces métiers, le groupe Duran Duboi a développé des outils pour le marché de l’Internet.

LES AVANTAGES DE MENDEL 3D :

la première technologie 3D dédiée au vivant
les fichiers 3D les plus légers du monde
Un moteur gérant des surfaces de type “courbe” ou de type “polygonal”
Un contr?le temps réel de la morphologie des objets
Création et contr?le en temps réel des animations
Des objets 3D avec un caractère dynamique et naturel en temps réel


eonreality
http://www.eonreality.com/
EON Viewer
What is EON Studio?

EON Studio is a complete development tool that allows users of all experience levels to build complete, interactive simulations quickly and easily with no programming experience required.

Whether you create 3D Applications for architecture, marketing or training, EON Studio provides a unique range of benefits and functionality making it the best choice.
What is EON Server?

EON Server is a modular server based solution for distribution of EON 3D content over the web as well as managing large 3D product repositories. Two modules in this product suite EON Dynamic Load and EON Track are now available.

EON Server can be used on any type of web-server very similar to e.g. how regular html pages or gif files are served up. The difference with EON Server is that EON 3D content is served up rather than html pages.

Objects and/or components are streamed into the scene, allowing extremely small file-size and full interactivity from the first downloaded component. The parts can be launched automatically in three different ways using EON Server. One is through dynamic load, another is by triggering any of EON Studio's sensors within the 3D environment (such as a click sensor or a proximity sensor). A third alternative is actually to load the objects through an html page by clicking on a button, text or image link from a 2D catalog e.g.

The software application modules for EON Server include:

EON Dynamic Load allows for dynamically loading and unloading of EON objects over the Internet into a 3D environment such as a showroom. The virtual products are located in a repository of objects on a web server allowing for easy access. An EON object can contain all aspects of EON features including 3D models, behavior, textures, interactivity, audio, video etc. Dynamic Load takes advantage of existing features within EON Studio that allows for compact file size and fast distribution. This approach allows end users to browse through a product catalog walking through the showroom getting detailed information about the products and actually see how the products work and interact with them. In addition, the initial download size/time is kept very small allowing users to start interacting instantaneously.

EON Track is part of the EON Server solution and provides users the ability to track user interaction in an EON application and store the information in a database. The database can be accessed via a web interface in order to get up-to-date information anytime. Tracked events are set up using the GUI of EON Studio. Key benefits for EON Track are found within e.g. E-commerce applications where statistical marketing data is gathered for examination or within E-learning where critical learning data is logged for student evaluation purposes.
Application areas for EON Server include:

E-commerce/marketing , dynamic loading of product catalogues
E-learning/training, dynamic loading of training materials/objects
Architecture, collaborative design reviews and presentations with dynamic loading of e.g. rooms
Maintenance/support, e.g. dynamic access of 3D maintenance manuals
Education and Research

What is EON Immersive?

EON Immersive is an extension of EON Studio and includes features for interfacing with advanced display and integrated Virtual Reality systems that include Concave Reality System?and Immersive Reality System? (Read more about these systems in the Integrated Systems section >>)

EON SDK

Although EON Studio offers a wide range of features, sometimes there are unique requirements for more functionality. EON SDK, our most versatile tool, extends all the standard features of EON Studio and EON Immersive (sold separately), by adding the ability to create new nodes, modules, and applications for use with EON Applications.

EON nodes that are action-related, or initiate the operation of other nodes, are referred to as agents. EON SDK provides the advanced development environment required for the creation of EON agents and modules. This is the same development tool that EON Reality, Inc. developers use for creating EON's standard agents and modules.

EON SDK incorporates the programming power and versatility of Microsoft Visual C++, and requires a working knowledge of this language. EON SDK adds two wizards to Visual C++, several base classes to connect your code to the EON framework, and a number of libraries.

The EON modules you create are independent programs that add new functionality to EON. With EON SDK, third-party developers can create and license protect specialized EON plug-in modules.
EON Plug-ins

On this site you can find out more about different Plug-ins from EON Reality.

EON FastView
A complete building or a single object can be quickly brought up inside ArchiCAD using the EON FastView Add-On real-time viewing environment. Camera views or walkthroughs can be saved for later sharing or modification in real-time.

EonXtra
EonXtra is a plug-in for Macromedia Director that enables you to embed and run interactive EON Applications in a Director application.


Eovia
http://www.eovia.com/, http://perso.club-internet.fr/odrion/tutorim/eindex3.htm
Amapi 3D has been developed to enable graphic artists, designers and multimedia producers to create 3D models. The software supports functions like polymesh surface distortion, keyframe NURBS and much more.

In addition to the new Shockwave3D and Flash, Amapi 3D 6.1 also supports the ability to publish content using its own 3Space web 3D format, which provides the ability to create behavior normally found in 3D game engines, like animated particle effects, explosions, gravity and collisions. Eovia noted that Amapi 3D 6.1 also features some bug fixes.

The software is available for Mac OS and Windows, and carries a suggested retail price of US$399. Sidegrades are available for owners of Carrara, Carrara Studio, Ray Dream and Infini-D, for $199. Visit the download page to get the 6.1 upgrade now.

Carrara
Carrara Studio is the complete, extensible and affordable 3D solution for modeling, animation, rendering, and special effects. Optimized for blazing performance, Carrara Studio enables full real time scene manipulation and high-quality 3D rendering up to eleven times faster than its predecessors. With an elegant, intuitive and uncluttered user interface, Carrara Studio delivers professional results without a professional learning curve. Whether experienced in 3D or not, Carrara Studio is the clear choice for every digital artist, web designer and multimedia producer.
webXport, a Carrara extension for converting Carrara Studio scenes to Viewpoint Experience Technology (VET), the popular rich media platform used to display 3D graphics over the Web.

The Eovia webXport provides Carrara users with a new and interactive way to publish textured and animated 3D scenes to one of the highest quality 3D web formats available today. The Eovia webXport extension makes Carrara Studio the best-value web 3D authoring solution for the Macintosh and Windows.

And best of all, this powerful extension is free for all Carrara users.

Viewpoint Experience Technology
The VET format for web 3D displays streaming, real-time, interactive views with a quality comparable to raytracing, complete with transparency, textures, light maps and animation. The Viewpoint Media Player is a free browser plug-in which self-installs when downloaded from the Viewpoint website, automatically updating itself with further enhancements when they are needed to show a VET file.
Ray Dream
Infini-D

Short Amapi tutorial

Basics :

the interface

At first, you will have to find the appropriate tools in the three main toolboxes.

These toolboxes are located at the upper right corner of your screen. They appear when you move the cursor against the right side of the screen.

The Amapi 4 new interface allows you to toggle between the Amapi original "workshop" interface to another one, a floating tools palette, that looks like more ordinary softwares.

I prefer the "workshop" interface which is the most intuitive and faster.

The Construction Tools

The first one is the construction tools palette, which use is to set the basis of our model.

The Modeling Tools

The second one is the modeling tools palette. We will use it to modify, adjust our model.

The Assembling Tools

The third one is the assembling tools palette. We will use it to place our objects into the scene, control their scale, their number...

The Control Panel

The Control Panel appears at the bottom of the screen. It can appears only when the mouse pointer comes to the botom of the screen or always diplayed, depending your interface preferences choice. It will be useful, while the modeling to zoom on the model, hide the unused shapes or unhide them when necessary.

Amapi's "magic" keys and shortcuts

Space Bar

It has many toggling effects.

The Duplicate, Hull surface or Swep tools, for instance, will offer different solutions if you hit the space bar.

With Single Axis Scale Tool, you can lock your modifications onto one axis.

Arrow keys

Use them to adjust the view incrementally. The left arrow shifts the view toward the left, the up arrow shifts the view up, and so on.

To achieve a panning effect, use the control key with the arrows.

Number Pad :

5 : Top view

2, 4, 6 : front view, left view, right view

8: rear view

+, - allows you to increase or decrease the accuracy of an action (with Smoothin tool for example)

3 : zoom in

. : zoom out

Option key (for Mac) , control key (for PC) :

It allows you to access sub-tools that are available with the currently selected tool. For example, when the Wand Tool is showing, the selection tools (Lasso and Bull's Eye) can be accessed using the Option Key.

shift

If you hold the shift key and move the cursor around, the cursor will snap to the nearest point.

Delete :

It allows you to ... delete the current object.

Hit the delete key at any time to undo your last action when you are inside a tool.

Tab :

Use the tab key to access data boxes that appear at the lower corner of the screen.


Eyematic

Eyematic Interfaces Incorporated
http://www.shout3d.com
Shout3D is an altogether new approach to online visualization and immersion that lets any standard web browser display interactive 3D graphics without the need for extra plugins or downloads. That means users don't have to know a single thing about the technology or how it got there.


geometra
http://www.geometra-3d.com/
由照片直接生成VRML文件


GLViwer

GLView.exe ver 6.0b VRML Browser与3D File Viewer


Hypercosm
http://www.hypercosm.com/
Server License

A Hypercosm Server License authorizes and enables a website to host Hypercosm content. We charge an annual license fee based on your number of concurrent users and product features. We can help you choose a model suited to your specific needs.

To find out more about Hypercosm Server Licenses and how we can put one to work for you, contact us at license@hypercosm.com.
Developer Toolkit

Using Hypercosm's Developer Toolkit, you will be able to bring your own 3D visions to life on the Web. You can use Hypercosm translators to convert existing 3D models into super-small Hypercosm applets, or you can use the Hypercosm Studio development environment to develop and customize new graphics.

Hypercosm not only provides you with the software tools you need to produce highly-interactive Hypercosm content, but we also provide the training you or your developers need to get up-to-speed with Hypercosm technology. In addition, Hypercosm provides a full set of manuals, tutorials, and a web site dedicated to applet developers, ensuring that help in applet production is never hard to find.


IBM
http://www.alphaworks.ibm.com/tech/
3D Graph
The 3DGraph framework provides a C++ library that can be used to display and manipulate large graphs in 3D.
The large number of nodes in a graph, and the complex relationships of large systems that a graph can represent, create real problems when trying to understand and visualize by existing 2D tools. To help overcome these difficulties, 3DGraph introduces a graph management framework for 3D visualization and interactions for C++. The 3DGraph framework provides a C++ library that can be used to display and manipulate large graphs in 3D. The framework is composed of three major modules: a graph management module, a 3D visualization module, and a layout module.
As a basis for a graphic user interface that displays graphs, the framework also serves as a source of navigational tools useful for zooming moving, or rotating. The user of the 3DGraph framework creates graphs composed of edges and nodes that describe complex relations such as inheritance and dependency of classes within an OO system. These relations are visualized by the 3DGraph framework. The framework creates a visual representation of the graph using novel 3D graph layout algorithms. The framework supports a set of 3D navigation tools, abstraction capabilities, filtering, 3D graph editing and animation.


iceriver

http://www.iceriver.net/360

iCERiVER Panoramic，它包含五大特点：

   不需要浏览器插件；
不需要服务器端程序支持，适合任意平台；
可以任意定制界面；
可以控制起始状态；
可以切换显示多个场景。


IMoveViewer

ImoveViewer 全景浏览器


InterVista
WorldView 2.1(12MB)VRML浏览器


ipix

http://www.ipix.com
Rimfire's visual content infrastructure manages user-supplied media for today's most popular Web sites including
eBay.com REALTOR.com MakeoverStudio.com and more. Rimfire is a completely outsourced end-to-end solution that collects, transforms, and deploys millions of media objects in just seconds.
iPIX's patented technology creates immersive images by combining two 185film or digital photographs taken with a fisheye lens into one 360by 360spherical image. iPIX software automatically compensates for any minor error in camera placement and corrects the distortion inherent in these photographs. The resulting immersive image can be viewed in any direction, up-down, left-right, and horizon to horizon. The viewer can easily navigate the image by moving a cursor inside the image or using the iPIX navigation bar.

iPIX immersive technology, alone or combined with other digital media such as audio, video and animation, offers many compelling applications for many markets including real estate, e-commerce, travel and hospitality, entertainment and security and observation.


Jausoft
http://www.jausoft.com/
GL4Java
OpenGLTMfor JavaTM (abbrev.: GL4Java) maps the complete OpenGLTM 1.2 API and the complete GLU 1.2 API to JavaTM and integrates all managment functions, while using the JavaTM-Native-Interface (JNI) and the JDirect-Interface of MSTM-JVM !
GL4Java uses the native OpenGLTM library of the underlying operating System !


marlinstep
可用扫描仪生成三维物体。


MetaCreations

Canoma

http://www.metacreations.com
美国MetaCreations公司3D简易建模速成工具，可直接由二维图片导出三维效果。(不支持圆型)

Canoma 1.0

With Canoma you can create photorealistic 3D models from scanned or digital photographs quickly and without extensive 3D skills. Using a push-pin metaphor, Canoma lets you attach 3D, wireframe primitives on top of objects in a two-dimensional image (such as a scanned photograph, piece of stock photography, or even a digital drawing or painting).

With the click of a button, Canoma renders a 3D image by wrapping the two-dimensional surfaces around the three-dimensional primitives. You can either mirror textures to fill in the "invisible" sides of objects, or use multiple photographs of a single scene.

This method of modeling allows you to create realistic 3D models without any previous 3D modeling experience. Create furniture, interiors, buildings or whole city blocks, and even interactively walk through models or create animations.

Visit MiniDisco.com - E-commerce using MetaStream models created entirely in Canoma! (Requires MetaStream plug-in to view models.)

See how Canoma was used to recreate downtown Phoenix, Arizona!

Check out a Canoma Demo video presented by David Roberts from Siggraph 99' (courtesy of Digital Media Net- requires RealPlayer).
Patches! Updates to Canoma are in. Download them today!

Ground-breaking 3D Technology
Canoma is the first product that will allow 2D graphic artists and Web designers to create photo-realistic 3D content from their flat images. This opens up 3D as a medium to designers who have stayed in the realm of 2D graphics.

Flexible & powerful
Canoma can take any 2D digital source image as input, whether from a digital camera, historical materials, artwork, or hand drawn sketches. No need for specialized equipment, studio setup, calibration or "markers" on objects.

Web ready
Canoma can generate 3D models in MetaStream format and can also write VRML2 output.

Integrates & leverages existing workflows
Users can apply their MetaCreations Painter or Adobe PhotoShop skills to prepare and retouch photographs and textures. Canoma supports workflow for several types of media targets:

The Web: Import images, make models, export to MetaStream or VRML2 to post on the Web; create 3D models, change perspective, embed links on objects and output to html for interactive fly-throughs.

2D: In some cases, the output is another 2D image, usually a retouched source image where Canoma was used to "undo" the perspective on objects and allow pixel retouching in head-on views.

Online catalog customers
can preview “hard goods” such as furniture or appliances, enabling enhanced user interaction with products through photorealistic 3D models and animations.

Travel, tourism, and real estate
web sites can provide 3D previews of the destinations and properties.

Graphic designers
can modify packaging, designs, and environments.

Advertising agencies
can create comps of billboards, ads on buses, etc. in perspective.

3D artists
can quickly create photorealistic "clip objects."

Architects, urban planners, and property developers
can interactively preview the urban context in which their new building is placed.

Interior designers
can quickly generate "what if" scenarios, changing carpets, wall colors, tiles and furniture to easily create 3D interiors of buildings for interactive walk-throughs.

Game developers
and level builders can create low polygon count 3D models and environments with realistic textures, suitable for rendering in real time on today′s hardware.

Canoma Imports:

2D Files
BMP (Win only)
GIF (w/alpha channel)
JPG
PICT (Mac only)
PNG (w/alpha channel)
PSD (w/alpha channel)
TIFF (w/alpha channel)
Canoma Exports:

2D Files
BMP (Win only)
PICT (Mac only)
PNG
PSD
TIFF
Animation

QuickTime
Sequential BMP (PC)
Sequential PICT (Mac)

3D Files
AutoCAD (.DXF)
MetaStream (.MTS)
Poser Prop (.PP2)
Truespace (.SCN)
VRML2 (.WRL)
Wavefront (.OBJ)

Windows:

Pentium Processor
Windows 95/98/NT4.0
32MB Free RAM (48+ Recommended)
50MB HD Space for Processing
16 Bit Color (24 Bit Recommended)
CD-ROM Drive (For Install)
Macintosh:

Power Macintosh
Mac OS 8.0 or Higher
32MB Free RAM (48+ Recommended)
50MB HD Space for Processing
16 Bit Color (24 Bit Recommended)
CD-ROM Drive (For Install)


metacreations

Canoma

http://www.metacreations.com

Canoma 1.0

With Canoma you can create photorealistic 3D models from scanned or digital photographs quickly and without extensive 3D skills. Using a push-pin metaphor, Canoma lets you attach 3D, wireframe primitives on top of objects in a two-dimensional image (such as a scanned photograph, piece of stock photography, or even a digital drawing or painting).

With the click of a button, Canoma renders a 3D image by wrapping the two-dimensional surfaces around the three-dimensional primitives. You can either mirror textures to fill in the "invisible" sides of objects, or use multiple photographs of a single scene.

This method of modeling allows you to create realistic 3D models without any previous 3D modeling experience. Create furniture, interiors, buildings or whole city blocks, and even interactively walk through models or create animations.

Visit MiniDisco.com - E-commerce using MetaStream models created entirely in Canoma! (Requires MetaStream plug-in to view models.)

See how Canoma was used to recreate downtown Phoenix, Arizona!

Check out a Canoma Demo video presented by David Roberts from Siggraph 99' (courtesy of Digital Media Net- requires RealPlayer).
Patches! Updates to Canoma are in. Download them today!

Ground-breaking 3D Technology
Canoma is the first product that will allow 2D graphic artists and Web designers to create photo-realistic 3D content from their flat images. This opens up 3D as a medium to designers who have stayed in the realm of 2D graphics.

Flexible & powerful
Canoma can take any 2D digital source image as input, whether from a digital camera, historical materials, artwork, or hand drawn sketches. No need for specialized equipment, studio setup, calibration or "markers" on objects.

Web ready
Canoma can generate 3D models in MetaStream format and can also write VRML2 output.

Integrates & leverages existing workflows
Users can apply their MetaCreations Painter or Adobe PhotoShop skills to prepare and retouch photographs and textures. Canoma supports workflow for several types of media targets:

The Web: Import images, make models, export to MetaStream or VRML2 to post on the Web; create 3D models, change perspective, embed links on objects and output to html for interactive fly-throughs.

2D: In some cases, the output is another 2D image, usually a retouched source image where Canoma was used to "undo" the perspective on objects and allow pixel retouching in head-on views.

Online catalog customers
can preview “hard goods” such as furniture or appliances, enabling enhanced user interaction with products through photorealistic 3D models and animations.

Travel, tourism, and real estate
web sites can provide 3D previews of the destinations and properties.

Graphic designers
can modify packaging, designs, and environments.

Advertising agencies
can create comps of billboards, ads on buses, etc. in perspective.

3D artists
can quickly create photorealistic "clip objects."

Architects, urban planners, and property developers
can interactively preview the urban context in which their new building is placed.

Interior designers
can quickly generate "what if" scenarios, changing carpets, wall colors, tiles and furniture to easily create 3D interiors of buildings for interactive walk-throughs.

Game developers
and level builders can create low polygon count 3D models and environments with realistic textures, suitable for rendering in real time on today′s hardware.

Canoma Imports:

2D Files
BMP (Win only)
GIF (w/alpha channel)
JPG
PICT (Mac only)
PNG (w/alpha channel)
PSD (w/alpha channel)
TIFF (w/alpha channel)
Canoma Exports:

2D Files
BMP (Win only)
PICT (Mac only)
PNG
PSD
TIFF
Animation

QuickTime
Sequential BMP (PC)
Sequential PICT (Mac)

3D Files
AutoCAD (.DXF)
MetaStream (.MTS)
Poser Prop (.PP2)
Truespace (.SCN)
VRML2 (.WRL)
Wavefront (.OBJ)

Windows:

Pentium Processor
Windows 95/98/NT4.0
32MB Free RAM (48+ Recommended)
50MB HD Space for Processing
16 Bit Color (24 Bit Recommended)
CD-ROM Drive (For Install)
Macintosh:

Power Macintosh
Mac OS 8.0 or Higher
32MB Free RAM (48+ Recommended)
50MB HD Space for Processing
16 Bit Color (24 Bit Recommended)
CD-ROM Drive (For Install)


mgisoft

http://www.mgisoft.com/
Reality Studio ，全景照相馆

MGI Software Corporation（http://www.mgisoft.com）的软件Live Picture Reality Studio Trial Version，运行于Win98系统，是种“所见即所得”的工具。不需要多少Java语言知识，仅利用鼠标点选、拖曳，即可制作出基于Java内核的“交互式全景环视”场景。将你用图像处理软件做好的360°空间平视图，在web浏览器中作环绕转动，也可用鼠标在场景中随意拖动，观看场景的不同部位，可做放大、缩小变换。更高级的作品还具有场景转换功能，即点击场景中的切换点，可以进入另外的场景。使浏览者恍若行走在三维空间中。
PhotoVista
用PhotoVista制作全景照片无需任何专业设备和技能，操作过程非常简单。拍完照片之后，将图像上传到计算机上，下面的事情就“全包”给PhotoVista了。PhotoVista强大的引挚可自动计算接缝，再通过复杂的边缘探测和平滑计算方法，即可制成无缝360度全景图像。该软件程序会告诉用户与镜头设置相匹配的合理的相片数量。这个新版软件配有一个全新的用户界面和自动修剪功能，可以更容易地制作全景照片。
MGIvideowaveIII 全景浏览器


schmoozer
http://www.schmoozer.net/
About using Schmoozer and the scope of these Web Pages:

We are offering the Schmoozer Framework and the included content as freeware, provided that users agree to the terms of the included non-commercial license. Commercial licensing terms are also available. This site serves the dual purpose of providing potential users with information about Schmoozer, Open Community, and ISTP, as well as providing online help, User guides, and tutorial information about Schmoozer.
As Schmoozer is a live, rich, interactive environment, we expect these web pages to be so as well. We would appreciate and encourage your feedback to help make this web site useful, informative, and fun.

We envision a range of different users for this Framework:

The "As is" user - This user will use the included content or lightly customize the included content in a formulaic manner to get started in multi-user VR worlds and use the framework to connect to and explore other people's worlds. Most people would start here, at least as a learning experience.
The "Artist" user - This user is probably already adept at creating VRML content using various tools and will use this framework to build complex and rich worlds and environments on the web. The included basic scripting capabilities are almost enough for many of this type of user.
The "Java Geek" - This user group will extend the framework with their own Java classes and behaviors. They probably also could have the same VRML capability, experience and tools as the Artists.
The Applications programmer - This user may want to tear up our framework, add their own components, and design some sort of complex functional application.
This web site is intended for all of these user levels. Please remember this as you use it . . . some parts may be intended for more advanced users or applications developers, but we hope we have provided enough information and welcome all comments or suggestions to improve the web site.


modelworks

Site Pad pro

http://www.modelworks.com/

JPad
JPad is a full featured Java(tm) editor for building simple Java applications and applets. JPad makes it easy to:

write, compile, run, and test programs
locate syntax errors
switch between JDK tools
write your own custom tools using JavaScript

Features include:

support for Sun's JDK Java tools
custom template for creating new Java files
custom menus, toolbars, hotkeys, and bookmarks
syntax coloring for Java keywords
java reformat source command
block indent and unindent
multilevel undo/redo
search and replace
multifile search
split windows
line and column number indicator
line numbers in the edit view
custom scripting using JavaScript

JPad Pro
JPad Pro is an Integrated Development Environment (IDE) for building Java applications and applets with support for editing HTML and other files. JPad Pro makes it easy to:

write, compile, run, and debug complex programs
locate syntax errors
switch between Sun's JDK Java tools and Microsoft's Java SDK tools
locate classes, methods and packages using the built-in browser
write your own custom tools using JavaScript

Features include:

ability to add your own custom tools using JavaScript
project manager with class, package and file views (also supports browsing)
support for custom document types
built-in support for Java and HTML files
java development environment with support for Sun's Java Development Kit (JDK) and Microsoft's Java Development Tools (MSJ)
visual Java debugger
smart complete for Java
commands to compile and run Java applications and applets
reformat Java source command
access JDK and HTML help files
point and click to locate errors
support for creating and managing new file types
bookmarks and graphical breakpoints
autocompletion
smart indent
smart keys
hotkeys
custom toolbars
custom menus
syntax keyword coloring for Java, HTML and custom file types
exposed keyword files
input and output options for supporting Windows, UNIX and MAC files
support for remote volumes using UNC paths (UNIX, Netware)
tabs to spaces and spaces to tabs options
block indent and unindent
multilevel undo/redo
integrated Finder toolbar
search and replace
replace in open files
find in open files
send mail support
split windows
line and column number indicator
optional line numbers

SitePad
SitePad is a Java, HTML and VRML editor. It includes all the features of JPad plus support for editing HTML and VRML files.

Features include:

support for Sun's JDK Java tools
syntax coloring for Java keywords
java reformat source command
insert scripts for all VRML 2.0 nodes
custom template for creating new Java, HTML and VRML files
syntax Check tool for HTML, VBScript and JavaScript
custom menus, toolbars, hotkeys, and bookmarks
syntax coloring for Java, HTML and VRML files
block indent and unindent
multilevel undo/redo
search and replace
multifile search
split windows
line and column number indicator
line numbers in the edit view
custom scripting using JavaScript

SitePad Pro
SitePad Pro is an Integrated Development Environment (IDE) for Java, HTML, VRML and other files. It includes all the features of JPad, SitePad and JPad Pro.

Features include:

insert scripts for all VRML 2.0 nodes
ability to add your own custom tools using JavaScript
project manager with class, package and file views (also supports browsing)
support for custom document types
built-in support for Java, HTML and VRML files
java development environment with support for Sun's Java Development Kit (JDK) and Microsoft's Java Development Tools (MSJ)
visual Java debugger
smart complete for Java
csharp editor
commands to compile and run Java applications and applets
reformat Java source command
access JDK and HTML help files
point and click to locate errors
support for creating and managing new file types
bookmarks and graphical breakpoints
autocompletion
smart indent
smart keys
hotkeys
custom toolbars
custom menus
syntax keyword coloring for Java, HTML, VRML, and custom file types
exposed keyword files
input and output options for supporting Windows, UNIX and MAC files
support for remote volumes using UNC paths (UNIX, Netware)
tabs to spaces and spaces to tabs options
block indent and unindent
multilevel undo/redo
integrated Finder toolbar
search and replace
replace in open files
find in open files
send mail support
split windows
line and column number indicator
optional line numbers


NEMO SoundPlayer

Nemo
www.nemo.com
"NEMO SoundPlayer" embeds sounds into your HTML pages. It plays MPEG and RMF music files.
Use Shockwave technology.
"NEMO-RMFPlayer" is a standalone software for MAC and PC. Play easily all RMF music files on your computer.


neo3D

http://www.neo3d.com
neo3D is a component-oriented 3d programming system that makes it easy to create lightweight 3d plugins and standalone applications. neo3D is COM based, so it can be used with IE, Visual Basic, Visual C++, Delphi, or any COM supporting system.
Developing with neo3D, you get the power of high-level scripting AND the performance of compiled components. The scripting makes it easy to rapidly prototype your next 3d app using your own or others' components. neo3D components can be dynamically loaded at runtime (even over the Internet) so it is easy for your applications and content to keep pace with 3d's rapid evolution.
neo3D Component Library

These are the components that are currently under development alongside the neo3D System itself.

Component
VRML97 / X3D Suite
The basic building blocks of a VRML97 / X3D browser, including the capability to implement new nodes (EXTERNPROTOS) using neo3D components.

XML Suite
Several components that enable reading of XML data and reading/manipulating DOM representations.

Spatial Audio
3D Positional Audio using DirectSound 3d. Realtime mixing and pitch control. Doppler-shift effects.

Database Suite
Use ADO and ODBC for 2-way connection with a variety of data sources.

DirectInput
Use DirectInput to add support for low-latency input from Mouse, Keyboard, and a variety of configurations of Joysticks,3DOF and 6DOF input devices.

Music-Synch
Synchronize your content with music from cd, midi, wav, mod, or mp3.

neo3D Viewer Toolkit

The neo3D Viewer Toolkit consists of a set of "Containers" for making different types of applications, and a few core components to get you started. neo3D Containers provide these basic services:

Loading and initializing components from a local drive or over a network.
Scripted control using Microsoft Scripting?. VBScript and JScript included, other languages available.
Initialization of rendering layer. DirectX, OpenGL, and Glide supported.
Containers for these environments are included:

Netscape Plugin (pictured below)
ActiveX Control
Standalone Executable
Screen-Saver

Netscape plugin (full-page) created using neo3D System
Each application built with neo3D consists of a set of components and a script which specifies which are loaded, and how they will interact at runtime. The easy high-level control that scripts provide is complemented by the fast interaction possible between COM-based components. Different components can draw to the display at the same time, and all appear in the correct arrangement because of careful synchronization and a shared Z-buffer.
neo3D components are simple dual-interface COM objects which can be readily made using most of today's popular Win32 development tools. Because of the ubiquity of tools that can use such components, components written to operate in neo3D are easily useable in many contexts. Example neo3D components with source are included in the Toolkit.

neo3D IDE

To make it easy to rapidly develop using neo3D Containers,Components, and Scripts, our integrated development environment (IDE) brings it all together in one simple interface. Projects are displayed as a familiar "tree view", with all active components and media elements available for inspection.
A syntax-highlighted script editor and debugger is included which allows changes in the Script to immediately be reflected in a running application. This makes for an unprecedentedly rapid development process - encouraging experimentation and creativity. A component library, debugging console, and documentation are presented in an embedded HTML window. This allows all sorts of up-to-date resources to be pulled right into the IDE, where you need it.

neo3D Components can inform the IDE of corresponding Design-Time Components which are then available to be loaded into the interface. The IDE is in fact a special class of neo3d Container for design-time work.


Octree
http://www.octree.com/

Author - Converts 3-D datasets from standard formats (e.g., 3D Studio '.3ds' files) into files that can be viewed by Octree View. Price: $995 (PC version).

Octree View - Browser plugin for the interactive display of 3-D datasets generated by Author. Free for noncommercial use. Note: The Embedded Application SDK is available for the use of View in customer applications.

TrueSolid - Full-featured library and application for the conversion, manipulation, analysis and display of volumetric datasets.


Onlivel!Traveler


OpenWorldsTM

OpenWorlds
http://www.openworlds.com/
OpenWorldsTM is an open X3D-compatible system which extends new and legacy applications with immersive Web 3D graphics, multimedia, animation, and VR capabilities. Originally developed for NASA E-training, OpenWorlds is now available for your E-learning, Web-commerce, or other application.
  • OpenWorlds Merchant-WZTM VRML 97 Loader for OpenGL Optimizer ,
  • OpenWorlds Merchant-SZTMVRML 97 loader for OpenGL Optimizer 1.2TM ,
  • OpenWorlds Horizon-WZTM(OpenGL Optimizer based) ,
  • OpenWorlds Horizon-NGTM(OpenGL based) ,
  • OpenWorlds Horizon-HGTM(OpenGL based)
Product Overview Services Showroom Downloads

OpenWorlds Products

Check back in a couple of weeks for OpenWorlds new X3D player for IE!

OpenWorlds HorizonTM Extensible Browsers
OVERVIEW | PRODUCT PAGE | DOWNLOAD | PURCHASE SDK

OpenWorlds MerchantTM Geometry Loaders
OVERVIEW | PRODUCT PAGE | DOWNLOAD | PURCHASE

OpenWorlds AppKitTM Developer Libraries
OVERVIEW | PRODUCT PAGE | TRIAL CD | PURCHASE

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OpenWorlds Product Descriptions
OpenWorlds HorizonTM
Web 3D and Multimedia Browsers (supporting VRML and X3D) with extensible node support Software Development Kit (SDK). Create your own built-in nodes!
PRODUCT PAGE | DOWNLOAD | PURCHASE SDK

Horizon-WZ for Windows OpenGL OptimizerTM based
DOWNLOAD BROWSER | PURCHASE SDK

Horizon-WZ ActiveX Control for Windows OpenGL OptimizerTM based
DOWNLOAD BROWSER | PURCHASE SDK

Horizon-SP for SGI Irix OpenGL PerformerTM based
DOWNLOAD BROWSER | PURCHASE SDK

Horizon-SZ for SGI Irix OpenGL OptimizerTM based
DOWNLOAD BROWSER | PURCHASE SDK

main menu
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OpenWorlds MerchantTM
VRML 97 and X3D geometry-only importers for OpenGL PerformerTM and OpenGL OptimizerTM. Available in free demo version and full commercial version, or build a custom animation loader with the AppKit.
PRODUCT PAGE | DOWNLOAD | PURCHASE

Merchant-WZ for Windows
VRML/X3D Loaders for OpenGL OptimizerTM
DOWNLOAD DEMO | PURCHASE

Merchant-SP for SGI Irix
VRML/X3D Loaders for OpenGL PerformerTM
DOWNLOAD DEMO | PURCHASE

Merchant-SZ for SGI Irix
VRML/X3D Loaders for OpenGL OptimizerTM
DOWNLOAD DEMO | PURCHASE

main menu
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OpenWorlds AppKitTM
Application development kit to build new Web 3D and multimedia applications or to extend legacy applications. Includes Web 3D graphics (VRML, X3D) parsing, scene graph, routes, animation, scripting support, Javascript, external authoring, advanced rendering including shadows and NURBS, and more...


Others

  • Multiuser
  • Authorware
  • 3DS, 3DS Max, 3DS VIZ
  • Maya
  • LiveMotion
  • Director
  • Premiere
  • Freehand
  • Photoshop
  • SoftImage
  • CorelDraw
  • Illustrator
  • PageMaker
  • Pano
  • ADGPanorama
  • Bruce3D
  • Shockwave
  • Xtra
  • Quark3
  • Photopaint
  • VR360
  • AutoCAD
  • Lightwave
  • MaxScript ???
  • Media100
  • XSI
  • Dimension
  • Rhino
  • Brazil
  • VirtualLight


其他

3D Groove
http://www.3dgroove.com proprietary web browser
plugin Win/Mac streamed 3d ads in the environment

Alice
http://www.alice.org web browser plugin Win python as scripting language

Anfy 3D
http://www.anfyteam.com/
panfy3d.html pure java web browser plugin Win large collection of specialized applets

Atomic 3D
http://www.atomic3d.com/
start/start.html java web browser plugin Win

Brilliant Digital Entertainment (B3D)
http://www.multipathmovies.com/html/developer/index.html proprietary web browser plugin Win streaming, works with 3D StudioMax

Cult 3D
http://www.cult3d.com/ proprietary web browser plugin Win MacOS SunOS HP AIX Linux BeOS !!! look at the multiplatform support

Emotion 3D
http://www.anarkmedia.com/
products/emotion3d.htm simple authoring N/A all platforms 3D gif animations

EON Viewer
http://www.eonreality.com/
propretary standalone or plugin Win part of robust suite of tools

GL4Java
http://www.jausoft.com/
products/gl4java/
gl4java_main.html OpenGL in Java Win MacOS Linux Unix source available

Flatland
http://www.flatland.com/ proprietary web browser plugin Win 3DML - HTML-like markup language for very simple authoring

OZ, Fluid3D
http://www.oz.com/fluid3d/ proprietary RealMedia G2 plugin Win streaming

GEL
http://www.urstudios.com/ opensource ? uses QDraw for rendering (Win Linux FreeBSD forthcoming SonyPlaystationII)

Hypercosm
http://www.hypercosm.com/ proprietary web browser plugin Win/MacOS uses OMAR language

Java3D
http://java.sun.com/
products/java-media/3D/ java api Win/SunOS can import VRML


OZ
WWW.Oz.Com
Fluid3D
另 一 个Web3D 系 统 是 来 自Oz.Com 的Fluid3D 系 统 它 有 自 己 独 特 的 优 势： 它 依 附 于 网 上 最 流 行 的 媒 体 流 播 放 平 台 — —RealSystem。RealSystem 及 其 主 要 的 用 户 部 件RealPlayer 一 向 以 不 断 完 善Web 音 频 艺 术 而 著 称 于 世。 通 过 在RealPlayer 的 最 新 版 本RealSystem G2 中 加 入Fluid3D 插 件， 这 两 个 公 司 都 希 望 能 改 善Web 的3D 图 像 技 术。

---- 由 于Fluid3D 并 不 是 一 个Web 编 写 工 具， 因 此 它 着 眼 于 强 化3D 制 作 平 台 的 性 能。 直 到 最 近 才 公 诸 于 世 的Fluid3D 插 件 填 补 了 市 场 的 一 个 空 白， 尽 管 到 目 前 为 止 它 的 应 用 范 围 还 相 当 有 限。 它 的 主 要 功 能 是 可 以 用 来 传 输 高 度 压 缩 的3D 图 像， 而 这 种 图 像 的 下 载 通 常 是 相 当 麻 烦 和 耗 时 的。 它 的 运 用 有 助 于 使Web 的3D 技 术 更 实 用 和 切 合 实 际， 使 之 对 桌 面 用 户 而 言 更 有 乐 趣。


panavue

www.panavue.com
PanaVue ImageAssembler stands as a professional yet accessible image stitching software. Extremely powerful though deceivingly simple. It is meant for any type of users, from the beginner to the most experienced.

Panoramas
PanaVue ImageAssembler lets you assemble multiple photos to build genuine mosaics or restore vast panoramas. It can easily wrap a complete 360o panorama. Images can be saved in most common formats (bmp, tiff, jpeg, pict, targa, etc) but also in the QuickTime? VR format from Apple. Once saved in this format, images can be visualized in Virtual Reality with QuickTIme Viewer. They can also be published directly on the web and displayed in Netscape or Microsoft Explorer browsers (with the QuickTime plug-in).
PanaVue ImageAssembler earned the top rating from ZDNet online magazine

Publishing
Very robust, PanaVue ImageAssembler has also been designed to work on very high resolution images, with dimensions over 500 MB*, making it perfectly appropriate for stitching photos meant for high quality graphic printing.

* This size is for Windows NT/2000, it is about half this size for Windows 95/98/ME.

Increased scanner capacities
Very versatile, its TWAIN compatibility lets it directly import images from a scanner. It then becomes extremely easy, with PanaVue ImageAssembler, to digitize an image which dimensions exceed those of the scanner. All you have to do is scan the image in multiple parts and stitch them back together. As in photo stitching, the precision obtained is so good that it is usually impossible to tell that you are looking at a rebuilt image.

Aerial and satellite photos, multiple photos of a painting, a blue print, a map, or a microscope slide, medical imagery.
Provides a precise and easy way to assemble pictures of a single flat subject shot in multiple parts. Ideal for stitching aerial or satellite photos for cartography, multiple photos of a painting, a blue print, a plan, or a map, in fact any case where the camera is moved over a relatively flat subject while kept perpendicular to it.

Simple Interface
The interface amounts to merely little flags (or markers) that you simply click and drag with your mouse to pinpoint the way you want images to be stitched. On request, PanaVue ImageAssembler assists you in this task thanks to a powerful image recognition algorithm.

This approach, using markers to indicate stitching points, gives PanaVue ImageAssembler the special ability to work with tilted cameras and very high resolution files. But probably more important, it lets you, the user, keep complete control on how the images are stitched. At any time you can deactivate the "marker assistant" and manually place markers to precise stitching points allowing you to successfully stitch images that were not taken under ideal conditions.

Powerful Features

PanaVue ImageAssembler warps, color adjusts, and blends images. It automatically adjusts itself to any lens* focal length and works perfectly even with a tilted camera. In the all automatic mode, images are even positioned by the software.

*: supported lenses are: any rectilinear lens, lenses with some degree of distortion like zoom lenses and some wide-angle lenses that are not purely rectilinear, 16mm full-frame fisheyes.

Main Features:

works with high resolution (multi-megabytes) pictures
does photo-warping
blends images with an "intelligent" blending algorithm to remove double images and blurring
does color-matching
uses full pictures (not just thumbnails) for full zooming capacities to bring manual corrections if needed
can assemble a "mosaic" of images
works with a tilted camera
automatically adjusts itself to any rectilinear (e.g. standard) camera lens and full-frame fisheyes (16mm)
saves panoramas in QuickTime VR format
TWAIN compatible

Minimal requirements:
Pentium 90 MHz
Windows 95/98/ME/ with 32 MB virtual memory, Windows NT/2000 with 64 MB of virtual memory
10 MB hard disk space
800 x 600 monitor with 65536 colors (16 bit) or true color (24 bit)


Panorama Factory

Smoky City Design, LLC
www.panoramafactory.com
The Panorama Factory V2.2
不论您是要制作出具有360度效果的影像式虚拟实境，或者只想要制作出超宽幅照片，The Panorama Factory都可以让您只要透过几个简单的步骤就可以做到。
The Panorama Factory from Smoky City Design, LLC is a panoramic stitching program for Windows 95 / 98 / ME / NT / 2000. You can use it to create high-quality panoramas from a set of overlapping digital images from a single vantage point. The Panorama Factory transforms (warps) the images so that they can be joined seamlessly into panoramas whose fields of view can range up to 360 degrees. In fact, you can make panoramas that exceed 360 degrees if you wish!


parallelgraphics
http://www.parallelgraphics.com/
View Internet 3D with:
Cortona VRML Client
the client for MS Internet Explorer and Netscape Navigator, capable of browsing virtual worlds written in VRML.

Cortona VRML Client for Mac
Cortona for Mac is a free add-on for Microsoft Internet Explorer and Netscape Navigator which is capable of browsing virtual worlds written in VRML.

Cortona VRML Client for Mac OS X NEW version 1.0 Beta
Cortona for Mac OS X is a free add-on for Microsoft Internet Explorer which is capable of browsing virtual worlds written in VRML.

Pocket Cortona NEW version 1.5
The first ever VRML browser for viewing 3D on wireless devices.

Cortona Jet
a small cross platform Java Applet that enables any standard web browser with a Java Virtual Machine to display interactive 3D environments and models without the need for special plug-ins.

Develop with:
Cortona Software Development Kit NEW version 2.6
enables developers to integrate the Cortona 3D/VRML engine into web or standalone applications.
Multi-User Server
our new product allows you to: communicate with other on-line users in virtual scenes; place 3D objects into scenes and manipulate them in multi-user mode; and edit 3D objects in scenes. Try this technology for e-commerce, distance training, online collaborations, on-line games and virtual communities, etc.

Enjoy with:
VRML Screen Saver
brings you an expandable collection of charming and amusing VRML scenes for free!

Create 3D for the Internet:
The full range of ParallelGraphics' authoring tools offer you the technology to create dynamic Internet presentations for all your commercial, educational and entertainment projects and needs.
Design 3D scenes with ISB, add interactivities and animations with ISA, and populate your scenes with Internet Character Animator!

Internet Space Builder
a 3D tool that allows you to create impressive 3D worlds from scratch! Design objects, add textures and sounds, and Web links to them - and publish the final 3D scenes on the Web!

Internet Scene Assembler
a state-of-the-art revolutionary tool that allows you to assemble 3D scenes full of interactivities and animations without having to program! The range of applications is enormous: from virtual tours around real estate developments to interactive product presentations, and visual manuals for students anywhere in the world.

Internet Character Animator
offers visual support for the creation of professional quality 3D animations. Animated characters can be placed into ISA scenes to add a range of new interactivities and animations - an essential element in the development of interactive clips for the Web!

Internet Model Optimizer
a new innovative tool which provides an efficient way to optimize complex CAD/CAM/CAE files for use on the Internet.

VrmlPad new version 1.3
a professional VRML editor. VrmlPad combines time saving features of the text editor with visual support for the scene tree and document resource operations. VrmlPad is must have for all VRML professionals.

Extrusion Editor
A unique visual plug-in for VrmlPad that is effective in the creation and editing of extrusion models.


PixAround

http://www.pixaround.com.cn/

PixMaker 1.0

通过Snap, Stitch, Publish!? 三个简单步骤制作带有虚拟漫游的互动360度PixAround Webpage，然后将你的PixAround场景通过Hotspots与其他PixAround场景、网页、音频或视频文件链接起来。你可以选择将你的PixAround Webpage刊出在网络或你的个人数码助理上，所有这一切都不需要复杂的器材或额外的浏览插件软件。 商用版 （RMB 2800元） 为你的网上商店制作一个360度PixAround Webpage，通过使用Hotspots与其他PixAround场景、网页、音频和视频文件、或电子邮件链接起来，以完成整个网页的制作。从而让你的顾客收听产品介绍，观看产品使用示范，甚至是观看360度产品视图。 详细资料 | 下载 | 购买 家用版 （RMB 190元） 将一系列相片通过Snap, Stitch, Publish!? 三个简单步骤，转换成一个互动的360度PixAround Webpage；然后将你的PixAround场景通过Hotspots与其他PixAround场景、网页链接起来。 详细资料 | 下载 | 购买 注意：对家用和商用版的使用执照要求是：一个执照只能用于一个网站。如果您是增值性的转售商或网络发展商，需要为你的客户制作PixAround场景以及注册使用执照。请与我们联络sales@cndigital.com

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PixScreen 1.1

PixScreen 1.1是一个能制作幻灯片，并能离线观看和打印PixAround场景的观察程序。 商用版 在购买PixMaker 1.0(商用版)时，带有该软件 使用Hotspots离线观察360度物体视图、部分角度和360度全角互动PixAround场景。安装和使用简单，你也可以用它制作幻灯片，或将你的PixAround场景以普通形式或全景视图形式打印出来，以便分发和保存。 详细资料 | 下载 家用版 在购买PixMaker 1.0(家用版)时，带有该软件 观看带有Hotspots的部分角度和360度全角互动PixAround场景。安装和使用简单，你也可以用它制作幻灯片，或将你的PixAround场景以普通形式或全景视图形式打印出来，以便分发和保存。 详细资料 | 下载

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PixScreen 1.0 免费

PixScreen? 1.0是一个观察程序，它能让你在多种平台上观察360度或部分角度的互动PixAround场景。它安装和使用简单，你也可以将你的PixAround场景展现成一个幻灯片，或以普通形式或全景视图形式打印出来，以便分发和保存。 详细资料 | 下载

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PixScreen PDA Lite*

PixScreen PDA Lite让你在Palm? handhelds, HP Jornada, CASSIOPEIA? 以及其他Pocket PC和Windows? CE器件上观看你所喜爱的PixAround场景。作为英文版PixMaker 1.0(商用和家用版)的一项强化软件，你不需要为享有这一互动视觉内容而花费！PixScreen PDA Lite备有两种版本： PixScreen Palm Lite (英文版) PixScreen Palm Lite能在个人数码助理(PDA)上体验到PixAround场景。这包括了Palm? IIIc和Handspring? Visor? Prism。PixMaker 1.0英文版和家庭和商业用户将无需支付额外费用，而享有这一强化软件。 详细资料 | 下载

PixScreen WinCE Lite (英文版)

PixScreen WinCE Lite能在个人数码助理(PDA)上体验到PixAround场景。这包括了Casio CASSIOPEIA?，HP Jornada和其他Pocket PC。PixMaker 1.0英文版的家庭与商业用户将无需支付额外费用，而享有这一强化软件。 详细资料 | 下载 * 只备有英文版


Pulse Entertainment


Pulse 3D
http://www.pulse3d.com
Pulse Player

Pulse Player is a free browser plug-in that allows you to view and interact with content created using Pulse technology. No existing multimedia plug-in gives you as advanced interaction and high quality streaming as the Pulse Player

Pulse Creator

Pulse Creator allows content developers to author and publish sophisticated, interactive, lifelike 3D content in smaller file sizes than ever before. Pulse Creator enables interactivity to be brought into any Pulse-powered web project. Pulse's powerful and versatile scripting language offers full control over the elements of a Creator project allowing for additional interactive options and custom features.

datasheet
Pulse Producer

Pulse Producer?is the next step for 3ds max?developers who want to publish cutting-edge, interactive content on the Web directly from the MAX interface. Designed to add functionality to MAX content, Producer bridges the gap between creation and delivery by creating web-optimized, Pulse-enabled files. A companion to Pulse Creator, Producer enables MAX developers to publish detail rich, 3D content on the web

datasheet


Sense8

WorldUp
--http://www.sense8.com/
--Based on Sense8's World Toolkit (WTK) format which has been around for a long time. They claim very high performance.
EAI's Sense8 Products and Mitsubishi Electronics America, Inc. are pleased to announce the availability of Indy3D for you to download.

"HP is pleased to support Indy3D as an open industry standard benchmark for OpenGL. Indy3D has a number of advantages over what is currently available. Namely it's easy to use and market focused. It is meaningful to our Kayak PC Workstation customers because the benchmark engine is a real application and therefore presents a more realistic load to the computer."

Larry Mahoney
NT Graphics Performance Manager
Hewlett-Packard Company
www.hp.com/kayak
WorldToolKit
WorldToolkit is the leading cross- platform real-time 3D development tool.

WorldToolKit Release9 is a cross-platform software development system for building high-performance, real-time, integrated 3D applications for scientific and commercial use.

WorldToolKit R9 has the function library and end-user productivity tools you need to create, manage, and commercialize your applications. With the high-level application programmer's interface (API), you can quickly prototype, develop, and reconfigure your applications as required. WorldToolKit R9 also supports network-based distributed simulations, CAVE-like immersive display options, and the industry's largest array of interface devices, such as headmounted displays, trackers, and navigation controllers.

Designed for performance
The architecture of WorldToolKit R9 has been designed to incorporate the power of scene hierarchies. This efficient visual database representation provides increased performance, control, and flexibility through features such as hierarchical object culling and efficient use of transform information and level-of-detail switching.

Maximized for development
WorldToolKit R9 provides all the functionality you need to develop the most complex applications while improving your development productivity. It is an object-oriented library written in C with more than 1,000 high-level functions for configuring, interacting with, and controlling real-time simulations. One function call can do the work of 1,000 lines of C code, dramatically shortening development time. WorldToolKit R9 is organized into over 20 classes including the universe (which manages the simulation and contains all other objects), geometric objects, viewpoints, sensors, paths, lights, and others. Functions are included for device instancing, display setup, collision detection, loading object geometry from file, dynamic geometry creation, specifying object behavior, and controlling rendering.

Open and Optimized
WorldToolKit Release 9 incorporates the philosophy of OpenVRTM . This means that WorldToolKit R9 is portable across platforms, including SGI, Sun , HP, DEC, Intel, and Linux. WorldToolKit R9 is optimized to make full use of the unique capabilities of each platform to deliver the fastest graphics possible. A set of optimization functions unique to each platform interfaces directly with each system's graphics libraries. In addition, WorldToolKit R9 supports a wide variety of input and output devices, and also allows you to incorporate existing C code-such as device drivers, file readers, and drawing routines-and to interface with a variety of information sources.

World Up
World Up is a complete software development and delivery environment for building 3D/VR applications. Building upon the foundation of EAI's award-winning WorldToolKit, the industry's most widely used visual simulation software development toolkit, World Up provides powerful real-time functionality in an interactive, object-oriented environment.

World2World

World2World, the Client-Server Solution for 3D Real-Time Software Environments.

Engineering Animation Inc. has recently announced a client/server based networking solution named World2World, which integrates with its family of award-winning products WorldToolKit and World Up to enable developers to quickly and efficiently create multi-user 3D/VR simulation applications for Intranet and Internet deployment. This suite of tools will enable customers to take advantage of the decreasing cost of 3D graphics acceleration and increasing bandwidth and network pervasiveness to create compelling collaborative and distributed 3D real-time interactive simulations.

Unlike the recent spate of networking packages targeted primarily at game and chat applications, World2World has been designed specifically for the business community (applications like collaborative design/engineering, distance learning, multi-participant training, etc.). Corporate-focused features include secure firewall traversal and efficient transfer of data across a range of common enterprise network architectures. World2World’s client/server networking model allows multi-user 3D/VR applications to be efficiently deployed via the Internet as well as other local and wide area networks.


SGIP

http://www.sgip.net
SGIP三维全景展示系统－造景师（SGIP Scape）

产品简介：

造景师（SGIP Scape）提供了一种在因特网上逼真展示三维全景的崭新方法。 它能对一个现实场景拍摄的场景图像进行自动处理，自动生成交互式全景。 它能使用户方便地从多角度交互观看三维全景。该系统可广泛应用于房地产展示、虚拟旅游等行业。

系统构成：

造景师（SGIP Scape）主要由以下部分组成：
  • 三维全景制作发布软件(SGIP ScapeBuilder)：对拍摄的现实场景图像进行全自动处理，自动生成全景图像。
  • 三维全景查看软件(SGIP ScapeViewer)：用于在浏览器中播放三维全景。
  • 硬件：可配合鱼眼镜头的数码相机、鱼眼镜头和三角架等（推荐配置：Nikon CoolPix990+Nikkor FC-E8镜头+Manfrotto三角架和云台）。


Shells Interactive
http://www.shellsinteractive.com
Shells 3D Author can be used by over 500,000 Macromedia Director users to bring interactive 3D to the Shockwave Player platform for rich media 3D e-business presentations.
Shells 3D Author - Overview

Shockwave Compatible
Create dazzling interactive 3D building blocks for Macromedia Shockwave with an easy-to-use, script-free drag-and-drop authoring tool that requires no 3D modeling knowledge.

Director Extension
Interactive 3D building blocks can be integrated into virtual environments using Macromedia Directorò 8.5 Shockwave Studio.

Interactive 3D Wizard
User-friendly, powerful tool to define animations, create interactivity, insert sound files, add bitmaps, and change lighting, color and texture to create 3D building blocks for Shockwave.

Use Existing 3D Content
Easily export pre-existing models from the most popular 3D software applications, such as 3ds max and Maya, to the new Shockwave .w3d file format. All .w3d models can then be easily used in the Shells 3D Author, saving time and money

Optimize Streaming
Select the streaming order of model parts, integrate into your Shockwave content, and, with the click of the mouse, upload to the Shells server. View Shells

3D Content Anywhere
Over 200 million users worldwide can interact with Shells 3D content using Shockwave, the most pervasive multimedia playback engine on the Web.

Shells Server for Shockwave content provides e-businesses with tangible commercial benefits such as Digital Rights Management, Usage Tracking, and Non-linear and Non-uniform Streaming and the best end-user experience available on the Web today.

Overview
The Shells Server provides content developers and e-businesses the most effective way to manage and distribute interactive content. It will provide superior hosting and streaming tailored to interactive usage, digital rights management to protect and authorize the usage of content, and usage tracking to statistically evaluate the success of your content.

Uploading content
All interactive content created in the Shells 3D Author is uploaded to a server that has the Shells Server software installed. This process requires the content developer to register with the Shells Interactive Web site. Please see Support for more information.


Sumea
http://www.sumea.com
sumea::engine allows easy and rapid creation of 3d-applications to ordinary web pages. 3d-applications developed with Java-based sumea::engine require just a standard web browser to run, no plug-ins are required. The first non-public beta version of sumea::engine has been released and is now being field-tested.


TGS
http://www.tgs.com/
-- Proprietary web browser plugin by TGS
Open Inventor has become the de facto standard for development of cross-platform (Windows, UNIX, Linux) 3D graphics applications in C++ and Java. It is a powerful object-oriented toolkit with over 450 classes and an intuitive and easy-to-use programming interface that allows for rapid prototyping and development of graphics applications.

Open Inventor has an extensible architecture that allows developers to add their own functionality. TGS is offering extensions to the toolkit that will allow the developer to "mix and match" the extensions as needed, creating a developer's toolkit that is customizable to the individual developer's specifications. These extensions give the Open Inventor developer (and even the OpenGL programmer) new functionality that will speed up application development.

Automatic OpenGL optimization
Since Open Inventor was designed specifically to use OpenGL for graphics rendering, it is highly optimized to take advantage of all OpenGL accelerators. It provides the power and functionality of OpenGL at an object-oriented level.

Rapid Application Development
Its optimized scenegraph pipeline also allows the developer to target PC and low-end systems without hardware acceleration. Open Inventor is a very high-level API, reducing the programming time required of OpenGL or Direct3D by over 10 times - and resulting in products that can be completed in much less time with much more sophisticated capabilities.

MFC extension
Open Inventor is both a cross-platform UNIX-PC toolkit and a native 3D toolkit for Microsoft Windows operating systems. For the PC, TGS has developed a native 3D extension to MFC, called IVF (Interactive Visual Framework?), that is integrated with Open Inventor.

"The integration with Microsoft MFC is elegant!" Windows Magazine


ualberta

MR Toolkit
http://www.ualberta.ca/
MR (Minimal Reality) Toolkit is a set of software tools for the production of virtual reality systems and other forms of three-dimensional user interfaces. It consists of a set of subroutine libraries, device drivers, support programs and a language for describing geometry and behavior. MR provides a device independent and portable platform for the development of VR applications. Applications that are developed at one site can easily be ported to other sites with minimal or no change to the source code. VR tools for developing virtual environments includes Object Modeling Language (OML), 3D modeler (JDCAD+), and Environment Manager (EM) for running multi-user networked applications. The package runs on HP, SGI, DEC, and IBM RS6000 workstations. Some elements of the MR Toolkit also run on Suns, Alphas and other UNIX platforms. MR software is available at no cost to licensed academic and research institutions subject to the conditions in The MR Toolkit Software License Agreement.


Ulead

Ulead Systems, Inc.
www.ulead.com.tw
影像處理產品
- PhotoImpact
- 我形我速
- Ulead COOL 360
- Ulead Photo Explorer

動畫製作產品
- Ulead COOL 3D
- Ulead GIF Animator

影片剪輯產品
- MediaStudio Pro
- 會聲會影
- Ulead GoDVD!

3D繪圖產品
- ETShade

設計素材產品
- Ulead Pick-a-Photo
- Ulead Pick-a-Video


Ur Studios

www.urstudios.com

http://gel.urstudios.com

http://www.mutationlabs.com/gel/
GEL
Gel is a new open framework for enabling multi-user three-dimensional worlds. Combining fresh ideas with established techniques, Gel incorporates curved, non-polygonal modeling and animation capabilities, peer-to-peer networking, global time stamps, visual authoring, and a distributed processing model for dynamism and deep interactivity. Unifying and enabling these features is a powerful new programming paradigm, a graph-based programming language.

Gel allows the entire code for a virtual world to be visualized as 3D nodes in a tinker toy-like network that can be manipulated and edited in click and drag-style inside the world. This is intended to provide, in the long run, for end-user programming of all aspects of a virtual world, including behaviors. Users will no longer be limited to navigating someone else’s world but will be empowered to modify or create their own, and build worlds collaboratively, in real time. Gel is also designed to favor fast, responsive interactions between multiple users (or avatars) in small groups, within larger worlds that may contain any number of simultaneous users.

Gel is an open-ended platform intended to include all interested parties and the best and brightest of new ideas. Distribution of Gel will be free via open source, following the BSD license. The initial release will consist of a bare-bones infrastructure on top of which further tools, applications and virtual worlds can be built.

A compact, multi-threaded, object-oriented program, Gel is written in independent C++, and is designed to be easily portable, using multiple modules. It will work equally well as a web browser plug-in or a full-screen application, either stand-alone or networked. In addition, Gel combines three distinct layers written from the ground up--networking and the graph programming engine, a retained mode 3D renderer, and a graphics driver plus immediate mode 3D rendering engine (see QDraw addendum)--that can be incorporated individually or in tandem for other open source applications.

By re-thinking the methods and assumptions underlying current 3D applications for the Internet, we believe we have established a sound blueprint and working model for a universal visual communications medium. A medium designed to be owned by none, accessible to all, and adaptable to many different needs. We offer Gel as a functional kernel which, when fully developed, will have the potential to transform online 3D from the pursuit of a devoted minority into a true mass medium and industry. Conceivable applications of Gel-based virtual worlds span the spectrum from entertainment, including online and set-top gaming; science and education; virtual communities; new interface paradigms; and E-commerce applications including database visualization.

Note: This presentation is intended only as an overview of a work-in-progress. It is neither a technical specification nor a scholarly assessment of prior work and influences.

Key Features of Gel

As the concept of a graph is not necessarily familiar to many people, and because the graph engine is so central to Gel and some of its innovative features, we first provide a brief background on graphs and the Graph Evaluation Language.

Unified Graph Evaluation Language

What is a graph? "Graph" is a technical term from mathematics, designating a set of connected entities. A web site may be viewed as a graph: Seen from the "inside," it appears as a page with a set of embedded text hyperlinks to other pages. From the "outside," however, it can be visualized as a set of nodes connected by links--technically known as "edges." A physical network--such as the Internet itself--can also be modeled as a graph.

Graphs have been studied in mathematics extensively, and are a pervasive structure in computing. In fact, it is possible to argue that computing is inherently graph-based, and that linear programming languages are simply derivatives of this deeper structure (and that they in some ways serve to obscure it). By incorporating a graph paradigm in its foundations, Gel benefits from the large number of graph algorithms that have been discovered.

Gel’s groundbreaking Graph Evaluation Language conceptualizes the entire coding infrastructure of a 3D world as a network of connected objects, itself visualizable in three dimensional space. (In the long run, all the components of the Gel system itself--not just the worlds created with it--will be visualizable in the same manner.) Graphs allow scene description, object description and behavioral programming to be handled uniformly as graph structures. The Graph Evaluation Language examines these graph components and encodes them for concise shipping over the Net (generally, only portions which have changed).

The result is dynamism, smaller packets, and worlds built on a truly distributed basis. The graph structure also provides a convenient way of storing information about a network of Gel-enabled machines, for speeding up communications (see below). Finally, it enables a novel approach to visual authoring that goes beyond the standard click-and-drag menu formula, by 'wiring' 3D objects into programmatic networks. (Akin to a 3D version of the 'schematics' or 'hypergraph' features found in high-end 3D animation programs: Imagine file hierarchies visualized and manipulated in three dimensional space, with the files replaced by nodes representing the various objects in a scene, their behaviors, attributes, etc.)

Current Roadblocks and Gel Solutions

For each of Gel’s defining features, we first summarize the problem encountered by existing approaches, then Gel’s solution:

1) Non-polygonal rendering
2) Peer-to-peer networking
3) Global time stamps
4) Click and drag authoring in 3D
5) Distributed processing
6) Modular open source
7) Portability

1) Non-Polygonal Rendering

Existing approaches to online virtual worlds are generally premised on polygonal rendering. This was a natural route to take given limited processing power, previous work, and current graphics architectures which are designed to handle polygonal information (specifically, triangles). Any object can be modeled approximately using triangles. However, the larger and more complex and irregular an object is, the more triangles are required to define it well. In fact, an ideal standard range for the number of triangles rarely exists. If a complex object is viewed from a distance, polygons are largely wasted (using up precious processing power, and memory). If it is viewed from close range, there may not be enough facets to simulate smooth contours. Level-of-detail and progressive mesh techniques address these problems in some ways, but mostly current modeling and animation packages already use non-polygonal rendering techniques because it is in animation that the limits of polygonal approaches become most evident. Simple motions (for example, rotation) are workable with polygonal models, but the computations required for complex polygonal deformations (warping or bending of surfaces-- arms, for example) are undesirable for real-time applications. Thus programmatic polygonal animation is rarely smooth or natural in appearance. Additionally, polygonal descriptions of objects are large relative to the amount of information they convey and so transit times for complex models across the net are large.

Alternative higher-order (non-polygonal) mathematical descriptions of objects can shift the burden from transmission time to processor time on the local machine. If correctly implemented, non-polygonal descriptions can result in smaller average packet sizes for virtual worlds, but with a corresponding increase in processing on the receiving end. This is less of a hurdle now than it was just a few years ago, thanks to jumps in processing power, and the trend will continue. Additionally, such equations can provide for more complex and curvilinear models, flexibility in sizing and resolution, and smoother animation. Many non-polygonal algorithms are already well optimized since they have been de rigueur in high-end 3D animation for decades, and are now, or always have been, in the public domain.

3D volumetric representation is a powerful technique for implementing virtual environments. However, the computational requirements are high, data-sets large, and the availability of modeling tools for such an approach is low. Therefore, for the time being, we use surface representations--bicubic equations (patches) and NURBS ("non-uniform rational b-splines")--to describe objects' geometry. (Gel also supports traditional polygonal models.) From the patch or NURB description, objects are expanded via tessellation into triangles and exported to the local machine's graphics card for rendering. This tessellation approach is flexible enough to support implicit surfaces and other kinds of surface description as processing power increases.

In contrast to a complex polygonal object, an object described in the manner above, using functions and control points, is far easier to animate on the receiving machine. Such multi-modal representation allows for more complex, naturalistic models and better animation, while saving bandwidth.

2) Peer-to-Peer Networking

The strength of the Internet--its democratic structure--is also the source of its biggest liability: latency (transmission delays). Some degree of latency is unavoidable. Packets travel through routers and other intermediary machines, and encounter physical delays before they get to their destination. In all cases, the user’s experience of interactivity is strongly dependent on the means by which events are distributed between machines.

The current approach using client-server architecture automatically--and >unnecessarily--doubles whatever latency may be inherent at a given moment. To get from one client to another, control is forced to flow via the server rather than directly between the clients, going up to the server and back to the client instead of point-to-point. For clients communicating via a remote server, the delays can be considerable. Centralized servers have the added economic and social disadvantage of requiring large amounts of bandwidth and processing power to deal with simultaneous connections by many users.

With Gel, we dispense with the current client-server architecture altogether. Any machine can be a client, and any machine can be a server. Machines communicate directly with one another in a "conversation." They all share essentially the same set of objects. If an object is created in one machine in a given conversation, then that object (or more properly, a segment of "graph" describing it) is propagated to all the other machines that need to share the view. The relevant part of the database is thereby kept consistent across machines. Each machine gets an object only if it is part of a relevant conversation. All of the machines in the conversation take on a share of the work normally performed by the old-style server. Because there will always be varying latencies between machines, we observe these latencies using a method of global time stamping derived from Network Time Protocol (see below) to discover which machines are closest (time-wise).

3) Global Time Stamps

Another interactivity-related issue for online virtual worlds is that of synchronization and "locking." If two users try to pass through the same door at roughly the same time: Do they collide? If not, who is allowed to go first? How can the different machines know which event occurred first?

All events/packets transmitted in Gel’s peer-to-peer conversation receive a global time stamp, derived from Network Time Protocol (NTP). NTP is a well-researched and tested standard; Gel machines will use both conventional NTP servers and each other to set, and periodically refresh, their own global clocks. This mechanism, using contemporary connections, allows times on the different machines in a conversation to be closely synchronized. When an event arrives at a machine, we can examine its time stamp to see approximately when that event occurred. The use of time-stamping also allows Gel worlds to be interfaced with real-world real-time processes (e.g., weather).

4) Click and Drag Authoring in 3D

The use of graphs as a programming paradigm provides for a new kind of 3D user interface. On one level, it makes building worlds more accessible to non-programmers/end-users by unifying scene and object descriptions with behavior descriptions. On another level, it brings programming out of the realm of purely abstract conceptualization down to a more visually concrete, spatial framework. Considering that as a species we have evolved using our spatial sense to manipulate and analyze complex objects, why not apply this proclivity to the realm of software? Representing programs as a group of 3D objects connected in space takes the click-and-drag metaphor to a deeper level, where programs can be assembled like tinkertoy structures.

Imagine, for example, that you are using Gel to create a room. In the room there is a piano and a vase. It is possible to have Gel generate a 3D diagram, made up of 'visualized' nodes and edges. The diagram floats (perhaps translucently) over the image of the room itself. The nodes have name-tags--"Piano" and "Vase." There is also a third node labeled "Room." Right now the "Piano" node and the "Vase" node are both linked to the node for "Room," as they are both contained within the room.

In Gel we call the generated "Room," "Piano" and "Vase" nodes 'representations'. Think of them as stand-ins or icons for each of the objects in your virtual space. Given that the 3D diagram (graph) depicts the underlying scene description, we can expand the graph to view more of the scene description, or add to it. In our case, we add a "Group" node between the Room node and the Piano and Vase nodes. Using click and drag, we connect the Piano and Vase to be part of the same Group. This designates from the scene description point of view that the piano and vase are now connected in a larger whole--if you move the piano across the room the vase must now move with it. Both vase and piano nodes may be clicked on to reveal further details of their properties (which may display either as menus, dialogs or further node-edge structures).

This type of click and drag graph manipulation doesn't just cover scene graph editing. Multiple layers of representations can reveal the "wiring under the dashboard" of the entire scene, and a full 3D visual programming environment exists within Gel. In the case of our piano example above, there may exist one layer for the behavior associated with each object or group of objects, another layer for the definition of each object's visual appearance, and yet another layer for the spatial relationship of objects in the scene as a whole. This interface philosophy follows the model of architectural transparencies, in which different aspects of a building (plumbing, wiring, structural, etc.) are overlaid one atop the other in relation to their location.

One of the unique things about Gel is that it uses itself to visualize itself, in 3D, using the representations mentioned above. Virtually all of the system is viewable in a visual manner, and the system can be used to view external systems, such as pieces of the net, or other object structures.

5) Distributed Processing

Currently the type of programs and scripts used for commercial Internet-oriented 3D environments inherently preclude transmitting small changed portions separately from the entire body of the program. The ability to ship only changes would allow for virtual worlds with malleable, rather than fixed, environments. In other words, users could alter their environments’ appearance and behavior live, in process, rather than being forced to navigate in and "interact" with a basically fixed, predefined space.

Gel makes use of a programming technique known as "late binding"--in tandem with the definition of scenes and behaviors as graphs--to do just this. Relevant portions of graphs can be copied, exchanged and integrated into their appropriate places on remote Gel machines. Thus only needed sections have to be moved over the Net, with the result that most packets shipped--for behavioral descriptions, at any rate--will be extremely small. This also means that live changes (again, in scenes, objects or behaviors) can be distributed and integrated rapidly, improving dynamism. In other words, a Gel world is inherently a distributed environment. Pieces of it rest on different machines, and these pieces are constantly exchanged back and forth in Gel conversations as needed.

6) Open Source plus Plug-ins

The advent of virtual worlds as a mass medium is being held up by the proliferation of narrow proprietary solutions. Each of these competing solutions has its own particular drawbacks. Together they limit the possibilities of a broader industry. What is needed is a more universal, open-ended environment free of the limitations of past initiatives. Such a project, however, is too large for any one team to complete on its own.

Therefore we offer Gel as a skeletal but coherent system needing to be fleshed-out by a larger community of developers. Anyone using it is free to commercialize and ship it with their applications and extensions. Such developers are not required to ship the source code with the product to end users. However, parties that add to Gel are expected to contribute to the development and proliferation of the system.

We designed Gel from the outset with this collaborative scenario in mind. With modular APIs and an open, plug-in architecture, it will be easy for other parties to adapt and extend Gel without modifying the core source code.

7) Portability

The need to write applications for multiple platforms, and the constant, unpredictable evolution of the industry, are major issues for any proposed standard such as Gel. Technologies such as set-top boxes (WebTV), game boxes (Nintendo, PlayStation), and others yet unknown, need to be considered from the beginning as potential platforms for any new 3D Internet environment.

Gel is therefore written primarily in portable C++, so that it can be compiled to run on virtually all current, and most foreseeable, platforms with only a small amount of porting for system-specific classes. It will be compact enough to be easily downloaded, and for most current purposes will operate as a browser plug-in.

Summary

We believe Gel to represent a major advance in software for building online virtual environments. The points where previous efforts have foundered--smooth interactivity, dynamism, realistic modeling and animation--are where Gel begins. A cohesive set of technical solutions--some original, some adapted from earlier efforts--makes this possible.

Gel's innovative Graph Evaluation Language, the conceptual core of the system, underpins three of these. By allowing graph structures to be shipped around the net in synchrony, the Gel environment makes possible environments that are inherently distributed, multi-user, and interactive--environments that can be built collaboratively, live, in real time. At the same stroke the Graph Evaluation Language promises to put programming into the hands of the end-user with a new visual authoring paradigm. And on yet another front, Gel facilitates peer-to-peer networking for lower lag in small group scenarios.

Gel's other two key solutions are its adoption of non-polygonal rendering and global time-stamps. Non-polygonal rendering will allow for more naturalistic, curved surfaces and better quality animation. And time stamps, by keeping all Gel-users in a given conversation synchronized, will help to ensure a smoother interactive flow. We anticipate that once Gel has been fully fleshed out with the help of the open source community, the cumulative result will be a virtual experience significantly more responsive and visually compelling than has so far been possible.

ADDENDUM: THE QDRAW RENDERER

Gel incorporates an open source rendering module called QDraw, from Qube Software, London. QDraw is a graphics API for 3D rendering at the immediate mode level. It works on any current PC, and can communicate directly with an accelerator card or indirectly through the other major 3D APIs: Direct3D, OpenGL, and Glide.

Like the rest of Gel, QDraw is written in highly portable C++, making it easy for third parties to adapt it to run on other platforms. It also facilitates the addition of custom drivers for new hardware. Currently QDraw runs on Windows98/NT, Linux, and FreeBSD, witha version forthcoming on Sony PlayStation II.

QDraw gives the application developer maximum flexibility and ease of use in accessing and manipulating the low-level 3D functions. It does not aim to duplicate the entire scope of Direct3D and OpenGL, instead it provides the essentials in an efficient fashion, plus a few features not found elsewhere. The program includes support for full multi-texturing, a stack-based paradigm for transform matrices, portal rendering techniques, and tools for importing models and merging vertices with shared contents. It also significantly reduces the code overhead in initializing a program and putting up a window. QDraw also includes an independent open source math library module, QMaths, for common 3D objects.


Vecta3D
http://www.vecta3d.com/ , http://www.ideaworks3d.com/main/


Viewpoint

Viewpoint的前身是MetaStream

Viewpoint是一家领先的网络高端媒体(rich media)可视化解决方案提供商，Viewpoint可以创建照片级真实的3D影象，并且可以和其它高端媒体综合使用，更加引人注目的是在目前窄带环境里Viewpoint同样可以发挥她逼真的效果。目前Viewpoint公司已经为Nike, Sony, Eddie Bauer和Sharper Image等公司提供了在电子商务以及在线广告方面的解决方案。Viewpoint同样为娱乐业、广告业的客户提供全球最大的3D模型库，3D模型设计。Viewpoint公司的总部设在美国纽约 ，在洛杉机、三藩市、盐湖城、伦敦和东京分别设有分公司。

Viewpoint技术是由真正的3D模型建立的，所以她具有完全的互动功能，可以真实地还原现实中的物体功能，我们可以使用Viewpoint技术带给你更加真实的虚拟世界，正因为人们对网络目前的内容体现形式并不满意，Viewpoint则是最好的解决方案之一。

对于窄带应用上，Viewpoint所提供的技术也是最好的解决方案之一。她使用独有的压缩技术，把复杂的3D信息压缩成很小的数字格式，同时也保证我们的浏览器插件可以很快的将这些压缩的信息重新解释出来。在3D贴图上，我们使用JPEG的压缩格式，保证文件的贴图不会使3D文件加大。并且她传送给用户的方式像Flash、Quicktime、Real media等流行媒体一样，使用了流式播放方式，这就使用户不用下载完所有的文件即可看到Viewpoint的内容。

Viewpoint 制作工具

Scenebuilder

  这是制作Viewpoint的主要软件，将3DMax导出的.ase文件或是MTS2的.mts文件进行互动编辑后输出Viewpoint的.mts和.mtx文件。使用时要将屏幕分辩率调到 1024 x 768 或更高。

Mtx2Html

  MTX to HTML 用于把做好MTS和MTX文件嵌入网页文件html中，自动加入HTML文件需要的Java Script代码。

Stream Turning Studio

  Viewpoint模型优化软件，主要用于优化Viewpoint模型，对3D模型的多边形面，表面贴图压缩比、表面颜色进行交互式的编辑，优化后文件明显的缩小。

Viewpoint Media Player

Enhance iPIX Panoramas
Viewpoint 3D Photo Studio
Cinema 4D XL
Cinema 4D XL VER 5.29 的特点在于快速的渲染、基于多边形的造型方式、即时阴影和透明、抗锯齿等等。另外，Cinema4D XL 支持多重处理、批量渲染和可输出的Alpha 通道。XL 还可以输出各种广播级质量的图片与动画，还支持很多种外部格式如 DXF、VRML、Lightwave 和3D Studio的格式
MetaStream

MetaStream 3D文件格式是由Intel公司及MetaCreations公司联合发布的新兴的网上3D开放文件标准（基于Intel构架）。基于此标准，我们在网上可以非常方便的创建、发布及浏览可以放缩的3D图形，由于其小文件量及流传输的特点，该标准一经发布就深受好评。这个基于Intel架构的开放文件标准的发布使得长久以来电脑游戏及Internet商业使用统一标准开发成为可能，它将很快对3D处理方面带来巨大的冲击。

MetaStream格式的物体是可以缩放的。这意味着Metastream 3D格式的物体可以自动的调节精度及其它相关参数以获得最佳表现。游戏开发商只需开发一次高解析度的模型就可以满足游戏中不同层次精度的需要以减少开发时间。Web开发商则可以通过这项技术让用户端自行设定3D模型的精度及光滑程度以给予用户最大的自由度，亦可通过这种调节减少下载时间。用户可以非常方便的根据自己机器的处理速度以及modem的速度来对Metastream物体设定不同的精度以获得最佳感受。MetaStream格式的文件非常紧凑，它比其它任何一种已存在的Internet 3D技术压缩比都更高，其极小的文件量使得在网上浏览Metastream3D物体非常快捷。 　　用户端只需安装一个简单的插件（该插件是免费的）就可以在网上浏览到以流方式传输的3D模型，同时用户端还可以对该物体进行旋转、缩放等控制。

应用领域

游戏开发：设计者可以更为快捷的通过这个统一的标准制作高水准的动画，并且只需开发一次高解析度的模型就可以满足游戏中不同层次精度的需要以减少开发时间。

页面设计：可以为网站加入引人入胜的3D内容。

电子商务：在线购物者可以在购买前随意的旋转及放大商品以全面判别商品的质量，就象在真正的商场里做的那样。通过这种方式，网上购物 会更加符合人们的习惯。

科学研究：分散在各地的研究者们可以通过在网上共同分析一个3D物体以达到群体性研究的目的（例如网上会诊）。

网络展示：展示者可以通过这种方式来创建网上的生动立体的仿真展示会。

专业设计：专业设计者可以通过这种方式在作品中方便的将2D物体及3D物体融于一体。

如何制作

MetaCreations' 3D 的图形设计软件是Ray Dream Studio 5 以及Ray Dream 3D。拥有这些软件的人只需要在网站上下载一个免费的升级文件就可以通过这些软件来制作Metastream格式的物体了（这是由于Metastream标准发布的比这两个软件晚）。而刚刚推出的Infini-D 4.5则是第一个内建Metastream标准支持的3D制作软件。Ray Dream Studio 5 以及 Ray Dream 3D支持DXF, OBJ和3DS(3D Studio)等多种文件格式的导入。这意味着其它的3D处理软件制作出的3D物体可以在Ray Dream中导入以生成支持Metastream的文件格式。 　　此外，Real3D公司最新发布了一项新产品--RealScan 3D照相机。这是一个三维的扫描仪，只需对现实中的物体进行拍摄就可以生成这个物体的3D模型，这个模型是自动保存为基于Intel架构的MetaStream 3D 格式的。这样，即使不懂3D创作的人也可以非常简单的发布自己的3D模型了。

系统需求

基于Pentium?处理器的PC机 Netscape Communicator 3.x（或更高版本） 或者 Microsoft Internet Explorer 3.02 （或更高版本） 28.8 modem

Real3D
为 了 制 作3D 图 像， 另 外 一 家 名 为Real3D 的 公 司 设 计 了 一 种 称 为RealScan 3D 的 扫 描 仪。 这 种 扫 描 仪 实 际 上 是 一 部 照 相 机， 它 摄 制 实 物 对 象 的 数 字 化 照 片 然 后 将 之 转 化 为MetaStream 的3D 文 件 格 式。

1、3DS MAX输出ASE格式

2、ASE导入到Scene Builder中

3、在Scene Builder中加入交互控制，输出MTS和MTX

4、把MTX嵌入到WEB中

5、安装Viewpoint Media Player即可浏览。

准备：SCENEBUILDER 、MTX2HTM、全景图片一张

1、打开SCENEBUILDER，打开右边的GLOBALS标签，选LOAD CYLINDRICAL PANO...命令，导入你的全景图片。

2、把camera mode 设为pano

3、把shadows 设为off

4、调节show camera constraits 为ON，并把camera scale min 和camera scale max 分别设为0.5和1.5。

5、发布MTX和MTS

6、打开MTX2HTM，把你输出的MTX文件嵌入到网页里，在嵌入的时候别忘了输入BROADKEY。

7、浏览你输出的网页，看是否有不对的地方，可以调节MTX在页面里的宽度和高度。当然也可以从SCENEBUILDER重新设置。


Virtue3D

Virtual3D
http://www.virtue3d.com
Developer Toolkit

Virtue3D Optimizer

Virtue3D Optimizer significantly optimizes and transforms large 3D models into highly efficient, compact Web-ready files called VTU's. The Virtue3D Optimizer can compress 3D content down to 1% of original file size.

Features:
Effortlessly converts large and complex 3D models into VTU file format
Provides the best compression available in the market, reducing files to 1% of their original size
Offers up to 100% Loss Less Compression
Includes customized compression of geometry, image and animation
Generates Levels Of Details (LOD) for ordered 3D content download and streaming
Features customization of the model's appearance
Supports import from VRML 2.0, 3DS, OBJ, PLY, STL and DX

Virtue3D Max Plug-in

Virtue3D Max Plug-in extends Discreet 3ds maxTM to include an export utility for 3D content prior to optimization by Virtue3D Optimizer

Features:
Direct input to Virtue3D Optimizer
Creates optimal results for use in Virtue3D Optimizer
Enhanced to produce a more complete data output
Exports both simultaneous and independent animations, complete with interactions
Efficiently preserves animation, material and hierarchy data
Supports native 3ds max features like smoothing and particle systems
Preserves high-level of accuracy VRML 2.0 compliant file output
Compatible with 3ds max 3 & 4

Virtue3D Dreamweaver Extension

Virtue3D Dreamweaver? Extension is an add-on for Macromedia? Dreamweaver? that enables Web developers to seamlessly embed the Virtue3D Player into Web pages. The Virtue3D Dreamweaver Extension uniquely provides a dialog driven Property Inspector and Behavior Editors with which to define, control and customize interactive 3D content to the smallest detail.

Features:
Integrates Virtue3D content with Dreamweaver's object component tray
Inline editing via intuitive dialog driven interface within the Dreamweaver environment
The friendliest way to make use of all theVirtue3D Player API features
No programming experience required
Effective Property Inspector for management of advanced VTU properties like background color and lighting
Powerful Behavior Editors enable automated JavaScript generation for customization of major content properties like animation and texture
Compatible with DreamWeaver 3 & 4

Virtue3D Player

Virtue3D Player is the smallest available browser plug-in for optimal rendering and interactive viewing of Web 3D content. Virtue3D's rich and extensive Player API allows developers to interface directly with the Virtue3D Player, controlling almost all aspects of the scene and how the user interacts with it.

Features:
Smallest 3D Web viewer available
Easily embedded into Web pages with a rich API
One-time download by the client browser
Automatic upgrade detection and update
Interaction using any standard pointing device
Default controls for single objects or complex scenes include: rotate, zoom and pan functions
Advanced control of animations, textures, lighting and more via an extensive API and library of JavaScript functions
API accessible using JavaScript calls embedded within an HTML page, from Java applets, and via independent controls, that may be developed by any Web developer
Supports Internet Explorer, Netscape, AOL Web Browsers
Virtue3D Room Designer

A textbook example of how businesses and consumers alike can benefit from Virtue3D's revolutionary technologies.

The Virtue3D Room Designer is a Web based 3D application that enables the furniture industry to present user-configured furniture items in their "natural" environment in real-time. Integrated on several furniture manufacturers Web sites, Room Designer provides users with personalized design of environments and items and a fully interactive virtual walk-through experience that realistically simulates a real-world experience.

Virtue3D Online Training Applications

Complex techniques and processes are more easily communicated over the Web using Virtue3D's revolutionary technologies.

Virtue3D's technology simplifies processes and brings them alive. Using Virtue3D's tools and technologies to create Interactive 3D User Manuals, users benefit from full 3D detail and motion at a perspective of their choice. Companies provide their customers and technical staff with an on-line instrument, simplifying and making learning faster and easier.

Web3D Applications for Any Vertical Market
It is not hard to imagine how the concept of Interactive Web3D Applications, using Virtue3D technologies, can be replicated to deliver a wide variety of applications for virtually any market, including: Entertainment, Environmental Planning, Architecture, Computer Based Training, User Manuals, Apparel, Geographical Information Systems, Simulation … and many more.

Virtue3D's SDK enables authors of software developers to integrate Virtue3D's compression technology into third party applications, allowing the smooth conversion and delivery of 3D content within other platforms, therefore enhancing the 3D experience.

Virtue3D's compression far surpasses that of the competition because it uniquely handles geometry, image and animation compression and extraction, delivering the world's leading compression ratios.

Geometry Compression

Virtue3D compresses mesh connectivity, geometry and other 3D content properties, saving up to 99% of the space required to store 3D models.

Image Compression

Virtue3D's image compression significantly reduces image storage size, enabling images to be streamed in a significantly reduced amount of time.

Animation Compression
Virtue3D's technology compresses 3D animation sequences containing both rigid-body and soft-body motion data, reducing the memory footprint of an animation sequence.

Virtuoso


Viscape

Superscape
-http://www.superscape.com/
Viscape
Another pioneer in 3D on the Web. They've kept active in the Web3D Consortium while still pursuing their own vision. Their rendering is especially leading-edge.

What is Superscape e-Visualizer?

Superscape e-Visualizer (SeV) is an innovative technology, designed for the Web, that allows designers to integrate photorealistic interactive 3D content with other components on their Web pages, to deliver a rich media solution that has not previously been possible. SeV has an extensive Java interface and is compatible with other existing rich media technologies, allowing companies to develop compelling and attractive Web sites that will encourage users to explore them and return regularly.

SeV removes previous restrictions on graphical Web sites where users would have to download time consuming 2D graphics or install a separate browser for 3D objects, by displaying photorealistic, or 'toon-like', interactive 3D content with file sizes that are typically less than the equivalent 2D image. The browser, which enables users to view and interact with the objects, downloads almost instantaneously and installs seamlessly.

SeV is an extremely flexible control whose uses are limited only by the designers imagination. It can be used to visualize single objects on ecommerce sites, display immersive environments for training or simulation, agents on Web pages or computer desktops, or simply for 2D and 3D graphical effects.

If you want the content to look exactly the same on each system, regardless of the users PC or graphic card, content can be displayed using the optimized software renderer. Alternatively content can be displayed with the DirectX hardware renderer giving blistering performance and quality.

Processor friendly, SeV does not use unnecessary processing power required by other applications when idle. However, it does use the processor to generate the 3D content on the client system using the subdivision surface technique, rather than wait for large downloads.

SeV works with the two most common browsers: Microsoft Internet Explorer and Netscape Navigator, versions 4.0 or later, under Microsoft Windows 95, 98, NT 2000 and ME. The technology is also available as a full ActiveX control, 3Dcontrol2000, for embedding in ActiveX containers such as MS Visual C++, MS Visual Basic, or MS Office applications.

Patents have been applied for on this new Superscape technology.
I3D - implementation in the real world

Superscape's i3D technology is being implemented in a wide range of sectors. The power of i3D can be used to enhance existing processes, replace traditional method or visualize items and environments which do not or may never exist. Some example areas of application include implementing i3D:

as an effective medium for training staff on health and safety issues, and as proven means of aiding retention of complex information
as a visual, cost effective method of educating sales teams and distribution channels on the latest features, functions and operation of new products
to enhance customer relations and reduce call centre costs by simplifying customer support using the internet
to streamline decision processes through innovative methods of visualizing static data
as an enticing method of stimulating consumer interest and accelerating the buying cycle
to have fun - creating best selling games, invigorating web sites and delivering entertaining content


Visviva
--http://www.visviva.com/

Visviva Authoring Studio: VAS 1.5.

Announcement for 1.5 upgrade: Visviva Software, Inc. is proud to announce the newest upgrade for the Visviva Authoring Studio: VAS 1.5. This upgrade is our best ever, and it contains a number of useful objects that streamline the development process even more. Click the link at the left to view the new features.

If you've ever wanted to create professional presentations with TV-quality 3D multimedia effects... If you've ever thought about creating interactive training sessions and course content on CD-ROMs or on Web pages... The Visviva Authoring Studio is the solution you need.

So why should you choose the Visviva Authoring Studio over other presentation or authoring products? Because those static, plain vector or faked 3D presentations are stale, and you want something real and unique, with genuine 3D, to grab your audience's attention.

The Visviva Authoring Studio is the only authoring tool that completely integrates distinctive elements such as object design, animation composition, 3D modeling and composition, image painting, vector drawing, and hypertext editing. The Visviva Authoring Studio provides rich, stylistic expressions with an amazing variety of design choices, including over 500 different classes and types.

Complex particle systems, branch systems, dynamic textures for natural phenomena, vector effects, digital books, group animations, and 3D data charts are just a few of the many components you can create and customize to your specifications. Each Visviva Authoring Studio object contains a rich set of functions and attributes, and gives artists an unprecedented amount of control over object behaviors.

ScriptV is a very powerful dynamic object-oriented language that is used to describe all objects, classes, and functions created, automatically or manually, from the VAS. However, ScriptV is designed to be a general-purpose script language. It provides all the advanced features that you may find in other modern script languages. It is a complete, stand-alone object-oriented language, and can be compared to Java, Python, or SmallTalk.
The quickly expanding field of computer graphics/animation has introduced many new dimensions of applications that make more and more requirements on specific language features to support things like object-orientation, parallel computations, persistent objects, internet authoring, multi-player interaction, and event-driven simulation. As a result, many proprietary languages are introduced for specific products, and unfortunately, a great deal of these proprietary languages are handicapped, stuffed with many product-oriented features, and cannot exist alone.

ScriptV is designed in a different philosophy. Instead of being stuffed with product-specific features, ScriptV provides a transformable abstraction vehicle that is flexible enough for users to tailor to their own domain-specific "dresses". This enables a flexible framework for various applications, which include the specific features required by the Visviva Animation Engine. ScriptV provides a customizable dress that shapes software concepts faithfully. You may find that ScriptV has remarkably fewer concepts than other languages. Its unification makes the fixed and built-in part (the hard part) of the language framework smaller, while the user-definable part (the soft part) becomes larger so that the framework is flexible enough to build various domain-specific application models. ScriptV's flexibility and adaptability are what give it an edge over other script languages


VRInteractive

VR Interactive Inc.
www.surroundphoto.com
Surround Photo V2.0
开发者称这个软件“可迅速、廉价制成全景照片”。这个免费软件将展开用SurroundPhoto Reflector拍摄的照片，几秒钟之内，弯曲的原始照片即可转化为全景照片，可以进行存储，打印和发送。用户可预览和存储多张带有水印的QTVR图像，无需任何费用。


Wild Tangent
--http://www.wildtangent.com/

SDKs
Web Driver SDK Full

The Web Driver 2.0 SDK in combination with WTStudio provides everything you need and more to make cutting edge multimedia web applications. This SDK contains tools, documentation, demos, how-to's and tutorials that you can use to get up and running with the Web Driver.

Web Driver SDK Base

Web Driver 2.0 SDK Base install in combination with WTStudio provides just what you need to make cutting edge multimedia web applications.

Web Driver Training Package

Here is the package of demos, how-to's , templates, and tutorials contained in the Full SDK download.

Multiplayer Toolkit

Take your WildTangent content to the next level of interactivity! This toolkit will get you started with a simple how-to and full documentation.

Tools
WTStudio

A world editor for creating BSP geometry that can be loaded into your scene. Use WTStudio to quickly and easily prepare an intense scene for your Web Driver project.

3ds Max Exporter

Bring your 3ds max geometry, materials, and animations into the Web Driver. Export from 3ds max directly into a web page! This new version supports bone promotion and environment mapping.

Maya Exporter

Bring your Maya geometry, materials, and animations into the Web Driver. Export from Maya directly into a web page! This new version supports bone promotion and reflective mapping.

WildCompress

A compression and copyrighting tool that will prepare media for use with the Web Driver. Use it to compress and encrypt Bitmaps, Models, and Sounds for your Web Driver scene. Adjust the level of compression and protection for media you use with the Web Driver.

Packager

Packaging utility that allows for easy packaging of all your Web Driver projects including Visualizers and Screen Savers. Use WTPKG to bundle all your project files in one .exe ready for distribution with the latest available install of the Web Driver.

Documentation
Web Driver API Help Reference

Now you can take it with you... the Web Driver API in HTMLHelp form.

Media
3D Studio Max Samples

Sample 3D Studio Max files for several Actors.

WTStudio Sample Project

This package provides a sample WTStudio project setup. Sample Actors, materials, and sounds are setup in their proper directories and ready for use in WTStudio.

Viewers
Web Driver Media Viewer (WTViewer)

WTViewer provides a quick and easy way for you to view WildTangent content. Just drag and drop a model, texture, or sound onto the viewer for a look. The viewer includes the ability to preview compressed images and work with hierarchical models.

MapStreamTM
MapStreamTM is the fastest, easiest and most interactive way to view maps on the Internet! Using WildTangent's powerful and flexible Web Driver technology and ESRI's RouteMAP IMSTM, MapStream streams interactive, multimedia maps over a narrow bandwidth to the consumer's PC with minimal wait. MapStream's unique Web Driver technology enables the consumer to pan, zoom and search for address locations without having to wait for the screen to refresh.

Check out MapStream today at www.mapstream.com.


3cx

http://www.3cx.com/
3CX通过对计算、通信、消费性电子技术的集成，使得实时多媒体信息在Internet,Intra-net和数据TV网络上实现交换，并提供领先的多媒体通信解决方案。
3CX提供业界领先的解决方案:

●流式媒体

●远程教育/培训

流式媒体

3CX流式媒体解决方案提供了高质量的MPGE-1、MPEG-2视频播，以及实时的演讲、会议、简报和监控的MPEG广播。3CX提供的流式媒体解决方案满足了您的多媒体信息交换的所有需求。我们的目标是提供高质量的流式媒体，3CX流式媒体解决方案提供了最优的音频及视频质量。

远程教育和培训

3CX提供了高质量的视频资源管理工具，包括了安全、同步的、基于Web的带有PowerPoint展示的视频和视频索引。另外，还提供了安全的基于Web的视频搜索引擎。
IXJET Streaming以Client/Server结构为基础。
IXJET Streaming是一个提供了视频内容管理的服务器管理工具。另外，IXJET Streaming监控视频流的回放状态和通过对事件的日志记录报告任何不寻常的情况。使用IXJET Streaming，可以把视频流嵌入Web浏览器。图示表明了整个IXJET Streaming的体系结构。IXJET Streaming由五个主要部分组成：服务器、存储子系统、网络接口、 网络框架结构、客户端
IXJET Streaming将高质量的多媒体内容传输到成百上千个网络客户端。客户可以在任何时候观看存储在服务器内的多媒体视频内容。使用可控制的流式技术，只要在客户端的磁盘空间里有一小部分媒体数据存在，客户就可以开始观看该媒体，不像下载或简单的流式技术。可控制流式技术动态调节系统行为来适应意想不到的网络交通阻塞，从而保证服务质量。媒体服务器具有提供保证的媒体回放质量和用最小的启动延时进行传输的能力。这点对于交互式应用、卡拉OK、多媒体导购等等，是非常重要的。IXJET Streaming的可控制流式技术符合了这些应用需求的所有主要要求。
IXJET Streaming可以通过Internet、公司内部的Intranet、无线网或者卫星，把财经市场即时变化的信息、世界新闻、公司简报、讲座、研讨会和公众节目传送给全球任何可以到达的PC上。除了实时广播，IXJET Live还可以把空中的实时视频/音频信号进行编码和存储，提供以后重新广播。它也通过流行的WWW提供一个强有力的编程指导。所有观众可以即时观看到实时广播。

IXJET Live可以和IXJET Streaming无缝集成，传送实时的和预先存储的视频节目。一台Windows NT服务器可以支持3个MPEG-1压缩广播的现场频道。观众既可以收看来自模拟视频信号源的节目，也可以通过任何Web浏览器收看在IXJET Streaming上预先存储的视频节目。它可以传送很多需要广播的节目给无限数量的观众，以满足各方面不同需求。Live可以在Windows95/98和Windows NT 4.0/5.0上运行。
IXJET Explorer是一个主要为公司培训和网上教学而设计的在线式学习工具。它基于IXJET流式技术，提供在线的高质量的视频观看、课程讲座和基于Web的多媒体浏览。通过Internet和公司内部的Intranet，可以更加方便地进行公司培训和网上教学。无须本地存储要求，最终用户可以通过方便的鼠标点击，获得在线资源。

IXJET? Explorer遵照当前和将来的教育及Web标准,创建一个无限的、虚拟的学习环境.它可以方便地扩展到由IXJET? Streaming Server 提供的800个并发视频流. IXJET? Explorer同时提供“管理员”和“浏览者”两个版本。两者都运行在Microsoft Windows 95/98或者Windows NT 4.0/5.0下。

IXJET Explorer是基于软件结构设计的一个部件中心模块。通过Key地址技术优势在网络数据视频流和Web 上提供一个“生动的桌面”，就象超媒体用户接口。使用3CX的部件和应用builder,最终用户可以重新配置和组成他们自己传统的Web超媒体应用。可能利用的应用包括：公司培训，远程教学，多媒体导购，卡拉OK点播等。

IXJET Presenter为基于Web网络环境的同步媒体写作和演示带来了革新。通过先进的部件技术，IXJET? Presenter不仅可以播放来自IXJET? Streaming的高质量视频，还可以播放其它媒体格式，如Microsoft Netshow ? 的Active Streaming Format(AS F格式)和RealNetworks'RealServer?的RealMedia?(RM格式）。视频注释和幻灯片演示功能是这种流式媒体解决方案的一个组成部分。因此，它是网上点播方式学习与演示、POS和信息广告亭应用的理想工具。

IXJET Presenter提供了基于时间表的写作环境.文本注释和幻灯片演示内容可以方便地加入到视频/音频叙述中.它的步进式发布实用工具帮助内容创建者将同步媒体演示的最终结果发布到Web服务器上.通过非线性可视化的控制,用户能够在需要重复和仔细观看的地方来回切换.

IXJET Presenter具有Web方式的管理实用工具，实现了Windows NT域内访问控制的身份验证。学校和企业内的用户可以定义他们的流式媒体需求，并且选择用户，授予其写作和观看的权利。安全套接层接口规范增强了在公共网环境中使用时的数据完整性。IXJET Presenter可以运行在Microsoft Windows95/98,Microsoft Windows NT4.0/5.0上。
http://www.ustcn.com


ACCORD
MGC-100多点会议控制器

1. 系统描述

ACCORD公司的多点控制器MGC-100完全符合H.243国际标准，满足图像、语音和数据的会议电视标准。主要功能在于支持多个编解码器(Codec)组成的会议电视系统，让多个会场同时参加同一个会议，或分别同时召开各自的会议。这样，借助多点控制器，对于建立一个多点的会议电视系统来讲，既提高了工作效率，又降低了成本。

MGC-100是下一代符合ITU-T标准的多点控制/网关（MCU/Gateway）解决方案，它能够在单个MCU平台上实现ATM、IP以及ISDN等网络的多媒体视讯终端的实时交互通信。MGC-100开创性的结构、强大的功能以及优越的性能价格比必将为视频多媒体领域带来革命性的发展。 创新的结构

电信级结构设计，支持电源热备份，所有插槽通用并可自动识别硬件模块

适合于ATM、IP以及ISDN等通信网络

集成最新的网络接口和最新的国际标准于一台设备平台

所有类型的网络接口支持增强特性

无所比拟的性能价格比：

ISDN网络支持8~84点

ATM网络支持8~80点

IP网络支持12~132点

空前的可靠性

系统及模块前面板LED指示，能够尽快发现问题

在线诊断能够预知任何可能的问题

所有模块支持：

前端直接取放

带电热插拔

自动配置

三个可带电热插拔的电源模块槽位，所有负载共用电源，电源模块互为热备份

2. 系统功能

完全符合ITU-T H.261、H.263 (FCIF, QCIF)视频编码标准
完全符合ITU-T G.711、G.722、G.728音频编码标准
全面支持ITU-T T.120系列标准的各项功能
完全符合ITU-T静止图像标准H.261 ANNEX D
远端摄像机遥控(H.DLL，H.FECC)
会议地点名称文字化
具有多个MGC-100级联的能力：符合ITU-T星形配置，三级级联。
MGC-100有五种视频切换方式：
(1). 主席控制：利用MGC-100组成的多点会议电视系统的每个会议点，经过申请都能成为该会议的主席，同时具有广播选择权和整个会议的控制权。

(2). 声音控制：在多点会议电视系统中，每个与会者的声音经MGC-100后成为混合方式，即每个点能同时听到其他各点的声音。这样在声控方式下，MGC-100自动根据与会者发言音量的大小，将图像自动从一个会场切换到声音较大的会场并广播出去。

(3). 直接控制：每个与会者的状态（包括图像、声音和数据）都很形象地显示在与MGC-100相连的工作站的监视器上，管理者通过鼠标操作，可直接控制会议。

(4). 持续显示方式：支持5种不同的动态显示模式（2，4，5+1，9分屏或全屏），当前所显示的会场可在会议过程中随时更新，每个子画面都可以是固定会场或声音激励会场。 (5). 自动浏览：在主席控制或演讲模式下，可以设置为主席会场和演讲者可以自动浏览其它各分会场。

完善的诊断测试功能

所有系统硬件开机自动检测

在线监测系统硬件

MGC管理软件界面上在线显示所有状态（包括硬件、会议、会议点等等）

MGC管理软件界面上所显示的硬件模块与MGC-100插槽模块配置动态保持一致

MGC管理软件界面上显示当前正在使用的硬件资源

MGC管理软件界面上显示音频和视频同步丢失

对所有ISDN线路状态监视，并可记录24小时之内状态（包括误码率、CRC错误等）

历史事件记录

硬件故障后自动恢复能力

方便的软件升级能力

可通过TCP/IP远程下载软件

带电热插拔的硬件模块可自动更新其软件版本，与MCU最新版本保持一致

免费软件升级

系统时钟：MGC-100可选择由：内部时钟；外部时钟；信道传输数据码流。三种时钟源之一提取系统时钟，作为全网的同步时钟。

3. 系统特点（优越性）

多重协议自动转换

系统设计为H.3xx网关 + 多点会议功能（内置H.3xx网关）

支持不同速率、音频算法、帧频、分辨率、以及不同T.120数据速率会议电视终端之间的混合会议（如下图所示）：

音频 G.711,G.722,G.728,G.723

速率 64Kbps~1920Kbps

帧屏 7.5fps~30fps

分辨率 QCIF,CIF

T.120数据速率 6.4Kbps~128Kbps (HMPL)

每一个会议电视终端工作在最高能力

支持会议问候&指示(Greet&Guide)的全部自动协议转换

超级多分屏画面

支持5种不同的动态显示模式（2，4，5+1，9四种分屏方式或全屏）

动态更新：当前所显示的会场可在会议过程中随时更新

每个子画面都可以是固定会场或声音激励会场

可靠易维护的结构

坚固的电信级结构设计

任何模块可以热插拔（前面板）

模块前面板LED显示模块当前状态 模块自动配置

通用插槽结构—任何模块可以使用任何插槽

发生硬件故障时，重新自动地完成硬件资源分配

支持芯片级诊断

在线升级、更换

T.120数据功能

支持可达96个会议电视终端

HMLP速率可达128Kbps

功能强大的会议管理系统

基于Windows’95/NT图形界面，操作方便

可以通过Internet、Intranet（LAN）、拨号Modem或RS-232等不同方式连接MGC-100

同时支持16个本地或远端MGC管理员连接到MGC-100

一个管理软件平台可管理在多台MCU上召开的多个会议

可以通过具有TTCM的任何普通电话控制，并支持多个电话同时连接 可对会议点和会议进行剪切、拷贝、粘帖或拖动、下拉等操作，随心所欲

在一个窗口内显示所有硬件资源、会议以及会议点，直观全面

详细的CDR（会议详细记录）数据可方便地导入用户数据库和用户计费系统

用户管理和计费系统可以通过API存取MCU数据

4. MGC-100的配置

MGC-100是一台电信标准结构设计的新型的MCU，它集成ATM、IP以及ISDN等网络接口于一体，强大的功能以及灵活的配置可以满足不同用户需求，传输速率范围56kbps~2Mbps。

(1). MGC-100基本系统

16插槽主机，包括系统控制单元（含控制模块、软驱、硬盘、2个RS232口、1个LAN口）。

(2). 视频处理单元(Video)

MGC-100有两种视频处理模块：

Video/MUX-8：用于支持前8个会场，128~768Kbps速率支持8个点，E1速率支持4个点。

Video/MUX-16：每个该模块128~384Kbps速率支持16个会场，448~768Kbps速率支持8个点，E1速率支持4个点。

(3). 音频处理单元(Audio)

Audio模块-12：每个该模块可支持12个会场。

(4). 数据处理单元(T.120)

MGC-100有两种数据处理模块：

T.120模块-12：每个该模块可支持12个T.120会场。

T.120模块-30：每个该模块可支持30个T.120会场。

(5). 多重协议转换/分屏处理单元 (Transcoding/CP)

该模块处理不同速率（1920Kbps以下）、音频算法、帧频、分辨率、以及不同T.120数据速率会议电视终端之间的混合会议以及分屏，指标如下：

MGC-100有两种自动协议转换/分屏处理模块：

Transcoding/CP-6：每个该模块可支持6个自动协议转换和分屏的会场。

Transcoding/CP-12：每个该模块可支持12个自动协议转换和分屏的会场。

(6). 网络接口单元

N/I E1x2：双E1/PRI接口模块，每个模块支持60B ISDN通道（即30个128Kbps/10个384Kbps/5个768Kbps/2个E1 PRI），或2个专线连接会场。

NET-8 Leased：8xE1接口模块，每个模块8个专线连接会场。

ATM 25 Mbps：FVC ATM 25Mbps接口模块，每个模块支持60B ISDN通道（即30个128Kbps/10个384Kbps/5个768Kbps/2个1920Kbps）。

ATM 155 Mbps：FVC ATM 155Mbps接口模块，每个模块支持120B ISDN通道（即60个128Kbps/20个384Kbps/10个768Kbps/4个1920Kbps）。

5. 技术指标

(1) 系统容量

最大端口数量 ISDN ATM:25M ATM:155M IP
128Kbps 84 - - 132
384Kbps 60 60 80 132
512Kbps 45 32 48 132
768Kbps 36 32 48 132
1920Kbps 32 18 24 132
最大同时召开会议数量 21 20 20 33
最大支持分屏会议数量 12 12 12 15

(2) 级联：符合ITU-T（星形结构）

(3) ITU-T标准

视频会议/网关：H.320, H.323, H.321 (FVC), T.120

多点/主席控制：H.231, H.243

视频算法：H.261, H.263

音频算法：G.711, G.722, G.728

数据：H.243 LSD, T.122/T.125 (MCS), T.123, T.124 (GCC)

通信：H.221, H.242

通道复合：H.221, BONDING模式1, H0

(4). 外部通信

数据速率：56~2Mbps

时钟同步：提供内时钟或同步于网络时钟

(5). 网络接口

25Mbps ATM (FVC) ：56~1920kbps

155Mbps ATM (FVC) ：56~1920kbps

E1专用线路：6~1920kbps

E1/PRI (30B+D)：56~1920kbps

(6). 多点管理

工作站管理软件为Microsoft Windows’95/98应用程序。

提供LAN和RS232两种连接方式，直接或通过调制解调器连接，同时支持多个操作员。

(7). 会议控制

声音激励（支持自动浏览）

直接控制

主席控制（支持自动浏览）

超级多分屏显示（2/4/5+1/9分屏）

(8). 电气参数

功耗：500瓦(典型值)

工作电压：110-240VAC，50/60Hz；-48DC

(9). 物理参数

机械尺寸：高40.8cmX宽58.4cmX长50.2cm (10)

环境：工作温度范围 10~40°C

工作湿度范围：15~90% (无凝结)


Cisco

Cisco公司的IP/TV
思科IP/TV方案是端到端完整的网络视频解决方案。它整合了高性能的视频服务器-Cisco IP/TV 3400系列服务器，IP/TV 3400系列服务器预先配置了强壮的IP/TV 3400服务器软件，而客户端桌面PC配置了IP/TV客户端软件。Cisco IP/TV解决方案支持三种用途，实况转播、视频预订及视频点播(VOD)。Cisco IP/TV解决方案提供丰富的软件功能，可以提供高质量的视频流和具有良好的可管理性、扩展性、带宽有效利用等特性。

Cisco IP/TV解决方案包含了Cisco AVVID（Architecture for Voice, Video and Integrated Data），即一个包含了音频、视频整合数据的通信框架。能满足企业通信、职工培训、远程教育、商业电视等需求。采用RTP(实时传输协议)，RTCP(实时传输控制协议)，RSVP(资源预留协议)，MULTICAST(组播协议)，以软件为核心，在现有的计算机网络上，实现了视频节目的广播、点播等功能。Cisco IP/TV方案利用了经济实惠的Windows 95, Windows 98, and Windows NT平台，并充分利用了微软的Windows Media技术（WMT）。同时它与苹果公司的QuickTime客户端，UNIX VIC and VAT Mbone tools,即Netscape插件结构兼容。

Cisco IP/TV方案可以在任何IP网络上工作，如10BaseT 、100BaseT Ethernet 或千兆位以太网上工作，也可以在电缆、ADSL调制解调器及局域网仿真的ATM网络上工作。对于视频播放，Cisco IP/TV StreamWatch软件可以收集观众的信息，如观众人数、身份、及观看节目时间，对点播节目，日记文件能记录观众正在收看的节目。这些工具能提供数据帮助你分析消费类型。
更多产品：

Cisco IP/VC Videoconferencing Series
The Cisco IP/VC Videoconferencing Product Family provides an IP-based network videoconferencing solution, helping organizations make the transition to an Internet-driven world with instant, worldwide connectivity. Product Literature

Cisco Media Convergence Server
The Cisco Media Convergence Server is a high-availability server platform for Cisco AVVID (Architecture for Voice, Video and Integrated Data).

Cisco VN 5902 Video Networking System
The Cisco VN 5902 Video Networking System is a compact, high-performance video head-end solution that receives audio and video streams from any satellite, terrestrial, or wireless source, performs a wide range of video processing and adapts the streams to any standards-based digital broadband network.

Cisco VN 5900 Video Networking System
The Cisco VN 5900 Video Networking System is a video head-end solution that receives audio and video streams from any source, performs a wide range of video processing, and adapts the streams to any standards-based digital broadband network.

Cisco VN 2900 Video Networking System
The Cisco VN 2900 Video Networking System is a high-density video encoder and decoder that receives audio and video streams, performs video processing, and adapts the streams to any standards-based digital broadband network.

http://www.cisco.com


EZENIA
http://www.ezenia.com/, http://www.ezenia.com.cn
Ezenia的产品可为世界各地的内联网和外联网带来互动的多媒体通讯。

    使用我公司的服务器，可使在总部及代表处的工作人员及其它地方的人及合作伙伴之间无缝地联系，使他们可以体验各种媒体的互动。并利用图象实况、话音和一系列合作工具。

    网络互动服务器可以为网络增加实时话音的互动，吸引访问者并使其在此浏连忘返，这种互动能够提高您的品牌认知度并帮助您增强与客户的关系。

也许您想更加卓有成效地管理您的全球小组，也许您想使您的远程站点轻而易举的与您公司的总部进行通讯。

2000系列和 Velocity 将是您踏上多媒体通信的捷径 - 有什么样的要求，就会有什么样的网络。

    2000 系列和 Velocity 产品是全世界最畅销的多媒体通信服务器。不管您的企业的规模怎样及其灵活性要求如何，Ezenia!公司的产品都是支持高质量、高效率和低成本的多媒体会议的理想选择。

2000 系列和 Velocity的特性
2000 系列和Velocity 系列都基于同一个技术核心 ，然而在可 扩展性方面有着不同的特性：

    2000 系列多媒体通信服务器能够支持8到48个端口，并且相互之间都可以级联，从而可以产生一个庞大的会议环境。由于它具有可扩展性及可按用户要求量身定做的特性，因此它既可以满足大公司的要求，也能够满足会议服务的供应商的需要。Velocity4或8端口多媒体通信服务器用于较小型的多点会议-比较适用于那些需要在一段时间内使用会议服务，但并不想拥有自己的会议系统的客户。2000系列和 Velocity都支持各种高级特性，其中一些特性将在下面详细介绍。关于产品详细的性能指标，请参看我们的技术资料。

    四分屏功能具有在一个屏幕上同时看到多个站点的能力。 Ezenia! 公司先进的四分屏功能包括：支持的最高的宽带速率为2Mbps；使会议通话充分利用2000系列出众的音频和视频性能，帧速率最高达每秒30帧-与广播电视的水平基本相当。混速 功能:它是该行业第一个支持同一个会议的不同种类连接的平台，它可以使用户充分利用日益变化的带宽和经常配置的网络环境。2000系列可以不降低性能的情况下成功地发送高速信号和进行视频图象选择。

    支持不同的网络连接: 它是市场上出现的第一个支持 高速ATM, ISDN 和 Frame Relay （帧中继）的多媒体通信服务器。

    高级的调度和会议管理:通过功能强大而灵活的会议管理接口，管理员可以计划、监视会议并检查和排除会议中的故障。 　　级联:能够将多个多媒体通信服务器链接起来，从而支持多达数百个用户。帐户信息对于准确的报告是必须的，这样将有助于您报告网络的使用情况和网络的计划安排 。

    2000系列和Velocity系列的重要特性：

    符合H.320 标准的交换和专用数字网络；支持该行业最大范围的音频、视频和数据会议标准；可升级至最多48端口

    支持大型混合网络的能力: BRI ISDN, T1, E1, BRI, HSD, ATM, 帧中继,卫星；

    开放式的系统体系结构，可以和任何符合 H.320 标准的端点协同工作；

    能够与任何的 H.320 端点设备及电路交换和专用数字网络的混合网络协同工作；

    2000 系列是国际广泛使用和认证的多媒体会议服务器。该认证包括了大部分主要的国际市场，它们是：奥地利、日本、澳大利亚、卢森堡、比利时、荷兰、加拿大、新西兰、中国、挪威、丹麦、葡萄牙、芬兰、新加坡、法国、西班牙、德国、瑞典、希腊、瑞士、香港、英国、爱尔兰、美国和意大利等。

网络互动服务器

    网络互动服务器 --该服务器主要为主机服务单位的现有的基础设施配套设计，它提供的解决方案包括服务器平台、控制软件和开发包均可以很方便地进行升级。利用它可以进行以网络为基础的话音和视频通信。站点和门户可以主持实时的互动式的话音聊天和互动会议，如"在线访谈"。在带宽足够 的 情况下，如具有电缆调制解调器的社区， 主持的站点还可以提供视频功能。使得人们可以实时地见面和会话。

    互动服务器的问世改变了以往由网站发布内容，浏览者只是被动的接收的局面，它强调的是双方的交流。任何一个想在网上购买商品的客户都可以找到销售员询问或砍价。这种交互性对目前蒸蒸日上的各种网站来说是一个革命性的突破。为站点 所有者提供了新的增值点，互动服务器的编程界面非常灵活，使得站点所有者可以自己设定解决方案来满足他们的需要。对社区站点来说，它可以使观点一致的人们能够套论共同感兴趣的事，结成新的友谊，成立话音讨论组，加强站点的凝聚力；对于商业站点来说，它可以在供应商和消费者之间建立紧密的关系，为他们提供新产品的信息使得他们能和公司代表直接沟通以获得支持；对于远程教育来说，它可以使远程教育变得更加生动和更有效率。课堂上的人们可以组成在线讨论组进行互动式交谈并获得反馈；而对于电子商务站点来说，它可以使站点访问者在实时的会议 （如电子商务线交易）中向代表提问题和意见。软件开发商还可以把它与 游戏集成，使游戏爱好者们更能体验一起玩游戏的刺激与快乐！

多媒体通信能使物理空间上分离的个人无论相隔多远,有多大的地理屏障或网络配置如何,都能实现无缝透明的互动.全球范围内的公司都正在使用互动应用提供培训、召开项目评估会议及参加管理通报会等。无论商业应用如何，多媒体通信都能使这些组织共同有效地开展工作、迅速地传递信息以及更快地作出决策。

    Ezenia!所开发的Encounter!系列产品带有一个基于 IP的多媒体通信服务器(MCS)，能在整个企业间形成协作。我们的服务器能使完全相异的网络及现有的系统实现完美接合以实时提供高商业质量的视频、话音、数据通信。鉴于任何两个网络都不会完全相同，Ezenia!（前身为Videoserver）提供了广泛的可扩展的解决方案以配合不同的网络类型、设置水平及应用。对于希望通过综合的基于IP的视频、话音、数据提供多媒体组通信的组织而言Encounter系列确为最理想的解决方案。

    无论什么样的商业应用，ECOUNTER3000家族系列都能使人们加入实时的多媒体会议并且能够使全世界的伙伴通过"面对面"的会议进行联系。 Encounter 3000 NetServer 是一个能够满足一个公司或服务提供商所有需求的多媒体通信服务器, Encounter NetGate把视频、话音及数据合作带入了公司内部及公司之间的通信中。NCOUNTER3000中央控制系统(ECMS) 为ENCOUNTER3000网络服务器提供基于网络的会议预订功能。

Encounter家族的用户：

    财富1000家公司-帮助公司内部网提供员工培训，项目 管理回顾会议并提供执行简报。

    政府机关-为分散的部门提供 无缝连接以保证相关人员的迅速决策。

    教育机构-使用高速内部及外部校园网来远程教学。

    网络服务提供商-通 过 VPN提供会议服务

Encounter家族的特点：

    互操作性。基于ITU-TH.323标准，通过领先的终端制造商及IP设备提供商，Encounter系列成功的演绎了真正的互操作性。而且，通过我 们提供的H320/H323网关，Ezenia顺利实现了对H320终端与H323终端的互操作挑战。

    灵活性-Encounter系列允许各种不同多媒体性能的参与者加入到同一个会议中。你可以选择用蜂窝电话，普通电话，桌面视频会议系统加入会议，允许与会者实时共享如　　word文档，powerpoint幻灯片或图表之类的应用。

    可按比例放大的结构-Encounte系列加入了一个新的可按比例放大空间的功能。由于虚拟会议在一个机构中使用得越来越多，你可以在你的现有系统中加入更大空间，使更多的员工能同时加入虚拟会议。

    基于浏览器的配置及管理-- Encounte系列的基于浏览器的用户界面管理系统只需在浏览器上轻轻一点，便可帮助你配置你的系统，预订会议并监测所有会议及终端信息。

    简便的拨号程序-过Encounter网闸地址翻译，你不用进入复杂的地址字符串去连接不同络上的不同类型的终端。

    商务图像质量-- Encounte系列是第一个能提供商用质量的音频 、视频和数据混合，提供高速连接，优化 压缩并集成T.120数据会议的IP会议解决方案。

Encounter3000网络服务器

Encounter NetServer是一个能够满足一个公司或服务器提供商所有需求的多媒体通信服务器。它基于ITU H.323及T.120标准，能提供无缝、透明、整个企业间的广泛通信。其特点是：

易调整的图像浏览选项包括语音激活图像切换，用户选择图像切换及四分屏，四分屏使得屏幕上能同时出现四个图像窗口。如果有三个以上的Encounter? 3000级联则不具备四分屏功能。
音频代码转换使得每一个端点都能在使用最小带宽的同时获得最佳的语音质量。
对于Encounter? 3000系列内置的音频网关可支持24电话用户同时加入一个会议。
音频互动响应(IVR)允许电话用户通过拨号盘提供会议及密码，从而简便地加入会议。
通过密码进入会议的方式保障了与会者的隐私。
会议级联功能允许在两个Encounter 3000 NetServer之间联接而不必在乎他们的位置。这不但使Encounter 3000可以按照最方便的方式在网络中分配会议资源，而且支持一个Encounter 3000支持不了的大型会议。
应用立即开会(Conference Now)功能，用户可以在终端上开启并加入多媒体多点会议，简单得就象他们自己的会议。
Encounter 3000 NetServer可详细记录以往的使用信息，使记录及报告更为容易。

Encounter NetServer技术规格

系统容量：
最多可同时容纳80个会议；最高支持64个H.323音频-视频终端；23个美国POTS电话（欧洲为24个）

软件：
Encounter 3000 NetServer 1.0版；Microsoft Windows NT 4.0版及Service Pack 5；Microsoft Internet Infomation Web Server 4.0

传输速率：高至2M bps

会议视频切换模式：
语音激活；用户通过网络UI选择；四分屏模式

管理界面：
通过Microsoft浏览器；IE4.01或更高版本浏览器或Netscape4.6或更高版本

诊断：
系统配置水平；带宽级别-MPU2及ISDN接口卡；会议级别
终端类型：
H.323音频/视频/数据终端；通过IP的T.120数据终端；H.323网络电话；普通电话

系统模块：
以太网接口-10/100 BaseT以太网卡；ISDN接口(普通电话)双E1/PRI或双T1/BRI；媒体流处理单元(MPU2)

转码：
音频G.711,G.723.1,G.722

监测及状态：
支持MIB以太网的SNMP协议

管理功能：
管理者登录；系统、会议及用户事件记录；系统资源状态及可用性

系统配置：
会议优先权及管理；FTP/远程登录
Encounter Netgate网关

把视频、话音及数据合作带入了公司内部及公司之间的通信中。在保证IP会议环境与ISDN端点实现有效结合的前提下，Encounter Netgate网关能一边保护各组织的现有技术投资，一边推进可靠有效的通信。Encounter Netgate还可作为基于IP的多媒体通信服务器及基于ISDN的多媒体通信服务器(Ezenia! 2000 MCS)之间的中介。通过ISDN和V.35接口，Encounter Netgate可直接与基于ISDN的多媒体通信服务器(Ezenia! 2000 MCS)相连。这一紧密的配置能使IP用户无须经过额外的交换线路呼叫就能参与ISDN对话。这无需交换的配置使公司在充分利用现有的BRI连接的同时避免另付ISDN线路费用。其特点是：

使基于标准的ISDN(H.320)及基于IP的端点(H.323)之间实现无缝通信。
提供一系列的转换电路及专用的网络设备接口，使用户可选择最适合他们应用的接口。Encounter 3000网关可配置3种不同网络接口，包括4XBRI口，双T1/PRI口，双E1/PRI，及多至2个双V.35/RS-449，所有ISDN接口均包括内置的IMUX。
支持2B系到768K和384K H0，提供高品质的会议效果。
音直接向内拨号(DID)，音频互动响应(IVR)使WAN到LAN拨号更加容易。
动态选择端点可支持的最佳的视频标准(H.261和H.263)。
实时话音代码转化能令按呼叫顺序方式进行的连接得到优化。
在Encounter Netgate及(Ezenia! 2000 MCS)系列间建立直接联系而无须交纳昂贵的线路收费。
支持所有速度的LAN到WAN，WAN到LAN呼叫及由管理者发启的网关呼叫，提供灵活的呼叫方式。
TANDEM支持功能(网关到网关)提供高性价比的WAN到LAN连接。
具有管理用户接口的浏览器允许系统管理者配置、管理及监测网关，包括是否支持T.120，WAN到LAN，LAN到WAN的呼叫状态。

Encounter NetGate技术规格

系统容量：
同时有16个会场(其中有8个音频转码)时传输速率最高可到384Kbps； 同时有12个会场(其中有8个音频转码)时传输速率可到512Kbps； 同时有6个会场时传输速率可到768Kbps

软件：
Encounter 3000 NetGate 1.0版；Microsoft Windows NT 4.0版及Service Pack 5；Microsoft Internet Infomation Web Server 4.0

传输速率：
支持2B到768K和384 H0

转码：
音频G.711,G.723.1,G.728

监测及状态：
支持MIB以太网的SNMP协议

管理界面：
通过Microsoft浏览器；IE4.01或更高版本浏览器或Netscape4.6或更高版本

诊断：
系统配置水平；带宽级别-MPU2及ISDN接口卡；会议级别
系统模板：
媒体流处理单元2(MPU2)；以太网接口-10/100基带以太网；WAN界面可选择性(可至以下所列中的3个)：
双T1/PRI，带IMUX
双E1/PRI，带IMUX
QBRI，带IMUX
双V.35/V.36/RS-449 DDM(每个系统仅限两个模块)

采用标准：
H.320：
音频-G.711,G.728,G.722；
视频-H.261,H.263；
数据-T.120；
呼叫及控制-Q.931,H.320,H.242
H.323：
音频-G.711,G.728,G.723.1,G.722；
视频-H.261,H.263；
数据-T.120；
呼叫及控制-H.225,H.245,H.246

管理界面：
管理者登录；系统、会议及用户事件记录；系统资源状态及可用性

系统配置：
网闸注册重新注册；呼叫开始/呼叫结束
Encounter GateKeeper

用户可管理在IP网上出现的音频及视频信号堵塞。网络管理员可制定各种政策来管理带宽使用情况、路径以及监测已注册会议用户的活动，网关及多媒体会议服务器。Encounter Gatekeeper是一个软件，运行在WINDOWS NT超作系统上。可以将它安装在Encounter网络服务器、网关或任一个单独的服务器上。其特点是：

与其它Gatekeeper进行区间对话、地址转换等通信，使用户能够连接不同网络上的不同端点
在遵守登记规则、带宽使用政策及资源可用性的基础上控制与LAN的接入
全套综合管理工具使管理人员能够密切监视区域活动及记费
网关路由呼叫服务能在符合传输速率及带宽要求等呼叫特征和资源可用性的基础上，将呼叫引导至一个具体的网关
区域控制使管理员能够在不同设置的区域上进行注册
Microsoft ILS(因特网定位业务)服务器使用户能找到终端及Encounter NetGate和Encounter NetServer之间的对话
基于浏览器的接口使得从LAN因特网或公司的内联网的任何一个位置上对网络的管理都变得简单方便
支持H.323版本1和版本2，确保所有H.323终端均可兼容
立刻开会(Congference Now)功能用于终端与Encounter网络服务器的连接，使任何323终端召开多点会议就象一个点对点呼叫那么容易设置
复杂呼叫功能允许Encounter网关在IP网络会议中充当视频PBX的功能。通过Encounter会议服务器和网关，呼叫转接功能可使用户不在时将视频呼叫转接到可代替的用户或电话号码上
永久注册功能允许将呼叫转接到非RAS终端，例如H.320基于ISDN的终端

Encounter GateKeeper技术规格

支持的标准：
H.323修订版1及修订版2；网闸路径

会议容量：
同时支持1000个H.323设备；同时支持500个网闸会议
服务器系统要求
软件：
Microsoft Windows NT 4.0版及Service Pack 5；Microsoft Internet Infomation Web Server 4.0
最小硬盘：
PIII 450MHz，内存128MB；10/100以太网NIC接口
Encounter eMCS

为Encounter网络服务器提供基于网络的会议预订功能。eCMS能够使终端用户及会议管理者无论身在何处都能通过Encounter网络服务器预订并管理会议。通过一个单用户的会议数据，eCMS能够看到整个的网络资源。eCMS运行在WINDOWS NT超作系统上。它可以安装在Encounter网络服务器或安装在一个单独的服务器上来管理一个以上的服务器。其特点是：

基于浏览器的用户界面为终端用户或管理者们提供简便的会议预订和管理手段
可利用立即开会、设定时间或重播来安排会议，提供给用户灵活的预订方式
可设定特殊会议，如仅允许特殊人员参加的会议或先来者参加的会议。用户可选择在一个特殊的Encounter网络服务器或允许eCMS选择一个最合适的服务器来预订会议
通过电子邮件自动通知与会者保证了所有与会者可得到会议通知
直观的会议管理界面包括类似如下特点：加入或退出会议，拨入或拨出及延时或停止一个会议
通过登录/密码登录到基于网络浏览器的用户界面，三个授权级别允许管理者给每个用户帐号分配资源及图像优先权
以前的及现有的事件日志为管理者提供一个会议资源使用情况的参考
支持Microsoft Access(默认)或Microsoft SQL(供客户选择)数据库，使管理者们能为大型会议安装更强大的数据库

Encounter eMCS技术规格

支持的数据库：
Microsoft Access(默认)；Microsoft SQL(客户可选)

eCMS预订及管理：
授权许可；单用户eCMS(对一个进行Encounter NetServer安排及管理)；其它Encounter NetServer管理的用户数是：4,8,12,16
服务器系统要求
软件：
Microsoft Windows NT 4.0版及Service Pack 5；Microsoft Internet Infomation Web Server 4.0
最小硬盘：
PIII 450MHz，内存128MB；10/100以太网NIC接口

客户端要求：
通过Microsoft IE4.0或更高版本浏览器或用Navigator 4.6或更高版本


IBM

IBM公司
Hotmedia-Rich Media for the e-Generation

HotMedia is the most comprehensive Java-based solution for incorporating dazzling and powerful rich media effects into any Web application. Currently available as a free download from IBM, HotMedia is the perfect tool for Web integrators who want to enhance e-business applications with interactive rich media without the requirement of plugins or specialized servers.
VideoCharger
IBM VideoCharger是IBM 内容管理软件包（IBM Content Manager）的重要一员，它与IBM DB Digital Library 和管理多媒体内容的IBM DB2 Universal Database for managing multimedia content 通用数据库紧密集成，能通过企业内部网或互联网向多个用户桌面传送高质量的实时音频和视频数据流视频信号，而用户可以通过传统的浏览器如IE或Netscape观看视频。IBM内容管理器产品的设计是用来帮助人们全方位管理今天e化商务的数字信息，从垂直的商务应用，到客户服务、ERP和供应链管理。作为Content Manager的组件之一，VideoCharger支持基于最新标准的技术，可把多媒体内容组织到一体化的平台上，并支持点播，广播和实时压缩播放。

Content Manager VideoCharger Server

Whether you’re seeking a cost-effective tool for sales force training and corporate communications, or an educational aid for distance learning programs, there’s no match for digital video in getting your message across and making a lasting impression. Content Manager VideoCharger transforms digital video into an effective desktop training and commnications tool, helping you deliver high-impact information where it’s needed.

Supporting the latest standards-based technologies, Content Manager VideoCharger broadcasts high-quality, real-time audio and video streams to multiple viewers over corporate intranets or the Internet. It consolidates multimedia content onto a single server or cluster of servers that users can access at any time to view video-on-demand. And, unlike analog videotape, digital video retains its quality over time -- the picture is as good after you play it a hundred times as it was the first time.

Whatever the size of your business, Content Manager VideoCharger has the optimal solution for your communication requirements for audio and video. With Content Manager VideoCharger on AIX, you get the high performance, scalability, and reliability of the RS/6000 family of servers -- all the way from uniprocessors to massively parallel processing systems. It lets you expand to video server complexes by clustering RS/6000 processors as demand for video streams increases.

Content Manager VideoCharger on Windows NT is an easy-to-install and easy-to-configure solution, with integrated MPEG encoding technology-- an efficient method of broadcasting a live event while simultaneously recording it to be played back later.

Imagine the power of adding audio and video to your Content Management solutions. With DB2 Universal Database’s support for multimedia objects you can enable a whole new set of business applications enhanced with the capability of streaming audio and video.

Integration with IBM Content Manager provides a complete solution for managing multimedia content. With IBM Content Manager, you can store petabytes of text, images, audio, and video into digital form, and distribute it worldwide, securely over any network. More information on IBM Content Manager solutions and business partners, visit the IBM Content Manager Web site.

Content Manager VideoCharger V7.1 Player

Runs on Windows 95, Windows 98, and Windows NT or Windows 2000 clients using a browser such as the Microsoft Internet Explorer or Netscape Navigator.
Selects, receives, presents, and controls the playback of video/audio datastreams received from the IBM VideoCharger Server.
Scales from default to full screen size.

--Version 7.1 player enhancements include:

full enablement of video/audio delivery from low bit rate to business-quality MPEG1 and MPEG2 (up to 15 Mbps) streams
TCP and HTTP stream support
port configuration for passing through Internet firewalls.
Player support for the Arabic language
The player when used as a stand-alone "helper" application, supports a draggable screen, video segment selection for repeated play, and changing video selections without reloading the player.

The player can also be used as a browser "plug-in" viewer that lets the HTML author integrate streaming video and audio with text, graphics, and images in the HTML page. The "plug-in" executes under the control of the browser and does not require an extra window for displaying the video.

Mouse buttons provide player control. The player uses the Microsoft ActiveMovie multimedia subsystem, which is software provided, free of charge, by Microsoft Corporation and is licensed according to Microsoft terms and conditions.

Related products:

Content Manager portfolio for enterprise content management

Content Manager for documents, workflow, and multimedia

Content Manager OnDemand for computer output and ERM

Content Manager CommonStore for archiving

Enterprise Information Portal for information integration


iVISTA

Inetcam
http://www.inetcam.com/
Our iVISTA Software Packages are designed to stream your live video and audio content onto the Internet with virtually any webcam/camera and a PC.

iVISTA Professional Edition:
iVISTA Pro Webcasting

Run your own PROFESSIONAL WEBCASTING STUDIO with iVISTA Pro Webcasting. You can webcast from as many video sources as your PC can handle - and even add an Audio channel. Your webcast is available both on your personal VideoWebPage or with our innovative Video E-mail. In addition, you can record both audio and video clips, and use the Screen Capture tool (so you can broadcast your computer desktop just like a camera - perfect for tech support or software training) and our motion-detection module for setting up a home video security system.

Modules Included

Audio
Multiple Video
Video E-mail
VideoWebPage Address
Screen Capture Video
Scheduler
Wireless Video & Audio
Clip Recording & FTP
30-day FREE Support

WebPrice

$199.99

iVISTA Pro Security

iVISTA Pro Security is our most COMPREHENSIVE MULTIMEDIA WEBCASTING PRODUCT, and can take advantage of the power of our affordable iMIRROR co-hosting service. Exclusive to iVISTA Pro Security, the iMIRROR subscription service allows you to serve hundreds of simultaneous viewers from one or two PCs in real time!

With iVISTA Pro Security, you can webcast as many video sources as your PC will recognize, add motion detection to any of those video sources (great for setting up a video security system), webcast audio, and record your audio and/or video webcasts for later playback. The Screen Capture module allows you to broadcast your computer desktop just like a camera - perfect for tech support or software training.

Modules Included

Audio
Multiple Video
Video E-mail
VideoWebPage Address
Screen Capture Video
Scheduler
Wireless Video & Audio
Clip Recording & FTP
Multiple Motion Detection & Notification
1 year FREE iVISTA Consulting & Technical Support

WebPrice

$399.99

iVISTA Personal Edition:

iVISTA Video, Audio & Video E-mail

Stream LIVE VIDEO and AUDIO with the world's most advanced Webcam Operating Software.

With iVISTA, you can share your Video and Audio streams and recorded clips either on your personal VideoWebPage or with our innovative Video E-mail. And with the Screen Capture capability, you can broadcast your computer desktop just like a camera - perfect for tech support or software training.

Modules Included

Single Video
Single Audio
Video E-mail
VideoWebPage Address
Screen Capture Video
Scheduler
Wireless Video & Audio
Clip Recording & FTP
30-day FREE Support

WebPrice

$49.99

iVISTA Home Security

Turn your PC into an AFFORDABLE and EFFECTIVE VIDEO SECURITY SYSTEM with iVISTA Home Security. You can use your webcam with the iVISTA motion detection module to watch your home while you're away. IVISTA Home Security allows you to customize the severity of motion to detect, as well as giving you a full menu of responses, from an e-mail notification to recording video and posting it to your Web site. And with the Screen Capture capability, you can broadcast your computer desktop just like a camera - perfect for tech support or software training.

Modules Included

Single Audio
Single Video
Single Motion Detection & Notification
Video E-mail
VideoWebPage Address
Screen Capture Video
Scheduler
Wireless Ability
Clip Recording & FTP
30-day FREE Support

WebPrice

$99.99

VideoWebPage Software BASIC

Stream LIVE VIDEO With the World's Only Advanced Webcam Operating Software.

With this iVISTA VideoWebPage package, your friends, family and associates can easily view your live video stream by simply typing in your personal VideoWebPage address (myname.inetcam.com). No other live broadcasting software is as simple, flexible or fast. Use iVISTA to go Live匜rom Anywhere?. Includes a 1 year subscription to VideoWebPage Address.

Modules Included

VideoWebPage Address
Scheduler
Wireless Ability
Recording & FTP
Single Video
30-day FREE Support

VideoWebPage Software PLUS

Stream LIVE VIDEO & AUDIO With the World's Only Advanced Webcam Operating Software.

With the iVISTA VideoWebPage PLUS your friends, family and associates can easily SEE & HEAR your live audio and video streams over the Web by simply typing in your personal VideoWebPage address (myname.inetcam.com). No other live broadcasting software is as simple, flexible or fast. Use iVISTA to go Live匜rom Anywhere?. Includes a 1 year subscription to VideoWebPage Address.

Modules Included

VideoWebPage Address
Scheduler
Wireless Ability
Recording & FTP
Audio
Single Video
30-day FREE Support

VideoWebPage Software HOME SECURITY

MONITOR YOUR HOME or BUSINESS LIVE With the World's Only Advanced Webcam Operating Software.

The motion detection feature of the iVISTA VideoWebPage HOME SECURITY package will automatically record motion sequences from the live video stream for immediate online viewing and e-mail notification. No other security monitoring software combines such powerful functionality with such an affordable price. With iVISTA Home Security software, now you can monitor, Live匜rom Anywhere?. Includes a 1 year subscription to VideoWebPage Address.

Modules Included

VideoWebPage Address
Scheduler
Wireless Ability
Recording & FTP
Audio
Single Video
Single Motion Detection & Notification
30-day FREE Support


iPresentation

北京传述信息科技有限公司
http://www.presenter.com.cn， http://www.presenter.com
- 传述公司提供企业级网络多媒体信息和知识共享解决方案。
iPresentation制作系统
  • iPresentation Authoring Server - Presenter's core server technology which governs the presentation creation services. Through capabilities such as integrated workflow, process automation, robust security, PowerPoint converter, and telephony services, the iPresentation Authoring Server makes it easy to create, organize, and monitor all the functions and tasks involved in creating presentation content.
  • Authoring Interface - A web-based interface that provides presentation-authoring functionality from a browser. This interface is intuitive and extremely easy to use. Business users create and publish presentation via log-in and log-out mechanisms that ensure content confidentiality. Administrators have the ability to deploy the Authoring Interface to an entire enterprise with the click of a button.
  • iPresentation Video Studio - A desktop client that provides a familiar Windows desktop environment for creating video-based presentation and uploading the content to a content repository.
iPresentation管理系统
  • iPresentation Management Server - Presenter's core server technology governs the content repository and enables a rich set of presentation content management services for controlling both content and processes throughout and between distributed enterprises. Through capabilities such as integrated workflow, process automation, and robust security, the iPresentation Management Server makes it easy to define, organize, and monitor all the functions and tasks involved in creating and delivering Web presentation.
  • Site Administration - This web-based interface provides powerful site management functionality from a browser to manage and administer all presentation content, rich media Web sites, users, and groups, regardless of their location across the virtual enterprise. By automating site administrative tasks, the site administrator protects the integrity of business-critical processes while lowering the cost of owning and maintaining complicated applications.
  • Site Customization - The site administrator can upload a logo, banner, site page header, site page footer, and home page to customize a Web site for enterprise group usage. Presentations can be created and published by multiple authorized users on the fly. However, each presentation will automatically be framed with a site-specific look and feel.
  • iPresentation Customization - The iPresentation Authoring Server allows users to create and publish Web presentations on the fly, ensuring dynamic, personalized presentation publishing anywhere, anytime. iPresentation customization services improve the relevance of your presentation by automatically framing your presentation with your personalized logo, banner, and images. Images can be updated independently from the content, thereby allowing you to instantly re-purpose a specific presentation for greater impression in targeted delivery.
iPresentation发布方案(1)
  • iPresentation Player - A robust streaming solution for viewing Web presentations stored in the content repository. This player does not need to be installed on the user's system -the player and the content are delivered on the fly.

    The iPresentation player leverages industry-leading streaming media technology and takes full advantage of the iPresentation Suite object architecture to manage each video, audio, and slide sets as separate objects, thereby enabling users to view rich media presentations over the Web.

  • iPresentation Mobile Player - A robust wireless solution for viewing Web presentations stored in the content repository. A mobile device must have the iPresentation Mobile player installed. Presentation contents can be downloaded to the mobile device for remote viewing.

    The iPresentation Mobile player leverages industry-leading wireless technology and takes full advantage of the iPresentation Suite object architecture to manage each video, audio, and slide as separate objects, thereby enabling users to view rich media presentations over mobile devices.

  • iPresentation Telephony Playback Option - The Telephony Playback Option enables companies to provide employees and partners with an easy way to listen to voice-narrated PowerPoint presentations, at their own convenience, without having to make additional IT investments for the most up-to-date audio technology.

    Presenter has developed the Telephony Playback Option as an alternative to listening to voice narration by way of streaming media. Instead of listening to audio through their PC, users can employ their telephone to listen to the voice narration synchronized to the on-demand PowerPoint presentation on their PC. This is an easy, effective way to listen to the narrator of the presentation when a company's IT infrastructure does not support streaming media, when there are firewall or bandwidth issues, or when employees wish to listen to a presentation without disturbing their colleagues with sound from their PC speakers.
iPresentation文献
iPresentation Authoring Server 介绍
iPresentation Management Server 介绍
iPresentation Video Studio 介绍
iPresentation Playback Options 介绍


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OpenVideo

OpenVideo 版本 4.0
http://www.commerceware.com.cn

产品发布日期
2001年9月

产品基本介绍

东软软件的OpenVideo系统是一个利用高速以太网络和宽带城域网提供高质量视频点播服务的系统，从软件和硬件两个方面为用户提供了完善的构造视频点播解系统的解决方案。

从可用性来看，OpenVideo软件的用户使用界面和管理界面均采用Web方式，所有操作均符合用户上网习惯，只要用户会上网就会使用；OpenVideo软件具有完善的点播、组播、直播和业务管理等功能；由于OpenVideo软件预装于专用硬件服务器上，用户使用时只需要将服务器接入网络并将服务器的IP地址修改成需要的地址即可使用OpenVideo系统。

从性能上看，OpenVideo软件使用定制的Linux操作系统、多线程、多级缓冲、磁盘文理化等技术大大的提升了系统性能，充分的发挥了硬件的潜力；与OpenVideo 4.0软件捆绑的MediaBox硬件服务器是我们经过对国内外多家知名厂商的服务器测试和评测而最终筛选出的，这几款服务器具有稳定性高，性能优越，扩展性好等特点，使整个视频点播系统具有极高的性能价格比。

产品新增功能

OpenVideo 4.0 新增以下主要功能：

1、多频道管理功能

2、Mpeg 4编码功能

3、直播管理功能

4．频道预览功能

改进的功能：

1、重新设计的简单易用的用户使用界面。

2、检索功能

运行环境

Windows 2000 server;RedHat Linux 6.2


Optibase

Optibase公司
http://www.optibase.com
成立于1990年的Optibase公司是一家在宽带视频流领域处于领先地位并在美国NASDQ上市（NASDQ:OBAS）的以色列高科技公司。公司在为以强有力的服务器平台基础的为开发视频在IP网络和ATM网络上应用创造了条件。这些应用包括远程教育、商务电视、监控、网络电视、视频点播等。Optibase公司还和Cisco System, Gilat Satellite Network, Harmonic等全球声誉卓著的公司结成战略联盟，为世界网络市场提供视频解决方案。

Optibase公司总部设在以色列的硅谷Herzliya，并在北美多地拥有分公司。它的办事机构遍布英国、日本、法国和中国，全球雇员130多人。

Optibase公司的产品技术在全球40多个国家拥有众多用户。它的产品通过直销、分销商、授权代理商、系统集成商和OEM进行销售。Optibase通过网络、电话、传真向全球用户提供技术支持。同时Optibase还通过向分销商、授权代理商提供技术研讨会和技术培训来加深他们对公司产品和技术的了解。

Optibase是一家在宽带网络上的视频流领域具有极强竞争力的公司，是国际标准化组织（ISO）MPEG的主要成员之一。凭借在该领域中的世界一流的专家队伍，本公司已发展了一系列与视频和音频压缩和低位率的MPEG压缩专有技术，能够为企业界提供完整的视频流网络解决方案。

Optibase的产品包括由MPEG MovieMaker视频压缩设备和MPEG ComMotion传输系统所组成的视频流传输服务器、以及实时、可远程管理的视频流软硬件，适用于在包括IP和ATM等先进数字网络上传输高质量的视频/音频流。此外Optibase还提供端点解决方案，比如VideoPlex解压卡和 MPEG ComMotion接收软件等。

Optibase 公司通过其在全球卓有声誉的OEM、系统集成商和战略伙伴将她的数字视频解决方案带给最终用户。Optibase 公司可以根据用户的需要提供不同的产品以满足各个用户对大型项目的需求。在这些伙伴和用户中有不少是该领域的领导者，例如Cisco System, Fore System(Marconi Communication), SeaChange International, Gilat Satellite Network, Hughe，Olivetti Telecom, Deutsche Telecom, Telecom Italia, Ncube, Concurrent Computer, Gilat Communication, GTE, Oracle Corp., SGI, AstraNet, Harmonic Inc., IBM, FVC.com, Matra,Teracom, PictureTel，Moconia 等等。

2000年5月30日Optibase公司中国上海办事处成立，上海长江新成计算机系统集成有限公司与Optibase公司签约，成为其在中国区的产品销售总代理，负责Optibase公司全线产品在中国大陆的分销、渠道建立和市场拓展。

1、MPEG-1 压缩平台 （MPEG MovieMaker? 系列）

  • MPEG MovieMaker Plus
  • MPEG MovieMaker XPress

2、MPEG-1&2 压缩平台

  • MPEG MovieMaker 200 Basic
  • MovieMaker 200 Networker
  • MPEG MovieMaker 200 Publisher MGW2000

3、制作软件

  • MPEG Composer

4、传输软件

  • MPEG ComMotion UDP 3.5
  • MPEG ComMotion Pro
  • Commotion Receiver

5、解压平台

  • VIDEO PLEX? XPress Video Plex Plus

6、DVD制作

  • DVD Fab! Xpress

7、非线性编辑

  • MPEG Carver Pro

8、SDK 开发包


Oracle Video Server

Oracle公司的OVS

1 Oracle Video Server简介
OVS(Oracle Video Server)是能适合较大规模视频点播系统(几百个以上的并行输出码流)的视频服务器软件。Oracle公司的视频服务器(Video Server)可在包括网络计算机(NC)和机顶盒(SetTo pBox)在内的系列平台上播放视频。同时还可以传送MPEG2、AVI格式视频及WAV音响数据流。Oracle使用Oracle8。Oracle在客户机一端的应用开发工具很强大,它提供全套Java系列和ActiveX控制工具,允许在播放环境下顺利进行集成。在规模化的能力成为产品的关键时，Oracle公司的视频服务器是个不错的选择。

2 ORACLE视频服务器系统组成

ORACLE视频服务器系统包括以下几个部分：

  • ORACLE视频服务器（OVS）
  • ORACLE视频客户机（OVC）
  • ORACLE视频服务器管理器（VSM）
  • ORACLE数据库

OVS的特点：
OVS是建立在简化的Unix操作系统，操作使用方便。 OVS是一个开放的网络系统结构,支持从局域网(LAN)、电缆电视系统(CATV)、数字视频广播(DVB)到卫星网络系统。 OVS遵循Client/Server 体系结构。Client可以是机顶盒(set top box)、微机、网络计算机等设备,它们具有通信功能并能解码MPEG-1或MPEG-2流，Server可以是一个或一组运行OVS服务的计算机。

3 OVS系统上的视频通信过程

    在OVS上一个典型的视频请求与播放过程有以下几步组成：

  • 应用服务器上的软件使得客户机能通过定制的视频接口导航。
  • 当客户机发出一个视频请求，请求命令被送到视频服务器。
  • OVS收到请求后，如确认有足够的资源发送视频内容，就从硬盘的存储区中取出视频内容。
  • OVS通过视频流将视频内容"流"到客户端。
  • OVC收到视频流在PC或电视上播放。

图3-1 基本的视频请求与播放过程

4 客户端与服务器之间的RTSP通信

客户端应用程序使用实时流协议（RTSP）与视频服务器通信,RTSP是一个应用层的协议它提供了一个可控、点播发送实时数据如声音和视频的可扩展框架。

另一方面，OVS内部过程的通信是通过Oracal媒体网络（Oracle Media Net）。Oracal媒体网络是使用异类网络协议的亚网络结构，它使得OVS各部分在分布式网络结构中有效地通信。它是Oracle的 CORBA实现。另外它还负责OVS的错误与警告消息的日志纪录。 为使得OVS和OVC能互相通信，OVS包括作为中间层的RSTP服务，它处在RTSP客户端与基于网络的OVS媒体过程之间。如图4-1所示，RSTP服务接受来自客户端的基于RTSP的请求，并将RTSP请求映射到适当的基于网络的OVS调用，通过执行合适的OVS过程上的媒体网络调用，并将响应对应到RTSP，然后发送到客户端。

图 4-1 RTSP客户端与OVS通信

5 OVS与不支持RTSP协议的客户端通信
对于不使用RTSP通信的客户端，可使用桥服务器与RTSP服务器通信。例如桥服务器使得客户端能使用对象代理协议（Object Request Broker protocol） ORB与RTSP服务器通信。这种情况下，桥服务器将ORB调用翻译成他们各自的RTSP请求。如图5-1所示，单一的桥服务器能服务来自多个客户端的请求，将它们翻译成RTSP并复合在一起，然后通过一个单独的控制通道连接到RTSP服务器，同时这个单独的控制通道也被桥服务器用来接收来自RTSP服务器的复合应答。

图 5-1 非RTSP通过桥服务器与OVS通信

6 OVS处理视频请求的内部过程
当客户端请求视频，OVS必须分配适当的资源，从存储库里查找数据，然后发送视频到客户端。图6-1图解说明了OVS处理视频请求的主要内部服务。这些服务包括：

  • 会话与回路服务（vscsmsrv）
  • 流服务(vsstrmsrv)
  • 内容服务(vscontsrv)
  • MDS 目录服务器 (mdsdirsrv)
  • 视频泵(vspump)

括号中的术语如vscsmsrv和vsstrmsrv是OVS认可的内部过程名。管理OVS的所有程序遵守这些命名惯例。

图 6-1 OVS 处理视频请求的内部服务

6.1 会话与回路服务（vscsmsrv）
会话与回路服务的主要任务（vscsmsrv）是建立和保持客户端/服务器端的会话，并为客户端设备管理一批OVS资源。当客户端请求一段视频，会话与回路服务首先建立一个会话，每个会话包括：

  • 一个客户端标识，
  • 客户端与(OVS)之间控制消息与视频传输的一个或多个回路，
  • 客户端及其连接到OVS的资源或状态信息。

每个客户端设备仅允许一个会话，当客户端结束它的会话，会话与回路服务释放所有会话的回路和资源。每个会话和一个或更多回路相关联。一个回路由客户端与服务器端的一个或多个通信通道组成。有单一通道组成的回路叫对称回路，又两个通道组成的回路叫非对称回路。
共有三种类型的通道：

  • 上流，描述从客户端到服务器端的连接。
  • 下流，描述从服务器端到客户端的连接。
  • 双向流，描述从客户端到服务器端的双向连接。

在一个方向上（上或下）通信的回路叫单向回路，在两个方向上（上和下）通信的回路叫双向回路，
在宽带网络中，机顶盒设备与OVS通过低带宽上行信道通信，同时通过高带宽下行信道接收视频，这是使用的是非对称双向回路。

6.2流服务
在通信会话建立后，客户端的视频请求接着被送到流服务处理，流服务完成下列处理：

  • 通知内容服务把对逻辑内容标题的请求解析成一个或多个标题文件
  • 读取与逻辑内容标题相关的标题文件，每个标题文件对应了要发送的请求文件的某个部分。
  • 告诉视频泵要播放内容文件的哪个部分。
  • 指示视频泵以实时流的形式发送视频数据。

6.3 内容服务(vscontsrv)
映射客户端请求的逻辑内容标题到存储在MDS的相关内容文件的信息保存在数据库中，由内容服务管理。当客户端应用程序请求一段视频，内容服务将请求一个逻辑标题的请求解析为一个或多个标识文件，这些标识文件接着被送到流服务，流服务通知视频泵发送视频。

6.4 MDS目录服务器(mdsdirsrv)
MDS目录服务器控制对MDS文件的访问，并管理它们在磁盘上的排列。读取或写入MDS文件的进程必须首先获取对MDS文件的访问权。例如，当视频泵获得命令播放一段视频，它向MDS目录服务器发送一个消息，得到一个描述要打开的文件在磁盘上排列的数据结构，从而可以打开文件。有了这些信息，视频泵就可以直接获取文件的内容，防止MDS目录服务器成为I/O瓶颈。

6.5视频泵(vspump)
视频泵从MDS上读取视频文件，然后将它们实时发送到网络上。在一个视频请求过程中，视频泵从流服务接收消息，从MDS上读取文件的对应部分，然后通过合适的下行信道从网络上将视频数据发送到客户端。

速度控制
速度控制是流服务和视频泵一起工作时提供的一种功能。速度控制使得客户端像录像机控制键的功能去控制和重定位流视频。OVS支持下列速度控制功能：

  • 暂停-停止视频播放并保持当前状态
  • 恢复-继续从停止点播放视频
  • 搜索-直接跳到视频的前点或后点
  • 扫描-直观快速向前或回绕

7 Oracle视频客户端回放接收的视频流
如图7-1所示，一个典型的客户端应用程序进行视频回放的构成包括三个逻辑部分：
前端：识别从键盘或鼠标、远程控制、或其它输入设备来的用户命令。这一部分也可以通过图形用户界面提供用户控制。
服务器端：管理到视频服务器控制信道，将用户命令转换成服务器命令，并处理从服务器来的响应。
流解码器：读取服务器从数据信道发送来的视频流，管理流的任何异常，同时把流数据解压并译码，并在客户端显示设备上播放。

图 7-1 OVS客户端的回放显示

8 管理与配置OVS
    管理OVS包括以下任务：

  • 系统规划
  • 基本配置
  • 启动、停止OVS
  • 查看系统日记
  • 监视用户端
  • 管理视频存储
  • 实况视频编码和流播出
  • 配置逻辑内容服务和节目预定服务
  • 提高网络负载平衡能力

8.1系统规划
OVS 是端到端遵循client/server结构的软件解决方案，它提供数字视音频的存储、管理、播放。要成功地实施OVS系统首先要考虑下面几个方面的问题：

  • 同时服务多少用户
  • 计划同时服务的用户数量影响对系统的整体配置，如服务器的处理器数量、网络带宽及系统提供的MDS文件系统的总量。
  • 要提供的视音频的的质量
  • 存储的视频文件数量即需要的硬盘空间
  • 是否要不停顿提供服务
  • 另外要提及的是编码速率与能同时服务的用户量是相互关联的，也就是编码速率越低，能同时服务的用户量越大，视频文件占用的存储空间越小。

8.2 硬件规划
OVS的性能和扩展性直接与服务器硬件相关，要对用户提供连续的流媒体服务，要求服务器应具有充足的处理能力、系统I/O和内存。
处理器越多支持的视频泵越多
要提供的流服务数越多，视频流的位率越大，需要的内存越多
硬盘驱动器I/O能力越强，视频服务器服务与扩展能力越强
要提供更多的负载平衡能力与带宽，应考虑视频服务器支持多网卡。

8.3规划Oracle媒体数据存储
OVS将内容存在Oracle媒体数据库中（MDS）,MDS是一个存储和发送连续实时视频的实时文件系统。配置MDS主要是确定以下几个方面的配置：

  • 视频内容的位率
  • RAID大小
  • 存储的内容多少
  • 同时提供的视频流数

8.4 基本配置
OVS提供两种管理界面配置服务器：OVS管理器（OVSM）和UNIX命令行。启动与停止OVS可以使用这两种管理界面。
OVS管理器:
OVS管理器提供了一个图形化用户界面来管理和监测OVS，除去操作任务，OVS控制台提供了完成基本配置任务的界面。但是，OVS控制台只允许配置值使用一个视频泵的过程，如果系统使用一个视频泵足已，OVS管理器就可作为主要的配置工具使用。
UNIX 命令行:
如果需要更复杂的配置，如需要提供多个视频泵过程来支持用户需要，就需要使用UNIX 命令行。使用UNIX 命令行要通过编辑ovsstart文件来实现，ovsstart文件作为OVS服务与过程的的启动脚本和配置文件。
基本的配置任务包括：

  • 设定最大的用户数
  • 调整视频流位率
  • 为多处理器服务器配置视频泵
  • 提高网络负载平衡

8.5 配置视频存储
Oracle媒体数据库是一个用来存储和实时播放多媒体数据到多用户的文件系统，访问MDS由MDS目录服务mdsdirsrv来控制，MDS的配置由配置文件voltab配置文件确定。voltab配置文件是定义所有OVS能访问的MDS卷的配置文件。
配置MDS有以下几个方面的内容：

  • 创建新的MDS卷
  • 建立到MDS卷的路径
  • 配置MDS卷的访问模式
  • 改变MDS卷的名字
  • MDS卷的碎片整理
  • 配置MDS卷能使用FTP访问
  • MDS内容的档案管理
  • 创建新的MDS卷:

如果视频文件库增长，系统的存储需求超过了原有的存储能力，这是就需要增加新的MDS卷。创建新的MDS卷要执行以下几个步骤：
    1． 关闭OVS.
    2． 编辑voltab文件来包括要创建的新的MDS卷。
    3． 使用mdsvolinit 设备初始化卷。MDS卷只有初始化之后才能被OVS访问。
    4． 使用mdsvolstat确定MDS卷的最大持续吞吐量。
    5． 使用新的 voltab文件来启动OVS （待续）


QuickTime

http://www.apple.com
苹果公司的QuickTime
Apple公司的QuickTime于1991年登台亮相，是Apple公司面向专业视频编辑、Web网站创建和CD-ROM内容制作领域开发的多媒体技术平台，QuickTime支持几乎所有主流的个人计算平台，是数字媒体领域事实上的工业标准，是创建3D动画、实时效果、虚拟现实、A/V和其他数字流媒体的重要基础。QuickTime 4是苹果公司最新的流视频平台，对于使用Mac OS X的用户来说是一个比较理想的流视频方案选择。目前QuickTime 4播放器已经在全世界被众多的Mac及视窗用户所采用，是仅次于RealPlayer、Windows Media Player的流视频播放器。QuickTime 4支持开放标准RTP 、RTSP 协议及HTTP 流。QuickTime的一个显著特点是支持转播功能和模块化API，用户可以方便地通过QTSS API为服务器添加新的功能。
QuickTime编程
第一节 QuickTime流式传输
QT流是通过网络将视频从服务器发送到客户的传输方式。与文件传输不同，客户端边下载边播放，而不必等到下载完毕。服务器将视频内容分成包，通过网络发送出去；在接收端，包被重新组装，到来后就可播放。QT支持单播和组播。

接收、播放视频内容
一般的，可通过打开视频文件、SDP文件与URL来打开流视频。通常调用NewMovieFromFile来打开视频文件，也可以调用NewMovieFromDataRef从URL打开视频文件。对实时流视频，URL必须使用RTSP协议。以RTSP
                    URL打开视频的代码如下：
char url[] = "rtsp://www.mycompany.com/mymovie.mov";
Handle urlDataRef;
urlDataRef = NewHandle(strlen(url) + 1);
if ( ( err = MemError()) != noErr) goto bail;
BlockMoveData(url, *urlDataRef, strlen(url) + 1);
err = NewMovieFromDataRef(&movieInfo->theMovie, newMovieActive,
nil, urlDataRef, URLDataHandlerSubType);
DisposeHandle(urlDataRef);
应用要可靠的播放实时流视频，必须遵从如下步骤：

  • 以高级视频工具箱或视频导入器打开视频。
  • 不要假定播放的视频轨结构反映了原始视频的轨结构。
  • 使用视频控制器播放视频，或使用新PrePrerollMovie函数在播放前设置流。
  • 显示视频控制器返回的状态信息。
  • 播放视频时准备处理播放错误
  • 准备动态改变视频特征，如高度、宽度等。
  • 不要认为视频立即开始播放。

服务器流式传输视频内容
服务器需要RTP服务软件与RTSP控制器应用传输视频内容，但不需要在服务器上安装QuickTime。如服务器仅充当组播中继，则不需要任何其它软件，以通常方式转发所请求的RTP流。

服务器在QT流视频中使用提示轨将视频打包成RTP流。如服务器发送有提示视频的单播， QuickTime视频控制器将允许用户暂停、快进与快退，这将用到RTSP与服务器通讯。RTP 服务器不需要知道QuickTime 媒体类型或codecs。视频文件中提示轨为将QuickTime媒体转化为RTP包提供了信息。每个提示轨包含建立特定轨媒体包头所需的数据，也提供了指向媒体数据的指针。RTP服务器要能够充分解析QuickTime视频文件以找到每个提示轨，然后再找到提示轨指向的轨和采样数据。提示轨包括一些必要的预计算值，使服务器创建RTP包更容易。提示轨减少了RTP服务器很多计算量，结果使RTP服务器发送数据更有效。

第二节 QuickTime流式传输服务器（QTSS）端模块
QTSS是一个代码公开、基于标准的流式传输服务器，可运行在多种UNIX操作系统上，如Mac OS Server、Linux、 FreeBSD与Solaris。要使用QTSS编程接口，必须熟悉RTSP、RTP、RTCP与SDP协议。QTSS的核心功能是作为模块实现的，对模块的支持被设计进服务器的核心。可开发独立的模块，在服务器启动后载入；也可将代码与服务器一起编译。两种方法的模块是相同的，不同的是编译方式。

每个QTSS 模块必须实现两个程序：主程序与分派程序。主程序是在QTSS初始化模块时调用，而服务器调用分派模块实现特定目的。
主程序模块：
QTSS_Error MyModule _Main(void*inPrivateArgs)
{
return _stublibrary_main(inPrivateArgs,MyModuleDispatch );
}
分派程序模块：
    void MyModuleDispatch (QTSS_Role inRole,QTSS_RoleParamPtr inParams);

2．1 模块角色
角色给模块提供了为执行某种类型处理而已定义好的状态。QTSS_Role定义每个角色的类型，并表示服务器的内部处理状态。一般的，服务器使用对象来交换模块间的信息。

2．2 QTSS对象
QTSS对象为模块从服务器取得数据与向服务器提供数据提供了一条途径。QTSS定义了几个对象，每个对象都有一套预定义的属性。服务器定义了如下一些对象类型描述客户连接和流，RTSP头、连接和请求，全局服务器信息、服务器偏好和错误信息。

    QtssRTPStreamObjectType：
    单个RTP流相关属性，RTP流对象(RTPStreamObject )是这个对象类型的
    事例，调用QTSS_AddRTPStream 创建。

    qtssClientSessionObjectType ：
    客户连接相关属性。

    QtssRTSPSessionObjectType：
    RTSP客户服务器连接相关属性，RTSP连接对象(RTSPSessionObject ) 是这个对象类型的一个事例。

    QtssRTSPRequestObjectType：
    单个RTSP请求相关属性，RTSP请求对象(RTSPRequestObject ) 是这个对象类型的一个事例。

    qtssRTSPHeaderObjectType ：
    单个RTSP请求相关的所有RTSP请求头。

    QtssServerObjectType：
    全局服务器属性，如服务器统计。

    QtssPrefsObjectType：
    服务器内部偏好存储系统的属性。

    qtssTextMessageObjectType ：
    包含其值将返回给客户的属性。

    取得属性值
    模块使用存储在对象中的属性与服务器交换信息，因此需要频繁的设置或取得属性值。有些属性是抢先安全的，可在任何时候调用QTSS_GetValuePtr 取得其值；另一些属性是非抢先安全的，必须调用QTSS_GetValue 取得其值。获得对象属性代码如下：
UInt32 MyGetNumCurrentConnections(QTSS_ServerObject inServerObject)
{
//qtssRTPSvrCurConn is a UInt32,so provide a UInt32 for the result.
UInt32 theNumConnections =0;
//Pass in the size of the attribute value.
UInt32 theLength =sizeof(theNumConnections);
//Retreive the value.
QTSS_Error theErr =QTSS_GetValue(inServerObject,qtssRTPSvrCurConn,0,
&theNumConnections,&theLength);
//Check for errors.If the length is not what was expected,return 0.
if ((theErr !=QTSS_NoErr)||(theLength !=sizeof(theNumConnections))
return 0;
return theNumConnections;
}

QTSS_RTSPMethod MyGetRTSPRequestMethod(QTSS_RTSPRequestObject inRTSPRequestObject)
{
QTSS_RTSPMethod*theMethod =NULL;
UInt32 theLen =0;
QTSS_Error theErr =QTSS_GetValuePtr(inRTSPRequestObject,qtssRTSPReqMethod,0,
(void**)&theMethod,&theLen);
if ((theErr !=QTSS_NoErr)||(theLen !=sizeof(QTSS_RTSPMethod))
return -1;//Return a -1 if there is an error,which is not a valid
//QTSS_RTSPMethod index
else
return *theMethod;
}

2．3 QTSS服务
QTSS服务是模块可访问的，可以是服务器提供的内建服务，也可以是另一模块提供的附加服务。例如，日志模块允许其它模块向错误日志中写信息。模块使用回调程序注册、激活服务，与以添加、查找对象属性类似的方式添加、查找服务。
每个服务有一个名称，要激活服务，调用模块必须知道服务名称，并将名称解析成ID。服务有着自身特定的参数块格式，输出服务的模块应将输出的服务仔细归档。模块在注册角色中调用QTSS_AddService将服务添加到服务器内部数据库中，代码如下所示：
void MyAddService()
{
QTSS_Error theErr =QTSS_AddService("MyService",&MyServiceFunction);
}
MyServiceFunction函数对应于必须在同一模块中实现的函数名称，如：
QTSS_Error MyServiceFunction(MyServiceArgs*inArgs)
{
//Each service function must take a single void*argument
//Implement the service here.
//Return a QTSS_Error.
}
    为了使用服务，模块调用QTSS_IDForService 获得服务的ID，并将服务名称作为一个参数。模块使用服务ID调用QTSS_DoService 使服务运行，代码如下：
void MyInvokeService()
{
//Service functions take a single void*parameter that corresponds
//to a parameter block specific to the service.
MyServiceParamBlock theParamBlock;
//Initialize service-specific parameters in the parameter block.
theParamBlock.myArgument =xxx;
QTSS_ServiceID theServiceID =qtssIllegalServiceID; //Get the service ID by providing the name of the service.
QTSS_Error theErr =QTSS_IDForService('MyService ',&theServiceID);
if (theErr !=QTSS_NoErr)
return;//The service isn 't available.
//Run the service.
theErr =QTSS_DoService(theServiceID,&theParamBlock);

第三节 QuickTime的Windows编程
QuickTime为Windows编程提供了完整的开发包，这里只简单介绍在Windows环境下编程的步骤并给出例程。 开发基本步骤为：

    1、在程序其始处初始化QuickTime媒体层(InitializeQTML) 与QuickTime(EnterMovies) 。
    2、建立QuickDraw图形端口与视频窗口(CreatePortAssociation)的联系。
    3、打开视频文件(OpenMovieFile) 并从中提取视频内容(NewMovieFromFile)。
    4、创建屏幕上显示视频的控制器 (NewMovieController)。
    5. 在窗口过程中，将输入信息转化成QTML事件(WinEventToMacEvent) 并将其传输给视频控制器进行处理 (MCIsPlayerEvent)。
    6、当不再需要时，处理视频(DisposeMovie) 和视频控制器。
    7、当窗口被破坏时(DestroyPortAssociation)，处理视频窗口图形端口。
    8. 在程序结束处，中断QuickTime (ExitMovies) 与QuickTime 媒体层(TerminateQTML)。

以下例程说明了程序框架与建立典型Windows应用程序的步骤：

#define IDM_OPEN 101

// Global variables
char movieFile[255]; // Name of movie file
Movie theMovie; // Movie object
MovieController theMC; // Movie controller
//////////////////////////////////////////////////////////////////////
int CALLBACK WinMain (HINSTANCE hInstance, HINSTANCE hPrevInstance,
LPSTR lpCmdLine, int nCmdShow)
{
    InitializeQTML(0); // Initialize QTML
    EnterMovies(); // Initialize QuickTime

///////////////////////////////////////////////////////////////////////
// Main message loop
///////////////////////////////////////////////////////////////////////

    ExitMovies(); // Terminate QuickTime
    TerminateQTML(); // Terminate QTML
} /* end WinMain */
//////////////////////////////////////////////////////////////////////
LRESULT CALLBACK WndProc (HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam)
{
    MSG winMsg;
    EventRecord qtmlEvent;
    int wmEvent, wmId;
// Fill in contents of MSG structure

    NativeEventToMacEvent (&winMsg, &qtmlEvent);// Convert message to a QTML event
    MCIsPlayerEvent (theMC, (const EventRecord *) &qtmlEvent);
// Pass event to movie controller
switch ( message )
{
    case WM_CREATE:
    CreatePortAssociation (hWnd, NULL); // Register window with QTML
    break;
    case WM_COMMAND:
    wmEvent = HIWORD(wParam); // Parse menu selection
    wmId = LOWORD(wParam);
    switch ( wmId )
{
    case IDM_OPEN:
    CloseMovie (); // Close previous movie, if any
    if ( GetFile (movieFile) ) // Get file name from user
    OpenMovie (hWnd, movieFile); // Open the movie
    break;

    default:
    return DefWindowProc (hWnd, message,
    wParam, lParam); } /* end switch ( wmId ) */
    break;
    case WM_CLOSE:
        DestroyPortAssociation (hWnd); // Unregister window with QTML
    break;

    default:
    return DefWindowProc (hWnd, message, wParam, lParam);
} /* end switch ( message ) */
    return 0;
} /* end WndProc */
/////////////////////////////////////////////////////////////////
BOOL GetFile (char *movieFile)
{
    OPENFILENAME ofn;
// Fill in contents of OPENFILENAME structure

    if ( GetOpenFileName(&ofn) ) // Let user select file
        return TRUE;
    else
    return FALSE;
} /* end GetFile */
////////////////////////////////////////////////////////////////
void OpenMovie (HWND hwnd, char fileName[255])
{
    short theFile = 0;
    FSSpec sfFile;
    char fullPath[255];
    SetGWorld ( (CGrafPtr)GetNativeWindowPort( hwnd ), nil); // Set graphics port
    strcpy (fullPath, fileName); // Copy full pathname
    c2pstr (fullPath); // Convert to Pascal string
    FSMakeFSSpec (0, 0L, fullPath, &sfFile); // Make file-system
// specification record
    OpenMovieFile (&sfFile, &theFile, fsRdPerm); // Open movie file
    NewMovieFromFile (&theMovie, theFile, nil, // Get movie from file
    nil, newMovieActive, nil);
    CloseMovieFile (theFile); // Close movie file
    theMC = NewMovieController (theMovie, ... ); // Make movie controller

} /* end OpenMovie */
////////////////////////////////////////////////////////////////
void CloseMovie (void)
{
    if ( theMC ) // Destroy movie controller, if any
    DisposeMovieController (theMC);
    if ( theMovie ) // Destroy movie object, if any
    DisposeMovie (theMovie);
} /* end CloseMovie */


RadVision
http://www.radvision.com/
OnLAN
RADVISION's award-winning OnLAN family of V2oIP networking systems can be used to build a total enterprise IP-based PBX network solution that supports both voice and video, or can be integrated as network components with other IP communications systems.
The OnLAN family includes:
Gateways - for interfacing between traditional circuit-switch networks and IP networks.

IP Conferencing Bridges - for voice or multimedia conferencing over packet networks among three or more participants.
Gatekeepers - for call control and network management

viaIP
Designed for next generation communications networks for the V2oIP experts, RADVISION's new viaIP multi-function platform is a superior IP-centric solution for deploying enhanced real-time voice, video and data conferencing services.

The viaIP product family provides cost-effective solutions for the IP communication requirements of service providers, government agencies and large enterprises. viaIP products integrate multimedia gateway, multipoint conferencing, data collaboration, and gatekeeper intelligence into a single platform.
RADVision推出通过IP的多种服务平台

2000-12-06

亚洲网香港消息，RADVision 公司（纳斯达克市场代码：ＲＶＳＮ）－－用于通过因特网协议实时传输音像通信的获奖的、行业标准产品与技术的领先提供商－－４日宣布向亚太市场推出其基于机架的通过因特网协议的多种服务平台。这种通过因特网协议的平台正在香港举行的电信亚洲２０００会议上展出。这是一次针对服务提供商、下一代电信公司、大型企业的重要电信会议，时间为１２月４日至９日。RADVision 公司的通过因特网协议的一体化解决方案把多媒体网关、多点会议、数据集合，以及网关控制器智能集成到一个单一的、基于标准的平台上。这种成本有效的、因特网音像通信（V2oIP （商标））解决方案向在大型因特网协议通信网上配置ＩＰ中心语音、图像和数据服务提供了规模可调节性和得到验证的互动操作性。这是在大型因特网通信网上配置ＩＰ中心语音、图像和数据服务所需要的。

RADVision 公司展位＃３３１７号的访问者将获邀参与互动式“图像酒吧”，这里有座位，访问者可以在这儿轻轻松松和互动地使用由领先的图像设备制造商提供的图像通信终端产品。设备制造商包括：Polycom和ＶＣＯＮ。４个Polycom公司的观览站和４个ＶＣＯＮ公司的ViGO站将由通过因特网协议来管理，以展示互动式多点会议和数据集合能力。

RADVision 公司今年早些时候成立的一家子公司，负责向日益扩展的亚洲市场提供销售和营销支持的RADVision （香港）公司的经理唐·霍奇伯格说：“亚太市场正在经历ＩＰ网上大规模音像传输的显著增长，尤其是在中国内地、台湾地区及韩国这些地方。RADVision 公司的通过因特网协议为高容量、ＩＰ中心多点／网关平台设立了一套全新的价格／性能标准。它支持最大数量的并行用户、会议和参与者，并且是目前现有的最具成本效益、灵活和方便用户的解决方案。”

RADVision 公司现在在主要活动场合推出通过因特网协议，并在全球进行路演。该公司在美国的ＩＳＰＣＯＮ和亚太电信亚洲展示会作首次推出之后，RADVision公司将于２００１年１月１５日至１８日，在伦敦、巴黎和慕尼黑的欧洲路演中在整个欧洲推介其通过因特网协议平台。如果您想注册，或者需要更多信息，请访问公司网址：http://www.radvision.com。

通过因特网协议－４００（viaIP-400）简介

通过因特网协议－４００预计于２００１年第一季度开始出货，它是公司推出的通过因特网协议平台的首个版本。它是一个４Slot Compact PCI（注册商标）（cPCI）机架，具有支持热交换、混合－匹配功能。这种高度可配置和规模可调节的设计支持用于多点V2oIP 会议功能的ＭＣＵ卡，每张卡可用于３０个、６０个和１００个会议点，高性能Windows NT（商标）应用服务器卡用于运行数据集合服务器（ＤＣＳ）和增强型通信服务器（ＥＣＳ）应用产品。ＥＣＳ提供Ｔ１２０数据共享能力。ＥＣＳ提供先进的网关控制器功能，用于管理Ｈ３２３网络资源，实施策略，对实时的音像传输进行控制。用于Ｈ３２０和Ｈ３２３之间转换的每张有两个ＰＲＩ界面的多媒体网关卡将于２０００年第二季度推出。

RADVision公司简介
RADVision 公司是支持通过数据包网络进行实时语音、图像和数据通信的产品和技术的领先提供商，这些网络包括因特网和其他基于因特网协议或ＩＰ的网络。RADVision公司的产品和技术被RADVision公司的客户用来开发这样的系统，它支持企业和服务提供商使用下一代实时ＩＰ通信的数据包网络。RADVision 公司积极参与行业标准的制定，这种标准推动用于实时通信的数据包网络使用的兴起和发展，并且是支持技术和通过数据包网络进行实时语音、图像传输所需的产品的第一个推向市场的标准。结果是，RADVision 公司具有以其产品和技术领导市场的优势，其产品和技术支持企业和服务提供商把他们的语音和图像通信从传统的电话网络移植到下一代数据包网络传输。该公司的产品和技术包括基于标准的网关、会议桥、网关控制器和软件工具组。如需更多信息，请访问我们的网址：http://www.radvision.com。

本新闻稿中含有前瞻性声明，要受到风险和不确定性的影响。可能会造成实际结果与这些前瞻性声明中所陈述的结果大不相同的因素包括，但不限于，行业的总体商情，对产品需求的变化，订单的时机、数量或取消订单，以及RADVision公司不时向证券交易和管理委员会提交的文件中所详述的其他风险，包括RADVision公司的Ｆ－１注册声明。所有商标都已被确认。

消息来源：RADVision公司

联系人： CONTACT:凯伦·格威兹， Karen Gurwitz,
Dir公司 Dir, Corp,
RADVision有限公司通联部， Communications of RADVison,Inc.
电话：201-539-4300, ext. 305电子邮件：kgurwitz@radvision.com； kgurwitz@radvision.com;

戴维·塞利格曼， David Seligman,
RADVision公司首席财务官， CFO of RADVision, Ltd.,
电话： +972-3-645-5446,电子邮件：Seligman@tlv.radvision.com； Seligman@tlv.radvision.com;

桑杰·赫里 或者乔迪·伯芬宁 Sanjay Hurry or Jody Burfening
ＬＨＡ投资者关系部， Investor Relations of LHA,
电话： 212-838-3777,电子邮件：jbs@lhai.com， jbs@lhai.com,
服务于RADVision有限公司 for RADVision, Inc.,
网址：http://www.radvision.com Web site:http://www.radvision.com
http://www.lhai.com http://www.lhai.com


RealNetworks

RealNetworks公司是世界领先的网上流式视音频解决方案的提供者,提供从制作端、服务器端到客户端的所有产品。它的客户端播放器 Realplayer的全球注册人数已经超过了一亿六千万人。ReaNetworks公司最新的网上流式视音频解决方案叫RealSystem IQ，RealSystem IQ容易安装，在高低带宽均可提供良好的视音频质量，但价格较贵。作为流媒体领域的主导厂商，ReaNetworks公司凭借其优秀的技术,占领了一多半的网上流式视音频点播市场。

1 RealSystem系统组成
RealSystem IQ由服务器端流播放引擎(realserver)、内容制作、客户端播放三个方面的软件组成：

  • 制作端产品：RealProducer 有初级版(Basic)和高级版（Plus）两个版本。RealProducer的作用是将普通格式的音频、视频或动画媒体文件通过压缩转换为RealServer能进行流式传输的流格式文件。它也就是RealSystem的编码器（encoders）。 RealProducer是一个强大的编码工具，它提供两种编码格式选择： HTTP 和SureStream，能充分利用RealServer服务器的服务能力。
  • 服务器端产品：服务器端软件RealServer用于提供流式服务。根据应用方案的不同，RealServer可以分为basic、plus、intranet和professional几种版本。代理软件RealSystem Proxy 提供专用的、安全的流媒体服务代理，能使ISPs等服务商有效降低带宽需求。
  • 客户端产品：客户端播放器RealPlayer分为 Basic和Plus两种版本，RealPlayer Basic是免费版本，但RealPlayer Plus不是免费的，能提供更多的功能。RealPlayer既可以独立运行，也能作为插件在浏览器中运行. 个人数字音乐控制中心RealJukebox能方便地将数字音乐以不同的格式在个人计算机中播放并且管理。

2 RealSystem的通信过程与协议
2.1 RealSystem通信使用的通道和协议
RealServer使用两种通道与客户端软件realplayer通讯：一种是控制通道，用来传输诸如"暂停"、"向前"等命令，使用TCP协议；另一个是数据通道，用来传输实际的媒体数据，使用UDP协议。 RealServer主要使用两个协议来与客户端联系： RTSP (Real Time Streaming Protocol) 和 PNA (Progressive Networks Audio).

图2-1 Encoder、RealServer和RealPlayer之间的通信

如图2-1所示，在RealSystem中，通信过程可分为两部分：

Encoder与RealServer之间的通讯
当Encoder需要向RealServer传输压缩好的数据时，通常使用one-way(UDP)与RealServer通讯。而一些防火墙通常禁止UDP数据包通过，因此，RealProducer可以设置成使用TCP协议的方式向服务器传输数据。
RealServer与RealPlayer之间的通讯
当用户在浏览器上点击一个指向媒体文件的链接时，Realplayer打开一个与RealServer的双路连接，通过这个连接与RealServer之间来回传输信息。一但RealServer接受了客户端的请求，它将通过UDP协议传输客户请求的数据。

2.2 RTSP通信
2.2.1 Realplayer播放过程
如图10-2 所示，浏览器通过HTTP协议向RealServer服务器发出请求，URL请求中包含激活RAMGEN的参数。 指向被请求SMIL文件的URL引发RAMGEN自动产生一个包含SMIL文件位置的RAM文件，这个RAM文件将被传送给浏览器。 RAM文件的扩展名（.ram 或者.rpm）将使得浏览器激活RealPlayer程序。

图2-2 RealPlayer的视频播放过程

RealPlayer接受浏览器传递过来的RAM文件，然后用RTSP协议与RealServer进行通讯，请求该RAM文件中包含的SMIL文件。 根据在SMIL文件中包含的信息，Realplayer向RealServer请求、接受并播放媒体元素。
RTSP 通信数据包格式
RealNetWorks公司在RealSystem系统中率先实现了RTSP标准协议通信。RTSP 协议通信是一种有状态的通信，在语法及操作上均与HTTP/1.1很相似，但仍有许多方面区别很大，如RTSP 服务一般需要保持状态，而HTTP本质上是无状态的。
对于 RTSP通信, 数据可以通过不同的协议进行传输（如 RDT或 RTP）。目前，RealServer通过标准的实时传输协议RTP和Real数据传输协议RDT两种数据包格式将流媒体数据发送到RTSP客户端。
1.标准RTP通信
RTSP 客户端在UDP上使用RTP协议与RTSP服务器通信时建立三个网络信道，如图所示：全双工TCP连结用来进行控制、协商，单工UDP信道用来使用RTP包格式传送媒体数据。全双工UDP信道访问RTCP用来向客户端提供同步信息，将包丢失信息发送给服务器。

图2-3 RTSP Client/Server通信的标准UDP模式

2.RealNetworks' RDT
当数据使用RDT发送时，RTSP 客户端与RTSP服务器通信时建立三个网络信道，如图所示：
全双工TCP连结用来进行控制、协商，单工UDP信道用来使用RTP包格式传送媒体数据。另一条UDP信道客户端用来向服务器请求重发送丢失的UDP媒体数据包。

图2-4 RTSP Client/Server通信的标准RDT模式

3 RealServer 中的组播（Multicast）
3.1 简介
RealServer中的组播是将一个现场直播流同时传递给多个客户端，而无需为每一客户的连结发送一个单独的数据流，客户端只需连结到这个数据流，而不是连结到RealServer服务器，从而降低带宽的使用。为了利用组播技术所带来的优越，在RealServer与Realplayer客户端之间的所有设备必须是支持组播技术的，包括之间的路由器、交换机、和其他的网络设备。正是由于这个原因，组播通常用在Intranet环境中。RealServer的组播有两种：反向信道组播（back-channel multicast）和可伸缩组播（scalable multicast）,这两种方法可同时使用。
3.2 反向信道组播（back-channel multicast）：
反向信道组播（back-channel multicast）在客户端和服务器之间保持一个用于统计和控制信息交互的控制信道如图3-1所示，由于客户端和RealServer之间的信息交换是双向的，从而能发送验证信息、用户统计及服务质量信息等，象RealSystem管理器中Java Monitor之类的监视工具可以显示客户端的情况。反向信道组播（back-channel multicast）的访问可以使用RTSP 或PNA协议，RTSP组播比PNA组播多提供一项智能流（SureStream）功能，两者均提供验证和连接统计功能。

图 3-1 反向信道组播

3.3 可伸缩组播（scalable multicast）
与反向信道组播，可伸缩组播没有控制信道，所以这种方法占用更少的带宽，RealServer的系统资源使用也少。由于没有控制信道，Java Monitor之类的监视工具就不能跟踪用户的活动，用户统计也只能在组播结束或用户停止播出或关闭RealPlayer播放器时。
由于传输是单向的，可伸缩组播能向无限的用户播放。提供验证、连接统计和智能流功能。如图10-12所示：

图 3-2 可伸缩组播

可伸缩组播使用不同于RTSP组播或 PNA组播的URL格式，用户连接到可伸缩组播是通过点击 会话描述协议文件（SDP）的链接，此文件是用户点击链接时，RealServer自动产生的。

4 RealServer中的分流技术（splitting）
RealServer中使用分流技术（splitting）在服务器之间传输直播数据。Splitting方法可以解决RealServer超负荷的问题，使得客户端可以就近访问realserver服务器，获得更好的访问质量，并且减小带宽使用，服务更多用户。Splitting技术可以采用UDP单播、UDP组播和TCP三种方式进行通信。通过分流，一个或者多个RealServer服务器加入到transmitter中，来分散transmitter的流数量，而不是所有的请求都到达一个RealServer服务器。

图 4-1 分流技术示意图

如图4-1所示：实况内容源处的RealServer是发送服务器（transmitter），它将实况播放给其他RealServer服务器接收，接收的RealServer服务器(receiver)一般更靠近访问者。网页上的链接指向接收的RealServer服务器而不是发送服务器。当用户点击链接时，接收服务器识别出特定的URL，然后把从发送服务器来的视频流转播给用户。
当transmitter开始播放实况流，它将节目广播给所有的receiver。当用户从receiver上请求一个播出节目时，transmitter和receiver之间已经建立了一个连结，播出节目也就立即发送到用户。

RealSystem 8中有两种分流方法: 推(push splitting)和拉(pull splitting)。
推模式要预先建立一个连接，所以第一个客户端的连接不用等待。当等待listen的过程中要占用带宽。当一个客户端请求一个媒体文件时，由于transmitter和receiver之间的连接已经建立，所以可以立即传送媒体流，这是RealSystem 8 的缺省方式。

拉模式不需要预先建立一个连接，当第一个连接建立后要保持该连接，除非编码器停止编码。第一个请求的客户端必须等待30秒或者一个连接建立。一个连接请求将列出包含该媒体文件的transmitter和receiver之间的名字，当一个receiver收到一个传送文件的请求时，将向transmitter请求打开一个媒体流，RealServer将媒体流发送给splitter,splitter再将媒体流发送给客户端。这两种方法可以同时使用。

RealServer 8.0 版本与以前的版本有些不同，transmitter和receiver之间能通过组播通信，以节约带宽。

  RealSystem SDK

RealServer和RealSystem的客户端都支持开放的流传输协议，并允许和其它基于标准流数据系统进行交互操作。RealSystem SDK提供开发者扩展和自定义RealSystem 的公共接口，该SDK允许开发者进行如下开发：
· 流式传输新数据类型
创建RealSystem客户端应用
自定义RealServer
1 SDK简介
RealSystem是基于COM二进制标准，可使用任何编程语言开发RealSystem 组件。但为了简化跨平台开发，RealSystem与COM标准略有差异。

RealSystem可执行文件和函数库位于SDK的/bin 目录下。开发包中播放器有RealPlayer与TestPlay。实现了RealPlayer的核心功能，但没有图形用户接口。可使用TestPlay来测试你开发的插件，也可以其为基础建立RealSystem客户端。测试程序时，服务器端可采用RealServer。

插件结构是RealSystem的核心，它允许RealServer流式传输任何数据类型，也允许你定制RealServer。在Windows平台上，RealSystem 插件是32为动态链接库；在UNIX 与Macintosh平台上，是共享库。由于RealSystem提供几个跨平台服务，所开发的插件代码不特定针对操作系统。

RealSystem头文件定义RealSystem接口。头文件包含函数变量与返回值的信息。头文件位于所下载SDK的include目录下。

SDK中包含大量事例，你可使用这些事例文件作为模板建立RealSystem组件。应用这些代码需要C或C++的知识，这些代码是与平台无关的。事例在samples 目录下，包括头文件、C++ 文件、与工程文件。

2 SDK安装

安装RealPlayer与TestPlay
运行RealPlayer安装程序，遵循如下步骤：
1)、指定安装位置，缺省为c:\Program Files\Common Files\Real\
2)、将PNEN3260.DLL, PNUI3260.DLL, and PNCRT.DLL放在c:\Program Files\Common Files\Real\Common目录下
3)、将插件安装在c:\Program Files\Common Files\Real\Plugins
4)、将codecs安装在c:\Program Files\Common Files\Real\Codecs
5)、配置浏览器，使收到.ram 或 .rpm文件时激活RealPlayer
为了使RealPlayer使用RTP数据传输格式代替标准的RDT从RealServer接收数据,在注册表中增加如下键：
HKEY_CLASSES_ROOT
\Software
\RealNetworks
\RealPlayer
\6.0
\Preferences
\UseRTP
键值为1时，使用RTP传输数据；键值为0时，使用RDT传输数据。
TestPlay是作为源代码提供的，在sdk/samples/intermed/testplay中。由于TestPlay与RealPlayer 使用相同的传输引擎、plug-ins和codecs ，如前所述安装RealPlaye最新版本，再编译。
安装、运行RealServer

RealServer运行在UNIX 或Windows 32位操作系统上，运行它需要许可证（license key）。你将在下载RealServer时提供的e-mail里收到许可证，将其拷贝到RealServer设置文件中即可进行安装。

RealServer可与任何支持MIME的网页服务器一起运行，在网页服务器中正确设置MIME使浏览器以RealPlayer播放RealSystem文件，而不是将文件下载到浏览器。下面几项是必须设置的：
application/smil
audio/x-pn-realaudio
audio/x-pn-realaudio-plugin

5 RealServer的系统需求
支持的操作系统及硬件

Processor | Operating System
Intel Pentium | Windows NT 4.0 or 2000 Workstation or Server, Linux 2.2 (glib c6), Free BSD 3.0
Sun SPARC | Solaris 2.6, 2.7, 2.8
IBM RS/6000 PowerPC | AIX 4.3
HP PA-RISC 2.0 | HP-UX 11.x
R4000 running MIPS3 instruction set | IRIX 6.5

内存需求
在原先RealServer占用的64MB可用内存基础上，每kbps数据流还要占用12K的内存。
例如：
20kbps需占用240KB的内存
100kbps需占用1200KB的内存
以下是比较常见的算法

Stream Data Rate | Max Size of Audience | Bandwidth Required | Example Connection
20kbps | 60 | 1200kbps or 1.2Mbps | T1
60% 20kbps, 40% 80kbps | 100 | 4400kbps or 4.4Mbps | Fractional T3
80kbps | 100 | 8000kbps or 8Mbps | 10Mbps fractional T3
20kbps | 2000 | 40000kbps or 40Mbps | T3

存储需求
RealServer本身大约需要8MB的存储空间和另外的媒体数据流所需空间，算法如下：
磁盘空间＝数据流速率×所需时间(s)÷8
对于自适应流式媒体文件的算法相对更困难一些，要求对每个嵌入式速率都进行运算。例如：

Data Rate of the Clip | Length in Seconds | Storage Required
20kbps (single rate) | 180 | 450KB
20kbps (SureStream) 20kbps rate 12kbps rate 8kbps rate | 180 | 900KB

WebServer的要求
RealServer与现有的大部分WebServer都是互相兼容的，并且支持MIME格式的建立。已经过测试无误的所有WebServer如下：
Apache1.1.1
CERNHTTPDversion3.0
EMWCHTTPSversion0.96
HTTPD4Mac
MacHTTP
Microsoft Internet Information Server
NCSAHTTPDversions1.3or1.4
Netscape Netsiteand Netscape Enterprise Server
0'Reilly Website NT
Spinnerversion1.0b12through1.0b15
WebstarandWebstarPS

3 开发框架
RealSystem也称为RealMedia 结构 (RMA)，基于微软组件对象模型(COM)。RealSystem组件使用COM的 IUnknown::QueryInterface 方法暴露其接口，接口以"IRMA"前缀开始，IRMA表示"RealMedia接口结构"。RealSystem没有采用COM的全部，而只实现COM的一个子集提供跨平台操作。应用SDK，可建立下列类型的插件。
文件格式Plug-in： 该插件将某种数据类型转化为RealServer可流式传输的包。尽管RealServer主要使用文件格式插件传输， RealSystem 客户端也可用它们来播放本地文件。
1.播放Plug-in ： 该插件接收数据包，并在客户端回放。每个文件格式插件有一个相应的播放插件。
2.文件系统Plug-in ： RealServer与RealSystem客户端使用文件系统插件从数据源读取文件。例如，可建立一个插件从数据库中读取数据。
3.广播Plug-in ： 广播插件将现场数据转化为RealSystem包。尽管你可建立自己的广播插件，RealSystem包括将编码应用与RealServer标准广播插件结合的远程广播库。
4.监控Plug-in： 监控插件从RealServer注册表中检索系统信息，如当前连接客户数目、客户所请求的URL。

3．1 创建Plug-In事例
RealSystem没有使用Windows CoCreateInstance函数创建插件对象，而是采用RMACreateInstance, 一种"C-风格"入口点，暴露IRMAPlugin 接口，它使用IRMAPlugin 决定插件特征。入口点样例如下：
STDAPI
RMACreateInstance(IUnknown** ppExFileFormatObj) {
*ppExFileFormatObj=(IUnknown*)(IRMAPlugin*)new CMyExampleFileFormat();
if (*ppExFileFormatObj != NULL)
{
(*ppExFileFormatObj)-AddRef();
return PNR_OK;
}

return PNR_OUTOFMEMORY;

RealNetworks
http://www.realnetworks.com

Real Networks Real Player 播放器
Realplayer8.0 下载 (11,777K) | RealPlayer8.0 完全正式Basic版
Real Jukebox2.0 下载 (7,933K) | Real Jukebox2，可以用来作为个人音乐中心，它可以将网上的Mp3等文件边下载边播放，也可以将CD音轨抓下来变成rmj格式，并可以制作目录并存放，另外它还支持Skin，使得界面更加灵活，漂亮。
Real Networks Real Rroducer 音视频制作

RealProducer8.0 下载 (4,507K)

 RealProducer8.0,可以在生成Real文件加入Keyword，便于搜索引擎自动搜索，还可以定义安全级别。在视频上，有RealVideo8选项，还多了两种过滤器，它可以生成比VHS还要好的视频，直播还多了一个协议的选择，UDP和TCP可选。另外，它还可以简单编辑Real文件，可以修改其Title,Author,copyright...等信息。

Real Networks Real Server 网络播放服务器

RealServer 7.0

RealServer 7.0 更好的支持自适应流，更稳定，能查看SMIL。

Real Networks Tools 工具
RealSlideShow 下载 (3,125K) | RealSlideShow，可以用来将图片文字和real文件组合，生成SMIL文件，使播放的时候更精彩。
RealPresenter 下载 (9,265K) | RealPresenter，将微软的Powerpoint文件转换，使得它可以在网上流式播放。
SMIL Composer 下载 (2,852K) SMIL Wizard 下载 (619K) | SMIL Composer，SMIL制作工具。
REALSERVER BASIC REPORTS 下载 (2,439K) | REALSERVER BASIC REPORTS BY LARIAT SOFTWARE，用来分析Realserver的日志，很有用的，可以分析视听的各种结果，并生成图表。
REAL System Proxy Server 下载 | REAL Proxy SERVER 可以用在局域网上，For NT，可以安装在 Windows NT上，使得在一个局域网上多台机器能连接同一个Real文件，而带宽连接只占用一条。
RealServer文档 | RealServer Administration Guide , RealServer Production Guide , RealSystem G2 SDK Developer's Guide
RealProducer文档 | RealProducer Plus User's Guide , RealProducer G2 Core SDK Developer's Guide
SMIL 文档 | Real Embed , SMIL , RealPix , RealText , SMIL Example 1(非洲美景) , SMIL Example 2(房屋展示) ...另外还有几个模板，也可以算例子，就不再列出了

3．2 建立RealSystem对象
RealSystem组件可使用the C++ new操作符创建对象，为了使对象可传递到其他RealSystem组件，组件应该使用IRMACommonClassFactory。当RealSystem 初始化组件时，向组件传递一个指向系统上下文的指针，组件可使用这个指针调用IRMACommonClassFactory::CreateInstance并创建一个新RealSystem对象。如：
m_pClassFactory-CreateInstance(CLSID_IRMABuffer, (void**)&pStringObj);

3．3 使用IUnknown::AddRef和IUnknown::Release

因为RealSystem对象经常被其他RealSystem对象使用，对象必须正确实现引用计数。COM函数 IUnknown::AddRef 和 IUnknown::Release 控制引用计数，从而决定每个对象的生命期。下列规则说明RealSystem组件何时需要AddRef与Release 对象：

下列函数在返回前AddRef对象。当组件用完对象，必须释放。
RMACreateInstance
IUnknown::QueryInterface
IRMAFileSystemObject::CreateFile
IRMAFileSystemObject::CreateDir
IRMACommonClassFactory::CreateInstance
如组件接收对象为一个函数的参数，组件必须AddRef该对象。当组件用完对象，必须释放。如组件以C++ new操作符创建一个对象，组件必须AddRef 对象，用完后释放掉。

3．4 异步操作
RealSystem组件异步调用，使用响应接口返回对其调用的数据。例如，文件格式插件通过IRMAFileObject从文件系统插件请求文件数据，文件系统插件然后使用IRMAFileResponse返回所请求的数据。此异步结构允许当文件系统插件准备所请求的数据时文件格式插件执行其他操作。有了RealSystem的异步特性，插件能在其处理数据或等待其它组件响应时处理任何调用。

3．5 使用IRMABuffer创建数据缓冲区Data Buffers
IRMABuffer接口允许RealSystem对象创建COM引用管理的数据缓冲区。RealSystem对象通常使用这些缓冲区对象传递数据。例如，文件系统插件通过缓冲对象将流的头数据传递给文件格式插件。创建缓冲对象如下：
通过IRMACommonClassFactory创建IRMABuffer接口
调用IRMABuffer::SetSize 设置缓冲区大小，执行内存分配。
调用 IRMABuffer::GetBuffer 获得指向缓冲对象的指针。
使用 IRMABuffer::Set 向缓冲区写数据。
传递缓冲区指针给其他组件。
用 IUnknown::Release释放缓冲区对象。
当组件收到指向缓冲对象的指针时，调用IRMABuffer::GetSize 得到缓冲区大小，而调用IRMABuffer::Get 读取缓冲区数据。

3．6 使用IRMAValues 创建索引列表
象IRMABuffer, IRMAValues 接口广泛用在RealSystem系统中。IRMAValues 接口允许RealSystem组件创建名称、数值通用列表。IRMAValues 数值类型如下：
unsigned long
指向任意数据缓冲区的指针
指向以null结尾的C字符串缓冲区的指针
RealSystem组件创建IRMAValues 对象过程如下:
通过 IRMACommonClassFactory 创建IRMAValues接口
调用IRMAValues::SetPropertyULONG32、IRMAValues::SetPropertyBuffer、或 IRMAValues::SetPropertyCString 方法添加名称/数值。
传递对象指针给其他组件。
用 IUnknown::Release释放接口。

事例如下所示：
IRMAValues* pHeaderObj = NULL;
m_pClassFactory-　　　　CreateInstance(CLSID_IRMAValues, (void**)&pHeaderObj);
if (pHeaderObj != NULL)
{ IRMAPluginpHeaderObj-SetPropertyULONG32("StreamCount", 1);
IRMAPluginpHeaderObj-SetPropertyBuffer("OpaqueData",
pHeaderDataReadFromFile);

收到指向IRMAValues 接口的指针后，RealSystem组件可使用IRMAValues::GetProperty 根据名称检索数值，此处 为ULONG32、缓冲区、或 Cstring。组件可通过IRMAValues::GetFirstProperty 与IRMAValues::GetNextProperty

遍历列表。

3．7 使用IRMAPacket创建流数据包
RealSystem组件使用IRMAPacket接口创建数据包。例如，文件格式插件需要此接口为服务器准备流数据包；而客户端播放插件使用系统后通道向文件格式插件发送信息包 。RealSystem组件创建包过程如下：
通过IRMACommonClassFactory创建IRMAPacket 接口。
调用 IRMAPacket::Set 向包传递一个指向IRMABuffer 接口的指针，并定义包属性，如发送时间、自适应智能流管理规则。包属性有助于RealSystem有效传输。
传递指向其他组件的包指针。
以 IUnknown::Release释放包接口。
事例如下所示：
IRMAPacket* pPacketObj = NULL;
m_pClassFactory-　　CreateInstance(CLSID_IRMAPacket, (void**)&pPacketObj);
if (pPacketObj != NULL)
{ IRMAPluginUINT32 deliveryTime = m_NextPacketDeliveryTime; IRMAPluginUINT16 streamNoIRMAPlugin = MY_STREAM_NO;
IRMAPluginUINT8 ASMFlags = RMA_ASM_SWITCH_ON;
IRMAPluginUINT16 ASMRuleNo = 0;
IRMAPluginpPacketObj-Set(pPacketDataReadFromFile, deliveryTime, streamNo, ASMFlags, ASMRuleNo);

收到指向包接口指针后，RealSystem组件用IRMAPacket::Get检索包数据。其他方法允许组件检索特定包属性。组件也可调用IRMAPacket::IsLost 决定包是否丢失。

3．8 设计插件
开发插件时，记住如下一些通用基本点：
1、尽可能保持插件简单、自足、通用。仔细考虑对通道时机和观众的影响。
2、记住RealSystem的异步特性。当在处理数据或等待其他对象响应时，你的插件必须能处理任何对它的调用。不要把插件编成依赖特定顺序。
3、努力使插件在未压缩时大小在300 KB 以下。
4、设计数据类型，满足所有用户，即28.8 Kbps 以上，随连接速度提高而扩展。
5、设计代码可在Macintosh、Windows,和UNIX 平台上运行。
6、不要依赖MMX 提高客户端回放质量。
7、如开发音频数据类型插件，使用RealSystem音频服务。此服务功能强大，可处理音频混合、采样、音量控制与即时声音。
8、由于RealPlayer和RealServer已本地化为多种语言，建议使用资源表等方便本地化。
9、为数据类型和插件提供优秀的文档。并把插件与文档分开，便于用户下载插件。
10、设计内容创建工具，考虑流式传输数据的速率。让设计者决定怎样制作内容。设计好的数据类型将使用自适应智能流特征给流速率分级。

3．9 编译插件
在开始开发插件前，应测试、编译几个例程。其中最简单的是"Hello World"插件，它在RealServer控制台上打印出 "Hello World"。"Hello World" 例程在/samples/intro/hellowld/hellowld.cpp 中。例程文件包含评论，解释每个函数功能。在 Windows上，RealNetworks 建议使用Microsoft的Visual C++ 4.2 或6.0。编译过程如下 ：
打开Microsoft Developer Studio程序。
在文件菜单中点击打开工作空间 。
在文件类型框选择Makefiles (*.mak)。
在欲测试的例程目录下选择make文件，并点击打开
在选择缺省工程设置框选择Release build或Debug build.。
点击 Build按钮或点击Build 菜单中Build 文件名。
也可在命令行编译，如：
nmake /f "exffplin.mak" CFG="exffplin - Win32 Debug" nmake /f 　　　　　　　　"exffplin.mak" CFG="exffplin - Win32 Release"
在UNIX 中，可采用gcc进行编译，如：
make -f unix/Makefile.

3．10 测试插件
下表是一个测试插件的基本指南：
确认所设计的扩展名文件类型与流MIME类型对应。
确认设计的文件类型播放正确。
确认窗口在播放器控制台内或外缺省位置正确。
如已实现，检验定位可正确工作。
确定暂停/恢复功能运行正常。
检验在流式传输中途停止运行正常。
确认在数据缓冲期间所期望行为发生。
确定内存用完时处理正确。
确认在较慢的机器上运行可接受。
看看播放器是否能同时在一台机器上播放几个流。
播放长时间流来测试每个包内存泄漏情况。


Red Spider

红蜘蛛软件
http://www.21cngo.com/down/downsoft.asp?softID=1344

红蜘蛛软件（Red Spider）运行于加载TCP/IP协议的Windows95/98/NT网络，主要在局域网上实现多媒体信息的广播，并同时实现网络屏幕监视和远程控制的目的。它专门针对电脑教学网络开发，可以非常方便地完成电脑网络教学任务，包括屏幕图象监视、远程控制、屏幕广播与点播、网上语音广播、两人对讲和多方讨论、VCD/MPEG/AVI/WAV/MOV等视频流的广播、电子教鞭、电子黑板与白板、自由的交互式短信息发送、电子举手、锁定学生机的键盘和鼠标等，而独特的"每日一读"功能还可以使老师的教学内容变得丰富多彩。

◇屏幕监视：同屏监视多个主机的屏幕图象内容

◇远程控制：同时远程控制网络上的一台或多台电脑主机

◇屏幕广播：实时广播“教师机”的屏幕图象内容到“学生机”上

◇屏幕点播：随时“点播”学生机进入“教师机”角色广播其屏幕

◇电子教鞭：可在屏幕上绘画图形标记、文字，进行“圈圈点点”

◇黑板白板：黑板与白板功能已经可以取代传统黑板了

◇消息传送：老师与学生，学生与学生之间可以自由进行消息传送

◇远程命令：远程重启和关机、锁定键盘、电子举手、网络分组等

◇每日一读：创意独特、使您的课堂生动而内容丰富


rhythm

北京太白星信息技术有限公司 - 语音及媒体流服务器研发，产品有通远程语音实时教学系统，双工语音聊天室。另有楼智能小区，网站建设等成功经验。

语音产品 Voice System
语音产品概述:语音产品的应用
-网络语音聊天社区
-远程有声教育
-实况转播系统
-远程安全商务会议
         语音产品的系统特点：

-中央服务器架构
-支持大访问量
-高度可定制性
-简洁的服务器接口
-完善的管理功能 		产品的性能指标：

-服务器冲击测试
-产品实测性能指标
-网络带宽需求
-客户端系统需求
         产品的功能描述：

-多种可选模块
-完善的权限管理功能
-用户功能
-服务器配置功能


SGI

SGI公司的 Kasenna MediaBase

1. Kasenna MediaBase概述
MediaBase是由SGI为了满足媒体服务的各个方面，包括流媒体传输服务，联网、内容和操作管理等而开发出来的，所有这些服务都可以从一个基于Web的控制台提供。MediaBase支持领先的流媒体标准，这些标准包括RealSystem G2、QuickTime 和更高位率的MPEG-1和MPEG-2。MediaBase利用SGI Origin 服务器的可扩展性和可靠性来提供功能丰富、经济有效的基于Web的企业媒体服务器，使用户能够向消费者或整个企业发送具有高度影响力的信息。

在2000年1月SGI公司将其成功的视频流服务器软件--SGI MediaBase分离出来成立了一家新公司Kasenna。 Kasenna MediaBase结合易扩展的Origin服务器硬件硬件允许你充分发挥流媒体传输的潜力,并彻底改造创建,传输和显示信息的方式.

2. MediaBase的主要特点：
智能化媒体管理

SGI MediaBase 可提供出色的媒体管理功能,它可以充分利用业界邻先的关系型数据库技术,诸如Oracle, Informix 等.对于管理,跟踪,控制大容量数据的存取来说,高效,使用方便的媒体管理工具至关重要.用不同压缩的媒体资源或具有不同速率的媒体资源可以利用同一个名字进行查阅.SGI StudioCentral 库可以对各种数字资产进行"登记",并把它们存入到MediaBase中,这对于大容量多媒体档案管理十分重要.SGI MediaBase 可以利用CD光盘(CD Jukebox)ak 磁带库(tape rlbots)作媒体播放.用户在浏览视频节目的同时,存储设备上的资源传输到MediaBase的文件系统上.用户的授权,认证,记账(AAA)应用程序接口可以与普通的统计报表,存取控制软件结合起来以保证安全地对内容进行存取.

2.1 灵活的媒体流回放选件
当今,SGI MediaBase在MPEG-1及MPEG-2媒体流传输解决方案中占优势,在世界范围内它可以提供应80000多个高质量的MPEG媒体流.通过Quick Time 及Real Media 支持H.263,H261.Sorenson, M-PEG,QUALCOMM Pure Voice及Q Design audio等比特率较低的格式.SGI Media Base可以每秒28kb至15Mb速率支持因特网各内联网的许多应用.SGI MediaBase 可以保证视频及音频数字资产的点播.播放器可以嵌入到Netscape Navigator或Microsoft Internet Explore Web浏览器中.可以利用HTML,Java,Visual Basic Scripting控制回放.SGI Media Base 通过webcasting作多点广播及模拟多点广播.

2.2 客户机和网络的互操作性
SGI Media Base 可以在各种客户端及多种网络拓扑结构环境中顺利地动作.它支持Apple Macintosh , Windows95/98/window NT及各种UNIX 客户机SGI Media支持Microsft Direct Show体系结构,可以与符合Direct Show框架的软硬件编者按码解码器实现即用的互操作。SGI Media Base可以根据可用的带宽智能化地自动选择适当的压缩格式，在当前所选择的界面下优化媒体流传输。除了支持在ATM（AAL5）网络上作媒体流传输外，SGI Media Base也支持LAN仿真及经典的IP网络播放视频媒体流。SGI Media Base提供经过扩展的RTSP以支持IP及非IP网络，允许装有TCP/IP协议的客户机（PC，机顶盒）与SGI Media Base服务器相连。

2.3 采集功能
如果与第三方编码解决方案结合，SGI MediaBase能从现场视频频摄像机，电视信号，有线电视的输入信号采集各种视频内容，并实时地在大量异机种客户构成的Web网络中实时播放。该服务器也可以存放所采集的内容以便在未来播放。

2.4 可靠的，可扩展的结构
为了使可用性达到最大限度，SGI Media Base 服务器还可以配置IRIS Fail Safe软件。IRIS Fail Safe在集群环境下运作，万一某台机器发生故障时该软件可以是应用程序从一台机器自动转移到另一台机器上运行。 SGI MediaBase 还支持用RAID技术来存储多媒体内容，也支持通过光纤通道高速访问数字资产。SGI Media Base 与线性扩展的Origin 服务器相结合，可以充分发挥媒体流传输的功能，并以崭新的方式创建，分发及显示视频媒体流传信息。

3.Kasenna MediaBase系统结构
Kasenna MediaBase是一个高度集成的媒体管理、媒体分发和媒体流播的平台，Kasenna MediaBase的组成部分包括：内容管理、内容分发和内容流，下面是集成进MediaBase 种中的各种功能的框图：

图 3-1 MediaBase系统功能框图

媒体管理
媒体管理功能包括以下几个部分：
4.1 元数据管理
元数据是指关于媒体文件的描述信息，如格式、位率、内容标题、帧率、版权、作者和内容描述，Kasenna MediaBase?提供了存储、管理及利用元数据的功能，它与Informix或Oracle数据库紧密集成来存储管理元数据。
4.2 内容管理
Kasenna MediaBase提供对多格式音频、视频数据文件的无缝安装、修改和删除，同时利用业界领先的数据库技术如Oracle、 Informix 等对大规模商业应用提供对存储数据的管理,跟踪,控制。
Kasenna MediaBase的管理功能可以通过网络用户界面访问。
4.3 内容获取管理
Kasenna MediaBase 提供与业界领先的编码技术无缝集成，支持实况的实时编码和捕获，并可以生成不同格式的文件(包括MPEG-1, MPEG-2, MP3, RealVideo, RealAudio, Quicktime等)运用到宽带网络上。
流
Kasenna MediaBase包括了多种及第三方视频服务引擎的流管理功能。
Kasenna自身的视频流引擎支持 MPEG-1, MPEG-2, MP3, and Quicktime媒体格式
第三方视频服务引擎包括Real G2 server, Burstware Server等
Kasenna MediaBase在支持的速率范围很广（8 Kbps - 15 Mbps），
支持以下流格式：MPEG-1, MPEG-2, MP3, RealVideo, RealAudio and QuickTime
可以服务于拨号用户和宽带xDSL 和线缆用户.

5.媒体分发(Media Distribution)
Kasenna MediaBase媒体分发的基础结构与网络上要求的扩展性、低反应时间的媒体服务分布式结构相吻合。其特点包括：
传输媒体数据及其相关元数据包括用户自定义属性的能力。
端到端或可靠组播复制。T
支持点播和预定传输。
通过GUI和CLI界面预定传输。
容易的批量传输模式。
Kasenna MediaBase支持的文件格式：
Kasenna MediaBase支持以下流格式：MPEG-1, MPEG-2, MP3, RealVideo, RealAudio 和 QuickTime。
支持的系统平台
服务器端平台：
硬件平台：SGI, SUN和 Intel/Linux
软件平台SGI Irix, Intel/ Linux和Sun Solaris.
网络和网络协议：IP, ATM (Native ATM, CLIP, LANE), FDDI and Ethernet (10Base-T to Gigabit).
客户端平台：
播放器：Windows Media Player、Real Player、 QuickTime player和Kasenna Broadband Player.
客户端平台：Windows 95, Windows 98, Windows NT, Windows 2000 和 Macintosh.


SMIL

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体-视频流
解决方案
产品
SMIL
在线媒体
SMIL - (Synchronized Multimedia Integration Language, pronounced "smile")
  • Jeff Rule's SMIL Demos
  • SMIL at INRIA Rhone-Alpes
  • Just SMIL - covers SMIL news, resources, design, and production. Explores streaming video, audio, and animation.
  • Synchronized Multimedia Integration Language 1.0 specification - W3C recommendation page.

Free SMIL Authoring Tools
  • GRiNS Editor (Mac, Win95/NT, SGI Irix 6, Sun) from CWI
  • MSlide Builder (Web-based)
  • Real EasyPix (Win95/98/NT) from RealSMILSoftware.com
  • RealProducer G2 Authoring Kit (Win95/98/NT) from RealNetworks
  • RealSlideshow (Win95/98/NT) from RealNetworks
  • SMIL Composer SuperTool (Win95/98/NT) from Sausage Software
Pay SMIL Authoring Tools
  • Allaire HomeSite (Win95/98/NT)
  • ActivePack (Wind95/98/NT & Mac) from Equinox Communications
  • G2 Objects for Dreamweaver (Win95/98/NT) from RealNetworks, Macromedia
  • G2 Object for Asymetrix Toolbook II (Win95/98/NT) from Asymetrix
  • L p Studio (Win95/98/NT) from The Productivity Works
  • L p Studio PRO (Win95/98/NT) from The Productivity Works
  • RealProducer Pro G2 (Win95/98/NT) from RealNetworks
  • SMIL Composer SuperTool (Win95/98/NT) from Sausage Software
  • T.A.G. Composer 2.0 for RealSystem G2 (Win95/98/NT) from Digital Renaissance
  • T.A.G. SMIL Editor 1.0 (Win95/98/NT) from T.A.G. Software (Digital Renaissance)
  • V-Active for RealSystem G2 (Win95/NT) from Veon
SMIL Utilities
  • HyperGen Image Mapping (Win95/98/NT) from ArsT Design
  • JPEGTRAN (courtesy of Ulead) - DOS - from Independent JPEG Group
  • RealPix Bandwidth Calculator (Microsoft Excel) from RealNetworks
  • RealSystem G2 Authoring Kit (Win95/98/NT) from RealNetworks
  • SMIL Evaluator (Web-based) from RealNetworks
  • SMIL Validator (Web-based) from CWI
SMIL Browsers & Players
  • Helio Java Player (Java based platforms) - free
  • GRiNS (Win95/98/NT, Mac 68k/PPC, Irix 6, Solaris 2.5) from CWI - free
  • RealPlayer G2 (Win95/98/NT, Mac PPC early preview version) from RealNetworks - free
  • RealPlayer G2 Plus from RealNetworks - pay
  • Crescendo Forte (plug-in for G2) (Win95/98/NT) from LiveUpdate - free
  • HPAS (Win95/98/NT) from Compaq - free
  • S2M2 Java Based SMIL Player (Java Based platforms) from NIST - free
  • SMILeBaby Java Based Player (Java Based platforms) from Rolande Kendal - free
  • Lp Player (Win95/98/NT) from The Productivity Works - pay
SMIL Encoders
  • RealProducer G2 Authoring Kit (Win95/98/NT) from RealNetworks - free
  • RealProducer G2 (Win95/98/NT) from RealNetworks - free
  • RealProducer Plus G2 (Win95/98/N, DEC Apha) from RealNetworks - pay
  • RealProducer Pro G2 (Win95/98/NT) from RealNetworks - pay
  • T.A.G. Batch Encoder 1.0 (Win95/98/NT) from T.A.G. Software (Digital Renaissance) - free
SMIL Servers
  • Basic Server Plus G2 from RealNetworks
  • Interaction Web Server Companion from Media Design in-Progress
  • Veon Activation Server from Veon


解决方案

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体-视频流
解决方案
产品
SMIL
在线媒体
当前，视频流传输市场现已孕育出较为成熟的复合式产品系列，市场中既有以软件驱动为主的产品；也有以计算机集群为主导，高性能高价位的解决方案，它能在全球范围内传送成千上万条高带宽信息，可与电视台播放的视频节目媲美。

区别于传统的视频收看形式,视频流一般指通过专用网或Internet/Intranet将视频从网络服务器传送到远距离的用户面前。宾馆、大众娱乐场所、有线闭路电视网、学校及教育培训中心,对多路实时的网络视频点播有规模化方面的需求;公司、企业和许多服务性行业则会更注重通过互联网传送产品和服务信息。各单位目的和期望值不同,选购和实施网络视频产品也有不同的侧重点,公司和企业应该根据自己的实际需求和市场上各种产品的类型,选择最适用的网络视频解决方案。 下面几个方面的问题是在选择视频方案是要着重考虑的问题：

  • 服务多少用户
  • 用户的期望
  • 需要的图像质量
  • 投资多少
  • 技术水平怎样

    其他还有如：带宽、费用、与其它系统的集成、播放器的流行程度。 最后还要强调的是,在视频流应用中,用户应花大量时间了解自己的技术细节要求,与产品供应商、系统集成商及现有用户进行多层次的交流,掌握实际情况。随着系统的复杂程度及价格的增长,供应商和集成商的服务支持能力也必须成为用户考虑的重要因素之一。

校园网视频解决方案

引言
校园网的建设随着教育产业的兴起和发展也逐渐呈现出蓬勃向上的态势。尤其是各级重点学校的网络硬件平台的建设，其水平和质量都非常之高，在世界范围内作横向比较也毫不逊色。但是，困惑也随之而来，具体表现为以下几个方面：
A、校园网投入大，但没有用在教育主业上。
B、网络仅用在办公自动化中，投资效益低。
C、无法实现充分共享。即享受好的教育资源的学生很有限；同样的课程需要年复一年的教授；同样的问题需要一次次重复回答；材质差异明显的学生按同一模式接受教育，做不到因材施教。
计算机网络技术在教育产业中的应用现状和由此产生的问题引起了教育界和计算机界对于计算机网络条件下教学模式的思考。教学模式在网络条件下最终会变化成什么样子？目前和将来一段时间内网络技术发展到底能导致产生哪些更富成效的教育手段，逐步推动教学模式的改变？ 随着多媒体技术的不断发展，特别是多媒体传输技术的突破，使网络多媒体教学得以实现。现在已经有许多的成熟的产品可以用来组建网络多媒体教学的解决方案。下面我们来讨论校园网视频系统的解决方案。
一 系统需求
1、通过校园网实现音、视频实况转播、视频预订，制作并存储节目。
2、在校园网上实现VOD教学。
3、广播领导讲话。
二 方案建议
根据用户的网络条件和要求,建议采用以下介绍的美国CISCO公司的IP/TV产品。IP/TV是全球最大的网络公司美国CISCO SYSTEM公司最新的网络视频点播/广播软件产品，具有强大的网络能力和高质量的视频和音频及目前最高的性能价格比。
通过该产品提供的实时广播，定时广播，视频点播三种通信模式，在现有校园网络基础之上，即可实现系统的需求。
三 系统选型
思科IP/TV方案是端到端完整的网络视频解决方案。它整合了高性能的视频服务器-Cisco IP/TV 3400系列服务器，IP/TV 3400系列服务器预先配置了强壮的IP/TV 3400服务器软件，而客户端桌面PC配置了IP/TV客户端软件。Cisco IP/TV解决方案支持三种视频传播模式:实时转播（live）,点播（on demand）,预定节目广播（scheduled）。可用于计算机网络上的电视会议，广播领导讲话，楼宇监控，网上培训教学，电视节目播放，现场实况转播，多媒体资料和动态视频节目检索、点播（VOD），发布信息等，使传统的计算机网络成为具有多种用途的多媒体网络。Cisco IP/TV解决方案提供丰富的软件功能，可以提供高质量的视频流和具有良好的可管理性、扩展性、带宽有效利用等特性。
Cisco IP/TV解决方案包含了Cisco AVVID（Architecture for Voice, Video and Integrated Data），即一个包含了音频、视频整合数据的通信框架。能满足企业通信、职工培训、远程教育、商业电视等需求。
采用RTP(实时传输协议)，RTCP(实时传输控制协议)，RSVP(资源预留协议)，MULTICAST(多播协议)，以软件为核心，在现有的计算机网络上，实现了视频节目的广播、点播等功能。
Cisco IP/TV方案利用了经济实惠的Windows 95, Windows 98, and Windows NT平台，并充分利用了微软的Windows Media技术（WMT）。同时它与苹果公司的QuickTime客户端，UNIX VIC and VAT Mbone tools,即Netscape插件结构兼容。
Cisco IP/TV方案可以在任何IP网络上工作，如10BaseT 、100BaseT Ethernet 或千兆位以太网上工作，也可以在电缆、ADSL调制解调器及局域网仿真的ATM网络上工作。对于视频播放，Cisco IP/TV StreamWatch软件可以收集观众的信息，如观众人数、身份、及观看节目时间，对点播节目，日记文件能记录观众正在收看的节目。这些工具能提供数据帮助你分析用户的需求类型

远程教育解决方案

引言
知识经济的时代需要人们不断的学习新的知识、技能，才能跟上时代的步伐。学习必须转变成一个伴随每个人一生的过程。网上教育突破了传统“面授”教学的局限，为求知者提供了时间分散、资源共享、地域广阔、交互式的教学新方式，因而广受人们观注。
无论您身处何方，无论在深夜或是严冬、无论您的基础好坏、无论您的进度快慢，您都可以获得同样好的教材和同样优秀的老师。这就是理想中的“全世界同一大课堂”的网上教学。但要真正实现这种理想仍需进行多方面的实验与尝试，形成一套稳定有效的教学方法，达到网上的教学资源的积累（题库、评测），才能为网上学生带来最大的学习效果。
传统的基于课本（文本资料）、少量的实验的方式的课堂式教学是线性的。这种方式本质上是把立体的、交叉的、综合的知识体系用一个线形的模型来描述、传递、感知，进而从新再在学习者中构重新建立体的、交叉的、综合的知识体系。这种知识的传递方式显而易见是低效率、不完善的。一种可能的方式应该是立体的、非线形的多种体验的，基于超连接、多媒体的教材。
中国政府确立了未来3年现代远程教育框架：以多媒体计算机技术为核心的教育技术在学校的普及和应用；校园网络的普及和应用，利用网上资源提高教学质量；开办现代远程教育，建设并提供大量的网络资源，不断满足社会日益增长的自身教育需求。 远程教育(Distance Education or Distance Learning)是任何一种师生分离的,不能面对面组织的教学。从远程教育的定义可以看出它有下列三方面的内涵:学生与教师的分离，学生与学生的分离，利用传播媒体和传输系统组织教学。
从技术上讲，远程教育系统是建立在现代传媒技术基础上的多媒体应用系统，它通过现代的通信网络将教师的图象、声音和电子教案传送给学生，也可以根据需要将学生的图象、声音回送给教师，从而模拟出学校教育的授课方式；同时还可以利用现有的网络条件建立虚拟的班级，加强学生之间的交流。
概括地说，远程教育的优势在于它突破了时空限制，增加了学习机会，有利于扩大教学规模、提高教学质量、降低教学成本。学习者可以在自己方便的时间，适合的地点，按照自己需要的速度和方式,运用更加丰富的教学资源来进行学习。因此，从发展的眼光看，远程教育会成为学校教育的补充和扩展，同时会促进学校的教育改革。
鉴于远程教育的深远意义，教育部制定了《面向21世纪教育振兴行动计划》，把现代远程教育工程作为重点工程之一，并提出了发展我国现代远程教育的16字指导方针：统筹规划，需求推动，扩大开放，提高质量。 一 系统需求
实现教学课件的点播（VOD），教学直播，网络课堂等等。
二 系统选型
Windows Media Service是Microsoft提出的流信息播放方案，其主要目的是在Internet和Intranet上实现包括音频、视频信息在内的多媒体流信息的传输。
在IP网上开展远程教学活动，需要解决两个基本问题：音频、视频流信息的传送以及它们与数据之间的同步。由于音频、视频信息的带宽比较宽，不可能让学生将所有的节目下载到本地计算机上后再播放，必须要采用先进网络播放技术来实现边发送边播放。此外，由于在教学过程中教师会经常使用电子教案来辅助教学，比如用PowerPoint，而电子教案的展示与音频、视频流之间有严格的时间同步关系，这就要求在传输过程中我们仍然要保持它们之间的同步关系。
基于Microsoft的Windows Media Service建立远程教育系统投入少，建设时间短，使用简单，易于维护。通过反复比较，我们最终选择了Microsoft的Windows Media Service来建立基于IP网的远程教育系统。

三 系统结构
Media Service是由一系列的工具构成，主要包括MediaTools,MediaServer和MediaPlayer三个部分组成。MediaTools提供一系列的流处理工具，它们完成流信息的生成，编辑等功能。MediaServer的主要功能是完成流信息的播放，MediaServer既支持流信息的点播功能，也支持流信息的组播功能。MediaPlayer是客户端的播放应用程序，它负责流信息的播放，目前MediaPlayer已经集成在IE5.0中，是标准插件。如果用户使用其它版本的浏览器则需要安装该播放器以接收并播放流信息。下面我们将通过WindowsMediaService在远程教育系统中的应用来介绍WindowMediaService的特点。
总体结构

图 远程教育系统结构

视频直播解决方案

一、业务需求

    随着Internet网络的普及，使网络上传输的资料不仅仅限于文字和图形。有许多的Internat的视频应用需要在Internet网络上直播；如现场直播、企业融资路演等等直播业务。它们都要求最大范围的让观众观看到高质量的节目，象电视直播一样达到宣传、广告或满足观众需求的目的。这就要求系统具备高传输速率、数据同步、数据流的分流、高稳定性等特性。实现网络的视、音频传输最好的解决方案就是流式媒体的传输方式。
本系统在完成提供电视节目的网络直播之后，也可以提供视频点播、音频点播、MTV播放、音乐会播放、音乐欣赏、多媒体广告发布等服务。

二、系统选型
RealSystem是在流式媒体方面最为成功的系统。RealSystem具有跨平台（支持NT/Windows2000，以及Solaris、Linux、AIX等多种平台），稳定性高，特别是对直播条件要求不高非常容易实现在Internet网上进行视频直播。其应用领域涉及教育、政府和娱乐等等。全球85%的网上直播系统采用RealSystem。与此同时，RealSystem在远程教育、电子商务以及网上媒体点播系统（VOD）方面同样出色。
RealSystem在最广的范围、最快的连接速度基础上提供了性能最好的多媒体效果--从企业网络到遥远的拨号用户，RealSystem有功能非常强大的RealAudio，并使其性能上升80%；新一代的RealVideo为其提供了在高比特率连接方式下的满屏显示，每秒可达30帧显示。
SMIL支持丰富多彩的媒体显示包括新的数据型RealPix,RealText,MPEG-1(DigitalBitcasting)及由Learnkey提供的Computer Screen Cams。
强有力的系统管理和可伸缩性能力。使用RealSystem，你可用Splitting，IPMulticating，向成千上万的桌面用户广播，通过跨平台网络，以WEB为基础的Realsystem管理方式,以Lariat软件集成的RealServerReports以及JavaPerformance监视器使系统管理变得非常之容易。使用WindowsNT与NTPerformance监视器的集成，NTEvent监视器，及NTAuthentication。并通过用户登录认证之后，登记并跟踪雇员的参与与进展情况。
RealSystem是一个开放的，标准型的，穿越平台的架构。RealSystem支持领先的工业标准，例如：RTSP（Real-time的主流协议）和SMIL（声音图像同步的多媒体结合语言）。RealSystem可在现在流行的15种任何操作系统上开展，包括Windows、Macintosh、Unix,SmartNetworking为标准IP协议。IP多点广播RTP .WDP .TCP/IP和HTTP提供支持。防火墙代理工具包让防火墙也非常容易的适应于RealsystemG2。RealsystemG2SDK提供了一个正被100多个应用工具和数据型发展的公司使用的可延展的架构。

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产品
SMIL
在线媒体
公司 产品
3cx
  • IXJET Streaming
  • IXJET Streaming
  • IXJET Explorer
  • IXJET Presenter

Accord
  • MGC-100多点会议控制器
Apple
  • Quicktime
Cisco
  • Cisco IP/TV
  • Cisco IP/VC Videoconferencing Series
  • Cisco Media Convergence Server
  • Cisco VN 5902 Video Networking System
  • Cisco VN 5900 Video Networking System
  • Cisco VN 2900 Video Networking System
Ezenia
  • Encounter3000网络服务器
  • Encounter Netgate网关
  • Encounter GateKeeper
  • Encounter eMCS
FVC
  • 视频门户技术CTM和软件编解码器V-Meeting
IBM
  • Hotmedia
  • VideoCharger
Inetcam
  • iVISTA
  • VideoWebPage
Ipresenter
  • iPresentation制作系统
  • iPresentation管理系统
  • iPresentation管理系统
Longcent
  • IP-VIDEO网络视频系统
Microsoft
  • WINDOWS MEDIA
CommerceWare
  • OpenVideo 版本 4.0

Optibase

MPEG MovieMaker

  • MPEG Composer
  • MPEG ComMotion
  • VIDEO PLEX
  • MPEG Carver
Oracle
  • Oracle Video Server
PictureTel
  • PictureTel会议电视系统
RadVision
  • OnLAN
  • viaIP
Real Networks
  • RealPlayer
  • RealProducer
  • RealPresenter
Redspider
  • RedSpider

Rhythem
  • Voice System
SGI
  • Kasenna MediaBase
Sun Microsystems
  • Sun StorEdge媒体中心视频服务器
Topskys
  • 视频服务器
  • 流式媒体播放器
  • 机顶盒
V2Tech
  • V2 Producer
  • V2 MediaServer和
  • V2 Player
VCon

VCON桌面系统

  • ESCORT 25 PRO桌面会议系统
  • CRUISER 75 PLUS桌面会议系统
  • CRUISER 150 桌面会议系统
  • CRUISER 384桌面会议系统

VCON会议室系统

  • Media Connect 6000系列
  • Media Connect 8000系列

ViGO Product Fact Sheet

Falcon IP
ViCall
  • ViCall
Videojet
  • VideoJet 多媒体视频编码器
Vtel
Webcam
  • WebCam


上海同天视讯公司

- 研究MPEG流式（Streaming)视频及DVB，提供视频点播（VOD）、直播（LIVE）、卡拉OK（KTV）、交互电视（ITV）、知识管理等宽带应用，提供流式媒体的ASP服务。

  • 产品介绍 VOD介绍
    视频服务器
    流式媒体播放器
    机顶盒


北京威速科技有限公司

http://www.v2tech.com/cn/,http://www.voicity.com.cn

流媒体解决方案

企业级应用

北京威速科技有限公司日前在京发布了基于MPEG-4的流媒体系统V2 MediaSystem 1.0版。V2 MediaSystem是一个基于MPEG-4的多媒体传输应用软件，包括

  • V2 Producer
  • V2 MediaServer和
  • V2 Player

三部分，真正实现了音视频在线点播、直播的一体化管理，能有效提供企业管理数字化资产的制作、发布和播放。该软件能够适应多种节目源及多种系统平台，且具有灵活的带宽适应能力。产品的成功运用可使企业降低成本、有效提高用户沟通服务能力。

个人应用

V2 MediaStudio
V2 MediaStudio是基于行业标准的多媒体传输软件，具有很强的扩展能力。

通讯解决方案

企业级应用

V2 CallCenter
V2 CallCenter是基于通用浏览器的在线支持/服务系统，为电子商务网站运营者实现实时互动的语音和文本交流功能，从而为在线用户提供更好的服务。

V2 Conference
V2 Conference网络会议系统应用先进的Internet技术将世界范围缩短在你的屏幕上。在世界各个角落，成员只要登陆V2 Conference System的网络会议系统，在公司的虚拟会议室中就可以直接召开会议，进行讨论。

个人应用

V2 Communicator
V2 Communicator是先进的点对点即时通讯工具。通过它，用户可以在网上进行实时的文本和语音交流、发送语音文件及传输文件。

V2 VoiceMail
V2 VoiceMail是一个语音邮件生成软件。利用它将语音信息和文本信息录制成邮件后，可以发送给任何有Email账号的人。由于生成的邮件可以是一个自播放文件，对方接收到eMail 后，不需要任何的其它软件或插件就可以收听语音信息。


VCON

VCON通信有限公司
http://www.vcon.com
VCON通信有限公司是基于ISDN和IP网络的视频会议系统的开发商，生产制造商、销售商，被视频会议行业誉为商业IP视频会议产品的世界领导者。公司提供基于ISDN，TCP/IP、ATM，卫星、XDSL和其它网络环境下的从桌面型、小型会议型到会议室型系统全系列视频会议解决案。VCON与世界范围内具有领导地位的一些高科技公司建立了战略性的联盟，为用户提供一流的音频、视频与数据协作整体网络多媒体解决方案。VCON通信有限公司总部在以色列，在美国（奥斯汀、芝加哥、纽约、圣约瑟、华盛顿）、德国、西班牙、英国设有分公司；日本、中国设有销售代表处。
VCON公司的任务
VCON公司一直认识到人们对于把视频、音频和数据集中到一个单一的企业范围内IP网络上的需要。因此，VCON的目标是领导市场从以基于电路交换的视频会议主要是ISDN（H.320）向基于IP（H.323）网络的商业/企业通信方向转变。为了达到这个目标，VCON不断寻求并扩展与网络和通信行业中的一流的生产商的伙伴关系，为市场提供完整的企业网络多媒体解决方案。
VCON的新技术
作为IP视频占有率第一的VCON公司通过开发其基于IP网络的第三代视频会议技术：交互式IP多点广播，VCON PacketAssistTM 体系，1.5Mbps数据速率，带宽自动调节，Internet Locator Sever(ILS)，非对称网络环境支持（xDSL），VCON后处理算法（VPP）等将网络视频会议系统推广到世界多媒体通讯市场。 1999年6月VCON在上海成立办事处，同年9 月上海长江新成计算机系统集成有限公司与VCON公司签约，成为其在中国地区的总代理，负责VCON公司全线产品在中国大陆的分销、渠道建立和市场拓展。为用户提供最高视频质量的、最多功能的、通信网络最灵活的和最具竞争力价格的多媒体视频应用解决方案，是上海长江新成计算机系统集成有限公司的宗旨。

VCON桌面系统

  • ESCORT 25 PRO桌面会议系统
  • CRUISER 75 PLUS桌面会议系统
  • CRUISER 150 桌面会议系统
  • CRUISER 384桌面会议系统

VCON会议室系统

  • Media Connect 6000系列
  • Media Connect 8000系列

ViGO Product Fact Sheet

Falcon IP

VCON视频会议系统简介

VCON的桌面视讯会议系统是真正的低成本将顶级质量的视频会议系统。只需要一个PC插槽， VCON单板解决方案下的桌面系统就可以为您提供全面符合H.323/H.320标准并通过MS NetMeeting全面实现T.120数据协作应用的桌面视频会议系统。 PCI总线的系统编解码器，结合先进的PC硬件，通过任何基于TCP/IP网络协议或者ISDN的线路， 即可实现“即插即用”的视频会议，而且本系统支持局域网络(LAN)和ATM网络上的视频会议。

全功能的桌面视讯会议系统

VCON Escort 25 Pro 视频会议系统( H.323 for LAN，64K-1.5M,30FPS)

配置: - 视讯会议系统软件MeetingPoint 4.01

- 模拟彩色摄像头和电缆

- 视音频频编码/解码卡(单插槽,PCI总线)

- 音频话筒手机

- 操作手册

- PTZ远端遥控变焦摄像头 ED31(可选)

VCON Cruiser75Plus视频会议系统

(H.323 for LAN,64K-1.5M,30FPS;H.320 for ISDN,128K,15-30FPS)

配置: - 视讯会议系统软件MeetingPoint 4.01

- 模拟彩色摄像头和电缆

- 内含ISDN接口的视音频频编码/解码卡(单插槽,PCI总线)

- 音频话筒手机

- 操作手册

VCON Cruiser 150 视频会议系统(包含MVIP接口)

( H.323 for LAN，64K-1.5M,30FPS;H.320 for ISDN,128K,15-30FPS)

配置: - 视讯会议系统软件MeetingPoint 4.01

- 模拟彩色摄像头和电缆

- 内含ISDN接口的视音频频编码/解码卡(单插槽,PCI总线)

- 音频话筒手机

- 操作手册

- 标准MVIP接口（连接V.35、E1、T1、ATM选件）

VCON Cruiser 384 视频会议系统(包含MVIP接口)

( H.323 for LAN，64K-1.5M,30FPS;H.320 for ISDN,386K,30FPS)

配置： - 视讯会议系统软件MeetingPoint 4.01

- 模拟彩色摄像头和电缆

- 内含三个ISDN接口的视音频频编码/解码卡(单插槽,PCI总线)

- 音频话筒手机

- 操作手册

- 标准MVIP接口（连接V.35、E1、T1、ATM选件）

数据会议

Vcon 桌面视讯会议系统集成了Microsoft NetMeeting；VCON桌面视频会议支持网络系统的动态带宽分配，更快，更有效地共享数据。

多点会议支持

通过相应的多点控制单元(MCU)，使用标准的H.323/H.320/T.120支持48个音频

/视频/数据会议，最多支持48点的音频／视频会议Microsoft NetMeeting支持多点数据会议功能.

高速Internet接入支持

支持与第三方多点服务的通讯.支持128K Internet接入(PPP或MPP)和远程LAN

的接入.

Vcon 桌面视讯会议系统性能：

  • 支持Windows 95/98/NT平台
  • 用先进的统一桌面视频会议软件，实现ISDN(H.320)和LAN(H.323)双工作模式。
  • 通过MS NetMeeting 全面支持T.120协议下的应用共享，文件传输，电子白板
  • 等数据协作。
  • 内含 MS NetMeeting 应用软件
  • 图像电话簿，图像抓取
  • 支持交互式多点广播（Interactive Multicast）
  • 内置回声消除器（AEC）
  • 完全符合H.323 视频会议标准
  • 完全符合H.320 视频会议标准（Escort25 Pro除外）
  • 本地窗口
  • 可移动画中画（PIP）
  • 可调节视频窗口大小直至全屏
  • 多声源选择
  • 支持H.323 MCU
  • 支持H.320 MCU （Escort25 Pro除外）
  • 支持双模拟摄像机（PAL/NTSC）
  • 支持远端PTZ摄像机控制
  • ILS支持

Vcon 桌面视讯会议系统技术规格：

视频会议：

视频压缩：符合H．261(P×64)；H．263可软件升级

LAN传输分辨率： CIF(352×288像素)可达30帧／秒

QCIF(176×144像素)可达30帧／秒

VGA分辨率： 所有VGA分辨率为15／16／32彩色

视频输人： Philips NTSC或PAL从模拟摄像机； RCA接口第二视频输入

特殊功能： 可任意缩放视频窗口的大小，画中画，静止图像

音频会议:

音频压缩： G.711-3.4KHz，56kbps和48kbps

G．722-7KHz，56kps和48kbps

G．728-3．4KHz，16kbps

音频输人／输出： 配置电话听筒

线水平输出，接多媒体扬声器

线水平输出，接声霸卡

可选件： 电话耳机

电话头戴耳机

全双工免提系统

内置回声消除器(AEC)—30db ERLE@＞200ms

自动增益控制： —95Db至十95Db

软件控制功能： 音量控制和静音

数据会议:

支持T．120

LAN速率下的LAN数据速率

内置Microsoft NetMeeting

．连接:

8芯Mini—DIN视频、音频和电源接口，连接Philips NTSC／PAL从摄像机

RCA复合端子音频、视频接口连接第二模拟摄像机或VCR

RJ22接口，连接电话听筒或耳机

3.5mm微型插头，连接多媒体扬声器

通信和协议:

●LAN: 兼容H．323 (要求MS TCP／IP )

支持视频速率56kbps到768kbps，1.5Mbps

●ISDN: 兼容H．320

支持视频速率128kbps: C75 PLUS、C150

384kbps :C384

●H.323—H.320网关支持

BADVision网关

VideoServer网关

First Virtual Corp．网关

Madge网关

系统最低配置:

  • Intel Pentium 133微机处理
  • 32M RAM for Microsoft Windows95 or 98
  • 64M RAM for Microsoft Windows NT
  • 80M可用硬盘空问
  • 一个可用的PCI插槽
  • CD-ROM驱动器
  • 15/16/32位色或更高的VGA和SVGA,支持DirectDRAW
  • Microsoft Windows95/98/NT
  • 用于LAN／WAN需要有网卡、 TCP／IP

远端可遥控摄像头ED31

ED31是一台视频会议本地0和远端都可以控制的可摇移/俯仰/变倍的高清晰度摄像机。

. 传 感 器： 1/3英寸 AFCCD

. 图 像： PAL制，752x585

. 摄像机位置预制： 最多6个位置 摇移/俯仰/变倍

. 变 焦： 12倍 5.4mm~64mm

. 控 制: 变倍,调焦,光圈

. 控制接口： RS 232-VISCA

. 遥控方式: 视讯会议本地/远端/本地红外遥控器

视频会议系统结构

系统实现方式

1．系统采用交互式多点广播的方式，实现方式如下：

具体的会议方式是在一个会议中先确定一个会议主席，会议刚开始的时候主席是自然的发言者，所有与会者接收到的图像、声音信号均来自于主席；在会议的进行中任何一个与会者均可以向主席提出发言申请，主席同意后则所有的与会者将自动切换接收来自于该发言者的图像声音信号，主席在会议中拥有最高控制权，可以任意切换发言人及会议的进程。整个过程均由会议主席控制。

该方案由于使用了数据流技术，所以无论有多少人参加会议，也只占用一路音视频信号的带宽（128K~1536K），不占用过多的网络带宽，尤其适应于有远程连接而带宽有限的网络环境。另外, 该技术是VCON公司和CISCO公司合作的结果, 所以普通PC终端安装了CISCO公司的IP-TV客户软件后也可以接受并软件解压VCON系统发出的音视频信号，从而以纯接收者的身份加入视频会议（不能发言）。这样可以有更多的人进行“旁听”。

如此搭建的系统，可以充分利用通信的前端科技，实现会场间交互式的会议，几乎等同于现场会议的实时效果。因此整个方案是一个投资不多但很实用很有生命力的一个解决方案。

主会场加配SONY EDI31摄像头，可以实现遥控器和软件控制摄像头的摇移、俯仰、变倍，并支持远端用户控制（H.281）。

2．系统采用多点会议方式，实现方式如下：

系统通过增加多点控制单元（MCU）来实现多点会议的目的，多点控制单元包括硬件方式及软件方式两种，软件方式相对比较便宜。

软件方式：CyberMeeting PictureTel ....

硬件方式：Radvision ,VideoServer.....

支持10/100BaseT Ethernet以太网、广域网口。

支持SNMP网管协议

支持会议预约

支持会议计费信息

支持会议管理切换

8．MCU可以级联，不同的MCU端口用户之间切换效果和同一个MCU是一样的

Multicast实现功能是由软件来完成，它可以切换主画面，也可以将主席的控制权在主席允许下移交到其他的点。

。MULTICAST多点广播与基于MCU的主要区别:

MULTICAST的优势:

1、无须增加昂贵的MCU多点控制单元。

2、加入会议点数不受限制，这是MCU做不到的。

2、可节省广域网带宽，不论对端有多少点接收图像，对于广域网来讲，只把对

方看成一点，而MCU则是星形结构，广域网带宽等于每点带宽乘以所有点数。

3、支持64K-1.5MBPS速率广播图像，用户数量不受限制。

4、支持主席控制，电子白板，应用程序共享，元件传输等功能。

MCU的优势:

1、MULTICAST只能做单向的广播，而MCU在广播视频的同时，还可以收到底下一点的图像，做到广播的同时可以交互。

2、MCU有混音，MULTICAST没有，只能广播一路声音。

5.3 方案说明

该方案的基础是架构在一个完善、高性能的TCP/IP网络之上的,干线连接具体的底层物理网络采用邮电的ATM宽带网, 或是广电的光纤网均可以。对于网络的要求，一是要提供足够的带宽（一般要保证点对点连接在2M以上），二是要尽量减少网络时延。因此，网络架构应尽量采用交换式设备或ATM技术以满足要求，达到较好的实际效果。由于基础网络建设部分部属于本建议范畴，故在此不作深入讨论。

系统包括X个用户终端。每个点配置一套VCON Escort25视频会议终端。通过系统的10/100M以太网络接口接入网络。

X台视频终端，任意两台之间可以通过网上拨号建立视频连接，视频码流速率从64K到1.5M可调，在384K的情况下可以达到FCIF 30帧/秒的图像效果，且编解码时延不大于300ms（不考虑网络时延），虽比不上广播级图像质量，但完全可以满足一般会议之用。为了达到理想的图像效果，演播室内应按要求配置灯光、音响设备及环境布置（详见下节），而远程教室则应配置高亮度投影等高性能显示设备和功放音箱等扩音设备。通过系统内置的NetMeeting软件，可以在远程教学过程中实现文件传输电子白板及应用共享等功能，使得会议过程更为高效 。

另外，VCON的多点广播功能也非常适合会议所用。该功能可以替代昂贵的硬件MCU设备实现H.323终端之间的多点会议，其核心技术采用VCON公司独有的交互式多点组播技术（Interactive IP Multicast）来实现。该技术是基于先进的视频流（Video Stream）思想，结合CISCO公司的多点组播技术来实现的。

具体的会议方式是在一个会议中先确定一个会议主席，会议刚开始的时候主席是自然的发言者，所有与会者接收到的图像、声音信号均来自于主席；在会议的进行中任何一个与会者均可以向主席提出发言申请，主席同意后则所有的与会者将自动切换接收来自于该发言者的图像声音信号，主席在会议中拥有最高控制权，可以任意切换发言人及会议的进程。整个过程均由会议主席控制。

该方案由于使用了数据流技术，所以无论有多少人参加会议，也只占用一路音视频信号的带宽（128K~1536K），不占用过多的网络带宽，尤其适应于有远程连接而带宽有限的网络环境。另外, 该技术是VCON公司和CISCO公司合作的结果, 所以普通PC终端安装了CISCO公司的IP-TV客户软件后也可以接受并软件解压VCON系统发出的音视频信号，从而以纯接收者的身份加入视频会议（不能发言）。这样可以有更多的人进行“旁听”。

如此搭建的系统，可以充分利用通信的前端科技，实现会场间交互式的教学活动，几乎等同于现场教学的实时效果。因此整个方案是一个投资不多但很实用很有生命力的一个解决方案。


VideoJet
VideoJet 多媒体视频编码器

VideoJet基于现有的计算机网络传递实时视频。根据ITU-T H.261标准，有效压缩，确保在TCP/IP协议下通过局域网，广域网的视频通信。所有安装只需配置一个IP地址和连接以太网与VideoJet的接口。

VideoJet可以做发送器和接收器。发送器将把任意PAL/NTSC视频源连接到计算机网络上。相反，接收器将把视频图象显示到任意标准的PAL/NTSC监视器上。另外，还可以通过任意PC机上的PROVI软件解码器接收视频信号。

特 性

．VideoJet为远程监控和保安提供一套先进的特性：当现场的运动被探测到，集成的运动视频传感器将建立一个自治的连接。报警前的记录被储存到一个视频铃缓冲器上以便报警。远程控制的外围设备可以用R S232系列界面，例如，pan/tilt/zoom摄像机。音频界面允许全双音频传输。

应 用

．CCTV系统使用现有的网络
．安全和访问控制
．楼宇和房间的视频监控
．机械的远程维护
．设备管理和安全问题
．基于IP的多媒体应用 优 势

通过计算机网络传输实时视频、音频和数据（以太网，TCP/IP）

使用现有的计算机网络进行远程监控，不需视频电缆

便携式自治系统，不需PC机

适合各处，例如：电缆管或摄像机架

高质量，全动态，彩色实时视频；分辨率达704x576，像素达30帻/秒（最大）；符合ITU-T H.261标准

过硬的实时质量：ITU-T H.261标准为pan/tilt/zoom 控制提供高压缩率和低延迟

容易操作，集成了Web服务器

用您喜爱的Web浏览器接收MJPEG视频与系统集成

单一软件接收器PROVI应用软件或 PROVILook应用软件

将PC机转变成接收器或监视站，软件解决方案，用于任何PC机

透明的全双工RS-232数据通道

遥控连接的设备，摄像机连接典型的Pan/tilt/zoom控制

控制外部传感器输入，继电器输出


VTEL

世界领先的企业网络视讯方案、产品与服务供应商VTEL 美国视讯公司（NASDAQ：VTEL）日前进一步明确了公司最新发展方向，并通过其新近成立的独立业务实体就其视讯产品业务作出了长期承诺。

“VTEL将保持其在业界顶级视讯终端产品开发的领先地位的承诺为其整个产品业务实体注入的新的活力。”VTEL 产品业务实体总经理Bob Swem 说，“这标志着VTEL 产品业务发展的一个新的里程碑。”

Swem补充道：VTEL 银河系列会议电视产品，将继续作为该公司的旗舰产品系列。VTEL工程技术队伍将致力于不断完善银河系列产品的各方面性能，并继续对下一代视讯终端产品的研发工作。公司还将继续销售与支持其ESA企业系列会议电视产品，并与其已经并入新成立的VTEL解决方案业务实体的服务部门一道，为已经安装的系统提供完善的售后服务。

VTEL产品业务实体的主要办公机构位于奥斯汀北部Waterford。该实体全面负责VTEL基于PC平台的系列视讯产品的研发、制造、市场与销售，并将集成VTEL合作伙伴，如Accord 、RADVision、 Ezenia! 等公司网络产品。该实体将通过加强VTEL世界级的电信渠道合作伙伴及其增值分销体系开展其市场销售活动。目前公司超过90%的营业额来自这一体系。

“Bob Swem先生及其经验丰富的产品研发生产队伍在对我们的客户给予充足的投资保护的同时，将专注于产品业务的发展。他们将能更快、更好地满足市场及我们现有的客户对基于PC平台、并具备协作性结构的视讯产品的需求。” VTEL总裁兼首席执行官Stephen Von Romp 说。

VTEL的产品业务重点在于其具有绝对优势的中、小学教育及联邦与州政府应用市场的营销工作上。VTEL于2000年6月开始运营的独资中国子公司也将隶属于该产品业务实体。“作为中国领先的视讯公司，VTEL对中国不断增长的、极具吸引力的发展机会充满信心。”Swem先生说。立的VTEL解决方案业务实体的服务部门一道，为已经安装的系统提供完善的售后服务。

VTEL产品业务实体的主要办公机构位于奥斯汀北部Waterford。该实体全面负责VTEL基于PC平台的系列视讯产品的研发、制造、市场与销售，并将集成VTEL合作伙伴，如Accord 、RADVision、 Ezenia! 等公司网络产品。该实体将通过加强VTEL世界级的电信渠道合作伙伴及其增值分销体系开展其市场销售活动。目前公司超过90%的营业额来自这一体系。

“Bob Swem先生及其经验丰富的产品研发生产队伍在对我们的客户给予充足的投资保护的同时，将专注于产品业务的发展。他们将能更快、更好地满足市场及我们现有的客户对基于PC平台、并具备协作性结构的视讯产品的需求。” VTEL总裁兼首席执行官Stephen Von Romp 说。

VTEL的产品业务重点在于其具有绝对优势的中、小学教育及联邦与州政府应用市场的营销工作上。VTEL于2000年6月开始运营的独资中国子公司也将隶属于该产品业务实体。“作为中国领先的视讯公司，VTEL对中国不断增长的、极具吸引力的发展机会充满信心。”Swem先生说。


3DML Tutorial
WELCOME: THE LOW DOWN ON 3DML
3DML is a simple markup language very similar to HTML, the language used to build pages on the Web. 3DML creates, or "describes" Internet-ready, 3-dimensional rich media environments called SPOTs. Much of the syntax will be familiar to you, if you already know basic HTML.

[Psst: The information in this tutorial is current for v2.0 of the Flatland Rover. This tutorial is also available in an offline version. With the offline tutorial, you can proceed through learning 3DML at your own pace, without needing to be online. Simply download the OFFLINE TUTORIAL FOR WINDOWS (3.2 MB) or the OFFLINE TUTORIAL FOR MAC, (4.2 MB), and use your web browser to view the tutorial offline at your convenience.]

3DML is unique because it allows you to build a 3D space on the Web without doing any 3D modeling. And you can integrate many kinds of media right into this 3D spot, including video, sound, animation, 2D graphics, and text. Building a 3DML space for the web is actually very similar to building in the real world using familiar pieces such as simple wooden blocks or even 2" x 4"s from the local lumberyard. In 3DML, there is a set of blocks which you put together to build a house, or a waterfall, or anything you desire. In the basic 3DML block set, there are blocks which are the shape ramps, columns, signs and more. The village 3DML block set has blocks shaped like trees, houses, and sidewalks. Each of these blocks is represented by a character on your keyboard.

Like an HTML file, a 3DML file has 2 major sections: the <HEAD> and the <BODY>.

The <HEAD> is the section where you set parameters that are true for the entire SPOT, such as the map dimensions, ambient light and sound, the sky texture, etc.

The <BODY> is the section where you can customize your Blocks, and where you create your actual map. The map is the heart of a 3DML file, where you use different kinds of Blocks (represented by ASCII characters) to build a 3D space. Each block occupies a space of 256 x 256 x 256 (pixels). Blocks are arranged into a grid pattern to create each horizontal level of a SPOT. Levels are stacked on top of each other to create multi-story SPOTs.

This tutorial will take you step by step through the process of creating a 3DML spot. Check the 3DML Reference Guide for a complete list of 3DML tags. The Block Reference Guides have a complete list of the blocks in each blockset, with their default symbols and part names.

Before you begin the tutorial, there are 2 things you will need to do:

Download and install the Flatland Rover software
Download and install the tutorial files.
If you haven't downloaded your free Flatland Rover software, download Rover now!

There are also a few files you will need in order to follow along with the tutorial. You can get the tutorial files here. This download will unzip to a folder called Flatland Tutorial. Save your 3DML files that you create during the tutorial in this folder.

3DML GOES MULTILINGUAL
3DML Tutorials are now available in many languages!
new! Italian http://spots.flatland.com/pietro/tutorial/
Portuguese http://www.internight.net
German http://www.digitaldream.de/3dml/
German http://www.3dmlzone.de
French http://www.global-dev.com/ress_dev/3dml.htm
Spanish http://www.dromosfera.com.br/globsetutesp.html
Russian http://snake.2sun.ru/3d/3dml/

3DML Reference Guide
This reference guide provides the details of the syntax for each of the 3DML tags. A thorough description of the blocks available can be found in the Blockset Guides. These guides are designed to be used in conjunction with the 3DML Tutorial, which gives step by step instructions on how to build a SPOT. It is advisable to complete the tutorial first.

3DML is a mark up language that describes 3 dimensional spaces (called SPOTs) that are viewable with the Flatland Rover. Wherever possible, 3DML syntax is identical to or as similar to HTML syntax as possible. In some cases, however, we chose to make things a little different from HTML in order to retain XML compliance.

This guide is current for Rover v2.0

The code samples provided here are given in an extended form with line breaks between tag properties to make them easy to read. Please note, however, that in 3DML you can write tags either way, as long, one line tags, or with line breaks as we've done here.

General Rules About 3DML Tags

One line tags follow this basic syntax:
<TAG ATTRIBUTE="value" />

Tags that bound other groups of tags follow this basic syntax:
<TAG1 ATTRIBUTE="value">
<TAG2 ATTRIBUTE="value" />
</TAG1>

The tags that can bound other tags are:
<SPOT>, <HEAD>, <BODY>, <CREATE> <ACTION>, <IMAGEMAP>

All tags must be bounded by <>.

Tags and attributes are not case sensitive, but your files will be easier to read if you capitalize them.

All values, meaning anything immediately following an equals sign(=) must be surrounded by quotes(").

Any value that describes an x,y or x,y,z coordinate must be bounded by parentheses( ).

R,G,B color values also must be surrounded by parentheses( ).

To include comments in a 3DML file, use the following syntax:
<!--your comments here-->
Any information bounded in this way will be ignored by Rover.

--------------------------------------------------------------------------------

Basic structure of a .3DML file:
<SPOT VERSION="current_version_number">...</SPOT>
The first and last tags in a 3DML file. Everything between these tags is considered to be a spot described in the .3DML format. The VERSION parameter specifies the oldest version of Rover the spot was designed for.

<HEAD>...</HEAD>
These tags define a block of information which appears before the body section. The header acts as it does in HTML, containing information that applies to the entire SPOT.

<BODY>...</BODY>
These tags surround the body content of the spot description, including the map itself.

--------------------------------------------------------------------------------

Tags that can appear in the <HEAD> of a 3DML file
<DEBUG/>
Used when building a 3DML file. If the DEBUG tag is present, Rover will display error messages that will help the author find and correct errors in their 3DML file. It is recommended that the DEBUG tag be removed before publishing your 3DML file to the Web.

<TITLE NAME="name" />
The text in the <TITLE> tag is the name of the world, and will be displayed in at the bottom of the browser window.

<BLOCKSET HREF="url"/>
Specifies which set of 3D blocks (i.e. textures, sounds, models and behaviors) to use to display this spot in the browser.

<MAP DIMENSIONS="(columns,rows,levels)" STYLE="single|double"/>
DIMENSIONS specifies the size of the 3D map described in this 3DML file in units of blocks (every block is the same size; imagine them as wooden cubes placed side by side and also stacked to create levels). STYLE determines whether single or double character symbols will be used to represent blocks in the map and in CREATE tags.

<SKY TEXTURE="folder/image.gif -or- URL" COLOR="(red,green,blue)" BRIGHTNESS="brightness%"/>
Uses the given image file (GIF or JPEG) as the tiled texture for the sky above the world. Alternately, a color can be specified to appear in the SKY, instead of a texture. The brightness parameter sets the light on the sky image between 0 and 100 percent (default is 100%).

<GROUND TEXTURE="folder/image.gif -or- URL" COLOR="(red,green,blue)" />
If supplied, the browser uses the given image (or color) as the ground plane directly underneath the first level of the map. An author can then build a map without having to supply a solid floor. To use the default ground texture, include an "empty" ground tag: <GROUND />

<AMBIENT_LIGHT BRIGHTNESS="brightness%" COLOR="(red,green,blue)"/>
Set the ambient light level and color for the entire spot. Default is 100% brightness, and white light. Colored light will only be visible when Rover is running on 3D acceleration hardware.

<ORB TEXTURE="folder/image.gif -or- URL" POSITION="(turn, tilt)" BRIGHTNESS="brightness%" COLOR="(red,green,blue)" HREF="url" TARGET="target frame" TEXT="text"/>
Sets an image to be displayed in the sky such as a sun or moon. Also defines a source position for a directional light that shines from the ORB over the entire spot, and the brightness and color of that light. COLOR will only be seen on 3D acceleration hardware. HREF defines a link to a url and TEXT defines what text will be displayed on mouse rollover.

<AMBIENT_SOUND FILE="folder/sound.wav -or- URL" VOLUME="volume%" PLAYBACK="looped|random|once" DELAY="minimum..maximum" />
Uses the given WAV file as the ambient sound of the entire spot. The volume of the sound can be between 0 and 100 percent (default is 100%). The sound can either be played once, looped, or played at random intervals. If PLAYBACK="random", you can specify a range of times in between playbacks. Delay times are measured in seconds, and from the beginning of the sound, rather than the end.

<PLACEHOLDER TEXTURE="folder/image.gif -or- URL"/>
Uses the specified texture in place of any custom textures while the custom textures download.

<STREAM NAME="stream_name" WMP="url-for-WMP-stream" RP="url-for-RP-stream"/>
Specifies a streaming media file to use for both Windows Media Player and for RealPlayer.

<ONLOAD HREF="url" TARGET="target_name"/>
Launches the specified URL as soon as the spot is loaded. This is useful for displaying information in another frame or window along with your spot.

--------------------------------------------------------------------------------

Tags that can appear in the <BODY> of a 3DML file

<CREATE SYMBOL="symbol" BLOCK="symbol-or-block-name"> </CREATE>
Every 3D block object is assigned a single printable ASCII character as a symbol. For instance, a FULL block is assigned to the "#" character. So when you make a wall on the map you might type ##### which is a wall that is five blocks wide. Double-character symbols may also be used, if STYLE="double" in the MAP tag. When using double-character symbols, each default single-character symbol is preceeded by a "." So the default double-character symbol for a FULL block is ".#"

Every block is 256 pixels cubed. The <CREATE> tag allows you to change the textures applied to a block object and change some other features of the block, such as the orientation, the lighting (brightness, radius, and color) or the sound (wave file, volume, radius and playback mode).

Below is an example of a <CREATE> tag with all of the possible attributes:

<CREATE SYMBOL="symbol" BLOCK="symbol-or-block-name">
<PARAM ORIENT="up|down|north|south|east|west,0|90|180|270" SOLID="yes|no"/>
<PART NAME="name" TEXTURE="folder/image.gif-or-URL"
ANGLE="0-359"
COLOR="(red,green,blue)"
TRANSLUCENCY="number%"
STYLE="tiled|scaled|stretched"
PROJECTION="top|bottom|north|south|east|west"
FACES="0|1|2"
SOLID="yes|no"
STREAM="stream_name"
RECT="x1,y1,x2,y2"/>
</CREATE>

The <CREATE> tag can also include any or all of the the following tags: <ENTRANCE>, <EXIT>, <POPUP>, <POINT_LIGHT>, <SPOT_LIGHT>, <SOUND>, <ACTION>. When used inside the <CREATE> tag, these tags use the same syntax that they use on their own, except that they don't take a LOCATION attribute when used in the <CREATE> tag.

<LOAD TEXTURE="folder/image.gif"/>
<LOAD SOUND="folder/sound.wav"/>
Forces Rover to load the specified file. Normally, Rover will load textures and sounds in the order in which they appear in the 3DML file. Using the LOAD tag, you can force Rover to load images or sounds in a different order.

<LEVEL NUMBER="number" >...rows of building block symbols...</LEVEL>
Defines the two dimensional map for one floor level of a spot. Between the tags, all letters are interpreted as building blocks for rendering the spot. The map must be written as a rectangle of characters with all rows equal in length. There is a one to one correspondence between the symbol positions in the map and the placement of the 3D blocks in the resulting spot. The NUMBER attribute is optional. It is expected in general that each consecutive LEVEL defines a higher floor level of the spot.

<ENTRANCE LOCATION="(column,row,level)" NAME="name" ANGLE="0 - 359,-90 - 90"/>
Defines a location where players can hyperlink into this SPOT from another SPOT or Web page. More than one of these can be defined in a single SPOT description. There must be at least one ENTRANCE named "default" in every 3DML file. ANGLE defines what direction the viewer will be facing when she enters through this entrance (0 - 359 degrees with 0 equal to north, and -90 - 90 degrees to determine whether she is looking up or down.) The <ENTRANCE> tag can be placed anywhere within the BODY. It is usually placed at the end of the BODY, after all of the LEVELs have been defined. Some authors prefer to put them immediatley following the LEVEL in which they occur. An ENTRANCE can also be assigned to a block by placing it inside the <CREATE> tag. It does not take a LOCATION attribute if it is placed in the <CREATE> tag.

<EXIT LOCATION="(column,row,level)" HREF="folder/spot.3dml#entrance-name" TRIGGER="click on,step on" TEXT="text" TARGET="destination name"/>
A hyperlink to another .3DML file. LOCATION defines where in the spot the link will be placed. The HREF gives the filename or URL of the destination spot or html page, with an optional entrance name (if omitted the "default" entrance will be used). The TRIGGER attribute defines how the link can be activated, either by clicking on it, stepping on it, or both. The TEXT attribute defines the text that will be displayed when the mouse rolls over the link. TARGET names the frame or window in which the link will open, just as it does in HTML. The default value is "self". Like the <ENTRANCE> tag, the <EXIT> tag can also be assigned to a block by including it in the <CREATE> tag, or it can be placed in the body on its own, usually at the end of the BODY or immediately following the LEVEL in which it occurs.

<ACTION LOCATION="(column,row,level)" TRIGGER="roll on|roll off|click on|step in|step out|proximity|timer|location" RADIUS="number-of-blocks" DELAY="min..max"/>
<REPLACE SOURCE="symbol|(column,row,level)" TARGET="(column,row,level)"/>
</ACTION>
Defines an ACTION which takes place as a response to a particular TRIGGER. REPLACE is the only action that is currently available. RADIUS is used only for TRIGGER="step in" or "step out". DELAY is only used for TRIGGER="timer". DELAY is measured in seconds. If only one DELAY value is specified, the DELAY time will remain consistent. If DELAY is expressed as a range from minimum to maximum times, the DELAY will be random within those parameters. REPLACE defines a block to be replaced by another. TARGET defines the location of the block that will be replaced. SOURCE specifies the block that will take the place of the specified TARGET. If no TARGET is specified, then the SOURCE will replace the block which holds the ACTION tag. ACTION tags can stand alone in the BODY of the 3DML file, or they can be attached to blocks inside the CREATE tag. ACTION can also be used in an IMAGEMAP with the additional attributes of SHAPE="rect|circle" and COORDS="x1,y1,x2,y2|x,y,radius".

<POPUP />
POPUPS are 2D images that get displayed on the screen when the user travels within the radius of the location defined - this 2D image can be a texture (animated or still) or a color. The position and size of the popup image on the screen can be specified. Text can also appear on a popup, with a given alignment and color. When text is placed over a TEXTURE, the COLOR attribute will define the color of a drop-shadow to make the text more legible. Finally, the brightness of the entire popup can be specified. POPUPs can be assigned to a location in the map in the BODY section, or they can be assigned to a specific block in the <CREATE> tag. If used in the <CREATE> tag, the LOCATION attribute is not needed. If used in the BODY, and no LOCATION parameter is defined, then the POPUP will display throughout the entire spot.

Following is an example of a POPUP tag with all possible attributes:

<POPUP LOCATION="(column,row,level)"
TRIGGER="rollover,proximity|everywhere"
RADIUS="number-of-blocks"
TEXTURE="folder/image.gif -or- URL"
COLOR="(red,green,blue)"
PLACEMENT="mouse|top-left|top|top-right|left|center|right|bottom-left|bottom|bottom-right"
SIZE="(width, height)"
TEXT="message"
TEXTALIGN="top-left|top|top-right|left|center|right|bottom-left|bottom|bottom-right"
TEXTCOLOR="(red,green,blue)"
IMAGEMAP="map name"
BRIGHTNESS="brightness%" />

ImageMaps
<IMAGEMAP NAME="imagemap name">
<AREA SHAPE="rect|circle"
COORDS="x1,y1,x2,y2 | x,y,radius"
HREF="destination URL"
TARGET="destination target"/>
<AREA ......./>
<ACTION SHAPE="rect|circle"
COORDS="x1,y1,x2,y2 | x,y,radius"
TRIGGER="roll on|roll off|click on|step in|step out|timer"
</ACTION>
</IMAGEMAP>
Defines an imagemap. Imagemaps are images that have areas that contain links to other 3DML spots or HTML pages. Imagemaps can be used in POPUPs only. When creating a rectangular area of an imagemap, the coordinates x1,y1 refer to the top left corner of the rectangle, and x2y2 refer to the bottom right corner. When creating a circular area of an imagemap, x,y refers to the center of the circle.

<SOUND FILE="folder/sound.wav-or-url"
LOCATION="(column,row,level)"
VOLUME="number%"
PLAYBACK="looped|random|once|single"
DELAY="minimum..maximum"
RADIUS = "#_of_blocks"
FLOOD="yes|no"
ROLLOFF="1.0"/>
Specifies a sound file that will play in the spot. LOCATION refers to the placement of the sound in the map. The sound can either be played once, once every time the player enters the specified RADIUS (single), looped continuously, or played at random intervals with the PLAYBACK attribute. If PLAYBACK="random", you can also specify a range of DELAY times between playbacks. DELAY times are measured in seconds, and are measured from the time that the sound begins, rather than when it ends. FLOOD="yes" will cause the sound to fill the specified RADIUS at the specified VOLUME. RADIUS should only be used if FLOOD="yes" or PLAYBACK="single" or "once". ROLLOFF determines how quickly the sound will taper off as you move away from the source. Sounds can also be assigned to specific blocks within the <CREATE> tag. If used in the <CREATE> tag, the LOCATION attribute is not necessary. Default values are as follows: VOLUME="100%" PLAYBACK="looped" DELAY="5..10" RADIUS="1" FLOOD="no" ROLLOFF="1.0"

<POINT_LIGHT STYLE="static"
LOCATION="(column,row,level)"
POSITION="(x, y, z)"
BRIGHTNESS="n%"
RADIUS = "#_of_blocks"
FLOOD="yes|no"
COLOR="(red,green,blue)"/>
Defines a static light at a specific location in the map that shines in all directions. LOCATION refers to the placement of the light in the map. POSITION refers to the position of the light within the 256-pixel blockspace. FLOOD="yes" will cause the light to fill the radius at the specified brightness. FLOOD="no" will create a light that is the specified brightness at the center, and gradually drops off to the AMBIENT_LIGHT level at the far end of the radius. The default value is FLOOD="no". COLORed light will only be visible on 3D acceleration hardware. LIGHTs can also be assigned to specific blocks within the <CREATE> tag. If used in the <CREATE> tag, the LOCATION attribute is not necessary.

<POINT_LIGHT STYLE="pulsate"
LOCATION="(column,row,level)"
POSITION="(x, y, z)"
BRIGHTNESS="min%..max%"
RADIUS = "#_of_blocks"
FLOOD="yes|no"
COLOR="(red,green,blue)"
SPEED="cycles_per_second" />
Defines a point_light that constantly pulses from the minimum brightness to the maximum brightness. If SPEED="2", the light will go from the minimum brightness to the maximum and back again 2 times per second.

<SPOT_LIGHT STYLE="static"
LOCATION="(column,row,level)"
POSITION="(x, y, z)"
BRIGHTNESS="n%"
RADIUS="#_of_blocks"
FLOOD="yes|no"
COLOR="(red,green,blue)"
DIRECTION="(turn, tilt)"
CONE=angle"/>
Defines a static spot_light at a specified location that shines in a specified direction. DIRECTION is expressed as a pair of angles. The turn angle describes a direction in the horizontal plane, from 0 to 359 degrees, with 0 being north. The tilt angle describes a direction in the vertical plane, from -90 to 90 degrees, with 90 pointing straight up, 0 pointing at the horizon, and -90 pointing straight down. The CONE describes how wide the light is in degrees.

<SPOT_LIGHT STYLE="search"
LOCATION="(column,row,level)"
POSITION="(x, y, z)"
BRIGHTNESS="n%"
RADIUS="blocks"
FLOOD="yes|no"
COLOR="(red,green,blue)"
DIRECTION="(turn1,tilt1)..(turn2,tilt2)"
CONE = "angle"
SPEED="cycles_per_second" />
Defines a searching spot_light that moves from direction 1 to direction 2 and back again at the specified speed.

<SPOT_LIGHT STYLE=revolve
LOCATION="(column,row,level)
POSITION="(x, y, z)"
BRIGHTNESS="n%"
RADIUS="blocks"
FLOOD="yes|no"
COLOR="(red,green,blue)"
DIRECTION="(turn1,tilt1)..(turn2, tilt2)"
CONE="angle"
SPEED="revolutions_per_second" />
Defines a rotating spot_light that passes through directions 1 and 2 at the specified number of revolutions per second.

Block Reference Guides
The blockset guides show you what blocks are available in each block set, with a list of their part names, default symbols, and default textures. You may find it useful to print these guides to use as a reference while you are building spots. The block set demo spots allow you to view each block in the block set in a 3DML environment, and give some examples of how the blocks can be put together. If you approach a block in one of these spots, a POPUP will appear with the block name, default symbol, and part names.

Basic Blockset Guide

Basic2 Blockset Guide

Village Blockset Guide

Islands Blockset Guide

Interior Blockset Guide

THE TEXTURE SETS

The Basic Textures

The Basic2 Textures

The Village Textures

The Islands Textures

The Interior Textures

The Spotsprings Textures

The TombRaider Textures

BLOCKSET DEMO SPOTS

Basic Blockset Spot

Basic2 Blockset Spot

Village Blockset Spot

Islands Blockset Spot

Interior Blockset Spot


3DML语言

网络多媒体-3D-编程语言

3DML语言 这是一种比VRML更简单易学的3D Web场景制作语言，是由Flatland公司（http://www.flatland.com）创建。该公司声称：用这种语言建立3D homepage像用HTML建立2D网页那样简单。该公司提供浏览器插件，观看3DML场景您可以下载Rover1.4（800K）。有了它您就可以观看用3DML建立的3D Web了。

Flatland Rover for Netscape 1.0 (665 免费软件)

用 3DML （ 叫 运 动 ） 生 成 的 网 页 是 完 全 可 浏 览 的 、 完 全 可 用 户 化 的 虚 拟 环 境 ， 它 综 合 了 图 像 、 文 本 、 动 画 、 声 音 和 超 连 接 。 你 可 以 用 构 造 部 件 建 造 三 维 空 间 ， 而 不 必 精 通 一 些 复 杂 的 造 模 程 序 ， 并 不 必 成 为 一 个 程 序 员 。 Flatland Rover 提 供 高 水 平 的 构 造 部 件 ， 如 广 告 板 、 街 柱 灯 、 墙 、 树 、 房 子 和 与 3DML 相 连 的 超 连 接 ， 这 些 部 件 使 单 个 建 造 者 建 造 相 当 好 空 间 和 交 互 式 的 界 面 变 得 简 单 。 Flatland Rover 支 持 JPG 和 GIF 文 件 （ 包 括 动 画 GIF ） 、 立 体 空 间 声 音 （ 用 WAV 格 式 ） 和 Direct3D 。

版本号码： 1.0
文件大小：665
发布日期：1998-12-10
购买信息：免费软件
操作平台：Windows 95/98/NT
THREE WAYS TO HOST A SPOT
The EMBED tag in HTML (the easiest way!)

The first is to embed your 3DML spots in HTML pages. (see below). This solution will work for any Web server out there.

EMBEDDING 3DML IN AN HTML PAGE
With this solution, you put an HTML page up on your site that includes a simple EMBED tag - this tag works for both MS IE 4.0, 5.0beta and Netscape 3.0, 4.5. The EMBED tag includes the 3DML MIME type and a link to your .3dml files.

Just copy the code below, and save it as an HTML file. Edit the TITLE to be your spot title and SRC to point to your 3DML file. If your 3DML file is called "flatrocks.3dml", then you will want to call this HTML page "flatrocks.html". If someone goes to this HTML file and does not have Rover, they will be given the option to go to the PLUGINSPAGE (our download page) to get their own copy.

This should work on all Web servers out there, with the exception of some of the free homepage services. Tripod, for instance, will only allow you to upload files that have specific file extensions, and .3dml is not one of them (yet). We are working on solutions for these situations. If this solution does not work on your server for some reason, please let us know.

<HTML>
<HEAD>
<TITLE>Flatland Rocks!</TITLE>
</HEAD>
<BODY BGCOLOR="#000000" LEFTMARGIN=0 TOPMARGIN=0 SCROLL="no">

<EMBED
        TYPE="model/vnd.flatland.3dml"
SRC="flatrocks.3dml"
PLUGINSPAGE="http://www.flatland.com/download/"
HEIGHT="100%"
WIDTH="100%">
</BODY>
</HTML>

例子:
Hosting 3DML spots at Flatland or on free web hosting services

Many folks building on the web today put their websites up for free on free web hosting services. Currently, some free hosting services do host 3DML spots, while some do not. Click here to learn how to host your Spot at your free homepage hosting service.

TRIPOD ADOPTS 3DML MIME TYPE
Great news! The free homepage hosting service Tripod, at http://www.tripod.com, has adopted the 3DML MIME type. For builders who use Tripod to host your web sites and Spots, you no longer need to embed your Spot in an HTML page. Instead, you can link to it directly!

HOSTING 3DML SPOTS
Most free homepage hosting services will host a Spot which has been embedded in an HTML file. However, the process for setting up a site differs slightly on the different hosting services. Here we've provided a guide for how to set up a site on most free homepage hosting services:

  • Tripod
  • Xoom
  • Acmecity
  • Fortune City
  • Geocities

HOSTING TOOLS > NOVICE & BROWSER BASED UPLOADS
Generally, free homepage hosting providers have one of three ways to set up a site. First there is a "novice" tool that walks you through building your first HTML only page. Typically, a Novice tool will prompt you where to put your name, e-mail address and picture of your cat, and will save the file to your space on their server. Novice tools are not generally useful for 3DML files as they are very simple tools that only feature HTML. The second tool you'll come across from a hosting service is usually a browser-based file-uploading tool. This allows you to upload files to the server that you have already built on your hard-drive. In most cases, neither of these two options will work for posting 3DML spots to your web sites. Instead, the best route for putting 3DML Spots on your site is to use FTP.

HOSTING TOOLS > FTP CLIENTS
Many of the providers have a way of "FTPing" your files to their server. FTP stands for File Transfer Protocol and means that your files are transferred directly to the server space you have been given. For information on downloading and using an FTP client see the help pages at http://geocities.yahoo.com/help/ftp/. For hosting 3DML Spots, the FTP client will usually be your best bet.

HOSTING YOUR SPOT > DON'T FORGET TO EMBED!
Currently, TRIPOD is the only free hosting service which supports the 3DML mime type. If you are using any other service, you will need to embed your 3DML spot in an HTML file. This is very simple! Click here to embed your Spot in an HTML file.

HOSTING GUIDE
Click on the name of the service that you use to learn how put your Spot on the Web.

  • Tripod
  • Xoom
  • Acmecity
  • Fortune City
  • Geocities

The .htaccess file for Apache servers

This second method works only on Apache Web servers. (Over half of the Web servers out there run Apache.) If you know your Web server is Apache, you can simply upload a single simple file called the .htaccess file that will take care of the whole MIME type issue. Click here to learn more about the .htaccess file for Apache servers.

Hosting spots on Apache Servers
There are two different ways to get Apache to handle the 3DML MIME type correctly. Either upload a .htaccess file to the toplevel of your directory, or get your ISP to support the 3DML MIME type on the entire system.

You can put a .htaccess file in your top level Web site directory which will tell your Web server about the 3DML MIME type.

Putting 3DML on the Web: Add an .htaccess file to your web server

If you already have a .htaccess file, then all you need to do is add the following line to this file near the bottom:

AddType model/vnd.flatland.3dml .3dml .3dm

If you don't know whether or not you have a .htaccess file, then you probably don't. So here's what to do:

Download this .htaccess file, and rename the file by adding a period [.] to the beginning of the file name. The file should now be called ".htaccess". Don't forget that period! Without the period at the beginning of the file name, it won't work. Now you can FTP that .htaccess file into the top level directory for your Web site.

The top level directory of your Web site is the directory (or folder) on your server that holds all of the contents of your Web site. For instance, if the URL for your Web site is http://www.acme.net/~myname , then when you connect to the acme server via ftp, you probably land in a directory called "myname". This is the directory where you want to put the .htaccess file.

Before you FTP your .htaccess file into the top level directory of your site, check the directory, and make sure you don't already have an .htaccess file. If you already do, download the file, add the line from the top of this page, and upload your new .htaccess file back into your directory.

You can ask your ISP [Internet Service Provider] to add the 3DML MIME to the server directly. Flatland has created an automated request form-letter that makes asking your ISP a simple one-click task.

3DML Tutorial
click here to learn more about 3dml.


DirectX
Microsoft的DirectX系统提供了一套快速图形、声音和控制接口．它分为 Direct Draw、Direct 3D、Direct Sound、Direct Music、Direct Input.
概述

DirectX是一套为Windows程序提供对系统硬件更紧密控制的组件。（表1列 出了DirectX 7.0的组件及其作用）。那么，紧密控制是什么意思呢？

表1：DirectX 7.0的组件及其作用

组件 | 用途
DirectDraw | 高速2D图象
DirectSound | 短响应时间声音输出
Direct3D | 高速3D图象
DirectInput | 面向游戏的对游戏杆和其它输入设备的访问
DirectSetup | 方便的安装DirectX组件
DirectPlay | 面向游戏的通信和网络支持
DirectShow | 视频流支持
DirectAnimation | 动画录放支持

DirectX提供的硬件控制常常被描述成底层控制，这会使人联想起位操作和其它讨厌的事情。实际上，DirectX组件包含许多高层API，使得象复制位图和播放声音等复杂的工作变得相当简单。用“为程序提供比过去更好的对硬件的控制”来形容DirectX更准确。这在Windows中是一个显著的特性，因为 在Windows中，资源是共享的，并由操作系统控制。

DirectX组件遵守称为COM的二进制对象的工业标准。

开始DirectX

下面从DirectX的安装开始讲起。大多数情况下，某个好玩的游戏就会为系统安装DirectX。为得到最新的版本，应该从最新的Microsoft Platform SDK中 将DirectX安装到系统中。可以在http://www.microsoft.com/msdn站点或者 MSDN光盘中找到platform SDK。缺省情况下，Microsoft Platform SDK被安装到缺省驱动器根目录下的\MSSDK目录中。DirectX的头文件安装在 \MSSDK\INCLUDE目录中，Lib文件安装在\MSSDK\LIB目录中。

Platform SDK包含了一些非常好的DirectX例子和文档。早期发布的 DirectX 文档非常粗略而且有些是错误的，现在的版本已经极大地改正了这一问题。最好要熟悉这些文档。

现在已经为安装利用DirectX的程序做好了准备。所幸的是，不必一次就处理DirectX的全部功能。DirectX是一套可以分别使用的组件。实际上，在编程概念中，DirectX的不同部分互相没有联系。它们仅仅是具有相同的设计风格和目标：使Windows的游戏编程变得容易。

使用DirectX组件的程序有什么特殊的地方吗？根本没有。使用DirectX组件 的程序是基于Win32的程序，它们使用普通Win32 API集，并且可以访问所有可以获得的操作系统工具。实际上，DirectX既可以用于GUI程序，也可以用于控 制台程序。可以直接用Petzold-style SDK编程开发程序，也可以用基本类库， 如MFC。总的说，唯一的要求是大多数DirectX组件在程序中需要HWND，所以至少要有一个窗口。

虽然DirectX组件是分离的，但是每个组件的实现风格和使用都是相同的。 DirectInput是学习DirectX的非常好的出发点，原因是DirectInput是最简单的组件之一。

关于DirectDraw

DirectDraw是DirectX API的一部分能让你直接操作显存，硬件显存块移动(Blitter)，支持硬件屏遮(OverLay)，转动平面(Flipping Surface)。DirectDraw在提供这些特性同时保持与Microsoft Windows的应用程序及设备驱动程序的兼容。

DirectDraw是一个与Windows 图形系统接口(GDI)相兼容的直接操作显示设备的软件接口。这并不是一个高级的图形API。DirectDraw为游戏及Windows提供一个与系统无关的软件子系统，例如：3-D图形及数字图象编译码器，更好的访问特殊显示设备。

DirectDraw可以在许多各种不同的显示硬件上工作，从简单SVGA监视器到硬件支持剪切、伸拉，及非RGB色彩格式。这个接口可使你的程序使用各种硬件特性及DirectX 模拟的硬件尚不支持的特性。

DirectDraw提供与硬件无关性的同时允许直接操作显存。程序只要使用一些基本的标准硬件约定如：RGB及YUV色彩格式及解析度。你无须调用特殊的过程来使用显存块移动(Blitter)及调色板。使用DirectDraw，你可简单操作显存，完全使用各种硬件特性而不必理会各种不同硬件之间的差异。

DirectDraw提供一个世界范围的运行在Windows95及Windows NT Version4.0 及以上的游戏图形系统。

为什么使用DirectDraw?

DirectDraw为Windows图形程序提供了许多有力的特性功能：

DirectDraw的硬件操作层(Hardware Abstraction Layer<HAL>)为直接操作显示硬件提供了一个坚实的接口，并给予最大的优化。

DirectDraw会评估硬件的性能，使用硬件提供的特性如果可以的话。例如：如果你的显示卡支持硬件显存块移动，DirectDraw就会将工作交由显示卡来完成，从而获得优化。另外，DirectDraw提供一个硬件模拟层(Hardware Emulation Layer<HEL>来支持硬件不支持的特性。

DirectDraw基于Windows，可充分发挥操作系统提供的32-Bit内存寻址及线性内存模式。DirectDraw将显存及内存看作为一个大的块，并不是段。如果你以前使用段寻址的话，那么你会为线性内存模式感到激动。 DirectDraw使你的全屏程序可以方便生成屏后缓冲的页交换 (Page Flipping 译者按：交换屏后缓冲与显示缓冲地址的一种过程，有效的将图象从屏后缓冲放入显示缓冲，从而显示该图象。)详见页交换和屏后缓冲。

窗口全屏的剪切支持。

3-D Z-缓冲支持。

硬件重叠层(OverLays)的Z-顺序支持。

硬件图形伸拉。

同时访问标准及增强的显示设备内存区域。

其他特性还有定义及动态调色板，专有硬件访问，分辨率开关。

这些特性使你能完全能表现标准的基于GDI的Windows程序甚至MS-DOS 应用程序。


梦幻般的VRML技术

随着国际互联网络的普及，网络技术和硬件设施的飞速发展，虚拟现实技术将成为今后网络多媒体发展方向的主流。VRML作为一种ISO国际标准将得到越来越广泛的应用。 VRML语言的起源可以追溯到1994年3月，当时，World Wide Web以及HTML语言的主要创始人Tim Berners-Lee和对HTML语言做出重要贡献的David Raggett在瑞士日内瓦召开的第一次世界World Wide Web大会期间，召集了一次题为Virtual Reality Markup Language and the World Wide Web（虚拟现实标注语言与万维网）的会议。以此为开端，许多研究人员参与了VRML 1.0规范的讨论与规划。 VRML 1.0草案于1994年10月在美国芝加哥召开的第二次世界World Wide Web大会上发布。 虚拟现实本身需要的只是艺术的三维造型和天马行空的创意，但由于现今计算机软件在这方面技术支持的缺乏，使得虚拟现实的制作不得不面对枯燥的VRML编写，要把那些数字和三维空间的模型联系起来是一件很困难的事。 现在有许多3D制作软件支持VRML格式的直接输出，不再面对枯燥的VRML代码，是一件多么令人感到惬意的事情。
The Web3D Repository

Web3d creation tools
A Web3D creation tool is any application, that assists a content creator to create 3D content or automatically generates Web3D content.

The listings below provide links to vendors providing free, shareware, or pay-ware products.

By listing the products below, Web3D consortium and the Web3D Repository are only providing information, and are not endorsing any of these products.

Note: as the differences between VRML 2.0 and VRML 97 are, for most purposes minor, the term VRML 97 will be used to refer to both in the technology column.

68 Entries Listed Alphabetically by Item
Item Technology
  • 2000cities Builder (2000cities )
    • VRML97

    With the 2000cities Builder you can build 3D sites for the 2000cities Traveler plug-in for Internet Explorer. Easily create highly interactive 3D experiences for everyone, since the data is fastly transmitted over narrwoband connections.

      Platform:
      • Windows
  • 3DAnywhere Monfort Software Engineering Ltd
    • VRML 2.0

    3DAnywhere is the ultimate tool for building web catalogs and 3D presentation over the Internet FREE DOWNLOAD

      Platforms:
      • PC
  • 3D Create ( Darwin 3D )
    • VRML 1.0

    Create a 3D Avatar from any image file. Attach 3D accessories and select from 100 motion files. Includes mesh deformation and 3D Paint.

      Platforms:
      • Windows95
  • 3DDreams (Shells Interactive )
    • SHOCKWAVE

    Use 3D Dreams 2.0 from Shells Interactive to build real-time 3D experiences. Enhance creativity and user interactivity in all the Internet and multimedia projects you build with Director. 3D Dreams 2.0 is a breakthrough, freeing the multimedia author from Director's linear limits.

  • 3Dstats ( Stefan Stapelberg )
    • VRML 1.0

    3Dstats analyzes the access log of a Web server and creates a simple VRML model of the load by day and by hour. Although 3Dstats is copyrighted, the source code is free available.

      Platforms:
      • C source code
  • 3D Virtual Characters ( W Interactive SARL. )
    • VRML97 -JAVA

    W Interactive offers high quality 3D models of human faces produced from photographs. We can make a 3D VRML model of any person rapidly, with high quality and at a low cost. W Interactive also offers Java-based talking Virtual Characters for the Web. The company is looking for resellers and offers 10% commission with our easy-to-use Reseller Program.

    n.b. this is a service rather than a tool

      Platforms:

      • any web browser
  • AC3D
    • VRML97 -POV +

    AC3D is popular 3D object/scene modeller. It's is very easy to use but powerful too - anyone can create good looking 3d objects in minutes.

    It outputs POV-Ray, VRML (1 and 2), RenderMan, Dive, Massive and other formats.

      Platforms:

      • Windows 95/NT
      • Linux
      • SGI
      • Solaris - V2 Free (unsupported)
      • HP - V1.66 (HPUX 10.10) Free (unsupported)
      • SunOs - V1.55 - (sorry, there will be no more Sun4 versions - upgrade to Solaris)
  • Alice (Carnegie Mellon )
    • Alice

    includes:

    • The Alice Development Environment
    • A Collection of 3D Objects and Textures

    The Alice authoring tool doesn't require any special graphics boards, input devices, or hardware acceleration.

      Platforms:

      • Windows 95/98/NT

  • Art of Illusion (Peter Eastman )
    • Java - VRML

    Art of Illusion is a free, open source 3D modelling and rendering studio. It is written entirely in Java, and should be usable on any Java Virtual Machine which is compatible with JDK 1.1 or later. The current version is 0.8, released April 5, 2001.

    It already has modelling, texturing, and rendering capabilities which exceed those found in many commercial programs. Exports VRML

      Platforms:

      • Windows
      • Mac
      • Linux
      • Solaris

      N.B. this software is Alpha software - novice computer users should only install if competent help is available
  • Atmosphere Builder (Adobe)
    • unknown

    Are you ready to create the third dimension on the Web? Snap together walls, windows and staircases, and apply textures, lighting, sounds, and animations. Don't just create a site on the web梒reate a new immersive, virtual 3D world.

      Platforms:

      • Windows

    n.b. this software is beta software

  • Amapi 3D - The Natural Way to Model ( Template Graphics Software )
    • VRML 1.0

    Amapi 3D is a phenomenal Nurbs model with a natural approach to a unique user interface for 3D sculpting, design and modeling. With a large collection of powerful 3D tools like extrusions, sweeps, double-sweeps, hulls, Coons patches and complex Gordon surfaces, creating complex shapes is a snap. Additional modeling tools include a fast fileting (bevels), Smoothing (organic looks), various stretching and molding tool, MetaNurbs, and thickness tools. The Assembly toolkit has Unfold tools, duplication (along paths and surfaces too), and more. Objects you create in Amapi can include curves, Nurbs curves, surfaces, Nurbs surfaces, Volumes, and the measurement tool tells you all about their precise metrics. Amapi also includes a hybrid renderer with raytracing and cartoon effects, as well as animation along paths and 3D morphing (keyframes) into Quicktime or AVI. There is a vast files export list (over 22)including some suited for the web, such as VRML 1.0 and ZAP. Best of all, Amapi is fun, extremely fast and very affordable, especially for students. Lots of kids (Amapikids) have discovered and use Amapi as an extension of their 3D creativity.

      Platforms:
      • Windows 9X/NT4
      • MacOS 8
  • AvatarMaker 3D 1.0 ( Sven Technologies Inc. )
    • VRML 1.0 VRML 97

    n.b. end user sales discontinued

    AvatarMaker is the first consumer avatar creation tool. It allows the user to create full photorealistic 3d characters and people for use in VRML1.0/2.0, web pages, and multi-user worlds. A unique intuitive interface allows sophisticated authoring without expertise or experience.

      Platforms:
      • Windows 95 ·
      • Windows NT
  • Avatar Studio (Canal+)
    • VRML97

    Avatar Studio is an avatar creation tool that helps you build your own personalized and animated character.

      Platforms:
      • PC
  • b3d Studio (b3d)
    • b3d

    b3d Studio's real-time 3D technology and editing tools give you the power to create complex interactive animated content for the web. From interactive 3D objects in a web page to full-feature movies, b3d Studio delivers. For larger productions, b3d Studio Pro supports multiple simultaneous users and rendered video output.

      • PC
  • Canoma ( Metacreations Inc.)
    • VRML 97

    Canoma can generate realistic 3D models from one or more photographs or sketches using a process called image assisted modeling. Models can be exported in a variety of 2D and 3D formats including VRML97 (see http://www.canoma.com/vrml for examples)

      Platforms:
      • Win32
      • Mac
  • CiteMap Builder ( Trivista.)
    • VRML 97

    CiteMaps are interactive VRML scenes of hyperlinked 3D objects. The CiteMap Builder is designed to be very simple and easy to use, even for those with no VRML experience. A collection of over 100 objects can be dragged and dropped onto a grid, and additional information such as URL, label, title, and abstract can be applied to each object.

    n.b.: CiteMap Builder is available as unsupported freeware.

      Platforms:
      • Win32
  • Clayworks
    • VRML 1.0 · VRML 97

    A new version of Clayworks, a complete rewrite , is currently under development. This software is a major break from the old 16bit dos application and is set to become something rather special. The final version of the 16bit software with improved VRML export support is available from that URL. The new version will support VRML 1.0 & 2.0 import and export as well as a variety of other common formats and a wide range of modeling tools and paradigms including improved vertex/polygon level editing as well as other techniques such as metaballs and curved surfaces.

      Platforms:
      • Windows 95
      • Windows NT
    CONOMAL
  • Cortona SDK version 2.0 ( ParallelGraphics)
    • VRML 97

    Cortona SDK enables developers to integrate Cortona 3D/VRML engine into applications written in C/C++, Visual Basic? Delphi?or HTML - as well as to any application supporting ActiveX technology (MS Word, MS PowerPoint etc.).
    With Cortona SDK, you can create a wide array of 3D applications ?ranging from a 3D presentation of your company to advanced VRML authoring tools. Utilizing Cortona SDK can dramatically improve your business.
    You can use the tool for:
    * Interactive product presentations
    * Realty information services
    * Engineering visualizations
    * Virtual manuals for distance learning
    The Cortona SDK 2.0 distribution package contains: - Cortona's redistributable components - Programmer's reference for Cortona ActiveX control - Documentation for VRML Automation - Tutorials for Visual Basic and Delphi programmers - Description of VRML extensions in Cortona - Interface definition files for C/C++ projects - I3DViewService3 interface - ASCII to UTF8 converter 1.0 - User friendly examples of 3D applications Additionally, ParallelGraphics grants Cortona SDK users a license for the redistribution of 100 copies of Cortona VRML client.
    If you are looking for an effective and powerful 3D engine for your web site or standalone application - check out Cortona SDK!

      Platforms:
      • Windows 95 and above
  • Daylon Leveller ( Daylon Graphics)
    • exports to VRML97-DFX-POv +

    You've struggled to make bumpmaps and terrain with paint programs and bitmap editors. You've bumped up time and again against the limits of 8-bit grayscale files. You've played with idiosyncratic shareware. Wouldn't it be great if someone simply made a true, polished, fully supported heightfield modeler, and made it very affordable?

  • Design ( Inquire )
    • Various

    Inquire?Design was developed to support the product design process and, in particular, the designer himself as he works on a design. Therefore, this software package provides the freedom for innovative, conceptual design work using only the most sensible and relevant functions found in more traditional CAD tools. For every task involving object form, in the most varied of branches - with Inquire?Design each will find a perfect tool tailored to one's exact needs. Complex changes may be speedily performed with this product because the breadth of features, coupled with the simple interface, allow rapid entry into the creative process. Both the refinement of existing models, as well as the creation of new models, is quickly and simply done with Inquire?Design - with just a few mouse clicks new forms can be created and modified and all that without large computation delays. Inquire?Design - the new dimension in design.
    The following object exchange formats are also supported:
    3DS COB DXF POV INC NFF OBJ RAW IGES IV WRL STL and WIRE

      Platforms:
      • Windows 95/98
      • Windows NT 4.0
      • SGI IRIX 6.3
  • DesignSpace ( DesignSpace, a division of ANSYS )
    • VRML 1.0 · VRML 97

    DesignSpace is engineering software that enables design engineers to obtain answers to basic design performance questions without the steep learning curve of traditional methods. DesignSpace is integrated inside mainstream PC-based solid modelers, such as Autodesk Mechanical Desktop and SolidWorks. Simulation results can be saved in VRML 1.0 or 2.0 format for inclusion in web-enabled engineering reports. Users not only can view results over the Internet, they can also interact with the results.

      Platforms:
      • Windows 95
      • Windows NT
  • Dimension 3D Scanner ( Micrografx )
    • VRML 97

    Dimension 3D Systems offers an easy to use camera based 3D scanner that enables you to create realistic models out of real 3D objects within minutes. Output models are fully textured (360 deg) closed triangular meshes in many 3D formats

      Platforms:
      • Windows 95/98
      • Windows NT
      • IRIX 5.3 & higher
    Dune v0.13 (Stephen White)
    VRML97

    The open source authoring tool for 3D. There's still lots of work to do, but with the addition of NurbsSurface support, you can almost do some real modeling with it now.

      Platforms:
      • Win95/98/NT/2000
      • linux
      • irix 6.5
      • solaris
  • Extrusion Editor ( ParallelGraphics)
    • VRML 97

    Extrusion Editor, a visual plug-in for ParallelGraphics' VrmlPad, offers you an effective method for creating and editing extrusion models.
    Key features include: Visual support for every step in the creation of extrusions; all manipulations with the extrusion parameters are immediately displayed in the 3D window. Ability to create the cross-sections and spines based on spline curves. Advanced interactive texture mapping . Ability to assemble created extrusions in complex models. Expandable library of extrusions.
    Full VRML97-compliance.

      Platforms:
      • Win 95/98/ME/2000 or Win NT 4.0

  • ez Avatar Builder ( P Flavin)
    • X3D

    X3D Viewer with extensions ( without VRML EAI ) -
    Load _ Multiple _ X3D / VRML files from a List - change rendering modes - cool textured Sci-fi Biped Walking Tank -
    see the future of the 3d on the Web today ...
    " ez Avatar Builder " _ extends _ the Shout3d X3D Viewer

    n.b. this tool is still under development at the date of listing 2000.4.30
  • Geomagic Studio (Geomagic)
    • various

    Geomagic Studio is a must-have tool for people working with traditional CAD, CAE, and CAM applications. Geomagic Studio 3.0 expands your ability to quickly and accurately create, edit, export, and output high-quality, manufacturable NURBS surfaces.

      Platforms:
      • PC Win98/NT
      • SGI IRIX
      • Sun Solaris
  • GEOMETRA ( AEA Technology plc )
    • VRML 97

    GEOMETRA is a program which allows the quick and easy construction of 3-D VRML models from multiple photographs of an object or scene. These models can be output and then used directly for publication on the web or further manipulated in other 3-D editing software. The basic version of GEOMETRA is free for noncommercial use while more advanced versions featuring photogrammertric capability and epitomized model output can be purchased on-line.

      Platforms:
      • PC Win95/98/NT
  • Hot Media 3.5 ( IBM )
    • JAVA

    IBM HotMedia is the industry's most complete solution for incorporating rich media effects in today's web applications. HotMedia lets you easily add interactions and special effects such as video, 3D, animations, panoramas, streaming audio synchronized with images and more. It provides a single, easy to use authoring environment for creation of a wide range of rich media effects. The result is a single file containing multiple interactive elements that is easily added to a web page. HotMedia does not require a plugin or any special servers and its offered free-of-charge from IBM.

      Platforms:
      • PC Win95/98/NT
      • Macintosh
      • Java
  • Hypercosm 3D development tools Hyperscom
    • JAVA

    Using Hypercosm's powerful set of 3D development tools, you will be able to bring your own 3D visions to life on the Web. You can use Hypercosm translators to convert existing 3D models into super-small Hypercosm applets, or you can use the Hypercosm Studio development environment to develop and customize new graphics.

    Hypercosm not only provides you with the software tools you need to produce highly-interactive Hypercosm content, but we also provide the training you or your developers need to get up-to-speed with Hypercosm technology. In addition, Hypercosm provides a full set of manuals, tutorials, and a website dedicated to applet developers, ensuring that help in applet production is never hard to find.

      Platforms:
      • Java
  • Innovation3D 0.5
    • VRML97

    Innovation3D is an Open Source, 3-dimensional modeling program developed for Linux.
    The goal of Innovation3D ( I3D ) is to provide a modeling tool that allows an artist to utilize a variety of techniques. Polygonal modeling is currently the focus, but there is some preliminary support for NURBS curves and surfaces, as well as basic animation. Innovation3D is software in active development.

    n.b. under development
    You can use it for many things, but you many not get it to compile, and it may crash. Please take this in to account when using it. Be sure to report any problems that you are having! g, etc. We also reserve the right to include a small advertisement in your home world.

      Platforms:
      • Linux
  • Inspire 3D ( NewTek)
            • See list

    Inspire 3D is packed with high-quality tools that help guarantee you'll be ready for the new generation of professional graphics. With Inspire 3D, you can model, animate and render 3D elements in any style and complexity. By adding texture, motion, lighting effects and more, your print materials will almost pop off the page. Use the images you create as single frame print graphics or as lower resolution animation files for multimedia or the web卭r choose from a library of pre-created images. And use the photorealistic or stylized animation images you create for real-time graphics applications, including VRML 2.0, for all kinds of projects.

      • Import DXF (AutoCAD) 3DS (3D Studio) OBJ (Alias/Wavefront) LightWave
      • Export DXF (AutoCAD) 3DS (3D Studio) OBJ (Alias/Wavefront) LightWave VRML 2.0 3DMF

      Platforms:

      • Windows
      • Mac

  • INT3D ( Pharus S.r.l. )
    • VRML 97

    INT3D System is made for the creation of 3D virtual interiors to present on Internet. The system is realized in VRML format, but the user does not need to know that language. INT3D?System includes:
    Online 3D editor (INT3D-editor)
    Online 3D viewer (INT3D-viewer)
    Interactive 3D models (INT3D-models)
    3D scenes (INT3D-scenes)

      Platforms:
      • Not applicable - this an online tool


梦幻般的VRML技术
  • Internet Character Animator v. 1.0 ( ParallelGraphics )
    • VRML 97

    ICA lets you animate 3D characters for the Internet ranging from sketches to complex games and presentations. Key features include:
    - Key Frame Animator. With KFA you can endow characters with a variety of expressions, gestures and movements.
    - Animation Organizer allows you to set the sequence and duration of created animations.
    - Animated characters can be published on the Web. And the interface for the first nine animations can be created by a single mouse-click!
    - Compatibility with Internet Scene Assembler of ParallelGraphics. Animated characters can be placed into ISA scenes to add a range of new interactivities and animations
    - an essential element in the development of interactive clips for the Web! ICA supports VRML97 format and H-anim standard.

      Platforms:
      • Win 95/98/2000 Win NT
  • Internet Model Optimizer ( ParallelGraphics )
    • VRML 97 - DXF

    IMO is a next generation tool that provides an efficient way to optimize complex 3D models, which originate from CAD/CAM/CAE systems and other sources, for use on the Internet. Many companies have large libraries of CAD models but have until now been unable to use this valuable resource on the Internet. IMO allows users to dramatically accelerate the rendering of these models by polygonal simplification and offers a wide range of optimization modes - from batch processing to manual mode - plus the ability to optimize selected parts of the model only.

      Platforms:
      • Win 95/98/2000 Win NT
  • Internet Scene Assembler ( Parallel Graphics )
    • VRML 97

    Internet Scene Assembler allows you to assembly interactive and dynamic scenes. You can choose animated or static objects from the extensive ISA- galleries or use any other VRML-file as an object and animate it with ISA. Created scenes can be published on the World Wide Web and viewed in all major VRML-browsers. You can make objects react to user action or events, which happen inside scenes. ISA allows you to establish relations between various events, so you can create complex objects behavior. You can create interactive objects merely adding various properties to them, for example, "Moveable", "Hidable", "Highlighted", "Turnable " or "Labeled" - to link texts to objects etc. With ISA Keyframe Animator you will easily define changing of object size, position, orientation, color, transparency, intensity etc. If you establish objects subordination, all movements of the main objects will spread to all their sub-objects. For example, a table is an object and a vase is its sub-object. When you move the table, the vase is moved too ISA includes pre-build galleries with static and animated objects - figurines, furniture, plants etc. The galleries also contain a special group of system objects. Using them you can set light sources and animated camera in scenes, add sounds to objects etc. You can save the track of the camera movements. It helps to present objects and scenes to viewers in the most attractive or unusual ways or define complete tour along created scenes. One of the main ISA advantages is visual support for all major operations with objects. You do not need to program, all manipulation with objects are represented in specialized windows: Perspective and Plan - view of objects and scenes; Animator - objects animation parameters; Routing Diagram - relations between different events; Events/Properties - lists of objects properties (e.g. "Moveable") and events; Scene Tree - hierarchical structure of objects

      Platforms:
      • Win 95/98/2000 Win NT
  • Internet Space Builder 3.0 ( Parallel Graphics )
    • VRML 97

    A simple way of arranging objects ("drag&drop"); Editing of 3D objects - rotation, scale, deformation, mirror and texture mapping; Building of complex 3D-objects and structures from simple elements by merely adding and cutting; Direct editing of objects and scenes in a 3D- window; Texture editing - scale, rotation, drawing; Creation of complex panoramic images by using pre- built impressive landscapes, selecting background textures and editing background colors; transparency effect; Multimedia support - sounds (WAV and MIDI formats) can be linked into objects and movies can be placed on object surfaces; The objects and scenes created may be published on the World Wide Web. (Then they can be viewed using any standard VRML browser); Internet addresses can be linked to the objects created The ISB Library contains a wide range of textures, pictures, 3D-models and objects, movies and virtual world examples. A friendly and adaptable interface. ISB contains a detailed Help system and an illustrated hypertext Quick Start Guide, which includes descriptions of the basic methods of creating 3D objects and scenes, editing textures and objects etc. Evaluation version available.

      Platforms:
      • Win 95/98/2000 Win NT
  • ImageModeler2 (Realviz)
    • various

    to build realistic models directly from photos ! It will automate construction of, dimensionally accurate 3D models including texture maps, from still pictures
    Instead of modeling complicated geometry, materials and lighting from scratch, ImageModeler?taps directly into the richness of the real world. Designed specifically for computer graphics professionals and animators, ImageModeler?is the first high-end "Image-Based Modeler" to produce 3-D models from photo, video or cinematic images.

      Platforms:
      • Win NT
      • IRIX

    IVL: An Interactive VRML Modeler and Scene Builder.

  • Jicasso (Equitysoft)
    • Java3D

    Jicasso creates 3D scenes based on Java3D without any programming. Components from a library can be selected, positioned, colored and textured to create the required layout. The overall applet size can be as big or as small as is required. To create a scene is simple

      Platforms:
      • Java
  • Jvr - Java VR Creation tool (Orbitec Pty Ltd)
    • Java

    Jvr is a java application to create and edit 3D geometry and export it as VRML97 IndexedFaceSets.

      Platforms:
      • Any with Java Virtual Machine
  • Lodestar LOD Generator ( Technical University of Vienna )
    • VRML 1.0

    Manual creation of levels of detail for complex models is too labor intensive. Therefore, a tool is needed to generate LODs (levels of detail) automatically. We have implemented such a tool that supports VRML-1.0. It is able to reduce indexed face sets (polygonal data) and indexed line sets that embody the bulk of VRML data commonly found in VRML models. The algorithm is based on octree quantization of vertices. The tool reads a VRML file and generates LODs for each IndexedFaceSet and IndexedLineSet. Further the tool removes double defined coordinates, materials, normals, texture coordinates, faces and lines within the VRML nodes. The resulting VRML scene will be written into a new file.

      Platforms:
      • HP-UX
      • Linux
      • OS/2
      • SGI
  • Lparser ( Laurens Lapre )
    • VRML 1.0

    Lparser is a utility which reads an Lsystem description in and processes it into a 3d form which can then be exported in several formats, including VRML, DXF and POV.

      Platforms:
      • DOS
  • MagicSuite ( Corey Huang )
    • Java

    Magicsuite is an interactive multimedia software designed for the creation of 3D pictures and virtual reality type images. Software compatible with any standard digital camera. Browser independent, does not require any plug-ins and generates relatively small files sizes. Hardware required: 1 tripod (included).
    N.B. Java applets are used for 3d display in web pages.

      Platforms:
      • Windows

    MAPINFO
  • mjbWorld ( Martin Baker )
    • VRML97 - Java3D

    Written entirely in Java using JDK1.2 and Java3D standards. Can create, read, write and edit VRML97 worlds. It can do this graphically selecting and dragging shapes on the screen, where you need more precise control you can set the values in the scene graph. Export to Java3D to allow you to generate Java3D applications from VRML for example. Bean available so that you can incorporate this functionality in your own program.

      Platforms:
      • Java
  • Milkshape Modeler ( Chumbalum Soft)
    • Various

    MilkShape 3D is a low-polygon modeler, which was initially designed for Half-Life. During the development, many file formats have been added. MilkShape 3D has all basic operations like select, move, rotate, scale, extrude, turn edge, subdivide, just to mention a few. MilkShape 3D also allows low-level editing with the vertex and face tool. Primitives like spheres, boxes and cylinders are also available. MilkShape 3D has also skeletal animation capabilities. This allows to export to morph target animation like the ones in the Quake model formats or to export to skeletal animations like Half-life or Genesis3d.

      Related site:
      • A VRML97 exporter plugin for the Milkshape modeler from Roland Smeenk
  • MultiGen Creator ( Multigen Paradigm Inc.)
    • Various

    MultiGen Creator is MultiGen-Paradigm's industry-leading software toolset for creating highly optimized, high fidelity real-time 3D content for use in visual simulation, interactive games, urban simulation, and other applications. This integrated and extensible toolset puts more interactive realtime 3D modeling power in your hands than other modeler. The MultiGen Creator package is cost-effective, interactive, highly automated software that enables productive, efficient, real-time 3D database building without compromising visual quality.

    Supported formats include: .tri .3ds .max . IGES .dxf .lw hrc & database .vis .obj

      Platforms:
      • PC
      • IRIX
  • Nendo ( Nichimen )
    • 3DS, VRML 97, DirectX, Game Exchange 2.0, HMD

    With Nendo, you can create compelling 3D objects for use in model libraries, games, print material, web sites, visual simulation, and architectural applications. Powerful operations for modeling and 3D painting are incorporated into an interface that is simple and intuitive to use.

      Platforms:
      • Windows
  • Online Generato r
    • VRML 97

    At this site I have posted a couple of VRML primitives generators and several examples of obtained VRML-files. The first one is based on Exstrusion node, the second - on IndexedFaceSet.

      Platforms:
      • all
  • PFE
    • VRML - OpenGL

    PFE is a shareware running on the Windows platform free for individual (non commercial) use only. It is dedicated to build 3D text using any font you like. The text can be bevelled, and you can change numbers of parameters such as the level of detail of the mesh or the materials. PFE is user friendly and can be handy for programmers, web designers and artists. PFE outputs still jpeg images, VRML 3D models or OpenGl source code.

      Platforms:
      • win32
  • PhotoModeler Lite
    • DXF, 3DS, and VRML

    PhotoModeler Lite is a fully functional, high-quality Windows freeware program for creating 3D models of real-world objects and scenes through the use of photographs

      Platforms:
      • windows
  • Platinum VRCreator ( Platinum Technology (formerly VREAM) )
    • VRML 1.0 - VRML 97

    VRCreator allows you to author both VRML 1.0 and 2.0 worlds. It comes bundled with 1000 3D VRML objects. VRCreator's modeling engine is ACIS based. It also supports importing file formats such as .3DS, .DXF, Caligari, Lightwave, and more. Comes with the WIRL plugin for Netscape. The graphics display uses Microsoft's Direct3D API for ultra-fast performance. Modelers can drag and drop objects, colors, textures and behaviors to create the most exciting content on the Web. Wizards also help create worlds easily and automatically add them to Web sites.

      Platforms:
      • Windows 95
  • Poser 4 ( Curious Labs)
    • various

    Poser 4 is a 3D-character animation and design tool for artists and animators. Users can create images, movies, and posed 3D figures from a diverse collection of fully articulated 3D human and animal models. Libraries of pose settings, facial expressions, hand gestures, and swappable clothing are included as well. Posing and animating is fast and easy with Poser's unique interface.

    Use of Poser Pro Pack . The Pro Pack offers a combination of robust plug-ins that enable the hosting of Poser scene files inside of 3DstudioMax?and LightWave? exporters to generate 2D Flash animation, and web deployable 3D characters via Viewpoint output, and delivers added core functionality such as Motion Blur, Multi-pane Views, and fully scriptable application control through a Python Interface. New Figure Set-Up tools make it easy to create new characters from any geometry. From creating 2D Flash and streaming 3D for the web, or integrating Poser scenes into powerful 3D tools, the Pro Pack transforms Poser 4 into a character animation powerhouse.

      Platforms:
      • Windows 95
      • Mac
  • Rational Reducer ( SIM )
    • -

    Rational Reducer increases the rendering performance of any computer by reducing the number of polygons in the models, while keeping the visual quality. For most models, Rational Reducer will also substantially reduce the model file size, giving shorter download times. Rational Reducer offers a combination of ease of use and visual quality, achieved by employing a set of advanced algorithms, including differential evolution and experience based algorithms, developed by SIM

      Platforms:
      • SGI IRIX 6.2 and above
      • Microsoft Windows 95/98/NT/2000
      • Linux/x86 2.0 or later
      • HP-UX 10.20 or later
  • Real2Virtual Modeller ( Real2Virtual Modeller )
    • VRML1.0/VRML2.0/VRML97

    Real2Virtual Modeller is a tool for generating 3D VRML models from digital-camera-images, graphical-images, or from free-hand line drawings. No special equipment is needed to use the program - and models may be generated even without a camera. Complex 24-bit colour texture-mapped models can be created by simply drawing around objects seen in the images, or by drawing freehand. Objects with sub-parts, complex shapes, and fine details can be modelled accurately and quickly. Over 120 cameras are now directly supported, and unsupported cameras can be used by following a simple calibration procedure. Models can be viewed using Real2Virtual Viewer (included), or published to the web as very compact VRML1.0 or VRML2.0/VRML97 files. The program is free to use for 60 days, and US$30 to register. The package includes 6 example projects, extensive documentation, and links to online resources. Registered users receive free online support.

      Platforms:
      • Win95/Win98/WinNT
  • RenderSoft VRML Editor ( RenderSoft Software and Web Publishing )
    • VRML 1.0 VRML 97

    RenderSoft VRML Editor is shareware that allows you to quickly and easily create VRML web pages.
    Features supported by the editor include textures, materials, primitives, object transformations and WWW anchor.
    Its rendering is based on OpenGL and is available in Windows 95 platforms.
    The program reads and writes VRML 1.0 ascii files and is able to export VRML 2.0 files.

      Platforms:
      • Windows 95
  • Renoir ( Integra )
    • Inspirer - VRML 97

    RENOIR is a software intended for: Reconstruction of the shape and color attributes of architectural objects from photo-images of these objects. Texture mapped 3D model of an object is created;
    RENOIR may be used in various areas: architecture design and restoration (both of exterior and interior scenes); objects and devices reconstruction for animators; creation of virtual reality scenes; photomontage scenes creation; advertising.
    Also it can be used as a measuring tool.

      Platforms:
  • Rotor ( David Harvey )
    • Java

    This applet generates solid of rotation from cross-section created with user mouse input. Outputs a Shape block with Extrusion geometry, which may be edited before copying into a VRML source. Good for disks, torus, goblets, vases, and much more.

      Currently Supported Platforms:
      • Any system with a Java interpreter

  • Rover 1.5 ( Flatland )
    • BLOCK

    3DML supports creation of 3D worlds through the stacking of 3D Building Blocks. These building blocks are described in an XML format called BLOCK that is fairly simple to understand. Flatland has released a standalone tool that makes it easy to modify and compile and set of building blocks into a Blockset. A blockset contains a set of BLOCK files plus a style file that names each block + gives it a symbol for use in 3DML.

      Currently Supported Platforms:
      • WIN 95/98/NT

  • ShapeCapture (ShapeQuest)
    • VRML 1.0-VRML97- DFX -OBJ

    The creation of 3D models from images for visualization and virtual reality applications has become very widespread in computer graphics. Approaches in image-based modeling and rendering have been demonstrated widely over the past few years. Also several commercial software packages are now available. However, most of these approaches do not demonstrate high geometric accuracy sufficient for applications other than visualization. ShapeCapture?is a software tool that implements our approach to creating highly accurate 3D models from images.

    • Accurate 3D measurement and modeling
    • Photogrammetric image registration
    • Full camera calibration
    • Outputs accuracy estimates for all measurements
    • Automatic target extraction, matching, and measurement
    • Export 3D coordinates and models to various 3D formats

  • Simple Polygon Reduction
    • OpenGL

    To maintain a good frame rate in 3D interactive programs it often necessary render objects using fewer polygons. Here you will find a simple technique that is fairly fast, and generates reasonably good low-poly models

    with links to
    -A Polygon Reduction Plugin for 3DS Max (with support for texture coordinates).
    -A Polygon Reduction Plugin for Lightwave (by Kasper J. Wessing).

  • Simply 3D 2.0
    • VRML 1.0 VRML 97

    Simply 3D 2 will save its animations as animated GIF files, VRML 1.0 or VRML 2.0 files for the Internet. Users can use Simply 3D inside any OLE 2.0 capable program such as Microsoft Word or PowerPoint. Users can also use it to create stills and animations for multimedia and print (up to 8000 x 8000 pixels). It also comes with over 400 professionally designed 3D objects, 100+ textures, 10 lighting scenes, and 50+ animation primitives in an easy to use drag and drop catalog. Simply 3D 2.0 fully supports Direct 3D and OpenGL acceleration. A free downloadable trial version is available at www.micrografx.com

      Platforms:
      • Windows 95
      • Windows NT
  • SitePad SitePad Pro ( Modelworks Software )
            • VRML 2.0 · Java

    SitePad is an Integrated Development Environment (IDE) for HTML and VRML. Some of its features include support for HTML and VRML files, syntax coloring, the ability to add custom tools using JavaScript and VBScript, syntax Check tool for HTML, VBScript and JavaScript

      Platforms:
      • Windows 95
      • Windows NT
  • Spazz3d Virtock Technologies

    • z-Spazz3D

    VRML 97 -X3D

    It doesn't get much easier. We have taken a complicated task and made it simple. Define the position, rotation, and scale of your geometry at various points along a path. Sensors and Timers can trigger Animations, lights, sounds, and switches. We give you the tools you need to create the world in your imagination.

      • VRML97
      • Shout3D
  • Spotnik Flatland
    • 3DML

    An online tool for the creation of 3DMl spots on a server or on your hard drive.
  • TAXI Web3D without plugins ... lazyhorse
    • JavaScript

    Scene tree structure similar to VRML.
    Intelligent moveable objects like CODE WARS.
    A 3D space for HTML.
    Fully integrated into the Document Object Model ( D.O.M. ).
    Tiny javascript driver ( free )..
  • Toposcopie Annet Groneman
    • various

    Toposcopie is a new photogrammetric tool to make virtual maquettes of existing cities in 1/3 of the time and with the accuracy of land survey. Photo images and a 2D digital map are merged to an interactive 3D system. After the calibration, locations and heights are determined by alternatively clicking on points in the map and an image. The program uses parametric mathematical models of common house types to speed up the building process and to allow modelling of houses that are only partly visible in a photo. The walls of the houses can be mapped automatically with the images used to build the maquette. Roofs can be coloured or mapped automatically with repeating pixel patterns. Trees are added from a library and are placed on turning billboards.

      • exports to many formats including VRML97
    Ulead Face Factory
  • Viewpoint creator ( Robert Walker )
    • VRML 97

    I've written a small program that makes a VRML Viewpoint, given the location of the viewpoint, and a point to look at. It calculates the axis, and the angle to rotate by, something that takes a fair while to do by hand.
    So I think it will be of interest to other VRML developers.
    It is freeware.
    There is another program by Stephen Chenney that does the same thing (mentioned in the FAQs), but this one is a windows app instead of an MSDOS program, which makes it easier to use, with the new viewpoint complete, ready to paste, and changing immediately as you change the numbers. It uses a different mathematical method from Chenney's program, to get the same results.

      Platforms:
      • Windows 95 / 98
  • Vecta3D (IdeaWorks3D)
    • Vectra3D

    Vecta3D is a powerful new tool which lets anyone add amazing vector-based 3D images and animations to their Flash movies. Note this is not a modeling tool in itself.

      Platforms:
      • 3DS Max plug-in
      • Windows (available soon)
      • Mac (available soon)
  • Vera (VRML3d.com)
    • VRML 1.0 - VRML97

    VERA contains the following features:
    1. Creation of VRML-1 models and worlds.
    2. Proprietary animation for VRML-1 worlds.
    3. Exportation of spec-compliant VRML97 for some of the animations.
    4. High quality (ray traced) rendering, including output of animation frames. The frames are saved as both bitmaps (.BMP) and still VRML97 worlds.
    5. Limited editing of static VRML-97 objects.
    7. An open API for those who wish to experiment.
    8. Tools for creating PNG images via the SFImage field...

      Platforms:
      • Windows
    N.B. this software is due to become abandonware(or similar) in April 2001
  • vrmlClass ( Ken Schwarz )
    • VRML 97 - Inventor

    The vrmlClass API is a set of C++ classes which generate models in VRML or Inventor format. Standard VRML browsers, Inventor, or Performer can be used with the API to generate cross-platform 3D imagery.

      Platforms:
      • Portable C++ source code
  • VrmlPad 1.2 ( ParallelGraphics )
    • VRML 97

    VrmlPad is a professional editor for VRML programming. Key timesaving features include: Smart AutoComplete, dynamic errors detection, syntax highlighting, advanced find and replace commands, automation and scripting, keyboard shortcuts customization, etc. VrmlPad offers visual support for the scene tree and document resource operations. In addition, VrmlPad allows the user to preview the scene, organize and optimize it for publishing.

      Platforms:
      • Win 95/98/2000 Win NT
  • VRMLPlot.m ( Dr. Craig Sayers )
    • VRML 97

    VRMLplot.m is a Matlab function for generating interactive 3-D VRML 2.0 graphs and animations. It plots points, surfaces and lines. It can also generate animations of articulated structures such as robots and vehicles. To run VRMLplot you'll need a copy of Matlab. To view the output files, you'll need a VRML 2.0 compatible browser/plug-in. VRMLplot.m is available free of charge.

      Platforms:
      • Matlab source code
  • WinPlace Gary Beene
    • VRML 97

    WinPlace is a freeware application which allows creation of 2D and 3D models. The models are built within a 2D design interface and viewed real-time with the built-in 3D (VRML) viewer..

      Platforms:
      • VRML
  • Writing a VRML Modeler in DHTML JavaScript antar@softdom.com
    • VRML 1.0

    article on using a combination of DHTML and VRML to create basic 3D shapes in an interactive application for the web.

      Platforms:
      • Java script - DHTML
  • wrlgrid ( John Moreland, San Diego Supercomputer Center )
    • VRML 1.0

    wrlgrid outputs a colored, regular or warped grid of line sets or face sets. This can be used to generate base grids for scientific visualizations, or to form grout lines for floor-tiled areas of virtual environments. In the latter case, we've found that the addition of grout lines helps create a sense of depth and provides a size-comparison visual cue that makes virtual environments seem more real.

      Platforms:
      • Perl source code
  • X3D-Edit
    • VRML 97 - X3D

    X3D-Edit is a graphics file editor for Extensible 3D (X3D) that enables simple error-free editing, authoring and validation of X3D or VRML scene-graph files. X3D-Edit uses the XML tagset defined by the X3D Document Type Definition (DTD) in combination with Sun's Java, IBM's Xeena XML editor, and an editor profile configuration file.

    • Platforms:
      • Windows 95, 98, NT and 2000
  • X3D-SAI
    • X3D

    The X3D Scene Authoring Interface (SAI) is an application programming interface (API) for the X3D scene graph.
    SAI scripts will work for Script nodes inside the scene, external applets outside the scene in a Web page, Java and EcmaScript (i.e. JavaScript), and for language-independent scripting via XML's Document Object Model (DOM). SAI profiles for GeoVRML, H-Anim, DIS-Java-VRML and NURBS are included.

    • Platforms:
      • Java
    z-Spazz3D Virtock Technologies, Inc. VRML所见即所得编辑器，支持X3d； z-Spazz3D支持VRML97的曲面建模方式。并且可像在3dmax那样使用摄像镜头。


JPEG

JPEG 2000

JPEG 全名为 Joint Photographic Experts Group，它是一个在国际标准组织(ISO)下从事静态影像压缩标准制定的委员会。它制定出了第一套国标静态影像压缩标准：ISO 10918-1 就是我们俗称的 JPEG 了。

JPEG 2000， 正式名称为 "ISO 15444" ，同样是由JPEG 组织负责制定。自1997年三月开始筹划，但这几年间，在算法选取问题上耽误了不少时间，人们普遍预计要到2000年十二月 JPEG2000才能制定完成!，但在今年 3 月的东京的一个会议上，可能是由于数字照相机厂商们施加压力，规定基本编码系统的最终协议草案提前出台，终于不用改名为 JPEG2001 了。标准既然已经定了，那么相对的应用软件就很快就出来了。现在是 8 月，我已经找到几套这样的软件了，在介绍它们之前，我们先看看 JPEG2000 的原理、优点、应用。

JPEG2000的原理： JPEG 2000 与传统 JPEG 最大的不同，在于它放弃了 JPEG 所采用的以离散馀弦转换(Discrete Cosine Transform) 为主的区块编码方式，而改采以小波转换(Wavelet transform) 为主的多解析编码方式。小波转换的主要目的是要将影像的频率成分抽取出来。

JPEG2000的优点：

1、JPEG2000 作为JPEG升级版，高压缩（低比特速率）是其目标，其压缩率比 JPEG 高约 30% 左右。

2、JPEG2000 同时支持有损和无损压缩，而 JPEG 只能支持有损压缩。无损压缩对保存一些重要图片十分有用。

3、JPEG2000 能实现渐进传输，这是JPEG2000的一个极其重要的特征。也就是我们对 GIF 格式影像常说的“渐现”特性。它先传输图像的轮廓，然后逐步传输数据，不断提高图像质量，让图象由朦胧到清晰显示，而不必是像现在的 JPEG 一样，由上到下慢慢显示。

4、JPEG2000 支持所谓的“感兴趣区域”特性，你可以任意指定影像上你感兴趣区域的压缩质量，还可以选择指定的部份先解压缩。这样我们就可以很方便的突出重点了。

JPEG2000的应用： JPEG 2000的应用领域可概略分成两部分，

一为传统JPEG的市场，像印表机，扫描器，数位相机等，

一为新兴应用领域，像网路传输，无线通讯，医疗影像等。

目前对 JPEG 2000 热情最大的当然就是那些数字照相机厂商。JPEG 2000 和 JPEG 相比优势明显，且向下兼容，因此取代传统的JPEG格式指日可待。


JPEG 2000


Opengl

MS Opengl
OpenGL
Learn the hows and whys of this industry open standard for high-performance graphics.
http://www.opengl.org/

Nate Robins - OpenGL
Learn more about the OpenGL standard through this index of various tutorials, personal notes taken from seminars and links to related projects.
http://www.xmission.com/~nate/opengl.html

Silicon Graphics - OpenGL
Foundation for high performance graphics programming language. Includes technical resources, FAQs, and list of programming courses.
http://www.sgi.com/software/opengl/

eMediaWeekly - OpenGL to Revive Mac 3D
Read about the possible implications of Apple Inc. acquiring Conix code in FindArticles January 1999 report. Includes integration concerns.
http://www.findarticles.com/cf_dls/m0HBJ/1999_Jan_25/53661877/p1/article.jhtml

Apple - Software Updates for OpenGL 1.0
Download Apple's OpenGL 1.0 to help Mac OS 8.6 run smoothly. Find installation instructions and links to support.
http://asu.info.apple.com/swupdates.nsf/artnum/n11420

OpenGL 1.1 Reference
Presents a list of OpenGL functions in alphabetical order, indicating what type of function it is and providing individual overviews.
http://www.hp.com/unixwork/products/grfx/OpenGL/Web/RefTOC.html

Deus Ex - Deus Ex Tweaking Guide
Guide offers advice on tweaks that work with Direct3D and OpenGL for Deus Ex.
http://www.hal-pc.org/~mikromak/deusexguide/deusexguide.html

3DTop
Take a look at a Windows shell replacement supporting an added visual dimension, for contrasting desktop icons. Check supported OpenGL hardware.
http://www.3dtop.com/

AlteredWorlds
OpenGL 3D screensaver action game can be previewed via eight .mpg movies. Windows and Linux users may download installation and library files.
http://www.alteredworlds.com/

Best 3D Video Card
Supplies computer users with gaming and data-protection hardware, including OpenGL 3D video cards and RAID cards for system crashes.
http://www.best3Dvideocard.com/

FOX
C++ based toolkit for developing graphical user interfaces with OpenGL widgets and 3D graphical manipulation. Free ftp download available.
http://cyberia.cfdrc.com/FOX/fox.html

3Dscreensaver.com
Browse and download screensavers for Direct3D, 3dfx-Glide, OpenGL and DirectX. Order a personalized 3D screensaver or submit one to the database.
http://www.3dscreensaver.com/

WebCubed 3D Education
Delivers courses in web design, open development, VRML and OpenGL.
http://www.webcubed.com/

C-Scene
Free e-zine on C and C++ programming posts all issues produced, each consisting of articles by developers. Learn more about debugging and OpenGL.
http://www.cscene.org/

Mesa 3D Graphics Library
Free 3D graphics documentation and source code which use SGI's OpenGL API. Works on most X systems, Windows, and Macs.
http://www.mesa3d.org/

ICBM3D/2
Stands for Inter-Continental Ballistic Missiles 3D II and its offered free from Newbreed Software for X-Windows using OpenGL.
http://www.newbreedsoftware.com/icbm3d2/

C++ Builder Programmer's Ring - Webring
Group of sites founded mainly by developers covers issues such as applications, Windows API, and OpenGL. Receive project advice.
http://www.webring.org/cgi-bin/webring?ring=cbuilder&list

Mg^2
3D modeler, formerly called Mod, for X11 using Gtk, Glib, Imlib, Gtk glarea and Mesa/OpenGL. Includes comics, screenshots and music.
http://www.op.net/~finklesk/3d.html

GLmame
Features the OpenGL and glide (3Dfx) display driver for the xmame arcade game emulator. Provides screenshots, specs and downloads.
http://glmame.linuxgames.com/

GLView
Offers evaluation versions of the commercial scientific program which uses OpenGL on Unix or Windows NT/95.
http://www.viewtech.no/

Kyriazis, George
Meet George who works on OpenGL. Find his photographs and details on his friends.
http://reality.sgi.com/kyriazis/

mHockey
OpenGL based hockey game released under the GPL includes such features as skeletal animated 3D players and a "halfway decent" AI system.
http://www.linuxgames.com/mhockey/

RivaZone.com
FAQs cover device cooling and OpenGL rendering, while hardware reviews include tweaking tips. Note developer conference dates for these issues.
http://www.rivazone.com/

SGIGL
SGI OpenGL1.1 for Win95/98/NT。


SVG

S V G（Scalable Vector Graphics，可缩放矢量图形）

SVG 其实是一种开放标准的矢量图形描述语言。使用 SVG ，可以在网页上显示出各种各样的高质量的矢量图形，支持很多您想象得出的功能：几何图形、动画、渐变色、滤镜效果等——最关键的是：它是完全是用普通文本来描述的！也就是说：这是一种专门为网络而设计的基于文本的图像格式。

SVG是一种可缩放、可查询、与平台无关、基于文本的图形格式。SVG矢量文件无论在Web制作上、出版印刷、还是其他方面都可提供打印高品质的图形。与其他许多基于打印的矢量图形技术产品（如Adobe的 Encapsulated PostScript，即EPS格式）的不同之处在于，它是基于开放的XML（Extensible Markup Language，可扩展的标签语言）标准。作为一个开放的标准，SVG不属于任何公司，它是工业界先驱们同心合作的产物。它不是凭空制造出来的，而是集成了几种标准和建议的结果，如微软的VML (矢量标签语言)，Adobe 基于EPS的 PGML (精度图形标签语言)等。这些厂商都是业内知名的企业：包括Adobe、Apple、Autodesk、BitFlash、Corel、HP、IBM、ILOG、INSO、Macromedia、Microsoft、Netscape、OASIS、Open Text、Quark、RAL (CCLRC)、Sun、Visio、Xerox等。他们也纷纷推出了自己开发的相应的浏览软件和插件。而且他们的很多主流产品也都开始支持 SVG 输入或者输出。

（１）基于XML标准 　　XML是公认的下一代网络标记语言，拥有无穷的生命力。SVG 则是在最开始设计的时候就基于 XML，这使得它具有一种先天的优势，并且同HTML、CSS、DOM、XSL、JavaScript、CGI一样，成为新的标准。

（２）高质量的图像 　　由于基于矢量，使得图像的质量得到大大的提高。放大、缩小以及各种特效都比位图的表现要好，在打印的时候，完全可以以印刷质量输出图片。

（３）灵活易用的文件格式 　　SVG 主要由３个部分组成：矢量图形、位图和文字。而由于文件格式是文本的，那么更改起来是非常方便的，在页面运行的过程中，我们也可以对很多部分做修改。而其中的图形描述可以被任何人重复的使用。

（４）支持交互 　　由于支持SMIL（synchronized multimedia integration language），用户可以自由的同 SVG 中的元素完成一些交互的动作，从而完成既定的目标，这一点是目前的图片所完成不了的。

（５）文本就是文本 　　现在，您将有机会查找“图片”中的字符，是不是很不可思议呢？

（６）其它 　　可以内嵌字体、图片；众多开发工具支持；可以轻易的同网页上的脚本做交互；文件相对来说，相当小……等等。

SVG的优势

利用SVG可让你设计激动人心的、精彩缤纷的高分辨率Web图形页面。如果你感到无法理解，不妨回忆一下完全基于Flash技术的网站带给你的视觉冲击。借助相关的软件工具，可以实现渐变、嵌入字体、透明效果、动画和滤镜等效果，并且可使用标准HTML命令将图形命令插入到HTML和XML编码中。

这里谈到了大家不太熟悉的XML，暂不多谈。大家只要知道，现在从Web业界到开发商都开始对XML进行广泛而热烈的支持这个事实即可。所有与XML相关的技术都成为热门话题，继承了XML所有优势的SVG也因此倍受瞩目。与我们熟悉的HTML不同的是，XML将内容完全从显示中分离出来。通过在结构数据类型方面的描述，用户程序可以同时处理XML页面的显示或数据，而不仅仅像HTML那样只是单纯地显示内容。SVG继承了XML所提供的更好的结构方面的控制，功能更为丰富。SVG是完全基于XML的。

用SVG画一个圆
如果你了解XML语言，理解SVG 将非常容易。SVG利用“样式”来定义图形的显示方式。我们先来看一个简单的例子，它的功能是画一个圆。
XML代码如下:
<?xml version="1.0" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 20000303 Stylable//EN"
" svg-20000303-stylable.dtd ">
<svg width="200" height="200">
<circle style="stroke:#000000; stroke-width:3; stroke-opacity:1;
fill:#ff0000; fill-opacity:1" cx="104" cy="101" r="80"
transform="matrix(1 0 0 1 -4 -1)" />
</svg>

    这段代码首先声明本文件是XML文件，接着是DTD (文件类型定义)，接着是<svg> 标签、文件的根元素，在它之间的是图形和文本标签。这里是 <circle>标签，说明画一个圆。属性有“style”和“transform”。“style”属性定义的是图形的大小和颜色，而 “transform”属性则定义了作图区的范围。
也许你会说这个例子太简单了。但考虑以下的事实，画一个类似的图形JPEG格式需占用约4K字节，而XML的代码只有444字节，只是前者的十分之一。另外，放大和缩小SVG图形不会影响它的显示效果。如果你有XML开发工具，还可以像产生其他XML文件一样通过编程产生SVG文件。
现在介绍一个更复杂的例子：
<?xml version="1.0" standalone="no"?>
<!DOCTYPE svg SYSTEM "svg-20000303-stylable.dtd" >
<svg width="500" height="250">
<desc>Chip Logo</desc>
<g transform="matrix(1.30132 0 0 0.597561 -232.581 22.6341)">
</g>
<text style="font-size:43; font-family:Arial Black; fill:#000080; fill-opacity:1" transform="matrix(1.19431 0 0 1.09428 158.607 112.951)">CHIP</text>
<path style="fill:#000000; fill-opacity:1" d="M 368 25 c 36 39 29 68 32 93 C 384 76 381 55 355 39 313 13 254 14 254 14 c 0 0 73 -15 113 11 z" transform="matrix(-0.677324 0.444894 0.608862 0.00421806 358.382 -75.5501)" />
<path style="fill:#008080; fill-opacity:1" d="M 378 36 c 41 28 33 95 33 95 0 0 0 -56 -42 -83 C 327 21 237 25 237 25 237 25 336 7 378 36 z" transform="matrix(-0.0236587 -0.51162 0.488666 0.396378 108.924 293.155)" />
<text style="font-size:44; font-family:Arial Black; fill:#800000; fill-opacity:1" transform="matrix(1 0 0 1 152 149)">CHINA</text>
<text style="font-size:20; font-family:Arial Italic; fill:#808080; fill-opacity:1" transform="matrix(0.99996 -0.00899489 0.00899489 0.99996 145.041 167.962)">www.Chip-China.com</text>
</svg>

在此个例子中包括了分组、自定义图形及伸缩。这个例子显得十分复杂，徒手设计这个SVG图形当然会很困难。人们需要某种图形设计工具来完成如此复杂的设计，可预见这个市场又会产生激烈的争夺。但无论结局如何，对Web 设计师都将是个福音。

不过，需要注意的是，提倡使用SVG的主要原因并非是文件大小，不是在所有的情况下SVG都能赢得 “小文件”的优势的。通常色彩丰富、边界规则且幅面较大的图形会使SVG构成的图形文件大小令人满意，而色彩单一的小幅面图形或照片之类的东西就不一定了。

SVG 技术给Web世界带来了新的图形表示能力。它可以创建静态的图形或图表、可伸缩的地图以及拥有动画功能的演示节目。SVG技术构成的图形可以完满地显示在各种电脑、PDA或手机设备上。SVG 很有可能引起印刷出版界的一场新的革命，它可以提供从数字到打印、印刷模式的无缝转换，这预示着SVG必将取代现存的专有格式。如果你是一位现代技术的追随者，就请耐心期待吧，很快就能见到SVG变革整个互联网时代的到来。如果你是一个网络技术人员，请多关注SVG技术的最新发展吧，也许它是你成功的起点。
在应用于Web方面，基于文字的SVG与传统矢量技术相比，也有着许多先天的优势：
1. 一个SVG图像是由基于XML的文字命令表述的，可以和JavaScript或 XML完全一致，它是非常精炼的编码。
2. 作为基于文字的格式，在SVG图像内的文字可以让用户通过搜索引擎在浏览器内进行搜索。
3. SVG也可以通过JavaScript、Perl、或Java等描述语言动态创建。
4. SVG 完全支持 DOM (Document Object Model) ，因而是完全可编写的。SVG图像或其部分都可以对鼠标点击或移动给出反应，引发图形本身的变化或链接到其他HTML页面或图形上。
5. SVG针对不同的平台、不同的输出分辨率、不同的颜色空间、不同的带宽等，都能很好地工作。

SVG相关链接

万维网联合委员会之SVG 标准：http://www.w3.org/TR/SVG/
SVG 技术：http://www.pinkjuice.com/SVG/
Adobe SVG相关内容：http://www.adobe.com/svg/
Sun Microsystem公司SVG开发参考：http://www.sun.com/software/xml/developers/svg/

CHIP新电脑 http://www.chip-china.com/

http://www.yesky.com
SVG和其他W3C标准的关系

W3C作为一个国际的工业联盟，通过开发共同的协议，促进革新和保证相互的操作性，领导World Wide Web，将其潜能发挥到最大。为了保证在Web上的一致性和平衡性， W3C已经设计了SVG和其本身的成果(DOM1、 DOM2、 CSS、 XML、 XPointer、 XSLT、 XSL、 SMIL、 HTML、和 XHTML)兼容并和其他的标准技术(ICC、 URI、 UNICODE、 sRGB、 ECMAScript/JavaScript、和Java)同样兼容。
DOM

DOM是Document Object Model（文件物体模式）的首字母缩写。DOM是一个平台和语言中性的界面，允许程序和命令语言动态地访问和升级内容、结构和文件格式。SVG的 DOM允许通过命令语言直截了当和高效地产生矢量图形动画。类似OnMouseOver和OnClick的大量的event handlers（事件句柄）可分配给任何SVG图形物体。SVG具有和其他Web标准的兼容性和平衡性，例如scripting（描述，一个SVG特性〕这样的特性可在同一个Web页面内同时影响HTML和SVG元素。
SVG创作工具

目前的SVG创作工具还处于开发和研制阶段,仍然没有一款非常成熟的包含静态,动态,交互功能创作的软件.这里介绍几个目前可以进行一些研究和测试的SVG创作软件.

Adobe Illustator
Adobe在SVG的开发中扮演了重要角色.Adobe Illustrator 9.0是较早的一款结合SVG功能的矢量创作软件.目前可以进行静态图形的创作和部分交互功能的实现.其交互功能需要手写javascript脚本.创作AI图像后,选择File->Export(文件->输出),选择文件类型SVG,在SVG Option面板中设置相关属性,可以输出SVG文件,关于属性设置,请参看<<SVG中文教程>>.
Web Draw

WebDraw是Jasc Software按照W3C组织制定的SVG规范书开发的矢量图像和动画制作工具,专业应用于SVG创作.WebDraw通过直接画布拖拽绘图以及滤镜效果模块化组合,可以避免手写源代码.同时提供源代码视图窗口,支持后续源代码编辑和修改.

软件的整体布局类似于目前许多的图形创作软件.与职业的矢量创作软件Adobe Illustrator和Corel Draw相比较,Web Draw在功能上还不足以抗衡,但作为专业开发SVG的创作工具,也许可以预想,经过一段时间的积累,它将成为下一个成功的Fireworks.(Fireworks成功的开发了PNG格式.)

最新版本是Preview Release 4.目前还不支持动态SVG效果.另外, 应用滤镜效果并不能在画布真实表达输出后的SVG图像.

下载(4.45M):
http://www.jasc.com/webdraw.asp (国外)
http://www.2svg.com (国内)

Web Engine

IMS Web Engine (Interactive Multimedia System)是Virtural Mechanics开发的一款网页创作软件,主要应用于创作静态和动态的HTML,DHTML和SVG页面.Web Engine是目前极少数不需要通过手写代码即可完成SVG动态交互创作的工具.它的精灵向导可以很快的定义简单的交互动作.

Web Engine的界面比较粗旷,或者说不是很精细,很多操作是双击对象弹出面板,调整选项,这有点像当时的Flash3.0和4.0.Web Engine有一个比较不足的地方,给设计者带来很大的限制,就是没有提供源代码视图,无法直接进行源代码的修改和编辑.
目前的版本是 Version 2 Beta.

下载(3.86M):
http://www.virtualmechanics.com(国外)
http://www.2svg.com (国内)


基础技术

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网络多媒体-3D与虚拟现实技术
基础技术
应用产品
OpenGL
Java3D (1-10), (11-13), (14-16), (17-20)
DirectX/Direct3D
SVG
VRML (1), (2)

X3D

3DML
<


X3D

X3D-Edit for Extensible 3D (X3D) Graphics

http://www.web3D.org/TaskGroups/x3d/translation/README.X3D-Edit.html
X3D-Edit is being used to develop and test the Extensible 3D (X3D) tagset for the next-generation Virtual Reality Modeling Language (VRML 200x). X3D-Edit also exercises various X3D graphics rendering and translation implementations.


Programming

Solaires provides clients' websites with interactive, database-driven programming using the state-of-the-art technologies, like:

            • CGI (perl,shell),
            • php,
            • c,c++,
            • VBScript,
            • JavaScript,
            • ActiveX,
            • ASP,
            • JSP/Servlet,
            • EJB/CORBA,
            • middlewar,
            • XML/XSLT/Schema/Namespace,
            • WAP/WML/WMLScript,
            • VRML
            • 3D
            • ...

时力为客户的交互，动态的电子商务网站构建数据库驱动的网络应用，采用当今最新的技术，根据拥护需要从以下技术中进行选择：

  • CGI (perl,shell),
  • php,
  • c,c++,
  • VBScript,
  • JavaScript,
  • ActiveX,
  • ASP,
  • JSP/Servlet,
  • EJB/CORBA,
  • 中间件，
  • 应用服务模块，
  • XML/XSLT/Schema/Namespace,
  • WAP/WML/WMLScript,
  • VRML
  • 3D
  • ...

等构建在 Internet/TCP IP 上的应用编程。

General
Bogislafski Основы программирования p119.pdf
Course8Ηλεκτρονικ? Επιχειρε?ν p27.pdf
iouniou_programmatismos2012_13 p11.pdf
Joyanizis linear-programming p149.pdf
Magos Algorimso p10.pdf
PROGRAMMATISMOS SUSTHMATOS p185.pdf
Γαβι?τη? - Τεχνολογ?ε? & Μεθοδολογ?ε? Προγραμματισμο? p20.pdf
ΣακελλαρYYY Γλ?σσε? Προγραμματισμο? Μεταγλωττιστ?? p39.pdf

Assembly/

Blum Professional Assembly Language p577.pdf

Duntemann Assembly Language step by step p469.pdf

Hyde 汇编语言编程艺术清晰版 p794.pdf

MASM_Programmers_Guide.chm

Wang 汇编语言_第2版 p351.pdf

杨季文 80x86 汇编语言程序设计教程 p540.pdf

汇编语言教程.chm

RadAsm指南/

masmhelp/

汇编指令查询器 v1.2/

C/C++

ANCADZZZ Quicck Staart MATFOR In C++ p47.pdf
AppleZZZ The Objective-C Programming Language p240.pdf
AroraZZZ C++ Programming Basics p124.pdf
BellZZZ C++ Programming for Physicists p34.pdf
BogislafskiZZZ Основы программирования p119.pdf
BrainZZZ Understanding Cpp An Accelerated Introduction p63.pdf
breymannZZZ_Objektorientierte Programmierung mit C++ p451.pdf
breymann_Objektorientierte Programmierung mit C++ p451.pdf
BurgessZZZ The GNU C programming p290.pdf
BurgessZZZ The GNU C Programming Tutorial p272.pdf
DaithankarZZZ Tutorial For_C and CPP_Programming On Linux_p18.pdf
DodrillZZz C Language Tutorial p124.pdf
FleuretZZZ__C++_Lecture_Notes p146.pdf
Galub Правила программирования на Си и Си++ p241.pdf
GalubZZZ Правила программирования на Си и Си++ p241.pdf
GoughZZZ Programming in C p85.pdf
GoughZZZ Programming in C++ p53.pdf
HarbisonZZZ C A Reference Manual 5th Ed p551.pdf
HaskinsZZZ c-programming-in-linux p84.pdf
HillegassZZZ Objective-C Programming p256.pdf
JesshopeZZZ-utc an intermediate language for programming.pdf
JoyanizisZZZ linear-programming p149.pdf
Kernigan Язык программирования Си p253.pdf
KerniganZZZ Язык программирования Си p253.pdf
KernighanZZZ C_Programming_Lang p205.pdf
KernighanZZZ The C Programming Language p217.pdf
KernighanZZZ The C Programming Languagep318.pdf
KernighanZZZ The_C_Programming_Language p295.pdf
KlotzZZZ C for Embedded Systems Programming p67.pdf
KriemannZZZ C++ for Scientific Computing p320.pdf
kulakov-Программирование на языке Си p44.pdf
kulakovZZZ-Программирование на языке Си p44.pdf
LindenZZZ_Expert_C_Programming__Deep_C_Secrets p290.pdf
MachanickZZZ C_C++_in 5 Days p61.pdf
MALIK C++ Programming From Problem Analysis to Program Design p1392.pdf

MALIK, D.S.: C++ PROGRAMMING: FROM PROBLEM ANALYSIS TO PROGRAM DESIGN, FIFTH EDITION, 2011 Course Technology .......p1392

MilesZZZ Introduction to C Programming p94.pdf
OSCZZZ Introduction to the C Programming Language p188.pdf
OuallineZZZ Practical C++ Programming 1995 p549.pdf
OuallineZZZ Practical C++ Programming p549.pdf
OuallineZZZ 实用C++编程大全 p535.pdf
PardueZZZ C Programming for Microcontrollers p300.pdf
ParlanteZZZ Essential C p45.pdf
PodrazaZZZ The C Programming Language p43.pdf
SchildtZZZ C++Complete Reference p1041.pdf

Schildt, Herbert: C++: The Complete Reference, Third Edition, McGraw-Hill, 1998 ????????p1041

SoulieeZZZZZZZ C++ Language Tutorial p144.pdf
StroustrupZZZ The CPP Programming. Language p1022.pdf

Stroustrup, Bjarne: The C+ + Programming Language, Third Edition, AddisonWesley, 1997 ? p1022
SunZZZ C++ Programming Guide p104.pdf
TerrelZZZ C++ Programming Basics p253.pdf
VasudevanXXX C++ Programming HOW?TO p62.pdf
WikibooksZZZ C Programming_Print version p129.pdf
WikibooksZZZ C_Programming p271.pdf
ZZZPROGRAMMATISMOS SUSTHMATOS p185.pdf
宋劲杉ZZZ Linux C编程一站式学习 p674.pdf
徐晓鸣ZZZ C++语言程序设计.ppt

Davis C++ For DUMMIES p435.pdf
Downey How to think like a computer scientist p189.pdf
Halterman Fundamentals of Programming C++ p647.pdf
Hekmat C++ Essentials p311.pdf
Jones The New C Standard p1612.pdf
Kernighan The C programming Language p295.pdf
Kirch-Prinz A Complete Guide to Programming in C++ p846.pdf
Oualline Practical C++ Programming p549.pdf
PERENS C++ GUI Programming with QT3 p464.pdf
Perforce CC++ API User Guide p330.pdf
Rasheed C# School p338.pdf
Ronkko C++ tutorial for C users p100.pdf
Soulié C++ Language Tutorial p144.pdf
Valsamma C PROGRAMMING FOR MATHEMATICAL COMPUTING p152.pdf
Vasudevan C++Programming HOW-TO p59.pdf
Wiegand Teach Yourself C++ in 21 Days p772.pdf
codes/
cplusplus.com Complete C++ language tutorial p187.pdf
eclipsews/
宋劲杉 Linux+C+编程一站式学习 p697.pdf

================================

SystemC

http://www.systemc.org/

SystemC is a system based on C++ that is widely used to simulate architectures.

It is a library of C++ classes, global functions, data types and a simulation kernel that can be used for creating simulators for hardware.

By using C/C++ development tools and the SystemC library executable specifications of a model can be created in order to simulate, validate, and optimize the system being designed. An executable specification is essentially a C++ program that exhibits the same behavior as the system when executed.

Synopsys SystemC UserGuide p212 2002

de GraafZZZ SystemC-AMS Analog & Mixed-Signal System Design p89.pdf
EsperanZZZ SystemC_tutorial p16.pdf
JesshopeChrisZZZ SystemC Tutorial p11.pdf
MoondanosZZZ SystemC Tutorial p48.pdf
MosaffaZZZ SystemC System-Level Modeling p46.ppt
msdlZZZ System C by Microsoft Visual C++ p8.pdf
RuggieroZZZ SystemC p36.pdf
SynopsysZZZ Describing Synthesizable RTL in SystemC p116.pdf
SynopsysZZZ SystemC UserGuide p212.pdf
VelosoZZZ SystemC Tutorial p38.ppt
ZoltanZZZ System Level Design SystemC p45.pdf
ZZZModeling and Simulation with SystemC p16.pdf

================================

SystemC AMS

================================

c-shell

================================

Fortran
Adams Fortran 90 Handbook p835.pdf

Java
Allimant The Java tutorial.chm
Jendrock j2ee-tutorial.chm

PHP
Achour php52_manual_en.chm
php2013-10-31_enhanced_en.chm
php2013-10-31_manual_en.chm
php_manual_en.tar
php_manual_en.tar.gz
php_manual_en560.chm

Python

<DIR> Rossum Python Tutorial
Andrew Hands-On Python p113.pdf
Downey Think Python p234.pdf
Downey Think Python p240.pdf
Gouillart python_scientific_tutorial p139.pdf
PyScripter.chm
python273.chm
PyWin32.chm
ZZZPython 2.1 Quick Reference p54.pdf
ZZZPython 2.4 Quick Reference Card.pdf

Hetland Python基础教程第2版.pdf
PyScripter.chm
UN_Hetland Python基础教程第2版.pdf
python273.chm
python325.chm

Wing IDE doc/

Perl
foy Perl语言入门第四版 p201.pdf
Hall Perl高效编程.(第2版) p333.pdf
optiperl.chm
Pleditor.chm
Schwartz Learning Perl 3rd Ed p259.pdf
Schwartz learning_perl 2nd ed p454.pdf
Schwartz Perl语言入门 5th ed CN p343.pdf

perl

================================

tcl

=========================

Delphi/

DelphiHelper20/

DelphiProgrammingHelper/

Delphi好帮手/

Delphi编程技巧/

learndelphi/

huanghw DELPHI编程手册 p6022.pdf
刘啸 Delphi高级编程 p376.pdf
李文池 Delphi程序设计基础 p392.pdf
金石通工作室安世伟 编程魔法师DELPHI 入门实战百例 p297.pdf

================================

Rosetta programming

Program0.doc
Program1.doc
Program2.doc


IT technologies related to chip research, development, design, fabrication and applications.

Programming Languages

C/C++

MALIK, D.S.: C++ PROGRAMMING: FROM PROBLEM ANALYSIS TO PROGRAM DESIGN, FIFTH EDITION, 2011 Course Technology .......p1392

Schildt, Herbert: C++: The Complete Reference, Third Edition, McGraw-Hill, 1998 ????????p1041

Stroustrup, Bjarne: The C+ + Programming Language, Third Edition, AddisonWesley, 1997 ? p1022

================================

SystemC

http://www.systemc.org/

SystemC is a system based on C++ that is widely used to simulate architectures.

It is a library of C++ classes, global functions, data types and a simulation kernel that can be used for creating simulators for hardware.

By using C/C++ development tools and the SystemC library executable specifications of a model can be created in order to simulate, validate, and optimize the system being designed. An executable specification is essentially a C++ program that exhibits the same behavior as the system when executed.

Synopsys SystemC UserGuide p212 2002

================================

SystemC AMS

================================

c-shell

================================

perl

================================

tcl

=========================

HDL

Hardware Description Languages

=======================

VHDL

VHDL is a hardware description language. It describes the behavior of an electronic circuit or system, from which the physical circuit or system can then be attained (implemented).

VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an abbreviation for Very High Speed Integrated Circuits, an initiative funded by the United States Department of Defense in the 1980s that led to the creation of VHDL.

Its ?rst version was VHDL 87, later upgraded to the so-called VHDL 93. VHDL was the original and ?rst hardware description language to be standardized by the Institute of Electrical and Electronics Engineers, through the IEEE 1076 standard. An additional standard, the IEEE 1164, was later added to introduce a multi-valued logic system.

VHDL is intended for circuit??synthesis? as well as circuit?simulation. However, though VHDL is fully simulatable, not all constructs are synthesizable. We will give emphasis to those that are.

A fundamental motivation to use VHDL (or its competitor, Verilog) is that VHDL is a standard, technology/vendor independent language, and is therefore portable and reusable. The two main immediate applications of VHDL are in the ?eld of Programmable Logic Devices (including CPLDs—Complex Programmable Logic Devices and FPGAs—Field Programmable Gate Arrays) and in the ?eld of ASICs (Application Speci?c Integrated Circuits). Once the VHDL code has been written, it can be used either to implement the circuit in a programmable device (from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication of an ASIC chip. Currently, many complex commercial chips (microcontrollers, for example) are designed using such an approach.

A ?nal note regarding VHDL is that, contrary to regular computer programs which are sequential, its statements are inherently??? concurrent?? (parallel). For that reason, VHDL is usually referred to as a??code? rather than a program. In VHDL, only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.

Ashenden, Peter J.: VHDL Quick Start, p42, 1998

Ashenden, Peter J.: VHDL Tutorial, Elsevier Science (USA), 2004, p 84

Cooper, Scott: Introduction To The VHDL-AMD Modeling Language, 13 November 2007, p102

Díaz-Pérez, Arturo: An Introduction to the Digital Design Process, p22 Sept 2008

Doulos Vhdl_Golden_Reference_Guide, Version 1.1, December 1995, p136

Essential VHDL, 2006-01-12, P20

Khalifa, Yaser: Introduction to VHDL,? p108 2003-9-17

Macchett Introduction to the VHDL language p94

Turner, Jon: Using VHDL to Design Digital Circuits – Part 1, p19, Sept 2012

VHDL-Handbook p76 April 2006 HARDI Electronics AB

=================================

VHDL-AMD Modeling Language

=================================

VHDL-AMS

AMS => Analog / Mixed Signal Extensions

=================================

VeriLog

Open Verilog International (OVI)

www.esperan.com

Verilog-XL simulator

Cantrell, Joshua: Verilog Tutorial .p5 ...Oct 2000

Doulos The Verilog? Golden Reference Guide Version 1.0, August 1996 p151 ............14

Qualis Verilog HDL QUICK REFERENCE CARD

MPl TKK Verilog p22 5.10.1999

==============================================

Verilog-A

==============================================

Verilog-A/MS - Verilog-AMS

==============================================

SystemVerilog

=============================

Spice

=============================

schematics

=============================

EDIF (netlists)

=============================

GDS, CIF (masks)

=========================

Logic Programming and Constraint Logic Programming

Some of the current CLP languages and their domains are:

  • Prolog III
  • Prolog IV—trees, reals, intervals, rationals, finite domains (including Booleans), strings
  • CLP(BNR)—trees, intervals
  • CLP(R)—trees, floating-point arithmetic
  • CHIP—trees, floating-point arithmetic, finite domains
  • CAL
  • CHARME
  • Chleo/Chlare

Constraint Satisfaction Problem

Node and arc consistency

General backtracking algorithm

  • Generate and Test (GT)
  • Standard Backtracking (SB)
  • Forward Checking (FC)
  • Look Ahead (LA)

Comparison on the queen example

=============================

ProLog

  • Edinburgh Prolog
  • SWI-Prolog
  • Quintus Prolog
  • Visual Prolog www.pdc.dk
  • BIM Prolog
  • Beta-ProLog
  • SICStus Prolog

Blackburn, Patrick et al: Learn Prolog Now 2001 p184

Bramer, Max: Logic Programming with Prolog Springer 2005 p228 .................... 6

Brna, Paul: Prolog programming p193 Jan 2001

Costat, Eduardo: Visual Prolog 7.2 for Tyros, 2009 p252

de Boer, Thomas W.: A Beginners Guide to Visual Prolog, Version 7.2, 2009, p281

ISL(Intelligent Systems Laboratory): SICStus Prolog Users Manual, June 2002 p774

Lu, James and Mead, Jerud J.: Prolog A Tutorial Introduction p42 May 2003

Simonis, Helmut: Constraint Logic Programming p37 ..............27/02/2008

Wielemaker, Jan: SWI-Prolog 5.6 Reference Manual Updated for version 5.6.32, March 2007

=============================

Symbolic Languages

Macsyma

Maple

Mathematica

Matlab

Ptolemy

=============================

Unified Modeling Language（UML）

Booch, Grady et al: The Unified Modeling Language User Guide Addison Wesley First Edition October 20, 1998 p390 .

Colbert, Edward: Introduction to the Unified Modeling Language (UML) Sept 2001 p258

================================

Rosetta programming

Computer Hardware, Operation Systems

Kernel

Bovet, Daniel P.: Understanding the Linux Kernel 3rd Edition, O'Reilly, November 2005

3.4. Creating Processes

the Free Software Foundation: The Linux Kernel API, 2008.

Kroah-Hartman, Greg: LINUX KERNEL IN A NUTSHELL, O’Reilly, 2006.

Love, Robert: Linux Kernel Development, 2nd edition, Pearson, 2005

Mauerer, Wolfgang: Professional Linux kernel architecture, Wiley Publishing, Inc., 2008 .....p1370 ...... 199

Pomerantz, Ori: Linux Kernel Module Programming Guide, 1999

Rusling, David A: The Linux Kernel, 1999 .

?oltys, Jaroslav: Linux Kernel 2.6 Documentation (Master thesis), 2006

毛德操，Windows 内核情景分析- 采用开源代码ReactOS， 电子工业出版社，2009 .

谭文: 寒江独钓-Windows内核安全编程(完整版)， 电子工业出版社，2009

谭文: 天书夜读-从汇编语言到Windows内核编程， 电子工业出版社，2008

网络/计算机/电脑硬件

网络原理
电脑网络技术
互联网原理
互联网技术
互联网基础
Internet
Internet fundamentals
计算机/电脑硬件原理
计算机/电脑硬件技术
计算机/电脑硬件基础
计算机/电脑硬件介绍
Computer hardware

主板

Mainboard
Motherboard
Mainboard design
Motherboard design

主板
主板设计

http://www.enet.com.cn/motherboard/

http://www.motherboards.org/

Intel Embedded Pentium Processor with MMX Technology Flexible Motherboard Design Guidelines October 1998 p50


Hardware Description Languages

HDL

Hardware Description Languages

=======================

VHDL

VHDL is a hardware description language. It describes the behavior of an electronic circuit or system, from which the physical circuit or system can then be attained (implemented).

VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an abbreviation for Very High Speed Integrated Circuits, an initiative funded by the United States Department of Defense in the 1980s that led to the creation of VHDL.

Its ?rst version was VHDL 87, later upgraded to the so-called VHDL 93. VHDL was the original and ?rst hardware description language to be standardized by the Institute of Electrical and Electronics Engineers, through the IEEE 1076 standard. An additional standard, the IEEE 1164, was later added to introduce a multi-valued logic system.

VHDL is intended for circuit??synthesis? as well as circuit?simulation. However, though VHDL is fully simulatable, not all constructs are synthesizable. We will give emphasis to those that are.

A fundamental motivation to use VHDL (or its competitor, Verilog) is that VHDL is a standard, technology/vendor independent language, and is therefore portable and reusable. The two main immediate applications of VHDL are in the ?eld of Programmable Logic Devices (including CPLDs—Complex Programmable Logic Devices and FPGAs—Field Programmable Gate Arrays) and in the ?eld of ASICs (Application Speci?c Integrated Circuits). Once the VHDL code has been written, it can be used either to implement the circuit in a programmable device (from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication of an ASIC chip. Currently, many complex commercial chips (microcontrollers, for example) are designed using such an approach.

A ?nal note regarding VHDL is that, contrary to regular computer programs which are sequential, its statements are inherently??? concurrent?? (parallel). For that reason, VHDL is usually referred to as a??code? rather than a program. In VHDL, only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.

Aboulhamid VHDL Design Flow BEHAVIORAL AND LOGIC SYNTHESIS p112.pdf

Altium Welcome to the VHDL Language Guide p399.

Ashenden VHDL-Cookbook p111.pdf

Ashenden, Peter J.: VHDL Quick Start, p42, 1998

Ashenden, Peter J.: VHDL Tutorial, Elsevier Science (USA), 2004, p 84

Cooper, Scott: Introduction To The VHDL-AMD Modeling Language, 13 November 2007, p102

Díaz-Pérez, Arturo: An Introduction to the Digital Design Process, p22 Sept 2008

diVerona An Overview on VHDL2SC1.0 Translator p46.pdf

Doulos Vhdl_Golden_Reference_Guide, Version 1.1, December 1995, p136

Díaz-PérezZZZ Arturo An Introduction to the Digital Design Process p22.pdf

EdwardsZZZ Writing VHDL for RTL Synthesis p12.pdf

Essential VHDL, 2006-01-12, P20

IEEE VHDL Standard Referrence Manual VHDL87 p218.pdf

Khalifa, Yaser: Introduction to VHDL,? p108 2003-9-17

Macchett Introduction to the VHDL language p94

Mealy Free Range VHDL p151.pdf
Mealy, free_range_vhdl p192.pdf
Perry VHDL Programming By Example p497.pdf
QualisZZZ VHDL QUICK REFERENCE CARD.pdf
Salapura A VHDL Synthesis Tutorial p127.pdf
Singh vhdl-tutorial p264.pdf
Synario VHDL Reference Manual p144.pdf

Turner, Jon: Using VHDL to Design Digital Circuits – Part 1, p19, Sept 2012
TurnerZZZ Using VHDL to Design Digital Circuits Part 1 p19.pdf
VHDL Language Reference p138.pdf
Xilinx VHDL Reference Guide p348.pdf
ZZZEssential_VHDL_P20.pdf
ZZZVHDL-Handbook p76.pdf

VHDL-Handbook p76 April 2006 HARDI Electronics AB

=================================

VHDL-AMD Modeling Language

=================================

VHDL-AMS

AMS => Analog / Mixed Signal Extensions

=================================

VeriLog

Open Verilog International (OVI)

www.esperan.com

Verilog-XL simulator

Accellera SystemVerilog_3.1a Language Reference Manual p586.pdf

Cantrell, Joshua: Verilog Tutorial .p5 ...Oct 2000

Doulos The Verilog? Golden Reference Guide Version 1.0, August 1996 p151 ............14

MPl TKK Verilog p22 5.10.1999

Navabi Verilog Digital System Design RT Level Synthesis Testbench and Verification p402.pdf
OVI Verilog HDL LRM p296.pdf
OVI verilog-a-lrm-1-0 p170.pdf
Padmanabhan Design through Verilog HDL p461.pdf
Palnitkar Verilog HDL A Guide to Digital Design and Synthesis p399.pdf

Qualis Verilog HDL QUICK REFERENCE CARD
ShettyZZZ System Verilog Testbench Tutorial Using Synopsys EDA Tools p44.pdf
Sutherland SystemVerilog for Design 2nd Edition p436.pdf
Synopsys FPGA Compiler II FPGA Express Verilog HDL Reference Manual p307.pdf
Tala verilog_tutorial p227.pdf

==============================================

Verilog-A

==============================================

Verilog-A/MS - Verilog-AMS

==============================================

SystemVerilog

=============================

Spice

=============================

schematics

=============================

EDIF (netlists)

=============================

GDS, CIF (masks)

=========================


Java

Java Learning is a painful experience, with the rapid development of the Java technologies lead by Sun Technologies. From the early 1998 I have been following that technologies - at that time it was its Jini technololy which attracted me very much. Jini enables all digital devices communicapable once connected in a network. But now it seems this is not the most useful side of Java.
There are of course history behind my decision to focus on Java. Before that I have studied many other programming languages ...
Over the last four years, I have studied and used most of the web application technologies, incl. programming (Java, C, C++, VB, VC, Delphi, Perl, PHP, Python,CFM, JavaScript, VBScript, HTML, XML...), databases (Oracle, Notes, SQL Server, MySQL, mSQL, Access, PowerBuilder, VisualFoxPro, SQL, ODBC, JDBC ...), IDE (VisualStudio, JBuilder, Visual Cafee...), web builder (Dreamweaver, Frontpage, GoLive, Hotdog, HomeSite, VisualInterdev, ...), web application servers (WebLogic, WebSphere, Apache, IIS, Netscape Server,Domino, JRun, Java Web Server, Tomcat, Resin, Enhydra, JBoss, SilverStream ...), image editors (Fireworks, Phtoshop, Photopaint ...), 3D and multimedia (VRML, Flatland and 3dml, WindowsMedia, QuickTime, RealProducer, and hundreds more),
I have tried to get rich by providing my IT services, but my hard studies and hard working seemed not rewarded. I have decided to give up that business in late 2002 after nearly 4 years of try. I was once determined to become a specialist in web building. But now I have to say farewell to IT.
However, all the technologies and skills, knowledge are among my rich resources which may be useful someday. And I still have some interest in them, therefore I am still keeping an eye on the development of the technologies - perhaps once every two months, I will go to some important websites and review the latest development.
And I don't want me kicked off the track of the IT professionals. Therefore I have never stopped to learn some of the software and Internet technologies - and right now I have chosen Java as the focal point. It is planned to learn it during the evening time every other day.
Learning Process ...

J2SE Platform
Java 2 Platform, Standard Edition (J2SE) and its predecessor JDK versions.

J2EE Platform
Java 2 Platform, Enterprise Edition (J2EE).

J2ME Platform
Java 2 Platform Micro Edition (J2ME).

XML
Java Technology and XML.

Java API Docs
API specifications

Tutorials - September 2003
Tutorial about Java technology with these detailed online tutorials and short courses.

Code Samples
Example code illustrates how to perform various programming tasks using the Java programming language.

Articles
Technical articles on topics of interest to Java developers.

FAQs
Answers to Frequently Asked Questions for Java platform-based products and technologies.

White Papers
View white papers with technical and architectural information about Java technology.


Logic Programming

Logic Programming and Constraint Logic Programming

Some of the current CLP languages and their domains are:
  • Prolog III
  • Prolog IV—trees, reals, intervals, rationals, finite domains (including Booleans), strings
  • CLP(BNR)—trees, intervals
  • CLP(R)—trees, floating-point arithmetic
  • CHIP—trees, floating-point arithmetic, finite domains
  • CAL
  • CHARME
  • Chleo/Chlare

Constraint Satisfaction Problem

Node and arc consistency

General backtracking algorithm

  • Generate and Test (GT)
  • Standard Backtracking (SB)
  • Forward Checking (FC)
  • Look Ahead (LA)

Comparison on the queen example

=============================

ProLog

  • Edinburgh Prolog
  • SWI-Prolog
  • Quintus Prolog
  • Visual Prolog www.pdc.dk
  • BIM Prolog
  • Beta-ProLog
  • SICStus Prolog

Blackburn, Patrick et al: Learn Prolog Now 2001 p184

Bramer, Max: Logic Programming with Prolog Springer 2005 p228 .................... 6

Brna, Paul: Prolog programming p193 Jan 2001

Costat, Eduardo: Visual Prolog 7.2 for Tyros, 2009 p252

Covington Prolog Programming in Depth p516.pdf

de Boer, Thomas W.: A Beginners Guide to Visual Prolog, Version 7.2, 2009, p281

ISL(Intelligent Systems Laboratory): SICStus Prolog Users Manual, June 2002 p774

Lu, James and Mead, Jerud J.: Prolog A Tutorial Introduction p42 May 2003

Simonis, Helmut: Constraint Logic Programming p37 ..............27/02/2008

Wielemaker, Jan: SWI-Prolog 5.6 Reference Manual Updated for version 5.6.32, March 2007

=============================


Perl

Install perl modules for MySQL and Oracle

login as root:

Mysql --

#tar zxvf DBI-1.13.tar.gz

#cd DBI-1.13

#perl Makefile.PL

#make

#make test

#make install

#cd ..

#rm -rf DBI-1.13

#

Oracle --

#tar zxvf DBD-Oracle-1.03.tar.gz

#cd DBD-Oracle-1.03

#perl Makefile.PL

#make

#make test

#make install

#cd ..

#rm -rf DBD-Oracle-1.03

#

#tar zxvf Msql-Mysql-modules-1.2209.tar.gz

#cd Msql-Mysql-modules-1.2209

#perl Makefile.PL

select 1(MySQL)and y(Mysql.pm)

#make

#make test

#make install

#

Configure with Apache CGI mode
modify http.conf, uncomment AddHandler cgi-script and change to AddHandler cgi-script .cgi .pl


Python
How to run Python in Apache

Set execution permission:

option one: modify directory properties:

<Directory "f:/phpsite">
Options Indexes FollowSymLinks MultiViews ExecCGI
AllowOverride None
Order allow,deny
Allow from all
</Directory>

optioon two: use ScriptAlias

ScriptAlias /cgi-bin/ "f:/phpsite/cgi-bin/"

Change handler:

uncomment AddHandler cgi-script

change to AddHandler cgi-script .cgi .py

Test

test code

#!d:/python21/python.exe
print "Content-type: text/html"
print
print "<h1>hello,world!</h1>"


Symbolic Languages

Macsyma

Maple

Mathematica

Matlab

Ptolemy


Unified Modeling Language（UML）

Booch, Grady et al: The Unified Modeling Language User Guide Addison Wesley First Edition October 20, 1998 p390

Booch The Unified Modeling Language User Guide 2nd Edition p571.pdf
BoochZZZ the-unified-modeling-language-user-guide p390.pdf
ColbertZZZ Introduction_to_UML p258.pdf

Colbert, Edward: Introduction to the Unified Modeling Language (UML) Sept 2001 p258

GrahamZZZ Uml_tutorial p120.pdf
ISOIEC Unified Modeling Language Specification UML-1.4.2 p454.pdf
OMG Unified Modeling Language p740.pdf
StorrleZZZ Unified Modeling Language 2 p244.pdf
WilliamsZZZ An Introduction to the Unified Modeling Language p18.pdf
YoungZZZ The Unified Modeling Language with Markup p20.pdf
ZZZUML Unified Modeling Language p63.ppt


XML

如何建立一个 XML 的开发环境

学习 XML 的最佳途经是从简单的开发入手，大胆实践，循序渐进。XML 的妙处只有在开发过程中才能深入体会，离开了开发是学不好 XML 的。因此学习 XML 首先应该建立一个 XML 的开发环境。我给大家介绍一下怎样建立一个基于 Java 的 XML 开发环境。因为我现在没办法用到 Linux，所以所有的例子都是在 Windows 上做的。但是这里介绍的所有的软件在 Linux 和 Windows 上都是可以用的，用法也大同小异。而且除了 Sun 的 JRE 以外都是 open source 软件，任何人都可以拿来做任何用途，甚至是商业目的的重新发行。JRE 也是可以免费下载和使用的，只是没有源代码。如果您有在 Linux 上使用这些软件的经验，希望能贡献给大家。

建立一个 XML 的开发环境需要经过以下步骤：
1。安装 Java runtime environment
2。安装一个 Java 编译器。
3。安装一个 JSP Container。
4。安装一个支持 XSLT 的 taglib。
5。安装一个 XML Parser。
6。安装一个支持 XSLT 的浏览器。
7。安装一个 XML 文件的编辑器 (可选)。

步骤1。安装 Java runtime environment

推荐使用 Sun 的 JRE 1.3，可以从这里下载：
http://java.sun.com/j2se/1.3/jre/download-windows.html
注意：不是 JDK 1.3，我们需要的只是 JRE 1.3

下载完 JRE 1.3 后运行安装程序，假设安装在 C:JRE1.3 下。然后需要设置三个环境变量。
JAVA_HOME=C:JRE1.3
CLASSPATH=.;C:JRE1.3librt.jar
PATH=%PATH%;C:JRE1.3bin

如果是 Windows 95/98/me，将环境变量的设置放在 Autoexec.bat 中，然后重启机器，Windows NT/2000 在“我的电脑/属性”中设置就可以了。

步骤2：安装一个 Java 编译器。

推荐使用 IBM 的 jikes，一个高效的 open source 的 Java 编译器。jikes 的主页在
http://oss.software.ibm.com/developerworks/opensource/jikes/
最新的版本是 1.1.3， 可以从这里下载：
http://oss.software.ibm.com/pub/jikes/jikes-1_13-mingw-win32.zip
下载后解压缩，得到一个 jikes.exe，放在任何 PATH 环境变量中的目录下，比如 C:JRE1.3bin

编辑一个简单的 hello world 程序试一下：
// hello.java
public class hello {
public static void main(String [] args) {
System.out.print("hello, world!n");
}
}

然后编译
jikes hello.java

如果生成了 hello.class 就可以用了。

步骤3。安装一个 JSP Container。

推荐使用 Jakarta 的 Tomcat 3.2.1。Tomcat 3.2.1 可以从这里下载：
http://jakarta.apache.org/builds/jakarta-tomcat/release/v3.2.1/bin/
你需要下载 jakarta-tomcat-3.2.1.zip 这个文件
如果你是在 Windows NT/2000 下安装，还有 win32/i386 目录下的 jk_nt_service.zip 。

下载后解压缩，假设放在 C:tomcat 下
然后需要设置一个环境变量
TOMCAT=C:tomcat

为了使 Tomcat 可以使用 jikes，你需要做一点点的 hack，方法如下：
将 tomcat 的 lib 目录下的 parser.jar，jaxp.jar，webserver.jar 加入环境变量 CLASSPATH，使其生效后执行以下步骤：
cd tomcatsrcorgapachetomcatcontext
编辑文件 WebXmlReader.java，将
// sw.addInitParam("jspCompilerPlugin", "org.apache.jasper.compiler.JikesJavaCompiler");
前的注释去掉

然后编译
jikes WebXmlReader.java

建立一个临时目录，使用 jar 工具(可以从 JDK 中获得) 解压缩 Tomcat 的 lib 目录下的 webserver.jar
mkdir t
cd t
jar xvf ..webserver.jar
将 orgapachetomcatcontext 下的 WebXmlReader*.class 替换为刚才编译生成的 WebXmlReader*.class
然后重新打包：
jar cf webserver.jar .
使用新的 webserver.jar 替换 Tomcat 的 webserver.jar

编辑 Tomcat 的 conf 目录中的 web.xml，将

外的注释去掉。

编辑 Tomcat 的 bin 目录中的 tomcat.bat，将所有的 tools.jar 替换为 rt.jar
启动 tomcat，运行 bin 目录中的 startup.bat。
使用浏览器做一下测试，访问
http://localhost:8080
如果 JSP 和 Servlet 的例子都能编译和运行，Tomcat 就可以用了。
停止 Tomcat 用 shutdown.bat

在 Windows NT/2000 下，可以把 tomcat 安装为一个 service，方法如下：
将 Tomcat 的 conf 目录下的 wrapper.properties 拷出来并编辑。将其中的两个变量
wrapper.tomcat_home
wrapper.java_home
分别设置为 TOMCAT 和 JRE 的安装路径，将所有的 tools.jar 替换为 rt.jar。
然后运行
jk_nt_service -I Tomcat wrapper.properties
其中 Tomcat 是我们安装的 service 的名称。
进入控制面板中启动 Tomcat service。Tomcat service安装后设置为手工启动，你可以修改 Tomcat service 的属性使其成为自动启动。

删除 Tomcat service 用：
jk_nt_service -R Tomcat

步骤4。安装一个支持 XSLT 的 taglib。

推荐使用 Jakarta Taglibs 中做 XSLT 的 XSL Taglib
其页面在 http://jakarta.apache.org/taglibs/doc/xsl-doc/intro.html
从该页面上下载 XSL Taglib 的 snapshot。你也可以下载全部的 Jakarta Taglibs，Jakarta Taglibs 的范围很广，但是这里我们要用到的仅仅是其中的 XSL Taglib。

下载完后解压缩，将其中的 xsl-examples.war 和 xsl-doc.war 这两个文件拷到 Tomcat 的 webapps 目录下，然后重新启动 Tomcat。使用浏览器访问
http://localhost:8080/xsl-examples/
运行页面中的 Apply.jsp，如果没有出错，显示了一个有很多表格的页面，XSL Taglib 就可以用了。
XSL Taglib 的文档也装好了，在
http://localhost:8080/xsl-doc/

你可以从这个例子出发，一步一步地开始写你自己的 XML 处理程序。比如你可以在 Tomcat 的 server.xml 中添加一个新的 Context

docBase="path-to-your-work-directory"
crossContext="false"
debug="0"
reloadable="true" >

其中的 path-to-your-work-directory 是你的开发目录。将 Tomcat 的 webapps/xsl-examples 目录下的内容原封不动的拷到你的开发目录，以这个程序为参考开始写你自己的 XML 处理程序。

关于如何使用 JSP 做 XML 开发可以参考 Sun 的 whitepaper ，在：http://java.sun.com/products/jsp/pdf/JSPXML.pdf
讲的基本上就是我上面告诉你的这种方法。

步骤5。安装一个 XML Parser。

做完了步骤3 和 步骤4，你已经有了两个可用的 XML Parser 了，那就是 Tomcat 本身使用的 Sun 的 JAXP 和 XSL Taglib 使用的 xml.apache.org 的 Xerces。JAXP 包括两个文件 parser.jar 和 jaxp.jar，Xerces 只有一个文件 xerces.jar，这几个文件可以从 Tomcat 的目录下找到。
推荐使用 Xerecs 这个 XML Parser，因为它目前已经可以支持 XML Schema，并且它是 open source 软件。但是这完全是出于个人喜好，Sun 的 XML Parser 也是非常出色的。决定使用哪个 XML Parser 后将其文件加入到 CLASSPATH 中。但是不要同时使用两个 XML Parser。CLASSPATH 生效后你就可以在你的 Java 程序中使用 JDOM 和 SAX 的 API 处理 XML 文件了。

关于 JDOM 和 SAX 适用的场合和用法的例子可以从这里找到：http://developerlife.com

步骤6。安装一个支持 XSLT 的浏览器。

这一步并不是必须的，因为我们现在已经可以在 Server 端使用 XSL Taglib 将 XML 文件转换为 HTML 格式后发给 Browser，所以实际上你可以使用任何你喜欢的浏览器。但是安装一个支持 XSLT 的浏览器可以方便我们的学习。虽然现在我们需要在 Server 端做 XSLT，但是将来支持 XSLT 的浏览器流行了之后我们甚至连这一步都可以省掉，直接把 XML 和 XSL 文件发给浏览器就行了。这样就可以大大减轻 Server 端的负担，因为做 XSLT 可不是一件轻松的工作。

推荐使用 Mozilla 0.8。说到这里，你可能又要问了，为什么不使用 IE 4/5 呢？IE 4/5 不是也可以做 XSLT 吗？除了个人喜好以外，我可以举出 3 个使用 Mozilla 的理由：
首先 Mozilla 支持的 XSLT 版本比 IE 4/5 要新，IE 4/5 支持的 XSLT 不是正式版本，而是一个草稿。即：http://www.w3.org/TR/WD-xsl ，而 Mozilla 支持的 XSLT 是 XSLT 的正式版本。即：http://www.w3.org/1999/XSL/Transform 。
其次 Mozilla 中的 XML 应用不仅包括 XSLT，还包括 RDF，XUL，SVG，MathML 等等，所以 Mozilla 对 XML 的支持从广度和深度上都要超过 IE 4/5。
第三 XML FAQ 的作者对 Mozilla 推崇有加，认为 Mozilla 对 XML 的支持在鲁棒性上比 IE 4/5 要好得多。

OK，说了这么多，现在转到正题上来，如何使 Mozilla 0.8 支持 XSLT？
首先，从这里下载 Mozilla 0.8：http://www.mozilla.org/releases/
最新的是 0.8.1 版，但是这个版本安装了支持 XSLT 的模块后无法运行，所以目前还只能使用老一点但是比较慢的 0.8 版。
如果你不想再要其它诸如 SVG/MathML 的功能的话，最方便的方法是使用做好的 .exe 文件安装。
安装完毕后，启动 Mozilla，访问这个页面：http://www.mozilla.org/projects/xslt/
页面里有一个 Install 按钮，点击这个按钮就可以安装实现 XSLT 功能的 TransforMiiX 模块。
重新启动 Mozilla，访问上面提到的那个页面。点击上面 simple example 的链接。如果看到的结果与点击 look like 链接看到的结果相同，那么你的 Mozilla 就已经能够支持 XSLT 了。

关于如何配置 Mozilla 0.8 支持 Java Plug-in 请参考我发在 XML 版的另一篇帖子：基于 Mozilla 的 XML 客户端解决方案，这里就不多说了。

步骤7。安装一个 XML 文件的编辑器。

这一步就更不是必须的了。你听说过现在还有人使用 vi 做 HTML 页面吗？我就见过这样的人，那就是于明俭老师。在于老师的个人主页上有样一句醒目的话：Just vim it ! 实际上你可以使用任何你喜欢的编辑器来编辑 XML 文件，但是为了方便那些习惯使用 WYSIWYG 编辑器的朋友，我还是推荐几个比较好的 XML 编辑器：
1。XML Spy：一个功能很全的 XML 编辑器，有试用版可以下载。
http://www.xmlspy.com/
2。EditML Pro：另一个功能比较全的 XML 编辑器。
http://www.editml.com
3。PSGML for Emacs：Emacs，我就不用说什么了吧？
http://www.lysator.liu.se/projects/about_psgml.html

这里只是为了锦上添花再介绍一些其它的知识，使用这些知识我们可以建造一个更为强大的开发环境。

步骤8。安装一个比较好的 JSP Framework

推荐使用 Struts。Struts 是 Jakarta 项目的一个子项目，目的是开发一个基于 MVC 设计模式的 JSP Framework。在 Struts 的框架内做开发可以有效地分离 Web 应用的表示层和实现层，提高代码的可重用性。基于 MVC 设计模式的开发也就是所谓的 Model 2 开发模式。目前该项目已接近完成，最新的版本是 1.0-beta-1。

关于什么是 MVC 设计模式可以参考机械工业出版社的《设计模式》这本书。关于 Struts 的用法，可以参考我翻译的《Struts 用户指南》，在文章荟萃里：http://www.linuxforum.net/doc/strutsuserguide.html

从这里下载 Jakarta Struts：
http://jakarta.apache.org/builds/jakarta-struts/release/v1.0-b1/
你需要下载 jakarta-struts-1.0-b1.zip 这个文件。
将其解压缩，然后将其中的 struts-example.war，struts-documentation.war 这两个文件拷到 Tomcat 的 webapps 目录下，然后重新启动 Tomcat。使用浏览器访问
http://localhost:8080/struts-example/
运行页面里的 MailReader 程序，如果能正确注册就可以用了。
Struts 的文档也装好了，在
http://localhost:8080/struts-documentation/

关于如何在自己的开发目录中使用 Struts，请参考 Struts 所带的文档。Java 版里有一些关于 Struts 的讨论，使用论坛的搜索功能可以找到。

步骤9。建立与 Apache 的连接

这已经是老生长谈了，我介绍一下最简单的方法，使用 mod_jk 建立与 Apache 的连接。
假设你已经安装好了 Apache，从 这里下载 mod_jk：
http://jakarta.apache.org/builds/jakarta-tomcat/release/v3.2.1/bin/win32/i386/
你需要下载 mod_jk.zip 这个文件。
将其解压缩，得到一个 mod_jk.dll，拷到 Apache 安装目录下的 modules 目录中。
修改 Apache 的配置文件 httpd.conf，加入以下两行：
Include C:/tomcat/conf/mod_jk.conf-auto
JkMount /*.do ajp12
其中“C:/tomcat”是 Tomcat 的安装目录。
将 index.jsp 加到 DirectoryIndex 中，即：
DirectoryIndex index.html index.jsp
如果 ServerName 前有注释，打开 ServerName 前的注释，将其设置为 localhost，即：
ServerName localhost

重新启动 Apache，访问这个页面：
http://localhost/examples/
如果能列出 jsp 和 servlet 目录，Tomcat 和 Apache 的连接就建好了。

OK，说这么多，其实不过是整理了一下内务。现在内务整理好了，我们可以开始做 XML 开发了。:-)

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XML 编辑器
Xeena-1.1.exe

有名的X3d编辑器

by IBM Haifa Research Laboratory

http://www.alphaworks.ibm.com/tech/xeena
Xeena, a visual XML editor, is a generic Java application from the IBM Haifa Research Laboratory for editing valid XML documents derived from any valid DTD.

The editor takes as input a given DTD, and automatically builds a palette containing the elements defined in the DTD. Users can thus create/edit/expand any document derived from that DTD, by using a visual tree-directed paradigm. The visual paradigm requires a minimum learning curve as only valid constructs/elements are presented to the user in a context-sensitive palette.

A Key feature of Xeena is its syntax directed editing ability. Xeena is aware of the DTD grammar, and by making only authorized elements icons sensitive, automatically ensures that all documents generated are valid according to the given DTD

Other Xeena features include:

Intuitive viewing and editing of XML documents in a tree control view
Editing of multiple XML documents
Includes XML source viewer
Restricts adding and editing of features according to the DTD, and checks validity of produced documents
Easy customization of display
How does this technology work?

Xeena is a Java application built on top of Swing and XML Parser for Java. The XML attributes of the elements are edited via a table. Each attribute value is entered using an editing GUI component (e.g. combo-box, text-field) which is also derived from the DTD. The editor guides the user in inserting elements into the tree in a correct order (according to the DTD) by making the elements palette sensitive to the current selected tree node and by not allowing to insert elements in an invalid order. The editor is a Multiple Document Interface application (MDI) with full fledged support to edit multiple XML documents and copy, cut and paste from one document into another.

Xeena, running on the MAC

Xeena is now being used by the web3D consortium to edit Extensible 3D (X3D) graphics files. See a screen shot, then read more about X3D.


XML
Our services | JAVA | XML | Tips
XML editor
Xeena-1.1.exe

by IBM Haifa Research Laboratory

http://www.alphaworks.ibm.com/tech/xeena
Xeena, a visual XML editor, is a generic Java application from the IBM Haifa Research Laboratory for editing valid XML documents derived from any valid DTD.

The editor takes as input a given DTD, and automatically builds a palette containing the elements defined in the DTD. Users can thus create/edit/expand any document derived from that DTD, by using a visual tree-directed paradigm. The visual paradigm requires a minimum learning curve as only valid constructs/elements are presented to the user in a context-sensitive palette.

A Key feature of Xeena is its syntax directed editing ability. Xeena is aware of the DTD grammar, and by making only authorized elements icons sensitive, automatically ensures that all documents generated are valid according to the given DTD

Other Xeena features include:

Intuitive viewing and editing of XML documents in a tree control view
Editing of multiple XML documents
Includes XML source viewer
Restricts adding and editing of features according to the DTD, and checks validity of produced documents
Easy customization of display
How does this technology work?

Xeena is a Java application built on top of Swing and XML Parser for Java. The XML attributes of the elements are edited via a table. Each attribute value is entered using an editing GUI component (e.g. combo-box, text-field) which is also derived from the DTD. The editor guides the user in inserting elements into the tree in a correct order (according to the DTD) by making the elements palette sensitive to the current selected tree node and by not allowing to insert elements in an invalid order. The editor is a Multiple Document Interface application (MDI) with full fledged support to edit multiple XML documents and copy, cut and paste from one document into another.

Xeena, running on the MAC

Xeena is now being used by the web3D consortium to edit Extensible 3D (X3D) graphics files. See a screen shot, then read more about X3D.


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jboss1.htm

resin.htm

resin1.htm

weblogic.html


Apache/PHP4/FastCGI/Oracle/MySQL环境

Linux/Apache/PHP4/FastCGI/Oracle/MySQL/+FrontPage 2000
如何集成Linux/Apache/PHP4/FastCGI/Oracle/MySQL环境

一. 准备工作

要实现将以上环境集成,必需先准备好以下软件包:

(一)数据库的Perl接口

1.perl5的Oracle数据库DBI驱动程序:DBD-Oracle-1.03.tar.gz

2.perl5的通用数据库接口程序:DBI-1.13.tar.gz

3.perl5的MySQL数据库DBI驱动程序:Msql-Mysql-modules-1.2209.tar.gz

(二)Oracle数据库

4.Oracle 8iR2(8.1.6) for Linux安装盘:oracle8161.tar.gz

(三)MySQL数据库

5.MySQL 3.22.32服务器程序包:MySQL-3.22.32-1.i386.rpm

6.MySQL客户端程序包:MySQL-client-3.22.32-1.i386.rpm

7.MySQL开发包(头文件/库文件):MySQL-devel-3.22.32-1.i386.rpm

8.MySQL共享库程序包:MySQL-shared-3.22.32-1.i386.rpm

(四)Apache服务器

9.Apache 1.3.12源码包:apache_1.3.12.tar.gz

(五)PHP模块

10.PHP 4.0.0源码包:php-4.0.0.tar.gz

(六)FastCGI模块

11.FastCGI模块源码包:mod_fastcgi_2.2.4.tar.gz

12.FastCGI的perl开发模块:FCGI-0.53.tar.gz

二. 安装Oracle客户端

由于Oracle 8.1.6是在XWindows下安装的，所以必须是事先配置好XWindow,如果你的显卡不支持XWindow,也可以用exceed进行远程安装(这里不提远程如何安装).

安装Oracle 8.1.6 for Linux详细参见

在此简单列出操作过程:

(一)设置环境变量:

在/etc/profile中加入:

export ORACLE_HOME=/opt/oracle8i/u01

export ORACLE_BASE=/opt/oracle8i

export ORACLE_OWNER=oracle

export ORACLE_SID=ORCL

export ORACLE_TERM=ansi

export PATH=$PATH:$ORACLE_HOME/bin

export LD_LIBRARY_PATH=$ORACLE_HOME/lib

export ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data

export NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"

(二)建立oracle组和用户

#/usr/sbin/groupadd dba

#/usr/sbin/useradd -g dba oracle

#/usr/bin/passwd oracle

(三)创建$ORACLE_HOME目录

#mkdir /opt

#mkdir /opt/oracle8i

#mkdir /opt/oracle8i/u01

#chown -R oracle.dba /opt

(四)安装Oracle 8iR2

以oracle用户登录,解开Oracle安装包:

$tar zxvf oracle8161.tar.gz

$startx 启动XWindow界面,并打开一个rxvt终端窗口

$cd Oracle8iR2

$./runInstaller

此时出现Oracle安装界面,在安装时选择安装Client/Application User

(如果Oracle服务器不在本机上运行,另有专用机器),安装完毕后配置SQL*Net8并

测试连接远程服务器通过即可.

三. 安装MySQL服务器和客户端

以root身分进入,安装MySQL各个包:

#rpm -ivh MySQL-3.22.32-1.i386.rpm

#rpm -ivh MySQL-client-3.22.32-1.i386.rpm

#rpm -ivh MySQL-devel-3.22.32-1.i386.rpm

#rpm -ivh MySQL-shared-3.22.32-1.i386.rpm

四. 安装Perl的数据库接口模块

以root身分进入,然后执行:

#tar zxvf DBI-1.13.tar.gz

#cd DBI-1.13

#perl Makefile.PL

#make

#make test

#make install

#cd ..

#rm -rf DBI-1.13

#

#tar zxvf DBD-Oracle-1.03.tar.gz

#cd DBD-Oracle-1.03

#perl Makefile.PL

#make

#make test

#make install

#cd ..

#rm -rf DBD-Oracle-1.03

#

#tar zxvf Msql-Mysql-modules-1.2209.tar.gz

#cd Msql-Mysql-modules-1.2209

#perl Makefile.PL

选择1(MySQL)和y(支持Mysql.pm)

#make

#make test

#make install

#

五. 安装Apache+PHP+FastCGI

(一)解开Apache/PHP/FastCGI包:

#tar zxvf apache_1.3.12.tar.gz

#tar zxvf php-4.0.0.tar.gz

#tar mod_fastcgi_2.2.4.tar.gz

(二)编译PHP4

配置apache编译参数

#cd apache_1.3.12

#./configure --prefix=/usr/local/apache

配置PHP编译参数

#cd ../php-4.0.0

#./configure --with-apache=../apache_1.3.12 \

> --with-mysql \

> --with-oracle=$ORACLE_HOME \

> --with-oci8=$ORACLE_HOME \

> --enable-track-vars

编译PHP模块:

#make

#make install

创建php.ini参数文件

#cp php.ini-dist /usr/local/lib/php.ini

#cd ..

(三)添加FastCGI模块:

#mv mod_fastcgi_2.2.4 apache_1.3.12/src/modules/fastcgi

(四)编译安装Apache

#cd apache_1.3.12

配置编译参数

#./configure --prefix=/usr/local/apache \

> --activate-module=src/modules/php4/libphp4.a \

> --activate-module=src/modules/fastcgi/libfastcgi.a

编译Apache

#make

安装Apache

#make install

(五)关闭原有系统自带的Apache

#/etc/rc.d/init.d/httpd stop

(六)配置Apache自身参数:

1.编辑/usr/local/apache/conf/httpd.conf文件,修改以下参数:

ServerName host.mydomain.name

DocumentRoot "/home/httpd/html"

Options Indexes FollowSymLinks MultiViews Includes

AllowOverride None

Order allow,deny

Allow from all

ScriptAlias /cgi-bin/ "/home/httpd/cgi-bin/"

AllowOverride None

Options None

Order allow,deny

Allow from all

DirectoryIndex index.html index.phtml index.php index.htm index.shtml index.fcgi

2.修改自启动链接

#cd /etc/rc.d/init.d

#ln -fs /usr/local/apache/bin/apachectl httpd

(七)配置PHP4.0参数:

1.修改/usr/local/apache/conf/httpd.conf文件,修改以下参数:

增加一行:

AddType application/x-httpd-php .php .phtml .php3

2.修改/usr/local/apache/bin/apachectl脚本,使启动支持中文ORACLE环境:

在文件中66行("start)")下面加入几行:

export ORACLE_HOME=/opt/oracle8i/u01

export ORACLE_BASE=/opt/oracle8i

export ORACLE_SID=ORCL

export LD_LIBRARY_PATH=$ORACLE_HOME/lib

export ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data

export NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"

3.修改/usr/local/apache/conf/srm.conf以在CGI程序中使用环境变量:

PassEnv ORACLE_HOME

PassEnv ORACLE_BASE

PassEnv LD_LIBRARY_PATH

PassEnv NLS_LANG

PassEnv ORACLE_SID

PassEnv PATH

(八)配置FastCGI执行环境:

1.修改/usr/local/apache/conf/httpd.conf文件,修改以下参数:

增加几行:

############ FastCGI Configures Begin ##########################

AddHandler fastcgi-script .fcg .fcgi .fpl

SetHandler fastcgi-script

Order deny,allow

Allow from all

Options ExecCGI Indexes Includes

############### FastCGI Configure End ###########################

2.创建fcgi的执行目录

#mkdir /home/httpd/html/fcgi

3.安装FCGI的Perl运行模块:

#tar zxvf FCGI-0.53.tar.gz

#cd FCGI-0.53

#perl Makefile.PL

#make

#make install

六.启运并测试

1.启动Apache服务器:

#/etc/rc.d/init.d/httpd start

2.编写PHP测试程序:

第一个测试程序:/home/httpd/html/t1.php

内容:

<? phpinfo() ?>

第二个测试PHP与Oracle连接的PHP程序(表已经建好):

<?
$conn=OCIlogon("username","password","dblink");
$stmt=ociparse($conn,"insert into testtable (name,id) values ('中文测试',15)");
ociexecute($stmt);
$stmt=ociparse($conn,"select name from testtab where id=15");
ocidefinebyname($stmt,"NAME",&$nick);
ociexecute($stmt);
ocifetch($stmt);
echo "my name is $nick";
?>

查看是否为中文输出

第三个测试PHP与MySQL连接的PHP程序(表已经建好):

<?
$conn=mysql_connect("host","username","password");
mysql_query("insert into testtable (name,id) values ('中文测试',15)");
$result=mysql_query("select name from testtab where id=15");
$query_data=mysql_fetch_row($result);
$nick=$query_data[0];
echo "my name is $nick";
?>

3. 编写FastCGI的测试代码: /home/httpd/html/fcgi/test.fcgi

#!/usr/bin/perl

use FCGI;

use DBI;

$dbname="oracle";

$user="user";

$passwd="password";

$dbh="";

while(FCGI::accept()>=0) {

&parse_form();

$id=$FORM{'id'};

$para=$FORM{'para'};

print "Content-type: text/html\n\n";

print "\n";

if (!$dbh){

print "no oracle, need to connect\n";

$dbh = DBI->connect("dbi:Oracle:$dbname",$user,$passwd);

}else{

print "OK, oracle aleady connected\n";

}

$sth=$dbh->prepare("select name from testtable where id=15");

$sth->execute;

@recs=$sth->fetchrow_array;

$sth->finish;

print "参数id=".$id." and my name is @recs[0] \n";

print "参数para=".$para."\n";

}

####传入参数处理部分#######

sub parse_form {

my($buffer);

my($pairs);

my(@pairs);

my($name);

my($value);

my $meth = $ENV{'REQUEST_METHOD'};

    if ($meth eq 'GET' || $meth eq 'HEAD') {

$buffer = $ENV{'QUERY_STRING'};

}

elsif ($meth eq 'POST') {

read(STDIN, $buffer, $ENV{'CONTENT_LENGTH'});

}

undef %FORM;

@pairs = split(/&/, $buffer);

foreach $pair (@pairs) {

($name, $value) = split(/=/, $pair);

$value =~ tr/+/ /;

$value =~ s/%([a-fA-F0-9][a-fA-F0-9])/pack("C", hex($1))/eg;

$value =~ s///g;

    if ($allow_html != 1) {

$value =~ s/]|\n)*>//g;

}

$FORM{$name} = $value;

}

}

测试看看FastCGI是否正常执行了

Redhat Linux7.1+Apache-1.3.22+MySQL-3.23.43+PHP-4.0.6 + FrontPage 2000

安装程序：

MySQL --> Apache configure --> PHP --> Apache

一、需求

1、一个基于Intel并安装了TCP/IP和libc6的Linux系统。如果Apache或MySQL已经安装好了，建议用软件包管理程序或手工删除它们。

2、需要安装的软件包，它包括：Apache 1.3.22、MySQL服务器、PHP4和FrontPage 2000扩展、Apache支持FrontPage 2000扩展的补丁、最新的gcc编译器及其相关库。

二、准备安装

1、下载软件包

下载下列软件包到/usr/local/temp目录下。

Apache_1.3.22.tar.gz
MySQL-3.23.43.tar.gz
PHP-4.0.6.tar.gz
FrontPage 2000 Extensions

2、解压缩源代码

将所有/usr/local/temp 目录下的源代码包（除了frontpage要解压缩到/use/local目录下）解压缩：

tar -zxfv apache_1.3.22.tar.gz
tar -zxfv fp40.linux.tar.gz -C /usr/local
tar -mysql-3.23.43.tar.gz
tar -zxfv php-4.0.6.tar.gz

三、安装MySQL

第一步先要安装MySQL，因为要安装支持MySQL的PHP，然后安装支持PHP的Apache，下面是具体步骤。

1、设置用户和组

首先，系统增加名为mysql的拥护和组。

groupadd mysql
useradd -g mysql mysql

2、配置并构建MySQL

进入目录/usr/local/temp/mysql-3.23.43 并运行configure 和 make 程序。如果想把数据库存在非缺省目录/usr/local/mysql/var/，则为configure指定选项localstatedir=/your_path。

cd mysql-3.23.43
./configure --prefix=/usr/local/mysql
make
make install

MySQL现在已经安装到/usr/local/mysql目录下。目前还没有一个数据目录，现在要运行MySQL自带的脚本创建目录并安装测试数据库。

scripts/mysql_install_db

在启动守护程序前，改变文件的属权，否则守护程序不能运行。

chown -R mysql.mysql /usr/local/mysql

3、启动MySQL守护程序

现在准备启动守护程序。safe_mysqld 等价于tcpwrapper for MySQL，tcpwrapper常用于包装inet的服务以增加安装性。

/usr/local/mysql/bin/safe_mysqld --user=mysql &

4、设置root用户口令并在引导时启动MySQL。

现在MySQL正在运行，可以用mysqladmin设置root用户口令。

/usr/local/mysql/bin/mysqladmin -u root -p password yourpass

最后一步是需要确保MySQL能在系统重起时启动。编辑/etc/rc/d/rc.local文件，并在末尾加入

/usr/local/mysql/bin/safe_mysqld --user=mysql & 。或者可以编写一个启动/停止的脚本并符号链接到适当的运行级别。

四、为Apache打补丁

在继续下列步骤前，我们必须给Apache打上FrontPage补丁，将FrontPage补丁复制到Apache源代码目录下并做一个到FrontPage的currentversion的符号链接。

cd /usr/local/frontpage/
ln -s version4.0 currentversion
cd currentversion/apache-fp
cp fp-patch-apache_1.3.12 /downloads/apache_1.3.19

1、打补丁

现在在Apache源代码目录下打上FrontPage补丁。这将需要将二进制补丁放在你的目录下。

patch -p0 < fp-patch-apache_1.3.12
这将在apache源代码目录下生成一个mod_frontpage.c文件，它需要复制到extras模块上。

cp fp-patch-apache_1.3.12 src/modules/extra/

2、运行一个简单的apache配置

现在运行一个简单的配置，等一下再运行更高级的配置。

/downloads/apache_1.3.19/configure

五、安装PHP4

PHP4是一种服务器端、跨平台、HTML嵌入式脚本语言，它赋予我们开发动态网站的能力，并能很容易地与MySQL服务器接口。

1、配置apache支持MySQL和Apache

cd /usr/local/temp/apache_1.3.22

./configure --prefix=/usr/local/apache

2、配置PHP4以支持MySQL和Apache

你将安装支持位于/usr/local/mysql目录下的MySQL的PHP4。

cd /usr/local/temp/php-4.0.6
./configure --prefix=/usr/local/php \

>>--with-mysql=/usr/local/mysql \

>>--with-apache=/usr/local/temp/apache_1.3.22 \

>>--enable-track-vars

3. 现在运行make和make install来编译Apache所需的文件。

make
make install

六、安装Apache服务器

Apache是本文的核心，所以请仔细安装下列步骤进行。现在PHP已经构建好，你将在Apache源代码目录下找到一个新目录../apache_1.3.22/src/modules/php4。现在我们再次配置apache，但这时对PHP和FrontPage的支持已经静态地构建好了。

1。设置有关环境变量

增加PATH, CLASSPATH, JAVA_HOME, JRE_HOME, TOMCAT_HOME的配置

2、配置Apache支持ForntPage和PHP4

现在，我们可以用--prefix=/usr/local/apache 配置apache。要知道，src/modules/php4/libmodphp4.a毫不存在，但将要生成。要注意用--add-module加入FrontPage，--activate-module加入PHP。现在运行make和make install以构建并安装Apache。其它无关紧要的是httpd.conf放在哪里，有些人喜欢放在/etc目录下。如果像这样做，加上--localstatedir=/etc即可。

cd /usr/local/temp/apache_1.3.22

./configure --prefix=/usr/local/apache \

--activate-module=src/modules/php4/libphp4.a \

--enable-module=so (启动Tomcat服务所需) \

--add-module=src/modules/extra/mod_frontpage.c

3、构建Apache

运行make将创建httpd二进制代码。如果你覆盖一个老版本的服务器，你要做的就是make，然后将httpd二进制代码从bin目录复制到现有的httpd产品目录即可。这里建议你有一个全新的安装，因为这样非常容易地从原先的安装迁移www数据和conf文件。

make
make install

七、修改httpd.conf

很好，你已经安装好了Apache，并支持FrontPage、PHP和MySQL。现在整理一下其他事情以便能工作得更好。首先修改一些httpd.conf配置。

1、增加PHP标记

为了让Apache处理PHP扩展名，必须加入该类型。确保你把配置文件中的下列两行去掉注释。如果这两行不存在，必须手工添加。

AddType application/x-httpd-php .php
AddType application/x-httpd-php-source .phps

2、改变Directory Index

改变Directory Index支持以增加index.php和index.shtml。这完全作为参考，但如果你的网站严格地用SSI或PHP编写，那么有这些额外的Directory Index文件将避免参照index文件的全路径，相反，你可以简单地键入http://www.virtual.com而不是http://www.virtual.com/index.php。

DirectoryIndex index.php index.shtml index.html index.htm

3、修改目录权限

对配置文件几个重要的修改是DocumentRoot和Directory的权限。修改DocumentRoot指向你的缺省网页文件，如

DocumentRoot /www/httpd
现在对它修改目录权限是的FrontPage能够用其.htaccess文件覆盖它们。AllowOverride从None改为All。

Options Indexes FollowSymLinks MultiViews
AllowOverride All
Order allow,deny
Allow from all

八、运用FrontPage Extensions到根网站

我们已经完成了支持PHP和MySQL的Apache，剩下的事情就是FrontPage服务器扩展了，你可能用或不用于你的网站。但你有多人需要编辑网站并且不是每个人都熟悉FTP和HTML时，它就有用了。

1、运行fpsrvadm.exe

我们把FrontPage扩展用于网站根目录（/www/httpd）。

cd /usr/local/frontpage/currentversion/bin/
并运行fpsrvadm.exe安装扩展到根目录。

./fpsrvadm.exe -o install

: 0 for apache (do not choose apache-fp)
: /usr/local/httpd/conf/httpd.conf (patch to server config file)
: ENTER (Just hit enter for a blank multi-hosting)
: apache (user owner of DocumentRoot (i.e. /www/httpd))
: web (group owner of DocumentRoot (i.e. /www/httpd))
: myuser (frontpage login)
: mypass (frontpage password)

注意，这里使用用户“apache”和“web”组。对于虚拟域，对每个虚拟域分开用户，但组总是“web”。

2、创建其他FrontPage用户

现在简单地为FrontPage提供一个管理员账号及该账号口令，它将是访问FrontPage的登陆名和口令。如果你保持这些与ftp登陆同步，可能更好些。你总能回来并运行./fpsrvadm.exe并用Option 7增加一个用户并输入正确的信息。或者你可以修改包含用户和加密口令的/_vti_pvt/service.pwd文件，如果需要生成一个加密口令，使用：

htpasswd temp.pass.file
Enter Password : **********
pico temp.pass.file
:3923kw#$sdfk32$

然后复制用户和加密口令到service.pwd并且该用户即可登陆，你也必须包用户组成一组，这样对网站的修改可以进行了，这通过编辑/_vti_pvt/service.grp完成。

pico _vti_pvt/service.grp
administrators : administrator
authors :

增加新用户到适当的修改网站的组中。现在尝试通过FrontPage登陆，用户再增加"author"或"administrator"后应该有权编辑了。

九、用FrontPage支持创建虚拟网站

这个过程与把它们加入根网站相同，唯一的差别是当运行fpsrvadm.exe时要提供一个muulti-hosting名而不是指打回车。多宿主名将是定义在中的ServerName。

首先，编辑htppd.conf并去掉NameVirtualHost行的注释。如果你在这台机器上只有一个IP地址，那么表中第一个虚拟主机将是你的根网站。如果有两个IP地址，那么你的根网站可能在192.168.0.1并且虚拟网站可能在192.168.0.2，这可以保持根网站的完整。

if you have 1 ip address
NameVirtualHost *
if you have a separate ip address just for your virtual webs
NameVirtualHost 192.168.0.2

确保如果你有多个IP地址，告诉Apache监听哪个IP地址，或用Listen *让Apache监听列在ifconfig中的所有接口。

# to make apache listen on all ip addresses assigned to the box
Listen *

# Listen for root web
Listen 192.168.0.1

# Listen for virtual webs
Listen 192.168.0.2

现在你已经知道该信息，假如一个虚拟网站。

ServerAdmin root@virtual.com
ServerName virtual.com
DocumentRoot /www/virtual.com/public_html
CustomLog logs/virtual.com/access_log combined
ScriptAlias /cgi-bin /www/virtual.com/public_html/cgi-bin/

AllowOverride All
Options Indexes FollowSymLinks Includes ExecCGI MultiViews
Options All
order allow,deny
allow from all

AllowOverride None
Options ExecCGI FollowSymLinks INcludes

LogFormat Combined
ServerAlias virtual.com *.virtual.com

首先，在这个虚拟域定义中有几点说明。

# To make this virtual web listen on all interfaces and all ports

# If you have a separate IP # for virtual hosting

# To listen only on port 80 on 192.168.0.2

# To listen only on port 80 on all interfaces

这里只使用，因为在机器上只有一个IP地址。记住，这的确破坏了你的根网站（/www/httpd）并使得第一个定义称为你的根网站。

在有人到达你的IP地址时，他们首先被第一个虚拟网站服务，而不是根网站。这是为什么机器要有两个IP地址并将根网站置于各自独立的IP地址的原因。或者你有整个C类地址，或一个子网，那么你可以将每一个网站赋予其自己的IP地址，这样会好些。

在虚拟主机中的定义允许FrontPage用.htaccess文件改写权限。

好了，现在你已经把一个虚拟主机加到了httpd.conf中，名为"virtual.com"，保存httpd.conf并运用FrontPage扩展。

cd /usr/local/frontpage/currentversion/bin
./fpsrvadm.exe -o install

: 0 for apache (do not choose apache-fp)
: /usr/local/httpd/conf/httpd.conf (patch to server config file.
: www.virtual.com (the name of ServerName in )
: apache (user owner of DocumentRoot (i.e. /www/httpd))
: web (group owner of DocumentRoot (i.e. /www/httpd))
: myuser (frontpage login)
: mypass (frontpage password)

注意，对虚拟网站，为每一个网站在机器上创建一个用户。

本例中用户和组为：

: virtual (virtual.com的用户)
: web (所有网站的用户组)

用户和组必须在运行./fpsrvadm.exe安装FrontPage扩展前在/etc/passwd和/etc/group中是有效的。现在FrontPage扩展已经被复制到了你的新虚拟网站的DocumentRoot（如/www/virtual/public_html）。

你可以改变该目录并检验再次有一个_vti_文件夹。

现在尝试通过FrontPage连接新虚拟网站，Open Web -> http://www.virtual.com。

它应该询问登陆名和口令，如果没问题，你可以增加更多的虚拟主机到httpd.conf中，然后以同样的方式实现FrontPage扩展。

十、测试文件

最后的步骤是测试PHP、CGI和SSI。你可以用下列文件或创建自己的。通过FTP上传文件到网站上，然后点击浏览器测试它们。

<略>
Oracle8.1.6i+ Apache1.3.14+PHP4.0.3完全安装实例

1． 本文目的
● 在redhat下安装ORACLE8数据库服务器
● 安装apache,并支持wml
● 安装PHP

2． 安装前的准备软件：
Redhat 6.2安装光盘
Oracle8.161.tar.gz 下载地址：
http://freeware.online.sh.cn/mirrors/LinuxApps/Database/Oracle下的oracle8.161.tar.gz
Java运行时刻环境（JRE）下载地址：
ftp://165.21.84.42/pub/j2sdk/1.3.0/xzc233fcslnx/下的j2sdk-1_3_0-linux-rpm.sh
Apache 1.3.14 下载地址：
http://www.apache.org/dist/apache1.3.14.tar.gz
php4.0.3 pl1 下载地址：
http://www.php.net/do_download.php?download_file=php- 4.0.3pl1.tar.gz&source_site=www.php.net

3． 安装oracle前的准备
● 安装JRE1.3.0
[root@wapdb /root]# #以root身份登录
[root@wapdb /root]# chmod 755 j2re-1_3_0-linux-rpm.sh #改变j2re-1_3_0-linux-rpm.sh
的权限
[root@wapdb /root]#./ j2re-1_3_0-linux-rpm.sh #运行j2re-1_3_0-linux-rpm.sh在同级目录
下可得到JRE的RPM包。
[root@wapdb /root]# rpm –i j2re-1_3_0-linux-rpm #安装JRE1.3.0:
● 创建oracle。apache用户组：
执行以下命令：
[root@wapdb /root]#　　　　　　　　　　　　　　 #以root方式登录
[root@wapdb /root]# groupadd oracle　　　　　　　　#创建oracle组
[root@wapdb /root]# useradd oracle -g oralce　　　 #在oracle组中建新用户oracle
[root@wapdb /root]# useradd apache -g oralce #在oracle组中建新用户apache
[root@wapdb /root]# passwd oracle　　　　　　　 #修改oracle用户口令
注：oracle组和oracle用户是oracle安装需要的
注：创建oracle用户后，linux系统自动在/home目录下创建/home/oracle目录，给oracle用户使用，oracle用户对此目录拥有所有的权限。
[root@wapdb /root]# cd /home/oracle
[root@wapdb /root]# vi .bash_profile　　　　#编辑.bash_profile文件，并输入以下内容
# Setup ORACLE environment
NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"; export NLS_LANG
JAVA_HOME=/usr/java/jre1.3
BASH_ENV=$HOME/.bashrc
ORACLE_HOME=/data/oracle/app/oracle/product/8.1.6
export ORACLE_HOME
ORACLE_SID=wap
export ORACLE_SID
# Set up the search paths:
PATH=$PATH:$HOME/bin:$JAVA_HOME/bin:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/d
bs
export USERNAME BASH_ENV PATH ORACLE_HOME JAVA_HOME

4． 安装Oracle8I
[root@wapdb /oracle]# exit　　　　　#退出，以oracle用户重新登录，以使设定的环境生效
[oracle@ wapdb/oracle]$
[oracle@ wapdb/oracle]$ tar zxvf oracle8161_tar.gz　　　#解压oracle压缩包到当前目录
[oracle@ wapdb/oracle]$ startx　　　　　#启动X-windows后，启用一个终端（xterm），
(图形窗口）在该终端中运行runInstaller
[oracle@wapdb /oracle]$ cd Oracle8iR2 #进入解压缩的目录
[oracle@wapdb /Oracle8iR2]$ ./runInstaller #执行oracle安装程序。

这时可以看到用jre运行的的图形化的OUI的欢迎画面，按照提示继续安装进程（这里我们可以选择典型安装）：
Welcome：
按next
File Locations：
按next
UNIX Group Name：
oracle，按next
出错，提示要以root权限运行“/data/oracle/app/oracle/product/8.1.6/orainstRoot.sh
CTRL+ALT+F2，打开一个新的控制台（字符窗口）
以root登录
[root@wapdb /root]# cd /data/oracle/app/oracle/product/8.1.6
这时，/data/oracle/app/oracle/product/8.1.6目录下有一个文件orainstRoot.sh，运行它
[root@wapdb /8.1.6]# sh orainstRoot.sh
CTRL+ALT+F7，回到安装界面（图形窗口）
按Retry按钮，就可以继续安装了，
Available Products：
选Oracle8i Enterprise Edition 8.1.6.1.0，按next
Installation Types：
选Typical（540MB），按next，这时，屏幕右上角出现一个进度标尺
Database Identification：
Global Database Name：输入wap（可以任意）
SID：保留wap
按next
Database File Location：
任意目录，本例设为“/data/oracle/app/oracle/product/8.1.6/data”，按Next，这时，屏幕右上角进度标尺继续前进
出现Summary，对你想要安装的产品作一个总结
按Install，出现Install画面，等待... 可以看到窗口底部提示的安装等log文件目录，可供以后查询。
弹出Setup Privileges窗口
提示：在安装继续进行之前，需要以root运行一个脚本
“/data/oracle/app/oracle/product/8.1.6/root.sh”，
CTRL+ALT+F2，回到刚才运行的第2个终端窗口
以root权限执行该文件，
[root@wapdb /8.1.6]# sh root.sh
屏幕显示：
Enter the full pathname of the local bin directory:[/usr/local/bin]:
回车
系统开始执行一些动作，执行完毕，CTRL+ALT+F7按返回OUI，按OK。
Database Creation Progress开始，逐步进行以下4个过程
Creating and starting Oracle instance
Copying database files
Initializing database
Database creation completed
以上4个过程完成，弹出Oracle Database Configuration Assistant Alert窗口，
提示：数据库创建完成，告诉你数据库的一些基本信息
global databse name：wap
database system identifier（SID）：wap
SYS account password：change_on_install
SYSTEM account password：manager
按ok
End of Installation，按Exit退出OUI，完成安装。
到此，已经完成了数据库服务器的安装，下一步进行web/wap服务器的安装。

5． 安装ORACLE客户端
（该步骤适合与数据库服务器与WEB服务器安装在不同机器上，若为同一台机器直接执行 第6步）
重复第3步
在第4步的安装中选择“客户端安装”步骤大致相同。
配置tnsnames.ora文件（可以在/$ORACLE_HOME/bin/运行netasst命令启动OUI来配置）。最快的方法是COPY数据库服务器端的tnsnames.ora到$ORACLE_HOME/network/admin中。
以ORACLE用户登录
[oracle@wapserver /]$ cd $ORACLE_HOME/network/admin
[oracle@wapserver admin]$ ftp xxx.xxx.xxx.xxx #使用FTP登录oracle服务器，以ORACLE 并使用oracle用户.
ftp>cd /data/oracle/app/oracle/product/8.1.6/network/admin
ftp>get tnsnames.ora
ftp>bye

6． 配置apache_1.3.14
[root@wapdb /local]# tar zxvf apache1.3.14.tar.gz #解压apache
[root@wapdb /local]# cd /usr/local/apache_1.3.14 #进入apache的解压目录。
[root@wapdb /local]# ./configure --prefix=/usr/local/apache

7. 安装 PHP4
[root@wapdb /local]# tar zxvf php- 4.0.3pl1.tar.gz #解压php
[root@wapdb /local]# cd php-4.0.3
[root@wapdb /php-4.0.3]#./configure --with-apache=../apache_1.3.14 \
--with-oracle=/data/oracle/app/oracle/product/8.1.6 \
--with-oci8=/data/oracle/app/oracle/product/8.1.6 \
--enable-track-vars
[root@wapdb /php-4.0.3]# make #编译
[root@wapdb /php-4.0.3]# make install # 安装
[root@wapdb /php-4.0.3]# cp php.ini-dist /usr/local/lib/php.ini #拷贝ini文件到lib目录

8．安装apache
[root@wapdb /php-4.0.3]# cd /usr/local/apache_1.3.14
[root@wapdb/apache_1.3.14]# ./configure --prefix=/usr/local/apache \
--activate-module=src/modules/php4/libphp4.a
[root@wapdb /apache_1.3.14]# make
[root@wapdb /apache_1.3.14]# make install

9．配置apache
[root@wapdb /apache_1.3.14]# cd /usr/local/apache/conf
[root@wapdb /conf]# vi httpd.conf
修改httpd.conf文件
以下几行去掉注释：
ServerName http://。。。。。。。 这个一定要去掉注释
Listen XXX.XXX.XXX:8888(其中xxx.xxx.xxx为域名，或者IP地址）
AddType application/x-httpd-php .php
AddType application/x-httpd-php-source .phps

修改以下两行：
User apache
Group oracle
[root@wapdb /conf]# vi mime.types
修改mime.types文件, 添加WAP支持,添加如下行:
text/vnd.WAP.WML WML
text/vnd.WAP.WMLscript WMLC
image/vnd.WAP.WBMP WMLP
application/vnd.WAP.WMLC WMLC
application/vnd.WAP.WMLCSRIPTC WMLSC
系统的安装已经完成，下面对环境进行测试：

10．启动数据库：
在数据库服务器里运行：
[oracle@wap /bin]$ svrmgrl
SVRMGR> connect internal
Connected.
SVRMGR> startup
ORACLE instance started

11．启动监听器
[oracle@wapdb /bin]$ lsnrctl
LSNRCTL> start
LSNRCTL> exit
这时，oracle数据库已经安装成功，并且数据库已经启动运行，可以试一下
[oracle@wapdb /bin]$sqlplus system/manager@wap

出现以下信息：
SQL*Plus: Release 8.1.6.0.0 - Production on Fri Oct 26 20:20:56 2000
(c) Copyright 1999 Oracle Corporation. ALL rights reserved.
Connected to:
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SQL> show user
USER is "SYSTEM"
SQL>
SQL> exit

12．启动Apache了
[oracle@wapdb /root]# cd /usr/local/apache/bin
[oracle@wapdb /root]# apachectl start

13．测试PHP
htdocs目录下编辑一个test.php
phpinfo();
?>
通过浏览器浏览该网页，可以看到PHP的环境参数，如果找到有oricle和orci8的支持，说明PHP已经支持ORACLE和OCI8。

12．测试PHP与ORACLE的连接
//文件名为test.php.
$conn=ocilogon("system","manager","test");
if($conn)
echo success;
else
echo fail;
?>
如果该程序返回成功标志，则表明连接成功。
13．测试时候支持WML
在htdocs目录下编辑test.wml

"http://www.wapforum.org/DTD/wml_1.1.xml">

hello word!

在任何其他一台win9x的机子上使用WAP模拟器浏览该网页，应该出现”hello word”。
现在整个环境已经调试完成，可以利用PHP+ORACLE8i进行动态html或wml的开发了！
Tomcat
安装TOMCAT(以root用户安装)
假设Java与Apache都已经安装好，分别位于：/usr/java/j2sdk1.4.0, /usr/local/apache
Apache安装时用--enable-module=so参数以支持mod_jserv.so

简介

Jsp是sun在servlet基础上发展而来的一种新的web开发工具，在国外EJB+JSP/Servlet+应用服务器+数 据库已经已经成为电子商务站点的流行架构。

所需软件及下载

jakarta-tomcat.tar.gz
http://jakarta.apache.org/builds/jakarta-tomcat/release/v3.1.1/bin/

mod_jserv.so
http://jakarta.apache.org/builds/jakarta-tomcat/release/v3.1.1/bin/linux/i386

下载目录：/usr/local/temp

安装步骤

1. 修改/etc/profile, ~/.bash_profile 环境文件

PATH="$PATH:/usr/local/tomcat/bin:/usr/java/j2sdk1.4.0/bin:/usr/java/j2sdk1.4.0/jre/bin"
JAVA_HOME=/usr/java/j2sdk1.4.0
export JAVA_HOME
JRE_HOME=/usr/java/j2sdk1.4.0/jre
export JRE_HOME
TOMCAT_HOME=/usr/local/tomcat
export TOMCAT_HOME
CLASSPATH=/usr/javal/j2sdk1.4.0/lib:/usr/java/j2sdk1.4.0/jre/lib
export CLASSPATH

2. 安装Tomcat
cd /usr/local/temp

cp jakarta-tomcat.tar.gz /usr/local

cd /usr/local

tar zxvf jakarta-tomcat.tar.gz

修改/usr/loccal/jakarta-tomcat目录为 /usr/local/tomcat

3. 运行tomcat服务器

cd /usr/local/tomcat/bin

./startup.sh start(用./shutdown.sh stop结束tomcat服务器）

lynx http://localhost:8080/

看见了jsp/servlet的东西，并且能运行它的例子程序，那么你的tomcat 服务器就安装成功了

4 和apache连接

(1) 简介：
    tomcat本身其实就是一个web服务器，我们可以把它和apache等其他web服务器连接起来，这两个服务器可以不在同一台机器上。下面的操作是在同一台机器上的情况。

(2) 拷贝mod_jserv.so
将mod_jserv.so 拷贝到apahce的libexec目录
cd /usr/local/temp
cp mod_jserv.so /usr/local/apache/libexec

(3) 修改Apache的配置文件，加入对tomcat的支持

cp /usr/local/tomcat/conf/tomcat.conf /usr/local/apache/conf/tomcat.conf

修改/usr/local/apache/conf/httpd.conf

加入Include /usr/local/apache/conf/tomcat.conf

配置和管理TOMCAT
/usr/local/jakarta-tomcat/conf/server.xml

测试及管理办法

退出并重新登入

重新启动你的apache, 然后运行tomcat服务器
lynx http://localhost/examples/
如果你看见了jsp、servlet目录，你的apche与tomcat已经连接成功了.

一些说明

如果你的jsp/servlet运行不了或者有错误，一般是你的CLASSPATH设置错误。

如果你的apache是自己编译的，编译apache时请把--enable-module=so打开。

HOWTO install and setup Apache+Jakarta-Tomcat4.01+webapp-modul for Linux

1.所需的软件包:
jdk1.3.1_01
Apache1.3.22
Jakarta-Tomcat4.01
Webapp-modul1.0

2.软件包下载地址:
(1) Java 2 SDK, Standard Edition Version 1.3.1_01 for Linux (Intel x86)
URL:http://java.sun.com/j2se/1.3/download-linux.html
(2) Apache_1.3.22
URL:http://httpd.apache.org/dist/httpd/apache_1.3.22.tar.gz
(3) Jakarta-Tomcat4.01
URL:http://jakarta.apache.org/builds/jakarta-tomcat-4.0/release/v4.0.1/bin/jakarta-tomcat-4.0.1.tar.gz
(4) Webapp-modul1.0
URL:http://jakarta.apache.org/builds/jakarta-tomcat-4.0/release/v4.0.1/bin/linux/i386/webapp-module-1.0-tc40-linux-glibc2.2.tar.gz

3.软件安装:
(1) 解开压缩包
     使用tar或rpm解开下载的软件包，按照默认方式安装既可
(2) 目录的处理
JDK安装目录: /usr/java/jdk1.3.1_01
Apache安装目录: /etc/httpd,/usr/lib/apache,/var/www
Jakarta-Tomcat安装目录: /usr/local/jakarta-tomcat-4.0.1
Webapp-modul安装目录:/usr/local/webapp-module-1.0-tc40

4.环境变量设置:
PATH=/usr/java/jdk1.3.1_01/bin:/usr/java/jdk1.3.1_01/jre/bin:/usr/local/sbin:/usr/sbin:/sbin:$PATH:$HOME/bin
JAVA_HOME=/usr/java/jdk1.3.1_01
CLASSPATH=/usr/java/jdk1.3.1_01/lib:/usr/java/jdk1.3.1_01/jre/lib
CATALINA_BASE=/usr/local/jakarta-tomcat-4.0.1
CATALINA_HOME=/usr/local/jakarta-tomcat-4.0.1

5.特殊安装:
把/usr/local/webapp-module-1.0-tc40目录下的mod_webapp.so文件复制到/usr/lib/apache
并执行如下命令来改变其属性
cd /usr/lib/apache
chmod +x mod_webapp.so

6.独立环境的测试
(1) 测试Java的运行状况,如下命令:
cd
java -version
javac -version
看到版本号则表示JDK安装成功
(2) 测试Apache的运行状况,如下命令:
/etc/init.d/httpd restart ## 重新启动Apache Server
使用任意一浏览器,输入服务器地址后回车,应该可以看到Apache的默认主页
(3) 测试Jakarta-Tomcat的运行状况,如下命令:
cd /usr/local/jakarta-tomcat-4.0.1
cd bin
./startup.sh ## 启动jakarta-tomcat-4.0.1服务
使用任意一浏览器,输入服务器地址和端口号8080后回车,应该可以看到jakarta-tomcat-4.0.1的默认主页
例如: http://192.192.192.1:8080
./shutdown.sh ## 关闭jakarta-tomcat-4.0.1服务

7.整合安装设置
(1) 修改/etc/httpd/conf/httpd.conf文件
在# Dynamic Shared Object (DSO) Support之后,添加如下内容
LoadModule webapp_module modules/mod_webapp.so
(2) 修改/etc/httpd/conf/httpd.conf文件
在ClearModuleList后,添加如下内容
AddModule mod_webapp.c
(3) 修改/etc/httpd/conf/httpd.conf文件
在文件尾部添加如下内容
WebAppConnection warpConnection warp localhost:8008
WebAppDeploy examples warpConnection /examples/

8.整合测试
重新启动所有服务
/usr/local/jakarta-tomcat-4.0.1/bin/shutdown.sh
/usr/local/jakarta-tomcat-4.0.1/bin/startup.sh
/etc/init.d/httpd restart
在浏览器中输入如下地址
http://服务器IP/examples/jsp/index.html,如果能够显示正常的网页,则安装成功
在浏览器中输入如下地址
http://服务器IP/examples/jsp/jsptoserv/jsptoservlet.jsp,如果能够显示正常的网页和时间,则jsp和Servlet安装成功

9.注意,
如在第8步中,重启Apache服务的时候报如下错误
Syntax error on line 1219 of /etc/httpd/conf/httpd.conf:
Invalid virtual host name
则证明在/etc/httpd/conf/httpd.conf中,未设定ServerName
打开/etc/httpd/conf/httpd.conf文件,找到ServerName一项,设定为你指定的名字,或简单的去掉#ServerName前的“#”号,再执行/etc/init.d/httpd restart就可以了!

apache+php+mysql+imap+ldap+jdk+tomcat的安装

以下过程在redhat6.2 7.0下通过。

使用软件：
apache_1.3.19.tar.gz
imap-2000c.tar.Z
mod_jserv.so..so
j2sdk-1_3_0_02-linux.bin
mysql-3.23.33-pc-linux-gnu-i6862.tar.gz
openldap-2.0.7.tar.gz
php-4.0.4pl1.tar.gz
jakarta-tomcat-3.3-m2.tar.gz
phpMyAdmin_2.1.0.tar.gz

一、下面以/home/hailang/ 目录为例：

tar zxvf apache_1.3.19.tar.gz
tar zxvf imap-2000c.tar.Z
tar zxvf mod_jserv.so..so
tar zxvf mysql-3.23.33-pc-linux-gnu-i6862.tar.gz
tar zxvf openldap-2.0.7.tar.gz
tar zxvf php-4.0.4pl1.tar.gz
tar zxvf jakarta-tomcat-3.3-m2.tar.gz
tar zxvf phpMyAdmin_2.1.0.tar.gz
chmod a+X j2sdk-1_3_0_02-linux.bin 会生JSDK1.3的目录

二、开始安装
安装IMAP
cd imap-2000c
make slx
cp imap/imapd /usr/sbin
cp ipopd/ipop2d /usr/sbin
cp ipopd/ipop3d /usr/sbin

三、 安装LDAP
cd ../openldap-2.0.7
./configure --prefix=/home/ldap
--enable-dns --enable-cldap --enable-ldapd
--enable-wrappers --enable-phonetic
--enable-passwd --enable-shell
make depend
make
make test
su root -c make install

四、 安装MYSQL
cd ../mysql.X.X
./configure --prefix=/home/mysql
make
make install
scripts/mysql_install_db
/home/mysql/bin/safa_mysqld &
/home/mysql/bin/mysqladmin -u username password yourpassword
自起动：
cp /home/mysql/share/mysql/mysql.server /etc/rc.d/rc.local/mysql
运行setup在系统一项中选择mysql

五、 安装PHP4
cd ../apache.1.3.19
./configure --prefix=/home/httpd
cd ../php4.0.4
./configure --with-mysql=/home/mysql
--with-apache=/home/hailang/apache源码
--with-imap=/home/hailang/imap源码
--with-ldap=/home/ldap
--enable-track-vars
make
make install

六、 安装apache
cd ../apache.1.3.19
./configure --prefix=/home/httpd
--activate-module=src/modules/php4/libphp4.a
--enable-moudle=so(如果不要JSP支持可以不要)
make
make install
cp ../php4.0.4/php.ini-dist /usr/local/lib/php.ini
将/home/httpd/conf/httpd.conf文件中的
# And for PHP 4.x, use:
#AddType application/x-httpd-php .php
#AddType application/x-httpd-php-source .phps
改为：
# And for PHP 4.x, use:
#AddType application/x-httpd-php .php .php3
#AddType application/x-httpd-php-source .phps
将：

DirectoryIndex index.html

改为：

DirectoryIndex index.html index.php index.php3 index.htm

重起apache:
/home/httpd/bin/apachectl start即可。
如果出现问题请确定是否有原来安装的apache服务器。
运行setup选择系统顶将 httpd项不选。重新起动机器。

apache服务器的自起动：
在/etc/rc.d/rc.local文件中加入：
/home/httpd/bin/apachectl start

七、安装JDK
在/home目录下：
ln -s hailang/jdk1.3 jdk
ln -s jdk/jre

设置$JAVA_HOME，$CLASSPATH
vi /etc/profile
加入：
JAVA_HOME=/home/jdk
export JAVA_HOME
CLASSPATH=/home/jdk/lib:/home/jre/lib
export CLASSPATH
PATH=$PATH:/home/jdk/bin:/home/jre/bin
注意，不能写错，要不出了问题可别找我。

八、安装tomcat

ln -s hailane/tomcat
运行tomcat服务器
tomcat/bin/tomcat.sh start
停止：
tomcat/bin/tomcat.sh stop
运行http://localhost:8080
如果看见了JSP/servlet 的例子页面，并且能运行它的例子程序，那么你的tomcat
服务器就可以了。有时候可能要多次刷新才可以。就多试几次吧。

九 . 和apache连接
cp mod_jserv.so /home/httpd/libexec
在/home/httpd/conf/httpd.conf文件中加入：
Include /home/tomcat/conf/jserv/tomcat.conf
作用是apache服务器在启动时候载入tomcat的模块。不过好象不好使，
每次都的我亲手再次起动tomcat.

重新起动apache。然后运行tomcat服务器。 http://localhost/ecamples/
如果你看见了JSP。SERVLET目录 ，那么你成功了。

如何配置，linux+apache+tomcat+Jserv,就是用apache 下编jsp应用

jakarta-tomcat.tar.gz //tomcat
jdk1_2_2-linux-i386.tar.gz //java环境
mm.mysql.jdbc-1.2c.tar.gz //数据库接口 已有更新的版本
mod_jserv.so //★jsp server模块

将 mm.mysql.jdbc-1.2c.tar.gz 和 jakarta-tomcat.tar.gz解到/下
将 jdk1_2_2-linux-i386.tar.gz 解到/usr/local下
$ cp mod_jserv.so /usr/local/apache/libexec
$ /jakarta-tomcat/bin/startup.sh
此时会出错，没关系，只是先让它产生一个文件 /jakarta-tomcat/conf/tomcat-apache.conf
$ vi /usr/local/apache/conf/httpd.conf
在最后加
include conf/tomcat.conf
后保存
$ cd /usr/local/apache/conf/
$ ln /jakarta-tomcat/conf/tomcat-apache.conf tomcat.conf
建立tomcat.conf的连接
修改profile设置环境变量
$ cd /etc
$ vi profile
再里面添加如下几句
JAVA_PATH=/usr/local/jdk1.2.2
export JAVA_PATH
CLASSPATH=/usr/local/jdk1.2.2/lib:/usr/local/jdk1.2.2/jre/lib:/mm.mysql.jdbc-1.2c:/jakarta-tomcat/src
export CLASSPATH
PATH="$PATH:$JAVA_PATH/bin:$JAVA_PATH/jre/bin:/usr/X11R6/bin"

其他
1)

去下载webapp-module-1.0-tc40-src.tar.gz
这个文件, 解压, 按照README.txt

./configure --with-apxs
make

这里面make后可能出现错误,要检查你的glibc.
比较复杂, 如果一切顺利.
你 到apache-1.3目录下会发现一个mod_webapp.so生成了,copy to apache的libexec目录下, 在httpdconf加入INSTALL.txt中的loadmudle 等语句 ,在指向examples

注意 localhost:8008处的localhost要和你的servername一样.

我已安装正常,对于apache1.3.20 安装tomcat.40的webapp.so目前我发现只有编译原代码. tomcat的webapp.so二进制文件不能用在linux7.0以下.
2)
关于linux7.1下tomcat3.1,3.2的安装

昨天在linux7.1装了tomcat3.1
在装的时候很顺利,tomcat的安装目录是/usr/local/下
但是在启动tomcat的时候,发现有问题,老是说在/usr/bin下没有cut文件,还有就是找不到libjvm.so文件.

后来找到在/bin下有cut文件,拷贝到/usr/bin下后
tomcat启动没提示有什么问题,但是tomcat就显示了一些path,classpath设置,就结束了

不知道tomcat还有什么要设置的

请高手指点

总算把tomcat装好了,原来是jdk1.3的问题
换jdk1.2.2就可以了,估计是jdk1.3对linux7.1的支持有问题


Apache/PHP4/FastCGI/Oracle/MySQL环境

Linux/Apache/PHP4/FastCGI/Oracle/MySQL/+FrontPage 2000
如何集成Linux/Apache/PHP4/FastCGI/Oracle/MySQL环境

张宏 （maczh@sina.com）

一. 准备工作

要实现将以上环境集成,必需先准备好以下软件包:

(一)数据库的Perl接口

1.perl5的Oracle数据库DBI驱动程序:DBD-Oracle-1.03.tar.gz

2.perl5的通用数据库接口程序:DBI-1.13.tar.gz

3.perl5的MySQL数据库DBI驱动程序:Msql-Mysql-modules-1.2209.tar.gz

(二)Oracle数据库

4.Oracle 8iR2(8.1.6) for Linux安装盘:oracle8161.tar.gz

(三)MySQL数据库

5.MySQL 3.22.32服务器程序包:MySQL-3.22.32-1.i386.rpm

6.MySQL客户端程序包:MySQL-client-3.22.32-1.i386.rpm

7.MySQL开发包(头文件/库文件):MySQL-devel-3.22.32-1.i386.rpm

8.MySQL共享库程序包:MySQL-shared-3.22.32-1.i386.rpm

(四)Apache服务器

9.Apache 1.3.12源码包:apache_1.3.12.tar.gz

(五)PHP模块

10.PHP 4.0.0源码包:php-4.0.0.tar.gz

(六)FastCGI模块

11.FastCGI模块源码包:mod_fastcgi_2.2.4.tar.gz

12.FastCGI的perl开发模块:FCGI-0.53.tar.gz

二. 安装Oracle客户端

由于Oracle 8.1.6是在XWindows下安装的，所以必须是事先配置好XWindow,如果你的显卡不支持XWindow,也可以用exceed进行远程安装(这里不提远程如何安装).

安装Oracle 8.1.6 for Linux详细参见

在此简单列出操作过程:

(一)设置环境变量:

在/etc/profile中加入:

export ORACLE_HOME=/opt/oracle8i/u01

export ORACLE_BASE=/opt/oracle8i

export ORACLE_OWNER=oracle

export ORACLE_SID=ORCL

export ORACLE_TERM=ansi

export PATH=$PATH:$ORACLE_HOME/bin

export LD_LIBRARY_PATH=$ORACLE_HOME/lib

export ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data

export NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"

(二)建立oracle组和用户

#/usr/sbin/groupadd dba

#/usr/sbin/useradd -g dba oracle

#/usr/bin/passwd oracle

(三)创建$ORACLE_HOME目录

#mkdir /opt

#mkdir /opt/oracle8i

#mkdir /opt/oracle8i/u01

#chown -R oracle.dba /opt

(四)安装Oracle 8iR2

以oracle用户登录,解开Oracle安装包:

$tar zxvf oracle8161.tar.gz

$startx 启动XWindow界面,并打开一个rxvt终端窗口

$cd Oracle8iR2

$./runInstaller

此时出现Oracle安装界面,在安装时选择安装Client/Application User

(如果Oracle服务器不在本机上运行,另有专用机器),安装完毕后配置SQL*Net8并

测试连接远程服务器通过即可.

三. 安装MySQL服务器和客户端

以root身分进入,安装MySQL各个包:

#rpm -ivh MySQL-3.22.32-1.i386.rpm

#rpm -ivh MySQL-client-3.22.32-1.i386.rpm

#rpm -ivh MySQL-devel-3.22.32-1.i386.rpm

#rpm -ivh MySQL-shared-3.22.32-1.i386.rpm

四. 安装Perl的数据库接口模块

以root身分进入,然后执行:

#tar zxvf DBI-1.13.tar.gz

#cd DBI-1.13

#perl Makefile.PL

#make

#make test

#make install

#cd ..

#rm -rf DBI-1.13

#

#tar zxvf DBD-Oracle-1.03.tar.gz

#cd DBD-Oracle-1.03

#perl Makefile.PL

#make

#make test

#make install

#cd ..

#rm -rf DBD-Oracle-1.03

#

#tar zxvf Msql-Mysql-modules-1.2209.tar.gz

#cd Msql-Mysql-modules-1.2209

#perl Makefile.PL

选择1(MySQL)和y(支持Mysql.pm)

#make

#make test

#make install

#

五. 安装Apache+PHP+FastCGI

(一)解开Apache/PHP/FastCGI包:

#tar zxvf apache_1.3.12.tar.gz

#tar zxvf php-4.0.0.tar.gz

#tar mod_fastcgi_2.2.4.tar.gz

(二)编译PHP4

配置apache编译参数

#cd apache_1.3.12

#./configure --prefix=/usr/local/apache

配置PHP编译参数

#cd ../php-4.0.0

#./configure --with-apache=../apache_1.3.12 \

> --with-mysql \

> --with-oracle=$ORACLE_HOME \

> --with-oci8=$ORACLE_HOME \

> --enable-track-vars

编译PHP模块:

#make

#make install

创建php.ini参数文件

#cp php.ini-dist /usr/local/lib/php.ini

#cd ..

(三)添加FastCGI模块:

#mv mod_fastcgi_2.2.4 apache_1.3.12/src/modules/fastcgi

(四)编译安装Apache

#cd apache_1.3.12

配置编译参数

#./configure --prefix=/usr/local/apache \

> --activate-module=src/modules/php4/libphp4.a \

> --activate-module=src/modules/fastcgi/libfastcgi.a

编译Apache

#make

安装Apache

#make install

(五)关闭原有系统自带的Apache

#/etc/rc.d/init.d/httpd stop

(六)配置Apache自身参数:

1.编辑/usr/local/apache/conf/httpd.conf文件,修改以下参数:

ServerName host.mydomain.name

DocumentRoot "/home/httpd/html"

Options Indexes FollowSymLinks MultiViews Includes

AllowOverride None

Order allow,deny

Allow from all

ScriptAlias /cgi-bin/ "/home/httpd/cgi-bin/"

AllowOverride None

Options None

Order allow,deny

Allow from all

DirectoryIndex index.html index.phtml index.php index.htm index.shtml index.fcgi

2.修改自启动链接

#cd /etc/rc.d/init.d

#ln -fs /usr/local/apache/bin/apachectl httpd

(七)配置PHP4.0参数:

1.修改/usr/local/apache/conf/httpd.conf文件,修改以下参数:

增加一行:

AddType application/x-httpd-php .php .phtml .php3

2.修改/usr/local/apache/bin/apachectl脚本,使启动支持中文ORACLE环境:

在文件中66行("start)")下面加入几行:

export ORACLE_HOME=/opt/oracle8i/u01

export ORACLE_BASE=/opt/oracle8i

export ORACLE_SID=ORCL

export LD_LIBRARY_PATH=$ORACLE_HOME/lib

export ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data

export NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"

3.修改/usr/local/apache/conf/srm.conf以在CGI程序中使用环境变量:

PassEnv ORACLE_HOME

PassEnv ORACLE_BASE

PassEnv LD_LIBRARY_PATH

PassEnv NLS_LANG

PassEnv ORACLE_SID

PassEnv PATH

(八)配置FastCGI执行环境:

1.修改/usr/local/apache/conf/httpd.conf文件,修改以下参数:

增加几行:

############ FastCGI Configures Begin ##########################

AddHandler fastcgi-script .fcg .fcgi .fpl

SetHandler fastcgi-script

Order deny,allow

Allow from all

Options ExecCGI Indexes Includes

############### FastCGI Configure End ###########################

2.创建fcgi的执行目录

#mkdir /home/httpd/html/fcgi

3.安装FCGI的Perl运行模块:

#tar zxvf FCGI-0.53.tar.gz

#cd FCGI-0.53

#perl Makefile.PL

#make

#make install

六.启运并测试

1.启动Apache服务器:

#/etc/rc.d/init.d/httpd start

2.编写PHP测试程序:

第一个测试程序:/home/httpd/html/t1.php

内容:

<? phpinfo() ?>

第二个测试PHP与Oracle连接的PHP程序(表已经建好):

<?
$conn=OCIlogon("username","password","dblink");
$stmt=ociparse($conn,"insert into testtable (name,id) values ('中文测试',15)");
ociexecute($stmt);
$stmt=ociparse($conn,"select name from testtab where id=15");
ocidefinebyname($stmt,"NAME",&$nick);
ociexecute($stmt);
ocifetch($stmt);
echo "my name is $nick";
?>

查看是否为中文输出

第三个测试PHP与MySQL连接的PHP程序(表已经建好):

<?
$conn=mysql_connect("host","username","password");
mysql_query("insert into testtable (name,id) values ('中文测试',15)");
$result=mysql_query("select name from testtab where id=15");
$query_data=mysql_fetch_row($result);
$nick=$query_data[0];
echo "my name is $nick";
?>

3. 编写FastCGI的测试代码: /home/httpd/html/fcgi/test.fcgi

#!/usr/bin/perl

use FCGI;

use DBI;

$dbname="oracle";

$user="user";

$passwd="password";

$dbh="";

while(FCGI::accept()>=0) {

&parse_form();

$id=$FORM{'id'};

$para=$FORM{'para'};

print "Content-type: text/html\n\n";

print "\n";

if (!$dbh){

print "no oracle, need to connect\n";

$dbh = DBI->connect("dbi:Oracle:$dbname",$user,$passwd);

}else{

print "OK, oracle aleady connected\n";

}

$sth=$dbh->prepare("select name from testtable where id=15");

$sth->execute;

@recs=$sth->fetchrow_array;

$sth->finish;

print "参数id=".$id." and my name is @recs[0] \n";

print "参数para=".$para."\n";

}

####传入参数处理部分#######

sub parse_form {

my($buffer);

my($pairs);

my(@pairs);

my($name);

my($value);

my $meth = $ENV{'REQUEST_METHOD'};

    if ($meth eq 'GET' || $meth eq 'HEAD') {

$buffer = $ENV{'QUERY_STRING'};

}

elsif ($meth eq 'POST') {

read(STDIN, $buffer, $ENV{'CONTENT_LENGTH'});

}

undef %FORM;

@pairs = split(/&/, $buffer);

foreach $pair (@pairs) {

($name, $value) = split(/=/, $pair);

$value =~ tr/+/ /;

$value =~ s/%([a-fA-F0-9][a-fA-F0-9])/pack("C", hex($1))/eg;

$value =~ s///g;

    if ($allow_html != 1) {

$value =~ s/]|\n)*>//g;

}

$FORM{$name} = $value;

}

}

测试看看FastCGI是否正常执行了

Linux+Apache 1.3.9+MySQL+PHP4+FrontPage 2000

[晏子　编译]

    本文介绍如何安装Apache以支持MySQL、PHP4、FrontPage2000服务器扩展和虚拟主机功能，本文的安装步骤在Redhat 7.0和Mandrake 7.2上测试通过，所以应该适用于任何Linux发行，它也适用于任何形式的*nix系统，只要下载不同的软件包。

一、需求

1、一个基于Intel并安装了TCP/IP和libc6的Linux系统。如果Apache或MySQL已经安装好了，建议用软件包管理程序或手工删除它们。

2、需要安装的软件包，它包括：Apache 1.3.19、MySQL服务器、PHP4和FrontPage 2000扩展、Apache支持FrontPage 2000扩展的补丁、最新的gcc编译器及其相关库。

二、准备安装

1、下载软件包

下载下列软件包到/download目录下。

Apache 1.3.19
MySQL Server
PHP4
FrontPage 2000 Extensions
2、解压缩源代码

将所有/download目录下的源代码包（除了frontpage要解压缩到/use/local目录下）解压缩：

tar zxfv apache_1.3.19.tar.gz
tar zxfv fp40.linux.tar.gz -C /usr/local
tar mysql-3.23.32.tar.gz
tar zxfv php-4.0.4pl1.tar.gz

三、安装MySQL

第一步先要安装MySQL，因为要安装支持MySQL的PHP，然后安装支持PHP的Apache，下面是具体步骤。

1、设置用户和组

首先，系统增加名为mysql的拥护和组。

groupadd mysql
useradd -g mysql mysql

2、配置并构建MySQL

进入目录/download/mysql-3.23.32并运行configure和make程序。如果想把数据库存在非缺省目录/usr/local/mysql/var/，则为configure指定选项localstatedir=/your_path。

cd mysql-3.23.32
./configure --prefix=/usr/local/mysql
make
make install

MySQL现在已经安装到/usr/local/mysql目录下。目前还没有一个数据目录，现在要运行MySQL自带的脚本创建目录并安装测试数据库。

scripts/mysql_install_db
在启动守护程序前，改变文件的属权，否则守护程序不能运行。

chown -R mysql.mysql /usr/local/mysql
3、启动MySQL守护程序

现在准备启动守护程序。safe_mysqld等价于tcpwrapper for MySQL，tcpwrapper常用于包装inet的服务以增加安装性。

/usr/local/mysql/bin/safe_mysqld --user=mysql &
4、设置root用户口令并在引导时启动MySQL。

现在MySQL正在运行，可以用mysqladmin设置root用户口令。

/usr/local/mysql/bin/mysqladmin -u root -p password yourpass
最后一步是需要确保MySQL能在系统重起时启动。编辑/etc/rc/d/rc.local文件，并在末尾加入/usr/local/mysql/bin/safe_mysqld --user=mysql & 。或者可以编写一个启动/停止的脚本并符号链接到适当的运行级别。

四、为Apache打补丁

在继续下列步骤前，我们必须给Apache打上FrontPage补丁，将FrontPage补丁复制到Apache源代码目录下并做一个到FrontPage的currentversion的符号链接。

cd /usr/local/frontpage/
ln -s version4.0 currentversion
cd currentversion/apache-fp
cp fp-patch-apache_1.3.12 /downloads/apache_1.3.19

1、打补丁

现在在Apache源代码目录下打上FrontPage补丁。这将需要将二进制补丁放在你的目录下。

patch -p0 < fp-patch-apache_1.3.12
这将在apache源代码目录下生成一个mod_frontpage.c文件，它需要复制到extras模块上。

cp fp-patch-apache_1.3.12 src/modules/extra/
2、运行一个简单的apache配置

现在运行一个简单的配置，等一下再运行更高级的配置。

/downloads/apache_1.3.19/configure
五、安装PHP4

PHP4是一种服务器端、跨平台、HTML嵌入式脚本语言，它赋予我们开发动态网站的能力，并能很容易地与MySQL服务器接口。

1、配置PHP4以支持MySQL和Apache

你将安装支持位于/usr/local/mysql目录下的MySQL的PHP4。

cd /downloads/php-4.0.4pl1
./configure --with-mysql=/usr/local/mysql --with-apache=/downloads/apache_1.3.19 --enable-track-vars

2、配置apache支持MySQL和Apache

现在运行make和make install来编译Apache所需的文件。

make
make install

六、安装Apache服务器

Apache是本文的核心，所以请仔细安装下列步骤进行。现在PHP已经构建好，你将在Apache源代码目录下找到一个新目录../apache_1.3.19/src/modules/php4。现在我们再次配置apache，但这时对PHP和FrontPage的支持已经静态地构建好了。

1、创建符号链接和目录结构

创建符号链接/usr/local/httpd指向/usr/local/apache-1.3.x，这样你可以构建一个新版本apache，然后在必要时重新链接。用下列命令：

mkdir /usr/local/apache-1.3.19
ln -s /usr/local/apache-1.3.19 /usr/local/httpd

2、配置Apache支持ForntPage和PHP4

现在，我们可以用--prefix=/usr/local/httpd配置apache，它是指向apache-1.3.19的符号链接。要知道，src/modules/php4/libphp4.a毫不存在，但将要生成。要注意用--add-module加入FrontPage，--activate-module加入PHP。现在运行make和make install以构建并安装Apache。其它无关紧要的是httpd.conf放在哪里，有些人喜欢放在/etc目录下。如果像这样做，加上--localstatedir=/etc即可。

cd /downloads/apache_1.3.19
./configure --prefix=/usr/local/httpd
--activate-module=src/modules/php4/libphp4.a
--add-module=src/modules/extra/mod_frontpage.c

3、构建Apache

运行make将创建httpd二进制代码。如果你覆盖一个老版本的服务器，你要做的就是make，然后将httpd二进制代码从bin目录夫知道现有的httpd产品目录即可。这里建议你有一个全新的安装，因为这样非常容易地从原先的安装迁移www数据和conf文件。

make
make install
七、修改httpd.conf

很好，你已经安装好了Apache，并支持FrontPage、PHP和MySQL。现在整理一下其他事情以便能工作得更好。首先修改一些httpd.conf配置。

1、增加PHP标记

为了让Apache处理PHP扩展名，必须加入该类型。确保你把配置文件中的下列两行去掉注释。如果这两行不存在，必须手工添加。

AddType application/x-httpd-php .php
AddType application/x-httpd-php-source .phps

2、改变Directory Index

改变Directory Index支持以增加index.php和index.shtml。这完全作为参考，但如果你的网站严格地用SSI或PHP编写，那么有这些额外的Directory Index文件将避免参照index文件的全路径，相反，你可以简单地键入http://www.virtual.com而不是http://www.virtual.com/index.php。

DirectoryIndex index.php index.shtml index.html index.htm
3、修改目录权限

对配置文件几个重要的修改是DocumentRoot和Directory的权限。修改DocumentRoot指向你的缺省网页文件，如

DocumentRoot /www/httpd
现在对它修改目录权限是的FrontPage能够用其.htaccess文件覆盖它们。AllowOverride从None改为All。

Options Indexes FollowSymLinks MultiViews
AllowOverride All
Order allow,deny
Allow from all

八、运用FrontPage Extensions到根网站

我们已经完成了支持PHP和MySQL的Apache，剩下的事情就是FrontPage服务器扩展了，你可能用或不用于你的网站。但你有多人需要编辑网站并且不是每个人都熟悉FTP和HTML时，它就有用了。

1、运行fpsrvadm.exe

我们把FrontPage扩展用于网站根目录（/www/httpd）。

cd /usr/local/frontpage/currentversion/bin/
并运行fpsrvadm.exe安装扩展到根目录。

./fpsrvadm.exe -o install

: 0 for apache (do not choose apache-fp)
: /usr/local/httpd/conf/httpd.conf (patch to server config file)
: ENTER (Just hit enter for a blank multi-hosting)
: apache (user owner of DocumentRoot (i.e. /www/httpd))
: web (group owner of DocumentRoot (i.e. /www/httpd))
: myuser (frontpage login)
: mypass (frontpage password)

注意，这里使用用户“apache”和“web”组。对于虚拟域，对每个虚拟域分开用户，但组总是“web”。

2、创建其他FrontPage用户

现在简单地为FrontPage提供一个管理员账号及该账号口令，它将是访问FrontPage的登陆名和口令。如果你保持这些与ftp登陆同步，可能更好些。你总能回来并运行./fpsrvadm.exe并用Option 7增加一个用户并输入正确的信息。或者你可以修改包含用户和加密口令的/_vti_pvt/service.pwd文件，如果需要生成一个加密口令，使用：

htpasswd temp.pass.file
Enter Password : **********
pico temp.pass.file
:3923kw#$sdfk32$

然后复制用户和加密口令到service.pwd并且该用户即可登陆，你也必须包用户组成一组，这样对网站的修改可以进行了，这通过编辑/_vti_pvt/service.grp完成。

pico _vti_pvt/service.grp
administrators : administrator
authors :

增加新用户到适当的修改网站的组中。现在尝试通过FrontPage登陆，用户再增加"author"或"administrator"后应该有权编辑了。

九、用FrontPage支持创建虚拟网站

这个过程与把它们加入根网站相同，唯一的差别是当运行fpsrvadm.exe时要提供一个muulti-hosting名而不是指打回车。多宿主名将是定义在中的ServerName。

首先，编辑htppd.conf并去掉NameVirtualHost行的注释。如果你在这台机器上只有一个IP地址，那么表中第一个虚拟主机将是你的根网站。如果有两个IP地址，那么你的根网站可能在192.168.0.1并且虚拟网站可能在192.168.0.2，这可以保持根网站的完整。

if you have 1 ip address
NameVirtualHost *
if you have a separate ip address just for your virtual webs
NameVirtualHost 192.168.0.2

确保如果你有多个IP地址，告诉Apache监听哪个IP地址，或用Listen *让Apache监听列在ifconfig中的所有接口。

# to make apache listen on all ip addresses assigned to the box
Listen *

# Listen for root web
Listen 192.168.0.1

# Listen for virtual webs
Listen 192.168.0.2

现在你已经知道该信息，假如一个虚拟网站。

ServerAdmin root@virtual.com
ServerName virtual.com
DocumentRoot /www/virtual.com/public_html
CustomLog logs/virtual.com/access_log combined
ScriptAlias /cgi-bin /www/virtual.com/public_html/cgi-bin/

AllowOverride All
Options Indexes FollowSymLinks Includes ExecCGI MultiViews
Options All
order allow,deny
allow from all

AllowOverride None
Options ExecCGI FollowSymLinks INcludes

LogFormat Combined
ServerAlias virtual.com *.virtual.com

首先，在这个虚拟域定义中有几点说明。

# To make this virtual web listen on all interfaces and all ports

# If you have a separate IP # for virtual hosting

# To listen only on port 80 on 192.168.0.2

# To listen only on port 80 on all interfaces

这里只使用，因为在机器上只有一个IP地址。记住，这的确破坏了你的根网站（/www/httpd）并使得第一个定义称为你的根网站。

在有人到达你的IP地址时，他们首先被第一个虚拟网站服务，而不是根网站。这是为什么机器要有两个IP地址并将根网站置于各自独立的IP地址的原因。或者你有整个C类地址，或一个子网，那么你可以将每一个网站赋予其自己的IP地址，这样会好些。

在虚拟主机中的定义允许FrontPage用.htaccess文件改写权限。

好了，现在你已经把一个虚拟主机加到了httpd.conf中，名为"virtual.com"，保存httpd.conf并运用FrontPage扩展。

cd /usr/local/frontpage/currentversion/bin
./fpsrvadm.exe -o install

: 0 for apache (do not choose apache-fp)
: /usr/local/httpd/conf/httpd.conf (patch to server config file.
: www.virtual.com (the name of ServerName in )
: apache (user owner of DocumentRoot (i.e. /www/httpd))
: web (group owner of DocumentRoot (i.e. /www/httpd))
: myuser (frontpage login)
: mypass (frontpage password)

注意，对虚拟网站，为每一个网站在机器上创建一个用户。

本例中用户和组为：

: virtual (virtual.com的用户)
: web (所有网站的用户组)

用户和组必须在运行./fpsrvadm.exe安装FrontPage扩展前在/etc/passwd和/etc/group中是有效的。现在FrontPage扩展已经被复制到了你的新虚拟网站的DocumentRoot（如/www/virtual/public_html）。

你可以改变该目录并检验再次有一个_vti_文件夹。

现在尝试通过FrontPage连接新虚拟网站，Open Web -> http://www.virtual.com。

它应该询问登陆名和口令，如果没问题，你可以增加更多的虚拟主机到httpd.conf中，然后以同样的方式实现FrontPage扩展。

十、测试文件

最后的步骤是测试PHP、CGI和SSI。你可以用下列文件或创建自己的。通过FTP上传文件到网站上，然后点击浏览器测试它们。

一、PHP测试文件：test.php

Oracle8.1.6i+ Apache1.3.14+PHP4.0.3完全安装实例

在redhat 6.2下 Oracle8.1.6I+ APACHE1.3.14+PHP4.0.3完全安装实例
1． 本文目的
● 在redhat下安装ORACLE8数据库服务器
● 安装apache,并支持wml
● 安装PHP
2． 安装前的准备软件：
Redhat 6.2安装光盘
Oracle8.161.tar.gz 下载地址：
http://freeware.online.sh.cn/mirrors/LinuxApps/Database/Oracle下的oracle8.161.tar.gz
Java运行时刻环境（JRE）下载地址：
ftp://165.21.84.42/pub/j2sdk/1.3.0/xzc233fcslnx/下的j2sdk-1_3_0-linux-rpm.sh
Apache 1.3.14 下载地址：
http://www.apache.org/dist/apache1.3.14.tar.gz
php4.0.3 pl1 下载地址：
http://www.php.net/do_download.php?download_file=php- 4.0.3pl1.tar.gz&source_site=www.php.net
3． 安装oracle前的准备
● 安装JRE1.3.0
[root@wapdb /root]# #以root身份登录
[root@wapdb /root]# chmod 755 j2re-1_3_0-linux-rpm.sh #改变j2re-1_3_0-linux-rpm.sh
的权限
[root@wapdb /root]#./ j2re-1_3_0-linux-rpm.sh #运行j2re-1_3_0-linux-rpm.sh在同级目录
下可得到JRE的RPM包。
[root@wapdb /root]# rpm –i j2re-1_3_0-linux-rpm #安装JRE1.3.0:
● 创建oracle。apache用户组：
执行以下命令：
[root@wapdb /root]#　　　　　　　　　　　　　　 #以root方式登录
[root@wapdb /root]# groupadd oracle　　　　　　　　#创建oracle组
[root@wapdb /root]# useradd oracle -g oralce　　　 #在oracle组中建新用户oracle
[root@wapdb /root]# useradd apache -g oralce #在oracle组中建新用户apache
[root@wapdb /root]# passwd oracle　　　　　　　 #修改oracle用户口令
注：oracle组和oracle用户是oracle安装需要的
注：创建oracle用户后，linux系统自动在/home目录下创建/home/oracle目录，给oracle用户使用，oracle用户对此目录拥有所有的权限。
[root@wapdb /root]# cd /home/oracle
[root@wapdb /root]# vi .bash_profile　　　　#编辑.bash_profile文件，并输入以下内容
# Setup ORACLE environment
NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"; export NLS_LANG
JAVA_HOME=/usr/java/jre1.3
BASH_ENV=$HOME/.bashrc
ORACLE_HOME=/data/oracle/app/oracle/product/8.1.6
export ORACLE_HOME
ORACLE_SID=wap
export ORACLE_SID
# Set up the search paths:
PATH=$PATH:$HOME/bin:$JAVA_HOME/bin:$ORACLE_HOME:$ORACLE_HOME/bin:$ORACLE_HOME/d
bs
export USERNAME BASH_ENV PATH ORACLE_HOME JAVA_HOME
4． 安装oracle8I
[root@wapdb /oracle]# exit　　　　　#退出，以oracle用户重新登录，以使设定的环境生效
[oracle@ wapdb/oracle]$
[oracle@ wapdb/oracle]$ tar zxvf oracle8161_tar.gz　　　#解压oracle压缩包到当前目录
[oracle@ wapdb/oracle]$ startx　　　　　#启动X-windows后，启用一个终端（xterm），
(图形窗口）在该终端中运行runInstaller
[oracle@wapdb /oracle]$ cd Oracle8iR2 #进入解压缩的目录
[oracle@wapdb /Oracle8iR2]$ ./runInstaller #执行oracle安装程序。

这时可以看到用jre运行的的图形化的OUI的欢迎画面，按照提示继续安装进程（这里我们可以选择典型安装）：
Welcome：
按next
File Locations：
按next
UNIX Group Name：
oracle，按next
出错，提示要以root权限运行“/data/oracle/app/oracle/product/8.1.6/orainstRoot.sh
CTRL+ALT+F2，打开一个新的控制台（字符窗口）
以root登录
[root@wapdb /root]# cd /data/oracle/app/oracle/product/8.1.6
这时，/data/oracle/app/oracle/product/8.1.6目录下有一个文件orainstRoot.sh，运行它
[root@wapdb /8.1.6]# sh orainstRoot.sh
CTRL+ALT+F7，回到安装界面（图形窗口）
按Retry按钮，就可以继续安装了，
Available Products：
选Oracle8i Enterprise Edition 8.1.6.1.0，按next
Installation Types：
选Typical（540MB），按next，这时，屏幕右上角出现一个进度标尺
Database Identification：
Global Database Name：输入wap（可以任意）
SID：保留wap
按next
Database File Location：
任意目录，本例设为“/data/oracle/app/oracle/product/8.1.6/data”，按Next，这时，屏幕右上角进度标尺继续前进
出现Summary，对你想要安装的产品作一个总结
按Install，出现Install画面，等待... 可以看到窗口底部提示的安装等log文件目录，可供以后查询。
弹出Setup Privileges窗口
提示：在安装继续进行之前，需要以root运行一个脚本
“/data/oracle/app/oracle/product/8.1.6/root.sh”，
CTRL+ALT+F2，回到刚才运行的第2个终端窗口
以root权限执行该文件，
[root@wapdb /8.1.6]# sh root.sh
屏幕显示：
Enter the full pathname of the local bin directory:[/usr/local/bin]:
回车
系统开始执行一些动作，执行完毕，CTRL+ALT+F7按返回OUI，按OK。
Database Creation Progress开始，逐步进行以下4个过程
Creating and starting Oracle instance
Copying database files
Initializing database
Database creation completed
以上4个过程完成，弹出Oracle Database Configuration Assistant Alert窗口，
提示：数据库创建完成，告诉你数据库的一些基本信息
global databse name：wap
database system identifier（SID）：wap
SYS account password：change_on_install
SYSTEM account password：manager
按ok
End of Installation，按Exit退出OUI，完成安装。
到此，已经完成了数据库服务器的安装，下一步进行web/wap服务器的安装。
5． 安装ORACLE客户端
（该步骤适合与数据库服务器与WEB服务器安装在不同机器上，若为同一台机器直接执行 第6步）
重复第3步
在第4步的安装中选择“客户端安装”步骤大致相同。
配置tnsnames.ora文件（可以在/$ORACLE_HOME/bin/运行netasst命令启动OUI来配置）。最快的方法是COPY数据库服务器端的tnsnames.ora到$ORACLE_HOME/network/admin中。
以ORACLE用户登录
[oracle@wapserver /]$ cd $ORACLE_HOME/network/admin
[oracle@wapserver admin]$ ftp xxx.xxx.xxx.xxx #使用FTP登录oracle服务器，以ORACLE
并使用oracle用户.
ftp>cd /data/oracle/app/oracle/product/8.1.6/network/admin
ftp>get tnsnames.ora
ftp>bye
6． 配置apache_1.3.14
[root@wapdb /local]# tar zxvf apache1.3.14.tar.gz #解压apache
[root@wapdb /local]# cd /usr/local/apache_1.3.14 #进入apache的解压目录。
[root@wapdb /local]# ./configure --prefix=/usr/local/apache
5. 安装 PHP4
[root@wapdb /local]# tar zxvf php- 4.0.3pl1.tar.gz #解压php
[root@wapdb /local]# cd php-4.0.3
[root@wapdb /php-4.0.3]#./configure --with-apache=../apache_1.3.14 \
--with-oracle=/data/oracle/app/oracle/product/8.1.6 \
--with-oci8=/data/oracle/app/oracle/product/8.1.6 \
--enable-track-vars
[root@wapdb /php-4.0.3]# make #编译
[root@wapdb /php-4.0.3]# make install # 安装
[root@wapdb /php-4.0.3]# cp php.ini-dist /usr/local/lib/php.ini #拷贝ini文件到lib目录
6．安装apache
[root@wapdb /php-4.0.3]# cd /usr/local/apache_1.3.14
[root@wapdb/apache_1.3.14]# ./configure --prefix=/usr/local/apache \
--activate-module=src/modules/php4/libphp4.a
[root@wapdb /apache_1.3.14]# make
[root@wapdb /apache_1.3.14]# make install
7．配置apache
[root@wapdb /apache_1.3.14]# cd /usr/local/apache/conf
[root@wapdb /conf]# vi httpd.conf
修改httpd.conf文件
以下几行去掉注释：
ServerName http://。。。。。。。 这个一定要去掉注释
Listen XXX.XXX.XXX:8888(其中xxx.xxx.xxx为域名，或者IP地址）
AddType application/x-httpd-php .php
AddType application/x-httpd-php-source .phps

修改以下两行：
User apache
Group oracle
[root@wapdb /conf]# vi mime.types
修改mime.types文件, 添加WAP支持,添加如下行:
text/vnd.WAP.WML WML
text/vnd.WAP.WMLscript WMLC
image/vnd.WAP.WBMP WMLP
application/vnd.WAP.WMLC WMLC
application/vnd.WAP.WMLCSRIPTC WMLSC
系统的安装已经完成，下面对环境进行测试：
8．启动数据库：
在数据库服务器里运行：
[oracle@wap /bin]$ svrmgrl
SVRMGR> connect internal
Connected.
SVRMGR> startup
ORACLE instance started
9．启动监听器
[oracle@wapdb /bin]$ lsnrctl
LSNRCTL> start
LSNRCTL> exit
这时，oracle数据库已经安装成功，并且数据库已经启动运行，可以试一下
[oracle@wapdb /bin]$sqlplus system/manager@wap

出现以下信息：
SQL*Plus: Release 8.1.6.0.0 - Production on Fri Oct 26 20:20:56 2000
(c) Copyright 1999 Oracle Corporation. ALL rights reserved.
Connected to:
Oracle8i Enterprise Edition Release 8.1.6.1.0 - Production
With the Partitioning option
JServer Release 8.1.6.0.0 - Production
SQL> show user
USER is "SYSTEM"
SQL>
SQL> exit
10．启动Apache了
[oracle@wapdb /root]# cd /usr/local/apache/bin
[oracle@wapdb /root]# apachectl start

11．测试PHP
htdocs目录下编辑一个test.php
phpinfo();
?>
通过浏览器浏览该网页，可以看到PHP的环境参数，如果找到有oricle和orci8的支持，说明PHP已经支持ORACLE和OCI8。

12．测试PHP与ORACLE的连接
//文件名为test.php.
$conn=ocilogon("system","manager","test");
if($conn)
echo success;
else
echo fail;
?>
如果该程序返回成功标志，则表明连接成功。
13．测试时候支持WML
在htdocs目录下编辑test.wml

"http://www.wapforum.org/DTD/wml_1.1.xml">

hello word!

在任何其他一台win9x的机子上使用WAP模拟器浏览该网页，应该出现”hello word”。
现在整个环境已经调试完成，可以利用PHP+ORACLE8i进行动态html或wml的开发了！

阅读：956次


Apache
Compiling sources

./configure \

--prefix=/usr/local/apache \ //install dir

--activate-module=src/modules/php4/libphp4.a \ //to work with PHP

--with-perl=/usr/local/perl/bin/perl \ //to work with Perl

--with-port=8000 \ //default http port

--enable-module=so //enabling Dynamic Modules Loading
Modify /usr/local/apache/bin/apachectl to support Chinese character in ORACLE

add the following below line 66 ("start)"):

export ORACLE_HOME=/opt/oracle8i/u01

export ORACLE_BASE=/opt/oracle8i

export ORACLE_SID=ORCL

export LD_LIBRARY_PATH=$ORACLE_HOME/lib

export ORA_NLS33=$ORACLE_HOME/ocommon/nls/admin/data

export NLS_LANG="SIMPLIFIED CHINESE_CHINA.ZHS16CGB231280"

Modify /usr/local/apache/conf/srm.conf in order to use environment variables in CGI programs:

PassEnv ORACLE_BASE

PassEnv LD_LIBRARY_PATH

PassEnv NLS_LANG

PassEnv ORACLE_SID

PassEnv PATH


Apache
如何让Apache 支持 python?

The easiest way is treat python programs as scripts. You can use:

AddHandler cgi-script .py

for faster execution, you can install py-apache or mod_python.


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综合开发平台

Instant ASP - http://www.halcyonsoft.com/ 在非IIS服务器与Windows平台上利用ASP开发网站

RJAX - 通过EJB,JavaBean访问ActiveX 与COM组件
OpenASP - http://www.activescripting.org , http://www.openasp.com 在非IIS服务器与Windows平台上利用ASP开发网站
ChiliASP - www.chilisoft.com， ASP pages on non-Microsoft servers
应用服务器
www.bea.com: WebLogic
www.IBM.com:WebSphere
www.silverstream.com: SilverStream
www.allaire.com: JRun
minij2ee
Apusic
Jakarta Tomcat/Cocoon
Resin
IAS - Inprise Application Server
IONA
JBoss
JONA
Orbix

Rose
Web服务器
Apache
Sambar
IIS
iPlanet
综合开发平台

Instant ASP - http://www.halcyonsoft.com/ 在非IIS服务器与Windows平台上利用ASP开发网站

RJAX - 通过EJB,JavaBean访问ActiveX 与COM组件
OpenASP - http://www.activescripting.org , http://www.openasp.com 在非IIS服务器与Windows平台上利用ASP开发网站
ChiliASP - www.chilisoft.com， ASP pages on non-Microsoft servers


Chili!Soft ASP
*IMPORTANT INSTALLATION NOTE*: Be sure to install Sun ChiliSoft ASP 3.6 into its own directory. Failure to do so could result in the loss of existing files contained in the installation directory. Things you will need in place before you begin installation of Sun Chili!Soft ASP for Linux are: -- A Web server that is already installed, but not running. -- Administrator rights for the computer you're installing Sun Chili!Soft ASP for Linux on.
Recompile:

1) mkdir -p /usr/local/src/casp/./asp/modules/linux2_optimized/apache_1.3.22/standard

2)cp <generated builddir>/modu_casp2.so /usr/local/src/casp/./asp/modules/linux2_optimized/apache_1.3.22/standard

3)rerun the installer: HASH(0X819fbc8) -{asphome}/INSTALL/install


Cocoon

Cocoon 1.8.2

To make visible to Tomcat, copy the cocoon.jar under /bin and all .jar files under /lib to Tomcat's /lib and /common/lib directories


Cocoon

Servlet/JSP/XML Frameworks介绍

现在，已经有众多的基于Java的开源Web Framework，让我们能更加容易构造Web应用。我在这里给大家作一个简单的
介绍。

Cocoon - 基于XML的Web内容发布
-----------------------------
Cocoon是采用100%纯Java编写的一个内容发布框架。Cocoon让你能采用W3C的最新技术(DOM、XML、XSL)来提供Web内容。

新的Cocoon模式能将文档内容、样式、处理逻辑进行完全的分离，允许这三层能独立地设计、创建和管理，从而减少了管理开销，加强了工作的重用性，减少了开发时间。

下载地址：http://xml.apache.org/cocoon

Xang - 快速开发动态网页
-----------------------
Xang能整合不同的数据源，让你能快速地开发数据驱动的、跨平台的Web应用。Xang体系结构能将数据、逻辑和表示完全划清。Xang基于开放的工业标准，例如HTTP、XML、XSL、DOM、ECMAScript(JavaScrip)。

下载地址：http://xml.apache.org/xang

Slide - 内容管理框架
--------------------
Slide是一个内容管理和集成系统，是一个内容管理底层框架。Slide提供了一个分级的结构，能将内容存储到任意的、分布式的数据仓库。出此之外，Slide还集成了安全、锁定、内容版本和其他一些服务。

下载地址：http://jakarta.apache.org/slide

Struts - 基于MVC设计模式的JSP
-----------------------------
Struts是采用Java Servlet/JavaServer Pages技术，开发Web应用程序的开放源码的framework。

采用Struts能开发出基于MVC(Model-View-Controller)设计模式的应用构架。
Struts有如下的主要功能：

1. 包含一个controller servlet，能将用户的请求发送到相应的Action对象。
2. JSP自由tag库，并且在controller servlet中提供关联支持，帮助开发员创建交互式表单应用。
3. 提供了一系列实用对象：XML处理、通过Java reflection APIs自动处理JavaBeans属性、国际化的提示和消息。

下载地址：http://jakarta.apache.org/struts

Jetspeed - 基于Web的组件
------------------------
Jetspeed是实现了Enterprise Information Portal的开源软件。Jetspeed能从Internet的纵多资源中提取信息，来帮助用户管理大量的数据。这些信息能来自不同的内容类型，从XML到XMTP，到iCalendar这些新协议。

下载地址：http://java.apache.org/jetspeed

Turbine - 基于Servlet的Web应用开发
----------------------------------
Turbine是基于servlet的framework，使有经验的Java开发员能快速地构建web
应用。

使用Turbine，可以通过创建使用特定服务来处理模板的Screen，来集成现有的模板技术（例如Velocity、Webmacro、Java Server Pages(JSP)、FreeMarker、Cocoon）。
下载地址：http://java.apache.org/turbine

各种Framework比较
-----------------
在这些framework中，我觉得Cocoon、Struts和Turbine比较好。这三者各有所
长，Cocoon是最好的XML Framework，Struts是最好的JSP Framework，Turbine是最好的Servlet Framework。


如何在Linux上建立DNS服务器

DNS服务器
如何在Linux上建立DNS服务器

由 root 在 Wednesday January 26, @ 11:00AM 维护加入 (部门: 四通立方网友-OpenView-E-mail：ws_sh@hotmail.com )
已被点击阅读 368 次
一、 假定
本文假定你已对域名服务器 DNS 有基本的了解，如果不是，请参看相关的文裆。
许多DNS的文章都是从DNS原理开始介绍，本人则从使用的角度出发，为Linux的管理员提供一些简单实用的应用实例。

下面假定我们需要建立一台企业网的DNS主服务器，应用条件如下：

（1） 一个C类网段地址 （本例中假定是192.22.33）

（2）企业域名为 my.com，并已注册 （主域名服务器地址 192.22.33.20，主机名为 linux.my.com）

（3）企业网通过路由器与Internet连接

假如你的应用环境与上述条件不同，也请往下看，本文会在上述例子的基础上针对以下情况作修正：

（1） 多个网段

（2） 封闭的内部网

（3） 只能访问局部公共网的情况（如169网、上海热线等）

二、named、/etc/named.boot 和 ndc
DNS 服务器的主体是域名服务器进程 named ，named 启动后向DNS客户机提供域名解析服务，把域名转换成IP地址。
named 启动时需要读取一个初始化文件，缺省情况下是 /etc/named.boot，所以/etc/named.boot 是 named 的基本配置文件。

虽然启动 named 可直接执行 named，在Linux上我们可以使用一个控制 named 的工具 ndc。ndc 可以用于启动、中止、重启动、刷新DNS数据、输出DNS数据等多种调试功能，我在这里推荐大家用这个工具来帮助 DNS 服务器的调试。

有关 ndc 的详细用法，请参看 Linux 有关文档。

三、建立 named 配置文件 /etc/named.boot
/etc/named.boot 是基本的配置文件，但不包含任何 DNS 数据，针对我们前面的假定，我们先建立以下 /etc/named.boot，其内容如下：
;
; boot file for name server
;
directory /var/named

primary my.com db.my
primary 0.0.127.IN-ADDR.ARPA db.127.0.0
primary 33.22.192.IN-ADDR.ARPA db.192.22.33
cache . db.cache
其中以“；”开头的行是注释行，其他各行含义是
（1）diretory /var/named

指定 named 从 /var/named 目录下读取 DNS 数据文件。这个目录用户可自行指定并创建，指定后所有的DNS 数据文件都存放在此目录下。

（2）primary my.com db.my

指定 named 作为 my.com 域的主域名服务器，db.my 文件中包含所有 *.my.com 形式的域名转换数据。

（3）primary 0.0.127.IN-ADDR.ARPA db.127.0.0

指定 named 作为127.0.0网段地址转换主服务器，db.127.0.0 文件中包含了 127.0.0.* 形式的地址到域名的转换数据。（127.0.0网段地址是局域网接口的内部 loopback 地址）

（4）primary 33.22.192.IN-ADDR.ARPA db.192.22.33

指定 named 作为 192.22.33 网段地址转换主服务器，db.192.22.33 文件中包含了所有 192.22.33.* 形式的地址到域名的转换数据。

（5） cache . db.cache

指定 named 从 db.cache 文件中获得 Internet 的顶层“根”服务器地址

要注意（3）（4）两行中的网段地址是倒写的，另外，各个文件名也是可以自行决定的。

四、建立各个 DNS 数据文件
下一步，要按 /etc/named.boot 中的定义，建立各个 DNS 数据文件。
（1）建立正向域名转换数据文件 db.my

根据 /etc/named.boot 的定义，我们在 /var/named 目录下建立 db.my，其中应该包括所有在 my.com 域内的主机节点。但在机器数量较多时，为了调试方便，建议一开始只把几台节点的数据放入文件，待 named 正常工作后再把其他节点的数据补充进去。下面是 db.my的例子：

@ IN SOA linux.my.com. root.linux.my.com. (
199511301 ; serial, todays date + todays serial #
28800 ; refresh, seconds
7200 ; retry, seconds
3600000 ; expire, seconds
86400 ) ; minimum, seconds
NS linux.my.com.
MX 10 support.my.com.

localhost A 127.0.0.1
linux A 192.22.33.20
support2 A 192.22.33.102
hp712 A 192.22.33.160
support A 192.22.33.100
mail MX 10 support.my.com.
MX 20 support2.my.com.
www CNAME hp712.my.com.
ftp CNAME hp712.my.com.
ns CNAME linux.my.com.
其中第一行是 SOA 记录，定义了域名数据的基本信息，依次是 DNS 服务器名、DNS 管理员邮件地址，括号内的第一个数字是文件版本号，每次本文件内容修改后，必须更改此号。其余数字与DNS服务器直接的数据交换有关，在这里我们不需要改动。
括号后面有一条 NS 记录和一条 MX 记录，定义了域名服务器本身的域名和 username@my.com 形式邮件地址所对应的邮件服务器名字。

在此以下是各种域名/地址转换数据，其中 A 记录是 DNS 域名到 IP 地址的记录，是必须有的，以 hp712.my.com 为例，在 A 记录中域 my.com 被省略，只写成 hp712，named 在处理时会根据 named.boot 中的定义自动加上 my.com，而其对应 IP 地址为 192.22.33.160。

另一种记录是 MX 记录。MX 是邮件地址转换记录，本例中定义了将 username@mail.my.com 的邮件地址转换成 username@support.my.com 或 username@support2.my.com，即实际上真正的邮件服务器是 support.my.com 和 support2.my.com，其中 support.my.com 的优先数为 10，support2.my.com 的优先数为 20，所以通常邮件首先被发往优先数小的主机 support.my.com。

还有一些是为方便提供的 CNAME 记录。CNAME 定义了一些主机的别名，比如我们将 hp712.my.com 作为公司的 www 和 ftp 服务器，所以我们提供了 www.my.com 和 ftp.my.com 作为 hp712.my.com 的别名，用户只需要根据习惯就可以访问公司的 www、ftp 服务器了，如果将来我们换用别的主机作 www 和 ftp 服务器，只需要修改 CNAME 记录就可，对用户没有影响。

注意：MX 和 CNAME 记录最后的带域名的主机名后必须带一个“.”

（2）建立反向 DNS 数据文件 db.127.0.0 和 db.192.22.33

反向 DNS 数据文件用来提供根据 IP 地址查询相应 DNS 主机名，每个网段分别有一个数据文件。

对于内部网段 127.0.0 通常只有一个地址，即 127.0.0.1 loopback 地址，db.127.0.0 内容如下：

@ IN SOA linux.my.com root.linux.my.com. (
1997022700 ; Serial
28800 ; Refresh
14400 ; Retry
3600000 ; Expire
86400 ) ; Minimum
IN NS linux.my.com.

1 IN PTR localhost.
而外部网段的数据文件 db.192.22.33 中包含所有主机 IP 地址到 DNS 主机名的转换数据。db.192.22.33 内容如下：
@ IN SOA linux.my.com. root.pc590.my.com. (
199609206 ; Serial
28800 ; Refresh
7200 ; Retry
604800 ; Expire
86400) ; Minimum TTL
NS linux.my.com.
;
; All hosts
;
20 PTR linux.my.com.
102 PTR support2.my.com.
100 PTR support.my.com.
160 PTR hp712.my.com.
反向 DNS 数据文件中的主要部分是 PTR 记录，PTR 记录中的 IP 地址都只有主机号，named 会根据 named.boot 的定义自动加上前面的网络号，注意后面的主机名要附加一个“.”
（3）获得 db.cache 文件

在 Linux 系统上通常在 /var/named 下已经提供了一个 named.ca，该文件文件中包含了 Internet 的顶层域名服务器，但这个文件通常会发生变化，所以建议最好从 Internic 下载最新的版本。该文件可通过匿名 ftp 从 ftp.rs.internic.net 下载，在 domain 目录下，文件名为 named.root。注意该文件下载后要拷贝到 named 的工作目录并重命名成 named.boot 中指定的文件名，本文中为 db.cache。

五、启动和测试 named
首先，根据先前推荐的方法，用 ndc 启动 named:
ndc start

然后，为了使用和测试 named，要把 Linux 设置在使用 DNS 状态。方法是在 /etc 目录下，创建 resolv.conf 文件。以我们的例子，/etc/resolv.conf 内容为：

search my.com
nameserver 192.22.33.20
然后，我们就可以测试 named 了。
Linux 和其他 Unix 系统均提供了 nslookup 工具，在命令行状态下输入：

nslookup

就进入交换式 nslookup 环境，如果 named 正常启动，nslookup 会显示当前 DNS 服务器的地址和域名，否则表示 named 没能正常启动。下面简单介绍一些基本的 DNS 诊断：

（1）检查正向 DNS 解析

在 nslookup 提示符下输入带域名的主机名，如 hp712.my.com，nslookup 应能显示该主机名对应的 IP 地址，如果只输入 hp712，nslookup 会根据 /etc/resolv.conf 的定义，自动添加 my.com 域名并回答对应的 IP 地址。

（2）检查反向 DNS 解析

在 nslookup 提示符下输入某个 IP 地址，如 192.22.33.20，nslookup 应能回答该 IP 地址所对应的主机名。

（3）检查 MX 邮件地址记录

在 nslookup 提示符下输入：

set q=mx

然后输入某个域名，以本文的例子，输入 my.com 或 mail.my.com，nslookup 应能够回答对应的邮件服务器地址，即 support.my.com 和 support2.my.com。

（4）检查 CNAME 别名记录

在 nslookup 提示符下输入：

set q=cname

然后输入某个别名，如 www.my.com，nslookup 应能回答对应的真实主机名，即 hp712.my.com。

如要退出 nslookup，可输入 exit。

六、修改 DNS 数据
如果要在网络中增加主机，例如要增加一台叫做 pc01.my.com 的 PC 机，管理员要在 db.my 中增加该主机对应的 A 记录，并且要在 db.192.22.33 中增加对应的 PTR 记录，然后用 ndc 更新 named 的数据：
ndc reload

要注意必须同时更改 A 记录和 PTR 记录，许多管理员往往只增加 A 记录而忽略了逆向查询用的 PTR 记录，结果会使许多应用程序不能正常运行。

特别注意，一旦修改了 DNS 数据文件的内容，请务必改动数据文件的版本号（ Serial ）

七、使网络中的其他系统(客户机)使用 DNS 服务器
一旦 DNS 服务器开始工作，就可以配置所有企业网内的主机使用 DNS 服务。
Unix 主机配置的方法，已经在前面说明过，即创建 /etc/resolv.conf 文件，内容见前面第五节。

Windows 95 的配置则是在网卡的 TCP/IP 配置中，选择使用 DNS （enable），然后在配置窗口中分别填入各项参数。以本文的例子，如果运行 Windows95 的主机被命名为 pc01.my.com，则在主机名（Host）一栏中填 pc01，在域名（Domain）一栏中填 my.com，然后把域名服务器 （DNS Server）加入搜索列表中。

Windows NT 节点的配置大致相同。

八、几种不同环境下的修正
（1）如果 IP 网段多于一个
假定现在在 my.com 域中增加一个 IP 网段 192.22.37，则 /etc/named.boot 的内容中就增加一个网段的定义，具体如下：

;
; boot file for name server
;
directory /var/named

primary my.com db.my
primary 0.0.127.IN-ADDR.ARPA db.127.0.0
primary 33.22.192.IN-ADDR.ARPA db.192.22.33
primary 37.22.192.IN-ADDR.ARPA db.192.22.37
cache . db.cache
而反向 DNS 数据文件则增加一个定义 192.22.37 网段的文件 db.192.22.37，其中包括了所有处于 192.22.37 网段中的节点，其格式与 db.192.22.33 类似。
（2）如果企业网是封闭的

如果企业网络不与外界 Internet 直接互连，DNS 服务器就不必关心本企业域以外的域名，所以配置 named 的时候可以不理会 db.cache，我们可以将 /etc/named.boot 中的 cache 行去除。

（3）如果你联入的公共网不能访问 Internet

如果你的内部网接入的公共网只能访问有限的范围，如免费的169网、上海热线等，那么你的 DNS 服务器就不能通过 Internet 的顶层服务器（root server）进行地址解析，所以你必须用你直接能访问到的 DNS 服务器来替代。具体办法是用 forwarders 选项来指定上级 DNS 服务器，以本文为例，named.boot 的内容为：

;
; boot file for name server
;
directory /var/named

primary my.com db.my
primary 0.0.127.IN-ADDR.ARPA db.127.0.0
primary 33.22.192.IN-ADDR.ARPA db.192.22.33
primary 37.22.192.IN-ADDR.ARPA db.192.22.37
forwarders ...
options forward-only
其中、等是你能直接访问到的 DNS 服务器的地址，通常就是你的 ISP （169、上海热线等）的 DNS 服务器的地址，至少要有一个。
通过 forwarders 和 options forward-only 参数的指定，你的企业 DNS 服务器就工作在 forward-only 模式下，所有本地不能解决的名字都被传送到 ISP 的 DNS 服务器上去解析。

九、建立后备 DNS 服务器 （Secondary DNS Server）
通常有一台 DNS 主服务器，网络即可正常工作，但根据 Internic 对域名的管理规范，一个独立的域名必须至少有两台 DNS 服务器，即一台 DNS 主服务器 （ Primary Server ）和一台后备 DNS 服务器（ Secondary Server ），这主要是为 DNS 服务的可靠性考虑，能使 Internet 的性能更为可靠。
现在仍以前面的例子，现在要加入一台运行 Linux 的机器 nspc.my.com，IP 地址为 192.22.33.60。

（1）主服务器上的修改

首先确认 DNS 主服务器工作正常，然后，在主服务器上的正向 DNS 数据文件 db.my 中，加入 nspc.my.com 的有关记录，并增加一个NS记录，使主服务器上的 db.my 成为下列内容：

@ IN SOA linux.my.com. root.linux.my.com. (
199511301 ; serial, todays date + todays serial #
28800 ; refresh, seconds
7200 ; retry, seconds
3600000 ; expire, seconds
86400 ) ; minimum, seconds
NS linux.my.com.
NS nspc.my.com. ; 必须增加的记录
MX 10 support.my.com.

localhost A 127.0.0.1
linux A 192.22.33.20
support2 A 192.22.33.102
hp712 A 192.22.33.160
support A 192.22.33.100
nspc A 192.22.33.60 ; 增加的记录
mail MX 10 support.my.com.
MX 20 support2.my.com.
www CNAME hp712.my.com.
ftp CNAME hp712.my.com.
ns2 CNAME nspc.my.com. ; 增加的记录
ns CNAME linux.my.com.
然后对主服务器上的各个反向 DNS 数据文件做类似的修改，增加有关后备服务器的 NS 记录，然后重新起动 named。
可见，其实在主 DNS 服务器上的改动主要是增加了一条 NS 记录，其余的改动和增加一台普通节点一样，如果是用现有的节点做后备 DNS 服务器，则增加 NS 记录是唯一必须的步骤。

（2）后备 DNS 服务器（secondary server）的配置

需要在后备 DNS 服务器上创建的配置文件只有 named.boot 和 db.cache，格式与主服务器相似，named.boot 内容为：

;
; boot file for secondary name server
;
directory /var/named

secondary my.com 192.22.33.20 db.my
secondary 0.0.127.IN-ADDR.ARPA 192.22.33.20 db.127.0.0
secondary 33.22.192.IN-ADDR.ARPA 192.22.33.20 db.192.22.33
cache . db.cache
其中的三行 secondary 定义，使得 named 从 192.22.33.20，即主服务器上获得各种 DNS 数据，并存在本地的各个数据文件中。本地的数据文件由 named 从主 DNS 服务器的 named 下载后生成，通常与主服务器上的数据文件完全一样，万一后备服务器与主服务器失去连接而不能下载 DNS 数据，后备服务器可利用本地的数据文件工作。
而后备 DNS 服务器的 db.cache 通常由系统管理员从主服务器上拷贝过来即可。

通常，后备 DNS 服务器可以建立在企业网内，也可利用外部的 DNS 服务器充当，如让 ISP 的服务器作为企业的后备 DNS 服务器，这样可以提高 DNS 服务的可靠性。注意，同一台 DNS 服务器可以同时成为多个 DNS 域的服务器，而且可以既作某些域的主服务器，同时又是另一些域的后备服务器。

（3）DNS 客户机端的改动

对于内部网上的 Unix 主机，应该在 /etc/resolv.conf 中增加一行 nameserver 说明，使得系统能够搜索后备 DNS 服务器，以本文的例子，/etc/resolv.conf 的内容为：

search my.com
nameserver 192.22.33.20
nameserver 192.22.33.60
注意，我们可以根据需要决定 /etc/resolv.conf 中所列出的 DNS 服务器的顺序，通常选择访问速度快的服务器在前。
对于 Windows95 和 NT，则是在 DNS 服务器的列表中把后备 DNS 服务器添加进去即可，添加的顺序同样可以决定访问各 DNS 服务器的优先级。


iASP

INstant ASP by Halcyonsoft

http://www.halcyonsoft.com
solaires@hotmail.com, IP=169.254.37.140, iASP_2.0_Unix.tar
Hi minghua,

Thanks very much for downloading Instant ASP 2.0 for your Linux/UNIX server!

Your 30-day license key is:

FEATURE iASP20 halcyon 1.000 26-mar-2002 0 CC5CC398649DF47C28B9 ""
INTERNET=169.254.37.140

To install your license key, after you have installed Instant ASP on your
Linux server, follow the instructions below (make sure the key is on a single
line):

1. Create a plain text file called 'license' (lowercase only).

2. Copy the license string above into the text file. Please be sure you
copy ONLY the license string.

3. Copy the license text file to the <iasp_home>/properties directory,
where <iasp_home> is the iASP installation directory on your machine.

4. Restart your web server and your iASP server.

If you have problems installing your license key, please contact
mailto:asp@halcyonsoft.com.

Regards,
Halcyon Software, Inc.
Solaires@163.com, IP=169.254.37.140,iASP2.01_Unix.tar
Hi minghua,

Thanks very much for downloading Instant ASP 2.0 for your Linux/UNIX server!

Your 30-day license key is:

FEATURE iASP20 halcyon 1.000 27-mar-2002 0 CC4CC3A9649EF47B27BA ""
INTERNET=169.254.37.140

To install your license key, after you have installed Instant ASP on your
Linux server, follow the instructions below (make sure the key is on a single
line):

1. Create a plain text file called 'license' (lowercase only).

2. Copy the license string above into the text file. Please be sure you
copy ONLY the license string.

3. Copy the license text file to the <iasp_home>/properties directory,
where <iasp_home> is the iASP installation directory on your machine.

4. Restart your web server and your iASP server.

If you have problems installing your license key, please contact
mailto:asp@halcyonsoft.com.

Regards,
Halcyon Software, Inc.
solaires@citiz.net, IP=, iASP2.02_Unix.tar
solaires@citiz.net, IP=10.10.1.1, iASP2.03_Unix.tar

Thanks very much for downloading Instant ASP 2.0 for your Linux/UNIX server!

Your 30-day license key is:

FEATURE iASP20 halcyon 1.000 27-mar-2002 0 9C3CF3B92E16DE49F0EB "" INTERNET=10.10.1.1

To install your license key, after you have installed Instant ASP on your
Linux server, follow the instructions below (make sure the key is on a single line):

1. Create a plain text file called 'license' (lowercase only).

2. Copy the license string above into the text file. Please be sure you
copy ONLY the license string.

3. Copy the license text file to the /properties directory,
where is the iASP installation directory on your machine.

4. Restart your web server and your iASP server.

If you have problems installing your license key, please contact
mailto:asp@halcyonsoft.com.

Regards,
Halcyon Software, Inc.
solaires@sohu.com, IP=10.10.1.1, iASP2.04_Unix.tar
Hi minghua,

Thanks very much for downloading Instant ASP 2.0 for your Linux/UNIX server!

Your 30-day license key is:

FEATURE iASP20 halcyon 1.000 27-mar-2002 0 9C3CF3B92E16DE49F0EB ""
INTERNET=10.10.1.1

To install your license key, after you have installed Instant ASP on your
Linux server, follow the instructions below (make sure the key is on a single
line):

1. Create a plain text file called 'license' (lowercase only).

2. Copy the license string above into the text file. Please be sure you
copy ONLY the license string.

3. Copy the license text file to the <iasp_home>/properties directory,
where <iasp_home> is the iASP installation directory on your machine.

4. Restart your web server and your iASP server.

If you have problems installing your license key, please contact
mailto:asp@halcyonsoft.com.

Regards,
Halcyon Software, Inc.


INstant ASP

INstant ASP by Halcyonsoft

http://www.halcyonsoft.com

To install your license key, after you have installed Instant ASP on your
Linux server, follow the instructions below (make sure the key is on a single
line):

1. Create a plain text file called 'license' (lowercase only).

2. Copy the license string above into the text file. Please be sure you
copy ONLY the license string.

3. Copy the license text file to the <iasp_home>/properties directory,
where <iasp_home> is the iASP installation directory on your machine.

4. Restart your web server and your iASP server.


JBoss

Getting Apache 1.3.22 / JBoss 2.4.4 / Tomcat 4.0.1 to work together using the mod_webapp module

download JBoss-2.4.4_Tomcat-4.0.1.zip from http://www.jboss.org/binary.jsp

download webapp-module-1.0.1-tc401-src.tar.gz from http://jakarta.apache.org/builds/jakarta-tomcat-4.0/release/v4.0.1/src/

I assume you have apache 1.3.22 running. make sure you have mod_so running by executing: httpd -l if not: recompile apache with --enable-module=so

-----------------WEBAPP MODULE----------------

compile the webapp module I used:

# ./configure --with-apxs=/usr/local/apache/bin/apxs \

--with-tomcat=/usr/local/JBoss-2.4.4_Tomcat-4.0.1/catalina \

--enable-java=/usr/local/jdk1.3.1_02

# make

optionaly:

copy mod_webapp.o to the libexec directory of apache

-----------------APACHE----------------

add the following lines to your httpd.conf

LoadModule webapp_module libexec/mod_webapp.so

AddModule mod_webapp.c and

(somewhere below the ServerName www.YOURSERVER.xxx statement)

WebAppConnection warpConn warp www.YOURSERVER.xxx:8008

WebAppDeploy jboss warpConn /jboss

--------------JBOSS-------------

the following applies to your jboss/catalina/conf/jboss.jcml file

change the Embedded catalina service part to look like this:

8008 www.YOURSERVER.xxx warp 5 75 true 10

start JBoss using run_with_catalina.sh and restart Apache.

http://www.YOURSERVER.xxx/jboss should work now

----------------TOMCAT EXAMPLES-------------------

to add the Tomcat examples to this installation do the follow

add the following to your httpd.conf

WebAppDeploy examples warpConn /examples

restart apache go to the catalina/webapps/examples directory

note1: I had to comment out the EJB reference examples in the WEB-INF/web.xml

note2: and for the JDNI servlet to (partialy) work I had to change the

to

in the WEB-INF/web.xml file. jar -cf examples.jar *

copy the examples.jar to the jboss/deploy directory and visit: http://www.YOURSERVER.xxx/examples/

Apache 1.3.23 + JBoss-2.4.4_Tomcat-4.0.1

========================================
This document defines the Installation instructions for setting up JBOSS with Tomcat and Apache on Linux:

Please note that I am not deploying a .ear file in the root context. Instead I am using the method suggested by warjort(look at http://main.jboss.org/thread.jsp?forum=67&thread=7059)

The document has the following sections

1) Resources - Lists the websites were the various pieces of software used to build this stack are available and also their versions.
2) Installing JBOSS with Embedded Tomcat.
3) Installing and Configuring Apache - Mentions the steps involved in setting up Apache as the Web server and making it work with JBOSS and Tomcat.

For purposes of this document
$JBOSS_HOME = .../JBoss-2.4.4_Tomcat-4.0.1/jboss
$TOMCAT_HOME = .../JBoss-2.4.4_Tomcat-4.0.1/catalina

=========================================================
* I. Resources *
=========================================================

1) JBOSS and Tomcat

Download JBOSS "version 2.3" with embedded Tomcat "version 4.0.1"
Website: http://WWW.JBOSS.ORG/binary.jsp
Documentation: http://www.jboss.org/documentation/HTML/index.html

2) Apache

Download Apache "version 1.3.23"
Website: http://www.apache.org/dist/httpd/
File: apache_1.3.23.tar.gz

3) Mod_jk for Linux
download the mod_jk-3.3-ap13-noeapi.so adapter from the following site
download: http://jakarta.apache.org/builds/jakarta-tomcat/release/v3.3/bin/linux/i386/

=========================================================
* II. Installing JBOSS with Embedded Tomcat *
=========================================================

Install
=======

For installing JBOSS with Tomcat, just extract the downloaded JBoss-2.4.4_Tomcat-4.0.1.zip to directory.

Run
====
The above step wud complete the JBOSS/Tomcat installation.
To check the installation, change directory to "$JBOSS_HOME/bin" and run "run_with_catalina.sh". If the installation were successful, the output would be something like this.

$ ./run_with_catalina.sh
JBOSS_CLASSPATH=:/usr/java/jdk1.3.1_02/lib/tools.jar:run.jar:../lib/crimson.jar
jboss.home = .../JBoss-2.4.4_Tomcat-4.0.1/jboss
Using JAAS LoginConfig: file:...../JBoss-2.4.4_Tomcat-4.0.1/jboss/conf/catalina/auth.conf JBoss release: JBoss-2.4.4 CVSTag=JBoss_2_4_4
JBoss version: 2.4.4.2001-12-29 02:04:40 PST
Using configuration "catalina"
...............
.................
................
[INFO,MailService] Mail Service 'Mail' bound to java:/Mail
[INFO,MailService] Started
[INFO,ServiceControl] Started 48 services
[INFO,Default] JBoss-2.4.4 Started in 0m:23s.55

To test if it runs: type http://localhost:8080/jboss/ in your browser, which should bring up the an example page. This is the application which is executed in jboss context.

=========================================================
* III. Installing and Configuring Apache *
=========================================================

To compile and install Apache with DSO(Synamic shared object) support
===========================================================
Since apache binaries available on Linux are not DSO enabled by default, we will have to compile apache with DSO support.
1. Download apacahe 1.3.21 from http://www.apache.org/dist/httpd/ --> apache_1.3.23.tar.gz
1. cd apache_1.3.23
2. ./configure --prefix=../apache_1.3.23 --enable-module=so
3. make
4. make install
5. ./httpd -l shud list mod_so.c if apache is succsfully compiled with the DSO support

Running without Tomcat and JBOSS
================================
Since Apache by default listens on port 8888, the port on which tomcat http adapter is already listening, you will have to change the port lets say to 8888 in conf/httpd.conf and then start apache.

$ cd .../apache_1.3.23/bin.
$ ./apachectl start

The console should specify that the server was started successfully. To verify, type http://localhost:8888/ on the browser that should bring up the apache page.

to stop apache:
$ ./apachectl stop

Configuring Apache with JBOSS and Tomcat
========================================

Download "mod_jk-3.3-ap13-noeapi.so" from
http://jakarta.apache.org/builds/jakarta-tomcat/release/v3.3/bin/linux/i386/
And copy it to .../apache_1.3.23/libexec directory

Put the following lines in .../apache_1.3.23/conf/httpd.conf file.
Please note that the file separator is a forward slash '/' and expand the variables wherever necessary.

1) Add "include $TOMCAT_HOME/conf/mod_jk.conf" at the beginning of the file.
2) Change 'DocumentRoot' to "$JBOSS_HOME/deploy/.war"
3) Change <Directory ".../apache_1.3.19/htdocs">
to
<Directory "$JBOSS_HOME/deploy/.war"> (replace JBOSS_HOME with appropriate path)

mod_jk.conf and workers.properties under $TOMCAT_HOME/conf/
---------------------------------------------------------
On how to create these 2 files refer http://jakarta.apache.org/tomcat/tomcat-3.2-doc/mod_jk-howto.html
I took it from the earlier vesrion of Jboss/Tomcat and modified it.

The listing of important things in the file mod_jk.conf are:

# The following line instructs Apache to load the jk module
LoadModule jk_module libexec/mod_jk-3.3-ap13-noeapi.so

JkWorkersFile "$TOMCAT_HOME/conf/workers.properties"
JkLogFile "$TOMCAT_HOME/logs/mod_jk.log"

# Root context mounts for Tomcat
JkMount /*.jsp ajp13

Changes to jboss.jcml
---------------------
After <!-- Uncomment to add embedded catalina service -->
comment out the following code
<!-- <mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat" /> -->
And add

<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<attribute name="Config">
<Connector className="org.apache.ajp.tomcat4.Ajp13Connector"
port="8009" minProcessors="5" maxProcessors="75"
acceptCount="10" debug="1" />
</attribute>
</mbean>

Creating root Context
-------------------
1) Create a directory called ".war" under $JBOSS_HOME/deploy.
2) create an index.html/pull all your static html/jsps to this location
3) Add a sub-directory called WEB-INF
4) In WEB-INF create a web.xml with the following content

<?xml version="1.0" encoding="ISO-8859-1"?>
<!DOCTYPE web-app
PUBLIC "-//Sun Microsystems, Inc.//DTD Web Application 2.3//EN"
"http://java.sun.com/dtd/web-app_2_3.dtd">
<web-app>
</web-app>

Running Apache with JBOSS and Tomcat
====================================

After the previous configuration is done, start the following in the order specified.

1) Start JBOSS by executing $JBOSS_HOME/bin/run_with_catalina.sh
2) Start APACHE ..../apache_1.2.23/bin/apachectl start
3) Access http::/localhost:8888/ shud bring up the index.html which is there in yr $JBOSS_HOME/deploy/.war directory
And if this starts up without any problem then the configuration is successful.

NOTES
=====
1. JBOSS does not read server.xml in catalina/conf
2. JBOSS does not come with an application in a root context.
Jboss and Apache, Tomcat

Integrating JBoss with Apache.

I have been able to correctly integrate the /examples context that comes as default with the JBoss-Catalina zip.
But, when it comes to adding my own application:

WebAppDeploy myApp conn /myApp

where myApp is an application (ear containing some ejbs and jsps) deployed in the jboss/deploy directory, i get this error:

[ERROR,EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConfigurationHandler] Cannot find "D:\JBoss-2.4.4_Tomcat-4.0.1\catalina\webapps\myApp" for appl. "myApp" host "abcd01.mynetabcd.com"

Any clues as to how to integrate JBOSS with Apache???

<<the web application works correctly on 8080 port but gives the error when i try to deploy it with apache.>>

Or was Earlier approach of mod_jk better (that used to work with earlier tomcat versions and integrated easily with Jboss running TC as well)?

May I integrate Apache + Tomcat + JBoss ?

I was able to get Apache working with Jboss-2.4.4 + Tomcat-4.0.1 using mod_jk.

I found the answer here:http://www.jboss.org/forums/thread.jsp?forum=50&thread=6544

Basically use mod_jk like you would with Tomcat 3.2.3 (see the Tomcat docs for details - not jboss docs)
then per the above thread the code in your jboss.jcml should be:

<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<attribute name="Config">
<Connector className="org.apache.ajp.tomcat4.Ajp13Connector"
port="8009" minProcessors="5" maxProcessors="75"
acceptCount="10" debug="1" />
</attribute>
</mbean>

Not as per jboss docs:

<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<config>
<Connector className="org.apache.ajp.tomcat4.Ajp13Connector"
port="8009" minProcessors="5" maxProcessors="75"
acceptCount="10" debug="1" />
</config>
</mbean>

The trick is in the config attribute.

ATTENTION !!!

<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<attribute name="Port">8080</attribute>
<attribute name="BindAddress">localhost</attribute>
<attribute name="MinProcessors">5</attribute>
<attribute name="MaxProcessors">75</attribute>
<attribute name="AcceptCount">10</attribute>
<attribute name="EnableLookups">true</attribute>
<attribute name="Config">
<Connector className="org.apache.ajp.tomcat4.Ajp13Connector" port="8009"
minProcessors="5" maxProcessors="75" acceptCount="10" />
</attribute>
</mbean>

And Use Xcerces instead of Crimson or

This solution also has enabled mod_webapp to function.

My entry in my jboss.jcml is....

<!-- Embedded tomcat 4.x with Warp Connector -->
<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<attribute name="Config">
<Connector className="org.apache.catalina.connector.warp.WarpConnector" port="8008" minProcessors="5" maxProcessors="75" enableLookups="true" acceptCount="10" debug="1" />
</attribute>
</mbean>

in my httpd.conf....

LoadModule webapp_module modules/mod_webapp.so
AddModule mod_webapp.c

WebAppConnection conn warp localhost:8008
WebAppDeploy jboss conn /jboss
WebAppInfo /webapp-info

I verified it was functioning by going to...

http://localhost/jboss/index.html

I was able to run the examples with no problems....
I have the following lines in my httpd.conf file.
###################################################
<IfModule !mod_jk.c>
LoadModule jk_module modules/mod_jk.dll
</IfModule>

JkWorkersFile "F:/jakarta-tomcat-3.3/conf/jk/workers.properties"
JkLogFile "F:/jakarta-tomcat-3.3/logs/mod_jk.log"
JkLogLevel emerg
JkMount /admin ajp13
JkMount /admin/* ajp13
JkMount /examples/*.jsp ajp13
JkMount /jboss/* ajp13
JkMount /examples/* ajp13
JkMount /servlet/* ajp13
#####################################################
After i started jboss-2.4.4_tomcat-4.0.1 using run_with_catalina, i can load http://localhost:8080/jboss/index.html.
But when I try http://localhost/jboss/index.html, i got
"page not found" in MS Explorer. it seems apache can't
connect to tomcat 4.0.1.

i tried to set the port for ajp13 in worker.properties file to 8008 or 8009, both of them don't work. my
server environment is NT SP6, Apache1.3, JBoss-2.4.4_Tomcat-4.0.1.

it looks all the examples worked through http://localhost:8080, but not through http://localhost.

i also tried to use mod_webapp, it doesn't work either through http://localhost. i managed to make the apache work with tomcat4.0.1 if i only start tomcat as a standalone, not throught a embedded service in jboss.

Apache-1.3.1 + JBoss-2.4.3_Tomcat-3.2.3 Problems...

On both Windows 2000 and NT4.0, I am having difficulty integrating Apache-1.3.22 with the pre-integrated JBoss-2.4.3_Tomcat-3.2.3 distribution from JBoss.org. I have followed the standard 3-step process:

(1) In $TOMCAT_HOME/conf/server.xml, add <ApacheConfig /> directive before closing </ContextManager> tag. (Note: The directions called for meto place this "after" the <AutoWebApp /> directive, which was not in the default server.xml file in my distribution.)

(2) In $APACHE_HOME/conf/httpd.conf, add the following "Include":
Include "C:/JBoss-2.4.3_Tomcat-3.2.3/Tomcat/conf/jk/mod_jk.conf-auto"

(3) Downloaded the precompiled win32 mod_jk.dll and placed in $APACHE_HOME/modules folder.

I start JBoss and Tomcat together using the $JBOSS_HOME/bin/run_with_tomcat.bat command (part of the distribution). At first glance, the JBoss-Tomcat install appears to run fine since the Tomcat JSP and Servlet examples run. However, the mod_jk.conf-auto and tomcat-apache.conf files are not created in order for the Apache installation to startup without terminal errors (which I can specifically identify as the problem when starting Apache by viewing the Application Error Log).

One more minor detail...

the documentation sets I have seem to be in conflict. The tomcat-apache-howto.html documentation file says these Tomcat-created dynamic setup files for Apache should be in $TOMCAT_HOME/conf/ and the mod_jk-howto.html documentation file indicates that they should be in $TOMCAT_HOME/conf/jk/. Which is correct?

Any help would be greatly appreciated. Thank you!

You will need to modify the following files:

1) server.xml in the TOMCAT_HOME\conf\ directory

add the following in the connector section

<Connector className="org.apache.tomcat.service.PoolTcpConnector"><Parameter name="handler" value="org.apache.tomcat.service.connector.Ajp13ConnectionHandler"/>
<Parameter name="port" value="8009"/>
</Connector>

2) workers.properties (use copy from TOMCAT_HOME\conf as a baseline). You will need to set the following variables to match your environment...
- workers.tomcat_home
- workers.java_home
- ps

3) httpd.conf (or your custom apache config file) add the following lines...

#Added for mod_jk - tc
LoadModule jk_module modules/mod_jk.dll

#Added for mod_jk - TC
AddModule mod_jk.c

<IfModule mod_jk.c>
JkWorkersFile <full path>/workers.properties
JkLogFile <full path>/mod_jk.log
JkLogLevel debug
JkMount /<YOUR APP NAME>/* ajp13
</IfModule>

(the above assumes you have downloaded a copy of the mod_jk.dll from apache and placed it in the modules directory).

I have made all the changes and started the JBoss-Tomcat process by DOS shell command line and then started the Apache service. The Apache service failed again as a result of Tomcat not creating the Apache configuration file:

TOMCAT_HOME/conf/jk/mod_jk.conf-auto

This is (as above) evidenced from the Event Viewer.

Do you have any suggestions for next steps? Possibly, did I not place the <ApacheConfig /> in the correct location in Tomcat's server.xml file?

Ahhh... I get it, you are running apache as a service. The instructions I gave are for manually running both jboss+tomcat and apache...I should have added:

4) from a command window, run_with_tomcat from the <fullpath>jboss\bin

5) from a command window, apache -f "<config file>" from <full path>apache

Sorry for the confusion.

Here is the output obtained by running Apache from the command line...

C:\Apache Group\Apache>apache -f conf\httpd.conf
fopen: No such file or directory
apache: could not open document config file c:/jboss-2.4.3_tomcat-3.2.3/tomcat/conf/jk/mod_jk.conf-auto
Note the errors or messages above, and press the <ESC> key to exit. 12....
C:\Apache Group\Apache>

I am also sending the server.xml, httpd.conf and workers.properties files directly to you in a separate email.

Problems with the httpd.conf (sent via email)

1) You must provide a JkMount, or mod_jk will not handle any request.

# JkMount /<MY APP NAME>/* ajp13

You need to define the pattern that will be handled by ajp13, for instance, if you want to be able to get the example application that ships with the JBoss+Tomcat bundle, you will need to define the following line:

JkMount /jboss/* ajp13

Which tells the mod_jk interceptor that this pattern will be handled by it using ajp13.

If you deploy a Web Application Archive (.war), by placing it in the <full path to bundle>jboss\deploy, named MyApp.war, you would then need to define the following additional mount:

JkMount /MyApp/* ajp13

2) The following line most likely will not function under the bundle as JBoss is handling the deployment of apps, not Tomcat. Comment it out and explicitly define patterns (as stated above).

Include "C:/JBoss-2.4.3_Tomcat-3.2.3/Tomcat/conf/jk/mod_jk.conf-auto"

ALRIGHT! It is working. I tested the JBoss examples; and, they all work. Also, I copied the contents under TOMCAT_HOME\webapps to the jboss\deploy loadpoint and modified httpd.conf to get all the JSP and servlet examples to work. I think I have the hang of this now!

A quick note...

The "C:\JBoss-2.4.3_Tomcat-3.2.3\tomcat\doc\mod_jk-howto.html" documentation that comes with the JBoss+Tomcat bundle explains that one would need to keep the Include line at the bottom of httpd.conf for an "auto-configuration". What it appears we have done is a "custom configuration", per the noted docuemnt. Does the auto-configuration work?

Albeit it is a "custom" configuration, but the JBoss+Tomcat Bundle is custom environment. The documents that are under the tomcat directory that come with the Bundle must be taken with a grain of salt as they were written for an environment that did not include JBoss.

JBoss/Catalina HTTP500

I downloaded and unzipped Jboss/Catalina, and started them with 'run_with_catalina.bat' under Windows2000. When I point my webbrowser at port 8080 of my machine, I get the browser error: HTTP Status 500 - No Context configured to process this request.

And get this from JBoss:

[INFO,Default] JBoss-2.4.4 Started in 0m:4s.96
[INFO,EmbeddedCatalinaServiceSX] StandardHost[localhost]: MAPPING configuration
error for request URI...
r.java:1011)
at org.apache.catalina.connector.http.HttpProcessor.run(HttpProcessor.ja
va:1106)
at java.lang.Thread.run(Unknown Source)

I don't know what could be causing Catalina to be failing like this, especially when no modifications have been changed, and in the Jboss startup messages it shows that Tomcat services have started fine on 8080 (I am guessing this is the default port).

IIS is not running, nor are any other servers on port 80.

I have looked through every configuration file with the best of my ability, but am unable to find a solution to this.

I talked to a friend of mine, he said the problem might be due to the fact that the new bundle does not include any sample apps. In other words, this error is trying to say that there is nothing in the server that can be run. I find this strange because there is no reason that I shouldn't be able to load index.html from Tomcat regarndless of whether JBoss is running or not. I'm going to try downloading the sample apps and see if this solves anything, though if anyone else has any insight to add, that would be great.

No app gets configured for the root context.

Okay, I saw the thread, but I didn't see what was useful in it. I tried putting tomcat-test.ear in the deploy directory, but that didn't make any difference. As has been stated before, I downloaded, unzipped and ran with no changes and got the HTTP500 error.

The tomcat-test.ear has a context root of "jboss". Therefore to access the tomcat-test.ear application you must access http://localhost:8080/jboss.

If you need an application w/ a context root of '/' then create an application.xml that specifies a web module with <context-root>/</context-root>.

Tomcat WARP connector and Apache

First of all, apologies for posting here, as my problem is not strictly related to JBoss, as I expect the problem actually lies with Tomcat or Apache. I find that JBoss seems to be better supported, and I am sure there are others who have experienced the same problem.

My configuration is as follows, JBoss 2.4.4, Catalina 4.0.1 bundle, SuSe Linux 7.1, with homemade 2.4.17 kernel.
Apache version, 1.3.14 and the new WarpConnector module.

The problem seems to occur regardless of which JVM I use.

I am using apache to route requests to Tomcat/JBoss via the Warp connector, and everything works great.
The only problem is, I keep getting these exceptions:

[ERROR,EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConnection] Exception on socket
java.io.IOException: Premature packet header end
at org.apache.catalina.connector.warp.WarpConnection.recv(WarpConnection.java:237)
at org.apache.catalina.connector.warp.WarpRequestHandler.handle(WarpRequestHandler.java:112)
at org.apache.catalina.connector.warp.WarpConnection.run(WarpConnection.java:194)
at java.lang.Thread.run(Thread.java:484)

The exception doesn't seem to cause any problems, but I am worried about 2 things:

1) What effect it will have in production?
2) The spurious log output it generates

Has anyone has this problem and/or found a solution for it?

My reasons for using apache are as follows:

1) It generates access logs, which I can analyse with tools like webalizer.
2) There is some security that mimises the risk of having to run as superuser on port 80. (On SuSe it makes use of a wwwrun user)

If I had a solution for these two problems, I'd be happiest to ditch apache completely as it adds a
significant overhead to my application. (200-400%)!

Additionally, there is a problem when you redeploy your application, you must also restart apache to prevent problems

Before I started my attempt to get JBoss -> Tomcat -> Warp -> Apache working, I had Tomcat -> Warp -> Apache working under Solaris and I got the same errors in the logs.
Here's what I know: (I'm using Solaris 8, JDK1.3, Tomcat 4.0.1, Apache 1.3.22)

1. When Apache starts up I got the following errors...
[Mon Feb 18 14:58:54 2002] [warn] Loaded DSO libexec/mod_webapp.so uses plain Apache 1.3 API, this module might crash under EAPI! (please recompile it with -DEAPI)

2. When using the version above, I get the errors you mention in the log file and I do have general process instability. (Every 3-4 weeks Apache just crashes.)

3. Last last week, I did the suggested recompile in the error messages, there is no longer an error at startup, and I have yet to see the Premature packet header end error.... but that doesn't mean that I won't....

I hope that helps, but now I have a Tomcat WARP Connector question for you...

I have succeeded in getting WARP to correctly deploy .war files in $CATALINA_HOME/webapps But what I really want is for warp to be able to deploy the .war components of .ear files.

In other words, I have not been able to get the tomcat-test.ear file that comes with the JBoss+Tomcat bundle to work while under warp. There is another forum thread where someone mentions that they use:

WebAppDeploy jboss conn /jboss

but that just doesn't make sense... I know the context for the tomcat-test.ear file is jboss, and I've gotten that working with just the HTTP Connector, but lets suppose for a minute I have an irrational desire to get WARP working Can you tell me how yours is set up if you are in fact able to reference .ear files through WARP? Thanks, hope the info above was helpful.

As for the EAPI problem, I had already fixed this one, so sadly it isn't the cause of my problem. Although I have a suspicion that I am only getting the errors when, static content is being retrieved - particularly binary data.

As for your question, I am happy to help with what I know. You may already know some of the stuff I mention below, but I will elaborate for others that are trying to get this working.

1)First, you must deploy your .ear files in $JBOSS_HOME/deploy rather than $CATALINA_HOME/webapps.

2)AFAIK, $CATALINA_HOME/webapps is redundant when using JBoss.

3)To get the WARP connector working, you basically need to edit two conf files: your jboss.jcml and your httpd.conf ( for apache ).

Some people may prefer to put the httpd.conf changes into a separate conf file (e.g. warp.conf) and link them in to the main httpd.conf.

If you already have Tomcat+Warp+Apache working, the chances are, you have already editted your httpd.conf.

If not, you will need to add some lines like this:
# Change this to point to the path of your module
LoadModule webapp_module /usr/lib/apache/mod_webapp.so

AddModule mod_webapp.c

WebAppConnection conn warp localhost:8008

# Replace your_application below with the name of your
# war file, minus the .war extension
# The forward slash at the end indicates that the
# application will be deployed from the (URLs) root path.
# You can change this to be whatever path you wish your
# application to run from.
# e.g. if you change it to /foo, then you will be
# able to access you application as:
# http://localhost/foo/mypage.jsp
WebAppDeploy your_application conn /

# This is useful if you wish to debug your installation
WebAppInfo /webapp-info

Now for you jboss.jcml. This is where the fun starts as this will *only* work in JBoss 2.4.4, although I haven't tried in on 3.0a. This took some figuring out as the JBoss docs were all wrong.
Find your catalina mbean and change it as below (Sorry about the tab damage).

<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat" >
<attribute name="Config">
<Connector className="org.apache.catalina.connector.warp.WarpConnector" port="8008" minProcessors="5" maxProcessors="75"
enableLookups="false"
acceptCount="10" debug="0"/>
</mbean>

Now if your .ear file has deployed correctly in $JBOSS/deploy, then you should be able to access your apps from apache.

If the above doesn't work for you, then the first thing to try, is to access your application from Tomcat's port 8080. If you can't access your application from that port either, then there is probably something wrong with your ear file, rather than your WARP configuration.

Has anybody managed to do this AND use virtual hosts?

I have Apache, Warp, and the JBoss2.4.4 + Tomcat 4.0.1 bundle working using the config Pete suggests, but when I try to use a virtual host, Catalina tries to find the webapp under it's webapps directory rather than using the deployed ear file from JBoss.

My additions to httpd.conf are:

######### start
NameVirtualHost *

WebAppConnection conn warp localhost:8008

<VirtualHost *>
ServerName ike.home
DocumentRoot /var/www/html/ike
</VirtualHost>

<VirtualHost *>
ServerName pickle.home
DocumentRoot /var/www/html/pickle
WebAppDeploy jobsite conn /jobsite/
WebAppInfo /webapp-info
</VirtualHost>
################ end

With this config and ike.home and pickle.home in another machine's hosts file (linux machines), I can happily browse to either virtual host from the other machine (for plain html files served by Apache).

I can also access the jobsite.ear deployed in JBoss using either http://pickle.home:8080/jobsite or http://ike.home:8080/jobsite.

But as soon as I try http://pickle.home/jobsite (or even http://ike.home/jobsite), Catalina looks for jobsite.war in it's webapps directory. The EmbeddedCatalinaServiceSX repeats an error message over and over to that effect. Here's the JBoss output from just when it deploys the ear file to when I connect via Apache:

[11:40:24,437 INFO ContainerFactory] Deployed application: file:/home/chris/JBoss-2.4.4_Tomcat-4.0.1/jboss/tmp/deploy/Default/jobsite.ear
[11:40:24,438 INFO J2eeDeployer] Starting module jobsite-web.war
...
[11:40:26,567 INFO RMIConnectorService] Starting
[11:40:26,585 INFO RMIConnectorService] Started
[11:40:26,587 INFO MailService] Starting
[11:40:27,011 INFO MailService] Mail Service 'Mail' bound to java:/Mail
[11:40:27,012 INFO MailService] Started
...
[11:40:39,361 ERROR EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConfigurationHandler] Error deploying web application "jobsite" under <http://pickle.home:80/jobsite/>

Catalina would normally look in it's webapps directory for war files, but I guess when it's bundled with JBoss, the EmbeddedCatalinaServiceSX reconfigures it so it can find the webapp once it's been deployed from the ear file. I know the bundled Catalina doesn't use it's server.xml file as I can connect to the webapp on port 8080 even if I delete it, so there's no point changing server.xml.

The WarpConnector is a configuration parameter of EmbeddedCatalinaServiceSX, so is there another attribute I need to use to make it work with a virtual host?

At last, figured it out. Looking at the source, I found that org.jboss.web.catalina.EmbeddedCatalinaServiceSXMBean has a setBindAddress method (don't you just love open source?), so I changed my jboss.jcml to this:

<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<attribute name="Config">
<Connector className="org.apache.catalina.connector.warp.WarpConnector" port="8008" minProcessors="2" maxProcessors="10" enableLookups="false" acceptCount="5" debug="1" />
</attribute>
<attribute name="BindAddress">pickle.home</attribute>
</mbean>

and it works. I can see the webapp on http://pickle.home/jobsite, but I can't see it on http://ike.home/jobsite, which is correct.

There were a few error messages when I first connected, but I but I think they're a red herring:

[12:21:24,513 ERROR EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConnector] Connection from localhost.localdomain/127.0.0.1:38227 to localhost.localdomain/127.0.0.1:8008
[12:21:24,518 ERROR EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConnector] Connection from localhost.localdomain/127.0.0.1:38228 to localhost.localdomain/127.0.0.1:8008
[12:21:24,580 ERROR EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConfigurationHandler] Filter mappings (0)
[12:21:24,589 ERROR EmbeddedCatalinaServiceSX] [org.apache.catalina.connector.warp.WarpConfigurationHandler] Filter mappings (0)

The messages come out of the Warp connector and the EmbeddedCatalinaServiceSX is reporting them as errors even though they don't appear to be real errors if you look at the Warp source.

I have followed the procedure as mentioned by you. Here are the configuration of my jboss.jcml.
<mbean code="org.jboss.web.catalina.EmbeddedCatalinaServiceSX" name="DefaultDomain:service=EmbeddedTomcat">
<attribute name="Config">
<Connector className="org.apache.catalina.connector.warp.WarpConnector" port="8008" minProcessors="5" maxProcessors="75" enableLookups="false" acceptCount="10" debug="0"/>
<attribute name="BindAddress">localhost</attribute>
</attribute>
</mbean>

I have addres the BindAdress attribute later. It did not work without bind address as well.

My Apache config is:

WebAppConnection warpConnection warp localhost:8008
WebAppDeploy emergingtrade warpConnection /emergingtrade/
WebAppInfo /webapp-info
WebAppConnection warpConnectionTest warp localhost:8008
WebAppDeploy examples warpConnectionTest /examples/

The example application is working as it is deployed in the catalina/webapps directory.

I figured it out. it is working now.

The bind address attribute in the jboss.jcml is required even if you are not using the virutal hosts in Apache. The name of the bind adress must match with the ServerName directive of the Apache server. I was using the ptrader name in apache and localhost in the jboss.jcml.

JBoss/Tomcat HTTP 500

I downloaded the JBoss/Tomcat bundle yesterday, and haven't been able to get Tomcat to process requests when I try to start the servers with 'run_with_catalina' (I Get 'HTTP Status 500 - No Context configured to process this request'). When I just run Catalina with 'catalina' everything runs AOK, but of course without JBoss. Any ideas? I'm trying to get this up and running for a corporate project, and if I can't get this going they're going to go ahead with Weblogic.

I haven't been able to get the root "/" context working yet, but the additional .war applications that I deployed in jBoss worked. It just seems that something may be wrong with the root context. I'm not sure if this applies to your situation, but maybe it will.

On Tomcat, the root context is called ROOT.war and if you deploy it it sets itself up as the root context... this doesn't seem to work in jboss though...

What you can do is go to sourceforge and get version 2.4.3. dont know why 2.4.4 bundle doesnt work but the 2.4.3 bundle works just fine. try it out.

Heh, it's not a trouble...
cd $CATALINA_HOME/webapp/ROOT
jar cvf ROOT.war *
mv ROOT.war $JBOSS_DIST/deploy/.war

cd $CATALINA_HOME/webapp/examples
jar cvf examples.war *
mv examples.war $JBOSS_DIST/deploy/

etc...

Hi - finally figured out how to get the JBoss 2.4.4 + Tomcat 4.0.1 working; in addition to creating the ROOT.war and examples.war files above and putting them in the $JBOSS_HOME/deploy directory, you also need to copy the tools.jar file from your $JAVA_HOME/lib directory into the $JBOSS_HOME/lib/ext directory so JBoss/Catalina will be able to compile JSP's.

Also, you have to access these web applications in their URL context's: ie:

http://<yourhostname>/ROOT
http://<yourhostname>/examples

and then (from what I've seen) everything seems to be working okay.

I haven't figured out yet how to specify a default web-app so if you just go to http://<yourhostname> a web-app will automatically load up.

->I haven't figured out yet how to specify a default web-app so if you just go to http://<yourhostname> a web-app will automatically load up.

mv ROOT.war $JBOSS_DIST/deploy/.war
(rename "ROOT.war" to ".war" and move it to your deploy dir).
When see http://<yourhostname>:8080

On windows, I can't change ROOT.war to .war. There was not problem when I deployed ROOT.war. But when I deployed examples.war, I got the following messages:

[ERROR,EmbeddedCatalinaServiceSX] Failed to setup web application ENC
javax.naming.NamingException: ejb-ref: ejb/Account, expected jndi-name in jboss-
web.xml
at org.jboss.web.AbstractWebContainer.linkEjbRefs(AbstractWebContainer.j
ava:428)
at org.jboss.web.AbstractWebContainer.
.........
.........
.........
at java.lang.Thread.run(Unknown Source)

But the examples are working well. What is this error message about?

To change the ROOT.war to .war in windows you have to use the command prompt:

c:>rename ROOT.war .war

I am trying to use this on Mac OSX and have a small problem, their is no tools.jar file. Can I use any other distributions tools.jar file ???

From a post on the dev-list

>On OS X the javac
> compiler is in the
>/System/Library/Frameworks/JavaVM.framework/Versions/CurrentJDK/Classes/clas es.jar

I think the article I wrote yeserday: "HOWTO: root.ear - tomcat 4.0.1 root application to deploy in jboss"
presents a much more elegant solution to the problem then renaming a war as you have done (just my opinion). Go ahead and check it out

> ->I haven't figured out yet how to specify a default
> web-app so if you just go to http://<yourhostname> a
> web-app will automatically load up.
>
> mv ROOT.war $JBOSS_DIST/deploy/.war
> (rename "ROOT.war" to ".war" and move it to your
> deploy dir).
> When see http://<yourhostname>:8080

Thanks for the info so far. I'm using JBoss 2.4.4 - Tomcat 4.0.1 with J2SE 1.4 running on Win2000 Professional. I've created and copied examples.war and root.war to $JBOSS_HOME/deploy, and renamed root.war to .war. All the examples work fine now apart from the naming servlet, and I get this output when I start JBoss:

[ERROR,EmbeddedCatalinaServiceSX] Failed to setup web application ENC
javax.naming.NamingException: ejb-ref: ejb/Account, expected jndi-name in jboss-
web.xml

...
at org.jboss.Main$1.run(Main.java:110)
at java.security.AccessController.doPrivileged(Native Method)
at org.jboss.Main.main(Main.java:106)

When I try to use the naming servlet I get the following output in the browser window:

JNDI lookup failed : javax.naming.NameNotFoundException: maxExemptions not bound
list() on /comp/env Context :
JNDI lookup failed : javax.naming.NameNotFoundException: not bound

I'm assuming these two problems are related. Any help / pointers would be much appreciated.

Forgot to mention. Also tried this with .war renamed back to ROOT.war and still get same exceptions thrown during startup.

Also, when I shut down JBoss I've noticed the following output:

[INFO,J2eeDeployer] Destroying application .war
[INFO,J2eeDeployer] Stopping module examples.war
at org.jboss.deployment.J2eeDeployer.stopService(J2eeDeployer.java:375)
at org.jboss.util.ServiceMBeanSupport.stop(ServiceMBeanSupport.java:138)
at com.sun.management.jmx.MBeanServerImpl.invoke(MBeanServerImpl.java:15
23)
at org.jboss.util.Shutdown.shutdownServices(Shutdown.java:87)
at org.jboss.util.Shutdown$1.run(Shutdown.java:56)
[INFO,J2eeDeployer] Destroying application examples.war

How to test the setup "Apache 1.3.23 + Tomcat4.01 + JBoss2.4.4"?

I just set up Apache 1.3.23 & Tomcat(4.01) with JBoss2.4.4 and want to know how to have a simple test to see whether all the things work properly. Because I can browse the site (e.g. http://10.1.0.x:8080) even without running Apache.
The "DocumentRoot" points to xxx/jboss/deploy/.war
P.S. I can start Tomcat_with_Jboss (run_with_catalina.sh) and Apache properly. But whenever I shutdown Apache, I got error message " [error] Cannot remove module mod_jk.c: not found in module list".

you can test it if you put apache in another port else 8080, for example the 80.

If your conf is ok, http://10.0.1.x/AppName should go.

When you start apache, Does the console say mod_jk1.1.0 is running???

If don't the problem is on the apache side.

When you start jboss+tomcat, Do you see mod_jk logs logs lisening to port 8009???

If don't the problem is on the jboss side. Check jboss.jcml file.

Another problem could be the workers.properties file that should be on CATALINA_HOME/conf or in the httpd.conf file of Apache.

By the way look at this thread, i think that with this info you should run Jboss+catalina+apache

http://main.jboss.org/thread.jsp?forum=50&thread=8591

http://main.jboss.org/thread.jsp?forum=50&thread=8823

I integrated Apache,tomcat, and jboss. My problem is everytime i change something on my servlets and recompile it, i need to restart jboss and apache. Is there any way to automatically load the servlets when it changes?

admiyo

Posts: 18
From: Oakland, CA
Registered: Oct, 2001

Re: How to test the setup "Apache 1.3.23 + Tomcat4.01 + JBoss2.4.4"? Posted: Mar 5, 2002 9:27 PM
Reply

Deploy as a web archive separate from the ejbs (.war vs .ear/.jar)

Even with vanilla tomcat, you want to copy all of your files into the webapps directroy when you make a JSP change, because of the dependency checking between files (if using static includes, haven't tried it with dynamic includes of 4). If you are doing a lot of html stuff, it is easier to work with the plain html files. If you are doing more servlet stuff, it is betytwer to deploy a .war

How to run sample JSP/Servlet from Catalina in JBoss-2.4.3_Tomcat-4.0

try declaring your dtd in web.xml:

<!DOCTYPE web-app PUBLIC "-//Sun Microsystems, Inc.//DTD Web Application 2.3//EN" "http://java.sun.com/dtd/web-app_2_3.dtd">

hope this helps

JSP execution problem in Jboss_2.4.3_Tomcat_4.0

The problem is that JBoss doesn't have in its classpath the reference to the java compiler.

To fix this, do this
Unix: export JBOSS_CLASSPATH=$JAVA_HOME/lib/tools.jar:$JBOSS_CLASSPATH

Windows: JBOSS_CLASSPATH=%JAVA_HOME%\lib\tools.jar;%JBOSS_CLASSPATH%
JBoss2.4.4/Tomcat4.0.1/cocoon2 on linux,win2K Posted: Jan 3, 2002 7:42 AM
Reply

Hello.

I got a problem in running jboss2.4.4/tomcat4.0.1 with cocoon2.

On Win2k Professional, suceeded running jboss with above combination,but on Linux I got a segmentaion-fault when starting run_with_catalina.sh.(tried on same machine.I use lilo)

Here is my conf and run.sh & run.bat
Xerces : xerces-1_4_3
Win2k professional: JDK 1.3.1 ( build 1.3.1_01 )
Linux 2.2.19: JDK 1.3.1 ( build 1.3.1_b24 ) glibc 2.1.3
-- run.sh --
JBOSS_CLASSPATH=$JBOSS_CLASSPATH:run.jar:../lib/xerces.jar
echo JBOSS_CLASSPATH=$JBOSS_CLASSPATH
java -classpath $JBOSS_CLASSPATH org.jboss.Main $@
-- run.bat --
set JBOSS_CLASSPATH=%JBOSS_CLASSPATH%;run.jar;../lib/xerces.jar
echo JBOSS_CLASSPATH=%JBOSS_CLASSPATH%
java -classpath "%JBOSS_CLASSPATH%" org.jboss.Main %1 %2 %3 %4 %5 %6 %7 %8 %9
pause

thanks for reading.
-- Auditd

gasperm

Posts: 6
Registered: Jan, 2002

Re: JBoss2.4.4/Tomcat4.0.1/cocoon2 on linux,win2K Posted: Jan 3, 2002 2:10 PM
Reply

Hello

I don't know the answer to your question but I didn't manage to install coocon2 on win2000 I get an

java.lang.NoClassDefFoundError: org/xml/sax/SAXException

and jboss won't even start. This happens when I delete crimson.jar as written in the docs. I have xerces-1.4.4.jar in the lib/ dir and included in run.bat .

What is your secret on how to install cocoon2?

Thanks

Gasper

auditd

Posts: 5
Registered: Jan, 2002

Re: JBoss2.4.4/Tomcat4.0.1/cocoon2 on linux,win2K Posted: Jan 3, 2002 9:07 PM
Reply

I just traced steps descibed in Cocoon2 install manual.
step 1. delete crimson.jar, jaxp.jar in $JBOSS_DIST/lib
step 2. delete parser.jar,jaxp.jar in $TOMCAT_HOME/lib for Tomcat ver. < 4.0. in case of TOMCAT 4.0, do nothing.
step 3. edit your $JBOSS_DIST/bin/run.bat referring to above thread.

step 4. download xerces package here(http://xml.apache.org/dist/xerces-j/). After unzip, copy xerces_X_X_X.jar to $JBOSS_DIST/lib.

found remedy in this forum's threads.

1. segmentation fault
add follow line in run.sh.(thanks for who answered segmentation-fault problem in this forum)
>> ulimit -s 2048

2. can't find sitemap.xmap error
also found remedy in cocoon2 FAQ.
according to FAQ, cocoon2 needs Xserver to run properly. so after starting X in linux box, above error disappeared.

It's usually easier not to replace jaxp/crimson with xerces, then rather include both; and put xerces in the front of the JBoss classpath. Even JBoss3 can run Cocoon2 this way - I have a working setup of these.

My cocoon2 deploys with JBoss2.4.4/Tomcat4.0.1/cocoon2 setup, but with an exception - below.

I've tried both your auditd, and your Cristopher, setups.

I found out that the jsp example does not work, all other examples do (except sql). I'm in pain because I need the jsp transformation - I'm building my app on it.

Did anyone get the jsp example to work??

[ERROR,EmbeddedCatalinaServiceSX] StandardContext[/cocoon]: Servlet /cocoon threw load() exception
javax.servlet.ServletException: Servlet.init() for servlet Cocoon2 threw exception
at org.apache.catalina.core.StandardWrapper.load(StandardWrapper.java:871)
at org.apache.catalina.core.StandardContext.loadOnStartup(StandardContext.java:3267)

...
at java.security.AccessController.doPrivileged(Native Method)
at org.jboss.Main.main(Main.java:106)


JBoss

Jboss下配置EJB

一、前言

     Jboss为Open Source，完全免费的Appliaction Server，对于J2EE有很好的支持，可以和Tomcat完美结合。

二、下载，安装

     下载地址为Jboss官方站点：http://www.jboss.org/，下载的是Jboss2，而且和tomcat一起的，这样避免了单个下载一起配置的问题。下载地址是：http://www.jboss.org/jboss_tomcat.zip

     下载完，解压到一个目录，我这里用E:\jboss_tomcat作为例子。下面有子目录:

E:\jboss_tomcat\jboss2

和

E:\jboss_tomcat\tomcat32b7

注意，我这里的目录稍微做了改动的，这样如果你不将TOMCAT_HOME加到CLASSPATH中，E:\jboss_tomcat\jboss2\inun_with_tomcat.bat这个文件要做相应改动才能正常运行。

三、配置运行

     基本上不要什么配置的，只要安装好了JDK，当然，最好将TOMCAT_HOME加到CLASSPATH中。

这样，E:\jboss_tomcat\jboss2\inun_with_tomcat.bat这个文件前的TOMCAT_HOME就可以去掉了。

运行E:\jboss_tomcat\jboss2\inun_with_tomcat.bat这个文件，这样，Tomcat端口在8080，Jboss为8083，

运行http://localhost:8080/将出现tomcat首页，

运行http://localhost:8083/将出现无错误的空白页，

四、测试EJB

     (1)启动JBOSS：

方法见上：

     (2)下载代码：

http://www.wodejia.net/softdownload/java/interestejb.zip

解开，出现如下目录：

interest/com

interest/docs

...

全部copy到jboss2下examples目录下，如果没有examples目录，建立一个，结构如下：

E:\jboss_tomcat\jboss2\examples\interest...

将文件E:\jboss_tomcat\jboss2\examples\interest\interest.jar复制到：

E:\jboss_tomcat\jboss2\deploy下：

在CLASSPATH中加入如下文件：

E:\jboss_tomcat\tomcat32b7\lib\servlet.jar;E:\jbossclient\jboss-lient.jar;E:\jbossclient\jnp-lient.jar;E:\jboss\lib\ext\ejb.jar;E:\jboss\examples\interest\interest-client.jar

为了测试Client通过servlet调用EJB，必须将： E:\jboss_tomcat\jboss2\examples\interest下EJB.class和EJB.java复制到：

E:\jboss_tomcat\tomcat32b7\webapps\ROOTWEB-INF\classes目录下

重新启动JBOSS_TOMCAT

     (3)command下client测试运行：

command下，进入目录E:\jboss_tomcat\jboss2\examples\interest
java InterestClient

将出现：

Got context

Got reference

Interest on 1000 units, at 10% per period, compounded over 2 periods is: 210.00000000000023

jboss窗口将出现：

[Interest] Someone called `calculateCompoundInterest!'

     (4)web下client通过Servlet测试运行：

http://cgreen:8080/servlet/EJB

将出现：

Interest on 1000 units, at 10% per period, compounded over 2 periods is: 210.00000000000023

jboss窗口将出现：

[Interest] Someone called `calculateCompoundInterest!'

到此已经成功了。


RESIN

After de-compressing, just run /bin/httpd.sh to start resin. To work with Apache, you need to compile resin sources:

./configure --with-apache \

etc


RESIN

在Linux上搭建WEB服务器:JSP

JSP相对于PHP来说，可能运行得更快，消耗系统资源更少，功能更为强大——例如对分布式处理和组件支持等等。JSP技术在国外已经相当普及，而在国内，只不过还是刚热起来而已……虽然现在ASP+在性能上给JSP带来严峻的挑战，但它作为微软以外的一个选择，又支持多平台，所以还是很多网站所采用的首选。在这一部分里，我们将讲解三种不同的JSP集成方案，代表着三种典型的应用范围。

Linux+Apache+PHP+JSP的Resin解决方案

首先向大家推荐的是Resin。Resin是快速的、容易配置和实施的、使用简单的JSP/Servlet引擎和Web服务器。这一点完全是无庸置疑的，无论是在windows平台还是在UNIX/Linux平台。然而目前的Resin 1.3 还不是一个应用服务器。不过Resin 2.0版有望取得很大的突破。因为它将包含一些最新的J2EE特性。Resin在JSP tags、XML解析等方面投入都比较早，现在也是处于比较领先的地位。而apache.org的tomcat更象是一个开发研究的产品。如果让我来做一个网站，RESIN肯定是我的首选——相信泛舟也是如此认为的。
我们将在Linux+Apache+PHP的WEB服务解决方案中加入JSP的支持，这也许是您升级网站的需要。就算你不需要PHP也没有关系，下面我也会讲解如何做到这一点。

1、软件包的获取
JDK是所有支持JSP环境所必须的，可以从http://java.sun.com获得它for linux的最新版本，现在好象是JSDK v1.3。
Resin可以从它的老家http://www.caucho.com获得它的最新版本。在5月初的时候它的最新稳定版是1.2.5。
至于apache什么的，请参考上一节有关内容。

2、安装JDK
在安装Resin前，最好先安装好JDK，如果是下载的rpm包的话，可以使用
rpm -Uvh java_version.rpm
如果是下载的GNU压缩包的话，直接解压就可以了。
别忘了确认java运行所需要的一些基本设置，可能包括PATH、JAVA_HOME、CLASSPATH，例如可以把这些行加入/etc/profile文件里：
-----------------------------------------------
PATH=/usr/local/bin:/usr/bin:/bin:/usr/java/bin
export PATH

JAVA_HOME=/usr/java
export JAVA_HOME

CLASSPATH=/usr/java/lib/tools.jar
export CLASSPATH
------------------------------------------------
具体请参考java.sun.com对相应版本的安装说明。

3、Resin对apache的要求
Resin可以为apache提供一个快速的servlet运行环境，允许apache处理servlets和JSP文件。但是它需要Apache的版本为1.3.x和DSO（Dynamic Shared Object，动态共享对象）的支持。所以在我们前一节中apache的编译选项中，需要添加一条--enable-module=so。如果我们并不需要PHP的支持的话，可以直接使用类似如下的方法编译apache：

linux> ./configure --prefix=/usr/local/apache
--enable-module=so
linux> make
linux> make install

4、编译mod_caucho.so
为了要编译mod_caucho.so，你需要先运行configure后才使用make。这一步将生成mod_caucho.so并把它放在Apache的module目录里。按照我们在第二节中的设置，mod_caucho.so将在/server/apache/libexec的目录下，否则一般都会被编译成/usr/local/apache/libexec/mod_caucho.so。

linux> ./configure --with-apache=/server/apache -----如果是按照前一步举例中的方法把apache的安装目录设置为了/usr/local/apache，那么，请修改这里apache的目录。
linux> make
linux> make install

这样你就已经可以了。但是假如你知道apxs的位置的话，你也可以使用如下方法来编译：

linux> ./configure --with-apxs=/usr/local/apache/bin/apxs
linux> make

apxs是一个apache安装配置时生成的一个小小的perl脚本。它可以使象resin这种模块获得apache所有的配置路径。你应该可以用whereis apxs获得它的位置。

如果你对配置选项需要更全面细致的定制的话，你还可以使用 ./configure的如下参数，例如apache-include， apache-libexec和apache-conf，下面是对它们的说明：
--with-apache=dir //Apache的根路径，也就是prefix指定的安装目录
--with-apxs=apxs //指向Apache的扩展脚本
--with-apache-include=dir //Apache包含文件所在的目录
--with-apache-libexec=dir //Apache模块所在的目录
--with-apache-conf=httpd.conf //Apache的配置文件

5、设置环境变量
我们已经完成了JDK的安装与环境设置，但还需要对resin进行环境设置。下面是一个典型的配置，需要你手动加入~/.profile或者/etc/profile文件中。
————————————————————
# Resin的安装路径。通常情况下Resin都在这样的目录下：
RESIN_HOME=/<installdir>/resin1.2
export RESIN_HOME

# 假如你使用了扩展类库，你需要把它加入到classpath中，
# 最典型的可能是JDBC的驱动程序了
CLASSPATH=$CLASSPATH:<JDBC_DIR>
————————————————————

6、配置resin.conf
缺省的，Resin将在resin1.2/doc目录下寻找JSP文件，在resin1.2/doc/WEB-INF/classes寻找servlets和beans。为了要让Resin使用Apache的发布文档目录（也就是我们发布WWW服务的根，在这里是/var/www/），我们需要配置app-dir。把app-dir从“doc”修改为/var/www或者你指定的WWW发布文档的根。下面是一个典型的resin.conf文件。

<!--//resin.conf -->
<caucho.com>
<http-server
app-dir='/var/www/'>
<servlet-mapping url-pattern='/servlets/*'
servlet-name='invoker'/>

<servlet-mapping url-pattern='*.xtp'
servlet-name='com.caucho.jsp.XtpServlet'/>
<servlet-mapping url-pattern='*.jsp'
servlet-name='com.caucho.jsp.JspServlet'/>
</http-server>
</caucho.com>

7、启动Servlet引擎
现在你需要启动servlet的引擎。和apache配合、resin单独运行，resin的启动方法都是一样的。当然，对resin1.2/bin/httpd.sh这个脚本文件来说，你一样可以使用start和stop参数。

linux> resin1.2/bin/httpd.sh
Resin 1.2.s010113 -- Sat Jan 13 11:17:18 PST 2001
http listening to *:8080
srun listening to localhost:6802

Resin将显示它监听的每一个端口。在上面这个例子中，Resin的http服务使用了8080，servlet支持协议使用了6802端口。也就是说mod_caucho只可以在本地的6802端口和Resin连接通信，但你可以通过8080端口在任何主机上浏览Resin服务器的内容。
下面这个片段显示了http和srun在上面这个例子中的配置。

<caucho.com>
<http-server>
<http port='8080'/>
<srun host='localhost' port='6802'/>

...
</http-server>
</caucho.com>

呵呵，现在你可以使用一些简单的脚本来测试你的jsp环境了。
附注：wrapper.pl
Resin使用一个perl的脚本，resin1.2/bin/wrapper.pl，来控制Java进程。（(bin/httpd.sh只是一个调用wrapper.pl的微型脚本而已）。你可以通过修改bin/httpd.sh或者bin/wrapper.pl来设定你的配置。
wrapper.pl在Resin结束的时候自动重起它。假如你需要使用kill命令停止Resin，你需要先用kill命令杀掉wrapper.pl进程（"httpd.sh stop"就是通过kill了wrapper.pl进程来实现的。


wap configurations

1. Network topology

Wireless terminals ( mobile phone, PDA ...) dial in through Internet via WAP server to Origin servers (WEB server, Email servers), information will be returned the same way back to wireless terminals.

2. System configurations
Different users may choose from different configurations, as below:

user type | Dial-in Server | WAP Server | Origin Server
ICP |  |  | √
general use |  | √ | √
enterprise use | √ | √ | √

ICP only provides WAP Web content for WAO clients, dial in and WAP gates can be done by other companies (such as telecom companies).
Normal users (e.g. e-business websites) need to set up its own WAP gates to achieve secure access for WAP clients and to provide other value added services. Dial in services can be done by others ( e.g. ISP).
Enterprise WAP application is provided to small scale wireless customers (e.g. enterprise internal personnel, simultaneous users of ca 100-500) for wireless connection and agency services.

We propose the following to enterprise users:
mobile phone：WAP mobile phone with data transmission
Dial-in Server：NT Server or Linux；Modem(connected with telephone line or ISDN)。ISDN can improve WAP connection speed；Remote Access Service or Routing and Access Service(with routing functions).
WAP Server：256M RAM，network card(for connection to Internet/Intranet)；NT Server (SP4 and above) or Linux；Nokia WAP Server；Nokia WAP Server Security Pack(secure transmission,secure certification and access, optional)；Nokia WAP Server SMS Bearer

Pack(supporting short message, optional)；
Web Server：IIS or Apache；WML/WMLScript；other static pages supporting WML/WMLScript.

To realize Push service based on SMS, you need: mobile with embedded modem to transmit SMS;
relevant software for this mobile(Nokia' Cellular Data Suite、7110's Expl and the like) to support SMS push

3. Functional modules
Provide value added service for wireless communications or WAP;
Publish and query for public information based on WML (news, yellow pages, whether, traffic, transport timetable, online traffic guides, dictionary, calendar, TV programs etc);
PIM：Personalized Information Management

Personalized E-business Services:
discount info, price reduction, promotion, price comparison;
buy guide, products search, order, ticketing, meals, online transactions;
order confirmation,delivery notice, reception notice;
entice stock(futures) info, stock/future transactions;
bank/finance services, transfer/query for deposit ;

Enterprise internal business system:
publish ontime products prices, inventory,orders, yellow pages,important notices,and

other important info to employees, sales and marketing personnel

4. Steps of implementation

Procure hardware equipment: telephone or ISDN lines, network cards, RAM, mobile phone (with data line to send SMS)
set up Dial-in Server；
set up Nokia WAP Server，and relevant software;
Install software package for your handy to realize SMS messaging;
Set up Web Server，to support WAP access;
Convert your HTML/JavaScript pages to WML/WMLScript.

WAP solutions

Wireless Internet is based on WAP technologies, its full operation needs three sectors: WAP gates, WAP content server and WAP terminals. Installation of WAP gates is normally done by wire operators such as communications companies or big ISPs, WAP terminals are produced by communications companies. With the WAP terminals and wireless Internet infrastructure, you need to set up WAP content server to provide information to WAP users. The following picture shows the WAP Internet configuration.

There are two solutions to WAP sites: WAP site + publish WAP gates and WAP content site + WAP gates. WAP site is coexist with Web site, and is an extension of Internet to wireless terminals, therefore a WAP site needs Web server. WAP and Web sites may or may not share the same server (hardware).

1.WAP content site + public WAP gate

this option involves smaller investment for setup and maintenance, suitable for small to medium enterprises. Details of configurations can be decided based on needs of individual companies:

options | WEB server | WAP server | notes
option 1 | DDN T1/EI | DDN T1/EI | flexible in configuration, easy to maintain, suitable for developing specialized, powerful and complex web/WAP site free to choose development environment,programming languages and new technologies cost high
option 2 | hosting | hosting | flexible in configuration,free choice of OS, languages, and new technologies maintenance and development not handy
option 3 | virtual hosting | virtual hosting | configuration dependent on host, can develop normal applications Cost low, maintenance easy No flexibility for free configuration and selection of development tools and apply new technologies

WAP gates can be chosen from public gates e.g. China Mobile, Unicom, but you pay for their services.

2. WAP content site + WAP gates

This option is more expensive but fit to needs of large companies.

options | WAP gates | WEB server | WAP server | notes
option 1 | WAP gates from Nokia, Ericcson,PHONE.COM etc | DDN T1/EI | DDN T1/EI | flexible in configuration, easy to maintain, suitable for developing specialized, powerful and complex web/WAP site free to choose development environment,programming languages and new technologies cost high
option 2 | WAP gates from Nokia, Ericcson,PHONE.COM etc | hosting | hosting | flexible in configuration,free choice of OS, languages, and new technologies maintenance and development not handy
option 3 | WAP gates from Nokia, Ericcson,PHONE.COM etc | virtual hosting | virtual hosting | configuration dependent on host, can develop normal applications Cost low, maintenance easy No flexibility for free configuration and selection of development tools and apply new technologies

WAP Info

WAP.doc

WAP2.doc

wap.htm

wap_internet.htm

waphandy.htm

waphosting.htm

wapres.htm

wapserver.htm

wapsystem.htm


WAP手机常识及特点

WAP手机是不仅具有普通手机的功能，而且还有收发电子邮件、传真、浏览新闻、查看股市行情等功能。WAP手机和一般的手机不同之处在于它内置有微型浏览器（MiniBrowser）、缓存（CACHE）和内存，并支持客户端COOKIES 和SESSION。WAP手机上网要进行一系列的设置。具体的设置详见WAP手机上网配置说明。

WAP手机上网和普通的电脑上网有很大的差别。由于WAP手机内存不大、屏幕小及无线频带窄，目前WAP手机所显示的网页内容主要是文字，也有一些较小的图片，但仅有黑、白和灰色三种颜色。业界专家指出，能够让手机和手持电脑成为上网工具的WAP技术将是互联网技术的下一个热点。 WAP手机可收发电子邮件、阅读新闻和股市行情，但是更复杂的通信应用，如在线采购和视频会议，目前的移动通信网运行速度就无法达到要求了。


WAP虚拟主机

A．提供高尖端的（HP LH3000）WAP专用服务器：

HP NetServer LH3000

Intel Pentium III 双处理器

集成双通道　Ultra 2 SCSI控制器及高性能磁盘阵列控制器

最大内置容量468GB

133MHz SDRAM DIMM

B．提供高质量的7X24技术支持和维护支持:

1、提供上班时间之内的预防性维护；

2、不限次数的“提问/解答”答复；

3、不限次数的“怎么办”答复；

4、提供WAP手机的应用与设置解答。

C．WAP虚拟主机市场建议服务报价

WAP虚拟主机 | 30M | 60M | 100M
网关占用费 | 4000元/年 | 8000元/年 | 12000元/年
空间租用费 | 2000元/年 | 3600元/年 | 5600元/年
一次性设置费 | 1000免 | 1200免 | 1400免
高速网络带宽 | √ | √ | √
WAP电子邮件 | 5M/100元/年 | 5M/100元/年 | 5M/100元/年
数据流量 | 4000元/年 | 6000元/年 | 8000元/年
访问统计报告 | 1000元 | 1500元 | 2000元
FTP服务器 | √ | √ | √
在线时间 | 98% | 99% | 100%
数据备份 | √ | √ | √
技术支持 | 1000元/年 | 2000元/年 | 3000元/年

注：100M以上，价格以300元/10M来计算，以此类推

“√”表示免费支持 “支持”表示收费服务

“—”表示不适用此项服务

可支持CGI、ASP 、ACCESS、SQL等数据库。

D．WAP网站解决方案

移动互联网的是建立在WAP技术之上的，要真正应用需要三个环节，即WAP网关的建设、WAP内容服务器和WAP终端，其中缺一不可。以下是 移动互联网的一个简单示意图：

一般可以采用：WAP内容网站+租用网关的解决方案。这样投入较少，而且维护费用减少，适合于非电信运营企业。具体实施方案也可根据企业的需求做一选择：

名称 | WAP网关 | WEB服务器 | WAP服务器 | 说明
方案一 | IPP提供 | 专线T1/EI | 专线T1/EI | 配置灵活，利于维护、开发有特色、功能强大的复杂的应用网站。 可自由选择开发平台、编程语言，采用新技术等优点。 缺点：费用高。
方案二 | IPP提供 | 主机托管 | 主机托管 | 配置灵活，可自由选择开发平台、编程语言，采用新技术等优点。 缺点:维护，开发不是很方便。
方案三 | IPP提供 | 租用虚拟主机 | 租用虚拟主机 | 配置取决于所租用主机的配置，可开发功能简单的一般性网站。 优点：费用少，维护简单。 缺点：无自由配置和选择开发语言的权力，无法应用最新的一些技术。

WAP网关可以选用IPP的公共网关。

根据XXX公司目前的具体情况，我们建议采用以下解决方案：

1、 公司现有的WEB网站不变。

2、 公司的DNS上增加WAP主机的指向：wap. .com指向IPP公司的WAP虚拟主机IP地址。

3、 IPP公司为 公司提供WAP虚拟主机服务，开辟专门的FTP帐号以方便 其公司对自己的WAP网页内容进行维护（不限次数的更新）。

4、 WAP网关由IPP公司提供。

5、 WAP虚拟主机服务器和WAP网关的日常维护由IPP公司承担。

6、 对手机用户访问XXX公司的WAP网页不限制访问流量。

7、为其公司提供7X24技术支持和维护支持，必要时为其公司提供远程诊断支持。

8、 上班时间之内的预防性维护。

9、不限次数的“提问/解答”答复（例行修复和有限系统干预）；不限次数的“怎么办”答复。


W　A　P　资　源

WAP文档类
  • WAP规范1.1版本（规范全部内容，2,763k）
开发工具包类
  • Nokia Wap Tookit 开发工具包
  • Ericsson Wap IDE2.08开发工具包
  • Phone.com UP.SDK4.0开发工具包

调试模拟WAP手机
  • Ericsson R380模拟WAP手机
  • WINWAP(在Windows下查看WAP页面，1,264K)

编辑工具

Nokia WML Studio

Nokia WML Studio是为Dreamweaver开发的WML插件。可以在Dreamweaver的工作界面下，“所见即所得”地常见WAP页面。使用很方便，特别适合于习惯使用Dreamweaver的用户。在安装Nokia WML Studio之前，需要安装Macromedia Dreamweaver和Extension Manager。目前该Studio的版本为1.0.0。

去往Macromedia网站 下载Extension Manager for Windows 下载Extension Manager for Mac 下载Nokia WML Studio

Nokia WAP Toolkit

Nokia公司自己开发的WAP工具包。要知道Nokia对WAP发展的作用不小哦，所以原汤化原食，这款工具自然会使您用得得心应手。其中包含了7110手机仿真器。目前该工具包的最高版本为2.0。我用了一下，的确不错。下载这个工具包可以去Nokia开发者网站，但是需要先注册，有些麻烦。

去Nokia开发者网站 下载该工具包

Ericsson Wap IDE SDK

Ericsson公司自己开发的WAP开发环境。同Nokia一样，Ericsson的这款工具也很优秀。其中包含了R320s仿真器，并且自带了一个Xitami V2.4d3的Web服务器。目前该工具最高版本为2.1。这个工具很精致，而且界面比较有特点，您用起来一定会觉得耳目一新。工具的安装分两步，首先安装WapIDE 3pp v2.0，接着安装WapIDE SDK v2.1。所以需要下载2个文件。

去Ericsson开发者网站 下载WapIDE 3pp 下载WapIDE SDK

WAPPage

WAPPage是WAPmine推出的一款WAP编辑器，支持预览、代码阅读、卡片浏览等功能，其用户图形界面很好，并且对于事件、定时等的处理都不错。（以上摘自国外waplinks网站对其的介绍）。就我个人使用经验……其实我根本没有机会实践，因为这个程序我down下来并且安装之后，居然使我的win98无法启动，我也不敢再在别人的机器上实验了。您可以式式。其实既然有更好的软件，为什么要用他的呢？该软件最高版本为1.0。

去WAPmine网站 下载该工具

Visual Pulp

Visual pulp 是wapholesun站点提供的一款WML编辑器。这是一个用java开发的编辑器，虽然功能比较简陋，但毕竟是个人开发的免费软件，大小只有70多K。您可以下载软件以及软件源码。对于想学习人家的编程技术的人是最好不过的了。这款软件允许您在仿真窗口中添加内容，软件会自动根据您的动作产生相应的代码，这点已经很不错了。本软件最高版本为0.12。

去wapholesun站点 下载该工具 下载源码

Dotwap

Dotwap是inetis网站提供的WAP编辑工具。软件包比较小，只有600多K。界面很普通，没有什么特点，但是很简单易学，所以，如果你是初学者，用它最合适不过了。目前该软件的最高版本为2.0。

去inetis网站 下载该工具

仿真工具
M3Gate M3Gate是Numeric Algorithm Laboratories提供的WAP仿真（浏览）器。需要系统安装了IE4以上的浏览器。如果系统安装了Netscape Navigator，M3Gate将会作为它的插件存在。目前该软件最高版本为0.5。站长强力推荐。 去往M3Gate的网站 下载M3Gate | ccWap ccWap本来就是个很好的关于WAP的网站，里面关于WAP的资料很多。现在它自己也推出了自己的仿真器。左边是它的界面。目前该软件最高版本为1.2。 去往ccWap网站 下载ccWap
YoSpace YoSpace网站提供的仿真器。是我觉得最好用的啦。提供了多种平台下的仿真工具。左图是windows下的，呵呵，真好用，而且可以用http的proxy。 去往YoSpace网站 下载for windows的YoSpace 下载for mac的YoSpace 下载for unix的YoSpace 下载for sun Solaris的YoSpace 下载for os2的YoSpace 下载其它平台下的YoSpace | Wapalizer Wapalizer是gelon网站提供的在线仿真器，包括7110、R380等多种仿真器。左图是试用的Ericsson R380仿真器的界面。该网站致力于WAP技术的发展，内容包含了WAP协议等各种WAP相关技术。值得浏览。 去往gelon网站
Winwap Winwap是Slobtrot网站提供的WAP仿真工具。它支持WML 1.0和1.1。可以将WML页面保存为HTML页面。我试用了一下，界面很好看，而且比较好用。在WINDOWS下就象在用IE一样舒服。不过这个软件不是免费软件，只有14天的试用期。如果谁可以crack它，告诉我。目前该软件最高版本为2.3 Light。 去Slobtrot网站 下载Winwap 2.3 Light 下载Winwap屏保 | Wapman Wapman是virtuacom网站提供的仿真工具。其界面很好看，有些前卫。而且，它能够象winamp一样改变skin，是不是很有创意？不过，我用了一下，觉得实用性不是很高，而且用起来不太方便。大家可以试试。目前该软件的最高版本为1.4。 去virtuacom网站 下载wapman
Wapsody Wapsody是IBM alphaWorks提供的仿真工具。它是基于Java的。不仅可以提供客户端的仿真（即浏览器），也可以提供整个WAP环境（包含客户机、服务器和网关）的仿真。试用了一下，觉得一般。 去alphaWorks网站 下载Wapsody |

图象工具

Pbmwbmp pbmwbmp是looplab网站提供的图象转换工具。可以在pbm和wbmp文件格式之间转换。是linux平台下的工具，有源码。注意，左图可不是程序界面，左图只是looplab网站的logo。 去往looplab网站 下载pbmwbmp-1.0.tar.gz 下载pbmwbmp-1.0-1.i386.rpm | Bmp2wbmp bmp2wbmp是waptiger网站提供的图象转换工具，可以在bmp于wbmp文件格式之间转换。包含windows/dos和linux不同平台下的版本，而且带源码。左图同样不是程序界面，只是waptiger网站的logo。 去往waptiger网站 下载bmp2wbmp（windows/dos） 下载bmp2wbmp（linux） 下载源码
Pictus Pictus是一个捷克网站checkit提供的图象转换工具，一个很正规的软件。可以在jpg、bmp和wbmp文件格式之间转换，可以调整分辨率，使用不同的抖动效果，并且可以根据不同的终端机调整图象大小，应该说是少有的功能比较强大的wbmp工具了。目前最高版本1.0。 去往checkit网站 下载Pictus | Pic2wbmp Pic2wbmp是Gingco网站提供的基于Java的图象转换工具，可以在多种文件格式与wbmp之间转换。操作简单，界面友好，用了一下，还不错。目前该软件最高版本为1.0。 去往Gingco网站 下载Pic2wbmp
Wapdraw Wapdraw是phnet网站提供的wbmp图象编辑器。左边是其界面。可以定义图象大小，可以使用画笔等工具，功能比较简单，用了一下，觉得用来创建简单的图象挺好，如果复杂一点就不成了。所以可以自己装装玩玩啦。目前该软件最高版本为1.01。 去往phnet网站 下载Wapdraw | Applepie Applepie是applesolutions网站提供的一个在线的gif到wbmp的转换工具。左边是该网站的logo。在该网站中敲入图象文件的url，这样就可以下载到该wbmp格式的图象了。 去往applesolutions网站
Teraflops Teraflops网站也提供了在线的转换工具，可以将本机的gif、jpg或bmp图象转换为wbmp格式的文件，其版本为1.0.02。左边是它的logo。 去往Teraflops网站 | Creationflux Creatinflux网站提供了一个photoshop的插件，不过只是Mac平台下的，有些不爽，我没有用过。你试试吧！ 去往Creationflux网站 下载插件

网关服务器

Ophelia & Kannel

Kannel的先前版本并不支持WTLS。这次在Ophelia找到了支持WTLS的Kannel Server了，这可是开放源码的好东西哦。如果已经安装了Kannel Server，那么还提供了WTLS补丁程序。

去往Ophelia网站 下载Kannel with WTLS 下载WTLS补丁

Ellipsus espresso

Ellipsus的Espresso 0.2BETA全部由Java实现，对面向连接和非连接的服务全部支持。也支持POST与GET。有很详细的PDF文档，介绍如何搭建WAP网关与服务器。

去往Ellipsus网站 下载Espresso 0.2BETA 下载readme.pdf

Ophelia

Ophelia以基于线程的方式非常有效地实现了WAP协议栈。它支持面向连接和无连接的WAP请求，它几乎支持WTLS中所有的加密算法，除了RSA以外。Ophelia可以运行在Linux、BSD、Solaris、SGI、Win NT、Win 98等多种平台下。

去往Ophelia网站 下载Ophelia 0.4

Expressway 2000

由英国公司Dialogue为Nokia WAP服务器专门开发的Email连接器，以作为标准的Nokia WAP服务器配置之一。在安装完连接器后，可以使用Expressway 2000的控制面板直接进行服务器的配置。

去往Nokia Forum网站 下载Expressway 2000

Jataayu

一个印度的网站Jataayu提供的服务器软件。为不同的平台准备了不同的版本。我装了windows的试了试，很easy哦。（看看人家印度好象也走到我们前面了啊。）

去往Jataayu网站 下载for windows的Jataayu 下载for SCO UnixWare的Jataayu 下载for RedHat 6.1的Jataayu 下载for RedHat 5.0的Jataayu 下载注册码

Gnuws

一个开放代码的WAP网关程序，最新的版本是4月7日公布的。运行平台是Red Hat Linux、Slackware或Solaris。

去往Gnuws网站 下载该代码

Melody Wap Mail

Melody Wap Mail是一个功能完备的Wap Mail服务器，它使得移动终端（WAP手机和PDA）可以收发电子邮件。它使用标准接口与其它的Mail服务其器软件通信，可以方便快速的设置帐号和口令，界面友好。目前最高版本为1.03。有免费版和收费版。免费版最多支持10个用户，试试？（分NT和Linux两个版本，软件注册码为：5025-7577-7928-9989）注意，左图不是程序界面。

去往Melody网站 下载NT版本 下载Linux版本

Waplite

Waplite提供的优秀的WAP服务器软件，分免费试用和收费两种版本。可将WAP手机与Internet连接起来，支持7110、MC218等多种设备。免费版本有30天的试用期。收费版本根据价格可以支持不同数目的并发用户数目。现在支持无限多用户的版本已经作好了。您可以去Waplite网站定购哦！目前试用版本为1.10。

去往Waplite网站 下载Waplite试用版本

RealGewi

RealGewi是RealWow网站提供的WAP网关。软件很小，功能不强大。分两种版本，一种是免费版本，功能较少，一种是收费版本（很便宜），功能功能多些。Beta版本的软件功能和收费版一样，但是有失效期。该软件只支持HTTP/GET，还支持WML到WML二进制码的转换。目前该软件版本为1.0，试用版本为beta3。

去往RealWow网站 下载RealGewi Beta版

Kannel

Kannel提供了Linux平台下的WAP网关。这个软件是免费的，而且代码公开，让人放心哦。不过该网站上没有关于该软件的介绍，我也没有试过，所以大家下载玩玩吧。记得把体会告诉我哦！目前该软件最高版本为0.12.3。（左图是kannel网站的logo）

去往kannel网站 下载readme 下载ChangeLog（软件记录） 下载NEW文档 下载源码（tar） 下载源码（zip） 下载结构与设计文档（tar） 下载结构与设计文档（zip） 下载RPM包 下载RPM的spec文件

Audicode

Audicode网站提供的for windows的WAP服务器。网站上吹的很牛。它不仅是网关，而且是一个真正的服务器。目前有两个版本，一个是免费版本（只支持一个用户），一个是收费版本。目前最高版本2.0。可以单独下载帮助文件、wml编码器和wmls编码器。抱歉，完整的audicode服务器软件有1.6M，但我总是下载失败，正在想办法。（左图是网站上的宣传图片）

去往audicode网站 下载aws20demo.zip 下载wml encode 下载wmls encode

Nokia Wap Server

诺基亚的WAP Server就不用介绍什么了。诺基亚是WAP大拿，做的东西自然功能是没得说了，当然，价钱也没得说的，好象很贵哦。不过，诺基亚好象很体谅有些想过过瘾的Wapper，所以提供了一个30天的试用版本。Nokia的Wap server软件很大，有10M多，分特！！！我下载了十几次都失败了。。（左图只是Nokia的宣传图片）

去往nokia forum网站（试用版本） 去往nokia网站（正式版本） 下载Nokia Wap Server试用版

免费的WAP主页空间
Mobitext Mobitext不仅提供了免费的WAP主页空间，而且使您可以在线编辑您的主页。我连过去了看了看，比较有趣。一般而言，您的WAP主页地址为：http://mobitext.com/go.cfm?yourid。做好主页，可以预览。Mobitext使用的仿真器是gelon网站提供的在线仿真器。左图就是我的注册一个帐号下的WAP页面哦！好玩吧！ 去往Mobitext网站 | Frazerandorr Frazerandorr提供了免费的WAP空间。需要填表获得该空间，表中一般要写住址什么的，也可以写自己需要的空间的大小。申请通过后，网站会发通知到你的信箱里。左图是这个网站的宣传图片。嘿嘿，看上面的机器是什么型号的？？看出来了吧－－7110。 去往Frazerandorr网站
Wapspy Wapspy提供了免费的WAP空间。我刚看到Wapspy网站，就觉得它有些象yahoo，因为它的样子让人觉得它很专业，可以在Wapspy搜索WAP网站，它还提供了WAP图象资源（WBMP），去看看吧。左图是它的logo。 去往Wapspy网站 | Wapdrive Wapdriver和Wapspy有些象，都是很好的网站，它提供了免费的WAP空间，而且还可以搜索WAP网站。另外，它除了提供在线WAP页面编辑外，还允许您在线编辑图画。这个网站还包括WAP新闻等内容，挺丰富的。左图是它的logo。 去往Wapdrive网站
Tagtag Tagtag提供了免费的WAP空间，提供在线编辑WAP页面的功能。不过只允许在线编辑哦，也就是说，你不能上载在本机上编辑好的页面。左图是它的宣传图片。 去往Tagtag网站 | Hoiley 这是一个WAP之家。在这里可以在线创建WAP页面，而且可以使用网站提供的一些模板，轻松实现一些功能。该网站还使您可以在线创建免费的WAP聊天室、WAP SHOP等，还提供了免费的无线FTP功能。在该网站，也可以进行WAP网站的搜索。去看看吧。左图是它的logo。（现在该网站也提供收费的商业服务） 去往Hoiley网站
Sowap 一个法语的网站，偶看不懂了。看Waplinks网站上介绍说它支持php哦。嘿嘿，如果你会法文，就看看吧。不会也可以乱蒙啦。 去往Sowap网站 | myFON 也是一个提供免费主机空间的网站。左图是它的宣传图片，看的出是什么手机吗？对，是高通的。 去往myFON网站


WAP Server

如何设置WAP Server？
http://www.sina.com.cn 2000/06/23 12:56 新浪科技

基于WINDOW NT 平台的IIS设置WAP Server

只要按照以下的简单设置，就可以让NT IIS成为WAP服务器，您可以撰写WML网页或者开发各种服务。

设定方式：(先确定NT Server已经安裝IIS了服务)

执行NT操作系统下的【开始】/【程序】/【Windows NT Option Pack】/【IIS 4.0】/Internet服务管理员。

在IIS服务管理员窗口內，点选主机电脑名称后，按鼠标右鍵，点选“属性”选项；

在属性窗后下部有一个文件类型按钮，单击此按钮，会出现文件类型界面；

单击‘新增类型’按钮，然后在相关的扩展名栏中填写 .wml ,在内容类型（MIME）栏中填写 text/vnd.wap.wml

单击‘确定’按钮

重复以上步骤将以下WML类型新增至MIME內：

相关的扩展名 內容类型(MIME)
.wml text/vnd.wap.wml
.wmlc application/vnd.wap.wmlc
.wmls text/vnd.wap.wmlscript
.wmlsc application/vnd.wap.wmlscriptc
.wbmp image/vnd.wap.wbmp

Apache Web Server

不管是NT 还是UNIX 或LINUX ，都是修改 Apache 安装目录下的conf/mime.types文件

在该文件中增加以下内容：

text/vnd.wap.wml .wml
image/vnd.wap.wbmp .wbmp
application/vnd.wap.wmlc .wmlc
text/vnd.wap.wmls .wmls
application/vnd.wap.wmlsc .wmlsc

存盘

重新启动APACHE WEB SERVER 即可。


WAP系统构建

系统构建

1. 网络拓布结构

无线终端 ( 手机, PDA ...) 借助ＷＡＰ服务器通过因特网与源服务器（WEB 服务器, Email 服务器)连接, 信息通过同一通路返回到无线终端。

2. 系统构造
不同的拥护也许会选择不同的配置方式，例如：

拥护形态 | 拨号服务器 | WAP 服务器 | 源服务器
ICP |  |  | √
普通使用 |  | √ | √
企业使用 | √ | √ | √

ICP 只提供WAP/Web内容，网络接入和WAP网关可以由其他公司（例如电讯）提供。

一般用户（例如电子商务网站）需要建立自己的WAP网关以实现安全连接，提供增值服务。接入服务可由其他业者提供，例如ISP。

企业WAP应用是为小规模的无线用户（例如企业内部人员，同时使用人数不超过100-500）的无线连接和代理服务。

我们为企业用户提供以下三种方案：
手机：WAP 手机加上数据传输
接入服务：NT Server 或 Linux；Modem(与普通电话线或ISDN连接)，ISDN 能够改进WAP接入速度 ；远程接入服务或路由和接入服务（带路由功能）
WAP 服务器：256M RAM，网卡(与Internet/Intranet连接)；NT 服务器 (SP4 和更高配置) 或 Linux；Nokia WAP 服务器；Nokia WAP 服务器安全包(安全传输，安全认证和接入，可选)；Nokia WAP 服务器 SMS 载体包(支持短信息，可选)；
Web 服务器：IIS 或 Apache；WML/WMLScript。

为实现SMS上的信息“推”服务，您需要内置modem的手机，相应的软件(Nokia的Cellular Data Suite、7110'的 Expl 等)。

3. 功能模块
为无线通讯或WAP提供增值服务；
在WML之上发布与查询公共信息(新闻，黄页，天气，交通，运输时刻表，在线交通指南，电话号码簿，电视节目等；
PIM：个性化的信息管理

个性化的电子商务服务：
打折信息，价格优惠，促销活动，价格比较，采购指南，产品查询，订购，订票，订餐，在线交易，订单确认，发货通知，到货通知，期货信息，期货/股票交易，银行/金融服务，存款转帐/查询。

企业内部业务系统：
发布即时产品价格信息，存货，订单，黄页，重要通告等

4. 构置步骤

采购硬件设备： 电话或ISDN线, 网卡, RAM, 手机 (带数据线以发送SMS)
设置接入服务器；
设置Nokia WAP服务器和其他软件;
安装收集软件包，以实现SMS消息传输；
设置Web服务器，以支持WAP连接；
转换HTML/JavaScript至 WML/WMLScript.


WAP与INTERNET的比较

如图2-1所示，图的左边是Internet的各个层次，图的右边是WAP的各个层次。
一、因特网三层架构 WAP（无线通讯协议）是在数字移动电话、因特网或其他个人数字助理机、计算机应用之间进行通讯的开放全球标准，就像HTTP协议一样是一种标准，规定了WEB 服务器与客户浏览器交互的方式、规范。我们先了解一下WEB服务器的工作方式和原理。图2-2表明了客户向URL所指定的WEB服务器发出了请求，WEB服务器根据请求的程序返回相应的内容至客户端，二者就是按HTTP协议进行交互的。客户端发出一个以HTTP开头的URL请求时，WEB服务器端的程序可能是CGI程序、或静态网页，或SERVLET程序，也可能是其他服务器端程序，但它们均以HTML格式将相应的内容返回给客户，这样客户就可在浏览器上的看到返回的内容。
二、WAP网络架构 WAP网络架构由三部分组成，即WAP网关、WAP手机和WAP内容服务器，这三方面缺一不可！其中WAP网关起着协议的'翻译'作用，是联系GSM网与万维网的桥梁；WAP内容服务器存储着大量的信息，以提供WAP手机用户来访问、查询、浏览等。图2-3表明了WAP网络的基本架构。当用户从WAP手机键入他要访问的WAP内容服务器的 URL 后，信号经过无线网络，以WAP协议方式发送请求至WAP网关，然后经过'翻译'，再以HTTP协议方式与WAP 内容服务器交互，最后WAP网关将返回的内容压缩、处理成BINARY流返回到客户的WAP手机屏幕上。编程人员所要做的是编写WAP内容服务器上的程序或曰WAP网页。
图2-3


网站设计-电子商务咨询

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网站设计-电子商务咨询

我们的咨询服务帮助您构思您的互联网战略， 包括投资回报分析，电子商务实施的时间表，投资额，以及网站建设的步骤。某些内容将在首次的免费咨询中进行讨论。

1. 客户介绍

  • 产品与服务
  • 市场态势
  • R&D, 设计与生产能力与技术
  • 其他(采购，仓储，货运，售后服务，支付体系等）
  • 电脑和办公自动化应用，MRP II, ERP 等
  • 网络 (LAN,WAN 等）
  • 目前网站情况(Internet/Intranet/Extranet)
  • 企业数据库应用

2. 网站设计和电子商务的目的

  • 服务对象
  • 网站访问者的特征以及消费偏好
  • 产品与服务种类以及格最佳的表现形式
  • 预计的获利与效率提升

3. 网站与市场研究

  • 您的主要竞争对手
  • 他们的网站
  • 他们的赢利模式分析

4. 您的核心竞争力

下列那一条符合您的企业 ?

  • 良好的客户与社会关系
  • 可靠的供应商渠道
  • 在以下方面降低采购/营销费用：通讯，运输，文件处理，以及促使交易的透明化
  • 价格信息丰富
  • 质量可靠
  • 声誉良好
  • 提高采购效率
  • i借助网站推行业务流程和生产管理

5. 实施电子商务的构思

  • 决定是否需要在线营销功能，如是，则说明
    • 支付手段
    • 安全与认证渠道
    • 交货方式
  • 实施电子商务的时间表

6. 费用

  • 网站建设（主机设置）
  • 网站/网页设计 (咨询，市场研究，网站策划和页面制作)
  • 网扎运行和维护
  • 网站的推广与营销

7. 对员工的要求

  • 网站维护人员 (硬件与软件)
  • 网站更新人员 (总体策划，程序开发，数据库，美工制作，内容编辑，语言翻译等）

8. 电子商务实施步骤

  • 注册域名
  • 租用空间
  • 市场调研
  • 信息收集
  • 网站策划 (风格，内容，功能，语言，技术等）
  • 网页制作
  • 网站发布和测试

9. 网站推广

  • 网站开发阶段考虑如何推广您的网站
  • 搜索引擎注册
  • 在主要的网站购买广告位
  • 免费的链接和旗标广告
  • 传统的广告方式 (报纸杂志等)
  • 其他

12. 参考网站

  • 告诉我们您认为值得推荐的网站
  • 或者您不喜欢的网站
关闭窗户


Consultation
Our consultation helps you to work out your Internet strategy, incl. your possible return of investment, your timetable for implementation, investment, and steps for building a website. Some of the following topics will be discussed during the first free meeting:

1. Client's introduction

  • products/services
  • market situations（area distributions, sectors distributions, market volume, market shares and future trends）
  • R&D, design capacity and facilities
  • production technologies/capacities/facilities
  • others (procurement,warehousing, transport/after-sales services/payment systems)
  • computer and OA applications, incl. MRP II, ERP etc
  • network status (LAN,WAN etc）
  • your current website (Internet/Intranet/Extranet)
  • enterprise database: databases and their distributions within your company

2. Purpose of building website and promoting e-commerce

  • your purpose of building a web presence ？
  • whom do you serve your products ？
  • what are the characters of your website visitors and their consuming behaviors ？
  • what kinds of products/services can you provide ？
  • in what form are best for your products/services to be presented ？
  • predicted profit & efficiency increase

3. Website study and market research

  • your main competitors
  • their websites
  • anatomy of their e-commerce functions

4. Core of your competitiveness

which of the followings apply to you ?

  • well-established client and social resources
  • reliable supplier channels
  • cost reduction for purchase/sales in the areas below:

    • communications, transport, documentation, and improved transparency of business transactions

  • rich price info
  • reliable quality
  • good reputation of the company
  • increased purchase/sales efficiency
  • implement business management and production coordination via the site

5. Implementation configuration

  • decide if you have an online sales function. If yes, indicate
    • payment methods
    • security and certification
    • delivery
  • timetable of the e-commerce strategy

6. Cost

  • site installation (hosting)
  • website design (consultation, market study, site plan and page design)
  • operation & maintenance
  • website promotion

7. Requirement of your staff

  • maintenance personnel (hardware & software)
  • website updating personnel (overall plan, programming, database, creative, content editing, language translation etc

8. Procedures of implementing a e-commerce plan

  • register domain
  • hosting
  • market study
  • collect information
  • website planning (styles, content, functions, languages, technologies etc)
  • page design
  • publish and test your content

9. Venture capital, financing, investment, and capital market - for industry portals only

  • sources of investment: public companies, VC companies etc
  • requirement of management team
  • uniqueness of you products/services/company
  • investment & return analysis

10. Promotion of your website

  • considerations at time of design
  • register by search engines
  • buy advertisement in major websites
  • free links & exchange of banners
  • traditional marketing (newspaper/magazines etc)
  • others

11. Others

  • quality system and its certification status
  • management environment of the company

12. Reference website

  • tell us which websites do you consider as your reference for building your own ?
  • or which websites you hate most ?
close

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网站设计-网站内容编辑，培训与翻译

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网站设计-网站内容编辑，培训与翻译
内容编辑服务
富有创意和高品位的网站，依托的是企业文化内涵、视觉形象和各种互联网技术的完美结合。我们拥有专业的网站创意策划和视觉形象设计团队，我们有能力把握您公司的企业文化，运用贵公司的视觉形象系统，为您塑造一流企业网站，使得贵公司的网站在Internet的信息海洋中更具竞争力。

    我们以自己的实力保证：

  • 将企业识别系统（CIS）中视觉形象（VI）的LOGO、标准色、标准字等充分的运用在企业网站设计中，强化公司LOGO在访问者的视觉印象，让访问者产生记忆，从而留下对公司的认知感和亲切感。
  • 在创意设计、网站整体架构规划上重点突出公司的行业特点、服务宗旨。提升企业理念，塑造公司品牌形象。网页设计、制作上充分利用Flash动态效果，渲染页面的设计表现力、有动感，展示企业的创造力与活力。

时力设计小组是专业版的网页设计小队，我们的图形设计和方案，在网络站点自称拥有专家水平。我们的每个成员交付你诚实地并且高效地服务。我们具创造性的队伍将为你设计并且开发网站。
我们有有力扫描设备能容易拷贝你的公司文学。如果费用超过你的预算，我们能为了减少你的费用重估并且工作。记住你不会被过高支付我们的网页设计服务，直到你满意于最后的结果。

如果你的地点与我们接触困难，那么别担心。因为我们大部分由电子邮件交流，也可以通过电话和传真通讯与我们的顾客接触。

你可以今天就联系我们，利用这种绝妙的服务，我们盼望听到你的消息！
编辑的内容

  • 首页设计，包括

    • 公司标记(logo),
    • 多媒体技术的采用，
    • 图像，
    • 导航结构，
    • 背景，
    • 颜色，
    • 字体，
  • 数据库的选择
  • HTML 编辑,
  • Java, Java Script, PERL, PHP等的编程
  • XML与其他电子商务数据交换 ...
  • 图象设计: logo 设计,数字影像等
  • 网站语言-英文，德文，中文等
培训服务
时力公司为方便客户自己进行网站的管理和维护，培养和壮大网络科技队伍，我们特举办了“网管人员培训班”由经验丰富和精通网站管理的网站设计师任教，备有多媒体电脑及详尽的教学计划、深入浅出的教学方法和大量的相关软件、书籍和光盘。包教包会，学会为止。并推出了:“在客户网管人员未毕业前,我们将免费为客户网站进行维护”的优惠政策,以解决客户的后顾之忧。
  • 初级班
    培训费： 300元
    培训时间： 5天
    培训内容： Internet Explorer5.0、Pronpage2000、Cutefpt4.0
    掌握技能： 全面掌握网页浏览技巧、邮件接收发送、网站的上传、下载、更新，
               熟练承担网页的基本编辑工作。
  • 中级班
    培训费： 800元
    培训时间： 10天
    培训内容： Dreamweaer4.0、Flash5.0、PhotoDraw2000
    掌握技能： 掌握网页图形、图片的制作、编辑和创意，Flash各种动画及网页特效的制作。
  • 高级班
    培训费： 1200元
    培训时间： 15天
    培训内容： Macromedie闪光三剑客、Dreamweaer4.0、Firework4、Flash5、HTML JAVA
               编程及Web数据库(Mysql\PHP、Access\asp)开发、管理
    掌握技能： 掌握和使用Macromedia公司的“三剑客”，能够掌握制作高级网站及网页的
               各种技能，熟练运用HTML和Java制作网页和脚本文件，掌握支持电子商务运
               作的Web数据库管理系统。

网站翻译服务
时力公司为以下的客户提供网站内容翻译：
  • 国外的公司／个人：如果您欲将有关的内容发布到位于中国的网站上，因此您需要在原先的语言版本之上增加一个中文版本的网站；
  • 国外的公司／个人：还没有自己语言的网站，但有意建设一个中文的网站以满足他的中国客户的要求。
  • 国外的公司／个人：　已经有了一个中文网站，但其内容并没有体现出原有的语言的网站的风格和精神，因此需要进行修改。
  • 国内的公司／个人：希望建设一个外语网站，例如英语，法语等...;
  • 国内的公司／个人：已经有了一个外语的网站，但需要修改或更新
翻译内容
  • 图像／动画／动画／声音／影像：大多数的图像和其他多媒体需要修改，去掉中文，代之于英文或相反。
  • 数据库：如果网站是交互性的　－　也就是说，信息可以通过从数据库查询得到，您必须做以下的二件事情：
    • 修改您的数据库 - 包括数据表，视图，流程图，存储过程 ... ，　然后将所有的内容都一一取代，翻译；
    • 修改您的所有与数据库有关的代码 - perl, php, cgi, ASP, JSP, CFML 等。
正如上述，网站内容翻译不是一般意义上的翻译　－　它与网络技术有关。　您必须熟悉网络的基本技术才能完整地翻译网页　的内容，除非您的站点主要是由静态页面组成。
价格
  • 普通 (静态文本) 翻译:
    • 英文 -> 中文: 300RMB/1000 英文单词
    • 中文 -> 英文: 400RMB/1000 中文字符
    • 其他语种 + (30-80%) 取决与语言种类和涉及的行业类别。
  • 图象和数据库内容，编程内容的翻译需要面谈讨论。


web content editing and design
  • First page design to decide for basic tune of the website, incl.
    • logo,
    • multimedia techniques (Flash, Shockwave, Audio/Video),
    • images and animation,
    • navigation structure,
    • background,
    • color,
    • font
  • website interactive databases design
  • HTML authoring,
  • Java, Java Script, PERL, PHP, and other programming techniques
  • XML and other e-business data exchange format
  • image design: logo, digital photography .
  • languages - English, German, Chinese ...

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网站合作

我们将众多的独立商业网站比作星星，你愿意做天边的一颗孤星，还是在星群中耀眼夺目，这就是与其他网站合作的意义。现在流行的友情链接是最简单的一种合作方式，有什么更好一些的合作技巧吗？

1. 栏目内容合作：创造一些很多网站都需要的有价值的内容，主动与可能会感兴趣的网站联系。当有些站点访问量很高时，你可能会产生某些畏惧心理，事实上这些站点也在不断吸收一些好的内容来补充自己的站点，如果从你的站点能拿到好素材，他们不会介意链接你的网址。

2. 品牌站点借力： www.CHINAMARKET.com.cn 是经贸部下属的大型商业网站，这个网站按产品分类，汇集了大量国内网址。与这种品牌站点协商互联的最好办法是准备一个成功故事。上海的富大胶带站点在1998年锲而不舍地请求与各大网站互联，最后功夫不负有心人，成为CHINAMARKET中的成功案例。

3. 多类型公司互联：与主题有相似之处而又非竞争对手的网站建立联盟。比如我们尝试进行旅游行业客户联盟，对象就可以是海南天域酒店、新加坡航空公司、云南探险旅游、天下第一城、北京香山滑雪场、国旅海外等等。站点联盟中的相互链接比宣传个别站点的效果更好。


网络数据库

国内主要数据库 | 国外主要数据库 | 其他数据库

业务范围
数据库存放着企业或个人的关键数据。广义来说，所有信息都是数据：文本，数字，文件，图像，照片，动画，声音，影像，图纸。这些数据以很多种不同形式存在，从微软的办公系列软件(Word, Excel, Outlook, PowerPoint, Frontpage, Publish...) 本地化的中文软件如 WPS 2000. 绘图软件如 Photoshop, 3D MAX, Authoware 则是处理图像数据的软件。.

狭义的数据库是指结构化的数据，例如生产过程的数据，销售记录，天气预报等。没有图像，没有多媒体，只有简单的文本和数字。

目前流行的数据库软件包括 Microsoft SQL Server, Oracle, DB2, Sybase, Informix 等.利用这些数据库应用系统您能够存储，处理和输出您的数据，长期保存 - 可以是单机，页可以是局域网。

时力公司作为一个网络技术服务商，帮助企业和个人建置从独立PC机， Internet，Intranet 到Extranet 采用 TCP/IP协议的各种数据应用. 或许您准备将您的某些产品/价格信息发布到您的客户/供应商/合作伙伴，您也许希望使您在办公室的业务数据与您的网站数据库保持同步。时力将使您的梦想成真。

借助最新的数据广播技术，我们能够将您的数据发布到任何网站，在任何的平台上，采用任何数据库，包括：
  • 平台: Windows 2000/NT/98/95, Unix, Linux, Solaris ...
  • 数据库:
    • SQL Server,
    • Oracle,
    • Informix,
    • DB2,
    • LotusNotes,
    • mySQL,
    • Sybase
  • 数据形态: 数字记录, 文本, 图像, 动画和多媒体, ..
请与时力联系，我们的 技术专家 会回答您所有的问题，提供您关心的数据发布问题的答案。


Database development
Databases are where critical enterprise or personal information are safeguarded. In its broad meaning, all kinds of information are data: texts, numeric data, documents/files, images/pictures, photo, animation, audio, video, drawings, and they are now kept in thousands of formats, from well-known Microsoft Office family programs (Word, Excel, Outlook, PowerPoint, Frontpage, Publish...) to native Chinese software such as WPS 2000. Graphic applications such as Photoshop, 3D MAX, Authoware are also software for handling and saving image data.

In its narrow definition of database, we are talking about those application which process only the structured data, such as records during a production process, sales records, whether forecast etc. No images, no multimedia, only plain texts and numeric.

Prevalent software of databases include Microsoft SQL Server, Oracle, DB2, Sybase, Informix etc.Using these databases you can store, process and output your data and keep them for long use in a variety of environment - from standalone computer to Internet use.

And now solaires, as a web-based company, helps companies and individuals to deploy their locally maintained to Internet/Intranet or Extranet over TCP/IP. You probably want to publish some of your products info, prices info to your clients/suppliers/partners, and you also want to synchronize your data in your own office with those of your websites. And solaires makes your dream become true.

With up-to-date web data broadcasting technologies, we can publish your data to any of your websites, in any platforms, and of any data type in any databases,incl.:

  • Platforms: Windows 2000/NT/98/95, Unix, Linux, Solaris ...
  • Databases:
    • SQL Server,
    • Oracle,
    • Informix,
    • DB2,
    • PowerBuilder,
    • Delphi,
    • VisualFoxpro,
    • LotusNotes,
    • Jasmine,
    • mSQL,
    • mySQL,
    • postgreSQL,
    • Access,
    • Excel,
    • iBASE,
    • DM2
    • and plain text formats (notepad or wordpad)
  • Data type: records, texts, images, animation and multimedia, just name a few...
Contact solaires for a consultation, our technical experts will answer all your questions and give suggestions of your data publishing plan.
close


Database Development
Databases China
Databases World
Databases Other
Databases are where critical enterprise or personal information are safeguarded. In its broad meaning, all kinds of information are data: texts, numeric data, documents/files, images/pictures, photo, animation, audio, video, drawings, and they are now kept in thousands of formats, from well-known Microsoft Office family programs (Word, Excel, Outlook, PowerPoint, Frontpage, Publish...) to native Chinese software such as WPS 2000. Graphic applications such as Photoshop, 3D MAX, Authoware are also software for handling and saving image data.

In its narrow definition of database, we are talking about those application which process only the structured data, such as records during a production process, sales records, whether forecast etc. No images, no multimedia, only plain texts and numeric.

Prevalent software of databases include Microsoft SQL Server, Oracle, DB2, Sybase, Informix etc.Using these databases you can store, process and output your data and keep them for long use in a variety of environment - from standalone computer to Internet use.

And now solaires, as a web-based company, helps companies and individuals to deploy their locally maintained to Internet/Intranet or Extranet over TCP/IP. You probably want to publish some of your products info, prices info to your clients/suppliers/partners, and you also want to synchronize your data in your own office with those of your websites. And solaires makes your dream become true.

With up-to-date web data broadcasting technologies, we can publish your data to any of your websites, in any platforms, and of any data type in any databases,incl.:

  • Platforms: Windows 2000/NT/98/95, Unix, Linux, Solaris ...
  • Databases:
    • SQL Server,
    • Oracle,
    • Informix,
    • DB2,
    • PowerBuilder,
    • Delphi,
    • VisualFoxpro,
    • LotusNotes,
    • Jasmine,
    • mSQL,
    • mySQL,
    • postgreSQL,
    • Access,
    • Excel,
    • iBASE,
    • DM2
    • and plain text formats (notepad or wordpad)
  • Data type: records, texts, images, animation and multimedia, just name a few...
Contact solaires for a consultation, our technical experts will answer all your questions and give suggestions of your data publishing plan.


网站设计-网站建设，策划，研究

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网站设计-网站建设，策划，研究
网站建设-域名注册与主机租用
网站内容咨询服务

无论是发布一个新网站或是更新网站现有内容，如何策划和编辑网站内容都是最关键也是最困难的工作。虽然一个网站通常都是由程序员、美工和营销人员共同参与完成的，但实际上这些人员往往会更容易专注于自己的专业领域而忽视了网站的整体特性和访问者的感受，使网站在某些方面十分突出而在某些方面存在明显不足，从而影响了网站的整体营销效果。网站的内容是为访问者服务的，只有解决了诸如访问者喜欢在您的网站上看到什么样的内容和这些内容以何种形式表现出来才能被访问者所喜爱之类的问题，网站内容的策划和编辑才有了基本的依据。我们的内容咨询服务正好切中此问题要害！我们会从网上定义您的访问者，针对网站的内容征求他们的意见，总结成功的内容服务的必要条件，使您的网站的内容建设成为今后成功的基石。
竞争分析服务

针对同一目标市场，竞争者们往往采用不同的策略和方法展开营销。这些方法是如此多样以至于您不可能同时全部采用！我们的竞争分析服务可以帮助您了解对手的网络经营策略：他们的产品和服务、营销策略、公关策略和广告策略等等。以用户的眼光来评价这些策略的优劣，另外我们会在为您准备的报告中提出我们的建议，使您能够取长补短，为您制订正确的市场策略提供有益的帮助.
在线市场调查服务

作为市场营销不可或缺的部分，市场调查对您的成功无疑是十分重要的。我们会利用我们的资源和知识为您提供在线市场调查服务，从设计调查问卷到技术设备支持；从实施调查到整理分析调查结果，我们可以为您提供一条龙的服务。我们将和您的营销人员紧密合作，成为您的得力助手！
网站评估服务

假如您的网站没有给您带来预期的回报或是您希望网站获得更大的成功，我们强烈推荐您采用我们的网站评估服务。我们会根据您的要求对网站的结构、内容、功能、设计、营销手段、市场地位和潜力等诸多方面做出客观的评价, 同时为您提供全面的对策和服务, 从网站建设和市场营销等诸多方面入手加以改进，使您的投入得到应有的回报!
网站策划服务

在与您的网站设计公司合作以前，先明确您的网站的目的。这个时候您关心的不是您的网站内容的颜色或字体，而是您如何选择网站的模式。不管您是设计一个新网站还是更新您的旧网站，只有当您确定了您的因特网公司的目标以后，您才能制订您的预算，安排您的时间表。

时力优秀的创意设计团队将根据企业主营业务与网站建设目的，精确分析确定包括网站形象定位、网站功能定位、目标访客定位、信息结构设计、导航体系设计、栏目设置、页面总量等内容。最终出具一套完整的《网站建设方案书》。策划和创意工作适于网页数量较大，需要有较复杂的结构设计和整体CIS的策划。

《网站建设方案书》经双方协商、沟通确认之后，设计师就可以开始做版面创意设计方案，接下来的工作是客户方对版面设计效果定稿。

倘若您还不很明确您的目标，以下的表格也许会帮助您作出决定：

网站的形式 | 目的 | 特征
按功能分：
介绍型网站 （1） | 让世界各地的客户了解您的公司 | · 若干图片（LOGO & 照片） · 公司介绍 · e-mail 或留言簿
电子商务网站 （2） | 世界各地的客户能够从您的网站采购商品 | 除（1）外增加: ·购物车 ·在线支付 ·安全数据传输
数据库驱动的网站（3） | 使客户/用户维护他们的帐号。搜索您的产品资料，了解更多的有关部门您的公司产品的信息 | 除（1）外增加: · 客户服务数据库 · 搜索工具
Extranet（4） | 您能够利用您的网站与您的客户和供应商安全地共享敏感的数据 | 除（3）外增加:: · 利用密码摄制访问许可 · 设置数据安全机制
按表现形式分：
专业网站 | 功能全面、界面分明、信息量大，设计与技术并重，适合所有企业、组织、政府或学校建立能够充分体现实力与权威的专业网站 | 以数据库查询为特征
形象网站 | 运用多种多媒体技术，力求超强的表现力和视觉冲击力，偏重设计，适合娱乐、设计和媒体等行业的企业形象站 | 以多媒体为特征，包括音频与视频
商业网站 | 可实现产品展示、在线订单、在线商厦等功能的商务网站，适合分销与信息服务等企业。 | 网上商城，拍卖等商业网站

您的竞争对手

为了帮助您的设计公司了解您的需求，您可以选择提供一个竞争对手网站的清单。您应该告诉您的设计公司什么地方您喜欢，什么地方您不喜欢。设计公司将据此来构建您的网站，包括网站特征的定义，以及格估计您的站点的规模。

做最好的

您应该将您的目光盯住您的最强有力的竞争对手。告诉您的设计公司您最喜欢或最不喜欢哪个公司的网站。

策划内容

网站策划包括单不限于:

1.首页设计, logo, 菜单和布置

2.站点的导航结构

3.网站技术的应用

4.网站内容的计划

5. 最后是有关背景，字体，颜色等的确定
虚拟主机配置与价格比较表
国内
诺亚思网络 | http://www.hothost.com.cn
 | 提供虚拟主机网络资源大全
网络时代 | http://www.now.net.cn/
 | 提供JSP支持
东方网景 | http://www.east.cn.net/
信诺立网络 | http://www.sinonets.com.cn/
263在线 | http://www.263.net/
信海科技 | http://www.chinadns.com/
 | 提供JSP支持
我爱天津--电子商务网 | http://www.52tj.com/
万网/迈至科 | http://www.net.cn - http://www.magicw3.com.cn/
 | 提供JSP支持
海威 | http://www.bestdns.net
 | 提供JSP支持
火速 | http://www.hotsales.net
热吧网络 | http://www.hot8.org/index.html
 | 提供JSP支持
东方通信域名注册中心 | http://reg.eastcom.com/index.htm
网络神 |
东方网景 | http://www.east.net.cn
中国频道 | http://www.china-channel.com/
飞华信通 | http://www.flink.cn.net/
网宿 | http://www.chinanetcenter.com/cn/index_ch.htm
网晖 | http://www.chinanetsources.com
7135 | http://www.7135.com
盈科 | http://www.1stchina.net/
天阙 |
中国亿网 |
国外
WebAppShowcase | http://www.webappcabaret.com


时力信息技术服务内容
电子商务咨询
为企业决策人提供电子商务实施的步骤，相关技术，费用，时间安排等的咨询。

这是企业在采用信息技术之前应该做的第一步，以了解将来需要做什么，怎么做，费用等

网站策划与设计
  • 域名注册，
  • 主机租用：
  • 网站策划，网站研究与分析：针对某一个行业的相关网站的研究与分析，以决定采用什么风格，内容编排，技术的应用等
  • 培训：针对公司相关员工的培训，使他们知道如何维护网站并在整个设计过程中恰当的配合
  • 内容编辑：
    • 首页设计，包括公司标记(logo),
    • 多媒体技术的采用，
    • 导航结构，
    • 背景，颜色，字体，图像，
    • 数据库的选择等。
  • HTML 编辑和称序设计, Java, Java Script, PERL, PHP, XML, ...
  • 图象设计: logo 设计,数字影像等
  • 文字与网站翻译：
    • 将您的网站 翻译 成英文或其他语言；或者相反

数据库开发和分布式数据集成与交换
  • 开发在线或/和离线数据库，为贵公司组织，商业伙伴，客户，供应商，贸易伙伴，以及公司员工的数据共享构建数据服务环境，包括您的B2B，B2C网站
  • 分布式数据处理
  • 数据转换
网站功能模块的开发

购物车，留言本，注册，在线论坛等

网站维护

  • 上载，下载或修改文件，图象
  • 维护数据库
  • 保证网站畅通，浏览速度快捷
  • 数据备份
  • 提供网站访问分析，客户分析，产品分析等
网络安全设置
如何保证发送与接受电子邮件安全？如何保证网站与用户的关键通讯得到保密？
WAP（Wireless Application Provider)内容设计

WAP是移动终端（手机，笔记本，手持电脑等设备）在互联网上的信息与数字传输协议。与HTML类似，WML是用来编写WAP页面，而 WMLScript与JavaScript/VBScript类似的编写动态WAP应用的脚本语言。。。

网站推广与网络营销

网站建设不等于万事大吉。如果没有恰当的推广与宣传，最好的网站都会默默无闻，少有访问者。我们将告诉您如何增加网站的知名度，和经济效益。
网络多媒体开发

多媒体增加使得原本死气沉沉的网站顿时多姿多彩。目前网站的多媒体技术呈现出五彩缤纷，有动态图像-例如GIF， 有FLASH动画，而近来则网络实时音乐和影像(Audio/Video}让人们足不出户，欣赏到美妙的乐曲和电影。另外一个行业应用是三维虚拟现实图像技术，它使观众亲身体验现实世界的物品，人物和自然界。
网络通讯服务

Internet使通讯方式发生了根本的变化，网络电话，网络传真，电子邮件，网上寻呼，聊天，以及与传统通讯工具和技术的结合，真让人眼花缭乱。。。
综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
<


e-business consultation

Solar Software
Windpower Software
Online Calculation

e-business consultation

Instruct corporation leaders on steps, relevant technologies, cost, time table and more about his/her e-business strategies:

  • introduction;
  • purpose of your website and your competitors;
  • structure & content;
  • implementation plan;
  • cost;staff and technologies;
  • timetable;
  • etc...

website configuration, planning, incl.:
  • domain registration
  • hosting
  • site architecture;
  • orientation (introductory, e-biz like, database-driven or Extranet/Intranet)

website research

study and analysis of websites in a certain industry

web content editing and design
  • front page design, incl. logo, multimedia tools, navigation structure, background, color, font, images, databases etc
  • HTML authoring, Java, Java Script, PERL, PHP, XML...
  • image design: logo, digital photography .

WAP -Wireless Application Protocol

WAP(WML/ WMLScript) ..

multilingual website design

 DETAILS>>>

translate your existing website to another languages - not just simple text translation. If your website involves databases, pictures, animations and audio/video, it's going to be very complicated

web functions customization / web programming

 DETAILS>>>

Website management/functions
 | --site advertisement system
 | --webmaster tools
 | --BBS/chatroom
 | --enterprise email system
 | -mailing list
 | --feedback system
 | --page publish system
 | --product publication and query system
 | --online poll systems
 | --website search functions
 | --online support systems
 | --news publishing system
Online business
 | --purchase
 | --supermarket/shopping mall/sales system/shops
 | --direct sales system/distribution system
 | --value added services
 | --payment

multimedia/VRML

DETAILS>>>
  • Flash and animation
  • stream audio/video
  • virtual reality scenes,simulating real world
Internet communications solutions

What are Internet communications in our case ? We are talking about communications tools integrated into your websites - not those stand-alone application software for telephone, fax and relay chatting.

Mutlmedia email

A website integrated mulmedia system enables your visitors to send to you or receive from email or documents with voice, music, video and animation. Thus give them more experiences of your company and the needs of your potential clients.

Website telephone

Image your client click on a link in your website which directly calls your servicemen ? With web telephony technologies this is possible now at very low prices.
Website faxing

The same as with telephone. You may also send and receive your faxes via your websites with emails at a cost of only a fraction of normal fax.

Chatting & call

These technologies are widely used. In addition, voice and image chatting are becoming a fashion. Check with us for your requirement ? Also Internet mesaging with your mobile and call devices are available for your websites.

website maintenance & promotion
  • collection and analysis of your material for maintenance door to door;
  • uploading, downloading files, images,
  • make sure your server is working well,
  • maintain your databases servers
  • making regular website visit report
  • analyse your visitor behaviors
  • speed up your communication with your client
  • understand your online sales statistics
  • design promotion banners;banner exchange; sitemarketing;
  • mailling list maintenance;
  • register to search engines - manually;
  • code preparation for backup purpose;
  • artistic design and structural planning for website upgrading & expansion;
  • training of your IT personnel for website maintenance;
  • and more

security issues
configure your secure email client, help you send and receive secure mails; set up your SSL web servers, think about your expensive data stored on your hosts ...

database development and distributed data exchange

 DETAILS>>>
  • database development,
  • distributed data exchange,
  • data format transformation

Design flow

Undestanding clients and their wishes
Please take some time to fill out this ONLINE APPLICATION FORM or call us to say what you want. We will possibly give you some ideas how your wishes can be satisfied by our services.

Let's talk about your fundamental needs: theme and tune of the website, basic functions and content blocks, compatibility with different browsers and screen resolution etc. Things like this must be determined before diving deep into the well !!!

Preparing for materials
You and me should work together to prapare for materials needed for website design - what to include and how they shal look like. We don't simply say hi, give me that and that and I make a website for you. We work together, from the beginning to the end.
Preliminary design
Now with materails on hand, we can discuss about details: the sturcture of the site, the technologies to achieve your functions and the first page of your website. You can choose your self how the first page and the whole site shall look like.
Domain name
If you have none, please rush for registering one.
Siging a contract

Although we're a private studio, not yet registered in the government, we still need to sign a paper with you. Within the contract, we fix thing like:

  • layout of the website
  • website structure
  • color for fonts, background; font style and sizes
  • pictures
  • dynamic functions and interactivity
  • other functions
  • prices and payment
  • disputes and solution
  • etc, etc

With this contract, you have to pay something - normally 30% of the contract value - depending on the value of the contract.
Review
roughly a week after signing a contract, we will finish the design of the first pages and several main pages for your review. Please carefully study these pages. Any changes to them will place significant burden on redesign of the whole site !!!
Design of the whole site
Now we will concentrate on the design of the rest of work - don't disturb us during that time - extreme concentration is needed for a web design, especially when programming is included. We will contact you when we need your help.
Complete !
Complete ! -- this is most probably the best word among the programmer's world. Each time you see this world after compiling a program, you feel relaxed and this is exactly the best time of the day - probably the years to a true programmer. And now it's you and me who will enjoy together for our successful cooperation. Let's go ahead.
Confirmation
We need your confirmation whether it's really complete. And don't forget to pay the last money to us within some fixed days - let's say a week after you witness the completion of the project
Maintenance
Of couse, we don't want to do an one-time business, if you trust us you can aks us to maintain your website - incl. modifications and redesign. We shall sit down and talk indepth.

Statement of Rules

Specifications
Pages are made according to HTML 4.0 published by W3C, default size:800X600 pixels,16 BIT COLOR. For any special needs, please advise us in advance.
Browser
Default browser is IE4.0.
Link to Solaires.com
Client's website will have a logo or text link to SOLAIRES.COM.
Copyright

Solaires is authorized to put identification marks of solaires.com; Products/software/applications belong to Solaires.com before full payment, after payment, the copyright will be transferred to the client. Client shall not publish the codes/products without permission of solaires.com.
Forms of materials
To shorten the time period of designing, clients shall endevour to provide electronic documents in .txt or .doc formats. Pictures shall be available in forms of high resolution TIF or CDR format. If client has a CIS manual, please tell us if you want to design your website according to this CIS manual.
Content of materials
If contents of client materials cause negative enfluence, it has nothing to do with Solaires.com.
Home page
Client shall submit a picture representive of company image. If ther's no such picture available, we can design one for you if you ask us to do so.Cost shall be calculated separetely.
Website maintenance
Maintenance fee shall be negotiated during or after design period.
Note: modifications to web pages without changing the wole structure and functions cost about 300 RMB/month for small website (<15 pages) or 50 RMB for each modification. For big websites we need to discuss about details.


网站设计-网站维护

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网站设计-网站维护

网站的制作和发布仅仅是实现网站功能的第一步，大量的工作是在网站的后续维护上，在行情和信息处于瞬息万变的今天，无法想象一个长时间得不到更新的网站怎能使访客有新颖感，而增加其吸引力？因此,网站的维护和更新是网站生命力的体现。

内容维护
  • 上载，下载或修改文件，图象
  • 维护数据库
  • 保证网站畅通，浏览速度快捷
  • 数据备份
网站统计分析与评估
  • 提供网站访问分析，客户分析，产品分析等
  • 网站技术层面分析-浏览速度，美观，兼容性等
网站维护>>>网站统计分析与评估软件
软件名称 | FastStats 2.73
运行平台 | Win95/98/NT
大小 | 1185K
简要描述 | 通过分析站点的日志，然后产生报表，图表和报告的日志分析软件。据 TUCOWS 测试，它分析一个 5MB 大小的日志文件只需 21 秒钟。
详细介绍 | http://www.mach5.com/fast/
下载 | ftp://ftp02.softhouse.com.cn/download2/8969fs273.exe

软件名称 | FileCombiner 1.0 beta
运行平台 | win95/98/nt
大小 | 12K
简要描述 | 免费软件.非常好的webserver日志记录软件。您可以用它查询每月甚至每年得到的站点的统计资料。而且这款程序无需其它计算机系统或外设。
详细介绍 | http://users.penn.com/~dgerg
下载 | ftp://ftp02.softhouse.com.cn/download2/ 19705filecombiner10beta.zip

软件名称 | Happy Log 1.0
运行平台 | Win95/98/NT/2000
大小 | 1457K
简要描述 | 共享软件.Happy Log 是一款网站日志文件分析软件.它可以生成图表、HTML、word和EXCEL文件格式的报告。你可以统计，如：点击数、访问人数、浏览器类型等数据。
详细介绍 | http://www.axolot.com/loganalyzer/index.htm
下载 | ftp://ftp03.softhouse.com.cn/download1/40874hlsetup.exe

软件名称 | LogFile Analyzer 1.1.400
运行平台 | Win95/98/NT
大小 | 3827K
简要描述 | 共享软件.Serv-U FTP服务器2.1以上版的Log文件分析工具。能找出所有的登录记录，有各种过滤功能，能分离出DELE、SITE和MDTM等命令，还可以分离出某一用户或某一IP的登录。
详细介绍 | http://www.abc.se/~m9652/bs/products/log.html
下载 | ftp://ftp02.softhouse.com.cn/download2/19809LogFile11a400.zip

软件名称 | Sawmill V6.0.9
运行平台 | Win95/98
大小 | 3132K
简要描述 | 免费软件.Sawmill透过分析Log File的方式来提供网站的访客流量数据。让你知道网友的停留时间、浏览网页等的喜好分析，下次你改版的时候才能清楚把握方向。
详细介绍 |
下载 | ftp://ftp03.softhouse.com.cn/download3/ 56156sawmill6.0.9_x86_win32.exe

软件名称 | SiteSpeed 1.0
运行平台 | Win95/98/NT
大小 | 499K
简要描述 | 试用软件.可以通过多次自动访问您指定的网站，来获取相关访问速度的报告。
详细介绍 | http://thedigitaldetective.com/SiteSpeed/default.htm
下载 | ftp://ftp02.softhouse.com.cn/download1/16936SetupSiteSpeed.EXE

软件名称 | SurfStats 6.005
运行平台 | Win95/98/NT
大小 | 7108K
简要描述 | 共享软件. 分析日志文件和生成网站活动记录，能从主机上取回你的日志文件，有详细报告或摘要，还支持动态DNS查找等。
详细介绍 | http://www.surfstats.com/
下载 | ftp://ftp03.softhouse.com.cn/download2/47472sstats.zip

软件名称 | WebSuxess - Log File Analyzer 3.0
运行平台 |
大小 | 2942K
简要描述 | 免费软件.这个软件可以自动对服务器中的Log文件进行分析，然后向你提交一份非常详细的网站访问报告
详细介绍 |
下载 | ftp://ftp.softhouse.com.cn/download2/5325websuccess.exe

软件名称 | WebTrends Log Analyzer V6.0c
运行平台 | Windows 95/98/NT
大小 | 10658K
简要描述 | 免费软件.一个非常强大的网站服务器端纪录文件分析工具，它能自动实时分析纪录，并提交标准 HTML 格式的报告，也可以通过 E-maiL 把报告发给你的用户。
详细介绍 | http://www.webtrends.com/site_download/default.htm
下载 | ftp://ftp03.softhouse.com.cn/download3/52338wtltrial.exe

软件名称 | WebWatch 2.0
运行平台 | WinNT/2000
大小 | 1176K
简要描述 | 共享软件. WebWatch 可以检测到个人主页的变化情况，哪怕是微小的变化，它也能检测到。只要将站点添加到 WebWatch 然后点击 Run 就可以了。
详细介绍 | http://www.softlocx.com/
下载 | ftp://ftp03.softhouse.com.cn/download2/47305WebWatchV1.exe

软件名称 | 网页访问人数曲线图 1.2
运行平台 | Win95/98/NT
大小 | 16K
简要描述 | 免费软件.改进了日期计算，同时加入了日平均人数的统计。需VB6.0运行库的支持
详细介绍 | http://personal.hb.cninfo.net/~hqse
下载 | ftp://ftp.softhouse.com.cn/download3/14439andpic.zip
< < < < < <


website maintenance

  • uploading, downloading files, images,
  • maintain your databases servers
  • making regular website visit report
  • analyse your visitor behaviors
  • understand your online sales statistics
  • make sure your server is working well,
  • speed up your communication between your client
  • and more
Site maintenance & management software

< < < < < <


multimedia/VRML
  • Flash and animation
  • stream audio/video
  • virtual reality scenes,simulating real world


网络数据库-其他

网络数据库
其他
国内

DBFT数据通

数据通dbft http://dbft.top263.net/ - 通用数据库管理工具

JBase

JBase 数据库系统 - JBase 数据库系统，纯 Java 编写，标准 SQL 语法，标准 JDBC 接口.

HYSQL

华易软件有限公司 -http://www.huayisoft.com/ 华易网络数据库HYSQL。

EasyWeb

东方新宏科技发展有限公司 - http://www.xinhong.net/ EasyWeb数据库

DfDraw 双狐数据图形软件 DfTask 双狐数据库集成软件

双狐数据库集成应用软件 - http://www.doublefox.com/prod02.htm 融合数据库、图形、地理信息系统、数据处理为一体的软件

DIPS

北京新星快威数码技术有限公司 - http://www.info-quick.com.cn/ 以图文库技术为核心、让用户在互联网上建立数字文献全文数据库检索系统的通用开发平台--数字文献处理系统（DIPS) 。

Visual DBTOOLS

上海讯光科技系统有限公司 - http://www.infolight.com.cn/ - 数据库开发工具--Visual DBTOOLS

DBTools-至嘉通用信息管理系统 2.1专业版共

http://dbtools.myrice.com

易表2000

http://www.egrid2000.com/

DBMaker

http://www.dbmaker.com.tw/DBMaker 最佳中文資料庫管理系統
專屬 DBMaker 的產品單元，在其中為您介紹所有和 DBMaker 相關的資訊．包括特色功能．對產品的疑難排解．和各種相關的資訊詳盡的呈現其中，讓您能對DBMaker有更進一步的了解．歡迎進入DBMaker 的世界。

Visual dBASE

http://www.sinter.com.tw/vbc.htm

瑞软全文及多媒体资料管理系统

http://www.readsoft.com.cn
通用SQL数据查询系统

http://www.coinfosoft.com

Data Anywhere

Data Bridge

JOX
国外

Delphi

http://www.sybase.com

VisualFoxpro

http://www.microsoft.com

Pervasive.SQL

北京亿达公司 - http://www.yida.com.cn/ PervasiveSQL数据库、Tango

Jasmine

http://www.ca.com

mSQL
    • http://www.hughes.com.au/
    • http://ftp.cdut.edu.cn/pub2/linux/system/database/msql/faq.html The mSQL FAQ

postgreSQL

http://www.pgsql.com.tw/

Access

http://www.microsoft.com

InterBase

    • http://www.borland.com/interbase/
    • http://www.3asoft.com/龙豪软件工作室

InstantDB

SAPDb

Solid

hsql db (Hypersonic)

Cloudscape

velocis

filepro

iODBC

Adabas

dBase

FrontBase

Empress

Unix dbm

Ingres
CloudScape


Web databases-Others

Web databases
Others
China

DBFT

dbft http://dbft.top263.net/

JBase

HYSQL

http://www.huayisoft.com/

EasyWeb

http://www.xinhong.net/

DfDraw, DfTask

http://www.doublefox.com/prod02.htm

DIPS

http://www.info-quick.com.cn/

Visual DBTOOLS

http://www.infolight.com.cn

DBTools

http://dbtools.myrice.com

EGrid?000

http://www.egrid2000.com/

DBMaker

http://www.dbmaker.com.tw/

Visual dBASE

http://www.sinter.com.tw/vbc.htm

RedSoft

http://www.readsoft.com.cn
GenSQL

http://www.coinfosoft.com

Data Anywhere

Data Bridge

JOX
International

Delphi

http://www.sybase.com

VisualFoxpro

http://www.microsoft.com

Pervasive.SQL

http://www.yida.com.cn/

Jasmine

http://www.ca.com

mSQL
  • http://www.hughes.com.au/
  • http://ftp.cdut.edu.cn/pub2/linux/system/database/msql/faq.html The mSQL FAQ

postgreSQL

http://www.pgsql.com.tw/

Access

http://www.microsoft.com

InterBase

    • http://www.borland.com/interbase/
    • http://www.3asoft.com

InstantDB

SAPDb

Solid

hsql db (Hypersonic)

Cloudscape

velocis

filepro

iODBC

Adabas

dBase

FrontBase

Empress

Unix dbm

Ingres


Plan your site
Your objectives

Before working with your design company, decide for the purpose of your website. At this stage, you don't need to think about the fonts or colors of your web contents, rather your choice of types of website. Regardless whether you're considering designing a new site or updating the existing one, your budget and timetable can only be fixed after you have decided for your objective of your Internet company.

If you're still unclear of your destination, the table below may help you make decision:

type of website | purposes | features
introductory site | clients worldwide can learn about your company | · some picture（LOGO & photos片） · company introduction · e-mail or guestbook
e-biz site | clients worldwide can buy your products from your website | in addition to above, plus: ·shopping cart ·online payment system ·secure transmission
database driven site | allow clients maintain their account info, search for documents of your products or learn more about your products sold off-line | additional functions: · client support database · search tools
Extranet | you may use your site to share sensitive data with your client and supplier securely | in addition to the datadriven site provide following functions: · visit permission by password verification · data security

Your competitors

To help website design companies know your requirement, one option is to provide a list of websites of your competitors. You must tell your designers what you like and dislike. Design companies use your information to configure your own site, with a clear definition of characteristic of your site, and estimate the size of your site.

The Best

You shall stick your eyes to a few of your competitors. Tell your designer which sites do you like or dislike the most. To let your designer know your likelihood of style can help your designer make a final product catering for the image of your company and the interest of your clients.

Planing

including but not limited to the following:

1.design of the from page, logo, menus and layout

2.Site structure: navigation, structure and directory

3.decide for technologies of the site

4.Decide for site content

5. Finally, background, fonts, color, etc
close


网络编程

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网络编程

时力为客户的交互，动态的电子商务网站构建数据库驱动的网络应用，采用当今最新的技术，根据拥护需要从以下技术中进行选择：

  • CGI (perl,shell),
  • php,
  • c,c++,
  • VBScript,
  • JavaScript,
  • ActiveX,
  • ASP,
  • JSP/Servlet,
  • EJB/CORBA,
  • 中间件，
  • 应用服务模块，
  • XML/XSLT/Schema/Namespace,
  • WAP/WML/WMLScript,
  • VRML
  • 3D
  • ...

等构建在 Internet/TCP IP 上的应用编程。


Web programming

Our services | JAVA | XML | Tips

Solaires provides clients' websites with interactive, database-driven programming using the state-of-the-art technologies, like:

            • CGI (perl,shell),
            • php,
            • c,c++,
            • VBScript,
            • JavaScript,
            • ActiveX,
            • ASP,
            • JSP/Servlet,
            • EJB/CORBA,
            • middlewar,
            • XML/XSLT/Schema/Namespace,
            • WAP/WML/WMLScript,
            • VRML
            • 3D
            • ...


website study & market research
Purpose

There's no differences between setting up a website and founding a company - for profit. And website owner is expecting to earn money much quicker and I much great scale.
Products/services

Before making any study, you need to decide which products/services will you provide to whom.
Market

The market status in reality - if you plan to deliver pizzas to middle school students in your community, you need to know who are providing this service and to which degree. And look at their websites.
Competition

We don't miss people with great ideas in this world, and many have big money in their pockets, but do you know who they are and what they have done so far from their websites:

  • technologies they use
  • website content
  • how their artistic look like, any multimedia used ?
  • which e-functions are applied ?
  • how to cash in and how much ?
  • who pour the money ?
  • a publicly listed company in the stock market ?
  • about the visitors
  • who visit their sites ?
  • who manage and run the site ?
  • ...
Advantages

Compared with the above folks, what advantages do you have over them ? More money ? With Harvard MBA ? Experiences in the Wall Street ? Or you have run a bankrupt company in Silicon Valley ? But remember, you're now in China, and things are upside down with the rest of the world.Forget your past and face the reality and prepare for failure.
Disadvantages

Good or bad, your social resources determine your success or failure. You have been in the US so long, but how many Chinese do you know. Just think how slow things go here, then you know books you perused in Harvard are just useless. Guanxi, Guanxi and Guanxi !
Management

Hard to tell which is the best management system, depends solely on personal style of the company and the size of the company. Opportunist is the only trick I would recommend.
Human resources

Use first class engineers.
Business & social atmosphere

Your business plan shall be compatible with technologies available and general business trends. If you invested 50 million RMB 5 years before for a B2B website, you must be bankrupt today.

Investment

How much money do you want to pour into your website ? how much money comes from your own purse ? how much money you want to borrow ? from whom ? under which conditions ? how you plan to pay back your borrowings ? how do you plan to spend your investment ? etc
Return

What kinds of returns investors will have ? Are they reliable ? where does your income come from ? advertisement ? business commission ? website service ? can you list your company to famous stock market like NASDAQ ?
Short turn forecast

invest and income prediction within half an year
Midterm forecast

invest and income prediction within 3 years
Long-term forecast

invest and income prediction within 5 years
close

<


网站设计-网络安全设置

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网站设计-网络安全设置
安全浏览 (Microsoft Internet Explorer)

1)申请一个数字证书

您可以到 CA (Certification Authorities) 的网站为您的电子邮件申请一个证书。详情请参考 "如何申请数字证书"一节的内容。

2)指示您的安全服务器安装您的数字证书

3)与服务器建立安全的连接(以https://www.secureweb.com/..方式.). 安全服务器的数字证书会自动地安装到您的浏览器中。

4)每次当您与安全服务器建立连接，系统会自动识别双方的数字证书
安全电子邮件 (Microsoft Outlook Express)

1)首先申请一个电子数字证书
您可以到 CA (Certification Authorities) 的网站为您的电子邮件申请一个证书。详情请参考 "如何申请数字证书"一节的内容。
2)将您的数字证书安装到您的电子邮件帐号
有二种方法安装您的数字证书：
  • 给其他人发送带数字签名的电子邮件:

    在发送电子邮件以前，单击工具栏上的“数字签名”图标，这样，当您发送邮件时，您的数字证书就自动导入您的邮件帐号中。

  • 手工添加数字证书:

    打开您的地址簿，选择您的邮件地址，双击以打开它；然后单击“数字标识”页，单击“引入”按钮，选择合适的证书文件（带有 p7c, p7b, cer后缀) 然后再单击“打开”。

3) 取得对方的数字证书
有三种途径可以取得对方的数字证书:
    • 当收取对方加密签名的邮件时，自动地获得对方的数字证书

    在激活此功能前，您必须进行设置。步骤如下： 工具->选项->安全->高级->数字签名电子邮件->将发送人的电子邮件加入我的地址簿->OK.

    • 引入发件人的数字标识文件

    双击地址簿种发件人的电子邮件地址->选择 "数字证书"->单击 "导入"->选择一个数字标识文件->选择 "打开"->OK.

    • 从CA网站下载一个数字证书，具体步骤参考有关的操作程序。

4)撰写和发送安全的电子邮件
有二种发送安全电子邮件的方式：
    • 手工方式：

    编写邮件->单击工具栏上的“签名”或/和“加密” 按钮->OK.

    • 自动方式

    按以下的步骤操作：选择 "工具"->"选项"->"安全"->然后选择 "加密邮件内容和附件“ 和/或 "在所有邮件中添加数字签名"
5)成功 !
以上设置完成后，您就可以象使用一般电子邮件一样发送和接受安全的电子邮件了。但是，什么是数字证书呢 ?
服务器安全 (IIS 5.0)
如果您的服务器上有敏感的数据，例如银行数据，价格等 - 您显然不想让这些数据成为公开化，您就需要设置您的服务器，使得它的通讯机制安全可靠。此处我们向您介绍一个方法，采用数字证书。我们将指导您如何设置您的 Microsoft Internet Information Server 5.0 使它能进行安全数据通讯。其他服务器的设置请参考相关的操作手册。

-取得和安装来自可信任的认证机构（CA）的数字证书. 您可以在 IIS MMC 中操作或直接到CA网站下载.

如果您在 IIS MMC案中操作, 请依照下面的步骤:

选取网站根目录或文件夹/文件->单击“属性”工具栏->选择目录/文件安全->安全通讯->选择服务器证书，按照提示从CA申请一个证书并安装在服务器上

-设置 SSL 加密和安全锻口

按照以下步骤:

设置SSL加密: 选取网站根目录或文件夹/文件->单击“属性”工具栏->选择目录/文件安全->安全通讯->编辑->安全通讯->选择 "需要 SSL 加密" 或"需要128位加密"

设置端口:选取网站根目录或文件夹/文件->单击“属性”工具栏->网站->网站标识->高级->高级多网址配置->本网站的多SSL证书->确认端口为443->(可选) 增加(添加更多SSL端口）

-将用户证书与用户帐号建立映射

首先导入一个用户帐号，然后按照下面步骤操作：

设置接受用户证书:选取网站根目录或文件夹/文件->单击“属性”工具栏->选择目录/文件安全->安全通讯->编辑->安全通讯->选择 "需要 SSL 加密"，在 "用户证书“项下从以下三种选项中任选一种：接受用户证书，需要用户证书，ignore client certificate

映射用户证书至Windows用户帐号:选取网站根目录或文件夹/文件->单击“属性”工具栏->选择目录/文件安全->安全通讯->编辑->安全通讯->选择"开始用户证书映射"->编辑->帐号映射->选择 "一对一"->添加新证书->定位证书文件->映射到帐号->输入一个映社名->输入您的Windows用户帐号和密码->OK
关于数字证书

正如所有其他证书，数字证书是您的身份，您的所有物 - 电子邮件号码，服务器，公司，互联网连接设备 - 等的证明。

除此以外，数字证书配合电子邮件和浏览工具的客户端可以用来在您发送信息前加密您的信息。所以，数字证书有二个功能：加密和签署您的信息。加密的作用是保证没有其他的人可以解码和了解您的信息，而签字可以保证信息是有签字者发送的。因为证书是由权威的机构发放的，我们应该有足够的信心。
如何为您的电子邮件或个人取得数字证书？
数字证书可以通过官方的认证机构- 例如 verisign.com. Microsoft 维护了一个CA的清单, 请参考
Microsoft Internet Explorer 数字证书站点.
在中国上海，有一个政府CA网站, SHECA, 处理所有证书申请和其他因特网相关的业务。可以到那里去申请一个证书。

个人可以申请二种不同的证书：电子邮件证书和个人身份证书。前者用来安全的电子邮件通讯而后者是用来当您浏览安全站点(以https://标识 )使识别您的身份的。
关闭窗户


Internet security
Secure browsing (Microsoft Internet Explorer)

1)apply for a digital certificate for yourself

you may go to CA (Certification Authorities) website for applying for a certificate for your email address. Details see explanations under "how to get digital certificate".

2)instruct your secure webserver to install your digital certificate

3)establish secure connection with secure server (https://www.secureweb.com/...). The digital certificate of the secure web server will be automatically installed into your system.

4)each time you connect to the same secure web server, their systems will automatically recognize each other's digital certificates.
Secure email (Microsoft Outlook Express)

1)apply for a digital certificate

you may go to CA (Certification Authorities) website for applying for a certificate for your email address. Details see explanations under "how to get digital certificate".
2)add your digital certificate into your email account number
Once you have your email certificate from a CA, you can add your digital certificate to your emain account in one of the two ways:
  • send an email to someone with digital signature:

    before sending your email, click the "digital signing" button on the toolbar, and your digital certificate will be automatically added to your email account

  • add your digital certificate manually:

    open your address book, select your own email address, double-click it and turn to "digital identity" page of the panel and click the "import" button, select an appropriate digital identity file ( with extension of p7c, p7b, cer) and click "open".

3) get the digital certificates of the persons with whom you communicate securely

There are 3 ways to get the digital certificates of the email account of your communication partners:
    • automatically add the digital certificates of the senders by receiving their emails with digital signature/encryption.

    But before that works, you must set your email client to work properly. Follow the steps: Tools->Options->Security->Advanced->Emails with digital signature->Add the digital certificates of the sender to my address book->OK.

    • import a digital identity file of your sender

    double-click the email name of the sender in your address book->select "digital certificate"->choose and click "import"->select a digital identity file->select "open"->OK.

    • download the digital certificate of the sender from a CA website:

    do according to instructions there.

4)write and send your secure email

Two ways to send a secure email: manual or automatic
    • manually signing and/or encrypt your email:

    draft you email->click the "signing" and/or "encrypting" button of the toolbar->OK.

    • automatic

    follow the steps here: "tools"->"options"->"security"->then:

    select "encrypt all contents and attachment of emails for sending" and/or "add digital signature to all emails to be sent"
5)ready !
After all these settings are well done, you can send and receive secure emails just like you send and receive normal email. But what about digital certificate ?
web server security (IIS 5.0)
When your server has sensitive information (bank data, account info, prices ...) and you don't want them to be made public, you need to configure your web server under secure communications. Here we introduce one method - using digital identity. We show you how to set up your server on Microsoft Internet Information Server 5.0. Measures for other servers please check with your server manual.

-get and install a digital certificate ID from a trusted Certification Authority (CA). You can either do this within the IIS MMC or go directly to CA's website.

When you do this within IIS MMC, please follow the steps below:

select a website directory or file->properties tab->directory/file security->secure communications->then choose:server certificate and follow the instructions to request a certificate from CA and install it on the spot.

-configure SSL encryption & secure port 443

Follow these steps:

to configure SSL connection: select a website directory or file->properties->directory/file security->secure communications->edit->secure communications->check "require SSL" or "require 128 bit encryption"

to configure port:select a website directory or file->properties->website->website identification->advanced->advanced multiwebsite configuration->multi-SSL certificate of this website->make sure the port is 443->(optional) ad (to add more SSL ports

-map client certificate to user account

first import a client account

the follow these steps:

configure to accept client certificate:select a website directory->properties->directory security->secure communications->edit->secure communications->check "require SSL" and under "client certificate check one of the three options: accept client certificate, require client certificate, ignore client certificate

map
                              the client certificates to Windows client account:select
                              a website directory->properties->directory
                              security->secure communications->edit->secure
                              communications->check "start client certificate
                              mapping"->edit->account mapping->check
                              "one to one"->add new certificate->locate
                              certificate file->map to account->type a mapping
                              name->type Windows client account and password-OK
About digital certificate

Like any other certificate, a digital certificate is a prove of your identity, identities of your belongings - email address, server, company, Internet access devices etc.

Additionally, a digital certificate can be used together with a email or browser client or encrypt your information before going to the Internet. Therefore, there are two basic functions of a digital certificate: encryption and signing your message. Encryption ensures no one else can decode and understand the content of your message, and signing guarantees that the massage is sent by the person of the holder of the certificate. Because the digital certificates are issued by authoritative organizations, we shall have enough confidence of their authenticity.
How to get your digital certificate for emails or for your private identity
Digital certificates can be applied through official certification authorities - such as verisign.com. Microsoft maintains a list of these CAs, see
Microsoft Internet Explorer digital certificate website for more details.
Here in Shanghai, China, there is a governmental CA website, SHECA, handling digital certificate application and other security-over-the-Internet related business. Go there to apply for one.

Two different certificates are available for private persons: email certificate and personal identity certificate. The former is used for email communications while the later is used to identify yourself when you browse a secure website (https:// or shttp://). Make sure you're using the right services.
close


网站设计>>>建站与发布管理工具

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语
网站设计>>>建站与发布管理工具
"999企业门户”、“999网站大师”
http://www.999asp.com/

“999企业门户”、“999网站大师”是一套旨在提高企业信息化和网站建设和管理水平、降低企业信息化建设总体成本的应用软件，客户可以无须软件开发，快速建成符合特定需求和用户界面的复杂网站和企业信息门户。实践证明，采用“999企业门户”、“999网站大师”可以减少90%的企业信息门户和网站建设和管理成本。

适用对象：
1．企业信息化：可以构建企业的信息平台、知识平台、应用平台，包括内部OA系统和外部的电子商务平台。
2．集团公司：用于总公司和下属机构开发同类复杂程度的独立网站和企业信息门户，不需另加投资。
3．政府上网：可以降低政府上网的门槛，加快政府的信息化进程。
4．区域互联网服务提供商、网页设计公司、专业服务网站。
国信贝斯
http://www.ibase.com.cn:85/

-SchoolSite校园网信息发布系统

-能够帮助中小学学校快速建立校园门户站点,使中小学学校从传统教学管理模式转变为以Web为战略中心,充分发挥Internet或Intranet的优化教学信息流通环节的功能,实现真正的数字化校园.
-iPAC图书馆网上信息资源发布和检索系统

-对于网络时代的图书馆来说，如何利用信息技术建立数字图书馆，使自己成为未来社会的公共信息中心和枢纽，更好地为社会和读者提供个性化的信息服务.
-CEP城市企业门户网站系统

-提供了一个企业进行网上信息发布的舞台，企业可以通过所在城市的企业门户网站将自己的企业形象、经营情况、企业资信、产品资料等进行网上宣传，通过低廉的投资，获取面向全国的宣传效果通过网络寻求合作伙伴和市场商机、招标平台、电子商务应用的环境和机会.

-iBASE 搜索引擎

-基于iBASE 非结构化全文检索内核技术，集成了包括简单检索、字段检索、二次检索和全文检索等多种检索方式，海量信息，秒级响应，奠定了企业知识管理的基础...
<


web content translation
solaires provides website content translation services for the following clients:
  • foreign companies/individuals who want to publish their content to a website in China, therefore need a Chinese language version of their websites in addition to their website of their own languages - English, French, German ...;
  • Foreign companies/individuals who don't have their websites in their own language but are interested in building a Chinese website to meet the needs of Chinese customers;
  • Foreign companies/individuals who already have their websites in Chinese but the Chinese content cannot reflect the souls and ideas of their original web contents of ideas of the web owners, therefore modifications are necessary to exact reflect the true mission of your companies and yourself;
  • Chinese companies/individuals who have or have not a website but need a foreign language version - English, French, German ...;
  • Chinese companies/individuals who already have a foreign language version of website but need either modifications/updating/upgrading/extension of their website's foreign language part, because either the previous translation is poor or information need updated/added
Web content translation does not simply translate the text from one language to another, it also includes the following aspects of modifications:
  • pictures/animation/audio/video: most of the pictures and other multimedia need to be redesigned, removing the Chinese or foreign characters or replace them with foreign or Chinese texts;
  • Databases: if the website is interactive - that is, information can be retrieved by interacting with a database server - then you need to do two jobs:
    • modify your database - incl. all database tables, views, diagrams, stored procedures ... if there's any, and replace all records with foreign languages/Chinese;
    • modify your program pieces in your web pages - perl, php, cgi, ASP, JSP, CFML etc
Summery
As discussed above, web content translation is not a normal sense of translation - it combines with web technologies and involves lots of site knowledge, if you have a complicated system. For static website without programming, most of translation work is for text translation plus some transfer of images when there are characters on web images, otherwise you don't need to change anything.
Prices
  • Plain (static texts) translation:
    • English -> Chinese: 300RMB/1000 English words
    • Chinese -> English: 400RMB/1000 Chinese characters
    • Other languages + (30-80%) depending on that language and the field of the information.
  • Prices for images and database conversion can only be discusses face to face.
close


网站设计-网站功能和因特网技术应用

综述
电商咨询
策划与主机
内容制作
功能设计
无线上网
网络安全
网站维护
网站推广
 建站工具
业务
MySQL
DB2
Informix
IBase
Kingbase
OpenBase
Oracle
DM3
PandalSQL
SQLServer
Lotus
Sybase
Others
Java
XML
IDE
应用服务
慨述
三维立体与虚拟现实
实时视频
DEMO
综述
网站多媒体电邮系统
网站传真
网站电话
网站聊天
在线呼叫与短信息
综合服务
演示
业务介绍
报道
行业网站
太阳能软件
风力发电软件
在线计算
注册登录
设计申请
研究申请
工作流程
网站合同
售后服务
价格
项目
招聘
常见问题
本站新闻
申明
术语

网站设计-网站功能和因特网技术应用

除了普通的网站/网页设计与电子商务解决方案服务以外，时力公司为您定做各种网站功能。我们也帮助您了解和应用最新的因特网技术，以帮助您改进企业工作流的效率，改进与您的客户，供应商和其他合作伙伴的交流。

B B S

时力开发的这套多类别多用户管理论坛系统适用于各专业站点和门户站点，采用最先进的程序技术而建立，灵活的网站接口和易操作性使得系统倍受关注。

运行参数：1、基于NT平台的ASP开发，数据库可选ACCESS或SQL。
2、三层用户管理，使权限更加清晰。
3、配备论坛邮件系统
4、可设立无限的论坛分类和无限的版主数，可扩展至超大型论 坛
5、独立的可扩充性和肢解性，满足不同场合需求

系统价格：
购买价格：5000元RMB

租用价格：600元RMB/月 加收一次性设置费费200元

聊天室系统
简介：

聊天室是提供给网民一个交友与娱乐的场所，在聊天室里网民可选择自已的聊天对象，与其进行对话交流，是网民之间相互沟通、交流情感的最佳方式之一。同时它已成为各网站提供的一个标准服务，是吸引网民，提高人气的一个重要方式。我公司凭借丰富的网站建设开发经验和优秀的技术队伍，开发的聊天产品采用的是当前国际上最先进的聊天室技术，用户可以自由设定聊天室的数量及名称，达到灵活好用，页面流畅，负载能力强，功能强大，性能稳定的目的。
功能介绍：

1．用户可以对聊天室内的所有人或某一特定用户聊天；
2．用户可以指定聊天语言文字色彩、动作表情；
3．用户可以通过点击"在线列表"中的聊天室内的某一用户进行私聊，
4．用户可以选择是否公布自己的个人信息，若公布了别人可以方便的了解自己从而加强联系。
5．用户可以通过"悄悄话"功能与所在聊天室内的某一用户进行私聊，其他用户看不到谈话内容；
6．用户可以通过 "屏蔽"功能将指定用户的谈话内容完全滤，此功能可以有效地防止个别用户的恶意骚扰；
7．管理员可以将捣乱的用户"踢出"
8．用户可以通过"查找聊友"功能，查找指定聊友是否在线，在哪个聊天室；
9．用户可以通过"退出"功能，随时结束聊天，退出聊天系统。

互 动 社 区 系 统

互动社区可独立于网站而单独使用，也可以完整的嵌入网站式服务，集成了BBS系统、站内邮件系统、排行系统和娱乐系统……，具有很强的分解性和融合性，优化了社区的访问端口，供更大的访问强度和在线人数。

运行参数：1、基于NT平台的ASP开发，数据库可选ACCESS或SQL。
2、独特的用户资料档案和涉及应用。
3、提供优秀的多论坛级BBS系统，并与站内信件和用户资料充分融合
4、先进的站内信件系统，
5、独立的可扩充性和肢解性，满足不同场合需求

系统价格：
正式运作版（购买） 价格：20000元RMB
互动租用版（租用） 价格：1000元RMB/月
加收一次性设置费费2000元

加选配件： 单房间版聊天室 配件价格：1000元RMB
多房间版聊天室 配件价格：2000元RMB
社区组合后台（集成社区各功能后台） 配件价格：5000元RMB
高端等级管理 配件价格：1500元RMB

客户反馈系统

简介：

客户反馈系统用于用户从网上获取各种客户反馈信息，客户反馈时几乎是所有网站必备的工具，而目前大部分网站的客户反馈功能是以邮件的信息直接发送到管理者信箱中，这种形式无法对反馈信息分类管理查询统计，而我公司反馈系统完全基于数据库设计，提供强大的后台管理功能。

功能介绍：

1．客户反馈系统
2．反馈表种类设计
3．提交反馈表
4．管理员查询反馈表
5．反馈种类、地域统计
6．反馈表回复
7．表单提交时，自动发送邮件

论坛系统

简介：

论坛是网上社区交流的主要形式，它使人与人的交流不受时间和地点的限制。我公司开发的论坛系统具有方便易用、界面简洁清晰、功能强大、易与扩展等特点，它不仅适用于互联网站，也可以用于有Intratnet网的单位用于内部员工交流。

功能特点：

1．论坛分类， 用户可方便快捷的构建自己的网站论坛。
2．文章发表
3．文章浏览
4．文章跟贴评论
5．文章查询，按时间或关键字查询。
6．热门论坛、热门话题
7．文章浏览统计分析
8．版主申请与授权
9．版主管理维护论坛文章。

邮件列表系统

简介：

为客户提供方便的及时的信息是网络服务的重要功能。 如果您的网站是否有许多的常客，可以通过建立一个邮件列表来发送您的网站最新信息或某些重要消息。如果您有太多邮件列表用户，是为发送邮件速度过慢而犯愁？如何有效的管理这些大量的邮件列表用户，选择我公司邮件列表系统，将给你带来无限方便和轻松。该系统除了适用于网站服务。也可适用于需要建立Internet和Intranet上的邮件订阅功能的个人、单位向订阅者、企业内部门之间，上下级发送新闻、杂志、通知等。

功能介绍：

1．用户可创建多个邮件订阅组；用户可方便地构建自己的邮件订阅。
2．订阅者更方便的订阅和取消订阅。
3．按月统计订阅者人数，并给出统计图表。
4．内容支持Text或HTML格式，也可以发送附件。
5．管理员可以网上进行发送邮件、更改密码、成员导入、删除等操作；
6．允许有多个管理员，成员管理时知道已确认者与未确认者。

新闻发布系统

产品简介

网站新闻发布系统，是将网站上的需要经常变动的信息，类似公司动态、企业新闻、新产品发布、促销活动和行业动态等更新信息集中管理，并通过信息的某些共性进行分类，最后系统化、标准化发布到网站上的一种网站应用程序。网站信息通过一个操作简单的界面加入数据库，然后通过已有的网页模板格式与审核流程发布到网站上。

目前许多企业网站的新闻大多是静态的HTML页面，每次更新信息需要做一个页面，然后FTP上传，再修改页面链接，这样维护非常麻烦，而网站新闻发布系统大大减轻了网站更新维护的工作量，通过新闻后台维护程序在浏览器上只需录入文字和上传图片就可以快速实现新闻维护，从而大大加快了信息的传播速度，时时保持网站的活动力和影响力。
功能模块：

（1）类别管理

新闻按类别组织，类别可以动态增加、修改或删除。类组织管理大大提高系统的灵活性和扩展性。
类别管理提供的具体功能如下：
1、增加、修改、删除新闻类别和专题；
2、更改类别顺序以确定新闻类别和专题在网站页面上出现的顺序；

（2）新闻管理

新闻管理功能实现新闻内容的更新与维护，提供在后台输入、查询、修改、删除各新闻类别和专题中的具体新闻的功能，选择某条新闻是否出现在栏目的首页、网站的首页等一系列完善的信息管理功能。
具体包括以下功能：
1、增添、修改、删除各栏目信息（包括文字与图片）的功能；
2、修改信息状态以确定信息是否出现在类别首页或网站首页的功能。

（3） 系统用户管理系统

系统用户：具有管理网站的权限（即可进入后台管理界面）的用户。其下又分为管理员与一般操作员。
管理员具有管理系统管理员的功能，可增加、删除系统管理员帐号，分配与修改一般操作员的权限，并拥有一般操作员的所有权限。
一般操作员可根据用户组进行管理，各用户组拥有不同的权限，同组不同管理员也可具有不同权限(即管理员可属于不同组)；进入后台管理界面后，可看到并对自己权限范围内的栏目进行信息管理。此功能设计便于由不同部门甚至交叉部门的管理员维护与管理不同栏目的信息。

对系统用户的管理包括：

1　增加、删除一般操作员的功能； （管理员才可实现的功能）
2　开放或禁止一般操作员管理权限的功能； （管理员才可实现的功能）
3　修改一般操作员权限的功能； （管理员才可实现的功能）
4　操作日志功能，系统自动记录操作员的操作在案，以备检索。

（4）网站页面编辑功能

网站页面编辑功能可以通过WEB编辑方式轻松实现网站页面的定制功能，还可将页面上的一些固定内容如页眉页脚、广告条、友情链接等，引入WEB编辑功能来处理，将这些日常维护工作量转为系统化、标准化的维护格式，从而保证网站设计风格的统一，同时也可以大大减轻工作量。
1、模板功能：通过引入CSS样式表，可以轻松统一定制网站的设计风格，编辑新闻类别、专题、最新新闻模板，保持页面美观。
2、编辑页眉页脚和导航条功能，页眉页脚独立存放，并可以任意修改页眉页脚的样式。
编辑友情链接功能，可在此用简单的HTML语句编辑网站的合作站点与友情链接，支持图片LOGO链接。

（5）前台新闻浏览及查询

1．最新重要新闻
首页显示重要的十条新闻，若当天新闻超过十条，则由新闻管理员筛选出重要的新闻，若当天新闻不够十条，则系统全部显示当天所有新闻
2．热门新闻
系统自动记录每条新闻的访问次数，在热门新闻中显示最近5天（天数由用户制订）的访问次数最多的新闻。
3．分类检索新闻
按新闻类别显示该类别的新闻。
4．关键字和日期检索
输入关键字和日期，系统检索出满足条件的新闻。

网上商店系统

概述：

我公司根据自己多年的电子商务应用实践和Internet/Intranet应用开发经验，结合国际先进技术和国内企业的特点，开发了一套适合中小企业应用的电子商务解决方案包。 Nets-Shop以国际通用浏览器/服务器工作模式进行设计，可直接运行于INTERNET／INTRANET环境下，其简易而功能强大的接口让使用者透过网络轻松的建立并管理自设的网络商店。毋须购买昂贵的软硬件设备及聘雇专业设计人员，只需一部计算机，透过浏览器，任何人皆可轻轻松松在网上开店做生意。企业可通过它建立自己独有的网上交易平台，可为消费者提供安全、便捷的购物方式，为商家提供交易处理和丰富的管理统计功能，并且该系统支持多种商家接入方式和支付手段。NetsShop具有用户界面友好、使用简洁方便、运行速度快、远程维护方便、系统稳定可靠、易于扩展等特点。它主要功能包括:企业商品录入、商品查询、在线购物、在线支付、定单查询、库存管理、订单管理、配送管理、销售统计分析、访问统计、供货商管理、产品消息发布、售后服务支持、权限管理等全套B2C电子商务功能。

系统功能特点：

一、操作简单易用
网站建构从开始到完全运作只需数小时。
不需懂HTML或其它程序语言。
不需另行安装软硬件设施。
所有网站建置和管理只需上网，透过浏览器即可完成。

二、强大的网站个性化定制功能
提供"网站精灵"引导初次使用者建立网站，并内建数十种各类形式的网页样本供选择。
所有网页可依喜好及需求自行设定，包括：美术设计，公司商标及产品照片，管理产品目录，设定运费及销售税，设定付款方式，增加或删除网页等等。
熟悉HTML的使用者可以使用HTML直接编辑网页。

三、超大商品记录容量及多种检索方法：
理论商品记录容量达1000万种，商品可以树型结构分类组织，用户可以通过分类目录查询，用户根据产品的类型、制造商等逐级进入分类目录，最终找到需要的产品。通过关键字快速查询，关键字可以为产品名称、制造商名称或其它关键字，也可多个关键字查询。

四、强大的销售管理功能：
系统提供定单管理、发货管理、退货管理、库存管理等完备的销售管理流程。库存管理包括货物进出库、库存过多/过少报警、库存时间过长报警、对供货商的应付款（代销或订金方式向供货商进货）等。当用户下完定单后，系统将立即自动向销售人员发出定单通知信，并更新定单库内容，操作人员根据定单执行情况随时更新定单库内容。系统根据定单库内容和库存内容提供动态查询功能，供管理人员随时掌握销售及库存情况。

五、灵活的价格管理体系：
系统对会员进行分组管理，如可以分为普通会员、银卡会员、金卡会员。对每种产品针对不同会员定义不同的优惠价格，会员在购物时候，系统根据其所属的会员组（可享受的折扣）自动计算购物金额。

六、详细的访问统计系统：
对商城的所有栏目都智能化的进行分析，使您能够根据访问的不同情况调配您的栏目分配和补充，最大限度的使您的栏目满足浏览者的爱好

七、智能销售统计及分析功能：
可以按产品分类统计、按产品统计、按会员组统计、按会员统计，可以统计日报、周报、月报、季报、年报。通过统计分析及时为企业作出物流量化分析，帮助企业改善销售策略和营销方式。
系统根据商品销售状况自动生成销售排行榜，在首页"热销产品"栏目中展示。

八、功能完备的新闻发布系统：
采用先进的在线技术，发布首页新闻。不再是简单的数据库信息的显示，而是对站点内容的一种完善和补充。

九、全面的安全控制：
1. SSL安全加密
2. 数据库级的安全控制
3. 跟踪记录每个操作动作，IP地址，操作员
4. 系统的维护和备份

十、可以与现有系统集成：
可输入网下的销售数据库资料，从而整合原有的管理系统。
支持线上实时或传统交易处理系统。

在线技术支持系统

系统功能特点：

1. 可对网站内提供咨询的信息进行分类管理(如技术咨询、设备问题、投诉等)，按照网站管理人员提供的类别进行分类，建立类别目录，管理人员可随时进行目录的修改，可任意增加或删减类别。用户在查找信息时可通过类别进行查找。

2. 网站管理人员可随时对网站中的咨询信息进行修改，可对咨询信息进行信息的更新及删除。信息分阅读级别，如中心、分站、会员、普通用户。每一条信息要指名阅读级别。每个用户只能查到自己权限范围内的信息。查看每条问题时，记录下点击次数。

3. 可实现咨询信息的搜索功能，用户无须在类别中查找，只需输入关键字进行搜索即可，系统在搜索完毕后会自动将搜索结果进行显示。

4. 用户如没有查询到答案，用户可以填写咨询表单，用户进入系统时,也可直接填写咨询表单, 咨询表单按类别分配给各相关处理部门,每个部门制定专业咨询员负责问题咨询，对用户提出的问题，咨询员在网上可以即时看到并且给予解答，对一些典型的问题可以选择加入知识库，这样知识库会自我增长，保证系统运行一段时间后，知识库会包含常用问题，从而减少人工咨询的压力。用户对已经回复的问题可以进一步提出问题，用户可以查询自己咨询单的回复情况。

主要功能模块：

1．技术咨询问题分类
2．技术咨询知识库维护
3．问题智能查询
4．咨询表单提交
5．问题回复
6．典型问题加入知识库
7．问题查询状况统计

网上调查系统

简介：

企业在网上开展调查用来了解客户地消费心理，通过调查统计从而更好地改善服务。我公司网上调查系统产品也适用于利用Internet/Intranet开展各种调查地新闻媒体、政府部门、专业调查公司等用户。

调 查 投 票 系 统

互动网络采用网络技术流行的投票调查方式，结合应用中的结构化处理技术，可简易的操作使用。

运行参数：1、基于NT平台的ASP开发，数据库为ACCESS。
2、独立的可扩充性和肢解性，满足不同场合需求

系统价格：
购买价格：200元RMB

功能介绍：
1．调查项目设置，用户可创建多个调查表；用户可方便快捷的构建的在线调查应用
2．调查表版面设置（宽度、背景色设置）
3．调查结果样式设置（拚图或条形图）
4．后台是设计时，可以随时预览。
5．网站调查表界面自动生成，即采用所见即所得方式建立和修改调查表。
6．调查结果自动生成
7．支持非法投票数据过滤、投票IP地址统计

产品发布系统

简介:
企业在网站上发布产品信息，是企业网站建设必须的也是最重要的。企业的产品数据会经常变化，以静态网页形式发布产品已经不适应这变化需求，我公司产品发布系统是一套基于数据库的即时发布系统，可用于各类产品的实时发布系，前台用户可通过页面浏览查询，后台管理可以管理产品价格、简介、样图等多类信息。本系统具有管理功能强大，速度快，可扩充能力强等特点。

功能介绍：
1．产品分类管理，可以多级分类，以树状组织。
2．产品资料管理，完成产品的增加、删除、修改。可以选择产品是否发布。若不发布，该产品在数据库中，但前台浏览不到。
3．产品分类检索
4．关键字查询产品
5．最新产品浏览
6．热门产品产品浏览
7．产品详细资料显示
8．产品浏览次数记录与统计
9．客户可以发表对产品的评论
10、后台分级别的管理员权限。；

网 络 购 物 系 统

在E时代的今天，电子商务风靡全球，互动网络提供优秀的电子商务全套服务，作你可靠的电子商务专家！
互动eshop网络购物程序基于稳定的服务器端与客户端PORT技术，配备强大功能的后台服务和前台多元化操作界面。

运行参数：1、基于NT平台的ASP开发，数据库为SQL或ACCESS。
2、独立的可扩充性和肢解性，满足不同场合需求
3、用户与购物服务的充分融合。
4、自主的商品类别管理
5、独立的个人用户服务区

系统演示：请点击进入系统演示，进入

系统价格：
购买价格：10000元RMB

租用价格：800元RMB/月 加收一次性设置费费1500元

访 问 统 计 分 析 系 统

基于高速网络访问平台的互动访问统计分析系统正式投入运行，其强大的统计资讯为网站带来科学的统计资料，互动网络同时提供网站流量的公正资料，高速宽敞的系统连接速度和客户资料的稳定性，适用于大中型网站，为您带来中国最好服务的统计分析系统！

运行参数：1、用户租用的访问统计分析系统放置于互动网络专用空间，基
于NT平台。
2、每个用户配备独立的单套程序，并保证享有5M的高速运行空
间。
3、用户无须初始化配置，但可以自己更改用户资料。

系统价格：
正 式 租 用 价 ： 300 元RMB/年
现 行 租 用 价 ： 266 元RMB/年

系 统 购 买 价 ： 6000 元RMB

在线会员注册，管理系统
功能描述：
基本型：浏览者在线填写注册表，经系统审核后实时成为网站全员，页面填加登录验证功能，前台会员可自行维护个人注册信息，可对个人注册信息进行修改和删除，如遗忘密码可在线查询密码，后台设置会员管理界面，管理员可对会员信息进行分类查询（日期、姓名）、删除。
报价：面议
增强型：网站内容针对会员进行个性化设置，可针对会员级别显示不同内容，会员可选定针对自己的个性化页面设计，后台管理界面可对会员依据一定规则(例如：性别、年龄段、所在地区、购物累计等)进行分类统计，可设定会员级别，支持会员级别依据规则自动升级。
报价：面议
网上贸易撮合系统
功能描述：贸易撮合系统提供了众多企业集中发布、查询供求信息的平台，实现了企业进行在线商贸洽谈.

报价：面议

销售与库存实时监测系统
功能描述：总部与分公司、企业与分销商、企业与供应商之间可就营销数据进行检索和统计，对分销商（分公司、供应商）可提供一定的管理权限，进行相关数据的维护、更新。

报价：面议

网上洽谈系统：
功能描述：实现供求双方网上实时在线议价。

报价：面议

网上拍卖系统：
功能描述：在网站上发布物品信息，并接受、记录、对比、处理买家竞投信息的平台.

报价：面议

网上会客室：
功能描述：在网站上用户可随时查询到在线的技术支持人员并与其进行交谈，可呼叫技术人员，可针对某位技术人员进行留言。

报价：面议


web functions & Internet technologies applications
Apart from standard website design and e-business solution services, solaires also provides custom design of various website functions, tailored for your needs. We also help you identify your use of Internet technologies to save communications and office cost, to improve your workflow efficiency and to improve your communications with your clients, suppliers and other partners of your business. Software programs will also be specifically designed for your enterprise deployment.
Website management/functions
--site advertisement system
--webmaster tools

--BBS/chatroom
--enterprise email system
-mailing list
--feedback system
--page publish system
--product publication and query system
--online poll systems
--remote repair system
--website search functions
--online support systems
--news publishing system
Enterprise Internet applications
--computing
--anti-virus
--data backup
--fax
--printing
--Internet access
--workflow
Web programming
--applications in Internet environment
--database programming, databroadcasting, data server, database gate
--multimedia:Flash4,MetaStream2, MP3，RealPlayer, RealSystem G2
Online business
--purchase
--supermarket/shopping mall/sales system/shops
--direct sales system/distribution system
--value added services
--payment
for more info contact our technical department.
close


Webdesign
Webdesign.doc

consult.htm

consult_2.htm

content.htm

content_2.htm

coop.htm

database.htm

database_2.htm

database_en.htm

hosting.htm

itservices.htm

itservices_en.htm

maintenance.htm

maintenance_2.htm

media1.htm

others.htm

others_en.htm

plan.htm

program.htm

program_en.htm

research.htm

security.htm

security_2.htm

toolkit.htm

translation.htm

webfunc.htm

webfunc_2.htm

Webdesign promote

  • ads.htm
  • bbs.htm
  • coop.htm
  • emailsales.htm
  • engine.htm
  • meta.htm
  • promotion.htm

信息技术服务内容
电子商务咨询
为企业决策人提供电子商务实施的步骤，相关技术，费用，时间安排等的咨询。

这是企业在采用信息技术之前应该做的第一步，以了解将来需要做什么，怎么做，费用等

网站策划与设计
  • 域名注册，
  • 主机租用：
  • 网站策划，网站研究与分析：针对某一个行业的相关网站的研究与分析，以决定采用什么风格，内容编排，技术的应用等
  • 培训：针对公司相关员工的培训，使他们知道如何维护网站并在整个设计过程中恰当的配合
  • 内容编辑：
    • 首页设计，包括公司标记(logo),
    • 多媒体技术的采用，
    • 导航结构，
    • 背景，颜色，字体，图像，
    • 数据库的选择等。
  • HTML 编辑和称序设计, Java, Java Script, PERL, PHP, XML, ...
  • 图象设计: logo 设计,数字影像等
  • 文字与网站翻译：
    • 将您的网站 翻译 成英文或其他语言；或者相反

数据库开发和分布式数据集成与交换
  • 开发在线或/和离线数据库，为贵公司组织，商业伙伴，客户，供应商，贸易伙伴，以及公司员工的数据共享构建数据服务环境，包括您的B2B，B2C网站
  • 分布式数据处理
  • 数据转换
网站功能模块的开发

购物车，留言本，注册，在线论坛等

网站维护

  • 上载，下载或修改文件，图象
  • 维护数据库
  • 保证网站畅通，浏览速度快捷
  • 数据备份
  • 提供网站访问分析，客户分析，产品分析等
网络安全设置
如何保证发送与接受电子邮件安全？如何保证网站与用户的关键通讯得到保密？
WAP（Wireless Application Provider)内容设计

WAP是移动终端（手机，笔记本，手持电脑等设备）在互联网上的信息与数字传输协议。与HTML类似，WML是用来编写WAP页面，而 WMLScript与JavaScript/VBScript类似的编写动态WAP应用的脚本语言。。。

网站推广与网络营销

网站建设不等于万事大吉。如果没有恰当的推广与宣传，最好的网站都会默默无闻，少有访问者。我们将告诉您如何增加网站的知名度，和经济效益。
网络多媒体开发

多媒体增加使 得原本死气沉沉的网站顿时多姿多彩。目前网站的多媒体技术呈现出五彩缤纷，有动态图像-例如GIF， 有FLASH动画，而近来则网络实时音乐和影像(Audio/Video}让人们足不出户，欣赏到美妙的乐曲和电影。另外一个行业应用是三维虚拟现实图像 技术，它使观众亲身体验现实世界的物品，人物和自然界。
网络通讯服务

Internet使通讯方式发生了根本的变化，网络电话，网络传真，电子邮件，网上寻呼，聊天，以及与传统通讯工具和技术的结合，真让人眼花缭乱。。。

I’ve devoted almost 4 years (end 1998 to early 2003) to the studies and applications of computer software and Internet applications.

I used to plan to devote my rest of life to IT, and particularly the web design business, for that purpose I have spent my very precious 3 or 4 years (1999-2003) on studying and learning almost all technologies and skills of the software and Internet.? And this is only my memory.

At the first, I wanted to implement an online procurement system when I was working at Deutsche Babcock in Beijing as its purchasing manager, but this was not agreed by the management, and then I’ve decided to go ahead with my plan to enter the IT business “solo”.

Soon afterwards I started to learn the basics of writing and composing and uploading a web page and site using simple tools provided by Netscape.

Then I have studied HTML language, then VBScript, JavaScript and several other scripture languages. To edit images, I have also learned the editing tools of pictures such as PhotoShop and FireWorks that is used by me now. To enable a dynamic website I have also learned a lot of other programming languages (Java, C, C++, VB, Python, PHP, Perl etc) and databases of all sorts (Oracle, SQL Server, MySQL, mSQL etc). And I found also the website is full of multimedia information and tools – Windows Media, Real Player, 3D, virtual reality (VRML) etc, I will also not miss them too. Internet communications was one of my core studies in the mid 2002 with instant messaging, online chatting, Internet fax and telephony, video phone etc as the interesting areas of studies.

And, to develop and configure your websites I’ve also acknowledged with the IDE (Integrated Development Environment) and their tools, and the server environments of all kinds for all programming languages.

Here below are listed technologies that I used to be acquainted with:

  1. Software solutions for Energy/power, Manufacturing(CIMS), SCM/SRM, CRM/ERP/MIS, Quality, Trading industries
  2. China sourcing, marketing, e-marketing or web promotion services.
  3. Consultant for Aerospace Zhonghui, Worknet Hangzhou and Biling Computer Software Ltd. for their Internet applications, and e-business design.
  4. Consultation for the corporate e-office infrastructure based on the LotusDomino and LotusNotes framework and Java programming environment at InRun Science & Technology Ltd. In Hangzhou, see its website at www.inrun.com.cn.
  5. E-business application design and consultation (website, database, programming, online multimedia etc)
  6. IT technology consulting: incl.
    1. E-business consultation
    2. Database design and enterprise data management over diversified platforms and database systems,
    3. Programming - .Net, Java/JSP/Servlet/EJB, PHP,Pyphon, Perl,
    4. Internet communications (VoIP etc),
    5. Multimedia and virtual reality and 3D modeling,
    6. Website configuration, planning, web page design and localization,?? Website research, Multilingual website design, Website management/functions/web programming/Website Communications????
    7. WAP -Wireless Application Protocol????
    8. Application Servers
    9. Enterprise management information systems (ERP, MIS, e-office, CRM, SCM, AMS, PMS, PLM)
    10. Industry software solutions for quality management, international trade, translation and software localization, and others
    11. Powerline communications (PLC);
    12. Software, online services, automation systems and consultation for the solar, windpower, hydropower and general power industries
    13. Software development
    14. Software support???
  7. Solar Software
  8. Windpower Software

This includes e-business consultation, database, programming, Internet communications, multimedia, web page design and localization, enterprise management information systems (ERP, MIS, e-office, CRM, SCM, AMS, PMS, PLM); and industry software (quality management, translation, trade, and others).

e-business consultation

Instruct corporation leaders on steps, relevant technologies, cost, time table and more about his/her e-business strategies:

  • introduction;
  • purpose of your website and your competitors;
  • structure & content;
  • implementation plan;
  • cost;staff and technologies;
  • timetable;
  • etc...

?

website configuration, planning, incl.:
  • domain registration
  • hosting
  • site architecture;
  • orientation (introductory, e-biz like, database-driven or Extranet/Intranet)

website research

study and analysis of websites in a certain industry

web content editing and design
  • front page design, incl. logo, multimedia tools, navigation structure, background, color, font, images, databases etc
  • HTML authoring, Java, Java Script, PERL, PHP, XML...
  • image design: logo, digital photography .

WAP -Wireless Application Protocol

WAP(WML/ WMLScript) ..

multilingual website design

 DETAILS>>>

translate your existing website to another languages - not just simple text translation. If your website involves databases, pictures, animations and audio/video, it's going to be very complicated

web functions customization / web programming

 DETAILS>>>

?

Website management/functions
 | --site advertisement system
 | --webmaster tools
 | --BBS/chatroom
 | --enterprise email system
 | -mailing list
 | --feedback system
 | --page publish system
 | --product publication and query system
 | --online poll systems
 | --website search functions
 | --online support systems
 | --news publishing system
Online business
 | --purchase
 | --supermarket/shopping mall/sales system/shops
 | --direct sales system/distribution system
 | --value added services
 | --payment

multimedia/VRML

DETAILS>>>
  • Flash and animation
  • stream audio/video
  • virtual reality scenes,simulating real world
Internet communications solutions

What are Internet communications in our case ? We are talking about communications tools integrated into your websites - not those stand-alone application software for telephone, fax and relay chatting.

Mutlmedia email

A website integrated mulmedia system enables your visitors to send to you or receive from email or documents with voice, music, video and animation. Thus give them more experiences of your company and the needs of your potential clients.

Website telephone

Image your client click on a link in your website which directly calls your servicemen ? With web telephony technologies this is possible now at very low prices.
Website faxing

The same as with telephone. You may also send and receive your faxes via your websites with emails at a cost of only a fraction of normal fax.

Chatting & call

These technologies are widely used. In addition, voice and image chatting are becoming a fashion. Check with us for your requirement ? Also Internet mesaging with your mobile and call devices are available for your websites. ?

?

website maintenance & promotion
  • collection and analysis of your material for maintenance door to door;
  • uploading, downloading files, images,
  • make sure your server is working well,
  • maintain your databases servers
  • making regular website visit report
  • analyse your visitor behaviors
  • speed up your communication with your client
  • understand your online sales statistics
  • design promotion banners;banner exchange; sitemarketing;
  • mailling list maintenance;
  • register to search engines - manually;
  • code preparation for backup purpose;
  • artistic design and structural planning for website upgrading & expansion;
  • training of your IT personnel for website maintenance;
  • and more

security issues
configure your secure email client, help you send and receive secure mails; set up your SSL web servers, think about your expensive data stored on your hosts ...

database development and distributed data exchange

 DETAILS>>>
  • database development,
  • distributed data exchange,
  • data format transformation


网络广告

网络广告最常见的表现方式是图形广告，如各门户站点主页上部的横幅广告。

使用注意事项：

1) 媒体选择：选择访问率高的ICP当然是最明智的选择，但是也要看你的广告受众是不是与ICP的受众完全吻合。地处京、冀的天下第一城在春节期间投放庙会广告宣传，因为游客定位在北京周边地区，又以娱乐为主，因此在选择范围内的5家ICP中（搜狐、国中网、搜索客、新浪、网易），最终根据访问者定位选择了新浪和搜索客进行广告投放。一周内10几万次的广告播映，点击率为1.5%。从客户的反映看，广告投入得到了相当的回报。

2) 购买方式：国内通用的广告收费模式是按照广告播映次数收取人民币120.00/CPM到320.00/CPM(Cost per one thousand impressions)不等的单位费用。另外搜狐主页的文字广告位是按月收费，最少购买量为3个月/次。

--CPM--Cost per one thousand impressions：以广告图形(Demographic)被LOAD（播映）1000次为基准的网络广告收费模式，如广告主购买20个CPM，意味着所投放的广告可以被播映20，000次。国内ICP偏爱这种计费模式。

--CPC--Cost per click through：也是千次成本计算单位，以广告图形被点击并连接到相关网址或详细内容页面1000次为基准的网络广告收费模式，如广告主购买10个CPC，意味着投放的广告可被点击10，000次。虽然CPC的费用比CPM的费用高得多，但是广告主往往更倾向选择CPC这种付费方式。

3) 广告创意：广告词创意一定要能够"勾住"浏览者的眼光，要能够唤起浏览者 点击的欲望，要给浏览者点击你的图标的理由。图形的整体设计、色彩和图形的动态设计不能喧宾夺主。

4) 广告监控：投放广告后，要求广告播映商提供报告或者直接登录监测广告访问情况。目前国内几大ICP的广告管理软件都比较先进，CHINABYTE采用了NETGRAVITY，搜狐的ACCESS WATCH也要更新为NETGRAVITY，为广告的管理提供了最简洁的界面。

5)最优秀的网络广告站点：

网络广告先锋 www.VIAIA.com ，该站点比较全面地介绍了各种网络广告，是目前国内最优秀的网络广告站点之一。


讨论组BBS

讨论组是指参与讨论的人们之间通过email进行在线交流。管理者有权力保留和删除任何内容。参与者可以用不同的身份参与讨论，以达到人们对你的话题感兴趣以至受到影响。如果每天给所有参与讨论的人们发送一份讨论话题的摘要，还会吸引更多的人参与你的讨论。当你拥有了一定的客户群或潜在客户群，就可以在他们间建立一个讨论组。

讨论组使用技巧：

  • 选择讨论组：先将你的网站归类，如果是关于医学的，就去找健康讨论组；如果是关于旅游的，就去找旅游讨论组。在找到相应的主题后，可以看看大家讨论的热点是什么。

  • 进入虚拟角色：你在进入讨论组时，应尽量避免广告宣传之嫌。可以使用一个虚拟身份参与讨论，然后以另外一个虚拟身份提供咨询或解答。这样的问答方式可能会引起热烈的反响。

  • 建立信任：在讨论问题时尽量务实，不要虚夸，这样容易使人对你的网站产生信任感。


目标电子邮件宣传

当电子商务在国内炒得非常火热的时候，您有没有想过您投资兴建企业网站是否已经为您带来了实际收益？您公司的订单实际增加了吗？我想大部分企业都是期望很高，但实效却相距甚远。引用外国权威机构的调查结果：

一、80%每天上网的用户是为了使用电子邮件；

二、中小型企业网站的访客比例由下面几种情况构成：

1、10-15%是因看到该企业的印刷资料及名片上的网址而访问该网站；

2、20-30%是通过搜索引擎去找到该企业并点击后进入访问；

3、50-60%是收到邮件后被邮件内容所吸引去访问该网站。

可见电子邮件对于互联网用户以及中小型企业的网站访问流量是极其重要的。通过电子邮件进行低成本网络营销是互联网络对全球商业最直接的贡献。电子邮件广告以其高效快捷廉价的特性风靡全球，其取代传统媒体广告的趋势越来越明显，其与传统广告之间的区别几乎就象飞行与步行一样显而易见。现在的您如果想发布任何信息，那么电子邮件毫无疑问是最高效与廉价的选择。

今天，中国的上网人数已近3000万，电子邮件信箱数最保守地估计也有5000万个，并且这个数字还在迅速地增加，全球的邮箱更是有数十亿之巨。拥有如此巨大的用户群，这使得通过电子邮件发布信息作为一种宣传手段日益受到人们的重视，无论你是个人还是单位，无论是求职 、求助 、寻朋觅友 ， 还是发布广告宣传自己的公司、网站，电子邮件宣传的优点都是显而易见的：

1、范围广：只要有足够多的电子邮件地址，你就可以在很短的时间内向数千万甚至上亿的收件人发布信息。

2、效率高：使用专业的邮件群发软件可以实现最高每小时200万封的发信速度，设定好之后，全部自动运行。

3：费用低：只是支付上网费而已。

4、操作便：操作简单，不需要懂高深的计算机知识。

虚拟世界里电子邮件威力无穷，关键看你用得是否巧妙。电子邮件网址宣传有点像传统方式的直销。千万不要相信什么20元买60000个电子邮件的谎言，因为这里可能有五分之四的地址不准确，剩下的五分之一中还可能没有你的潜在客户。

使用电子邮件宣传网址时，主要有如下技巧：

    1) 收集技巧：主动收集方法就是想方设法让客户参与进来，如竞赛、评比、猜谜、网页特殊效果、优惠、售后服务、促销等等。用这种方式来有意识地营造自己的网上客户群，不断地用Email来维系与他们的关系。这个客户群就是你的最大财富。

    2) 准确定位：WEBPRO.com.cn在搜集访问者信息时，将用户定位在WEBMASTER，用户在加入WEBPRO邮件列表后可以获得最新网址通知，而他们在看网址通知的同时也看到了邮件发送者WEBPRO。XIANZAI.com（现在）的对象是在北京地区居住或旅行的外籍人士，他们的电子邮件集中了各航空公司在各个时段推出的折扣政策、税务咨询和MBA培训等所有对外国人居住、学习和工作有用的信息。

    3) 发送周期：如果你是家猎头公司，你的邮件受众范围就很广了，因为每个人都可能换工作。这就是为什么CAREER-POST.com（白领招聘）和BJOL.com（北京职业在线）会在各网站搜集EMAIL地址的原因，因为没有废话，所以大家容易原谅并且接受这样的邮件。

    4) 管理技巧：创建一个邮件列表，把你搜集到的地址通通放进去，直接向这个地址发送就可以了。或者使用EUDORA这样的优秀EMAIL软件，使用EUDORA的Nicknames工具，你只要建立一个别名就可以包含所有的Email地址，然后用Bcc（秘密抄送）的方式发出就可以了。建议最好每个邮件列表以100个邮件地址为限。

    5) HTML格式：比如阿里巴巴网站发送的供求信息邮件是超文本格式，即使其内容与接收者关系不大，也不会被被当作垃圾信件马上删掉，人们至少会留意一下发送者的地址。所以说邮件格式也很重要。

    6) 个性化服务：美国很多在线交易网站会记录客户电子邮件信息，他们会用电子邮件进行客户跟踪。他们的电子邮件可能是生日问候或"一周后你女儿就满3周岁了，4个月前购买的鞋恐怕已经不合脚了，我们的在线商店新到几款童鞋……"

    7) 使用签名文件：据说签名文件是Internet上的广告牌，在签名文件里，你要列入的信息有：姓名、职位、公司名、网址、电子邮件地址、电话号码，这使潜在客户容易对你的网址产生信赖感并引导他们浏览你的网站。


搜索引擎注册

像YAHOO、LYCOS、ALTAVISTA、搜狐、搜索客、YEAH都是导航台，它们的网站功能相似，都是把众多的网站分门别类放到一个网站里，以便浏览者查询。 　　回忆一下，你是如何发现一些好网站的？肯定有导航台的功劳。所以要让别人知道你的网站，你就要想办法让导航台把你的网站收录进去。但仅仅这样是不够的，像ALTAVISTA、YAHOO等有名的英文导航台，每天申请登录的就有几千个网址，你的网站虽然被收录了，可是也许只能排在很靠后的位置。打个比方：你的网站是介绍衣架(hanger)的, 别人在查询关键字时敲了hanger，结果有2100个相符的网址，你在第1567位，可谁会有力气翻70多页呢？（导航台查询页面通常为10个或20个查询结果为一页）。所以一定要掌握注册技巧。

 1．搜索引擎注册技巧

ALTAVISTA、搜索客这样的导航台被称做搜索引擎，它自动收录提交的网址。你在提交网址时要注意：

1)提交内容最丰富的URL，不要只提交根网址(www.company.com)。因为很多公司习惯将主页作成美观的图形，像图书的封面，但是搜索引擎对图没有特殊的好感，自动搜索的软件只喜欢收录文字内容详细、贴切的URL(www.company.com/products.html)。

2)META的使用。有几个导航台（如ALTAVISTA, Hotbot, Infoseek）使用META作为识别标志，所以要正确使用这些信息。META里的Keywords和Description非常重要，它的格式为：
     <head>

<title>------------</title>

<meta name="keyword" content="-----------------------">

<meta name="description" content="---------------------">

     <／head>

3) 关键字要准确选择与放置。选择与站点内容最为贴切的两三个关键字。比如旅游站点可选中国旅游、中国旅行、TOUR CHINA和CHINA TRAVEL等作为关键字，并首先要在标题(TITLE)中出现，正文也要尽量有重复这些关键字。选择的关键字应该在三个以上，浏览者利用导航台查询信息时，键入的关键字往往很明确，如中国旅游代理--Tour Agent China。

4)不要提交分栏FRAME页面。大部分导航台不识别FRAME，所以一定要提交有内容的MAIN页面。但如果碰巧这个页面与其他页面没有做链接，那就需要一个桥页，也就是新设计一个符合各项要求的页面。

2．搜索目录提交技巧

像YAHOO、搜狐等导航台采用手工方式收录网址，以保证收录网站的质量，在分类查询时获得的信息相关性比搜索引擎站点（靠SPIDER自动搜索的）更强。这就是YAHOO、搜狐分别成为英文和中文访问人次最多的导航台的主要原因。

由于搜索目录网站收录网站的人为因素相对较多，因此在提交网站时要注意遵守规则。如YAHOO要求注册站点描述不超过25个单词。

1) 将网址提交到最合适的目录下面。最简单的办法是看看同类产品或服务的网址在哪一个目录下，比如你的产品是打火机，就查LIGHTER在什么目录下，到那里去提交网址。

2) YAHOO在1999年2月推出了"快速注册"收费服务。如果你的网站内容不错，而网址提交却屡试不中，但又十分想踏进YAHOO大门，那么你可以考虑购买此项服务。YAHOO工作人员会在收到199美金汇款后的七个工作日内，访问你的站点并认真考虑是否将其收录在YAHOO相应目录中。不过YAHOO对此不做承诺，如果网站内容粗糙，交了钱可能也无济于事。

3)中英文导航台提交网址URL
    Yahoo: http://add.yahoo.com/fast/add
    Excite: http://www.excite.com/Info/add_url.html
    AltaVista: http://www.altavista.digital.com/av/content/addurl.htm
    InfoSeek: http://www.infoseek.com/AddUrl?pg=DCaddurl.html
    HotBot: http://www.hotbot.com/addurl.html
    Lycos: http://www.lycos.com/addasite.html
    Webcrawler: http://www.webcrawler.com/Help/GetListed/AddURLS.html
    搜狐： http://168.160.224.207/cgi-bin/regform.asp
    搜索客： http://www.cseek.com/addsite.html
    新浪： http://search.sina.com.cn/cgi-bin/search_dir/addurl.cgi
    YEAH网易： http://www.yeah.net/cgi-bin/search/register/reg.cgi
    长青藤： http://add.tonghua.com.cn:8080/cgi-bin/add

< <


META设计/meta generation
AS Keywords Generator V1.06

软件大小： 308 KB
软件语言： 英文
软件类别： 国外软件 / 共享版 / 网站推广
应用平台： Win95/98/NT/2000
界面预览： 无
加入时间： 2001-05-05 19:08:12
浏览次数： 55
下载次数： 18

联 系 人：
开 发 商： http://www.softexe.com/askw.html

软件介绍：
是一款帮你生成关键字的软件。提高一个网站的访问量方法有许多，最被推崇的方法就是注册到搜索站点，或者设置关键字，等待搜索站点的机器人程序来抓取。AS Keywords Generator 可以帮助你设置关键字。使用起来非常简单，只是需要 3 个步骤。

全部下载地址

META Master 2000 V5.0

软件大小： 1522 KB
软件语言： 英文
软件类别： 国外软件 / 共享版 / 网站推广
应用平台： Win95/98/NT/2000
界面预览： 无
加入时间： 2001-01-19 00:00:00
浏览次数： 69
下载次数： 21

联 系 人：
开 发 商： http://www.net-matrix.com/mm/meta.html

软件介绍：
不错的META工具，帮助你的主页被各大搜索引擎登录提告网站的访问量。

全部下载地址

排名奇兵(Toprank) V1.0

软件大小： 528 KB
软件语言： 简体中文
软件类别： 国产软件 / 免费版 / 网站推广
应用平台： Win95/98/NT/2000
界面预览： 无
加入时间： 2000-12-25 00:00:00
浏览次数： 528
下载次数： 321

联 系 人：
开 发 商： http://www.worldfax.net/

软件介绍：
排名奇兵(Toprank)分析您所选关键字的使用频率，伪装各大搜索引擎蜘蛛程序获得排名第一位网站的秘密META标记，提升您网站在各大搜索引擎的排名。

全部下载地址 [将此软件E-mail给我] [推荐给好友]


网站设计-网络营销

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网站设计-网络营销

拥有一个精心设计的网站只是迈向成功的第一步，如果没有大量的和行之有效的网站推广活动，一个网站根本不会成功，因为少有人甚至没有人会知道它的存在！访问量从某种程度上来说是一个网站的生命线，也是决定一个网站成功与否的唯一标准。

网络营销的技术和方法在不断地变化，目前而言，可以有以下选择：

改造你的站点
1.华丽的页面
尽量使用最新的WEB技术来设计你的页面。因为即使内容是站点的关键,但没有好的视觉享受,会使得访客有枯燥无味的感觉,但在使用新技术时,不要凌驾于访客之上,尽量与每一个人的系统兼容;

2.随时更新
一个长时间不更新的站点,没有人会喜欢,所以,要随时更换站点上的内容,哪怕只是变化一个图片;

3.有价值的内容
网络上,获取信息变得十分容易,所以如果你的站点能经常提供有价值的信息,将更能吸引访客,而如果你只是照搬别人的信息,时间长了,就会令访客感到厌倦;

4.网站速度快
作为个人站点,在选择免费空间服务器时,要选择速度快的,而不是连接超时了,还没有见到半点动静的服务器;

5.交互的内容
越来越多的访客希望有互动的内容,他们不想只是看,还想动动手,在你的站点上加点什么,所以,增加一个BBS或者聊天室,这些都会提高站点的流量。改造站点是提高站点访问量最关键的一步,没有好的站点呈现给访问者,再做什么也是惘然。

搜索引擎登记
统计资料表明，当人们在Internet上寻找信息资源时，90%的人是使用搜索引擎来进行查询检索。建立了网站后，在全球的以及中文的重要搜索引擎、目录服务等站点中进行加注，是作为“网站主人”非常基本的一项工作

把站点注册到搜索引擎是每一个人都会做的,但却没有人真正了解这样做是否真有效。我们的经验,即使你把站点注册到搜索引擎里,也并不能提高站点的流量,可能的机会是,当有一万次搜索时,搜索到你网站点并进入的机会只可能会是1次,更有可能一次机会都没有,我并没有夸张。我们要了解一下注册的技巧,而不是简单的告诉搜索引擎我在那。

搜索引擎分为两种,一种为人工登记,比如yahoo,另一种为自动登记的,这是目前最多的类型。人工登记,就是靠人把站点的资料输入数据库,它的好处是目录会清晰明了,相对来说内容较少,但被搜索到的机会就会增加。而自动登记的站点,内容十分丰富,但这样一来,搜索时,会把不相关的站点也搜索出来。这两种站点,对于我们来说,都可以利用,但要知道一些技巧。

在这里,我要提议的是,如果你的站点是中文的,最好登记到中文的搜索引擎里去。因为这样被找到的机会就能增加不少,而中文搜索引擎站点,首推yaoo,可能你觉得yahoo中文有点不尽人意,但因为它的品牌深入人心,所以访问者非常多。而且它目前所含的内容不丰富,这样,当你把站点成功登记到YAHOO后,被发现的机会要比其它站点多。但有一点我们要注意,在登记站点时,不要把站点归类到个人站点项目里,而要归类到专业的类别,比如新闻或者音乐,因为个人站点所包含的内容太多,而其它专业项目相对来说,内容少得多。这一点要记住。

我们会根据网站的具体内容精确定位相关目录(国内外各主要搜索引擎，包括Yahoo, Alta Vista, MSN, AOL/NetFind, Lycos, Infoseek, Excite, Web crawler, Snap, Hotbot以及雅虎中文，搜狐，新浪网等等)，精心设计关键词、解说语，采用不同的链接方式助您登录，每周根据竞争的情况做出灵活的调整以确保您的网站的排位不断上升，同时我们每月会提交详细的技术分析供您决策。详细的注册程序见说明。

搜索引擎自动注册可以利用免费或付费的软件进行，见搜索引擎注册工具表。

搜索引擎排名设计
登录搜索引擎是目前最常用的网站推广办法。但是仅仅登录至相关搜索引擎并不能给网站带来理想的访问量。一个搜索站点可能会包含十分多的内容,这样,当你搜索某一个站点时,会搜索出成千上万个,而更多的站点已经埋没在了后面。怎样提高自己站点的排位变成了成功登记的关键,因为即使你登记到一个搜索站点上面,但被排在了后面,如果网站没有理想的排名，大多数的访问者是不会注意到您的网站的。所以，还需要在主页设计（关键词，描述文字，标题，内容设计，风格等），登记技巧等方面精心策划，唯此，才有可能达成理想排名的目标。

META的利用

META标签的作用是提供有关HTML文档信息,而它所包含的内容并不出现在网页上。有很多网页制作者很少注意这个标签,因为它并没有影响网页的外观,即使把它删除不用。META最大的作用就是提供搜索引擎关于本站的描述关键字,简单的说,当搜索站台的机器人搜索到你的网站时,会首先检查META所描述的关键字,然后把这些关键字加入到数据库中。所以,利用好META标签会让你在搜索引擎中被搜索到的机会增加。

META标签的用法是这样的:<metaname="Keywords" CONTENT="关键字,关键字,关键字">

在CONTENT处,你尽可能把热门的关键字列出在这里,即使你网页上并不包含这些内容。虽然,这种做法感觉上有点“欺骗”,但值得放心的是,我们只是"欺骗"机器人,所以,放心加入最热的关键字,比如Clinton(克林顿)，这里还有个技巧,你可以重复某一个关键字,这样可以提高自己网站的排行位置,
如:<metaname="Keywords"CONTENT="china,china,china,china>

不过,我还得提醒你,现在"新式"的搜索引擎不再关注META标签了,可能它们发现了那个欺骗,所以,机器人避开了,只是来扫描你的网页,并把出现最多的词作为关键字,或者把网页顶部的词作为关键字,这样,META失去了作用,怎么办,其实,这没有问题，我们还有更多的方法“欺骗”机器人。

因为目前的搜索引擎多数会扫描你的整个网页,这样你可以把热门的关键字放到网页上,这样,每个人都能看到关键字了,当然包括机器人,我们要设法把关键字隐藏到网页里面,怎样做,很简单,把关键字与背景颜色弄成一致即可。

还有一个更好的方法,制作一个网页,把你知道的关键字全部放到这个网页上,想怎么放就怎么放,因为这一页只是给机器人看的,你可以利用以上两种方法设置关键字。要记住,你要做一个链接,连接到你的网站,这样做是最好的方法,因为你可以尽可能提供机器人最全,最好,最热的关键字,而这一页并没有人看到。

投放标题广告
Internet不是魔术场，也遵循着商业正常的投入产出规律和关系。为了使你的站点真正名声大噪，除了网站内容丰富、制作精良、有实际内容和有效的服务，并经常更新和补充外，进行必要的有偿广告是建立高访量的捷径.

标题广告即我们通常所说的"Banner Advertising"。标题广告的大小通常为468*60像素或120*60像素的静态、gif动画或Flash图形。当访问者被广告标题所吸引并点击时，即被链接到广告发布者的网站上，达到网站推广的目的。

标题广告的收费和广告方式与网站的知名度，广告技术等有密切关系，详情见标题广告简介。

广告交换联盟
旗标广告互换是目前比较盛行的一种网站营销方式。你需要向该交换网的管理员申请一个帐号，提交一幅介绍你的站点的图片，该交换网给你一段html代码，你把该段代码加入到你的主页中，每当有人访问你的主页时，该交换网在你的主页上显示一个别人的广告图片（banner），同时你可以得到一定的分数，比如LinkExchange的交换比率是2：1，即当你的主页被访问两次，也就是显示过别人的广告两次，你的banner广告就会在LinkExchange的其它用户的主页上显示一次。由于网络带宽的限制，一般的广告交换网都规定了你的广告图片的大小，如LinkExchange限制为468*60像素，7K以内。LinkExchange不但可以为会员提供广告显示次数的分析，包括你的主页显示了别人的广告次数、你的广告的显示次数和有多少人通过广告访问了你的主页，还可以提供访问流量的分析，包括你的网页的每日访问量，访问量的柱形图，每个月的访问情况统计等.Banner交换方式也是一种很好网站宣传方式，我们将利用自己在这方面的丰富经验为用户解答在这方面的疑难问题。

我们会免费为您设计旗标，精心选择并加入有影响力的旗标互换项目，使您的网站的标志在众多流行网站中出现。

推荐连接站点

  • 网盟
  • 太极链
  • 123banner
  • 联盟广告网
  • hyperbanner

交 换 链 接
所谓交换链接即为利用网页内空闲位置为其他网站建立图片或字符形式的链接，并得到对方的同等交换，达到双方共享访客、共同提高网站访问量的目的。

链接服务与旗标广告服务类似，只是二者的外在表现方式不同。通过此项服务，我们同样可以是您的网站链接到很多有价值的专业网站，从而增加网站的专业访问量。

当你的站点有一定访问量和知名度之后，会有一些网站要求建立友情链接，同时你也可以选择适当的网站要求建立友情链接。这是一种互惠互利的网站推广方式。

详情。。。

E-mail广告
你可以定时向潜在的客户群集中发送目标电子邮件，宣传自己的网站和产品。通过发送大量的电子邮件，你可以提高自己网站的访问率，并从中获得非常有价值的客户。 但是，通过E-mail广告宣传自己，有可能，遭到人们普遍的抵触和厌恶。因此我们建议用户在自己的网站上建立一个邮件列表程序，供客户登记，不断收集客户E-mail信箱，每次发信时向这个邮件目录发信即可。

详情。。。

邮件列表
有许多邮件列表可以参加,你可以参加某一个热门邮件列表,然后试着发表你的讨论,当你的讨论内容被其它人适应的时候,就可以开始宣传你的个人主页了,在这个邮件列表里的人都可以看到你所发表的消息,包括你的URL。记住,别一开始就说出你的网站在那里。
新闻组
通过自己的努力，在Internet中人们自动集结起来的兴趣团体和社区里不断宣传自己，参与活动和讨论，也是一种提高网站知名度的积极有效途径......

新闻组服务是另一项十分重要的服务。我们会根据网站自身的特点和营销目标为您精心选择相关的新闻组并加入其中，及时合理地发布您的产品和服务新闻，从而为您带来理想的访问量。

详情。。。

专业目录服务
通过对您的产品和服务的认真分析。我们会为您选择相关的专业的目录服务机构并注册您的网站，采取与搜索引擎牌位服务类似的方法推广您的网站，确保为您带来可靠的专业访问量。
黄页目录服务
通过此项服务我们将力争使您的网站登录到你的目标市场的主要的黄页目录服务机构，使更多的潜在客户了解您的产品和服务。
与传统结合
1. 公司印刷品：公司信笺、名片、礼品包装都要印上网址名称。让客户在记住你名字、职位的同时，也看到并记住你的网址。

2. 报纸：报纸是使用传统方式宣传网址的最佳途径。"天地环网"网站利用IT报纸的宣传，使大量读者知道了中国库存商品调剂网站。

3. 户外：很多人知道拨263可以上网，进而知道了263就是首都公众信息网，消息途径来自地铁广告；中关村的一些路牌中常可以看到INTEL介绍Pentium III的中文网站 www.intel.com/cn。

4. 电视：中央电视台、凤凰卫视在节目后面都在屏幕上打上了网址名称，NBA现场转播时不时有www.NBA.com字幕滚动。

5. 口头传播：不要低估口头传播的能力，好的网址可以通过同事、朋友和家人进行宣传。

访问流量分析
1. EMAIL反馈分析：通过有效EMAIL数量增减情况判断网站访问量。
2. LOG分析：定期下载LOG访问记录，LOG是纯文本格式的访问者记录，包括访问者IP地址、所在国家、访问时间和访问页面等等。WebTrends Log Analyzer 是一款LOG中分析软件，可以直观地对LOG各项记录作出分析。
制造轰动事件

1. 有奖竞赛：如摩托罗拉经常展开诸如慧笔之类的有奖问答；VIAIA获得国中网和24/7公司的赞助，举办BANNER设计大赛等，都是为了通过活动提高自己的知名度。

2. 网上调查：零点公司和搜狐合作推出的多项调查成功地奠定了网上调查专业公司和网络媒体的合作方式。澳大利亚CONSULT.com.au每年一度在国内举办的网络公民调查也使调查者认识了这个网站。

3. 特殊事件：很多网友是通过亚运站点、国中网年会认识了CHINA.COM；1999年3月15日搜狐推出网上投诉；新浪网前不久推出中国足球联赛站点，这些事件都能为站点知名度锦上添花。


Snapshot of G:\studies\000Webit

2709 files in 610 folders (1717007972)
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Web & IT technologies

IT Technologies

Since end 1998 I was involved in IT technologies and I have spent thousands of hours learning all kinds of web technologies, ranging from programming to online media and hacking. And now my key concern is my online privacy because when I am online I am completely exposed to hackers and malicious people. When one is enclosed in an isolated wall like the Great Firewall Of China, one has to be careful that the government is following one as soon as one wants to surf the outside world. To make my online life more private and safe, I have to know various technologies, tools and strategies. People in China live like in a prison and must be very tactic in order not to be killed by the government. At the moment my IT skills are limited to some C/C++ coding, assembly language and cracking etc.

WEB and IT Studies

Something about the WWW and IT ......

>>> Cyber Security

anonp2p.htm

anonp2p_ref.htm

cracking.html

crypto.htm

webit_secure.htm

ComputerOS

Kernel.htm

Mainboard.htm

bash_profile.htm

devicedrivers.htm

os_intro.htm

shellbatch.htm

utility.htm

ComputerOS linux

  • dns.htm
  • linux-command.htm
  • linux.htm
  • linux4win.htm
  • linux4win1.htm
  • linux_win.htm
  • sendmail.htm
  • sendmail1.htm
  • system1.htm
  • system_en1.htm
  • wine.htm

Database

database.htm

Database china

  • danywhere.htm
  • danywhere_en.htm
  • dbridge.htm
  • dbridge_en.htm
  • dm3.htm
  • dm3_en.htm
  • jox.htm
  • jox_en.htm
  • kingbase.htm
  • kingbase_en.htm
  • others.htm

Database world

  • db2.htm
  • db2_en.htm
  • ibase.htm
  • ibase_en.htm
  • informix.htm
  • informix1.htm
  • informix_2.htm
  • informix_en.htm
  • lotus.htm
  • lotus_en.htm
  • mssql.htm
  • mssql_en.htm
  • mysql-jdbc.htm
  • mysql.htm
  • mysql1.htm
  • mysql_2.htm
  • mysql_en.htm
  • openbase.htm
  • openbase_en.htm
  • oracle-install-log.html
  • oracle-install.htm
  • oracle-install1.htm
  • oracle.htm
  • oracle1.htm
  • oracle2.htm
  • oracle_2.htm
  • oracle_en.htm
  • others_en.htm
  • postgrsql.html
  • psql.htm
  • psql_en.htm
  • sybase.htm
  • sybase_en.htm

IndSoft

comp.htm

crm.htm

erp.htm

mis.htm

net.htm

oa.htm

plc.htm

proj.htm

scm.htm

InternetWEB20

blogdiary.htm

diary.html

NOTICE02.HTM

NOTICE03.HTM

NOTICE04.HTM

Network.htm

myip1.html

websearch.htm

websearchref.htm

MyRegister

  • RegisterInfo-B2B2C.htm
  • RegisterInfo-BBS.htm
  • RegisterInfo-banner.htm
  • RegisterInfo-comm.htm
  • RegisterInfo-ebiz.htm
  • RegisterInfo-email-comm.htm
  • RegisterInfo-email.htm
  • RegisterInfo-energy-cn.htm
  • RegisterInfo-energy-intl.htm
  • RegisterInfo-engine.htm
  • RegisterInfo-girls.htm
  • RegisterInfo-host-domain.htm
  • RegisterInfo-java-other.htm
  • RegisterInfo-job.htm
  • RegisterInfo-marketing.htm
  • RegisterInfo-money.htm
  • RegisterInfo.htm
  • RegisterInfo1.htm
  • RegisterInfo2.htm
  • RegisterWebsites.htm

Netcomm

chat.htm

email.htm

mobile-message.htm

tel.htm

webfax.htm

netmedia

netmedia authoring

  • 3DDreams.htm
  • 3danywhere.htm
  • 3dcreate.htm
  • 3dexplore.htm
  • 3dmodelswork.htm
  • 3dvista.htm
  • EONReality.htm
  • activeworlds.htm
  • adobe.htm
  • albatross.htm
  • alice.htm
  • amiravis.htm
  • anarkmedia.htm
  • anfyteam.htm
  • atomic3d.htm
  • authoring.htm
  • authoring1.htm
  • authoring2.htm
  • authoring3.htm
  • authoring4.htm
  • autodesk.htm
  • b3d.htm
  • bangspace.htm
  • behere.htm
  • blaxxun.htm
  • burozicht.htm
  • cai.htm
  • cryonetworks.htm
  • cycore.htm
  • cylpan.htm
  • duran.htm
  • eovia.htm
  • eyematic.htm
  • geometra.htm
  • glviewer.htm
  • hypercosm.htm
  • ibm.htm
  • iceriver.htm
  • imoveviewer.htm
  • intervista.htm
  • ipix.htm
  • jausoft.htm
  • marlinstep.htm
  • metacreations.htm
  • metacreations1.htm
  • mgisoft.htm
  • mitsubishi.htm
  • modelworks.htm
  • nemo.htm
  • neo3d.htm
  • octree.htm
  • olivertravel.htm
  • openworlds.htm
  • other.htm
  • others.htm
  • oz.htm
  • panavue.htm
  • panofac.htm
  • parallal.htm
  • pixaround.htm
  • pulse.htm
  • pulse3d.htm
  • sense8.htm
  • sgip.htm
  • shellsinteractive.htm
  • sumea.htm
  • tgs.htm
  • ualberta.htm
  • ulead.htm
  • urstudio.htm
  • vecta3d.htm
  • viewpoint.htm
  • virtual3d.htm
  • viscape.htm
  • visviva.htm
  • vrinteractive.htm
  • wildtangent.htm

netmedia avi

  • 3cx.htm
  • LiveTV.htm
  • accord.htm
  • channel.htm
  • cisco.htm
  • ezenia.htm
  • ibm.htm
  • inetcam.htm
  • ipresenter.htm
  • openvideo.htm
  • optibase.htm
  • oracle.htm
  • quicktime.htm
  • radvision.htm
  • real.htm
  • redspider.htm
  • rhythem.htm
  • sgi.htm
  • smil.htm
  • solution.htm
  • techsummery.htm
  • topskys.htm
  • v2tech.htm
  • vcon.htm
  • videojet.htm
  • vtel.htm

netmedia tech

  • 3dml-tut.htm
  • 3dml.htm
  • directx.htm
  • editor.htm
  • editor1.htm
  • jpeg2000.htm
  • jpeg20002.htm
  • opengl.htm
  • svg.htm
  • tech.htm
  • x3d.htm

Programming

Programming.htm

Programming Languages.htm

LogicProgramming.htm

HDL.htm

java.htm

SymbolicLanguages.htm

UML.htm

perl.htm

python.htm

xml.htm

zeena.htm

zeena_en.htm

Servers

apache-php-mysql-tomcat-oracle1.htm

apache-php-mysql.htm

apache.htm

apache1.htm

appserv.htm

appserv1.htm

casp-save.htm

casp.htm

cocoon.htm

cocoon1.htm

dns.htm

iasp-save.htm

iasp.htm

jboss.htm

jboss1.htm

resin.htm

resin1.htm

weblogic.html

WAP

wap.htm

wap_2.htm

wap_internet.htm

waphandy.htm

waphosting.htm

wapres.htm

wapserver.htm

wapsystem.htm

Webdesign

consult.htm

consult_2.htm

content.htm

content_2.htm

coop.htm

database.htm

database_2.htm

database_en.htm

hosting.htm

itservices.htm

itservices_en.htm

maintenance.htm

maintenance_2.htm

media1.htm

others.htm

others_en.htm

plan.htm

program.htm

program_en.htm

research.htm

security.htm

security_2.htm

toolkit.htm

translation.htm

webfunc.htm

webfunc_2.htm

Webdesign promote

  • ads.htm
  • bbs.htm
  • coop.htm
  • emailsales.htm
  • engine.htm
  • meta.htm
  • promotion.htm

More info pls refer to this complete document below

webit.pdf

8Others_Computer.docx
8Others_Internet.docx
8Others_MyMotherWebsites_Wordpress.docx
8Others_MyWebsites.docx
8Others_MyownWebsites_Wordpress.docx
ChinaIT.doc
ITStudies.doc
IT_Info_All1.doc
IT_Info_All2.doc
IT_Info_TOC_1.doc
IT_Info_TOC_1_1.doc
IT_Info_TOC_1_11.doc
IT_Info_TOC_2.doc
WindfallIT.doc


Thermodynamics

00CancerThermo ?????????????

Thermal Physics & Thermodynamics (2008-2010)

After my solar research was given up, I decided to return to my old day learning subject - that is thermophysics. Now among the four key subjects of thermophysics - thermodynamics, fluiddynamics, heat transfer and combustion, I determined to choose thermodynamics as my potential research area, as this is the basics for all other three subject areas. Thermodynamics, unlike what were known to me n my university days, are developed into many new areas of applications. Among them I have exploited the following subbranches:

  • Non-equilibrium Thermodynamics
  • Nanothermodynamics,
  • Thermoeconomics, (exergoeconomic) and exergetic analysis
  • Mesoscopic Thermodynamics (Thermodynamics Of Small Structures),
  • Cosmic Thermodynamics Or Thermodynamics Of The Universe,
  • Thermodynamics Of Cancers,
  • Thermodynamics & Thermophysics Of Life, and Biology
  • Solar Thermodynamics & Thermophysics (corona heating thermodynamics),
  • Thermodynamics and Thermophysics In Solar Radiation And Measurement,
  • Thermodynamics Of Solar Energy Systems, Solar Technology, Industry And Applications
  • SO2 pollution control (1989) - which was my research subject while pursuing master's degree and which was also my possible research subject when trying to do PhD at Zhejiang University in 2011 in Hangzhou.

Here below are shown some records of the studies over the past years:

Solar and Cosmic Thermodynamics.htm

Thermal Physics Thermodynamics.htm

Thermodynamics Literature.htm

Thermodynamics of Cancers Researches.htm

Thermodynamics Researches.htm

太阳热力学研究.htm

Solar & Cosmic Thermodynamics Research Program

Dear Sir or Madam:

I write you this email in order to seek an opportunity to conduct my research and writing program of thermodynamics job at your institution.

My name is Chen Minghua, 45, male Chinese, a postgraduate of thermophysics from Tongji University, Shanghai, China in June 1989.

I have a diversified career path in various industries and roles – refer to my resume (Resume.doc) attached. And now I have decided to reenter the academic world after many ears in the industry and business (see Background.doc for my reasoning) and I am now already executing my thermodynamic research plan – see the plan document (Researches.doc). My aim is to establish a comprehensive Solar & Cosmic Thermodynamics, starting from the thermodynamics of the solar industry and technology in the near terms (2009-2011). The goal of this research and study is to explore possibility to explain relevant thermodynamics phenomenon involved in the entire solar industry. Details see the attached document, or other backing information I will compile in the future.

I hope my research program will invoke your interests.

Sincerely yours,

Chen Minghua
Hangzhou
China
Tel: 0571-8169-1576
Websites: www.helioslab.org

October 17, 2016
Attachments:
The attachments are packed in the Attachments.rar file, which includes the following:
1) Background information – Background.doc,
2) Thermodynamics research plan draft - Researches.doc,
3) Thermodynamics literature - ThermoLiterature.doc,
4) Resume, Resume.doc

Thermodynamics & Thermophysics Research Program

Dear Sir or Madam:

My name is Chen Minghua, 46, male Chinese, a postgraduate of thermophysics from Tongji University, Shanghai, China in June 1989. I write you this email in order to seek an opportunity to conduct my research and writing program of thermodynamics of life or in biology at your institution.

I have a diversified career path in various industries and roles – refer to my resume (Resume.doc) at the link given. And now I am ready to execute my Thermodynamics & Thermophysics research plan – see the plan document (Researches.doc). My aim is to establish a comprehensive Solar Thermodynamics & Thermophysics, starting from the Thermodynamics & Thermophysics of human health (for example illness, particularly cancer) and Thermodynamics & Thermophysics of life. The goal of this research and study is to explore possibility to explain relevant Thermodynamics & Thermophysics phenomenon involved in the entire living process and health problems ?– from the daily activities to cure of specific illnesses. Details see the attached document, or other backing information I will compile in the future.

In addition, I am also interested in the overall development of the thermodynamics science, for that purpose, I have compiled a literature index (in its primitive form) of that science – see ThermoLiterature.doc. Based on this I will further detail the scope and indepth of the studies of thermodynamics, in order to compile a comprehensive review of the thermodynamics science in the medium term.

My another interest is my long-time hobby for foreign languages, apart from English – almost my working language, German, and French (reading capacity), I am also competent to some degree in Russian, and some knowledge in Latin, Greek and Hebrew. I will continue to improve these languages and in the near future, will add Spanish, Arabic and Japanese to my language menu. And then stop.

I still stay in China mainly because I want to take care of my parents at their old ages but now the situation of China and particularly my own situation is so bad that I can’t do so any longer. It’s becoming an unlivable country now, with the authoritative regime controlling the people and media stricter and stricter. The only option is to quit that damned place. More information about the reasons why I want to leave China refer to Persecution.doc provided at the link.

Now, I would like also to remind you that although I am at my mid-40, I am still young – look young, think young, study, work and live like a young student 20 years ago. I have not changed my life style ever since I left the universities, unlike other mid-aged.

I hope my research program will invoke your interests.

Sincerely yours

Chen Minghua
Hangzhou
China
Tel: 0571-8169-1576
Websites: http://groups.google.com/group/helioslab (main entry),
Others: http://www.helioslab.org/
Private site: https://sites.google.com/site/helioslab/
October 17, 2016
Attachments:
The attachments are to be found at the following link ?https://sites.google.com/site/helioslab/today/exodus, which includes the following documents:

1) Thermodynamics research plan draft - Researches.doc,
2 Thermodynamics literature - ThermoLiterature.doc,
3) Resume, Resume.doc ?
4) My political and economical status quo, Persecution.doc
5) Past Researches and Studies - Past_Studies.doc
6) Past Business - Past_Business.doc

Solar Thermodynamics Research Program

Dear Sir or Madam:

I write you this email in order to seek an opportunity to conduct my research and writing program of thermodynamics job at your institution.

My name is Chen Minghua, 45, male Chinese, a postgraduate of thermophysics from Tongji University, Shanghai, China in June 1989.

I have a diversified career path in various industries and roles – refer to my resume (Resume.doc) attached. And now I have decided to reenter the academic world after many ears in the industry and business (see Background.doc for my reasoning) and I am now already executing my thermodynamic research plan – see the plan document (Researches.doc). My aim is to establish a comprehensive Solar Thermodynamics, starting from the thermodynamics of the solar industry and technology in the near terms (2009-2011). The goal of this research and study is to explore possibility to explain relevant thermodynamics phenomenon involved in the entire solar industry. Details see the attached document, or other backing information I will compile in the future.

I hope my research program will invoke your interests.

Sincerely yours,

Chen Minghua
Hangzhou
China
Tel: 0571-8169-1576
Websites: http://helioslab.tripod.com ?http://www.geocities.com/helioslab/

2008-12-24
Attachments:
The attachments are packed in the Attachments.rar file, which includes the following:
1) Background information – Background.doc,
2) Thermodynamics research plan draft - Researches.doc,
3) Thermodynamics literature - ThermoLiterature.doc,
4) Resume, ?Resume.doc

Dear Prof.,

I am writing this letter to talk about a Research on NanoThermodynamics at your group or for your considering my funding applications for my researches on NanoThermodynamics at your Fund.

My research will focuses on NanoThermodynamics.

My question remains what can thermodynamics do for the nanoscience and how new theories shall be developed to adapt to the new dimension.

I am also n writing the book titled “NanoThermodynamics – a Comprehensive Review”.

This book will summarize all thermodynamic topics related to the nano-technologies, mainly in three areas – nanoscale thermodynamics, thermodynamics of nano-materials and thermodynamics of nano-technologies. They can further be subdivided into many sections, for example (incmplete)

  1. Hill’s nanothermodynamics
  2. Tsallis thermodynamics
  3. Thermodynamics of Nano / Nanosize -systems
  4. Thermodynamics of Nano-Processes
  5. Thermodynamics of Nanomanufacturing / Nanofabrication
  6. Thermodynamics of Nano-engineering
  7. Thermodynamics of Nanomeasurements
  8. Thermodynamics of Nano scale characterization
  9. Thermodynamics of Nano-Phases
  10. Thermodynamics of Nanoelectronics
  11. Thermodynamics of Nanobiotechnology
  12. Thermodynamics of Nano Tools
  13. Thermodynamics of nanocanonical constraints
  14. Thermodynamics of nanoclays
  15. Thermodynamics of Nanodots
  16. Thermodynamics of Nanostructures
  17. Thermodynamics of Nano-materials
  18. Thermodynamics of Nano-Porous Materials
  19. Thermodynamics of Nanocrystals / Nanocrystalline materials
  20. Thermodynamics of nanocomposites
  21. Thermodynamics of Nanoparticles
  22. Thermodynamics of nanofibres
  23. Thermodynamics of Nanodroplets
  24. Thermodynamics of Nano-fluids
  25. Thermodynamics of Nano-Products
  26. Thermodynamics of Nano-components
  27. Thermodynamics of Nanodevices

Etc.

The book will describe each of these topic in full details: basic theory, research and application status. Key scientists, main problems, further research plans, problems.

I am planning to complete the writing of this book in two years.

I am not going to pursue a PhD or post-doc nor any specific academic titles. Instead I want to directly start my research without the needs of these programs.

For more details please refer to my research plans to be sent to you on demand.

Thank you very much for your kind consideration, your patience in reading this letter and I remain

Yours sincerely,

Chen Minghua
Shanghai, China
Supporting documents will be sent to you upon requests.

Microscopic Thermodynamics Research Program

Dear Sir or Madam:

I write you this email in order to seek an opportunity to conduct my research and writing program of thermodynamics job at your institution.

My name is Chen Minghua, 45, male Chinese, a postgraduate of thermophysics from Tongji University, Shanghai, China in June 1989.

I have a diversified career path in various industries and roles – refer to my resume (Resume.doc) attached. And now I have decided to reenter the academic world after many ears in the industry and business (see Background.doc for my reasoning) and I am now already executing my thermodynamic research plan – see the plan document (Researches.doc). My aim is to establish a comprehensive Microscopic Thermodynamics, starting from the thermodynamics of nano-scales and nano-science in the near terms (2009-2011). The goal of this research and study is to explore possibility to explain relevant thermodynamics phenomenon at the nano-level. Details see the attached document, or other backing information I will compile in the future.

I hope my research program will invoke your interests.

Sincerely yours,

Chen Minghua
Hangzhou
China
Tel: 0571-8169-1576

2008-12-24
Attachments:
The attachments are packed in the Attachments.rar file, which includes the following:
1) Background information – Background.doc,
2) Thermodynamics research plan draft - Researches.doc,
3) Thermodynamics literature - ThermoLiterature.doc,
4) Resume, ?Resume.doc

Microscopic Thermodynamics Research Program

My aim is to establish a comprehensive Microscopic Thermodynamics, starting from the thermodynamics of nano-scales and nano-science in the near terms (2009-2011). The goal of this research and study is to explore possibility to explain relevant thermodynamics phenomenon at the nano-level.

Research on NanoThermodynamics

My question remains what can thermodynamics do for the nanoscience and how new theories shall be developed to adapt to the new dimension.

I am also n writing the book titled “NanoThermodynamics – a Comprehensive Review”.

This book will summarize all thermodynamic topics related to the nano-technologies, mainly in three areas – nanoscale thermodynamics, thermodynamics of nano-materials and thermodynamics of nano-technologies. They can further be subdivided into many sections, for example (incmplete)

  1. Hill’s nanothermodynamics
  2. Tsallis thermodynamics
  3. Thermodynamics of Nano / Nanosize -systems
  4. Thermodynamics of Nano-Processes
  5. Thermodynamics of Nanomanufacturing / Nanofabrication
  6. Thermodynamics of Nano-engineering
  7. Thermodynamics of Nanomeasurements
  8. Thermodynamics of Nano scale characterization
  9. Thermodynamics of Nano-Phases
  10. Thermodynamics of Nanoelectronics
  11. Thermodynamics of Nanobiotechnology
  12. Thermodynamics of Nano Tools
  13. Thermodynamics of nanocanonical constraints
  14. Thermodynamics of nanoclays
  15. Thermodynamics of Nanodots
  16. Thermodynamics of Nanostructures
  17. Thermodynamics of Nano-materials
  18. Thermodynamics of Nano-Porous Materials
  19. Thermodynamics of Nanocrystals / Nanocrystalline materials
  20. Thermodynamics of nanocomposites
  21. Thermodynamics of Nanoparticles
  22. Thermodynamics of nanofibres
  23. Thermodynamics of Nanodroplets
  24. Thermodynamics of Nano-fluids
  25. Thermodynamics of Nano-Products
  26. Thermodynamics of Nano-components
  27. Thermodynamics of Nanodevices

Etc.

The book will describe each of these topic in full details: basic theory, research and application status. Key scientists, main problems, further research plans, problems.

I am planning to complete the writing of this book in two years.

Dear Prof.,

I am writing this letter to talk about a Research on Thermodynamics of Cancers at your group or for your considering my funding applications for my researches on Thermodynamics of Cancers at your Fund.

My research focuses on applying/developing thermodynamic theory to detect and diagnose cancers.

The first step of my researches is to find out thermodynamic properties, which will be unique to cancer cells and thus can be used to monitor cancer development.

My overall mission, however, is to further explore the possibilities of, to track the development of and to find out ways of applying thermodynamics to, the carcinogenesis mechanism and the prevention and detection of cancer

  1. by combining thermodynamics and oncology into one,
  2. by identifying
    1. thermodynamic, (entropy, enthalpy, Gibbs free energy, heat capacity, conductivity, opacity and others)
    2. cytological,
    3. biological? or
    4. general physical

properties or formulations that can be used to judge as criteria of cancerous sign evolution, exactly as the Gibbs energy is the criteria for judging whether a particular chemical reaction may proceed under certain conditions

  1. with non-classic thermodynamics (i.e.
    1. non-equilibrium,
    2. irreversible,
    3. definite-time,
    4. non-linear thermodynamics as well as,
    5. dissipative theory etc)
  2. at the specific domains (quantum, molecular, cellular and mesocopic levels)
  3. of a particular type of cancer e.g. lung cancer
  4. or a particular human organ/tissues
  5. under specified conditions (carcinogenetic instances such as smoking etc)

I am not going to pursue a PhD or post-doc nor any specific academic titles. Instead I want to directly start my research without the needs of these programs.

For more details please refer to my research plans.

Thank you very much for your kind consideration, your patience in reading this letter and I remain

Yours sincerely,

Chen Minghua
Shanghai / Hangzhou , China
Supporting documents will be sent to you upon requests.

Dear Prof. Dr. Randolph,

Recently I have read some of your papers and publications and I am interested to know if there are possibilities to carry out my researches on Oncological Thermodynamics (OncoThermodynamics) or Thermodynamic Oncology (ThermOncology) at your group.

I am a master of science of engineering thermophysics from an university in China in 1989, however I didn’t go to the academia afterwards, instead I was employed by various forms of corporate, institutions, organizations etc. But I am always looking for a chance to develop my own ideas and theory.

Now I am particularly interested in biothermodynamics and biothermophysics – i.e. these parts of thermodynamics (THD) and thermophysics (THP) applicable to biological substances and biotics and particularly the thermodynamics of cancer.

However, I am determined to turn to the battle against the cancer as this is one of the most dangerous illnesses facing the human kind and this is also one of the most challenging tasks of the world.

My research will focus on the thermodynamics of the theory, prevention, diagnosis, treatment and rehabilitation of cancers, in order to identify how thermodynamics can play roles in the above stages. I am planning to apply non-equilibrium and irreversible thermodynamics to the carcinogenic cellular development.

Please attached find a little more about my research plan.

Thank you very much for your kind consideration and I remain

Yours sincerely,

Chen Minghua
Hangzhou, China
2009/11/16
P.S.:
My resume: http://chen_minghua.gofreeserve.com/today/resume.doc
Mt research idea: http://chen_minghua.gofreeserve.com/today/Research_BioThermo.doc
More information about my qualifications please go to this link: http://chen_minghua.gofreeserve.com/

Dear Prof.,

I am writing this letter to know if there are possibilities to carry out my researches on Oncological Thermodynamics (OncoThermodynamics) or CarcinoThermodynamics? or Thermodynamics of Cancers at your group.

I am a master of science of engineering thermophysics from a university in China in 1989, however I didn’t go to the academia afterwards, instead I was employed by various forms of corporate, institutions, organizations etc. But I am always looking for a chance to develop my own ideas and theory.

Now I am particularly interested particularly in the thermodynamics of cancer, as I am determined to turn to the battle against the cancer as this is one of the most dangerous illnesses facing the human kind and this is also one of the most challenging tasks of the world.

My research will focus on the thermodynamics of the carcinogenetic theory and cancer prevention, in order to identify how thermodynamics can play roles in the above stages. I am planning to apply non-equilibrium and irreversible thermodynamics to the carcinogenic cellular development. Further studies on thermal science such as thermal physics will also be promoted to apply to cancer theory and diagnostics.

Please attached find a little more about my research plan.

Thank you very much for your kind consideration and I remain

Yours sincerely,

Chen Minghua
Hangzhou, China
2010/6/8
P.S.:
My resume: http://chenminghua.6te.net/today/resume.doc
Mt research idea:
More information about my qualifications please go to this link: ?http://chenminghua.6te.net/

Dear Prof Cathy Swart,

Thank you very much for your quick reply to my inquiry. I’ve also quickly reviewed your annual report which was very informative indeed. Although my planned research is not completely compatible with those in the report, nevertheless, I　would like to say that my research can still be done within your team wthout much engagement of your institution. Let me explain a little below.

As described in my brief plan – which I will be finetuning over the next months – I will mainly concentrate on literature reading and thinking, that is, the major part of this period of research is “indoor activities” – i.e. with minimum requirements of insitu observations or experiments – therefore it also involves minimum expenses except my own costs. No labor tests are foreseen. Most expenditures will be spent on how to gain access to the large amount of information, data and materials of other researchers, clinic people and facilities. My main work will be to think thermodynamics and oncology as a whole and to systematize what others have done or are doing upto now. That is, in my mind, more important than to do my own labwork, which is not my strong point.

And because of the nature of this research, which is more theoretical and philosophical than experimental science, my research can “theoretically” be done anywhere. Therefore there shall be no difficulty to “embed” my research activities into your system as well, provided that enough funds and facilities are provided and my freedom of research can be guaranteed. On the other hand, my major facet of the research is the carcinogenesis theory and cancer prevention, of course from the thermodynamics point of view. This approach falls in your domain of research. Diagnosis is of second importance and therapy of little priority.

I don’t want to take you too much time in explanation. If this explanation can help you understand how I am going to undertake my studies, then I will be very happy.

Best wishes,

Chen Minghua

Research on Thermodynamics of Cancers
Oncological Thermodynamics (OncoThermodynamics) or Thermodynamic Oncology (ThermOncology)

I am determined to turn to the battle against the cancer as this is one of the most dangerous illnesses facing the human kind and this is also one of the most challenging tasks of the world.

My research will focus on the thermodynamics of the theory, prevention, diagnosis, treatment and rehabilitation of cancers, in order to identify how thermodynamics can play roles in the above stages. I am planning to apply non-static/non-classic thermodynamics (i.e. non-equilibrium, irreversible, definite-time thermodynamics, dissipative theory etc) at the specific domains (quantum, molecular, cellular and mesocopic thermodynamics) to the carcinogenic cellular development..

The first step of my researches is to find out thermodynamic properties, which will be unique to cancer cells and thus can be used to monitor cancer development.

My overall mission, however, is to further explore the possibilities of, to track the development of and to find out ways of applying thermodynamics to, the carcinogenesis mechanism and the prevention and detection of cancer

  1. by combining thermodynamics and oncology into one,
  2. by identifying
    1. thermodynamic, (entropy, enthalpy, Gibbs free energy, heat capacity, conductivity, opacity and others)
    2. cytological,
    3. biological? or
    4. general physical

properties or formulations that can be used to judge as criteria of cancerous sign evolution, exactly as the Gibbs energy is the criteria for judging whether a particular chemical reaction may proceed under certain conditions

  1. with non-classic thermodynamics (i.e.
    1. non-equilibrium,
    2. irreversible,
    3. definite-time,
    4. non-linear thermodynamics as well as,
    5. dissipative theory etc)
  2. at the specific domains (quantum, molecular, cellular and mesocopic levels)
  3. of a particular type of cancer e.g. lung cancer
  4. or a particular human organ/tissues
  5. under specified conditions (carcinogenetic instances such as smoking etc)

During the first years I will mainly concentrate on literature reading and thinking, that is, the major part of this period of research is “indoor activities” – i.e. with minimum requirements of insitu observations or experiments – therefore it also involves minimum expenses except my own costs. No labor tests are foreseen. Most expenditures will be spent on how to gain access to the large amount of information, data and materials of other researchers, clinic people and facilities. My main work will be to think thermodynamics and oncology as a whole and to systematize and theoretize what others have done or are doing upto now. That is, in my mind, more important than to do my own labwork, which is not my strong point.

And because of the nature of this research, which is more theoretical and philosophical than experimental science, my research can “theoretically” be done anywhere, provided that enough funds and facilities are provided and my freedom of research can be guaranteed. On the other hand, my major facet of the research is the carcinogenesis theory and cancer prevention, of course from the thermodynamics point of view.

Further studies on thermal science and other physical sciences will also be promoted to apply to cancer theory, diagnostics, therapy later on.

Thermodynamics & Thermophysics of life

My aim is to establish a comprehensive Thermodynamics & Thermophysics of human health (for example illness, particularly cancer) and Thermodynamics & Thermophysics of life. The goal of this research and study is to explore possibility to explain relevant Thermodynamics & Thermophysics phenomenon involved in the entire living process and health problems? – from the daily activities to cure of specific illnesses.

I am particularly interested in biothermodynamics and biothermophysics – i.e. these parts of thermodynamics (THD) and thermophysics (THP) applicable to biological substances and biotics.

My first interests are twofold:
1) how to apply them to diagonize and treat cancers and tumors beginning with lung cancer
2) how to apply them to diagonize and treat disease in general
3) how to apply THD and THP to healthcare etc.

My health-related thermodynamic research will start with the diagnosis and treatment of cancers, particularly lung cancer, which is among the most fatal cancers in China and elsewhere. Are there thermodynamic and thermophysical ways, technologies, techniques and methods to detect, follow-up the development of and treatment of these tumors and cancers. How thermodynamics can play roles in the treatment of cancers of various types using technologies such as chemical therapy, radioactive therapy, hyper-thermal therapy and some of the other technologies.???

My aim is to find out bio-THD and bio-THP theories and techniques in the combat against tumors, cancers and other severe illnesses fatal to human life as well as the general healthcare. Among them my first step is to find out bio-THD and bio-THP theories and techniques related to the discovery and control of cancers. For example temperature may change once a cancer emerges, entropy may also be altered, and other THD and THP parameters such as Gibbs free energy flows of human bodies, parts, tissues, membranes, cells and molecular.

Then the researches will be extended to general disease discovery and treatment, where the Gibbs free energy dissipation scenario also very much attracts my attention, which is of course one of my key research areas – as healthy human body basically maintains constant temperature and pressure. Global analysis of Gibbs energy dissipation of healthy and diseased tissues and organisms will reveal some basic theories and practical medical treatment techniques. The difficulties may lie in the measuring technologies (bio-calorimetry) deep into the human body and the moral and ethic problems. Other Thermodynamic properties will also help in this area.

And last the research will be extended to healthcare and aging in general. I’ve read a paper about theromodynamics with aging recently, which also uses Gibbs energy as an indicator. It looks like most people relate health to Gibbs energy, because Gibbs energy in these cases is a direct indication of entropy change.

At the present I am only collecting information, arrange them in order, study these information and step by step I am hoping to figure out my own, systematic ideas in order to develop my particular system of theory. There are a dozens of universities in the world active in these fields but I still need more time to carefully study what they have done. Two or three international symposia have been held in Germany, Donald T. Haynie has written a book called Biological Thermodynamics but that’s all. In my opinion no systematic only sporadic researches here and there have been conducted. There are also no special journal, no special society and no special website dedicated to this area. There are even no faculties for this discipline and there are no … But biothermodynamics will certainly evolve into a big scientific area in the near future, as such it is just in the beginning and I want to involved in this area.

Research & Authoring Plan for
Oncological Thermodynamics (OncoThermodynamics)
or
Thermodynamic Oncology (ThermOncology)

General
My research will focus on thermodynamics of the

  1. Carcinogenesis theory
  2. prevention
  3. diagnosis
  4. monitoring
  5. treatment and
  6. rehabilitation

of cancers.

Non-equilibrium, Irregular Cellular Thermodynamics of Lung Cancers
Initially attention may be paid to apply the non-equilibrium, irregular cellular thermodynamics to lung cancers, which is among the most fatal cancers in the world, in order to identify thermodynamic and thermophysical theories, ways, technologies, techniques, methods and properties in the above stages of the cancer development and cure.

Integration of The Sporadic Thermodynamic Researches of the Worldwide Carcinogenic Academia
My greatest interest is to integrate the sporadic thermodynamic researches of the worldwide carcinogenic academia into a complete system and to understand the relationships between the cancer cell development and the thermodynamic phenomena in the normal cells. Of particular interests and importance is of course the irreversibility of the cell development and one of the most important task is to identify and quantify the critical point and criteria in determining the moment when the cell will be evolved into a malignant one. Thermodynamic models will be developed to quantify the cancerous cell development process and relevant thermodynamic properties used for diagnosis of cancer cells with calorimetry and other techniques.

Book Titled “Thermodynamics Of Cancers”
I am intended to write the book titled “Thermodynamics of Cancers” over the next years.

Current Status
At the present I am only collecting information, arrange them in order, study these information and step by step I am hoping to figure out my own, systematic ideas in order to develop my particular system of theory. There are a dozens of universities in the world active in these fields but I still need more time to carefully study what they have done.

My Research Capacity and Background
Although I am relatively new in this area, particularly I am weak in bioscience, molecular and atomic biology, medicine and medical science, but I realize this will not be a one-man job. Important is, that this man shall have a good picture of the future of this science and I think I am this one.

Also I am a person without Ph.D in science and without books and articles written upto now, but I have written tens of thousands of English reports in various subjects over the last couple of years alone, therefore I think I am able to conduct scientific researches and write scientific reports in the shortest time. I am learning several times faster than most people – while others read in pages, I in books, that is, I complete reading a book in hours not days. What others need months I need days, etc. Therefore I may catch up with those people who are in this area for decades in a couple of years. In addition I am also proficient in several European languages – English, German, French, Russian, and some Latin, Greek and Hebrew.

Research & Authoring Plan for
Oncological Thermodynamics (OncoThermodynamics)
or
Thermodynamic Oncology (ThermOncology)

General
My research will focus on thermodynamics of the

  1. Carcinogenesis theory
  2. prevention
  3. diagnosis
  4. monitoring
  5. treatment and
  6. rehabilitation

of cancers.

Non-equilibrium, Irregular Cellular Thermodynamics of Lung Cancers
Initially attention may be paid to apply the non-equilibrium, irregular cellular thermodynamics to lung cancers, which is among the most fatal cancers in the world, in order to identify thermodynamic and thermophysical theories, ways, technologies, techniques, methods and properties in the above stages of the cancer development and cure.

Integration of The Sporadic Thermodynamic Researches of the Worldwide Carcinogenic Academia
My greatest interest is to integrate the sporadic thermodynamic researches of the worldwide carcinogenic academia into a complete system and to understand the relationships between the cancer cell development and the thermodynamic phenomena in the normal cells. Of particular interests and importance is of course the irreversibility of the cell development and one of the most important task is to identify and quantify the critical point and criteria in determining the moment when the cell will be evolved into a malignant one. Thermodynamic models will be developed to quantify the cancerous cell development process and relevant thermodynamic properties used for diagnosis of cancer cells with calorimetry and other techniques.

Book Titled “Thermodynamics Of Cancers”
I am intended to write the book titled “Thermodynamics of Cancers” over the next years.

Current Status
At the present I am only collecting information, arrange them in order, study these information and step by step I am hoping to figure out my own, systematic ideas in order to develop my particular system of theory. There are a dozens of universities in the world active in these fields but I still need more time to carefully study what they have done.

My Research Capacity and Background
Although I am relatively new in this area, particularly I am weak in bioscience, molecular and atomic biology, medicine and medical science, but I realize this will not be a one-man job. Important is, that this man shall have a good picture of the future of this science and I think I am this one.

Also I am a person without Ph.D in science and without books and articles written upto now, but I have written tens of thousands of English reports in various subjects over the last couple of years alone, therefore I think I am able to conduct scientific researches and write scientific reports in the shortest time. I am learning several times faster than most people – while others read in pages, I in books, that is, I complete reading a book in hours not days. What others need months I need days, etc. Therefore I may catch up with those people who are in this area for decades in a couple of years. In addition I am also proficient in several European languages – English, German, French, Russian, and some Latin, Greek and Hebrew.

Research & Authoring Plan for
Oncological Thermodynamics (OncoThermodynamics)
or
Thermodynamic Oncology (ThermOncology)

General
My research will focus on thermodynamics of the

  1. Carcinogenesis theory and
  2. Cancer prevention.

Non-equilibrium, Irregular Thermodynamics of Cancer Cell Development
Attention may be paid to apply the non-equilibrium, irregular cellular thermodynamics to cancer development, in order to identify thermodynamic and thermophysical theories, ways, properties and criteria in the cancer genesis and later development and pemetration.

I am planning to integrate the sporadic thermodynamic researches of the worldwide carcinogenic academia into a complete system and to understand the relationships between the cancer cell development and the thermodynamic phenomena in the normal cells. Of particular interests and importance is of course the irreversibility of the cell development and one of the most important task is to identify and quantify the critical point and criteria in determining the moment when the cell will be evolved into a malignant one. Thermodynamic models will be developed to quantify the cancerous cell development process and relevant thermodynamic properties used for diagnosis of cancer cells with calorimetry and other techniques.

In one word, just like in chemical thermodynamics, a thermodynamic property shall be identified to be used as a judgment criteria when the normal cell will be changed into a cancerous one.

Book Titled “Thermodynamics Of Cancers”
I am intended to write the book titled “Thermodynamics of Cancers” over the next years.

Current Status
At the present I am only collecting information, arrange them in order, study these information and step by step I am hoping to figure out my own, systematic ideas in order to develop my particular system of theory. There are a dozens of universities in the world active in these fields but I still need more time to carefully study what they have done.

My Research Capacity and Background
Although I am relatively new in this area, particularly I am weak in bioscience, molecular and atomic biology, medicine and medical science, but I realize this will not be a one-man job. Important is, that this man shall have a good picture of the future of this science and I think I am this one.

Also I am a person without Ph.D in science and without books and articles written upto now, but I have written tens of thousands of English reports in various subjects over the last couple of years alone, therefore I think I am able to conduct scientific researches and write scientific reports in the shortest time. I am learning several times faster than most people – while others read in pages, I in books, that is, I complete reading a book in hours not days. What others need months I need days, etc. Therefore I may catch up with those people who are in this area for decades in a couple of years. In addition I am also proficient in several European languages – English, German, French, Russian, and some Latin, Greek and Hebrew.

Research & Authoring Plan for
Oncological Thermodynamics (OncoThermodynamics)
or
Thermodynamic Oncology (ThermOncology)

General
My research will focus on thermodynamics of the

  1. Carcinogenesis theory
  2. prevention
  3. diagnosis
  4. monitoring
  5. treatment and
  6. rehabilitation

of cancers.

Non-equilibrium, Irregular Cellular Thermodynamics of Lung Cancers
Initially attention may be paid to apply the non-equilibrium, irregular cellular thermodynamics to lung cancers, which is among the most fatal cancers in the world, in order to identify thermodynamic and thermophysical theories, ways, technologies, techniques, methods and properties in the above stages of the cancer development and cure.

Integration of The Sporadic Thermodynamic Researches of the Worldwide Carcinogenic Academia
My greatest interest is to integrate the sporadic thermodynamic researches of the worldwide carcinogenic academia into a complete system and to understand the relationships between the cancer cell development and the thermodynamic phenomena in the normal cells. Of particular interests and importance is of course the irreversibility of the cell development and one of the most important task is to identify and quantify the critical point and criteria in determining the moment when the cell will be evolved into a malignant one. Thermodynamic models will be developed to quantify the cancerous cell development process and relevant thermodynamic properties used for diagnosis of cancer cells with calorimetry and other techniques.

Book Titled “Thermodynamics Of Cancers”
I am intended to write the book titled “Thermodynamics of Cancers” over the next years.

Current Status
At the present I am only collecting information, arrange them in order, study these information and step by step I am hoping to figure out my own, systematic ideas in order to develop my particular system of theory. There are a dozens of universities in the world active in these fields but I still need more time to carefully study what they have done.

My Research Capacity and Background
Although I am relatively new in this area, particularly I am weak in bioscience, molecular and atomic biology, medicine and medical science, but I realize this will not be a one-man job. Important is, that this man shall have a good picture of the future of this science and I think I am this one.

Also I am a person without Ph.D in science and without books and articles written upto now, but I have written tens of thousands of English reports in various subjects over the last couple of years alone, therefore I think I am able to conduct scientific researches and write scientific reports in the shortest time. I am learning several times faster than most people – while others read in pages, I in books, that is, I complete reading a book in hours not days. What others need months I need days, etc. Therefore I may catch up with those people who are in this area for decades in a couple of years. In addition I am also proficient in several European languages – English, German, French, Russian, and some Latin, Greek and Hebrew.

Letter

Dear Prof. Dr. Randolph,

Recently I have read some of your papers and publications and I am interested to know if there are possibilities to carry out my researches on bio-thermodynamics at your group..

I am a master of science of engineering thermophysics from an university in China in 1989, I didn’t go to the academia afterwards, instead I was employed by various forms of corporate, institutions, organizations etc. But I am always looking for a chance to develop my own ideas and theory.

Now I am particularly interested in biothermodynamics and biothermophysics – i.e. these parts of thermodynamics (THD) and thermophysics (THP) applicable to biological substances and biotics.

My first interests are twofold:
1) how to apply them to diagonize and treat cancers and tumors beginning with lung cancer
2) how to apply them to diagonize and treat disease in general
3) how to apply THD and THP to healthcare etc.

My health-related thermodynamic research will start with the diagnosis and treatment of cancers, particularly lung cancer, which is among the most fatal cancers in China and elsewhere. Are there thermodynamic and thermophysical ways, technologies, techniques and methods to detect, follow-up the development of and treatment of these tumors and cancers. How thermodynamics can play roles in the treatment of cancers of various types using technologies such as chemical therapy, radioactive therapy, hyper-thermal therapy and some of the other technologies.???

My aim is to find out bio-THD and bio-THP theories and techniques in the combat against tumors, cancers and other severe illnesses fatal to human life as well as the general healthcare. Among them my first step is to find out bio-THD and bio-THP theories and techniques related to the discovery and control of cancers. For example temperature may change once a cancer emerges, entropy may also be altered, and other THD and THP parameters such as Gibbs free energy flows of human bodies, parts, tissues, membranes, cells and molecular.

Then the researches will be extended to general disease discovery and treatment, where the Gibbs free energy dissipation scenario also very much attracts my attention, which is of course one of my key research areas – as healthy human body basically maintains constant temperature and pressure. Global analysis of Gibbs energy dissipation of healthy and diseased tissues and organisms will reveal some basic theories and practical medical treatment techniques. The difficulties may lie in the measuring technologies (bio-calorimetry) deep into the human body and the moral and ethic problems. Other Thermodynamic properties will also help in this area.

And last the research will be extended to healthcare and aging in general. I’ve read a paper about theromodynamics with aging recently, which also uses Gibbs energy as an indicator. It looks like most people relate health to Gibbs energy, because Gibbs energy in these cases is a direct indication of entropy change.

At the present I am only collecting information, arrange them in order, study these information and step by step I am hoping to figure out my own, systematic ideas in order to develop my particular system of theory. There are a dozens of universities in the world active in these fields but I still need more time to carefully study what they have done. Two or three international symposia have been held in Germany, Donald T. Haynie has written a book called Biological Thermodynamics but that’s all. In my opinion no systematic only sporadic researches here and there have been conducted. There are also no special journal, no special society and no special website dedicated to this area. There are even no faculties for this discipline and there are no … But biothermodynamics will certainly evolve into a big scientific area in the near future, as such it is just in the beginning and I want to involved in this area.

Although I am relatively new in this area, particularly I am weak in bioscience, molecular and atomic biology, medicine and medical science, but I realize this will not be a one-man job. Important is, that this man shall have a good picture of the future of this science and I think I am this one.

Now let me ask you Prof. Dr. Randolph, ?are your department interested in the areas above-reiterated? If yes, do you think I may contribute to the development of your research programs? If again yes, do you accept a person without Ph.D in science and without books and articles written upto now, although I have written tens of thousands of English reports in various subjects over the last couple of years? I think I am not an ordinary man, learning several times faster than most people – while others read in pages, I in books, that is, I complete reading a book in hours not days. What others need months I need days, etc. Therefore I may catch up with those people who are in this area for decades in a couple of years. I am also proficient in several European languages – English, German, French, Russian, and some Latin, Greek and Hebrew.

Thank you very much for your kind consideration and I remain

Yours sincerely,

Chen Minghua
Hangzhou, China
2009/11/16
P.S.:More information about my qualifications please go to this link: http://chen_minghua.gofreeserve.com/

List of Study Notes

ThermoDynamics
├<000Miscelleous>
│ ├<Books>
│ │ ├Journals.doc
│ │ ├Terms.doc
│ │ ├Terms热力学术语符号和单位.doc
│ │ ├ThermoLiterature.doc
│ │ ├ThermoLiterature1.doc
│ │ ├ThermoLiterature2.doc
│ │ ├ThermoLiterature_Old.doc
│ │ ├中文Chinese.doc
│ │ ├数据库.doc
│ │ ├浙图书籍.doc
│ │ └热力学书籍.doc
│ ├<Events>
│ │ ├Events.doc
│ │ └学术报告通知.doc
│ ├<News>
│ │ └News.doc
│ ├<ResearchPlans>
│ │ ├Funds_ThermoPlan.doc
│ │ ├Funds_ThermoPlan1.doc
│ │ ├Funds_ThermoPlan2.doc
│ │ ├Researches1.doc
│ │ ├Researches2.doc
│ │ ├Researches3.doc
│ │ ├Researches4.doc
│ │ ├Researches_cn.doc
│ │ ├Researches_Thermodynamics.doc
│ │ ├Researches_Thermodynamics1.doc
│ │ ├Researches_Thermodynamics_Thermophysics_Life.doc
│ │ ├Researches_热力学研究方向.doc
│ │ ├RnDPlan_Thermo.doc
│ │ ├ThermodynamicsResearch.doc
│ │ ├ThermoPlan1.doc
│ │ └ThermoPlan2.doc
│ ├<Resources>
│ │ ├ThermoResources.doc
│ │ ├ThermoResources1.doc
│ │ └ThermoResources2.doc
│ ├<Scientists>
│ │ └Scientists.doc
│ ├<Software>
│ │ ├热力学软件.doc
│ │ ├热力学软件1.doc
│ │ └热力学软件2.doc
│ ├<Thermalpower>
│ │ ├ThermalPowerSystems.doc
│ │ ├ThermalPowerSystems2.doc
│ │ └TOC_ThermoPower.doc
│ ├<ThermoStudy>
│ │ ├ThermoStudy.doc
│ │ ├ThermoStudy1.doc
│ │ ├TOC_Thermo.doc
│ │ └TOC_ThermoPower.doc
│ └<Writing>
│ └Draft.doc
├<Aerosol>
│ └Aerosol Thermodynamics.doc
├<AETHEREAL>
│ └AETHEREAL_THERMODYNAMICS.doc
├<Alloy>
│ ├合金热力学.doc
│ ├合金热力学1.doc
│ ├合金热力学2.doc
│ └合金相图及热力学.doc
├<Ancientchina>
│ └中国古代热力学.doc
├<Applied>
│ └应用热力学1.doc
├<Atmospheric>
│ ├大气热力学.doc
│ └大气热力学1.doc
├<Bible>
│ ├圣经热力学.doc
│ └圣经热力学1.doc
├<Biological>
│ ├BiologicalThermodynamics.doc
│ └生物化学热力学.doc
├<Biotherm细胞热力学>
│ ├Biotherm1.doc
│ ├BiothermAging.doc
│ ├BiothermBooks.doc
│ ├BiothermDiseases.doc
│ ├BiothermEvents.doc
│ └BiothermHealth.doc
├<Businessmanagement>
│ ├BusinessManagementThermodynamics.doc
│ └工商管理热力学.doc
├<CancerThermo>
│ ├CancerHealthThermoNewResearch.doc
│ ├CancerHealthThermoResearch.ppt
│ ├CancerThermoDiagnosis.doc
│ ├CancerThermoDrugs.doc
│ ├CancerThermoPrevent_1.doc
│ ├CancerThermoPrevent_2.doc
│ ├CancerThermoPrevent_3.doc
│ ├CancerThermoPrevent_4.doc
│ ├CancerThermoRehabil.doc
│ ├CancerThermoSpecial.doc
│ ├CancerThermoTheory.doc
│ ├CancerThermoTherapy.doc
│ ├<Funds_Cancer>
│ │ ├Funds_Cancer.doc
│ │ └Funds_Cancer_2.doc
│ ├Research_CancerThermo.doc
│ ├Research_CancerThermo.ppt
│ ├Research_CancerThermo4.doc
│ └Theory.doc
├<Cell>
│ └cells.doc
├<Cement>
│ └Cement-Thermodynamics.doc
├<Chemical>
│ └化工热力学.doc
├<Chemicalequilibrium>
│ └化学平衡热力学.doc
├<Chemistry>
│ ├化学反应热力学.doc
│ ├化学热力学 (2).doc
│ ├化学热力学.doc
│ ├无机化学热力学 (2).doc
│ ├无机化学热力学.doc
│ ├无机化学热力学大纲.doc
│ └电化学热力学.doc
├<Climate>
│ └气候天气热力学.doc
├<Combustion燃烧热力学>
│ ├Combustion Thermodynamics.doc
│ └燃烧热力学.doc
├<Complexsystems>
│ └非常态及复杂体系化学热力学.doc
├<Computation计算热力学>
│ ├Computational Chemical Thermodynamics.doc
│ └计算热力学.doc
├<Continuum>
│ └连续热力学.doc
├<Cooperation>
│ └The thermodynamics of cooperationXXX.doc
├<Corrosion>
│ └腐蚀热力学.doc
├<Cryogenic>
│ ├低温热力学.doc
│ └低温热力学2.doc
├<Crystallization>
│ ├结晶岩热力学.doc
│ └结晶热力学.doc
├<Dissipative>
│ ├耗散结构理论.doc
│ └耗散结构理论1.doc
├<Earth>
│ ├EarthThermodynamics.doc
│ └地球热力学.doc
├<Ecological>
│ └生态热力学.doc
├<Energy>
│ └能量能源系统热力学.doc
├<Engine>
│ └发动机系统热力学.doc
├<Engineering>
│ ├工程热力学.doc
│ └工程热力学1.doc
├<Equibriluim>
│ └平衡态热力学.doc
├<Finance>
│ └金融热力学.doc
├<Finitetime>
│ ├有限时间热力学.doc
│ └有限时间热力学1.doc
├<Fluid>
│ ├流体热力学.doc
│ └超临界流体化学热力学.doc
├<Friction>
│ └摩擦体系热力学.doc
├<Fuel>
│ └Fuel Thermodynamics.doc
├<FuelCell>
│ └FuelCellThermodynamics.doc
├<Gravitational>
│ └GravitationalThermodynamics.doc
├<Greenhouse>
│ └GreenhouseThermodynamics.doc
├<Hierarchical>
│ └HierarchicalThermodynamics.doc
├<History>
│ └历史热力学.doc
├<Information>
│ └信息热力学.doc
├<Irreversible>
│ ├不可逆热力学.doc
│ └不可逆热力学1.doc
├<IT热力学>
│ └IT热力学.doc
├<Kingdom>
│ └王国热力学.doc
├<Life>
│ ├ThermodynamicsLifeEvolution.doc
│ └生命與熱力學.doc
├<Linear>
│ ├线性热力学.doc
│ └线性热力学2.doc
├<Literature>
│ ├文学热力学.doc
│ └文学热力学2.doc
├<Marine>
│ └海洋工程热力学.doc
├<Material>
│ ├MaterialThermodynamics.doc
│ ├含碳耐火材料热力学.doc
│ ├材料热力学.doc
│ ├材料热力学2.doc
│ ├材料的固态热力学.doc
│ ├硅酸盐热力学.doc
│ └耐火氧化物热力学.doc
├<Medecine>
│ └医药热力学.doc
├<Mesoscopic>
│ └MESOSCOPIC THERMODYNAMICS.doc
├<Metallurgical>
│ ├冶金热力学.doc
│ ├冶金热力学2.doc
│ └冶金热化学.doc
├<Metals>
│ ├金属材料热力学.doc
│ └金属热力学.doc
├<Microscopic>
│ └MicroThermoResearch.doc
├<Molecular>
│ └分子热力学.doc
├<Multicomponent>
│ ├Thermodynamics Three-ComponentSystems.doc
│ ├多组分体系热力学2.doc
│ ├多组分体系热力学3.doc
│ └多组分系统热力学.doc
├<NanoTherm>
│ └NanoThermPaper1.doc
├<Negativeenergyspectrum>
│ └负能谱热力学.doc
├<Network>
│ └网络热力学.doc
├<Newconcept>
│ ├新概念热学.doc
│ └新概念热学1.doc
├<NewEnergy新能源热力学>
│ └新能源热力学.doc
├<Nonequilibrium不平衡>
│ ├非平衡态热力学.doc
│ └非平衡态热力学1.doc
├<Nonlinear>
│ └非线性热力学.doc
├<Nuclear>
│ ├Nuclear_Physics_and_Thermodynamics.doc
│ └核热力学.doc
├<Organisms>
│ └Thermodynamics of Organisms.doc
├<Packaging>
│ └Thermodynamics of packaging.doc
├<Phantom>
│ └PhantomThermodynamics.doc
├<Pharma>
│ └药物热力学.doc
├<Physicalchemistry>
│ └物理化学.doc
├<Pnaumatic>
│ └气动热力学.doc
├<Politics>
│ └政治热力学.doc
├<Polymer>
│ └聚合热力学.doc
├<Porousmedia>
│ └多空介质热力学.doc
├<Power>
│ └动力热工学.doc
├<Power电力系统热力学>
│ ├电力系统热力学.doc
│ └电力系统热力学2.doc
├<Quantum>
│ └量子热力学.doc
├<Religion>
│ └宗教热力学.doc
├<Seawater>
│ └海水热力学.doc
├<Selforganization>
│ └自组织现象热力学1.doc
├<Sex>
│ └SexThermodynamics.doc
├<SmallSystems小系统>
│ └Researches_SmallSystemThermo.doc
├<Social>
│ ├社会热力学.doc
│ └社会热力学1.doc
├<SolarComsmoTherm>
│ ├CoronaHeating1.doc
│ ├CoronaHeating2.doc
│ ├Researches_SolarCosmicThermo.doc
│ ├Researches_SolarCosmicThermo1.doc
│ ├Researches_SolarThermo.doc
│ ├Researches_SolarThermo1.doc
│ ├Researches_SolarThermo2.doc
│ ├SolarCosmicThermoResearch.doc
│ ├SolarWind.doc
│ ├天体热力学.doc
│ ├天体热力学2.doc
│ ├太阳热力学.doc
│ ├太阳热力学1.doc
│ ├宇宙热力学.doc
│ ├宇宙物理.doc
│ ├空间热力学.doc
│ └黑洞热力学.doc
├<SolarRad太阳辐射热力学>
│ ├Thermodynamics太阳辐射热力学.doc
│ └太阳辐射热力学.doc
├<SolarThermo>
│ ├ThermodynamicsSolarPowerSystems.doc
│ └太阳能利用中的热力学.doc
├<Solids>
│ └THERMODYNAMICS OF SOLIDS.doc
├<Solution>
│ ├溶液热力学.doc
│ └电解质溶液热力学.doc
├<Statistical统计热力学>
│ ├热力学统计物理.doc
│ ├热力学统计物理1.doc
│ ├统计热力学.doc
│ └统计热力学1.doc
├<Surface>
│ └表面与界面现象热力学.doc
├<Theology>
│ └神学热力学.doc
├<Thermalchemistry>
│ └热化学.doc
├<Thermoeconomics>
│ ├EconomicsThermodynamics.doc
│ ├火用与火无经济学.doc
│ ├热经济学.doc
│ └经济热力学.doc
├<ThermoOthers>
│ ├Theory.doc
│ ├ThermoOthers.doc
│ ├ThermoOthers1.doc
│ ├热分析动力学.doc
│ ├热力学一般.doc
│ ├热动力学.doc
│ ├热工学.doc
│ ├熵.doc
│ ├第五定律.doc
│ └通用热力学.doc
├<Thermophysics>
│ ├ThermalPhysics热物理Lists.doc
│ └热物理.doc
├<Transport>
│ └交通运输系统热力学.doc
├<UniverseThermo>
│ └About_UniverseThermo.doc
├<Variablemass>
│ └变质量热力学.doc
└<Wealthy>
└富人热力学.doc
2018-01-05


Solar thermodynamics

HeliosLab
God is a sun

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You're here >>> Home >>> Solar Thermodynamics

Research & Writing of
Solar and Cosmic Thermodynamics

Thermodynamics of the Sun as well as thermodynamics involved in all areas of solar technology, science, industry and applications, a new chapter

1. General Plan

1) Understand thermodynamic science in its entirety, incl. all its branches. For this purpose a comprehensive list of thermodynamics literature available is prepared as a first guide to the studies. Thousands of papers and articles in different parts of Thermodynamics have also been collected and arranged in the same order as the literature index, so that all future researches can be carried out these bases.

2) Carry out special research on some selected topics of thermodynamics. The final decision is to carry out researches on Solar Thermodynamics, and later to be extended to Cosmic Thermodynamics, details see below.

3) Write the Thermodynamics Review books. This will only be realized at time of maturity – that is, when it's ready.

2. Special Researches – Solar & Cosmic Thermodynamics

This is the first priority of the plan and shall be executed in advance.

No reasoning about this final decision in great details will be given. However, it is based mainly on personal flavor as well as the firm belief that exploration of solar science will eventually benefit the human kind too, and some of the scientific achievements can be readily applied to social and technological progress. When making this decision, no consideration of economic outcome, environment and energy impact as well as food shortage and health problems facing the human race were made.

The solar thermodynamics researches will be split into two parts:

  • Thermodynamics in Solar Technology and Industry and
  • Solar Thermodynamics or Thermodynamics of the Sun

2.1. Thermodynamics in Solar Technology and Industry (2009-01-01 to 2011-12-31)

Three years will be devoted to the investigation and studies of thermodynamics theory involved in all aspects of the solar energy technology and applications, incl.

  • Solar radiation,
  • Solar materials
  • Solar thermal technology
  • Solar phovotoltaic technology
  • Other solar technologies
  • Research and development
  • Manufacturing and
  • Operation and maintenance

Purpose of the research is to find out how to optimize the thermodynamic process during the above processes, periods and stages, and to establish a complete system.

2.2. Solar Thermodynamics (2012-01-01 to 2013-12-31)

After the above research and studies are completed, then the second phase of solar related thermodynamics will be initiated, starting from the Thermodynamics of solar corona heating and Thermodynamics of solar wind.

2.2.1. Thermodynamics of solar corona heating (2012-01-01 to 2012-12-31)

The mechanism of solar corona heating is still unsolved. Where does the energy come to heat up the solar corona from about 10000 Kelvin at the base upto several millions K at its outer boundary – several sun diameter? Some argue it’s due to magnetic force, while other contribute it to seismological movement etc. The aim is to establish physical model to calculate the heating process with different assumptions and try to figure out which is correct. If none is correct, find an assumption. This is of course a challenging task, involving multidisciplinary sciences and lots of solar physics.

The researches will be presented in a paper or a booklet with the following sections:

Part One Solar Corona Physics
? Geometry
? Physics – temperature, density, pressure, velocity, magnetism, radiation and others
? Chemistry

Part Two Review of Solar Corona Heating Models
? Theories, mechanism and assumptions
? Data and charts
? Cons and pros

Part Three Solar Corona Heating Thermodynamics
Application of thermodynamic laws to solar corona heating – the thermal equilibrium, non-equilibrium and non-linear approaches

Part Four Conclusion and Proposals

2.2.2. Thermodynamics of solar wind (2012-01-01 to 2012-12-31)

Solar wind extends from solar atmosphere to the heliosphere and it is interacting with earth’s magnetospehere as well. Thermodynamics will be established to explore some of the key issues of the creation, movement and properties of the solar plasma.

2.2.3. Thermodynamics of the Sun (2013-01-01 to 2013-12-31)

Since 1960's, solar models are well developed, which can fairly correctly explain various sun phenomenon and physical parameters such as temperature, pressure, density, metal abundance, and over the last couple of years, observation, detection, measurement and studies of neutrinos have also proven the solar models.

Nevertheless, neither the solar models nor the solar physics do not touch the solar thermodynamics. The solar modelists concern more about the few basic equations of state, while the solar physicists care about the sun activities only, and now even the generation and activities of the solar magnetic fields and the solar corona heating mechanism are not yet rightly described.

Therefore it is necessary to observe and study the thermal physical phenomenon of the solar internal and surface from the thermodynamics aspects, incl. its thermodynamic state, thermodynamic functions and relations, and to explain the solar magnetic fields and solar corona heating with thermodynamic theory.

2.3. Cosmic Thermodynamics or Thermodynamics of the Universe (2014-01-01 to -- )

Based on the above, thermodynamics researches shall be extended to the cosmos and planets, because over there, the classic theories are no more working, even the entire classic thermodynamics might be overturned. For example, there might predominate the entropy decrease law in the cosmos, while temperature is in most cases negative, because there are sound proves that there exists large amount of dark or negative energy as well as dark and negative matters in the universe, thus the classic thermodynamics will surely be unable to function. All these problems needs to be studied.

A systematic approach will be adopted in the development of the Thermodynamics of Universe (TOU). From planets to stars to galaxies to star clusters and to the entire universe, from the solar system to other planetary systems and celestial bodies. Thermodynamics of all types of celestial bodies will be established with unique features of their own. Questions such as how the celestial bodies and even the Universe were created, evolved and run shall be answered, along with various thermal physical and chemical properties

The Thermodynamics of Universe (TOU) will be a complete science branch of the thermodynamics as a whole. It will establish theories, laws and rules governing the thermodynamic activities of the following:

  • The universe as a whole
  • The galaxies
  • The star clusters
  • The stars – black holes, dwarfs, super nova, etc
  • The planets
  • And other celestial bodies

At the moment, only black hole thermodynamics is relatively intensively researched, while some aspects of the solar thermodynamics (as part of solar, celestial physics and astrophysics) are touched. But generally a complete and logic system is still absent.

3. Thermodynamics Review (? to ?)

Over the past years, thermodynamics has been progressing in both the scope of depth and width.

In the scope of width, thermodynamics has already come out of the equilibrium arena and has entered and penetrated into the non-equilibrium, irreversible states and into the related and non-relevant disciplines such as pharmaceuticals, biotics, ecosystems, energy, social sciences, economics, and management theory etc.:

  • expansion into the cosmos that is the universe system, where gravitational and negative energy as well as dark matters may play vital roles
  • extension to the microscopic areas – cellular, molecular, nanoscales, atomic, subatomic areas and their thermodynamic treatment
  • penetration and merging with other areas of sciences - natural sciences, arts, incl economics, politics, culture, religion, biology, geology, astronomy, etc
  • marching towards the non-classic areas incl
    • non-equilibrium
    • irreversible processes

A preliminary survey shows the thermodynamics has already developed to more than a hundred subbranches. Of course not all of them have become independent disciplines. However special titles and books are already written and published in some branches (refer to ThermoLiterature.doc attached). This list also shows that many of the topics are still not yet covered by the authors.

Therefore it is necessary to understand the current status of the thermodynamics system. Is it necessary to have so many subbranches? Or it is better to maintain a limited number of independent disciplines while the majority appears like the application of the thermodynamic principles to those areas.

Nevertheless, it is necessary to summarize what is achieved in the thermodynamics - its knowledge, theory and experiences, and to present the summarization in form of an encyclopedia, which shall collect all the thermodynamics as detailed above.

This review will also study the correctness of the categorization of the current thermodynamics system, if necessary make some correction. And its main objective is to provide keynote introductions to the individual branches, its recent status of researches and progress, the main obstacles and problems unsolved, the research and development trends and forecasts, and the key scientists in brief.

This review might not be scheduled for the near term task, it will be rather a continuous effort to follow up the general development of thermodynamics and it will be presented to the audience only when it is mature to hand it out to the thermodynamic communities either as printout or e-media.

4. Thermodynamics Literature

A fairly comprehensive list of the thermodynamics literatures is prepared in orders according to its application fields. This 260+ booklet gives readers a first guidance in the realm of this thermal science, at least you know from it how far thermodynamics has now already been developed out of its classic theory back to the mid 1880's. It's amazing how thermodynamics is mingled with every facets of the society and science. It acts as a guide book what to read.

Check with the booklet (English, Chinese and partly French, German, Russian and Japanese).
Last update: July 22, 2016


太阳热力学研究

太阳热力学，以及太阳能利用中的热力学问题的研究

1. 一般计划

1) 全面理解热力学这门学科， 包括其所有分支学科。 为此， 编辑了一个比较详细和完整的热力学文选集， 作为今后学习与研究的书目指引。 也收集了成千上万页的有关热力学各分支学科的文件资料， 并按照文选集同样的分类整理归类。

2) 进行热力学专题研究。 决定进行太阳热力学的研究， 以及今后延伸到宇宙热力学。

3) 编著热力学综述丛书。

2. 专题研究 – 太阳和宇宙热力学

本研究计划将分三个阶段进行。

2.1. 太阳能利用中的热力学 (2009-01-01 至 2011-12-31)

今后三年将研究的重点放在热力学理论在太阳能利用中的应用， 包括：

  • 太阳辐射,
  • 太阳能材料， 例如太阳能级硅
  • 太阳能热利用技术
  • 太阳能光伏技术
  • 其他太阳能技术
  • 太阳能研发过程
  • 生产过程以及
  • 太阳能系统运行等

研究的目的是要以热力学理论来指导和优化上述过程， 并建立一个完整的理论和学科体系。

2.2. 太阳热力学 (2012-01-01 to 2013-12-31)

这是指太阳本身的热力学理论， 分成三个阶段进行。

2.2.1. 日冕加热的热力学 (2009-01-01 至 2010-12-31)

本研究的目的主要是从热力学的观点探讨日冕加热的机制， 并建立一个完整的日冕热力学体系。 研究的结果将表示成以下著述：

第一部分 日冕物理学
? 日冕几何学
? 日冕物理学
? 日冕化学

第二部分 日冕加热机制综述
? 理论， 机制和假设
? 数据和图表
? 评估

第三部分 日冕加热热力学
热力学理论在日冕加热中的应用 - 热力学平衡， 非平衡， 非线性规律

第四部分 结论和建议

2.2.2. 太阳风的热力学 (2010-01-01 至 2011-12-31)

太阳风加热，形成和加速机制是目前研究的热点之一， 如何应用热力学理论来解释这些现象是本课题的要点。 同时对太阳风的热力学相关机制做完整的描述是另一个主要目的。

2.2.3. 太阳热力学 (2010-01-01 至 2011-12-31)

在完成了上述专题研究后， 就进入太阳热力学的最后一个阶段， 太阳热力学理论的建立。这部分的内容需要对目前太阳物理的研究成果做全面的整理， 回顾和总结， 从中归纳出完整的太阳热力学体系， 它将太阳物理过程， 包括内核的能量产生， 以及它们通过各层 - 辐射层， 对流层， 太阳大气各层 - 的传播过程与热力学有关的研究成果汇集起来， 串成一体。 同时， 试图解释某些现象， 包括太阳黑子， 磁场， 日震， 等太阳现象和活动。

2.3. 宇宙热力学 (2014-01-01 至 )

有了以上的基础， 接下来有可能将研究范围扩大到整个宇宙。

宇宙热力学将探讨宇宙作为一个整体的热力学理论， 以及宇宙各部分的热力学现象。研究的范围将包括：

  • 宇宙作为整体
  • 银河系
  • 河外星系
  • 恒星 – 黑洞, 白矮星, 超新星， 类星体 等
  • 行星， 彗星
  • 其它天体

目前仅黑洞热力学有较多的研究。

3. 热力学综述 (? 至 ?)

目前还没有对这部分著述作出详细规划。 初步设想是对各热力学分支（按热力学文选集的顺序）加以整理， 提供如下内容：

  • 主要理论
  • 发展历史
  • 主要科学家和他们的贡献
  • 研究重点
  • 发展趋势
  • 问题和难点

4. 热力学文选集

已经编撰了热力学文选集的草稿， 共262页， 作为进一步研究的起点和参考。

《热力学文选集》（中英文， 部分法文，德文，俄文和日文）
最近更新: 2017-02-12


Thermal Physics & Thermodynamics (2008-2010)

After my solar research was given up, I decided to return to my old day learning subject - that is thermophysics. Now among the four key subjects of thermophysics - thermodynamics, fluiddynamics, heat transfer and combustion, I determined to choose thermodynamics as my potential research area, as this is the basics for all other three subject areas. Thermodynamics, unlike what were known to me n my university days, are developed into many new areas of applications. Among them I have exploited the following subbranches:

  • Non-equilibrium Thermodynamics
  • Nanothermodynamics,
  • Thermoeconomics, (exergoeconomic) and exergetic analysis
  • Mesoscopic Thermodynamics (Thermodynamics Of Small Structures),
  • Cosmic Thermodynamics Or Thermodynamics Of The Universe,
  • Thermodynamics Of Cancers,
  • Thermodynamics & Thermophysics Of Life, and Biology
  • Solar Thermodynamics & Thermophysics (corona heating thermodynamics),
  • Thermodynamics and Thermophysics In Solar Radiation And Measurement,
  • Thermodynamics Of Solar Energy Systems, Solar Technology, Industry And Applications
  • SO2 pollution control (1989) - which was my research subject while pursuing master's degree and which was also my possible research subject when trying to do PhD at Zhejiang University in 2011 in Hangzhou.

Here below are shown some records of the studies over the past years:

  • ThermoStudy.pdf - study schedules of thermodynamics and related sciences ( [image])
  • ThermalPowerSystems.pdf - thermal power systems ( [image])
  • ThermodynamicsCNAbout.pdf - about my thermodynamics studies and research in Chinese ( [image])
  • ThermodynamicsResearch.pdf - about my thermodynamics studies and research plan in details ( [image])
  • ThermoOthers.pdf - about other areas of thermodynamics studies and research ( [image])
  • ThermoLiterature.pdf ( [image])
  • ThermoResources.pdf ( [image])
  • SolarCosmicThermoAbout.pdf - about my solar and cosmological thermodynamics studies and research ( [image])
  • SolarCosmicThermoResearch.pdf - about my solar and cosmological thermodynamics studies and research plans in details ( [image])
  • CancerHealthThermoAbout.pdf - about research intention of thermodynamics of health in particular oncology ( [image])
  • CancerHealthThermoResearch.pdf - about research intention of thermodynamics of health in particular oncology in some details ( [image])
  • CancerHealthThermoNewResearch.pdf - about research intention of thermodynamics of health in particular oncology in detailed, updated recently ( [image])
  • CancerFunds.pdf - about research funds of thermodynamics of health in particular oncology with which I have some contacts ( [image])
  • MicroThermoAbout.pdf - about my microscopic in particular nano thermodynamic reseach ( [image])
  • MicroThermoResearch.pdf - about my microscopic in particular nano thermodynamic reseach in details ( [image])
  • Tongji_MaterThesisAbstract_SO2.pdf - some info about my mster thesis on SO2 pollution control ( [image])
  • ZJUniv_PhD_Plan_003.pdf - my PhD studies plan for Zhejiang University ( [image])
  • ZJUniv_PhD_Thesis_SO2v002.pdf - my PhD thesis plan on SO2 pollution control for Zhejiang University ( [image])
  • ZJUniv_Research_Plan_v010.pdf - my research plan for Zhejiang University ( [image])
  • ZJUniv_Complain.pdf - my complaint against the Zhejiang University's maltreatment of my PhD applications ( [image])


Thermodynamics of Cancer Researches

Our research focuses on applying/developing thermodynamic theory to detect and diagnose cancers.

The first step of our researches is to find out thermodynamic properties, which will be unique to cancer cells and thus can be used to monitor cancer development.

Our overall mission, however, is to further explore the possibilities of, to track the development of and to find out ways of applying thermodynamics to, the carcinogenesis mechanism and the prevention and detection of cancer ?

  • by combining thermodynamics and oncology into one, ?
  • by identifying
    • thermodynamic, (entropy, enthalpy, Gibbs free energy, heat capacity, conductivity, opacity and others)
    • cytological,
    • biological or
    • general physical

properties or formulations that can be used to judge as criteria of cancerous sign evolution, exactly as the Gibbs energy is the criteria for judging whether a particular chemical reaction may proceed under certain conditions ?

  • with non-classic thermodynamics (i.e. ?
    • non-equilibrium, ?
    • irreversible, ?
    • definite-time, ?
    • non-linear thermodynamics as well as, ?
    • dissipative theory etc) ?
  • at the specific domains (quantum, molecular, cellular and mesocopic levels) ?
  • of a particular type of cancer e.g. lung cancer ?
  • or a particular human organ/tissues ?
  • under specified conditions (carcinogenetic instances such as smoking etc)


Thermodynamics Literature

Here we present the visitors a collection of all books already published in the thermodynamics and its sub-branches, both from China and other countries, incl. the classics and the representatives of the current days. The books are arranged in orders of their branches in great details. This is currently the only one of the same kind.

The collection has now grown to about 240 pages in length and is still growing almost daily. At end of this page there is a table of content of this collection, which shows basically how the books are arranged and how deep the categorization is now. Contact us for obtaining a copy of the collection.

List of Collection of Thermodynamics Books in Specific Areas

(As of 2008-12-10)

1. 说明EXPLANATIONS 11

2. 基础学科 THE BASIC BRANCHES 12

2.1. 热物理学THERMAL PHYSICS / THERMOPHYSICS 12
2.1.1. 中文Chinese 12
2.1.2. 西文中译Translated to Chinese from Western Languages 12
2.1.3. 英文English 13
2.2. 热/热学THERMAL SCIENCE /THERMAL PHYSICS/THERMOTICS/THERMOLOGY/CALORIFICS/HEAT 15
2.2.1. 中文Chinese 15
2.2.2. 西文中译Translated to Chinese from Western Languages 18
2.2.3. 俄文中译Translated to Chinese from Russian 18
2.2.4. 日文Japanese 18
2.3. 新概念热学 NEW CONCEPT HEAT / NEW CONCEPT THERMAL SCIENCE 19
2.4. 热工/热工学 THERMODYNAMICS/ THERMAL ENGINEERING 19
2.4.1. 中文Chinese 19
2.4.2. 俄文中译Translated to Chinese from Russian 21
2.4.3. 日文Japanese 21
2.4.4. 流体熱工学 流体热工学 FLUID & HEAT ENGINEERING / Thermal Engineering Fluid 21
2.4.5. 建筑热工学 Building Thermal Engineering / Thermal Engineering Building 21
2.4.6. 机车热工学 Locomotive Thermal Engineering / Thermal Engineering Locomotive 22
2.4.7. 核反应堆热工/核反应堆热工学/反应堆热工水力学Reactor Thermal Engineering / Reactor thermal hydraulics 22
2.4.8. 压水反应堆热工/水冷反应堆热工学 Pressurized Water Reactor Thermal Engineering / WaterCooling Reactor Thermal Engineering 23
2.4.9. 冶金热工/冶金炉热工/冶金生产热工/冶金工厂热工/锻压生产热工学Metalurgical Thermal Engineering / Metallurgical Furnace Thermal Engineering / Metallurgical Production Thermal Engineering / Metallurgical Factory Thermal Engineering / Forging Process Thermal Engineering 24
2.5. 热力学 THERMODYNAMICS 24
2.5.1. 中文Chinese 24
2.5.2. 西文中译Translated to Chinese from Western Languages 29
2.5.3. 俄文中译Translated to Chinese from Russian 30
2.5.4. 英文English 30
2.5.5. 德文German 45
2.5.6. 法文French 48
2.5.7. 日文Japanese 51
2.6. 热动力学 / 动态热力学 / 热分析动力学THERMOKINETICS/HEAT DYNAMICS / DYNAMIC THERMODYNAMICS 51
2.6.1. 中文Chinese 51
2.6.2. 西文中译Translated to Chinese from Western Languages 52
2.7. 热静力学 THERMOSTATICS 52
2.8. 经典/古典热力学CLASSICAL / CLAUSIUS THERMODYNAMICS 53
2.8.1. 中文Chinese 53
2.8.2. 西文中译Translated to Chinese from Western Languages 53
2.8.3. 英文English 53
2.9. INTRODUCTORY THERMODYNAMICS 56
2.10. ELEMENTARY THERMODYNAMICS 56
2.11. BASIC THERMODYNAMICS 56
2.12. ORDINARY THERMODYNAMICS 57
2.13. 通用热力学 / 普通热力学 / 一般热力学 GENERAL THERMODYNAMICS / GENERALIZED THERMODYNAMICS 57
2.14. MODERN THERMODYNAMICS 58
2.15. EXTENDED THERMODYNAMICS 58
2.16. 分析热力学ANALYTIC THERMODYNAMICS 58
2.17. 应用热力学 APPLIED THERMODYNAMICS 59
2.18. 技术热力学TECHNICAL THERMODYNAMICS 61
2.19. 实验热力学PRACTICAL THERMODYNAMICS 62
2.20. 实验热力学EXPERIMENTAL THERMODYNAMICS 62
2.21. 热力学测量THERMODYNAMICS MEASUREMENT 63
2.22. 交互、互动热力学INTERACTIVE THERMODYNAMICS / INTERACTIONAL THERMODYNAMICS 63
2.23. 程序热力学PROGRAMMED THERMODYNAMICS 63
2.24. 非均匀系热力学INHOMOGENOUS THERMODYNAMICS 64
2.25. 物理热力学LA THERMODYNAMIQUE PHYSIQUE 64
2.26. 现象热力学、唯象热力学PHENOMENOLOGICAL THERMODYNAMICS 64
2.27. 热力学表计理论GAUGE THEORY OF THERMODYNAMICS 64
2.28. 水平热力学 65
2.29. 图像热力学GRAPHIC THERMODYNAMICS 65
2.30. 熵 ENTROPY 65
2.30.1. 中文Chinese 65
2.30.2. 西文中译Translated to Chinese from Western Languages 66
2.30.3. 英文English 67
2.31. 火用、火用与火无 EXERGY & ANERGY 68
2.31.1. 中文Chinese 68

3. 微观体系热力学 THE MICROSCOPIC THERMODYNAMICS 70

3.1. 微观热力学MICRO THERMODYNAMICS / MICROCANONICAL THERMODYNAMICS 70
3.2. 热力学与统计物理/ THERMODYNAMICS & STATISTICAL PHYSICS 70
3.2.1. 中文Chinese 70
3.2.2. 西文中译Translated to Chinese from Western Languages 72
3.2.3. 俄文中译Translated to Chinese from Russian 73
3.2.4. 英文English 73
3.2.5. 德文German 74
3.2.6. 法文French 75
3.2.7. 日文Japanese 75
3.3. 热力学与统计力学/ THERMODYNAMICS & STATISTICAL MECHANICS 75
3.3.1. 中文Chinese 75
3.3.2. 日文中译Translated to Chinese from Japanese 76
3.3.3. 英文English 76
3.3.4. 德文German 77
3.3.5. 法文French 78
3.4. 统计热力学 STATISTICAL THERMODYNAMICS/ THERMOSTATISTICS 78
3.4.1. 中文Chinese 78
3.4.2. 西文中译Translated to Chinese from Western Languages 80
3.4.3. 日文中译Translated to Chinese from Japanese 80
3.4.4. 英文English 81
3.4.5. 德文German 83
3.4.6. 日文Japanese 84
3.4.7. 平衡态和非平衡态统计热力学 Equilibrium & Nonequilibrium Statistical Thermodynamics 84
3.4.8. 非平衡统计热力学Nonequilibrium statistical thermodynamics 85
3.5. 固态热物理学SOLID STATE THERMODYNAMICS 85
3.6. 极端热力学 、极限热力学 THERMODYNAMICS OF EXTREMES 85
3.7. 多空介质热力学THE THERMODYNAMICS OF POROUS MEDIA 85
3.8. 表面与界面现象热力学THERMODYNAMICS OF SURFACE AND INTERFACE PHENOMENA 86
3.9. 界面/界观/表观/表面热力学INTERFACE/APPARENT/SURFACE THERMODYNAMICS 86
3.10. 正则，微正则，巨正则系统热力学THERMODYNAMICS OF CANONICAL, MICROCANONICAL, GRAND CANONICAL ENSAMBLES / MICROCANONICAL THERMODYNAMICS 86
3.11. 小系统热力学THERMODYNAMICS OF SMALL SYSTEMS 87
3.12. 微观组织热力学THERMODYNAMICS OF MICROSCOPIC ORGANS 87
3.13. 微细结构热力学THERMODYNAMICS OF MICROSTRUCTURES 87
3.14. 细胞热力学CELLULAR THERMODYNAMICS 87
3.15. 分子热力学 MOLECULAR THERMODYNAMICS 87
3.15.1. 中文Chinese 88
3.15.2. 俄文中译Translated to Chinese from Russian 89
3.15.3. 英文English 90
3.16. 流体的分子热力学LIQUID MOLECULAR THERMODYNAMICS 91
3.17. 流体相平衡的分子热力学MOLECULAR THERMODYNAMICS OF FLUIDPHASE EQUILIBRIA 91
3.18. 生物分子系统热力学THERMODYNAMICS OF BIOMOLECULAR SYSTEMS 92
3.19. 原子核热力学NUCLEAR THERMODYNAMICS 92
3.20. 量子热力学 QUANTUM THERMODYNAMICS 92
3.20.1. 中文Chinese 92
3.20.2. 英文English 92
3.21. 粒子热力学LA THERMODYNAMIQUE DE LA PARTICULE 93

4. 宇宙体系的热力学 THE COSMICAL THERMODYNAMICS 94

4.1. 宇宙热力学THERMODYNAMICS OF THE COSMOS / THERMODYNAMICS OF THE UNIVERSE 94
4.2. 恒星/行星热力学THERMODYNAMICS OF STARS/PLANETS 94
4.3. 等离子热力学THERMODYNAMICS OF PLASMA 95
4.4. 负能谱热力学NEGATIVE ENERGY SPECTRUM THERMODYNAMICS 95
4.5. 黑洞热力学 BLACK HOLE THERMODYNAMICS 95
4.6. 空间、太空热力学SPACE THERMODYNAMICS 95
4.7. 航天热力学THERMOPHYSICS OF SPACE FLIGHT 96
4.8. 大气热力学ATMOSPHERIC THERMODYNAMICS/ THERMODYNAMICS OF THE ATMOSPHERE 96
4.8.1. 中文Chinese 96
4.8.2. 英文English 96
4.9. 气候、气象，天气热力学WEATHER / METEROLOGICAL THERMODYNAMICS 97
4.10. 云的热力学THERMODYNAMICS OF CLOUDS 97
4.11. 悬浮物热力学THERMODYNAMICS OF AEROSOLS 98
4.12. 地球热力学EARTH THERMODYNAMICS 98
4.12.1. 地质学中的热力学Thermodynamics in geology 98
4.12.2. 地质热力学 / Geological thermodynamics 98
4.12.3. 地质化学热力学Geochemical thermodynamics 99
4.12.4. 土壤溶液热力学The thermodynamics of soil solutions 100
4.12.5. 土壤水分热力学Thermodynamics of Soil Moisture 100
4.12.6. 土壤有机质热力学Thermodynamics of Soil Organic 100
4.12.7. 地震热力学Earthquake thermodynamics 100
4.12.8. 矿物科学热力学Thermodynamics in Mineral Sciences 101
4.13. 流域热力学 RIVER BASIN THERMODYNAMICS 101
4.14. 海洋热力学MARINE THERMODYNAMICS 101
4.15. 海水热力学THERMODYNAMICS OF OCEAN WATER 102

5. 平衡态和非平衡态热力学 EQUILIBRIUM & NONEQUILIBRIUM THERMODYNAMICS 103

5.1. 平衡与非平衡统计热力学EQUILIBRIUM AND NONEQUILIBRIUM STATISTICAL THERMODYNAMICS 103
5.2. 平衡热力学 EQUILIBRIUM THERMODYNAMICS 103
5.2.1. 中文Chinese 103
5.2.2. 英文English 103
5.2.3. 法文French 105
5.3. 稳态热力学THERMODYNAMICS OF THE STEADY STATE 105
5.4. 外平衡态热力学 EXTERNAL EQUILIBRIUM THERMODYNAMICS 105
5.5. 局域平衡热力学LOCAL EQUILIBRIUM THERMODYNAMICS 105
5.6. 非局域热力学平衡NONLOCAL THERMODYNAMIC EQUILIBRIUM 105
5.7. 异构平衡热力学THERMODYNAMICS OF HETEROGENEOUS EQUILIBRIA 105
5.8. 非平衡态热力学/不平衡过程热力学NONEQUILIBRIUM THERMODYNAMICS 106
5.8.1. 中文Chinese 106
5.8.2. 英文English 106
5.9. 线性非平衡态热力学LINEARNONEQUILIBRIUM THERMODYNAMICS 109
5.10. 非线性非平衡态热力学NONLINEAR NONEQUILIBRIUM THERMODYNAMICS 109
5.11. THERMODYNAMICS OF SPONTANEOUS AND NONSPONTANEOUS PROCESSES 109
5.12. 理性热力学RATIONAL THERMODYNAMICS 109
5.13. 有限时间热力学 FINITE TIME THERMODYNAMICS 110
5.14. 随机热力学STOCHASTIC THERMODYNAMICS 110
5.15. 不可逆、内可逆过程热力学 (IRREVERSIBLE) ENDOREVERSIBLE THERMODYNAMICS 110
5.15.1. 中文Chinese 110
5.15.2. 西文中译Translated to Chinese from Western Languages 111
5.15.3. 日文中译Translated to Chinese from Japanese 111
5.15.4. 英文English 112
5.15.5. 德文German 113
5.15.6. 法文French 113
5.16. 耗散结构理论 DISSIPATIVE STRUCTURE THEORY 114
5.17. 混沌与有序的热力学THERMODYNAMICS OF CHAOS AND ORDER 114
5.17.1. 混沌热力学Thermodynamics of chaos 114
5.17.2. 混沌与有序的热力学Thermodynamics of chaos and order 115
5.18. 非耗散热力学NONDISSIPATION THERMODYNAMICS 115
5.18.1. 非平衡非耗散热力学NonEquilibrium & Nondissipation Thermodynamics 115
5.19. 自组织系统/自组织现象热力学THERMODYNAMICS OF SELF ORGANIZATION PHENOMENON 115

6. 线性、非线性热力学LINEAR /NONLINEAR THERMODYNAMICS 117

7. 物理体系相关 PHYSICOTHERMODYNAMICS 118

7.1. 数学，数量，计量热力学QUANTITATIVE THERMODYNAMICS / MATHEMATICAL THERMODYNAMICS 118
7.2. 计算热力学COMPUTATIONAL THERMODYNAMICS 118
7.3. 系统热力学THERMODYNAMICS OF SYSTEMS 120
7.4. 复杂系统热力学THERMODYNAMICS OF COMPLEX SYSTEMS 120
7.5. 自然体系热力学THERMODYNAMICS OF NATURAL SYSTEMS 120
7.6. 结构热力学THERMODYNAMICS OF STRUCTURE 120
7.7. 玻璃态热力学THERMODYNAMICS OF THE GLASSY STATE 120
7.8. 连续热力学CONTINUM THERMODYNAMICS 120
7.9. 相对论热力学RELATIVISTIC THERMODYNAMICS 121
7.10. 变质量系统热力学MASSVARIABLE THERMODYNAMICS 122
7.11. 伪塑性热力学THERMODYNAMICS OF PSEUDOELASTICITY 122
7.12. 摩擦体系热力学FRICTION SYSTEM THERMODYNAMICS 122
7.13. 损伤热力学 122
7.14. 机械热力学 MECHANICAL THERMODYNAMICS 123
7.15. 高压热力学THERMODYNAMICS AT HIGH PRESSURES 123
7.16. 过冷水热力学THERMODYNAMICS OF SUPERCOOLED WATER 123
7.17. THERMODYNAMICS OF VARIOUS SYSTEMS 123
7.18. 低温热力学LOW TEMPERATURE THERMODYNAMICS 124
7.19. 电子热力学ELECTRONIC THERMODYNAMICS 125
7.20. 半导体热力学 SEMICONDUCTOR THERMODYNAMICS 125
7.21. 激光系统热力学 THERMODYNAMICS OF LASER SYSTEMS 125
7.22. 能量（能源）系统的热力学THERMODYNAMICS OF ENERGY SYSTEM / ENERGY THERMODYNAMICS 125
7.23. 新能源热力学NEW ENERGY THERMODYNAMICS 126
7.24. 太阳能利用中的热力学THERMODYNAMICS IN SOLAR ENERGY TECHNOLOGY AND APPLICATIONS 126
7.25. 火力发电厂热力学THERMODYNAMICS OF FOSSIL POWER PLANTS 127
7.26. 核电厂热力学 THERMODYNAMICS OF NUCLEAR POWER PLANTS 127
7.27. 电力系统热力学THERMODYNAMICS OF POWER SYSTEMS 128
7.28. 交通运输系统热力学THERMODYNAMICS OF TRANSPORTATION & TRAFFIC SYSTEMS 128

8. 工程热力学ENGINEERING THERMODYNAMICS 130

8.1. 工程热力学ENGINEERING THERMODYNAMICS 130
8.1.1. 中文Chinese 130
8.1.2. 西文中译Translated to Chinese from Western Languages 135
8.1.3. 俄文中译Translated to Chinese from Russian 136
8.1.4. 英文English 137
8.1.5. 德文German 144
8.1.6. 日文Japanese 146
8.2. 基本工程热力学 BASIC ENGINEERING THERMODYNAMICS 146
8.3. 高等工程热力学ADVANCED ENGINEERING THERMODYNAMICS 146
8.4. 波传播的热力学效应THERMODYNAMIC EFFECTS IN WAVE PROPAGATION 147
8.5. 热力过程 THERMAL PROCESS 147
8.6. 流体与过程热力学/热流体学/可压缩流的热力学/液体热力学/LIQUID & PROCESS THERMODYNAMICS/ THERMOMECHANICS/THERMOFLUID / COMPRESSIBLE FLUID THERMODYNAMICS 147
8.6.1. 中文Chinese 148
8.6.2. 西文中译Translated to Chinese from Western Languages 148
8.6.3. 俄文中译Translated to Chinese from Russian 149
8.6.4. 英文English 149
8.6.5. 德文German 152
8.6.6. 法文French 152
8.7. 锅炉热力学 BOILER THERMODYNAMICS 152
8.8. 发动机热力学ENGINE THERMODYNAMICS 153
8.8.1. 中文Chinese 153
8.8.2. 西文中译Translated to Chinese from Western Languages 153
8.8.3. 英文English 154
8.9. 暖通空调系统热力学THERMODYNAMICS OF HVAC 155

9. 气动热力学AEROTHERMODYNAMICS 157

9.1. 气动热力学AEROTHERMODYNAMICS 157
9.2. 高超声速气动热力学ULTRAHIGH SUPERSONIC AEROTHERMODYNAMICS 157
9.3. 动力机械气动热力学AEROTHERMODYNAMICS OF POWER MACHINES 157
9.4. 叶轮机械气动热力学/透平机械热力学/涡轮机械气动热力学/燃气涡轮发动机气动热力学/ 飞机发动机气动热力学/汽轮机气动热力学ROTATING MACHINE AEROTHERMODYNAMICS/THERMODYNAMICS OF TURBOMACHINERY / AEROTHERMODYNAMICS OF TURBONACHINERY / AEROTHERMODYNAMICS OF GAS TURBINES / AEROTHERMODYNAMICS OF AIRCRAFT ENGINES / AEROTHERMODYNAMICS OF STEAM TURBINES 158
9.5. 航天与宇航热力学AEROSPACE & SPACECRAFT THERMODYNAMICS 159
9.6. 船舶动力装置气动热力学AEROTHERMODYNAMICS OF ONBOARD POWER UNITS 160
9.7. 船舶热能机械气动热力学AEROTHERMODYNAMICS OF THERMAL MACHINES FOR SHIPS 160
9.8. 级联气动热力学CASCADE AERODYNAMICS 160

10. 化学热力学CHEMICAL THERMODYNAMICS 161

10.1. 化学热力学CHEMICAL THERMODYNAMICS 161
10.1.1. 中文Chinese 161
10.1.2. 西文中译Translated to Chinese from Western Languages 164
10.1.3. 俄文中译Translated to Chinese from Russian 164
10.1.4. 英文English 165
10.1.5. 德文German 174
10.1.6. 法文French 175
10.1.7. 日文Japanese 177
10.2. 热化学THERMOCHEMISTRY 177
10.2.1. 冶金热化学Metallurgical Thermochemistry 178
10.2.2. 生物质热化学Biomass Thermochemistry 178
10.3. 化学反应热力学THERMODYNAMICS OF CHEMICAL REACTIONS 178
10.4. 无机化学热力学THERMODYNAMICS OF INORGANIC CHEMISTRY 179
10.5. 无机物热力学THERMODYNAMICS OF INORGANIC MATERIALS 179
10.6. 有机物热力学THERMODYNAMICS OF ORGANICS/THERMODYNAMICS OF ORGANIC COMPOUNDS 180
10.7. 溶液热力学THERMODYNAMICS OF SOLUTIONS/SOLVATION THERMODYNAMICS / SOLUTION THERMODYNAMICS 180
10.7.1. 电解质溶液热力学Thermodynamics of Electrolyte Solutions 181
10.8. 非电解质溶液热力学THERMODYNAMICS OF NONELECTROLYTE SOLUTIONS 182
10.9. 电化学热力学ELECTROCHEMICAL THERMODYNAMICS 182
10.10. 胶团热力学 THERMODYNAMICS OF MICELLE 182
10.11. 聚合物热力学POLYMER THERMODYNAMICS / THERMODYNAMICS OF POLYMERIZATION / THERMODYNAMICS OF POLYMER BLENDS 182
10.12. 聚合热力学THERMODYNAMICS OF POLYMER 183
10.13. 离子气热力学THERMODYNAMICS OF IONIZED GASES / THERMODYNAMICS OF PLASMA GAS 183
10.14. 冶金化学热力学THERMODYNAMICS OF METALLURGICAL CHEMISTRY 184
10.15. 计算机辅助化学热力学COMPUTER AIDED CHEMICAL THERMODYNAMICS 184

11. 化工热力学CHEMICAL ENGINEERING THERMODYNAMICS 185

11.1. 化工热力学CHEMICAL ENGINEERING THERMODYNAMICS 185
11.1.1. 中文Chinese 185
11.1.2. 西文中译Translated to Chinese from Western Languages 188
11.1.3. 俄文中译Translated to Chinese from Russian 188
11.1.4. 英文English 189
11.2. 高等化工热力学ADVANCED CHEMICAL ENGINEERING THERMODYNAMICS 189
11.3. 应用化工热力学APPLIED CHEMICAL ENGINEERING THERMODYNAMICS 190
11.4. 石油馏分热力学 190
11.5. 催化裂化反应的热力学 190
11.6. 金属溶剂萃取热力学CHEMICAL THERMODYNAMICS IN METALLIC SOLVENT EXTRACTION 190
11.7. 燃烧热力学THERMODYNAMICS IN COMBUSTION 191
11.8. 燃烧化学热力学COMBUSTION AEROTHERMOCHEMISTRY 191

12. 固体热力学THERMODYNAMICS OF SOLIDS / 合金热力学ALLOY THERMODYNAMICS /冶金热力学METALLURGICAL THERMODYNAMICS/ 材料热力学MATERIAL THERMODYNAMICS 191

12.1. 固体热力学THERMODYNAMICS OF SOLIDS 192
12.2. 材料热力学THERMODYNAMICS OF MATERIALS 192
12.2.1. 中文Chinese 192
12.2.2. 英文English 193
12.2.3. 德文German 195
12.2.4. 法文French 195
12.2.5. 日文Japanese 195
12.3. 材料合成热力学THERMODYNAMICS IN MATERIAL SYNTHEZATION 195
12.4. 等离子，金属和电解质的热力学和光学特性THERMODYNAMIC AND OPTICAL PROPERTIES OF PLASMA, METALS, AND DIELECTRICS 196
12.5. 金属热力学THERMODYNAMICS OF METALS 196
12.6. 金属材料热力学THERMODYNAMICS OF METALLIC MATERIALS 196
12.7. 耐火材料热力学THERMODYNAMICS OF REFRACTORY COMPOUNDS 196
12.8. 合金热力学THERMODYNAMICS OF ALLOYS 196
12.9. 冶金热力学METALLURGICAL THERMODYNAMICS 198
12.9.1. 中文Chinese 198
12.9.2. 西文中译Translated to Chinese from Western Languages 199
12.9.3. 俄文中译Translated to Chinese from Russian 199
12.9.4. 英文English 200
12.9.5. 日文Japanese 201
12.9.6. 冶金溶液热力学 Thermodynamics of Metallurgical Solutions 201
12.10. 合金相图及热力学PHASE DIAGRAM OF ALLOYS AND THEIR THERMODYNAMICS 201
12.11. 晶体热力学THERMODYNAMICS OF CRYSTALS 201
12.12. 结晶热力学THERMODYNAMICS OF CRYSTALIZATION 202
12.12.1. 结晶岩热力学Thermodynamics in Crystalline Petrology 202
12.13. 硅酸盐热力学THERMODYNAMICS OF SILICATES 202
12.14. 多组分系统热力学/多组分体系热力学THERMODYNAMICS OF MULTICOMPONENT SYSTEMS / THERMODYNAMICS OF POLYCOMPONENT SYSTEM 203
12.15. 腐蚀热力学THERMODYNAMICS IN CORROSION 203

13. 生态系统热力学 THE ECOSYSTEM AND THERMODYNAMICS 204

13.1. 宏观热力学MACRO THERMODYNAMICS / HIERACHICAL THERMODYNAMICS 204
13.2. 生物热力学 BIOTHERMODYNAMICS/ BIOTHERMODYNAMICS/ BIOLOGICAL THERMODYNAMICS 204
13.3. 生物学中的热力学THERMODYNAMICS IN BIOLOGY 207
13.4. 生物物理热力学BIOPHYSICAL THERMODYNAMICS 207
13.5. 生物化学热力学/生化热力学BIOCHEMICAL THERMODYNAMICS 208
13.6. 生化反应热力学THERMODYNAMICS OF BIOCHEMICAL REACTIONS 208
13.7. 药物热力学THERMODYNAMICS OF PHARMACEUTICALS / DRUG THERMODYNAMICS 208
13.7.1. 制药系统热力学Thermodynamics of pharmaceutical systems 208
13.7.2. 药物吸收热力学Drugreceptor thermodynamics 209
13.8. 生态热力学 ECOSYSTEM/ECOLOGICAL THERMODYNAMICS / ECOTHERMODYNAMICS 209
13.9. 环境热力学ENVIRONMENT THERMODYNAMICS 209

14. 人类活动相关的热力学 HUMAN ACTIVITIES & THERMODYNAMICS 211

14.1. 生命系统热力学THERMODYNAMICS OF LIVING SYSTEMS 211
14.2. 生命与热力学LIFE & THERMODYNAMICS 211
14.3. 生活的热力学机器THERMODYNAMIC MACHINERY OF LIFE 212
14.4. 信息热力学INFORMATION THERMODYNAMICS 212
14.5. 网络热力学NETWORK THERMODYNAMICS 212
14.6. 经济热力学ECONOMICS THERMODYNAMICS / ECOTHERMODYNAMICS 212
14.6.1. 热经济学 Thermoeconomics 213
14.7. 金融热力学THERMODYNAMICS IN FINANCE 214
14.8. 社会热力学SOCIAL THERMODYNAMICS 214
14.9. 宗教热力学THERMODYNAMICS OF RELIGIONS /FAITH / RELIGIOUS THERMODYNAMICS/ DIVINE THERMODYNAMICS /CHRISTIAN THERMODYNAMICS/ CREATIONIST THERMODYNAMICS 214

15. 未分类 UNCATEGORIZED 214

16. 杂志 JOURNALS 215

16.1. 中文 CHINESE 215
16.1.1. 工程热物理学报 215
16.1.2. 热科学学报 215
16.1.3. 热能动力工程 215
16.2. THERMODYNAMICS 215
16.2.1. Advances in thermodynamics 216
16.2.2. Archives of Thermodynamics 216
16.2.3. Bulletin of chemical thermodynamics 216
16.2.4. Bulletin of thermodynamics and thermochemistry 216
16.2.5. Chemical thermodynamics 216
16.2.6. Continuum Mechanics and Thermodynamics 216
16.2.7. Entropie 216
16.2.8. Exergy [electronic resource] : an international journal. 217
16.2.9. Experimental Thermodynamics 217
16.2.10. Fluid Phase Equilibria 217
16.2.11. International journal of applied thermodynamics 217
16.2.12. International Journal of Thermodynamics 217
16.2.13. The Journal of Chemical Thermodynamics 217
16.2.14. Journal of human thermodynamics 218
16.2.15. Journal of Non Equilibrium Thermodynamics 218
16.2.16. Journal of Thermodynamics 218
16.2.17. MONOGRAPHS IN STATISTICAL PHYSICS AND THERMODYNAMICS 218
16.2.18. The Open Thermodynamics Journal 218
16.2.19. Problems of low temperature physics and thermodynamics 218
16.2.20. Studies in modern thermodynamics 219
16.2.21. Thermodynamics Research Today 219
16.2.22. THERMOCHIMICA ACTA 219
16.3. THERMAL SCIENCE 219
16.3.1. 实验热流体科学（Experimental Thermal and Fluid Science） 219
16.3.2. INTERNATIONAL JOURNAL OF THERMOPHYSICS 219
16.3.3. Journal of thermal science : international journal of thermal and fluid sciences 220
16.3.4. Journal of thermophysics and heat transfer 220
16.3.5. Thermal science [electronic resource] 220
16.4. 其他 220
16.4.1. International Journal of Heat and Fluid Flow 220
16.4.2. W?rme und Stoffübertragung 220
16.4.3. Pyrodynamics 220

17. 热力学文选、文集，文献THERMODYNAMICS LITERATURE INDEX/COLLECTION 222

18. 热力学术语，词汇，词典，辞典，标准，单位等THERMODYNAMICS TERMS, TERMINOLOGY, GLOSSARY, DICTIONARY, ENCYCLOPAEDIA, STANDARDS, UNITS 223

19. 热力学评述THERMODYNAMICS REVIEW 225

20. THERMODYNAMICS PROPERTIES 226

20.1. THERMODYNAMICS SOFTWARE 226
20.2. 热力学 数据库THERMODYNAMICS DATABASE 226
20.3. THERMODYNAMICS PROPERTIES HANDBOOKS 228
20.4. THERMODYNAMICS PROPERTIES TABLES 229
20.5. THERMODYNAMIC DIAGRAMS & CHARTS 237
Last update: 2017-02-12


Thermodynamics Researches

1. Why Science?

Why do I plan to return to Universities or institutes for scientific researches?

The main reason of this fundamental change of my life and career is my firm believe that only the acquaintance with science and studies of the Nature can give me some sort of satisfaction and happiness. In my childhood, I have always been thinking about becoming a top scientist and this is still my unrealized dream. I am thirsty to learn everything about the Nature and her principles. All branches of sciences are attracting me – mathematics, physics, chemistry…. When dived into the kingdom of science, I forget all others.

Secondly, I’ve found the industry, commerce and politics all full of crimes, evils, lies and injustice, and I hate all these, therefore, after so many years there, I want to keep myself distant away from them and concentrate myself on pure scientific researches.

Thirdly, my personality is very fit for scientific researches. Although working in the industry and business over the last two decades, I am still maintaining my habit to learn new sciences every day without interruption. My reading and study capability is unique. Each day I might read more than 100 pages of books of various kinds. I am able to read papers in English, German and French and I am still improving my Russian. Over the next years, I plant to learn one or two languages every year.

And lastly, I should have been a top scientist if I have accepted the PH.D studies I won from several European and N. American universities such as University of Glasgow (gas turbine combustion), University of Paris (surface chemistry), Laval University, and universities of Germany and other countries during 1991-1992 shortly after graduation as a master of science. I was unable to attend these universities because of private reasons Further in 1996, I was nearly admitted by Harvard to pursue a MPA when my former boss told me that the job at Alstom was more than worth a Harvard MPA, a wrong judgment of course. Otherwise I might be engaged in US politics now, possibly will be running for the highest public administrative post now – the US Presidency. But now, neither a president job nor a business tycoon title can attract me, except a name in the science.

2. Why Thermodynamics?

Why have I chosen Thermodynamics as my research subject?

It is a purely random choice, because whatever I will select as my research subject, I will devote the same energy and with the same determination towards a success, i.e. whether or not there will be good results or not, does not much depend on the areas I am planning to work on. The only key issue is my determination.

However, choosing Thermodynamics might shorten the time for the preparation for entry into the academic communities, as this is the area where I have known relatively well since my graduate study, when I have pursued a master’s degree in Thermophsics, which also included Thermodynamics – the others included heat transfer, fluid flow, combustion and radiation. Thus I can save upto 2 years for further indepth studies, compared to a selection of a untapped area such as biomedicine or nano-manufacturing.

Another consideration is the concern about possible failure that eventually no university, no institute, in one word, no one would admit you into their academic circle so that I have to carry my research “solo”. In this case, I have to laboratories to work at for some experiments or observations, I would have little chance to read the books and papers because of the non-access to these resources. Therefore only theoretical studies and strategic thinking can help me overcome the shortcomings aforementioned. At lease during the first years when my researches could not be witnessed by others.

Earlier, I have spent more than a year to study solar radiation and radiation measurement. This is also a large subject and has been researched intensively. The problem like thermodynamics, it involves a lot of measurement technologies and therefore at the current stage, I am unable to carry out any practical researches without the delicate instruments. People are launching satellites worth many hundreds millions of Dollars to observe the Sun radiation and to measure its rays. I can’t sit quietly at home in order to get all the measurements done.

The last factor in choosing Thermodynamics is the belief that it is a science with universal applicability and long lasting effectiveness as Albert Einstein put it:

A theory is the more impressive the greater the simplicity of its premises is, the more different kinds of things it relates, and more extended is its areas of applicability. Therefore, the deep impression, which classical thermodynamics made upon me. It is the only physical theory of universal content concerning which I am convinced that, within the framework of applicability of its concepts, it will never be overthrown.

3. How am I Prepared?

Frankly speaking, I am not yet prepared for an indepth research of the thermodynamics.

I have completed my master degree about 20 years ago. While at University, I have studied wide spectra of sciences not just my own major. However, when trying to write a paper on certain topics of thermodynamics, I find myself in severe shortage of basic knowledge of mathematics, physics and other sciences. Therefore I need to enhance my capacity in these areas and this study will continue for all my career period. Mathematics is of particular importance in scientific research, therefore this will be one of my key areas of studies.

Nevertheless, the basic foundation of knowledge building is completed. And recently I have also carried out a preliminary research of the overall status of the Thermodynamics science, resulting in a comprehensive list of literatures arranged in the order of its their corresponding branches. It was easy to find out that one cannot tackle all these branches as his/her research areas. Careful considerations shall be given to final decision as to which area will be my target research subject.

Therefore, over the next months (about 6 to 9 months), I will read related papers and books about all these subbranch thermodynamics, in order to gain an insight into the general picture of the current Thermodynamic development. Of course I can’t read all these books and articles amounting to millions of pages. My aim is to screen through all these branches, get am impression, and finally to find out one or two focal areas that is worth my lifetime research and is of long time development trends. I will choose these areas which are of key importance to the Thermodynamics science and which are also of major impact on human development.

One of the major obstacles for entering the academic circles is my lack of records in scientific researches. That is not because of my inability to conduct researches, rather the absence of chance to work in the academic world. Since graduation, my career has been shifting between various industries and functions, however, ironically I was never employed by a research institution except the Guangdong Electric Power Design Institute, which is not a research organization in its true meaning. As such, I don’t have any paper to show possible employers, not talking about publications on major international magazines, such as Science, EI, Nature etc. However, I have written far more papers and articles than most others – amounting to tens of thousands of pages delivered to my clients in the solar and general power industries and several other industries. I don’t doubt about my ability to write first class articles. Of course, scientific papers and business reports are fairly different – both in their formats and contents. I know how to turn my style to the right path.

Let me first talk about

4. My General Plan

1) When I have decided to carry out thermodynamic studies, my first impetus is to understand thermodynamic science in its entirety, incl. all its branches, and at the same time. I shall know all major development, and all major research achievements of thermodynamics now and over the past decades. Simply put, I want to know everything about thermodynamics, that’s why I have first prepared a comprehensive list of thermodynamics literature available (which will be updated from time to time) as a first guide to my studies. I have also collected thousands of papers and articles in different parts of Thermodynamics arranged in the same order as the literature index, so that all my future research can be carried out these bases.

2) Carry out special research on some selected topics of thermodynamics. Likely areas of studies might be solar plasma thermodynamics, combustion related thermodynamics, MHD thermodynamic behavior, thermodynamics of small and microstructures etc. Final decision can only be made after my reading of the information collected in about 6 months.

3) Write several books of thermodynamics in several special fields incl. solar thermodynamics, combustion thermodynamics, solar and cosmos thermodynamics as well as the thermodynamics review books. Details about the writing and research plans see the following chapters.

5. Special Researches

This is the first priority of my plan and shall be executed in advance.

Thermodynamics virtually involves all areas of human activities, sciences and arts. If one tries to know everything about thermodynamics, then he or she has to learn all scientific and social knowledge and experiences of the human kind since its existence, and this is of course impossible to any person.

Therefore, areas of researches and expertise have to be identified before undertaking any researches in real sense. As the first step, I would suggest to carry our researches of thermodynamics phenomenon related to the solar corona heating mechanism, the solar magnetic fields and its formation. The negative temperature and negative energy thermodynamics, thermodynamics of small systems incl. nanoscale thermodynamics, thermodynamics of porous media and other compact systems related to the aerospace and chip industry. Details have to be identified and researched yet.
However, final decision can only be made within the next 6 months or so after:

  • Overall understanding of the entire thermodynamics and its branches in some details – with reading some of the major books and articles available to me
  • Determining the research orientation over the next two to three decades according to
    • My own research capacity, status of preparation and of course my interests
    • The development trends of the thermodynamics and its problems to be solved
    • Science and social development trends, hot spots and difficult points of the facing the human kind, such as energy crisis, food shortage, environment pollution, poverty and inequity, health etc
    • Other key issues
    • Combustion thermodynamics will be very likely to be the candidate research topic and at first research might be focusing on the thermodynamics of pollution and pollution control of combustion processes of various types, a continuous research of my master thesis of 20 years ago.

I plan to write one to two papers over the next year (Jan.2009 – Jan.2010), at least at their preliminary form.

6. Thermodynamics Review

Over the past years, thermodynamics has been progressing in both the scope of depth and width.

In the scope of width, thermodynamics has already come out of the equilibrium arena and has entered and penetrated into the non-equilibrium, irreversible states and into the related and non-relevant disciplines such as pharmaceuticals, biotics, ecosystems, energy, social sciences, economics, and management theory etc.:

  • expansion into the cosmos that is the universe system, where gravitational and negative energy as well as dark matters may play vital roles
  • extension to the microscopic areas – cellular, molecular, nanoscales, atomic, subatomic areas and their thermodynamic treatment
  • penetration and merging with other areas of sciences - natural sciences, arts, incl economics, politics, culture, religion, biology, geology, astronomy, etc
  • marching towards the non-classic areas incl
    • non-equilibrium
    • irreversible processes

A preliminary survey shows the thermodynamics has already developed to more than a hundred subbranches. Of course not all of them have become independent disciplines. However special titles and books are already written and published in some branches (refer to ThermoLiterature.doc attached). This list does not cover all areas of the thermodynamics, for example the following:

  • The new thermodynamics
  • Modern Thermodynamics
  • Thermodynamics of innovative thinking 思维创新热力学
  • Broad Thermodynamics 广义热力学
  • Nonextensive thermodynamics
  • Supercritical thermodynamics
  • Special- and general-relativistic thermodynamics
  • Gravitational Thermodynamics
  • Still state thermodynamics 寂态热动力学
  • PhantomThermodynamics
  • Thermotechnics
  • 多分形热力学
  • Holographic Thermodynamics
  • Greenhouse Thermodynamics
  • Fuel Thermodynamics
  • Solar thermodynamics
  • Solar radiation thermodynamics
  • Fuelcell Thermodynamics
  • Combustion thermodynamics
  • Applied Mineralogical Thermodynamics
  • Steam Thermodynamics
  • Thermodynamics of the human brain
  • IT thermodynamics
  • Thermodynamics of Productivity
  • Thermodynamics in investment & properties management投资理财热力学
  • Thermodynamics in trade贸易热力学
  • Thermodynamics of business administration and management 工商管理热力学
  • Thermodynamics of the Wealthy / Thermodynamics of the rich富人热力学
  • Thermodynamics in quality management/thermodynamics of quality质量管理热力学
  • Thermodynamics in Politics / Political Thermodynamics 政治热力学
  • Materialist thermodynamics
  • Theological Thermodynamics/Theology of Thermodynamics/Thermodynamics and Theology神学热力学
  • Bible and Thermodynamics/ Bible Thermodynamics/ Biblic Thermodynamics圣经热力学
  • Thermodynamics in Literatures文学热力学
  • Thermodynamics in Arts艺术热力学
  • Language thermodynamics语言热力学
  • Thermodynamics of love 爱情热力学
  • Kingdom Thermodynamics王国热力学
  • Thermodynamics in history历史热力学
  • Thermodynamics in Ancient China中国古代热力学
  • Sex and Thermodynamics
  • Entropic meteorology 熵气象学

Thus it is easy to see how wide and deep the thermodynamics has already expanded in other areas.

Therefore it is necessary to understand the current status of the thermodynamics system. Is it necessary to have so many subbranches? Or it is better to maintain a limited number of independent disciplines while the majority appears like the application of the thermodynamic principles to those areas.

Nevertheless, it is necessary to summarize what is achieved in the thermodynamics - its knowledge, theory and experiences, and to present the summarization in form of an encyclopaedia, which shall collect all the thermodynamics as detailed above.

This review will also study the correctness of the categorization of the current thermodynamics system, if necessary make some correction. And its main objective is to provide keynote introductions to the individual branches, its recent status of researches and progress, the main obstacles and problems unsolved, the research and development trends and forecasts, and the key scientists in brief.

This review might not be scheduled for the near term task, it will be rather a continuous effort to follow up the general development of thermodynamics and it will be presented to the audience only when it is mature to hand it out to the thermodynamic communities either as printout or e-media.

7. Solar Thermodynamics（2008-2010）

The sun is the primary, if not the only, energy sources of our earth. Utilizing solar energy to solve our many energy problems is one of the main means - of course not the only one. Over the past years, efforts have been made to understand various kinds of solar energy incl solar photovoltaics, solar heating etc. Over the past two years attention has been shifted to solar radiation theory as well as solar radiation measurement and solar physics, particularly solar models. Since 1960's, solar models are well developed, which can fairly correctly explain various sun phenomenon and physical parameters such as temperature, pressure, density, metal abundance, and over the last couple of years, observation, detection, measurement and studies of neutrinos have also proven the solar models.

Nevertheless, neither the solar models nor the solar physics do not touch the solar thermodynamics. The solar modelists concern more about the few basic equations of state, while the solar physicists care about the sun activities only, and now even the generation and activities of the solar magnetic fields and the solar corona heating mechanism are not yet rightly described.

Therefore it is necessary to observe and study the thermal physical phenomenon of the solar internal and surface from the thermodynamics aspects, incl. its thermodynamic state, thermodynamic functions and relations, and to explain the solar magnetic fields and solar corona heating with thermodynamic theory.

In addition, the solar thermodynamics shall be extended to the cosmos and planets, because over there, the classic theories are no more working, even the entire classic thermodynamics might be overturned. For example, there might predominate the entropy decrease law in the cosmos, while temperature is in most cases negative, because there are sound proves that there exists large amount of dark or negative energy as well as dark and negative matters in the universe, thus the classic thermodynamics will surely be unable to function. All these problems needs to be studied.

8. Combustion Thermodynamics （2008-2010）

Combustion is a phenomenon and process with tight connections with human life and work, and we have to face it every day, therefore it is never over-emphasized to point out its importance. Nevertheless, at the moment, there is still no book specially devoted to the introduction and description of the thermodynamic process of the combustion, either here in China or abroad. The only things we can find are some short introduction in the combustion literatures or books, and even these are not purely combustion thermodynamics - rather they are of form of chemical thermodynamics. In one word, this part of discipline is simply ignored.

Therefore I plan to write the <Combustion thermodynamics>, which shall apply all thermodynamic theories incl. the classic or Clausius thermodynamics, the equilibrium thermodynamics, the non-equilibrium thermodynamics, the reversible and irreversible thermodynamics as well as those developed over the last decades to the combustion phenomenon and process, with various fuels and combustion technologies (diffusion, premixed, explosive etc), under differing combustion and firing (normal, fire, forest fire etc). And at last, the combustion thermodynamics shall become a mature and independent discipline.

The book shall be devoted to Prof. Zhang Hesheng, my graduate mentor at Tongji University (1986-1989).

最后更新 Last update: 2008-12-10


Thermodynamics Research Program

Dear Sir or Madam:

My name is Chen Minghua, 46, male Chinese, a postgraduate of thermophysics from Tongji University, Shanghai, China in June 1989. I write you this email in order to seek an opportunity to conduct my research and writing program of solar thermodynamics at your institution.

I have a diversified career path in various industries and roles – refer to my resume (Resume.doc) attached. And now I have decided to reenter the academic world after many years in the industry and business (see Background.doc for my reasoning) and I am now already to execute my thermodynamic research plan – see the plan document (Researches.doc). My aim is to establish a comprehensive Solar Thermodynamics, starting from the thermodynamics of the solar corona heating ?and thermodynamics of solar PV plant in the near terms (2009-2011). The goal of this research and study is to explore possibility to explain relevant thermodynamics phenomenon involved in the entire solar process – from the sun events down to the solar energy use on the earth. Details see the attached document, or other backing information I will compile in the future.

In addition, I am also interested in the overall development of the thermodynamics science, for that purpose, I have compiled a literature index (in its primitive form) of that science – see ThermoLiterature.doc. Based on this I will further detail the scope and indepth of the studies of thermodynamics, in order to compile a comprehensive review of the thermodynamics science in the medium term.

My secondary research subject is cryptography, out of my need to combat the government censoring and filtering of Internet.

My another interest is my long-time hobby for foreign languages, apart from English – almost my working language, German, and French (reading capacity), I am also competent to some degree in Russian, and some knowledge in Latin, Greek and Hebrew. I will continue to improve these languages and in the near future, will add Spanish, Arabic and Japanese to my language menu. And then stop.

I still stay in China mainly because I want to take care of my parents at their old ages but now the situation of China and particularly my own situation is so bad that I can’t do so any longer. It’s becoming an unlivable country now, with the authoritative regime controlling the people and media stricter and stricter. The only option is to quit that damned place. More information about the reasons why I want to leave China refer to Reason.doc provided at the link.

Now, I would like also to remind you that although I am at my mid-40, I am still young – look young, think young, study, work and live like a young student 20 years ago. I have not changed my life style ever since I left the universities, unlike other mid-aged.

I hope my research program will invoke your interests.

Sincerely yours

Chen Minghua
Hangzhou
China
Tel: 0571-8169-1576
Websites: http://groups.google.com/group/helioslab (main entry),
Others: http://www.helioslab.org/, http://helioslab.org/,? http://helioslab.byethost22.com, http://helioslab.gofreeserve.com/

October 17, 2016
Attachments:
The attachments are to be found at the following link https://sites.google.com/site/helioslab/yesterday, which includes the following documents:
1) Background information – Background.doc,
2) Thermodynamics research plan draft - Researches.doc,
3) Thermodynamics literature - ThermoLiterature.doc,
4) Resume, Resume.doc ?
5) Reason for leaving China, Reason.doc
6) Past Competence - Past_Private.doc
7) Past Researches and Studies - Past_Studies.doc
8) Past Business - Past_Business.doc

Dear Prof.,

I am writing this letter to talk about a Research on NanoThermodynamics at your group or for your considering my funding applications for my researches on NanoThermodynamics at your Fund.

My research will focuses on NanoThermodynamics.

My question remains what can thermodynamics do for the nanoscience and how new theories shall be developed to adapt to the new dimension.

I am also n writing the book titled “NanoThermodynamics – a Comprehensive Review”.

This book will summarize all thermodynamic topics related to the nano-technologies, mainly in three areas – nanoscale thermodynamics, thermodynamics of nano-materials and thermodynamics of nano-technologies. They can further be subdivided into many sections, for example (incmplete)

  1. Hill’s nanothermodynamics
  2. Tsallis thermodynamics
  3. Thermodynamics of Nano / Nanosize -systems
  4. Thermodynamics of Nano-Processes
  5. Thermodynamics of Nanomanufacturing / Nanofabrication
  6. Thermodynamics of Nano-engineering
  7. Thermodynamics of Nanomeasurements
  8. Thermodynamics of Nano scale characterization
  9. Thermodynamics of Nano-Phases
  10. Thermodynamics of Nanoelectronics
  11. Thermodynamics of Nanobiotechnology
  12. Thermodynamics of Nano Tools
  13. Thermodynamics of nanocanonical constraints
  14. Thermodynamics of nanoclays
  15. Thermodynamics of Nanodots
  16. Thermodynamics of Nanostructures
  17. Thermodynamics of Nano-materials
  18. Thermodynamics of Nano-Porous Materials
  19. Thermodynamics of Nanocrystals / Nanocrystalline materials
  20. Thermodynamics of nanocomposites
  21. Thermodynamics of Nanoparticles
  22. Thermodynamics of nanofibres
  23. Thermodynamics of Nanodroplets
  24. Thermodynamics of Nano-fluids
  25. Thermodynamics of Nano-Products
  26. Thermodynamics of Nano-components
  27. Thermodynamics of Nanodevices

Etc.

The book will describe each of these topic in full details: basic theory, research and application status. Key scientists, main problems, further research plans, problems.

I am planning to complete the writing of this book in two years.

I am not going to pursue a PhD or post-doc nor any specific academic titles. Instead I want to directly start my research without the needs of these programs.

For more details please refer to my research plans to be sent to you on demand.

Thank you very much for your kind consideration, your patience in reading this letter and I remain

Yours sincerely,

Chen Minghua
Shanghai, China
Supporting documents will be sent to you upon requests.

Thermodynamics research career

Dear Sir or Madam:

I write you this email in order to seek an appropriate job at your institution to conduct my research and writing program of thermodynamics.

My name is Chen Minghua, 45, male Chinese, a postgraduate of thermophysics from Tongji University, Shanghai, China in June 1989.

I have a diversified career path in various industries and roles – refer to my resume (Resume.doc) attached. And now I am executing my thermodynamic research plan – see the plan document (Researches.doc). My aim is to establish a comprehensive Thermodynamics of the Universe, starting from the thermodynamics of solar corona heating mechanism and solar wind acceleration mechanism in the near terms (2009-2011). The goal of this research and study is to explore possibility to explain the creation, evolution and development of the Universe with thermodynamics theory and to complement its theories with new findings, incl. the explanation of solar corona heating as an example. Details see the attached document, or other backing information I will compile in the future.

I hope my research program will invoke your interests.

Sincerely yours,

Chen Minghua
Hangzhou
China
Tel: 0571-8169-1576

2008-12-24
Attachments:
The attachments are packed in the Attachments.rar file, which includes the following:
1) Thermodynamics research plan draft - Researches.doc,
2) Thermodynamics literature - ThermoLiterature.doc,
3) Resume, ?Resume.doc

热力学研究与著述

经过多年的摸索和尝试，我决定将我的业务以及研究方向都转回到我的老本行-热物理。我决定选择其中的热力学作为今后的研究和业务方向,包括对热力学学科体系的全面总结和回顾，撰写几部专著，包括太阳热力学，以及燃烧热力学，可能还有更多，就某些专题进行研究。有关计划的细节见附件– 热力学计划 ThermoPlan.doc。

目前，我初步将热力学的分支学科了解的结果汇集成文。除了工程热力学，化学与化工热力学，材料热力学，气动热力学，热力学与统计物理，统计热力学，非平衡态热力学，不可逆热力学和其他少数以外，极大多数还没有专著（也包括相应类别的热力学）。但总的来讲，热力学已经渗透到各个学科和行业，而不再局限在工程和技术领域。热力学向不可逆非平衡，向宏观和微观领域，向社会和经济领域，向人类一切活动范围扩展，从抽象，又向具体扩展。 有关热力学分支学科及相应的出版物的情况见文件ThermoLiterature.doc.


Fluiddynamics

(2010)

I cannot remember clearly how did I come to fluiddynamics. Of course it is one of the four key subjects of thermophysics - my major course of early days at university. My two key foci were CFD and nano fluidics or nano fluid dynamics.

Here below are shown a fraction (1/5 to 1/50 depending on which branch is related) of papers and books survived, that I have perused before.

Additional Explanations for CFD Researches & Designs.doc
FluidNeoFluidsServices.doc
Fluiddynamics.doc

<DIR> cn

流体力学.pdf
流体力学下册-朗道.pdf
第一章绪论X.pdf
第七章粘性运动.pdf
第三章运动学X.pdf
第二章静力学x.pdf
第五章势流.pdf
第四章动力学X.pdf
计算流体力学基础(苏铭德 清华大学).pdf
计算流体力学的理论、方法及应用.pdf
计算流体力学讲义.pdf
计算流体动力学分析-CFD软件原理与应用.pdf

<DIR> de

BrückerZZZ Str?mungsmechanik II_Skript_2007 p178.pdf
Fluiddynamik für das Masterstudium.pdf
Fluiddynamik von Gas-Fl?ussigkeits-Gemischen.pdf
NovikovFluiddynamik.pdf
Numerische Methoden.pdf
StroblZZZ Mikro- und Nanofluidik auf piezoelektrischen Substraten p157.pdf
stroemungslehre3.pdf
Stromungslehre-skript.pdf
TheorStromungslehre_Wieghardt_book.pdf

<DIR> EN

000Fluid Dynamics Physical ideas_good.pdf
000fluid_mech_module_good.pdf
000Fundamentals of Compressible Fluid_Good.pdf
000Fundamentals of Compressible_Good.pdf
000INTERMEDIATE FLUID MECHANICS_Good.pdf
000Lagrangian Fluid Dynamics3_Good.pdf
000luidLecture_Good.pdf
000Unsolved Problems in Fluid Mechanics_Good.pdf
ADVANCED FLUID MECHANICSX.pdf
AppliedFluidMechanicsX.pdf
BarMeirZZZ Basics of Fluid Mechanics 2010 p292.pdf
Compressible_Flow_Course_1X.pdf
Comp_Fluid_DynamicsX.pdf
Fluid mechanicistX.pdf
Fluid Mechanics from the BeginningX.pdf
FLUID MECHANICS lecture_notes_03X.pdf
Fluid Mechanics Stokes Law and ViscosityX.pdf
Fluid Mechanics3X.pdf
Fluid mechanicsX.pdf
FluidMechanics2X.pdf
FluidMechanics5X.pdf
FluidMechanicsX.pdf
FluidMechSlidesX.pdf
fluid_mechanicsX.pdf
Fluid_Mechanics_II_PDFX.pdf
Introduction to Computational Fluiddynamics_good.pdf
Introduction to Engineering Fluid MechanicsX.pdf
Introduction to Fluid Mechanics6X.pdf
Jeff Direct numerical simulation of turbulent chemically reacting flows p119.pdf
KreithZZZ Fluid Mechanics p209.pdf
lagrangian fluid dynamicsX.pdf
Lantos Advanced Numerical Methods for Option Pricing p126.pdf
Lomax Fundamentals of Computational Fluid Dynamics p275.pdf
Mathematical and Geophysical Fluid DynamicsX.pdf
Mathematical Fluid DynamicsX.pdf
McDonough COMPUTATIONAL FLUID DYNAMICS of INCOMPRESSIBLE FLOW p155.pdf
Methods for Numerical Flow Simulation.pdf
Modular Bases for Fluid DynamicsX.pdf
Moser Direct Numerical Simulation of Curved Turbulent Channel Flow p170.pdf
Non-Newtonian Fluid Mechanics Using Molecular TheoryX.pdf
Patankar-NHTFF-1980 p205.pdf
Rojas, An Introduction to Computational Fluid Dynamics p133.pdf
SANTOS Numerical methods for fluid-structure interaction problems with valves p204.pdf
SG2214 Fluid Mechanics_GoodX.pdf
Wei Direct Numerical Simulation p215.pdf
Wesseling ELEMENTS OF Computational fluid dynamics p147.pdf
xComputational Fluid Dynamics (CFD).pdf
xComputational Fluid Dynamics with OpenFOAM_Good.pdf
xComputational Fluid Dynamics_Good.pdf
xLattice-Boltzmann_Good.pdf

<DIR> fr

000luid_mechanics_goodX.pdf
000MECANIQUE DES FLUIDES APPROFONDIE.pdf
000Mecanique des fluides geophysiques VERSION PRELIMINAIRE.pdf
000Mecanique des Fluides66.pdf
000Mecanique des Fluides8.pdf
000Mécanique des fluides 1ère partie.ppt
000Mécanique des fluides appliquée.pdf
000Mécanique des fluides géophysiques.pdf
000Mécanique des fluides.pdf
000Mécanique des fluides3.pdf
000Mécanique des Fluides8.pdf
Analyse mathematique et numerique de la dynamique des fluides compressibles.pdf
DYNAMIQUE DES FLUIDES PARFAITS.pdf
Mecanique des Fluides parfaitsX.pdf
Mecanique des fluides Statique et cinematiqueX.pdf
Methodes numeriques pour la dynamique des fluides.pdf
Mécanique des fluides polycop_physX.pdf
rey_mechanique fluide turbines et compresseurs p79.pdf
xInitiation a la Simulation Numerique en Mecanique des Fluides a l'Aide de CASTEM2000.pdf
xInitiation a la simulation numerique en mecanique des fluides.pdf
xMecanique des Fluides Numerique sur GPU.pdf
xMecanique des fluides numerique2.pdf
xMécanique des Fluides Numérique.pdf

<DIR> gk

ΒΑΣΙΚΑ ΣΤΟΙΧΕΙΑ ΜΗΧΑΝΙΚΗΣ ΡΕΥΣΤΝ.pdf
ΕΞΕΤΑΣΕΙΣ ΣΤΗΝ ΜΗΧΑΝΙΚΗ ΡΕΥΣΤΩΝ.pdf
ΜΗΧΑΝΙΚΗ ΡΕΥΣΤΩΝ ΑΣΚΗΣΕΙΣ.pdf
Ρευστοδυναμικ?.doc

<DIR> ru

<DIR> nanofluidcs

NanoFluidDynamicsIntro.doc
NanoFluidDynamicsIntro.pdf
NanoFluidDynamicsIntro1.doc
NanoFluidDynamicsIntro1.pdf
NanoFluidicsBooks.doc
NanoFluidicsBooks.pdf
NanoFluidicsIntro.doc
NanoFluidicsIntro.pdf
NanoFluidicsIntro1.doc
NanoFluidicsIntro1.pdf
NanoFluidicsIntro2.doc
NanoFluidicsIntro2.pdf
NanoFluidicsResearchers.doc
NanoFluidicsResearchers.pdf
NanoFluidicsResources.doc
NanoFluidicsResources.pdf
NanoFluidicsTerms.doc
NanoFluidicsTerms.pdf
NanoFluidicsTransport.doc
NanoFluidicsTransport.pdf
NanoFluidicsTransport1.doc
NanoFluidicsTransport1.pdf

3D structures nanofluidicsXXX.pdf
COMPUTING THE NEAR-WALL REGION IN GAS MICRO-AND NANOFLUIDICS.pdf
Experimental Nanofluidics.pdf
Fabrication Nanofluidics Device.pdf
Fabrication of single nanofluidic channels.pdf
Focusing microparticles in a microfluidic channel.pdf
Fundamental Understanding of Nanofluidics.pdf
Gradient nanostructures nanofluidics.pdf
High-Frequency Nanofluidics.pdf
KEY NANOFLUIDICS PATENT.pdf
Kornev lab.pdf
Micro-Nano-fluidics challenges of fluid mechanics.pdf
microandnanofluidicdevices.pdf
Microfluidic drifting.pdf
Micronanofluidics and Lab-on-a-Chip.pdf
Nanofibers, nanofluidics, nanoparticles and nanobots.pdf
nanofluidbioX.pdf
Nanofluidic Systems.pdf
Nanofluidic tuning.pdf
nanofluidics DNA analysis.pdf
Nanofluidics in carbon nanotubes.pdf
Nanofluidics in the Debye Layer.pdf
Nanofluidics.pdf
NanofluidicsX.pdf
nanofluidics_webX.pdf
nanoplasmonic-nanofluidic biosensors.pdf
NanoWetting.pdf
RFLUID DYNAMICS XXX.pdf
robio2005-chinese-cfpXXX.pdf
RSC Nanoscience & Nanotechnology.pdf
Streaming Currents in a Single Nanofluidic Channel.pdf
Streaming Currents Nanofluidic Channel.pdf
Sub-wavelength nanofluidics in photonic crystal sensors.pdf
Targeting Transport Properties in Nanofluidics.pdf
Technologies for nanofluidic systems.pdf
Transport phenomena in nanofluidics.pdf
Wetting Phenomena.pdf

<DIR> Yachts

Autodesk Inventor杰玛游艇集团XXX.pdf
Better Yacht Design_GOODXXX.pdf
CouplingOfAeroandHydrodynamicsFinal2_GOODXXX.pdf
Development of a computer modelXXX.pdf
Dictionary of Ship Hydrodynamics.pdf
Hydrodynamic Modeling of Sailing Yachts_GOODXXX.pdf
Hydrodynamic PerformanceXXX.pdf
Maritime Hydrodynamics Research LaboratoryXXX.pdf
Modelling and Numerical Simulation for Yacht Engineering_GOODXXX.pdf
MOTOR YACHT HULL FORM DESIGN FOR THE DISPLACEMENTXXX.pdf
Sailing Vessel Dynamics_GOODXXX.pdf
Yacht Design & Technology1XXX.ppt
Yacht Design & TechnologyXXX.ppt

Problems

How to explain turbulent flow in molecular science?
用社么参数来判断湍流出现？怎样定量Re数与湍流的关系 （湍流度与Re数的关系）？

当黏度等于零时（无粘性流）Re 数无穷大，是否一定湍流？

How is eddy formed?

Unsolved Problems in Fluid Mechanics:
On the Historical Misconception of Fluid Velocity as Mass Motion, Rather than Volume Motion
Howard Brenner
Department of Chemical Engineering
Massachusetts Institute of Technology
Cambridge, MA 02139
hbrenner@mit.edu

Fluid Technologies Services
I've once tried to provide (on bahalf of a certain company name, possibly NeoFluid):

various design and consulting services incl Computational Fluid Dynamic (CFD) design, simulation and optimization of various fluid products and systems and also conducted market intelligence services for international clients.

CFD (Computational Fluid Dynamics) Designs & Services

We perform highly sophisticated CFD (Computational Fluid Dynamics) designs for aerodynamics and hydrodynamics machineries and systems (such as turbines, pumps, compressors, pressure vessels, ships, buildings, canals and pipes). We have extensive experience and capabilities in CFD simulations of complex engineered and natural systems.

Our consultants are a well-rounded and senior level group consisting with several decades of CFD modeling experience of CFD & FEA consulting analysts, CFD modeling specialists, experts in CAD and mesh generation, technical experts, Masters of Science and PhDs, leading software developers etc. They come from the academia (universities, institutions and laboratories), air-conditioning, automobile engineering, aviation and aerospace, chemicals, energy technologies, fluid machines, petroleum, private industry, refrigerating and shipbuilding and other industries.

We can offer you custom solutions to non-standard problems thanks to our many years of experience and our own intensive development efforts in the field of complex CFD tasks. Our staff members also have expertise in CFD code modification, and algorithm development to address specific client needs. We can perform all of the steps of the complex CFD workflow. We can also offer you product & process innovation engineering & construction plant optimization consulting & services.

We gained its CFD expertise across various applications by conducting cost-effective design studies to solve the industry specific full spectrum simulations. Our experienced CFD professionals will work with customers on a one-on-one basis in solving the CFD problem and providing with the analysis report detailing the study and discussing the results. We provide model templates to automate and streamline your CFD process so that you will have a full control over your end product in a shorter time.

Our CFD services include

  • Specialist consultation
  • Project consultation
  • R&D projects of fluid engineering
  • In-house engineering services
  • Process simulation and design
  • Process optimization:
  • Full process analysis, simulation and recommendations
  • Product redesign
  • Thermodynamic cycle analysis
  • Design optimization
  • Equipment design optimization:
  • Computer CFD modeling & analysis
  • On-site program support
  • FEA field
  • Subcontracting of numerical simulation
  • Software technical support
  • Software sales
  • Fluid flow and heat transfer analysis
  • Conjugate heat and flow analysis with multimode heat transfer and phase change
  • Integrated flow and thermal analysis of engineered and natural systems with interface modeling
  • Model development
  • Data analysis and interpretation

The above CFD design and simulations can be applied to all processes and flows, such as:

  • 3-D fluid field analysis
  • Aerodynamics
  • Chemical reaction flows
  • Combustion
  • Compressible flow
  • Discrete phase flow
  • External flow problems of complex structures
  • Fire dynamics simulation
  • Free surface flow
  • Heat fluid systems
  • Heat transfer
  • Hydrodynamics / river hydraulics and open channel flow
  • Incompressible flow
  • Macro-, meso- and micromixing effects
  • Micro-fluidics
  • Multi-phase and multi-component flow
  • Nano and mesoscopic flow
  • Non-Newtonian flow
  • Particulate and droplet flow simulation
  • Porous media flow
  • Post processing services
  • Radiation,
  • Rheological modeling for non- Newtonian fluids
  • Sedimentation simulation
  • Solid-liquid integration simulation
  • Steady-state / transient / unsteady flow analysis
  • Turbulent fluid flow / mixing and modeling / evaluation
  • Viscous flow
  • Visualization

Our services covers a variety of areas, incl. but not limited to the following industries and sectors:

  • Automobile
  • Aviation and Aerospace
  • Biomedical ??
  • Boilers of various types
  • Buildings
  • Chemical, petrochemical, material, environmental, biochemical, transportation, and other industries ??
  • Civil Construction
  • Coal and Mines
  • Coal combustion processes
  • Combined generation systems for cooling, heat and power
  • Combustion systems incl ovens and furnaces
  • Distributed energy and power systems
  • Electronics
  • Energy and Power
  • Energy storage systems
  • Engines and systems
  • Environment
  • Fans and blowers
  • Flue gas desulfurization and denitrixation systems
  • Food Engineering
  • Heat exchangers
  • Heat pumps
  • House Appliances
  • HVAC (refrigerating and air-conditioning systems)
  • Hydraulic Projects
  • Instruments and Meters
  • Management Information Systems & GIS
  • Material Processing
  • Metallurgy
  • Other applications
  • Other new energy and renewable energy - incl. direct hydrogen generation from carbon-content materials
  • Petroleum and Petrochemical
  • Power plants (steam turbine gensets, gas turbine gensets, combined cycles etc)
  • Pulp and Paper
  • Residue heat recovery systems
  • Ships, Shipbuilding, Marine, Submarine, Ocean Engineering
  • Solar heating – hot water systems, heat pumps, solar-heat pump floor radiation heating, direct expansion solar heat pump collectors, solar hot gas power systems, high concentration solar power systems, solar chimney power, solar how air power etc
  • Solar photovoltaic systems and equipments
  • Waste heat disposal

And also the

FluidTechChina reports

Apart from CFD related services, we also provide a range of consulting services of the fluid technologies, incl. but not limited to the following:

First of all, we’ve been preparing and delivering the FluidChina monthly reports in English to international fluid industry since 2005, a report about the flow rate and flow meter industry in China.

Another report, called FluidTechChina, reports in the areas of all fluid technologies and products incl.
turbines,
Hydro-turbines incl. reversed hydro-turbines for pumped storage power stations
Steam turbines
Gas turbines
Windturbines
Turbo-chargers
compressors,
pumps,
and
fluid dynamic applications in aircrafts, ships, buildings, vessels and containers, pipes etc.

Separate reports are also available for the following products:

Steam turbines
Gas turbines
Hydroturbines incl. reversible hydroturbines
Windturbines
Turbochargers
Boilers and pressure vessels
Pumps
Compressors
And finally I wanted to offer my

Fluids Technologies Consultation Services

First of all, we’ve been preparing and delivering the FluidChina monthly reports in English to international fluid industry since 2005, a report about the flow rate and flow meter industry in China

This report is a highly comprehensive, yet concise, compilation with researches, analyses, and information with timely insights into trends, events, and activities affecting fluid flow and flow rate measurement technologies and products in China.

The FluidChina Report contains independent and unbiased data, information, interviews and analyses of the fluid measurement technologies market in China on a monthly basis, which is the unique and the only one of such kind available on the market.

The report covers a wide spectrum of topics from research to development, from projects and applications, from government policy to regulations, from market trends to consumer, from the tier-1 cities of Shanghai, Beijing, Guangzhou to smaller cities in the provinces, from the coastal regions down to the heartland of China in the fluid measurement technologies sections. Here we show you some of the possible contents as below (but not necessarily in that scope and order):

Executive Summary
Development Trends
International Benchmarking
Risks
Problems, Challenges & Actions
News & Spotlights
Viewpoints
Policies, Laws, Financing And Incentives
Government & NGO Programs
Codes, Directives, Standards & Specifications
Certification, Licensing & Quality
Academic & Media
People
Organizations
Directories
Company Case Studies
Industrial Parks
Fluid technologies and products researches and development
Fluid technologies and products showcase
Fluid technologies and products producers and providers
Chinese Fluid Technologies and Products In The World
Foreign Fluid technologies and Companies In China
Supply Chain
Regional development
Market Status
Major development projects
Import & Export
Investment
Competition
Merger & Acquisition
IT & Internet for the Fluid industry
Calendar & Events

Our content is sourced from our proprietary, impartial researches with high net-worth consumers on major issues and current events. We also review leading publications, top tier consultants, leading universities and independent researchers, and governmental sources for additional independent materials of value for our readers.?

The report contains 120+ pages of rich information, analyses and insights and all necessary information you need to know about the Chinese fluid measurement technologies, products and market, and with 12 month issues a year and an annual analysis and summary report. In between we may present you additional reports as the case may arise – such as an important event etc.

These reports are customized for international clients in the fluid measurement industry who want to follow the development and enhance their presence here in China.

The reports are written in US English by fluid experts here in China. The main editors have many years experiences in leading multinational power corporations and thus are able to deliver the reposts in standard English and with professional insights.

The reports are delivered to our clients currently in PDF format electronically, to their email boxes.

The reports are delivered at the later half of the month for the last month.

Please check with our engineers for details.

In addition, we also help international fluid measurement technology companies to enter into the Chinese market by providing market studies and intelligence services, as well as local representative. Another of our fluid technology services is the design and engineering of flow measurement projects as well as the Computational Fluid Dynamics (CFD) services for various industrial and commercial applications.

FLUIDDYNAMICS / CFD CAPACITY

WHY CFD RESEARCHES AND WHY NOT IN CHINA???

Fluid Dynamics and related sciences
Numerical theory and techniques
CFD theory and techniques
CFD expertise
CFD consulting
CFD development
CFD related processes and subjects
CFD Related Systems and Equipments
CFD Relevant Industries and Areas of Applications
CFD applications & tools

WHY CFD RESEARCHES AND WHY NOT IN CHINA???

The reason to seek CFD is the fact that it belongs to one of the fundamental science of the thermal physics chapter and I have learned it very intensively over the past and my business over the last couple of years are related to this area.

China’s education and research segments are currently very corrupted, therefore it is impossible to undertake pure researches without the compromise with this system. And the general trends towards decay of the Chinese society does not allow for genuine researches and studies.

Fluid Dynamics and related sciences

  1. Aerodynamics
  2. Combustion, turbulent combustion
  3. Compressible flow
  4. Fluidized Beds
  5. Incompressible flow
  6. Micro/nano -fluidics
  7. Multi-phase and multi-component flow
  8. Non-Newtonian flow, Rheology - Rheological modeling for non- Newtonian fluids
  9. Pneumatic conveyors, bulk granular material handling
  10. Porous media flow
  11. Turbulent fluid flow / mixing and modeling / evaluation

Numerical theory and techniques

  1. Boundary Element Methods (BEM)
  2. Discrete Element Method (DEM)
  3. Direct Numerical Simulations (DNS)
  4. Finite Difference Methods (FDM)
  5. Finite Element Methods (FEM)
  6. Finite Volume Methods (FVM)
  7. Moving Interface Methods (MIM) such as
    1. Sharp Interface Method (SIM)
    2. Level Set Method (LSM)
  8. Probability Density Function (PDF)
  9. Adaptive, unstructured mesh CFD

CFD theory and techniques

  1. Detached Eddy Simulations (DES)
  2. Lattice Boltzmann CFD
  3. Large Eddy Simulation (LES)
  4. Reynolds Averaged Navier Stokes (RANS)
    1. U-RANS
    2. hybrid RANS/LES
  5. Reynolds Stress Model? (RSM) model
    1. Anisotropy-invariant Reynolds Stress Model of turbulence (AIRSM)
  6. Sliding mesh techniques
  7. Smoothed Particle Hydrodynamics (SPH)

CFD expertise

CFD consulting

My duties and responsibilities were/are:

  1. Specialist consultation
  2. Project consultation
  3. Process simulation and design
  4. Process, design, equipment optimization
  5. Thermodynamic cycle analysis
  6. Fluid flow and heat transfer analysis - 3-D fluid field analysis
  7. Software technical support

CFD development

Whereby I was involved in:

  1. Developing numerical algorithms and approaches
  2. Developing and implementing computational fluid dynamics codes
  3. Defining computational requirements
  4. Modeling and simulating various processes
  5. Documenting results
  6. Conducting data analysis and interpretation
  7. Performing post processing & visualization

CFD related processes and subjects

Flow Processes covered:

  1. Chemical reaction flows
  2. Fuel-air mixing processes
  3. Industrial processes
  4. Nucleate boiling
  5. Porous materials
  6. Sustainable energy systems
  7. Thermal flows
  8. Transport phenomena

CFD Related Systems and Equipments

  1. Boilers
  2. Burners
  3. Ducts and pipes
  4. Heat exchangers incl. condensers
  5. Pumps
  6. Steam/hydro turbines
  7. Thermal Energy Storage

CFD Relevant Industries and Areas of Applications

  1. Automobile
  2. Buildings
  3. Electronics
  4. Energy and Power
  5. Environment

CFD applications & tools

CFD applications (solver) such as

  1. Ansys: Ansys Workbench, Ansys CFX
  2. Fluent
  3. NUMECA
  4. OpenFoam
  5. Phoenix
  6. StarCD

CAD Software

  1. Pro/E
  2. solidworks

the most prevalent pre-processors

  1. Gambit
  2. ICEM-CFD

CFD post-processor

  1. EnSight

Letters to the Academia

Dear Prof. XXX:

I am pleased to submit my application documents for the position of “PhD in Fluid-Structure Interaction” at the department of Mechanical Engineering, the XXX University (XXX).

As an enthusiast of computational mathematics and physics, and a long-time engineer of CFD simulation particularly in the power and energy industry, I am interested in your program and the related researches. Here I have collected some documented facts of my CFD related experiences over the past for your reference. Further details may be provided for you upon request.

Here it is to mention that during these years of CFD career, I have also developed and upgraded several existing CFD models specific to the industries and applications.

My weak point is my lack of publication records in this area, mainly due to the lack of chances to write academic paper in the past.

Additional information about my career is also provided, although not directly related to this application but is absolutely worthwhile reading before making any conclusion about my qualifications, as I am not an average applicant for this job.

I strongly recommend you to read the “Wonderfulpast.pdf” file first which tells you why I am applying for a CFD research job at this stage of my life.

In addition, it’s also to mention my multi-lingual capacuty – English has been my working languages since the last two decades and it is close to my mother tongue. Apart from English I am also proficient in German, French, Russian and Greek to some degree, although they are not helpful in CFD stuff, but their studies give me fun and happiness particularly the learning of ancient Greek literature.

I am a Master of Science majoring in thermal physics in engineering with focus on pollution control on combustion.

Thank you for your patience in reading my motivation and explanatory letter and look forward to hearing from you soon.

Sincerely,

Chen Minghua
Hangzhou, P.R. China
P.S.:
(1) if my application is rejected, please be so kind as to give me your reasoning.
(2) I propose you try not to think too much and negatively about my age and instead put more efforts admiring my vast knowledge, experiences, expertise and capacity in CFD and other areas, and imagine me as an young PhD student with excellent learning ability and vividity.
(3) You may choose either one of the languages for communications as you prefer.

Attachments
(1) “ResumeAca_EN.pdf” - CV
(2) Research statement – I need more information to prepare for this document
(3) “Wonderfulpast_EN.pdf” is for your reference only otherwise you may not understand why I shall apply for job with my background – upon request
(4) “ITSkills.pdf” – IT skills mostly acquired before 2004
(5) “Xplains_EN.pdf” - Additional explanations – upon request
(6) “Referrers_EN.pdf” – my referrers upon request when I am short-listed
(7) A copy of the academic transcript will be sent to you only I am short-listed

2010-10-12

Another Inquiry Letter

Dear Prof. XXX,

I am pleased to submit my application documents for the position of “PhD in numerical hemodynamics” at the Australian School of Advanced Medicine (ASAM) at XXX University. ?I am intending to continue my research program after being interrupted more than 20 years ago for various reasons. But I don’t know if you mind my age and my zigzag past.

CFD related background

As early as in my graduate studies time I was already interested in and studied a little about the blood dynamics or hemodynamics in order to find out the causes of headache suffered by my mother. And still today, I am always interested in this subject, and wants to learn the mechanism of blood flow throughout the human body and its many factors and influences to health.

I’ve strong background in fluid mechanics and have demonstrated computational and experimental skills over the past in my work and studies, incl. among other, also high performance computing and parallel numerical simulations. During the last years, I have also been involving in the computational modeling of various industrial and commercial systems, facilities and equipments, as well as complex multiphase flow in various processes and systems.

As an enthusiast of computational science (mathematics, physics etc) I have been following this branch of science ever since my graduation in 1983, in my work as well in my part-time studies as one of my key hobbies and interests. During these years of CFD career, I have developed and upgraded several existing CFD models specific to the industries and applications.

MY CFD-philia is not just centered around fluid mechanics, rather spreads over to other branches of the thermophysics – heat and mass transfer, and combustion.

Details see below and the attached documents.

IT skills
I am familiar with all major IT technologies incl coding, databases etc.

Languages
English has been my working language since the 1991.

Apart from English and German I am also proficient in French, Russian and Greek to some degree.

Education
I am a Master of Engineering majoring in thermal physics in engineering with focus on pollution control on combustion [(bachelor1978-1983) and master’s (1986-1989) degree in thermal engineering]

Career
My career so far can be summarized as below:

2005 up to now:
Self-employed, with cooperation with others and the establishment of my own business docusing on technical and academic learning. Business has been shifted to fluid technology consulting and services incl. CFD design, simulation and optimization for various processes and industries. Academic researches have been also turned to CFD and fluiddynamics with focus on small structures and Non-Newtonian.

2000-2005
Self-employed with cooperation with others and the establishment of my own business. First concentrated on IT services mainly industry portal design and database design and management (2000-2003) . Then solar business, Conventional power, other renewable energy consulting, and information. ?For very short period of time I was also engaged in other discrete businesses such as business aviation, cryptography and thermodynamic consulting. Researches have been changing very tremendously from thermodynamics to cryptography, and solar physics etc.

1983-1986, 1989-1999
Career at major domestic and multinational organizations, corporations and institutions with functions such as procurement, marketing, quality assurance, design, coordination and planning, technical review and evaluation in the conventional power, nuclear power, telecommunications, electronics, and certification industries

Thank you for your patience in reading my motivation and explanatory letter and look forward to hearing from you soon.

Sincerely,

Chen Minghua
Hangzhou, P.R. China
P.S.:
(1) if my application is rejected, please be so kind as to give me your reasoning.
(2) You may choose either one of the languages for communications as you prefer.
(3) Please keep these documents and information confidential

Attachments:
(1) “Resume.pdf” - CV
(2) Research statement – I need more information to prepare for this document
(3) “Referrers_EN.pdf” – provided to you later
(4) Copy of the earlier academic transcript -
(5) Language test scores or testimony : the old TOEFL/GRE/IELTS scores in the early 1990’s.
(6) “Additional.pdf”: highly interesting background information about the reasons of seeking PhD studies, only for those with the sharpest eyes and on request

Additional Information
In addition, we also help international fluid measurement technology companies to enter into the Chinese market by providing market studies and intelligence services, as well as local representative. Another of our fluid technology services is the design and engineering of flow measurement projects.

How could I provide the above services to the world? Just a glimpse of my CFD expertise tell you the truth.
Armed with these capacity, I dared to offer my potentials to a number of academic institutions as well as commercial cooporations, with some elaborate inquiry messages such as those shown here as an example.
2017-02-12


Solar science

Solar Physics and Energy

G:\studies\OtherStudies\00solar\000Solarcraft\Europe

Solar science (2006-2007)

I was first in the solar energy business, especially the solar photovoltaic industry, providing information and consultancy for worldwide solar companies. As a result I was a bit familiar with some of the solar technologies. Later on, I was convinced to do some studies and researches on solar science - first solar radiation, then solar radiation measurement, and gradually continued to solar physics - in particular Solar Models and solar corona heating problems with thermodynamics theory. I was one time also ambitious to comprehend completely the solar powered aviation and light propulsion for spacecrafts. Here below are organized some documents in the above mentioned subject areas.

Solar Physics & Science

Here HeliosLab will present to you basic information about the solar science, incl:

Solar Introduction

Solar physics

I'll probably start with Solar Physics, an area of interesting topics.

Fundamental researches and studies of solar physics, particularly solar thermal physics and solar thermodynamics will be carried out, and research results will be presented here in the years to come in forms of documents or multimedia formats.

Solar Radiation

Basic theory, Sunlight direct use and storage, Software, databases, and online business, R&D, Scientists, Products, Organizations, Academic events, Publications, Special focus will be put on space solar photovoltaic theory and technology. Fundamental theory and practical technologies, with an integration of solar radiation mechanism on solid, liquid and gaseous objects with focus on:

  • Solar radiation measurement Solar radiation and
  • impact on human being, such as ultraviolet radiation protection, sun bathing, etc

Solar Materials

Solar Photovoltaincs

Solar Thermal Technology

Other Solar Technologies and

Solar Aviation & Aerospace

information about the past and existing aircrafts, ballons, blimps,and other air-borne flying objects powered by solar energy, as well as the solar power for space adventure, such as solar ion propulsion by NASA and ESA, and Solar and light sail projects by Russian and US astronauts and a number of interesting readings of science fictions using solar sail or light sail technologies.

Magnetic sail technology is also introduced.

Check these documents for more info:

SolarA2Z/
SolarA2Z_CN.doc
SolarA2Z_EN.doc

SolarHealth/
PhotoagingCN.doc
PhotoagingEN.doc
SolarHealthCN.doc
SolarHealthEN.doc

SolarIntro/
ChinaSolarCellModulesSheets.xls
PVResearch.doc
SolarIntro_CN0.doc
SolarIntro_EN_App1.doc
SolarIntro_EN_Cell1.doc
SolarIntro_EN_Cell2.doc
SolarIntro_EN_Gen1.doc
SolarIntro_EN_Gen2.doc
SolarIntro_EN_Gen3.doc
SolarIntro_EN_Mat1.doc
SolarIntro_EN_ModulesBOS1.doc
SolarIntro_EN_ModulesBOS2.doc
SolarIntro_EN_PowerSys1.doc

SolarOthers/
OthersIntro_CN.doc
OthersIntro_EN.doc
SolarOthersWebresources.doc

SolarPhysics/
SolarPhysics
├000SolarPhysics.doc
├Aerosole.doc
├Bow Shock.doc
├Chromosphere.doc
├columbia_annual_rep.doc
├Convection zone对流层.doc
├Coronal mass ejection日冕物质抛射日地传输时间的数值模拟.doc
├Corona日冕.doc
├Cosmophysics宇宙物理.doc
├Faculae光斑.doc
├Flare耀斑.doc
├Granules米粒组织.doc
├HELIOGRAPH.doc
├Heliopause.doc
├Helioseismology日震.doc
├heliosheath太阳风鞘.doc
├Heliosphere.doc
├ionosphere.doc
├magnetosphere.doc
├Milankovitch cycles.doc
├Moreton Waves.doc
├M区.doc
├Neutrino中微子.doc
├Photosphere光球层.doc
├Polar aurora极光现象.doc
├Radiation Zone辐射层.doc
├Solar core 日核.doc
├Solar flare谱斑.doc
├Solar magnetic field太阳磁场.doc
├solar maximum.doc
├Solar prominences日珥.doc
├Solar proton event太阳高能粒子.doc
├Solar radio burst太阳射电爆发.doc
├<SolarModels>
│ ├Books_SSM0.doc
│ ├Books_SSM0Key.doc
│ ├Books_SSM1A2E.doc
│ ├Books_SSM2F2Z.doc
│ └SSM.doc
├Solarwind太阳风.doc
├Spicules针状体.doc
├Sun Events - Solar phenomena太阳活动.doc
├Sun1.doc
├Sun2.doc
├Sun3.doc
├Sunspots黑子.doc
├Sunstructure构造.doc
├Sun其他.doc
├Sun太阳介绍.doc
├Sun太阳介绍1.doc
├Termination Shock.doc
├Transition region过渡层.doc
├冲浪日浪.doc
├喷焰.doc
├暗条.doc
└针状物.doc

SolarPortals/
PortalSolarChina.doc
PortalSolarDaylight.doc
PortalSolarWorld.doc
PortalSolar_ChinaWorld.doc

SolarRadMeasurement/
Instruments_CN.doc
Instruments_EN.doc
Products_CN.doc
Products_EN.doc
Project1.doc
Project2.doc
Project3.doc
Project4.doc
RadMeasure1.doc
RadMeasure2.doc
Soft.doc
SolarRadMeasurement.doc
光学.doc
太阳观测.doc
空间太阳望远镜.doc
空间探测.doc

SolarRadiation/
00SolarRadRnDPlan.doc
Rad1.doc
Rad2.doc
Rad3.doc
SolarRad.doc
SolarRadStudies.doc

SolarSpace/
SpacePV.doc
SpacePV1.doc
SpacePV2.doc

SolarThermal/
Researches_SolarThermo.doc
Researches_SolarThermo1.doc
Researches_SolarThermo2.doc
Thermal.doc
ThermalIntro_EN.doc
ThermalIntro_cn.doc

Solarcraft/
Solarcraft
├<China>
│ ├Solarcraft_China.doc
│ └Solarcraft_China2.doc
├<Europe>
│ ├Solarcraft_Europe.doc
│ ├Solarcraft_Europe1.doc
│ ├Solarcraft_Europe2.doc
│ ├Solarcraft_Europe3.doc
│ ├Solarcraft_Europe4.doc
│ ├Solarcraft_France.doc
│ ├Solarcraft_German.doc
│ ├Solarcraft_Germany.doc
│ ├Solarcraft_Suisse.doc
│ ├Solarcraft_Swiss.doc
│ ├Solarcraft_UK.doc
│ └Solarcraft_UK2.doc
├Gallery_SolarAircrafts.doc
├Gallery_SolarAir_Aircrafts_Backup.doc
├<Intro>
│ ├InfoTemplate.doc
│ ├Solarcraft_Intro.doc
│ └Solarcraft_Intro2.doc
├<Others>
│ ├Solarcraft_Israel.doc
│ ├Solarcraft_Israel2.doc
│ ├Solarcraft_Japan.doc
│ ├Solarcraft_Japan2.doc
│ ├Solarcraft_Others.doc
│ └Solarcraft_Others2.doc
├PortalSolarcraft.doc
├PortalSolarcraft1.doc
├<USA>
│ ├Solarcraft_ACP.doc
│ ├Solarcraft_ACP2.doc
│ ├Solarcraft_AeronViron.doc
│ ├Solarcraft_AeronViron2.doc
│ ├Solarcraft_Aeroscraft.doc
│ ├Solarcraft_Aerostar.doc
│ ├Solarcraft_Astro.doc
│ ├Solarcraft_NASA.doc
│ ├Solarcraft_NASA2.doc
│ ├Solarcraft_OSU.doc
│ ├Solarcraft_SolFlight.doc
│ ├Solarcraft_SolFlight2.doc
│ ├Solarcraft_Ultra.doc
│ ├Solarcraft_Ultra2.doc
│ ├Solarcraft_USA1.doc
│ ├Solarcraft_USA1_2.doc
│ ├Solarcraft_USA2.doc
│ ├Solarcraft_USA2_2.doc
│ ├Solarcraft_USA3.doc
│ ├Solarcraft_USA4.doc
│ ├Solarcraft_USA5.doc
│ └Solarcraft_USA6.doc
└WebsourcesSolarcraft.doc

Solarions/
ArthurClarke.doc
Gallery_SolarAir_LightPropulsion_BackupX.doc
SolarIon.doc
SolarSails.doc

Solarships/
Gallery_SolarAir_Ships_Backup.doc
SolarAirships_Aeroscraft.doc
SolarAirships_Aerostar.doc
SolarAirships_Asia.doc
SolarAirships_Canada.doc
SolarAirships_China.doc
SolarAirships_Europe1.doc
SolarAirships_Europe2.doc
SolarAirships_Israel.doc
SolarAirships_Japan.doc
SolarAirships_NASA.doc
SolarAirships_Others.doc
SolarAirships_SolFlight.doc
SolarAirships_Swiss.doc
SolarAirships_UK.doc
SolarAirships_USA1.doc
SolarAirships_USA2.doc
SolarAirships_USA3.doc
SolarAirships_USA4.doc
SolarAirships_int.doc

TOC/
ChinaSolarSummary0408TOC.doc
TOC_ChinaSolarDir.doc
TOC_China_Solar_All.doc
TOC_SolarCollections.doc
TOC_SolarPhysics.doc
TOC_SolarReportOthers.doc
TOC_SolarStudies.doc
TOC_SolarTech.doc
TOC_SolarTech07.doc
TOC_Solarcrafts.doc
TOC_WorldSolarDir.doc
Types of PV Cell
Crystalline Silicon (c-Si)
Crystalline silicon (c-Si) is the leading commercial material for photovoltaic cells, and is used in several forms: single-crystalline or monocrystalline silicon, multicrystalline or polycrystalline silicon, ribbon and sheet silicon and thin-layer silicon.

Common techniques for the production of crystalline silicon include the

  • Czochralski (CZ) method, - A seed of crystalline silicon is dipped to touch the surface of molten silicon in a crucible and is then slowly
    raised. Silicon solidifies—in the crystal pattern of the seed—as it is pulled from the crucible to form part of the growing boule. The CZ method
    dominates commercial growth of single-crystal silicon and produces laboratory cells with efficiencies as high as 20%.
  • float-zone (FZ) method, A rod of silicon is placed atop a crystalline-silicon seed, and a movable heating coil encircling the rod is slowly
    raised from the seed upward. As the coil is raised, it melts the silicon, which then solidifies in the pattern of the crystal seed below it as the coil
    moves farther upward. FZ silicon has produced cells with a laboratory efficiency as high as 24%. Commercial applications for FZ silicon,
    however, have so far been restricted largely to high-efficiency cells (such as for satellites or concentrator systems). One limiting factor for FZ
    technology is the need for the feed rod of silicon to be smooth, uniform in diameter, and free of cracks. This precludes the use of most
    electronics industry seconds—used by many of the other silicon growth processes in photovoltaic applications—therefore requiring more
    expensive silicon meltstock and keeping costs high.
  • casting - Casting/Directional Solidification—Molten silicon is either poured into a heated mold or melted in a crucible and allowed to slowly cool
    and solidify as multicrystalline silicon. Simple casting, however, has only relatively modest temperature control for producing quality cells.
    Most current casting operations have therefore added more complex temperature controls, and some have produced cells with a laboratory
    efficiency as high as 17.8%—the old record broken by the 18.2%-efficient cells made from HEM wafers. Cast silicon is usually made in square
    shapes that are better for packing solar cells into modules. (Both CZ and FZ single-crystal ingots are round.)
  • die or wire pulling
  • Ribbon/Sheet Growth—Several variations pull flat "ribbons" or sheets of multicrystalline silicon (one is single-crystal) from a crucible. The
    ribbons or sheets can then be cut directly into semiconductor wafers for solar cells, without the waste and expense of sawing ingots.
    Laboratory cell efficiencies reach 15%. The main drawback seems to be relatively slow production rates.
  • Thin Layer—Because of the potential for inexpensive production processes, there is considerable interest in thin films of amorphous silicon
    and various nonsilicon semiconductors for solar cells. It may also be possible to grow thin layers of crystalline silicon, and various researchers
    are investigating this option.

The removal of impurities and defects in the silicon is of critical importance, and is addressed with techniques such as surface passivation (reacting the surface with hydrogen) and gettering (a chemical heat treatment that causes impurities to diffuse out of the silicon). Also at issue as the industry grows is the availability and purity of the solar-grade silicon feedstock.

Although crystalline silicon solar cells have been in existence since 1954, new innovations continue to be developed, including the emitter wrap-through (EWT) cell and the self-aligned selective-emitter (SASE) cell.

Monocrystalline Silicon Cells:
Made using cells saw-cut from a single cylindrical crystal of silicon, this is the most efficient of the photovoltaic (PV) technologies. The principle advantage of monocrystalline cells are their high efficiencies, typically around 15%, although the manufacturing process required to produce monocrystalline silicon is complicated, resulting in slightly higher costs than other technologies.

Multicrystalline Silicon Cells:
Made from cells cut from an ingot of melted and recrystallised silicon. In the manufacturing process, molten silicon is cast into ingots of polycrystalline silicon, these ingots are then saw-cut into very thin wafers and assembled into complete cells. Multicrystalline cells are cheaper to produce than monocrystalline ones, due to the simpler manufacturing process. However, they tend to be slightly less efficient, with average efficiencies of around 12%., creating a granular texture

Thick-film Silicon:
Another multicrystalline technology where the silicon is deposited in a continuous process onto a base material giving a fine grained, sparkling appearance. Like all crystalline PV, this is encapsulated in a transparent insulating polymer with a tempered glass cover and usually bound into a strong aluminium frame.

Thin Films

Amorphous Silicon:

Amorphous silicon cells are composed of silicon atoms in a thin homogenous layer rather than a crystal structure. Amorphous silicon absorbs light more effectively than crystalline silicon, so the cells can be thinner. For this reason, amorphous silicon is also known as a "thin film" PV technology. Amorphous silicon can be deposited on a wide range of substrates, both rigid and flexible, which makes it ideal for curved surfaces and "fold-away" modules. Amorphous cells are, however, less efficient than crystalline based cells, with typical efficiencies of around 6%, but they are easier and therefore cheaper to produce. Their low cost makes them ideally suited for many applications where high efficiency is not required and low cost is important.

Thin film photovoltaic cells use layers of semiconductor materials only a few micrometers thick, attached to an inexpensive backing such as glass, flexible plastic, or stainless steel. Semiconductor materials for use in thin films include amorphous silicon (a-Si), copper indium diselenide (CIS), and cadmium telluride (CdTe). Amorphous silicon has no crystal structure and is gradually degraded by exposure to light through the Staebler-Wronski Effect. Hydrogen passivation can reduce this effect. Because the quantity of semiconductor material required for thin films is far smaller than for traditional PV cells, the cost of thin film manufacturing is far less than for crystalline silicon solar cells.

Group III-V Technologies
These photovoltaic technologies, based on Group III and V elements in the Periodic Table, show very high conversion efficiencies under either normal sunlight or sunlight that is concentrated (see "Concentrating Collectors" below). Single-crystal cells of this type are usually made of gallium arsenide (GaAs). Gallium arsenide can be alloyed with elements such as indium, phosphorus, and aluminum to create semiconductors that respond to different energies of sunlight.

Other Thin Films:
A number of other promising materials such as cadmium telluride (CdTe) and copper indium diselenide (CIS) are now being used for PV modules. The attraction of these technologies is that they can be manufactured by relatively inexpensive industrial processes, certainly in comparison to crystalline silicon technologies, yet they typically offer higher module efficiencies than amorphous silicon. New technologies based on the photosynthesis process are not yet on the market.

for research on higher-efficiency concentrator photovoltaic (CPV) III-V solar cells

High-Efficiency Multijunction Devices

Multijunction devices stack individual solar cells on top of each other to maximize the capture and conversion of solar energy. The top layer (or junction) captures the highest-energy light and passes the rest on to be absorbed by the lower layers. Much of the work in this area uses gallium arsenide and its alloys, as well as using amorphous silicon, copper indium diselenide, and gallium indium phosphide. Although two-junction cells have been built, most research is focusing on three-junction (thyristor) and four-junction devices, using materials such as germanium (Ge) to capture the lowest-energy light in the lowest layer
Advanced Solar Cells

A variety of advanced approaches to solar cells are under investigation. Dye-sensitized solar cells use a dye-impregnated layer of titanium dioxide to generate a voltage, rather than the semiconducting materials used in most solar cells. Because titanium dioxide is relatively inexpensive, they offer the potential to significantly cut the cost of solar cells. Other advanced approaches include polymer (or plastic) solar cells (which may include large carbon molecules called fullerenes) and photoelectrochemical cells, which produce hydrogen directly from water in the presence of sunlight.
Fabricating Solar Cells and Modules

A variety of technical issues are involved in the fabrication of solar cells. The semiconductor material is often doped with impurities such as boron or phosphorus to tweak the frequencies of light that it responds to. Other treatments include surface passivation of the material and application of antireflection coatings. The encapsulation of the complete PV module in a protective shell is another important step in the fabrication process.
Balance of System (BOS) Components

The balance of system (BOS) components include everything in a photovoltaic system other than the photovoltaic modules. BOS components may include mounting structures, tracking devices, batteries, power electronics (including an inverter, a charge controller, and a grid interconnection), and other devices.
Concentrator Collectors

Concentrating photovoltaic collectors use devices such as Fresnel lenses, mirrors, and mirrored dishes to concentrate sunlight onto a solar cell. Certain solar cells, such as gallium arsenide cells, can efficiently convert concentrated solar energy into electricity, allowing the use of only a small amount of semiconducting material per square foot of solar collector. Concentrating collectors are usually mounted on a two-axis tracking system to keep the collector pointed toward the sun.
Building-Integrated Photovoltaics (BIPV)

Building-integrated photovoltaic materials are manufactured with the double purpose of producing electricity and serving as construction materials. They can replace traditional building components, including curtain walls, skylights, atrium roofs, awnings, roof tiles and shingles, and windows.
Stand-Alone Photovoltaic Systems

Stand-alone systems produce power independently of the utility grid. In some off-the-grid locations as near as one-quarter mile from the power lines, stand-alone photovoltaic systems can be more cost-effective than extending power lines. They are especially appropriate for remote, environmentally sensitive areas, such as national parks, cabins, and remote homes. In rural areas, small stand-alone solar arrays often power farm lighting, fence chargers, and solar water pumps, which provide water for livestock. Direct-coupled systems need no electrical storage because they operate only during daylight hours, but most systems rely on battery storage so that energy produced during the day can be used at night. Some systems, called hybrid systems, combine solar power with additional power sources such as wind or diesel.
Grid-connected Photovoltaic Systems

Grid-connected photovoltaic systems, also called grid interface systems, supply surplus power back through the grid to the utility, and take from the utility grid when the home system's power supply is low. These systems remove the need for battery storage, although arranging for the grid interconnection can be difficult. In some cases, utilities allow net metering, which allows the owner to sell excess power back to the utility.
Space Applications

Solar arrays work well for generating power in space and power virtually all satellites. Most satellites and spacecraft are equipped with crystalline silicon or high-efficiency Group III-IV cells, but recently satellites have begun using thin-film amorphous-silicon-based solar panels.
2018-01-05


My Academic Endevour

4Research.docx
4Research1.docx
Background20090814.doc
Paststudies20090827.doc
PaststudiesOldDamagedRepaired.DOC
academic.docx
pastacademic20120227.doc
pastacademic20130127.doc
paststudies20110324.doc
studies_hobby1.doc


Funding My Researches

There was days when I fancied that someone would provide some capital for my scientific activities either researches or writing. But none have showed enough willingness.

Then suddenly, on Sept 13, 2014, a certain Mr Kenneth Whang, Program Director, Division of Information and Intelligent Systems, National Science Foundation sent me an email for the call of proposals for the Collaborative Research in Computational Neuroscience program. I was wondering how did he know that I am working on this subject and how did he get my email address. I can remember that I ever have left my email address to NSF site. And how did he get my email address is still a secret. Nevertheless, I did have some kind of studies of computation, but in fluiddynamics and thermodynamics but not neuroscience. I did have some population with the US government, when I was quoted as a solar expert by US National Renewable Energy Labs under the Ministry of Energy during 2005-2007.

But his email aroused my extinguished interest in NSF, and I decided to seek a funding from there. Therefore I have registered at NSF and prepared and submitted my application for funding package today (2014-09-17) . It took me 3 days to do so. My version of Chinese PDF reader has some defect so that the first submittals were failed and I have to switch to English version and change a bit of the contents, and finally the submission was done OK. Now I have to wait for the review results.

funds
├<Ford>
│ └appForm2010.doc
├<Funds_Cancer>
│ ├FundsCancer.doc
│ ├Funds_Cancer.doc
│ └Funds_Cancer_2.doc
├<Funds_CFD>
│ ├About_CFD1.doc
│ └Funds_CFD.doc
├<Funds_Math>
├<funds_math4chip>
│ ├funds_math4chip.docx
│ └<newton_institute>
│ ├142586.pdf
│ ├180928.pdf
│ ├application.docx
│ └proposals.docx
├<Funds_NanoFluids>
│ └Funds_NanoFluids.doc
├<Funds_Thermo>
│ ├Funds_ThermoPlan.doc
│ ├Funds_ThermoPlan1.doc
│ └Funds_ThermoPlan2.doc
├<Funds_Writing>
│ └FundsWriting.docx
└<nsf>
├budget.docx
├budget.pdf
├Current_Pending_Support.docx
├Current_Pending_Support.pdf
├cv_cmh0.doc
├cv_cmh0.pdf
├cv_cmh1.doc
├cv_cmh1.pdf
├Data Management Plan.docx
├Data Management Plan.pdf
├Equipment.docx
├Equipment.pdf
├Facilities_Other_Resources.docx
├Facilities_Other_Resources.pdf
├grant_application_guides_nsf.docx
├literature_referrence.docx
├literature_referrence.pdf
├math4chip_research_plan_abstract0.docx
├math4chip_research_plan_abstract0.pdf
├math4chip_research_plan_abstract1.docx
├math4chip_research_plan_abstract1.pdf
├math4chip_research_plan_overall0.docx
├math4chip_research_plan_overall0.pdf
├math4chip_research_plan_overall1.docx
├math4chip_research_plan_overall1.pdf
└oppPD-10-7970-cfda47.049.pdf


Research Methods

There are people who have worked on how to make scientific discoveries and have written tons of books and papers and invented millions of methods to improve to scientific finding capacity.

However, scientific finding is basically a luxurious job: when you have enough time and money, you can make new things to become reality, and if you're poor and too busy, you have no chance at all, regardless if you have learned all these methods or not. I know combinatorial techniques are the most effective ones.


Problems
Occasionally I would write down what I have in my mind about new ideas of a certain scientific topic. But I have no time to tackle them yet. See Problems.doc and Problems1.doc


Science Books

These are the greatest scientific and humanity works ever written in the history of humans. I have planned to read some of the most important but somehow I could not realize my plan because of my daily burden.

RAND_TR303.pdf
Sciences.docx
SciencesBooks20080918.doc
SciencesBooks20091015.doc
SciencesBooks20130127.doc
SciencesBooks20130628.doc
SciencesBooks_General.doc
SciencesBooks_General_EN.doc
SciencesBooks_OldChinese.doc
SciencesWeb.doc


scientists

As a result of my previous researches and studies, I have compiled a number of lists of worldwide scientists, in China and elsewhere, ancient and contemporary, in the fields of my interests. I have read some books and papers from some of them, I have also contacted some of them for research position by them. None was willing to accept me though.

scientists
├<000emails_scientists>
│ └emails_scientists.txt
├<CFD>
│ ├email_fluid.TXT
│ ├JOBsFluidPhD.DOC
│ ├JobsFluidTech.doc
│ └JOBsFluidTech1.doc
├<Chip>
│ ├email_chip.TXT
│ ├Whores_Chip.docx
│ └Whores_Chip.txt
├<General>
│ ├email_general.TXT
│ ├Scientists_General_CN.doc
│ ├Scientists_General_CN2.doc
│ ├Scientists_General_EN.doc
│ ├Scientists_General_EN1.doc
│ ├Scientists_General_EN2.doc
│ ├Scientists_General_EN3.doc
│ ├Scientists_Others.doc
│ ├Scientists_Others1.doc
│ ├TopScientists.doc
│ └TopScientists1.doc
├<Math>
│ ├email_math.TXT
│ ├Scientists_ALGEBRA.docx
│ ├Scientists_ALGEBRA.txt
│ ├Scientists_Math0.doc
│ ├Scientists_Math1.doc
│ ├Scientists_Math2.doc
│ └Scientists_Math3.doc
├<NanoFluidicsResearchers>
│ ├email_NanoFluidics.TXT
│ ├NanoFluidicsResearchers.doc
│ └NanoFluidicsResearchers1.doc
├<NanoThermScientists>
│ ├email_nanotherm.TXT
│ ├Scientists_NanoTherm.doc
│ └Scientists_NanoTherm1.doc
├<NumTheory>
│ ├email_numbertheory.TXT
│ ├Scientists_NumTheory.txt
│ ├Scientists_NumTheoryCurrent.docx
│ ├Scientists_NumTheoryCurrent1.docx
│ └Scientists_NumTheoryPast.docx
├<Solar>
│ ├email_Solar.TXT
│ ├Scientists_Radiation_CN.doc
│ ├Scientists_Radiation_CN1.doc
│ ├Scientists_Radiation_EN.doc
│ ├Scientists_Radiation_EN1.doc
│ ├Scientists_Radiation_EN1_1.doc
│ ├Scientists_SSM.doc
│ └Scientists_SSM1.doc
├<Thermo>
│ ├Coverletter_thermo20100820.doc
│ ├email_Thermo.TXT
│ ├Scientists_Biotherm.doc
│ ├Scientists_Biotherm1.doc
│ ├Scientists_BiothermA2C.doc
│ ├Scientists_BiothermD2Ir.doc
│ ├Scientists_BiothermI2UK.doc
│ ├Scientists_BiothermUS.doc
│ ├Scientists_Thermodynamics.doc
│ ├Scientists_Thermodynamics1.doc
│ ├Scientists_Thermodyn_Hist.doc
│ └Scientists_Thermodyn_Hist1.doc
├<ThermoCancer>
│ ├coverletter_thermocancer20100810.doc
│ ├coverletter_thermonano20100820.doc
│ ├email_ThermoCancer.TXT
│ ├Scientists_ThermoCancer.doc
│ ├Scientists_ThermoCancer1.doc
│ ├Scientists_ThermoCancer1_1.doc
│ ├Scientists_ThermoCancer2.doc
│ ├Scientists_ThermoCancer3.doc
│ ├Scientists_ThermoCancer4.doc
│ ├Scientists_ThermoCancerCFD.doc
│ ├Scientists_ThermoCancer_Key.doc
│ └Scientists_ThermoCancer_Key1.doc
├<Universe>
│ ├email_Universe.TXT
│ ├Scientists_Universe_CN.doc
│ ├Scientists_Universe_CN1.doc
│ ├Scientists_Universe_EN.doc
│ └Scientists_Universe_EN1.doc
└<Whores_ChipMath>
├000Whores_ChipMath_Final.docx
├000Whores_ChipMath_Final_Emails.txt
├000Whores_ChipMath_Final_temp.docx
├<Emails>
│ ├Whores_ChipMath_Emails.txt
│ ├Whores_ChipMath_Emails2.txt
│ └Whores_ChipMath_Emails_temp.txt
├Letter4graph4Chip_CNEN.docx
├Whores_ChipMath_Old1.docx
├Whores_ChipMath_Old2.docx
├Whores_ChipMath_Websites.txt
└Whores_ChipMath_WebsitesTemp.txt


study schedules

Since my early university days I have always been maintaining a more or less strict scheduling for all of my life activities, incl. also studies. I have a record only since roughly 1998 on my computer, the earlier ones were on paper and thus are mostly lost.

BooksPapersRead.doc
BooksPapersRead.pdf
Keywords.doc
MathStudies20140125.docx
MathStudiesAll.docx
MathStudiesOthers.doc
MyStudies.txt
Reading.doc
Study.doc
Study20110918.doc
Study20120922.doc
Study20121031.docx
Study20121031_old.docx
Study20130102.docx
Study20130126.docx


Why Science?

Why do I plan to return to Universities or institutes for scientific researches?

The main reason of this fundamental change of my life and career is my firm belief that only the acquaintance with science and studies of the Nature can give me some sort of satisfaction and happiness. In my childhood, I have always been thinking about becoming a top scientist and this is still my unrealized dream. I am thirsty to learn everything about the Nature and her principles. All branches of sciences are attracting me – mathematics, physics, chemistry…. When dived into the realm of science, I forget the rest of the world.

Secondly, I’ve found the industry, commerce and politics all full of crimes, evils, lies, corruption and injustice (in fact they are synonyms) , and I hate all these, therefore, after so many years there, I want to keep myself distant away from them and concentrate myself on pure scientific researches.

Thirdly, my personality is very fit for scientific researches. Although working in the industry and business over the last two decades, I am still maintaining my habit to learn new sciences every day without interruption. My reading and study capability is unique. Each day I might read more than 100 pages of books of various kinds. I am able to read papers in English, German and French and I am still improving my Russian.

And lastly, I should have been among the top scientists if I have accepted the Ph.D studies I won from several European and N. American universities such as University of Glasgow (gas turbine combustion), University of Paris (surface chemistry), Laval University, and universities of Germany and other countries during 1991-1992 shortly after graduation as a master of science. I was unable to attend these universities because of private reasons Further in 1996, I was nearly admitted by Harvard to pursue a MPA when my former boss told me that the job at Alstom was worth more than a Harvard MPA, a wrong judgment of course.

For short, only a scientific career can fulfill my dream of lifetime endeavors.


Combustion Theory and SOx Control

My Master of Engineering research topic was SO2 emission control for coal combustion process, hence I was heavily involved in the combustion theory. And in 2011 I was again forced to learn a bit because I was preparing for PhD exam into Zhejiang University.

While my primary interest is in mathematics, due to historical reasons, I am still involved in the researches of combustion and related SOx emission control, because this was my area of research at the time of my postgraduate studies. Another reasons is that I am currently writing a fairly comprehensive review of the deSOx theory, technologies and applications as my contribute to my postgraduate tutor as well as the academician and a thermophysical professor at Zhejiang University, who might admit me into his research program. I will tell you my writing and research progress here.

Unfortunately, I was not admitted into the PhD studies program at Zhejiang University's Institute of Energy and Environment in the Department of Energy. Although I passed the written exam with relatively good scores - English 80, Adv. Combustion and Heat Transfer both 70, the interview was not successful. No reason was given, even after I have sent inquiry email and made several phone calls to the admissions office. Later I have also filed complaints against towards the unfair treatment of my examinations, bust no one has replied to my requests within the Zhejiang University. I've sent the complaints to the deans of the Energy Dept and the Graduate Dept. My short experiences with the PhD admission policies have already revealed how serious the corruption is within the Chinese academic circles. Before sending my references, one of my colleagues at Tongji University, warned me not to pursue after a PhD at Zhejiang University, "in order not to sacrifice your life there", she said.

It took me four months to prepare for the examinations and some efforts to prepare for the interview and related documents. In fact, I've spent much more time than that. Over the last years or so, I've been in contact with Prof Cen Kefa, an academician of the Chinese Enginerring Academy, for my research plan and hence have submitted to him a number of documents detailing my research intentions. In one word, I have spent much much more time than the combined efforts for all other universities and institutions all over the world over the last 3 to 4 years (2006-2010).
This part of the studies has come to an end.


Heat transfer

Some time in 2010 -2011 I was again involved in heat transfer. First I was once again interested in thermodnamics and thermophysics and heat transfer is very closely related to them, because it is part of the thermophysics.

And likewise I have to study a little about heat transfer for preparing for the PhD entry exam for Zhejiang University in 2011.


Pollution Control

My Master of Engineering research topic was SO2 emission control for coal combustion process. It was a municipal research project of Shanghai in the late 1980's and thus I was a pioneer in China's anti-pollution efforts. Only 20 years later China has then really taken measures to mitigate the SOX and NOx emission from coal fired power plants and automobiles.

MaterThesisSO2AbstractChenMinghua.doc
MaterThesisSO2AbstractChenMinghua.pdf
Pollution燃煤SO2污染.doc
Pollution燃煤SO2污染.pdf
非线性复杂性科学在煤燃烧过程中SO2排放理论和数值模拟的应用.doc
非线性复杂性科学在煤燃烧过程中SO2排放理论和数值模拟的应用.pdf

Pollution Control

My Master of Engineering research topic was SO2 emission control for coal combustion process. It was a municipal research project of Shanghai in the late 1980's and thus I was a pioneer in China's anti-pollution efforts. Only 20 years later China has then really taken measures to mitigate the SOX and NOx emission from coal fired power plants and automobiles.

MaterThesisSO2AbstractChenMinghua.doc
MaterThesisSO2AbstractChenMinghua.pdf
Pollution燃煤SO2污染.doc
Pollution燃煤SO2污染.pdf
非线性复杂性科学在煤燃烧过程中SO2排放理论和数值模拟的应用.doc
非线性复杂性科学在煤燃烧过程中SO2排放理论和数值模拟的应用.pdf


Writing my Theses or Books

How to write my scientific books different from all the others so that people are enjoying reading math essays as they enjoy a love story, and on the other hand make my books as logical and systematic as possible. In addition, how to use the latest IT and Internet technologies so that its presentations can be more and more interactive with the readers as well. not just an one-sided information flow? These and more questions are concerned when writing my essays - albeit they willl not all be realized in the first papers I will be publishing. See this links for my considerations.

My Writing Style :

writing_style.htm

List of My Writings:

During the last years since 2003 I have written hundreds or even thousands of academic, business and commentary notes in the forms of papers, presentation slides, reports, booklets and books in the areas such as solar physics, thermodynamics, fluid dynamics, IT (incl cryptography), VLSI chip design and mathematics, incl math for VLSI design, among them are selected about 200+ pieces of quite comprehensive and indepth review and research as listed below, amounting to more than 40 000 pages (200 pages each on average) of essays, and some of them can be published after a little finetuning. And again, this 200+ papers, books and so alike were based on thousands of records, notes and reports produced during my preparations over the 2003-2015 period alone. The exact number is not known, a preliminary statistics indicates it at the range of 3000 to 3500.

See the reference for details:

WhatsWrittenSince2003.pdf

writing_list.html

writing_list1.htm

1document_list.pdf


MY RESEARCHES & AUTHORING

During the last years since 2003 I have written hundreds or even thousands of academic, business and commentary notes in the forms of papers, presentation slides, reports, booklets and books in the areas such as solar physics, thermodynamics, fluid dynamics, IT (incl cryptography), VLSI chip design and mathematics, incl math for VLSI design, among them are selected about 200+ pieces of quite comprehensive and indepth review and research as listed below.

?

I did not publish my academic writing results because none of these researches and writing are sponsored by any universities, institutions, other academic organizations and funds, for all of thousands of these organizations and professors have rejected my research incentives in the past. On the other hand, most of them are just my study aides or daily records, with exception of the business reports that are specifically prepared for a special purpose. Therefore they are mostly not written with the purpose of publication in mind. And my writing is to large extent only my hobby, for my own amusement, not for showing the world how capable I am. However, they are not necessary meant to be in low quality and just on contrary, they can be compatible with most published papers on the market.

?

Since 2003, especially during 2003 -2009 period, I’ve written quite a number of business reporting and analyses in some selected industries. Some of them were commercialized and the rest were not marketed yet.

?

I’ve also written some essays about the social life, politics ?etc, all after 2010.

?

Thus, with the exception of my master’s thesis in 1989, all of my writings are dated back from 2003. Therefore what I have written before that and after 1978 when I first attended the university at the age of 15, are not known and are all lost. They might be yet another great number as well.

?

What will be coming up after this listing?

?

Well, my writing will certainly no more spread over so large a spectrum as before. I might still write some business reports, but only on requests of my clients, therefore that is unpredictable. I might still write a large number of essays about my life and the social events happening here and there and which will eventually be part of my autobiography. Apart from this, my overall writing will be slowed down or even suspended for the moment, because of my poor economic status. For during the last decade I did not earn money in lieu of my researches and my purse is dried up, therefore I need to fill it up and hence for some months or even years from now I might shift to business and leave little time to studies – an hour a day at most.

?

Nevertheless, my academic writing and researches will be sure focusing on the following three areas for the rest of my life:

l? Graph theory for IC technologies, at the moment graph embedding (part of the extremal graph theory)

l? New generations of IC technologies, just for followup, no way to conduct real research

l? Software reverse engineering and hacking technologies or better put it networking security, for practical purpose.

?

I will no more write hundreds of them, but I will write some serious and useful essays in the above fields.

?

In addition to the above, as always I will continue to read books written by the greatest mathematicians, scientists, philosophers and novelists since the ancient days in Greek, Latin, Esperanto, English, French, Russian and German which I know to different degree. I want to know how they view the world and how they depict it. If you read the paper written by Albert Einstein, and other great scientists, you will pretty soon find out how they are different from those rubbish you will see on all the science journals.

?

If you don’t trust this list, I won’t care, nor will I try to argue with you, for I am not an ordinary person, thus judging from an ordinary person won’t be justified at all. But I can tell some of the truth already here. I read much faster than most people – I read books of a hundred pages just in an hours or so, depending on the easiness or difficulty of that book. And I also write much faster than most others. In an hour I can already write down an essay of a dozen pages. Therefore writing a 100-page book costs me only a week or so. If I write at full speed, I might write three thousand pages of all sorts of papers, essays or books in a year. Of course I cannot write mathematical article that quick. Math is different, one needs to spend hundred time more efforts to prepare for a same-length paper than for physical or social sciences. Math needs slow reading, slow digestion and slow writing. To conclude anyway, what others have to do in 10 years, I can do it in just a year, that’s where the difference is.

?

All books with a few exception are written in US English: a few in German and some others in Chinese.

?

Note that all page number calculations are rough estimation only.

?

ACADEMIC WRITING

(2007 – present)

GRAPH THEORY

On the part of graph theory for VLSI design, I have written some papers on graph theory for VLSI routing/detailed routing/channel routing, hypergraph modeling for FPGA design, graph theory for advanced chip design particularly quantum computing, graph partitioning for VLSI design, graph embedding for VLSI (particularly quantum circuits) design, graph theory for 3d VLSI design etc. I have also prepared for several pure graph theoretic essays.

?

Pure & Applied Graph Theories for IC Design

Graph Theory – an Introduction????????? ???????????????????????????????????????????????????????????????????????????? pp52

TSP – Traveling Salesman Problems, a comprehensive review?? ?????????????????????????????????????????????? pp67

Graph actions/operations????????? ??? ?????????????????????????????????????????????????????????????????????????????????? pp21

Graph/hypergraph clustering??????? ????????????????????????????????????????????????????????????????????????????????????? pp60

?

Graph embedding / graph packing ?/ Extremal Graph Theory – current focus??????? under preparation

?

Graph / Hypergrah features / instances / variables / parameters / Relations??????????????????????????????????? pp14

Graph/Hypergraph File Format???????????????????????????????????????????????????????????????????????????????????????? ?????? pp8

Graph function / components / characteristics??????????????????????????????????????????????????????????????????????????? pp14

Graph partitioning???? ??????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp330

Graph-to-hypergraph transformation ?????????????????????????????????????????????????????????????????????????????????????? pp20

Graph types??? ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????? p269

Tree types?????? ???????????????????????????????????????????????????????????????????????????????????????????????????????????????? p112

?

Graph/hypergraph modelling for VLSI design???? ????????????????????????????????????????????????????????????????????? pp40

Graph theory for reconfigurable computing – Part I Introduction?????????????????????????????????????????????????????? pp37

Graph Theory for Reconfigurable Computing – Part II: Control & Data Flow Graphs??? ??????????????????? pp77

?

Hypergraph

Hypergraph types????????????? ??????????????????????????? ?????????????????????????????????????????????????????????????? pp126

Hypergraph Models for FPGA design??????????? ????????????????????????????????????????????????????????????????? pp58

?

Combinatorics & Operational Optimizations????? ??????????????????????????????? pp49

?

Graph Theory and the Worldwide Web

Graph theory and the Word Wide Web – Some Special Topics???????????????????????????????????????????????????? pp250

(topics include graph theory for the Internet, search engines algorithms, Google Maps and other Internet map systems, peer-to-peer(p2p) networking and the TOR router)

?

CHIP DESIGN

Chip design study notes - electronic theories and technologies??????? ?????????????????????????????????????? pp62

Chip design study notes - general?????????????? ??????????????????????????????? ?????????????????????????????????? pp100

Chip design study notes – physical design?????????????? ?????????????????????????????????????????????????????? pp89

Chip design study notes – routing?????????????????????? ??????????????????????????????????????????????????? pp139

Chip design study notes – FPGA?????????????????? ???????????????????????????????????????????????????????????? pp56

?

New Generation of Information Processing and Computing

3D ICs????? ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp218

Membrane chips?????????????? ?????????????????????????????????????????????????????????????????????????????????????????? pp33

Nano chips????????????? ??????????????????????????????????????????????????????????????????????????????????????????????????? pp82

Neural computing?????????????????? ???????????????????????????????????????????????????????????????????????????????? pp36

Quantum chips?????????????????? ????????????????????????????????????????????????????????????????????????????????????? pp288?? ????????

Other next generations of IC technologies incl.:?????????????????????????????????????????????????????? under preparation??????

l? bio_DNA

l? bio_cellular

l? biocomputing

l? deep

l? dynamical systems computing

l? gallium

l? genetic

l? germanium

l? graphene

l? indium

l? molecular

l? molybdenium

l? nano

l? photonic/

l? resonant tunneling

l? reversible computing/

l? single electron/

l? strained silicon/

l? superconducting/

?

?

Spin Based Chips - current focus???????? ??????????? ??????????????????????????????? ?????? under preparation

?

MATHEMATICS – EARLIER RESEARCHES

Abstract Algebra – Encyclopedia?????????? ????????????????????????????????????????????????????????????????????????? pp41

Boolean Algebra?????????????????? ?????????????????????????????????? ?????????????????????????????????????????????????????????????? pp53

Complex Analysis?????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp56

?

Computational Analysis?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp135

Number Theory – a Review????????? ?????????????????????????????????????????????????????????????????????????????????? pp19

Applied Number Theory???????????????????????????????????????????????????????????????????????????????????????????????????????? pp120

Primality Testing – Comprehensive Review?????? ?????????????????????????????????????????????????????????????????? pp135

The AKS primality test algorithm – a review and improvement????????????? ?????????????????????????? pp196

Integer Factorization?????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp45

Random Number Generation???????????????????????????????????????????????????????? ????????????????????????????????????????? pp55

?

Functional Analysis ?????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp255

Differential and integral equations & mathematical physical equations???????????????????????????????????????? pp76

Computational Geometry??????????????????????????????????????????????????????????????????????????????????????????????????????? pp33

Probability and statistics????????????????????????????????????????????????????????????????????????????????????????????????????????? pp55

Ergodic Theory????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp43

Fast Fourier Transform?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp322

?

Cryptography ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp40

Quantum Cryptography?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp35

Postquantum Cryptography???????????????????????????????????????????????????????????????????????????????????????????????????? pp75

???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????

Information technology?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp90

Computer Algorithm?????????????????????????? ??????????????????????????????????????????????????????????????????????????????????? pp160

Computer Complexity???????????????????????????????????????????????????????????????????????????????????????????????????????????? pp230

?

Math for Search Engines??????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp210

Math in Music Composition???????????????????????????????????????????????????????????????????????????????????????????????????? pp66

?

Math formula tools???????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp280

?

FLUID DYNAMICS

Nano fluid dynamics: Introduction, Review and Tutorial??????? ??????????????????????????????????????????? pp450?

Computational Fluiddynamics – an Introduction??????????????????????????????????????????????????????????????????????? pp138

Yachts Hydrodynamics??????????????????????????????????????????????????????????????????????????????????????????????????????????? pp26

?

SOLAR RELATED RESEARCHES

有关太阳的一切??????????? ?????????????????????????????????????????????????????????????????????????????????????????????? pp84

About the Sun????? ???????????????????????????????????????????????????????????????????????????????????????????????????????????? pp400

?

Solar energy fundamentals? ?????????????????????????????????????????????????????????????????????????????????????????????????? pp450?

Solar thermal applications?? ???????????????????????????????????????????????????????????????????????????????????????????????????????? pp270

Solar phtovoltaics – wafer, cells, modules, BOS etc??????????? ?????????? ?????????????????????????????????? pp250

Space PV?? ???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp165

Solar power systems?????????? ??????????????????????????????????????????????????????????????????????????????????????????? pp70

Other Solar Technologies

(thermoionic power generation / daylighting / litrospheres?? / photoluminescence / solar hydrogen / solar to liquid fuel / solar photosynthesis)????? ???????????????????????????????????????????????????????????????????????????????????????????????????? pp40

?

Solar radiation theory?????? ???????????????????????????????????????????????????????????????????????????????????????????????? pp 450?

(Spectral radiation & the atmosphere, Solar radiation and the earth system, Solar radiation & climate change / global warming, Solar radiation and vegetation etc)

Solar radiation measurement technology??????? ???????????????????????????????????????????????????????????????????? pp 850

?

Solar Physics – an Introduction and Review??????? ??????????????????????????????????????????????????????????????? pp70

Solar Models (SSM – Standard Solar Models)????????? ???????????????????????????????????????????????????????? pp70

The Chromosphere???????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp10

The Corona??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp30

The Photosphere???????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp20

Solar prominences????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp10

Solar magnetic field?????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp8

Solar Flares?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp25

Helioseismology???????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp11

Solar neutrino problem?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp7

Sunspots?????????????????????????????????????????????????????????????????????????????????????????????????????????? ???????????????????? pp26

Solar wind???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp30

?

Solar aircrafts?????????????? ????????????????????????????????????????????????????????????????????????????????????????????? pp 2000????????

Solar airships????????????? ??????????????????????????????????????????????????????????????????????????????????????????????? pp 550

Solar sails / solar ion propulsion for far space ventures??????????? ???????????????????????????????????????????????? pp180

?

Photoaging??????????????? ??????????????????????????????????????????????????????????????????????????????????????????????? pp170

Solar health and therapy?????????? ????????????????????????????????????????????????????????????????????????????????????? pp245

?

THERMODYNAMICS

Thermodynamics Terminology ?????????????????????????????????????????????????????????????????????????????????????????????? pp32

Thermodynamics databases??? ??????????????????????????????????????????????????????????????????????????????????????????????? pp30

Thermodynamics software???? ??????????????????????????????????????????????????????????????????????????????????????????????? pp60

Thermodynamics events??????? ?????????????????? ???????????????????????????????????????????????????????????????????????????? pp50

?

Introduction to Thermodynamics ?????????????????????????????????????????????????????????????????????????????????????????? pp140

Modern thermodynamics- a comprehensive review, categorization and listing??????? ???????????????? pp267

Entropy?? ?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp60

Equilibrium Thermodynamics? ????????????????????????????????????????????????????????????????????????????????????????????? pp28

Non-Equilibrium & Non-linear Thermodynamics????????????????????????????????????????????????????????????????????? pp22

(Irreversible) Endoreversible Thermodynamics????????????????????????????????????????????????????????????????????????? pp28

Dissipative structure theory???????????????????????????????????????????????????????????????????????????????????????????????????? pp36

Finite Time Thermodynamics????????????????????????????????????????????????????????????????????????????????????????????????? pp8

Negative Energy Spectrum Thermodynamics???????????????????????????????????????????????????????????????????????????? pp9

Advanced Thermodynamics and Statistical Physics?????????? ???????????????????????????????????????????????? pp551

Physical chemistry ??????????????????????????????????????????????????????????????????????????????????? ??????????????????????????? pp50

?

Mesoscopic Thermodynamics??????????????????????????????????????????????????????????????????????????????????????????? pp15

Nano –thermodynamics – an overview?????????? ????????????????????????????????????????????????????????????????? pp150

Quantum Thermodynamics????????????????????????????????????????????????????????????????????????????????????????????????????? pp8

?

Cryogenic thermodynamics???????????????????????????????????????????????????????????????????????????????????????????????????? pp26

?

Computational Thermodynamics????????????????????????????????????????????????????????????????????????????????????????????? pp20

?

Thermodynamics of Polycomponent System??????????? ???????????????????????????????????????????????????????? pp77

Thermodynamics of Porous Media?????????????????????????????????????????????????????????????????????????????????????????? pp10

?

Surface thermodynamics / thermodynamics of surface / interface thermodynamics / interfacial thermodynamics /

thermodynamics of interfaces??????? ??????????????????????????????????????????????????????????????????????????????????? pp37

?

Network Thermodynamics?????????????????????????????????????????????????????????????????????????????????????????????????????? pp9

?

Liquid & Process Thermodynamics????????????????????????????????????????????????????????????????????????????????????????? pp8

Thermodynamics of Solutions/Solvation Thermodynamics????????????????????????????????????????????????????????? pp21

?

Engineering Thermodynamics??????? ??????????????????????????????????????????????????????????????????????????????????? pp87

?

Chemstry Thermodynamics????????? ??????????????????????????????????????????????????????????????????????????????????? pp130

Thermodynamics of Chemical Equilibrium?? ????????????????????????????????????????????????????????????????????????? pp55

Thermochemistry????????????? ?????????????????????????????????????????????????????????????????????????????????????????? pp64

Combustion thermodynamics??????????? ????????????????????????????????????????????????????????????????????????????? pp150

?

Thermodynamics of Materials????????????????????????????????????????????????????????????????????????????????????????????????? pp28

?

Thermodynamics of Crystalization?????????????????????????????????????????????????????????????????????????????????????????? pp12

Metallurgical Thermodynamics??????????????????????????????????????????????????????????????????????????????????????????????? pp33

Thermodynamics of Metals???????????????????????? ??????????????????????????????????????????????????????????????????????????? pp80

Thermodynamics of Alloys????????????????????????????????????????????????????????????????????????????????????????????????????? pp25

Phase Diagram of Alloys and their Thermodynamics????????????????????????????????????????????????????????????????? pp22

?

Cosmos Physics????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp279

Gravitational Thermodynamics??????????????????????????????????????????????????????????????????????????????????????????????? pp10

Thermodynamics of the cosmos (thermodynamics of the universe / cosmic thermodynamics) ????? pp170

Celestial thermodynamics??????????????????????????????????????????????????????????????????????????????????????????????????????? pp25

Black hole thermodynamics???? ??????????????????????????????????????????????????????????????????????????????????????????? pp110

Solar Thermodynamics????????? ????????????????????????????????????????????????????????????????????????????????????????? pp90

Thermodynamics of the solar corona heating mechanism ???????????????????????????????????????????????????? pp270

Thermodynamics of solar wind??????????????? ??????????????????????????????????????????????????????????????????? pp50

?

Earth Thermodynamics?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp10

Atmospheric Thermodynamics??????????? ??????????????????????????????????????????????????????????????????????????? pp46

Greenhouse Thermodynamics?????????????????????????????????????????????????????????????????????????????????????????? pp28

Ecosystem/Ecological Thermodynamics?? ?????????????????????????????????????????????????????????????????????????????? pp894

?

Thermodynamics of Energy System???????????????????????????????????????????????????????????????????????????????????????? pp19

Solar energy and thermodynamics??????????????????????????????????????????????????????????????????????????????????????????? pp25

?

Biological thermodynamics?????????? ????????????????????????????????????????????????????????????????????????????????? pp150

Thermodynamics of Organisms ????????????????????????????????????????????????????????????????????????????????????????????? pp21

?

Thermodynamics and health?????????? ???????????????????????????????????????????????????????????????????????????????? pp90

Thermodynamics of cancers (oncological thermodynamics / thermodynamic oncology / carcinothermodynamics)

Hierarchical Thermodynamics ??????????????????????????????????????????????????????????????????????????????????????????????? pp8

?

Thermodynamics of Pharmaceuticals ????????????????????????????????????????????????????????????????????????????????????? pp15

??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp790

Thermodynamics of economics??????????? ?????????????????????????????????????????????????????????????????????????? pp310

Thermoeconomics / Exergoeconomics???????? ?????????????????????????????????????????????????????????????????????? pp60

?

Sociological Thermodynamics?????? ???????????????????????????????????????????????????????????????????????????????????? pp147

Bible and Thermodynamics?????? ???????????????????????????????????????????????????????????????????????????????????????? pp130

Divine Thermodynamics??????????? ??????????????????????????????????????????????????????????????????????????????????? pp43

?

Thermodynamics of Business Management??????????????????????????????????????????????????????????????????????????????? pp12

Thermodynamics in Finance??????????????????????????????????????????????????????????????????????????????????????????????????? pp27

?

Thermodynamics of Ancient China?????????????????????????????????????????????????????????????????????????????????????????? pp10

Thermodynamics in Literatures??????????????????????????????????????????????????????????????????????????????????????????????? pp14

Thermodynamics in Politics???????????????????????????????????????????????????????????????????????????????????????????????????? pp28

?

?

LANGUAGES

überblick über deutsche Literatur ?????????????????????????????????????????????????????????????????????????????????????????? pp580

?

MISCELLANEOUS

Scientific research methodology?????????????????????????????????????????????????????????????????????????????????????????????? pp135

My science questions and proposals????????????????????????????????????????????????????????????????????????????????????????? pp28

?

WORLD SCIENTISTS DATABASES

The greatest scientists China and the world??????????????????????????????????????????????????????????????????????????????? pp100

Mathematicians????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp89

Graph Theorists????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp425

Algebraists??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp16

Number Theorists ???????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp234

Thermodynamicists ?????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp220

Cosmological Thermodynamicists ?????????????????????????????????????????????????????????????????????????????????????????? pp220

Scientists in Biothermodynamics????????????????????????????????????????????????????????????????????????????????????????????? pp465

Scientists in Oncology and Oncological Thermodynamics?????????????????????????????????????????????????????????? pp550

Nano Thermal Scientists????????????????????????????????????????????????????????????????????????????????????????????????????????? pp31

NanoFluidics Researchers ????????????????????????????????????????????????????????????????????????????????????????????????????? pp70

Solar Radiation Scientists???????????? ?????? ??????????????????????????????????????????????????????????????????????????????????? pp70

SSM (Standard Solar Models) Scientists index???????????????????????????????????????????????????? ???????????????????? pp350

?

MY THESES

?

My Master thesis (1989): Studies on SO2 Pollution Control during coal combustion ????????????????? pp100

?

?

APPLICATION WRITING

(2003-present)

?

IT RELATED

Software reverse engineering???????????????????????????????????? ?????????? under preparation

Network security or hacking technologies?????????????????????????? ????????? under preparation

?

Computer and OS Introduction???? ?????????????????????????????????????????????????????????????????????????????????????????? pp90

Computer and OS trouble shooting records and guides ?????????????????????????????????????????????????????????????? pp375

Internet protocols ???????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp50

Linux systems??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp120

Programming guides?????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp350

Databases?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp252

Servers??? ????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp320

Online communications?????????????????????????????????????????????????????????????????????????????????????????????????????????? pp250

Email security?????????????????????????????????????????????????????????????????????? ???????????????????????????????????????????????? pp210

Browser Security??????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp35

Online multimedia????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp350

GoogleMaps Introduction??????????????????????????????????????????????????????????????????????????????????????????????????????? pp110

WAP – Wireless Application Protocols ??????????????????????????????????????????????????????????????????????????????????? pp100

Website development guides??????????????????????????????????????????????????????????????????????????????????????????????????? pp240

Cryptology review??????????????? ????????????????????????????????????????????????????????????????????????????????????? pp76

Cryptological platforms????????????????????????????????????????????????????????????????????????????????????????????????????????? pp50

CryptoChina Report??????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp100

Internet freedom – a series of Internet access technology guides ??????????????????????????????????????????????????????? pp2300

VPN review and technologies????? ??????????????????????????????????????????????????????????????????????????????????????? pp410

?

Industrial software incl solar and windpower software ????????????????????????????????????????????????????????????? pp76

?

LANGUAGES

Translation & Localization Technologies?????????????????????????????????????????????????????????????????????????????????? pp63

?

?

BUSINESS WRITING

(2003-2009)

During my last years of business activities, I have been writing hundreds of consulting reports in several fields for my international clients. Here are a brief summarization:

?

AVIATION

Private space development???????? ?????????????????????????????????????????????????????????????????????????????????????? pp 340

Flying cars or Personal Air Vehicle?? ????????????????????????????????????????????????????????????????????????????????????????? pp 260

Business aircraft manufacturers in China?????????????????? ????????????????????????????????????????????????? pp360

Business aircraft manufacturers in the world???????????????? ??????????????????????????????????????????????? pp690

Business and general aviation China monthly and quarterly reports

?

ELECTRICITY POWER BUSINESS

China power monthly reports 12 issues,? total ???????????????????????????????????????????????????????????????????????? pp1200

China and world power generation equipment and systems? ??????????????????????????????????????????????????????? pp850

(steam turbines, gas turbines, gensets, hydroturbines, windturbines, etc)

?

HEALTHCARE DEVELOPMENT PROJECT WENZHOU

China Healthcare Development Report and Wenzhou New Hospital Development Project Plan ????? pp1600

The emergency medicine status report?????????????????????????????????????????????????????????????????????????????????????? pp90

?

LUXURIOUS MARKET

Luxurious Market China ??????????????????????????????????????????????????????????????????????????????????????????????????????? pp150

?

REAL ESTATE DEVELOPMENT

World and China Real Estate Development Industry Directory and Status Report????????????????????????? pp1500

?

SOLAR ENERGY BUSINESS

China solar monthly reports 36 issues,? total ?????????????????????????????????????????????????????????????????????????? pp 3600

?

THERMAL TECHNOLOGIES

Thermodynamic optimization????????????????????????????????????????????????????????????????????????????????????????????????? pp340

Water heater thermodynamic optimization? ??????????????????????????????????????????????????????????????????????????????????? pp100

Water heater safety guides?????????????????????????????????????????????????????????????????????????????????????????????????????? pp184

China Instant Electric Water Heater Technologies & Products????????????????????????????????????????????????????? pp10

Home Energy /Power Management System?????????????????????????????????????????????????????????????????????????????? pp14

Thermal technology company directory ?????????????????????????????????????????????????????????????????????????????????? pp410

?

WEALTHY REPORT

The richest people in the world – a comprehensive compilation ???????????????????????????????????????????????? pp1200

?

WEBMARKETING

Web marketing practical guide ??? ?????????????????????????????????????????????????????????????????????????????????????????? pp100

?

WINDFALL ANALYSIS

Windfall database China????????????????????????????????????????????????? ????????????????????????????????????????????????????? pp2500

?

WORLD CAPITAL MARKETS

World Capital Markets & Investment Consulting??????????????????????????????????????????????????????????????????????? pp80

?

YACHTS INDUSTRY

China yacht builders???????? ?????????????????????????????????????????????????????????????????????????????????????????????? pp 310

World yacht builders and other services??????? ????????????????????????????????????????????????????????????????????? pp 810

Yacht China Monthly Reports

?

OTHERS

(2006 – present))

Autobiography ??????????????????????? several thousands of pages in total??? to be prepared a decade later

About prayer?????????????????????????????????????????????????????????????????????????????? ????????????????????????????????????????? pp160

About religion?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp150

About SDA – the Seventh Day Adventist Church?????????????????????????????????????????????????????????????????????? pp35

America politics

China’s Internet

China politics???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? pp42

Exodus why?

Good Samaritan

Human rights in China

Lost opportunities, or rather, lost life

Market politics and a new China

My church experiences

My dream China

My experiences with PhD applications at ZD University

My testimony for Jesus

My zigzag road to faith

Persecution

Taxation

The Hukou problems

This is Hangzhou

This is Huzhou

My this 13 years

?

WEBSITES

?

In addition to the above writing, I have also developed many – perhaps a hundred - websites for various purposes. You may refer to the listing for a quick review. A website is also a kind of authoring and research, similar to a paper or a reporting.

?

THE EARLY DAYS (Before 2003)

???????????????????????????????????????????????????????

There might be another hundreds of essays, articles, papers, presentations or books, I can safely say, but the above is far than enough, therefore I would not bother to look for them, at least for now. A few years later, when I will resume my story, I may try to pick them up, wait a bit and be patient………..


Writing my Theses or Books

How to write my scientific books different from all the others so that people are enjoying reading math essays as they enjoy a love story, and on the other hand make my books as logical and systematic as possible. In addition, how to use the latest IT and Internet technologies so that its presentations can be more and more interactive with the readers as well. not just an one-sided information flow? These and more questions are concerned when writing my essays - albeit they willl not all be realized in the first papers I will be publishing. See this links for my considerations.
writing.html

RESEARCHES & AUTHORING

During the last years since 2003 I have written hundreds or even thousands of academic, business and commentary notes in the forms of papers, presentation slides, reports, booklets and books in the areas such as solar physics, thermodynamics, fluid dynamics, IT (incl cryptography), VLSI chip design and mathematics, incl math for VLSI design, among them are selected about 200+ pieces of quite comprehensive and indepth review and research as listed below.

I did not publish my academic writing results because none of these researches and writing are sponsored by any universities, institutions, other academic organizations and funds, for all of thousands of these organizations and professors have rejected my research incentives in the past. On the other hand, most of them are just my study aides or daily records, with exception of the business reports that are specifically prepared for a special purpose. Therefore they are mostly not written with the purpose of publication in mind. And my writing is to large extent only my hobby, for my own amusement, not for showing the world how capable I am. However, they are not necessary meant to be in low quality and just on contrary, they can be compatible with most published papers on the market.

Since 2003, especially during 2003 -2009 period, I鈥檝e written quite a number of business reporting and analyses in some selected industries. Some of them were commercialized and the rest were not marketed yet.

I鈥檝e also written some essays about the social life, politics 聽etc, all after 2010.

Thus, with the exception of my master鈥檚 thesis in 1989, all of my writings are dated back from 2003. Therefore what I have written before that and after 1978 when I first attended the university at the age of 15, are not known and are all lost. They might be yet another great number as well.

What will be coming up after this listing?

Well, my writing will certainly no more spread over so large a spectrum as before. I might still write some business reports, but only on requests of my clients, therefore that is unpredictable. I might still write a large number of essays about my life and the social events happening here and there and which will eventually be part of my autobiography. Apart from this, my overall writing will be slowed down or even suspended for the moment, because of my poor economic status. For during the last decade I did not earn money in lieu of my researches and my purse is dried up, therefore I need to fill it up and hence for some months or even years from now I might shift to business and leave little time to studies 鈥?an hour a day at most.

Nevertheless, my academic writing and researches will be sure focusing on the following three areas for the rest of my life:

  1. Graph theory for IC technologies, at the moment graph embedding (part of the extremal graph theory)
  2. New generations of IC technologies, just for followup, no way to conduct real research
  3. Software reverse engineering and hacking technologies or better put it networking security, for practical purpose.

I will no more write hundreds of them, but I will write some serious and useful essays in the above fields.

In addition to the above, as always I will continue to read books written by the greatest mathematicians, scientists, philosophers and novelists since the ancient days in Greek, Latin, Esperanto, English, French, Russian and German which I know to different degree. I want to know how they view the world and how they depict it. If you read the paper written by Albert Einstein, and other great scientists, you will pretty soon find out how they are different from those rubbish you will see on all the science journals.

If you don鈥檛 trust this list, I won鈥檛 care, nor will I try to argue with you, for I am not an ordinary person, thus judging from an ordinary person won鈥檛 be justified at all. But I can tell some of the truth already here. I read much faster than most people 鈥?I read books of a hundred pages just in an hours or so, depending on the easiness or difficulty of that book. And I also write much faster than most others. In an hour I can already write down an essay of a dozen pages. Therefore writing a 100-page book costs me only a week or so. If I write at full speed, I might write three thousand pages of all sorts of papers, essays or books in a year. Of course I cannot write mathematical article that quick. Math is different, one needs to spend hundred time more efforts to prepare for a same-length paper than for physical or social sciences. Math needs slow reading, slow digestion and slow writing. To conclude anyway, what others have to do in 10 years, I can do it in just a year, that鈥檚 where the difference is.

All books with a few exception are written in US English: a few in German and some others in Chinese.

Note that all page number calculations are rough estimation only.

ACADEMIC WRITING
(2007 鈥?present)
GRAPH THEORY
On the part of graph theory for VLSI design, I have written some papers on graph theory for VLSI routing/detailed routing/channel routing, hypergraph modeling for FPGA design, graph theory for advanced chip design particularly quantum computing, graph partitioning for VLSI design, graph embedding for VLSI (particularly quantum circuits) design, graph theory for 3d VLSI design etc. I have also prepared for several pure graph theoretic essays.

Pure & Applied Graph Theories for IC Design
Graph Theory 鈥?an Introduction聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp52
TSP 鈥?Traveling Salesman Problems, a comprehensive review聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp67
Graph actions/operations聽聽聽聽聽聽聽聽聽 聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp21
Graph/hypergraph clustering聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp60

Graph embedding / graph packing 聽/ Extremal Graph Theory 鈥?current focus聽聽聽聽聽聽聽 under preparation

Graph / Hypergrah features / instances / variables / parameters / Relations聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp14
Graph/Hypergraph File Format聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp8
Graph function / components / characteristics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp14
Graph partitioning聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp330
Graph-to-hypergraph transformation 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp20
Graph types聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 p269
Tree types聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 p112

Graph/hypergraph modelling for VLSI design聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp40
Graph theory for reconfigurable computing 鈥? Part I Introduction聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp37
Graph Theory for Reconfigurable Computing 鈥? Part II: Control & Data Flow Graphs聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp77

Hypergraph
Hypergraph types聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp126
Hypergraph Models for FPGA design聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp58

Combinatorics & Operational Optimizations聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp49

Graph Theory and the Worldwide Web
Graph theory and the Word Wide Web 鈥?Some Special Topics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp250
(topics include graph theory for the Internet, search engines algorithms, Google Maps and other Internet map systems, peer-to-peer(p2p) networking and the TOR router)

CHIP DESIGN
Chip design study notes - electronic theories and technologies聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp62
Chip design study notes - general聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100
Chip design study notes 鈥?physical design聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp89
Chip design study notes 鈥?routing聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp139
Chip design study notes 鈥?FPGA聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp56

New Generation of Information Processing and Computing
3D ICs聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp218
Membrane chips聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp33
Nano chips聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp82
Neural computing聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp36
Quantum chips聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp288聽聽聽聽聽聽聽聽聽聽
Other next generations of IC technologies incl.:聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 under preparation聽聽聽聽聽聽

  1. bio_DNA
  2. bio_cellular
  3. biocomputing
  4. carbon_nanotube
  5. dynamical systems computing
  6. gallium
  7. genetic
  8. germanium
  9. graphene
  10. indium
  11. molecular
  12. molybdenium
  13. nano_deep_submicron
  14. photonic/
    1. plasmonics
  15. resonant tunneling
  16. reversible computing/
  17. single electron/
  18. strained silicon/
  19. superconducting/

Spin Based Chips - current focus聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽 under preparation

MATHEMATICS 鈥?EARLIER RESEARCHES
Abstract Algebra 鈥?Encyclopedia聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp41
Boolean Algebra聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp53
Complex Analysis聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp56

Computational Analysis聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp135
Number Theory 鈥?a Review聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp19
Applied Number Theory聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp120
Primality Testing 鈥?Comprehensive Review聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp135
The AKS primality test algorithm 鈥?a review and improvement聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp196
Integer Factorization聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp45
Random Number Generation聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp55

Functional Analysis 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp255
Differential and integral equations & mathematical physical equations聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp76
Computational Geometry聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp33
Probability and statistics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp55
Ergodic Theory聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp43
Fast Fourier Transform聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp322

Cryptography 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp40
Quantum Cryptography聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp35
Postquantum Cryptography聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp75

Information technology聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp90
Computer Algorithm聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp160
Computer Complexity聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp230

Math for Search Engines聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp210
Math in Music Composition聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp66

Math formula tools聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp280

FLUID DYNAMICS
Nano fluid dynamics: Introduction, Review and Tutorial聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp450聽
Computational Fluiddynamics 鈥?an Introduction聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp138
Yachts Hydrodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp26

SOLAR RELATED RESEARCHES
鏈夊叧澶槼鐨勪竴鍒嚶犅犅犅犅犅犅犅犅犅犅?聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp84
About the Sun聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp400

Solar energy fundamentals聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp450聽
Solar thermal applications聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp270
Solar phtovoltaics 鈥?wafer, cells, modules, BOS etc聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp250
Space PV聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp165
Solar power systems聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp70
Other Solar Technologies
(thermoionic power generation / daylighting / litrospheres聽聽 / photoluminescence / solar hydrogen / solar to liquid fuel / solar photosynthesis)聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp40

Solar radiation theory聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 450聽
(Spectral radiation & the atmosphere, Solar radiation and the earth system, Solar radiation & climate change / global warming, Solar radiation and vegetation etc)
Solar radiation measurement technology聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 850

Solar Physics 鈥?an Introduction and Review聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp70
Solar Models (SSM 鈥?Standard Solar Models)聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp70
The Chromosphere聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10
The Corona聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp30
The Photosphere聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp20
Solar prominences聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10
Solar magnetic field聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp8
Solar Flares聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp25
Helioseismology聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp11
Solar neutrino problem聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp7
Sunspots聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp26
Solar wind聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp30

Solar aircrafts聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 2000聽聽聽聽聽聽聽聽
Solar airships聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 550
Solar sails / solar ion propulsion for far space ventures聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp180

Photoaging聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp170
Solar health and therapy聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp245

THERMODYNAMICS
Thermodynamics Terminology 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp32
Thermodynamics databases聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp30
Thermodynamics software聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp60
Thermodynamics events聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp50

Introduction to Thermodynamics 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp140
Modern thermodynamics- a comprehensive review, categorization and listing聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp267
Entropy聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp60
Equilibrium Thermodynamics聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp28
Non-Equilibrium & Non-linear Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp22
(Irreversible) Endoreversible Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp28
Dissipative structure theory聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp36
Finite Time Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp8
Negative Energy Spectrum Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp9
Advanced Thermodynamics and Statistical Physics聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp551
Physical chemistry 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp50

Mesoscopic Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp15
Nano 鈥搕hermodynamics 鈥?an overview聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp150
Quantum Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp8

Cryogenic thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp26

Computational Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp20

Thermodynamics of Polycomponent System聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp77
Thermodynamics of Porous Media聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10

Surface thermodynamics / thermodynamics of surface / interface thermodynamics / interfacial thermodynamics /
thermodynamics of interfaces聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp37

Network Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp9

Liquid & Process Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp8
Thermodynamics of Solutions/Solvation Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp21

Engineering Thermodynamics聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp87

Chemstry Thermodynamics聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp130
Thermodynamics of Chemical Equilibrium聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp55
Thermochemistry聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp64
Combustion thermodynamics聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp150

Thermodynamics of Materials聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp28

Thermodynamics of Crystalization聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp12
Metallurgical Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp33
Thermodynamics of Metals聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp80
Thermodynamics of Alloys聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp25
Phase Diagram of Alloys and their Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp22

Cosmos Physics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp279
Gravitational Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10
Thermodynamics of the cosmos (thermodynamics of the universe / cosmic thermodynamics) 聽聽聽聽聽 pp170
Celestial thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp25
Black hole thermodynamics聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp110
Solar Thermodynamics聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp90
Thermodynamics of the solar corona heating mechanism 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp270
Thermodynamics of solar wind聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp50

Earth Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10
Atmospheric Thermodynamics聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp46
Greenhouse Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp28
Ecosystem/Ecological Thermodynamics聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp894

Thermodynamics of Energy System聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp19
Solar energy and thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp25

Biological thermodynamics聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp150
Thermodynamics of Organisms 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp21

Thermodynamics and health聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp90
Thermodynamics of cancers (oncological thermodynamics / thermodynamic oncology / carcinothermodynamics)
Hierarchical Thermodynamics 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp8

Thermodynamics of Pharmaceuticals 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp15
pp790
Thermodynamics of economics聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp310
Thermoeconomics / Exergoeconomics聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp60

Sociological Thermodynamics聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp147
Bible and Thermodynamics聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp130
Divine Thermodynamics聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp43

Thermodynamics of Business Management聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp12
Thermodynamics in Finance聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp27

Thermodynamics of Ancient China聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10
Thermodynamics in Literatures聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp14
Thermodynamics in Politics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp28

LANGUAGES
脺berblick 眉ber deutsche Literatur 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp580

MISCELLANEOUS
Scientific research methodology聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp135
My science questions and proposals聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp28

WORLD SCIENTISTS DATABASES
The greatest scientists China and the world聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100
Mathematicians聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp89
Graph Theorists聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp425
Algebraists聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp16
Number Theorists 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp234
Thermodynamicists 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp220
Cosmological Thermodynamicists 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp220
Scientists in Biothermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp465
Scientists in Oncology and Oncological Thermodynamics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp550
Nano Thermal Scientists聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp31
NanoFluidics Researchers 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp70
Solar Radiation Scientists聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp70
SSM (Standard Solar Models) Scientists index聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp350

MY THESES

My Master thesis (1989): Studies on SO2 Pollution Control during coal combustion 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100

APPLICATION WRITING
(2003-present)

IT RELATED
Software reverse engineering聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽 under preparation
Network security or hacking technologies聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽 under preparation

Computer and OS Introduction聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp90
Computer and OS trouble shooting records and guides 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp375
Internet protocols 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp50
Linux systems聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp120
Programming guides聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp350
Databases聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp252
Servers聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp320
Online communications聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp250
Email security聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp210
Browser Security聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp35
Online multimedia聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp350
GoogleMaps Introduction聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp110
WAP 鈥?Wireless Application Protocols 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100
Website development guides聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp240
Cryptology review聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp76
Cryptological platforms聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp50
CryptoChina Report聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100
Internet freedom 鈥?a series of Internet access technology guides 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp2300
VPN review and technologies聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp410

Industrial software incl solar and windpower software 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp76

LANGUAGES
Translation & Localization Technologies聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp63

BUSINESS WRITING
(2003-2009)
During my last years of business activities, I have been writing hundreds of consulting reports in several fields for my international clients. Here are a brief summarization:

AVIATION
Private space development聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 340
Flying cars or Personal Air Vehicle聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 260
Business aircraft manufacturers in China聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp360
Business aircraft manufacturers in the world聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp690
Business and general aviation China monthly and quarterly reports

ELECTRICITY POWER BUSINESS
China power monthly reports 12 issues,聽 total 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp1200
China and world power generation equipment and systems聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp850
(steam turbines, gas turbines, gensets, hydroturbines, windturbines, etc)

HEALTHCARE DEVELOPMENT PROJECT WENZHOU
China Healthcare Development Report and Wenzhou New Hospital Development Project Plan 聽聽聽聽聽 pp1600
The emergency medicine status report聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp90

LUXURIOUS MARKET
Luxurious Market China 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp150

REAL ESTATE DEVELOPMENT
World and China Real Estate Development Industry Directory and Status Report聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp1500

SOLAR ENERGY BUSINESS
China solar monthly reports 36 issues,聽 total 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 3600

THERMAL TECHNOLOGIES
Thermodynamic optimization聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp340
Water heater thermodynamic optimization聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100
Water heater safety guides聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp184
China Instant Electric Water Heater Technologies & Products聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp10
Home Energy /Power Management System聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp14
Thermal technology company directory 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp410

WEALTHY REPORT
The richest people in the world 鈥?a comprehensive compilation 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp1200

WEBMARKETING
Web marketing practical guide 聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp100

WINDFALL ANALYSIS
Windfall database China聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp2500

WORLD CAPITAL MARKETS
World Capital Markets & Investment Consulting聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp80

YACHTS INDUSTRY
China yacht builders聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 310
World yacht builders and other services聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp 810
Yacht China Monthly Reports

OTHERS
(2006 鈥?present))
Autobiography 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 several thousands of pages in total聽聽聽 to be prepared a decade later
About prayer聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp160
About religion聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp150
About SDA 鈥?the Seventh Day Adventist Church聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp35
America politics
China鈥檚 Internet
China politics聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽聽 pp42
Exodus why?
Good Samaritan
Human rights in China
Lost opportunities, or rather, lost life
Market politics and a new China
My church experiences
My dream China
My experiences with PhD applications at ZD University
My testimony for Jesus
My zigzag road to faith
Persecution
Taxation
The Hukou problems
This is Hangzhou
This is Huzhou
My this 13 years

WEBSITES

In addition to the above writing, I have also developed many 鈥?perhaps a hundred - websites for various purposes. You may refer to the listing for a quick review. A website is also a kind of authoring and research, similar to a paper or a reporting.

THE EARLY DAYS (Before 2003)
???????????????????????????????????????????????????????
There might be another hundreds of essays, articles, papers, presentations or books, I can safely say, but the above is far than enough, therefore I would not bother to look for them, at least for now. A few years later, when I will resume my story, I may try to pick them up, wait a bit and be patient鈥︹�︹�?.

See also:

writing_style.htm


My writing style

Introduction

interactive

attractive and intersting 引人入胜 like love story

The Aim of Thesis

The Scope of Thesis

Research Hierarchical Diagram

Related Math Branches or Sub-Disciples

Presentation Styles

Different versions

Online web version with interactive functions

An internal, comprehensive version with all details and source data and information

A coloful presentation slide

An abstract for publishing in journals and web sites

===================================

Easy to read even for laymen and like lovestory

Short texts

Every definition shall be expressed in bold letters

Electronically available only

Electronic formats

Strictly local yet

Interactive

Use as much as drawings, pictures.animations as possible to accompany or replace texts

用各种IT技术

表

Charts

Graphs

Pies

Drawings

Pictures图

三维图标

EBOOKS IN CHM, HLP, EXE OR OTHERS

SLIDES

PPT

OTHER FORMS OF SLIDES

Movies and Animations

web audio and video

3D

VRML

Flash SWF Slides

FLASH MOVIES

streaming

QUICKTIME

REALMEDIA

WINDOWSMEDIA???

WEB PORTAL

web incl web2.0

html

php

java

SOFTWARE

DATABASE

MOBILE AND HANDHELD DEVICES

DVD/VCDs

Structures, Mode or System of Theorems

Newton or Euclid styles

Give every definiyion, axiom, proposition, theorem, corrolary etc a serial number and a name

conventions or notations

Common Notions

Definitions

Определение

Ορισμ??

Terms

Terminology

Etymology

Encyclopedia

Glossary

Lexicon

Nomenclature

Abbreviations

List of Symbols

Index

Axiom

аксиома

Principles

Assertion

Assumptions

Hypothesis

Hypothese

Vermutung

Annahme

Conjecture

Suggestion

Predicates

Theory

Theorem

Théorème

Теорема

ΘΕΩΡΗΜΑ

Θε?ρημα

A proposition of major importance is called a theorem.

a theorem is a deeper culmination of ideas,

Laws

Satz

Hauptsatz

Grundsatz

Gesetz

Rules

Statement

Caveat

Следствие

Замечание

Proposition

If we can prove a statement true, then that statement is called a proposition.

a proposition is a less important or less fundamental assertion,

A proposition of major importance is called a theorem.

Porism

Lemma

If a theorem is not particularly interesting, but is useful in proving an interesting statement,

then it’s often called a lemma. This one is found in Euclid’s Elements.

Sometimes instead of proving a theorem or proposition all at once, we break the proof down into modules; that is, we prove several supporting propositions, which are called lemmas, and use the results of these propositions to prove the main result.

a lemma is something that we will use later in this book to prove a proposition or theorem,

Hilfssatz

Zusatz

Lemme

Лемма

Замечание

Παρατ?ρηση

Scholium

Claim

Fact

Conics

Postulations

ΠΟΡΙΣΜΑ

Collonary

A corollary is a theorem that logically follows very simply from a theorem. A corollary is a theorem that logically follows very simply from a theorem. Sometimes it follows from part of the proof of a theorem rather than from the statement of the theorem. In any case, it should be easy to

see why it’s true.

If we can prove a proposition or a theorem, we will often, with very little effort, be able to derive other related propositions called corollaries.

a corollary is an easy consequence of a proposition, theorem, or lemma.

Korollar

Corollaire

Πρ?ταση

Conclusions

Folgerung

Behauptung

Consequence

Утверждение

Proof

Beweis

Comment

Observation

Note

Remark

Bemerkung

Remarque

Equations

Formulas

Literature Reference / Bibliography

  • Books
  • Databases
  • Multimedia
  • Websites
  • Theses
  • Proceedings
  • Papers
  • Presentations/Slides

Definitions. Terminology, Signs and Symbols

任何科学都从概念开始。

术语

名辞

定语

Nomenclature

List of symbols

Definitions

Assertion

Hypothesis

Terms

Terminology

Alphabets? and Signs

详细规划和说明下列字母的意义和用途：拉丁字母，希腊字母，俄文字母和希伯来字母。

同时要符合国内外学术界的惯例和习惯，又要强调概念清晰，唯一，统一，易于理解和明确。

花体字母

空心体字母

重体字母

斜体字母

Latin

Greek

Hebrew

Russian

Nomenclature

Nomenclature is a term that applies to either a list of names or terms, or to the system of principles, procedures and terms related to naming—which is the assigning of a word or phrase to a particular object, event, or property. The principles of naming vary from the relatively informal conventions of everyday speech to the internationally-agreed principles, rules and recommendations that govern the formation and use of the specialist terms used in scientific and other disciplines. ... nomenclature concerns itself more with the rules and conventions that are used for the formation of names (wikipedia)

Notation

We will use ?to denote the base 2 logarithm instead of ?? or lgn. Base 10 logarithms and natural logarithms will be denoted as ? n and ?respectively.

The notation ord r (a) represents the order of a modulo r, which is the smallest positive integer k, such that ? ?1(modr).

The notation (r) will be used to represent Euler’s totient function, which is defined as the number of positive integers less than or equal to r that are relatively prime to r.

The notation f(x) ≡g(x)mod(h(x),p) is used throughout to mean that f(x)=g(x) in the ring Zp[x]/(h(x)). In some cases, p will be prime and will have degree d and be irreducible in Zp(x), ?so that Zp[x]/(h(x)).will be a finite field of order .

Notation: p(x) ≡ q(x) mod (h(x), n) means that h(x)|p(x) ? q(x) all coefficients are taken modulo n

Time complexity functions will be written in “big-O” notation. A function f(x) is considered to be O (g(x))(pronounced “big-oh of g”) if given some function g(x) there exists a constant c such that |f(x)|≤c|g (x)|? for all values of x0, where x is defined to be the binary input length of n.

The function M(n) will be used to represent the time complexity function for multiplication.

Definitions

Diophantine equation

Euclidean Algorithm? Extended Euclid Algorithm?

The greatest common divisor GCD (or greatest common factor GCF)

List of theorems, formulars and equations

List of abbreviations

List of people mentioned in the book

Index

Explanations

Fonts

italic: for scalers;

Bold italic: for vectors in D-dimensional vector space, D = 1, 2, 3;

Boldface: for vectors in Rb ;

Sans serif: for operators or second rank tensors (matrices);

Bold sans serif: for matrices with vector/tensor elements;

BLA C K B O A RD BO LD : for vector space.

List of symbols

Sub and super scripts

Marks

@↑↓?

≈≠≡?∩∑∏ ?≈∵∴⊥∥≌∽∈

词冠???

10 12? Τ Τερα 核 ?10 9 Giga ?京? 10 -9? Nano ?钎? 10 -12 Pico

UNITS

Units designation

Atm? BYU? bar etc

Constants


This file was created on December 01, 2017, 08:23

scientists
├Aristotle METAPHYSICS p135.pdf
├Cauchy Cours de analyse p432.pdf
├Dalton New system of chemical philosophy p600.pdf
├Einstein Brownian Movement.pdf
├Einstein Relativity The Special and General Theory p56.pdf
├Einstein Relativity The Special and the General Theory A Popular Exposition, 3rd ed. P154.pdf
├Einstein The Meaning of Relativity p134.pdf
├Hayek The Road to Serfdom p266.pdf
├Malthus An Essay on the Principle of population p134.pdf
├MAXWELL A treatise on electricity p518.pdf
├Newton Mathematical Principles of Natural Philosophy p594.pdf
├Plato Republic p484.pdf
├Plato Republic p509.pdf
├Poincare Papers on Topology p281.pdf
├Poincare The Value of science p124.pdf
├Popper The Logic of Scientific Discovery p545.pdf
├Rawls A Theory of Justice Revised Edition p561.pdf
└Smith Wealth of nations p754.pdf


This file was created on December 01, 2017, 09:34

graph_algorithms_codes
├<ccppcsharp>
│	├echo-akash.cpp
│	├echo-akash.cpp.bak
│	├graph.c
│	├spl0i7.cpp
│	└spl0i7.cpp.bak
├Dasgupta Algorithms p318.pdf
├Demaine Graph Algorithms p500.pdf
├<Dijkstra_shortest_path_algorithm>
│	└Peyer A Generalization of Dijkstra's Shortest Path Algorithm with Applications to VLSI Routing p24.pdf
├<haskell>
│	├ericnething.hs
│	├ericnething.hs.bak
│	├fgl-5.4.2.2.tar.gz
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│	│	├.gitignore
│	│	├.travis.yml
│	│	├ChangeLog
│	│	├<Data>
│	│	│	└<Graph>
│	│	│	  	├<Inductive>
│	│	│	  	│	├Basic.hs
│	│	│	  	│	├Example.hs
│	│	│	  	│	├Graph.hs
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│	│	│	  	│	│	├Heap.hs
│	│	│	  	│	│	├Queue.hs
│	│	│	  	│	│	├RootPath.hs
│	│	│	  	│	│	└Thread.hs
│	│	│	  	│	├<Monad>
│	│	│	  	│	│	├IOArray.hs
│	│	│	  	│	│	└STArray.hs
│	│	│	  	│	├Monad.hs
│	│	│	  	│	├NodeMap.hs
│	│	│	  	│	├PatriciaTree.hs
│	│	│	  	│	├<Query>
│	│	│	  	│	│	├ArtPoint.hs
│	│	│	  	│	│	├BCC.hs
│	│	│	  	│	│	├BFS.hs
│	│	│	  	│	│	├DFS.hs
│	│	│	  	│	│	├Dominators.hs
│	│	│	  	│	│	├GVD.hs
│	│	│	  	│	│	├Indep.hs
│	│	│	  	│	│	├MaxFlow.hs
│	│	│	  	│	│	├MaxFlow2.hs
│	│	│	  	│	│	├Monad.hs
│	│	│	  	│	│	├MST.hs
│	│	│	  	│	│	├SP.hs
│	│	│	  	│	│	└TransClos.hs
│	│	│	  	│	├Query.hs
│	│	│	  	│	└Tree.hs
│	│	│	  	└Inductive.hs
│	│	├<fgl-arbitrary>
│	│	│	├ChangeLog
│	│	│	├<Data>
│	│	│	│	└<Graph>
│	│	│	│	  	└<Inductive>
│	│	│	│	  	  	└Arbitrary.hs
│	│	│	├fgl-arbitrary.cabal
│	│	│	├LICENSE
│	│	│	├Setup.hs
│	│	│	└<test>
│	│	│	  	└TestSuite.hs
│	│	├fgl.cabal
│	│	├LICENSE
│	│	├README.md
│	│	├Setup.hs
│	│	└<test>
│	│	  	├benchmark.hs
│	│	  	├<Data>
│	│	  	│	└<Graph>
│	│	  	│	  	└<Inductive>
│	│	  	│	  	  	├<Graph>
│	│	  	│	  	  	│	└Properties.hs
│	│	  	│	  	  	├Proxy.hs
│	│	  	│	  	  	└<Query>
│	│	  	│	  	  	  	└Properties.hs
│	│	  	├test.hs
│	│	  	└TestSuite.hs
│	├fgl-5.6.0.0.tar.gz
│	├fgl-5.6.0.0.zip
│	└fgl-master.zip
├<java>
│	├BellmanFord.java
│	├Digraph.java
│	├dijkstra.java
│	├EdgeWeightedDigraph.java
│	├Graph.java
│	├Graph2.java
│	├Graph4
│	├Graph4.java
│	├imamhidayat92.java
│	├imamhidayat92.java.bak
│	├MinCostMaxFlow.java
│	├mozi22.java
│	├mozi22.java.bak
│	├Prim.java
│	├<Sedgewick>
│	│	├AdjMatrixGraph.java.html
│	│	├<AdjMatrixGraph.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├AllPaths.java.html
│	│	├<AllPaths.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├Biconnected.java.html
│	│	├<Biconnected.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├Bipartite.java.html
│	│	├<Bipartite.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├BreadthFirstPaths.java.html
│	│	├<BreadthFirstPaths.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├Bridge.java.html
│	│	├<Bridge.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├CC.java.html
│	│	├<CC.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├Cycle.java.html
│	│	├<Cycle.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├DepthFirstPaths.java.html
│	│	├<DepthFirstPaths.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├Graph.java.html
│	│	├<Graph.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├NonrecursiveDFS.java.html
│	│	├<NonrecursiveDFS.java_files>
│	│	│	├ga.js
│	│	│	└java.css
│	│	├Sedgewick.txt
│	│	├Undirected Graphs.htm
│	│	└<Undirected Graphs_files>
│	│	  	├adjacency-lists.png
│	│	  	├algs4.css
│	│	  	├analytics.js
│	│	  	├cc-api.png
│	│	  	├cover-analysis-of-algorithms.png
│	│	  	├cover.png
│	│	  	├cover_002.png
│	│	  	├forest.png
│	│	  	├ga.js
│	│	  	├graph-anatomy.png
│	│	  	├graph-api.png
│	│	  	├graph-input.png
│	│	  	├graph.png
│	│	  	├maze14.png
│	│	  	├maze22.png
│	│	  	├minecraft-maze.png
│	│	  	├movies.png
│	│	  	├paths-api.png
│	│	  	├routes.png
│	│	  	├search-api.png
│	│	  	├swfobject.js
│	│	  	├symbol-graph-api.png
│	│	  	├symbol-graph.png
│	│	  	└tree.png
│	├Sumitjain.java
│	├Sumitjain.java.bak
│	├Tareq-SiSalem.java
│	├Tareq-SiSalem.java.bak
│	├thmain.zip
│	├yuxiangdai.java
│	└yuxiangdai.java.bak
├<jupyter-notebook>
│	├anirudhjayaraman.ipynb
│	├anirudhjayaraman.ipynb.bak
│	├FredtCh1996.ipynb
│	├FredtCh1996.ipynb.bak
│	├isurudilhansenanayaka.ipynb
│	├isurudilhansenanayaka.ipynb.bak
│	├ukc.ipynb
│	└ukc.ipynb.bak
├Kepner Graph Algorithms in the Language of Linear Algebra p372.pdf
├<lisps>
│	└Schulte.txt
├<perl>
│	├<Graph-0.9704>
│	│	├Changes
│	│	├DESIGN
│	│	├<lib>
│	│	│	├<Graph>
│	│	│	│	├<AdjacencyMap>
│	│	│	│	│	├Heavy.pm
│	│	│	│	│	├Light.pm
│	│	│	│	│	└Vertex.pm
│	│	│	│	├AdjacencyMap.pm
│	│	│	│	├AdjacencyMatrix.pm
│	│	│	│	├Attribute.pm
│	│	│	│	├BitMatrix.pm
│	│	│	│	├Directed.pm
│	│	│	│	├Matrix.pm
│	│	│	│	├MSTHeapElem.pm
│	│	│	│	├SPTHeapElem.pm
│	│	│	│	├<TransitiveClosure>
│	│	│	│	│	└Matrix.pm
│	│	│	│	├TransitiveClosure.pm
│	│	│	│	├<Traversal>
│	│	│	│	│	├BFS.pm
│	│	│	│	│	└DFS.pm
│	│	│	│	├Traversal.pm
│	│	│	│	├Undirected.pm
│	│	│	│	└UnionFind.pm
│	│	│	├Graph.pm
│	│	│	├Graph.pod
│	│	│	└<Heap071>
│	│	│	  	├Elem.pm
│	│	│	  	└Fibonacci.pm
│	│	├Makefile.PL
│	│	├MANIFEST
│	│	├META.json
│	│	├META.yml
│	│	├README
│	│	├RELEASE
│	│	├<t>
│	│	│	├00_use.t
│	│	│	├01_isa.t
│	│	│	├02_trap.t
│	│	│	├03_derived.t
│	│	│	├04_dgraph.t
│	│	│	├05_ugraph.t
│	│	│	├06_new.t
│	│	│	├07_gen.t
│	│	│	├08_stringify.t
│	│	│	├09_eq.t
│	│	│	├10_has_vertices.t
│	│	│	├11_vertices.t
│	│	│	├12_has_vertex.t
│	│	│	├13_add_vertex.t
│	│	│	├14_delete_vertex.t
│	│	│	├15_has_edges.t
│	│	│	├16_edges.t
│	│	│	├17_has_edge.t
│	│	│	├18_add_edge.t
│	│	│	├19_delete_edge.t
│	│	│	├20_countvertexed.t
│	│	│	├21_multivertexed.t
│	│	│	├22_refvertexed.t
│	│	│	├23_hypervertexed.t
│	│	│	├24_mixvertexed.t
│	│	│	├25_countedged.t
│	│	│	├26_multiedged.t
│	│	│	├27_omnidirected.t
│	│	│	├28_hyperedged.t
│	│	│	├29_uniqedged.t
│	│	│	├30_mixedged.t
│	│	│	├31_hypervertex.t
│	│	│	├32_hypervertex_edges.t
│	│	│	├33_hyperedge.t
│	│	│	├34_omnivertexed.t
│	│	│	├35_uniqvertexed.t
│	│	│	├36_omniuniqvertexed.t
│	│	│	├37_hypervertex_implicit.t
│	│	│	├38_vertices_at.t
│	│	│	├39_edges_at.t
│	│	│	├40_edges_from.t
│	│	│	├41_edges_to.t
│	│	│	├42_add_path.t
│	│	│	├43_has_path.t
│	│	│	├44_delete_path.t
│	│	│	├45_add_cycle.t
│	│	│	├46_has_cycle.t
│	│	│	├47_delete_cycle.t
│	│	│	├48_get_vertex_count.t
│	│	│	├49_get_edge_count.t
│	│	│	├50_vertex_attributes.t
│	│	│	├51_multivertex_attributes.t
│	│	│	├52_edge_attributes.t
│	│	│	├53_multiedge_attributes.t
│	│	│	├54_graph_attributes.t
│	│	│	├55_attributes.t
│	│	│	├56_neighbourhood.t
│	│	│	├57_degree.t
│	│	│	├58_connections.t
│	│	│	├59_dfs.t
│	│	│	├60_bfs.t
│	│	│	├61_connected.t
│	│	│	├62_bcc.t
│	│	│	├63_scc.t
│	│	│	├64_mst.t
│	│	│	├65_ref.t
│	│	│	├66_simple.t
│	│	│	├67_copy.t
│	│	│	├68_transpose.t
│	│	│	├69_complete.t
│	│	│	├70_complement.t
│	│	│	├71_spt.t
│	│	│	├72_transitive.t
│	│	│	├73_diameter.t
│	│	│	├74_random.t
│	│	│	├75_attribute_array.t
│	│	│	├76_attribute_hash.t
│	│	│	├77_adjacency.t
│	│	│	├78_expect.t
│	│	│	├79_unionfind.t
│	│	│	├80_isomorphic.t
│	│	│	├81_dump.t
│	│	│	├82_cycle.t
│	│	│	├83_bitmatrix.t
│	│	│	├84_all_cessors.t
│	│	│	├85_subgraph.t
│	│	│	├99_misc.t
│	│	│	├g02_00directed.t
│	│	│	├g02_01undirected.t
│	│	│	├g02_02multiple.t
│	│	│	├g02_03degree.t
│	│	│	├g02_04attribute.t
│	│	│	├g02_05copy.t
│	│	│	├g02_06transpose.t
│	│	│	├g02_07complete.t
│	│	│	├g02_08complement.t
│	│	│	├g02_09scc.t
│	│	│	├MyDGraph.pm
│	│	│	├MyGraph.pm
│	│	│	├MyUGraph.pm
│	│	│	├pod-coverage.t
│	│	│	├pod.t
│	│	│	├simple.pl
│	│	│	├u_an_uf.t
│	│	│	├u_at1.t
│	│	│	├u_at2.t
│	│	│	├u_at3.t
│	│	│	├u_bb_rv.t
│	│	│	├u_bf.t
│	│	│	├u_bill.t
│	│	│	├u_bo_ap1.t
│	│	│	├u_bo_ap2.t
│	│	│	├u_bo_apx.t
│	│	│	├u_cd_rv.t
│	│	│	├u_dl_uf.t
│	│	│	├u_jh_va.t
│	│	│	├u_mn_va.t
│	│	│	├u_mo_rv.t
│	│	│	├u_ng_mst.t
│	│	│	├u_ng_path.t
│	│	│	├u_ng_scc.t
│	│	│	├u_rb_cc.t
│	│	│	├u_re_sd.t
│	│	│	├u_ro_ra.t
│	│	│	├u_sc_me.t
│	│	│	├u_sn_sva.t
│	│	│	├u_te_ae.t
│	│	│	├u_te_ea.t
│	│	│	└u_te_me.t
│	│	├TODO
│	│	└<util>
│	│	  	├cover.sh
│	│	  	├grand.pl
│	│	  	├renum.pl
│	│	  	├size.pl
│	│	  	└srand.pl
│	└Graph-0.9704.tar.gz
├<python>
│	├anonym.py
│	├anonym.py.bak
│	├Ben.py
│	├Czepiel.py
│	├dijkstra.py
│	├DijkstraShortestPathAlgorithm.py
│	├DijkstraShortestPathAlgorithm.py.bak
│	├gndemo.py
│	├graphs.py
│	├Klein graph2.py
│	├Klein graph2.py.bak
│	├marazmiki.py
│	├marazmiki.py.bak
│	├metis.py
│	├mst.py
│	├prim.py
│	├Python Software Foundation.py
│	├Scellato.txt
│	├shintoishere (2).py
│	├shintoishere (2).py.bak
│	├shintoishere.py
│	├spl0i7.py
│	├spl0i7.py.bak
│	├Tschacher.py
│	├Tschacher.py.bak
│	├Udacity Creating Network Graphs with Python.docx
│	├vevurka.py
│	├vevurka.py.bak
│	└zzzinfo.txt
└<ruby>
      ├<rgl-master>
      │	├.codeclimate.yml
      │	├.gitignore
      │	├.travis.yml
      │	├.yardopts
      │	├ChangeLog
      │	├<examples>
      │	│	├canvas.rb
      │	│	├examples.rb
      │	│	├insel_der_tausend_gefahren.rb
      │	│	├<north>
      │	│	│	├g.10.0.graphml
      │	│	│	├g.10.1.graphml
      │	│	│	├g.10.11.graphml
      │	│	│	├g.10.12.graphml
      │	│	│	├g.10.13.graphml
      │	│	│	├g.10.14.graphml
      │	│	│	├g.10.15.graphml
      │	│	│	├g.10.16.graphml
      │	│	│	├g.10.17.graphml
      │	│	│	├g.10.19.graphml
      │	│	│	├g.10.2.graphml
      │	│	│	├g.10.20.graphml
      │	│	│	├g.10.22.graphml
      │	│	│	├g.10.24.graphml
      │	│	│	├g.10.25.graphml
      │	│	│	├g.10.27.graphml
      │	│	│	├g.10.28.graphml
      │	│	│	├g.10.29.graphml
      │	│	│	├g.10.3.graphml
      │	│	│	├g.10.30.graphml
      │	│	│	├g.10.31.graphml
      │	│	│	├g.10.34.graphml
      │	│	│	├g.10.37.graphml
      │	│	│	├g.10.38.graphml
      │	│	│	├g.10.39.graphml
      │	│	│	├g.10.4.graphml
      │	│	│	├g.10.40.graphml
      │	│	│	├g.10.41.graphml
      │	│	│	├g.10.42.graphml
      │	│	│	├g.10.45.graphml
      │	│	│	├g.10.46.graphml
      │	│	│	├g.10.5.graphml
      │	│	│	├g.10.50.graphml
      │	│	│	├g.10.56.graphml
      │	│	│	├g.10.57.graphml
      │	│	│	├g.10.58.graphml
      │	│	│	├g.10.6.graphml
      │	│	│	├g.10.60.graphml
      │	│	│	├g.10.61.graphml
      │	│	│	├g.10.62.graphml
      │	│	│	├g.10.68.graphml
      │	│	│	├g.10.69.graphml
      │	│	│	├g.10.7.graphml
      │	│	│	├g.10.70.graphml
      │	│	│	├g.10.71.graphml
      │	│	│	├g.10.72.graphml
      │	│	│	├g.10.74.graphml
      │	│	│	├g.10.75.graphml
      │	│	│	├g.10.78.graphml
      │	│	│	├g.10.79.graphml
      │	│	│	├g.10.8.graphml
      │	│	│	├g.10.80.graphml
      │	│	│	├g.10.82.graphml
      │	│	│	├g.10.83.graphml
      │	│	│	├g.10.85.graphml
      │	│	│	├g.10.86.graphml
      │	│	│	├g.10.88.graphml
      │	│	│	├g.10.89.graphml
      │	│	│	├g.10.9.graphml
      │	│	│	├g.10.90.graphml
      │	│	│	├g.10.91.graphml
      │	│	│	├g.10.92.graphml
      │	│	│	├g.10.93.graphml
      │	│	│	├g.10.94.graphml
      │	│	│	├g.12.8.graphml
      │	│	│	├g.14.9.graphml
      │	│	│	└Graph.log
      │	│	├north.rb
      │	│	├north2.rb
      │	│	└rdep-rgl.rb
      │	├Gemfile
      │	├<images>
      │	│	├example.jpg
      │	│	├module_graph.jpg
      │	│	└rgl_modules.png
      │	├<lib>
      │	│	└<rgl>
      │	│	  	├adjacency.rb
      │	│	  	├base.rb
      │	│	  	├bellman_ford.rb
      │	│	  	├bidirectional.rb
      │	│	  	├bipartite.rb
      │	│	  	├condensation.rb
      │	│	  	├connected_components.rb
      │	│	  	├dijkstra.rb
      │	│	  	├dijkstra_visitor.rb
      │	│	  	├dot.rb
      │	│	  	├edge_properties_map.rb
      │	│	  	├edmonds_karp.rb
      │	│	  	├graphxml.rb
      │	│	  	├graph_iterator.rb
      │	│	  	├graph_visitor.rb
      │	│	  	├graph_wrapper.rb
      │	│	  	├implicit.rb
      │	│	  	├mutable.rb
      │	│	  	├path_builder.rb
      │	│	  	├prim.rb
      │	│	  	├rdot.rb
      │	│	  	├topsort.rb
      │	│	  	├transitivity.rb
      │	│	  	├transitiv_closure.rb
      │	│	  	└traversal.rb
      │	├Rakefile
      │	├<rakelib>
      │	│	└dep_graph.rake
      │	├README.md
      │	├rgl.gemspec
      │	├<script>
      │	│	└test_all
      │	└<test>
      │	  	├bellman_ford_test.rb
      │	  	├bipartite_test.rb
      │	  	├components_test.rb
      │	  	├cycles_test.rb
      │	  	├dijkstra_issue24_test.rb
      │	  	├dijkstra_test.rb
      │	  	├directed_graph_test.rb
      │	  	├dot_test.rb
      │	  	├edge_properties_map_test.rb
      │	  	├edge_test.rb
      │	  	├edmonds_karp_test.rb
      │	  	├graph_test.rb
      │	  	├graph_xml_test.rb
      │	  	├implicit_test.rb
      │	  	├prim_test.rb
      │	  	├rdot_test.rb
      │	  	├test_helper.rb
      │	  	├transitivity_test.rb
      │	  	├traversal_test.rb
      │	  	└undirected_graph_test.rb
      └rgl-master.zip


This file was created on December 01, 2017, 09:27

graph_datastructures_algorithms_codes
├<ccppcsharp>
│	├<lists>
│	│	├Ajinkya-Sonawane.c
│	│	├Ajinkya-Sonawane.c.bak
│	│	├anonym.c
│	│	├anonym.c.bak
│	│	├anonym1.c
│	│	├anonym1.c.bak
│	│	├arbhie2581.cpp
│	│	├arbhie2581.cpp.bak
│	│	├Barnwal.c
│	│	├Bhojasia.c
│	│	├Bhojasia.c.bak
│	│	├Chhabra.cpp
│	│	├Chhabra.cpp.bak
│	│	├Coleman.cpp
│	│	├Coleman.cpp.bak
│	│	├Daal.cpp
│	│	├Daal.cpp.bak
│	│	├Elkan.c
│	│	├Elkan.c.bak
│	│	├ferenczi.cpp
│	│	├geeksforgeeks.cpp
│	│	├geeksforgeeks.cpp.bak
│	│	├iokon.cpp
│	│	├iokon.cpp.bak
│	│	├Jamal.cpp
│	│	├Jamal.cpp.bak
│	│	├Manish.cpp
│	│	├Manish.cpp.bak
│	│	├Morris.c
│	│	├Morris.c.bak
│	│	├NiclasJonsson.cpp
│	│	├NiclasJonsson.cpp.bak
│	│	├quickgrid.cpp
│	│	├quickgrid.cpp.bak
│	│	├quickgrid2.cpp
│	│	├quickgrid2.cpp.bak
│	│	├quickgrid3.cpp
│	│	├quickgrid3.cpp.bak
│	│	├quickgrid4.cpp
│	│	├quickgrid4.cpp.bak
│	│	├sanfoundry.cpp
│	│	├sanfoundry.cpp.bak
│	│	├Sangam.cpp
│	│	├Ullman.cpp
│	│	├Ullman.cpp.bak
│	│	├Wagner.c
│	│	├Wagner.c.bak
│	│	├Wagner1.c
│	│	└Wagner1.c.bak
│	├<matrices>
│	│	├adj-matrix-code.txt
│	│	├AdjacencyMatrixGraphImp.cpp
│	│	├AlgoList.cpp
│	│	├AlgoList.cpp.bak
│	│	├anonym.cpp
│	│	├anonym.cpp.bak
│	│	├anonym1.cpp
│	│	├anonym1.cpp.bak
│	│	├anonym2.c
│	│	├anonym2.c.bak
│	│	├anonym3.cpp
│	│	├anonym3.cpp.bak
│	│	├anonym4.c
│	│	├anonym4.c.bak
│	│	├anonym5.c
│	│	├anonym5.c.bak
│	│	├cguy3.c
│	│	├cguy3.c.bak
│	│	├Daal.cpp
│	│	├Daal.cpp.bak
│	│	├dharmendra.c
│	│	├dharmendra.c.bak
│	│	├erip.cpp
│	│	├erip.cpp.bak
│	│	├JohnLinux.cpp
│	│	├JohnLinux.cpp.bak
│	│	├Morris.cpp
│	│	├Morris.cpp.bak
│	│	├notes.cpp
│	│	├notes.cpp.bak
│	│	├Pokhrel.cpp
│	│	├Pokhrel.cpp.bak
│	│	├Sinha.cpp
│	│	├Sinha.cpp.bak
│	│	├Soni.c
│	│	├Soni.c.bak
│	│	├Subedi.cpp
│	│	├Subedi.cpp.bak
│	│	├tkc.cpp
│	│	├tkc.cpp.bak
│	│	├Trung.c
│	│	├Trung.c.bak
│	│	├Ullman.cpp
│	│	└Ullman.cpp.bak
│	└<transformation>
│	  	├kuruma.cpp
│	  	├kuruma.cpp.bak
│	  	├Ouda.cpp
│	  	└Ouda.cpp.bak
├graph_datastructures_algorithms_codes.htm
├<haskell>
├<java>
│	├<lists>
│	│	├AdjacencyList.java
│	│	├AdjacencyList.java.bak
│	│	├AdjacencyListGraph(1).java
│	│	├AdjacencyListGraph.java
│	│	├AdjacencyListGraph3.java
│	│	├AdjListsGraph.java
│	│	├Anonym1.java
│	│	├Anonym1.java.bak
│	│	├Anonym2.java
│	│	├Anonym2.java.bak
│	│	├Anonym3.java
│	│	├Anonym3.java.bak
│	│	├Anonym4.java
│	│	├Anonym6.java
│	│	├Anonym7.java
│	│	├Anonym7.java.bak
│	│	├AnujPrashar.java
│	│	├AnujPrashar.java.bak
│	│	├Barnwal.java
│	│	├Barnwal.java.bak
│	│	├clrs-java.java
│	│	├clrs-java.java.bak
│	│	├DeepBlackMagic.java
│	│	├DeepBlackMagic.java.bak
│	│	├dharmendra.java
│	│	├dharmendra.java.bak
│	│	├ed.java
│	│	├geeksforgeeks.java
│	│	├geeksforgeeks.java.bak
│	│	├geeksforgeeks1.java
│	│	├geeksforgeeks1.java.bak
│	│	├Ghosh.java
│	│	├Ghosh.java.bak
│	│	├Glenn.java
│	│	├Glenn.java.bak
│	│	├hrishikesh-kumar.java
│	│	├hrishikesh-kumar.java.bak
│	│	├Jamal.java
│	│	├Jamal.java.bak
│	│	├JavaHopper.java
│	│	├JavaHopper.java.bak
│	│	├javaRancher2009.java
│	│	├javaRancher2009.java.bak
│	│	├jeantimex.java
│	│	├jeantimex.java.bak
│	│	├jilianggqq.java
│	│	├jilianggqq.java.bak
│	│	├KernelLora.java
│	│	├KernelLora.java.bak
│	│	├klmr3d.java
│	│	├klmr3d.java.bak
│	│	├Krishna.java
│	│	├Krishna.java.bak
│	│	├Manish.java
│	│	├Manish.java.bak
│	│	├McKnight.java
│	│	├McKnight.java.bak
│	│	├mding5692.java
│	│	├mding5692.java.bak
│	│	├moose4204l.java
│	│	├moose4204l.java.bak
│	│	├Obidov.java
│	│	├Obidov.java.bak
│	│	├pbesra.java
│	│	├pbesra.java.bak
│	│	├Sanfoudry.java
│	│	├Sanfoudry.java.bak
│	│	├Sanfoundry Java Program to Describe the Representation of Graph using Adjacency List.docx
│	│	├Sangam.java
│	│	├Sangam.java.bak
│	│	├Sean.java
│	│	├Sean.java.bak
│	│	├Sedgewick.java
│	│	├Snipcademy.java.py
│	│	├Sumitjain.java
│	│	├Sumitjain.java.bak
│	│	├Thain.java
│	│	├Thain.java.bak
│	│	├Udayanga.java
│	│	├Udayanga.java.bak
│	│	├Wagner.java
│	│	├Wagner.java.bak
│	│	├Wagner1.java
│	│	├Wagner1.java.bak
│	│	└WeightedAdjacencyListGraph.java
│	├<matrices>
│	│	├AdjMatrixDiGraph.java
│	│	├AdjMatrixDiGraph.java.bak
│	│	├AdjMatrixGraph.java
│	│	├AdjMatrixGraph.java.bak
│	│	├AlgoList.java
│	│	├AlgoList.java.bak
│	│	├anonym.java
│	│	├anonym.java.bak
│	│	├Arndt.java
│	│	├Arndt.java.bak
│	│	├cpclass.java
│	│	├cpclass.java.bak
│	│	├dharmendra.java
│	│	├dharmendra.java.bak
│	│	├eleal.java
│	│	├eleal.java.bak
│	│	├GraphMatrix.java
│	│	├jinwu.java
│	│	├jinwu.java.bak
│	│	├Josephine.java
│	│	├Josephine.java.bak
│	│	├Manish.java
│	│	├Manish.java.bak
│	│	├MasterOdin.java
│	│	├MasterOdin.java.bak
│	│	├MatrixGraph.java
│	│	├myGraph.java
│	│	├pbesra.java
│	│	├pbesra.java.bak
│	│	├Sedgewick.java
│	│	├Sedgewick.java.bak
│	│	├someone.java
│	│	├someone.java.bak
│	│	└WeightedAdjacencyMatrixGraph.java
│	└<transformation>
│	  	├ed.java
│	  	└ed.java.bak
├<javascript>
│	├nivas8292.js
│	├nivas8292.js.bak
│	├w8r.js
│	└w8r.js.bak
├<lisps>
├<matlab>
│	├wanirepo.m
│	└wanirepo.m.bak
├<perl>
├<python>
│	├<lists>
│	│	├Abiy.py
│	│	├Abiy.py.bak
│	│	├Adjacency_List.py
│	│	├Adjacency_List.py.bak
│	│	├Bradfield.py
│	│	├Bradfield.py.bak
│	│	├ed.py
│	│	├ed.py.bak
│	│	├SQLAlchemy.py
│	│	├SQLAlchemy.py.bak
│	│	├theGreatWhatever.py
│	│	├theGreatWhatever.py.bak
│	│	├vevurka.py
│	│	├vevurka.py.bak
│	│	├yang.py
│	│	└yang.py.bak
│	├<matrices>
│	│	├ajasmar.py
│	│	├ajasmar.py.bak
│	│	├anonym.py
│	│	├anonym.py.bak
│	│	├anuvrat-tiku.py
│	│	├anuvrat-tiku.py.bak
│	│	├Baraa.py
│	│	├Baraa.py.bak
│	│	├Bolboa.py
│	│	├Bolboa.py.bak
│	│	├chabv.py
│	│	├chabv.py.bak
│	│	├exchez.py
│	│	├exchez.py.bak
│	│	├Hagberg.py
│	│	├JohanL.py
│	│	├JohanL.py.bak
│	│	├Manuel.py
│	│	├Manuel.py.bak
│	│	├NetworkX.py
│	│	├NetworkX.py.bak
│	│	├riccamastellone.py
│	│	├riccamastellone.py.bak
│	│	├scipy.txt
│	│	├tmsss.py
│	│	├tmsss.py.bak
│	│	├Toriyama.py
│	│	├Toriyama.py.bak
│	│	├toy.py
│	│	├toy.py.bak
│	│	├wjrl.py
│	│	├wjrl.py.bak
│	│	├<workhorse>
│	│	│	├bOOaa.png
│	│	│	└S9Dcx.png
│	│	└Workhorse.docx
│	└<transformation>
│	  	├Adrian.py
│	  	├Adrian.py.bak
│	  	├anonym.py
│	  	├anonym.py.bak
│	  	├anonym1.py
│	  	├anonym1.py.bak
│	  	├ed.py
│	  	├ed.py.bak
│	  	├Koledoye.py
│	  	├Koledoye.py.bak
│	  	├mpgn.py
│	  	├mpgn.py.bak
│	  	├Nepusz.py
│	  	├Nepusz.py.bak
│	  	├rupalbarman.py
│	  	├rupalbarman.py.bak
│	  	├talesa.py
│	  	└talesa.py.bak
├<ruby>
│	├<rgl-master>
│	│	├.codeclimate.yml
│	│	├.gitignore
│	│	├.travis.yml
│	│	├.yardopts
│	│	├ChangeLog
│	│	├<examples>
│	│	│	├canvas.rb
│	│	│	├examples.rb
│	│	│	├insel_der_tausend_gefahren.rb
│	│	│	├<north>
│	│	│	│	├g.10.0.graphml
│	│	│	│	├g.10.1.graphml
│	│	│	│	├g.10.11.graphml
│	│	│	│	├g.10.12.graphml
│	│	│	│	├g.10.13.graphml
│	│	│	│	├g.10.14.graphml
│	│	│	│	├g.10.15.graphml
│	│	│	│	├g.10.16.graphml
│	│	│	│	├g.10.17.graphml
│	│	│	│	├g.10.19.graphml
│	│	│	│	├g.10.2.graphml
│	│	│	│	├g.10.20.graphml
│	│	│	│	├g.10.22.graphml
│	│	│	│	├g.10.24.graphml
│	│	│	│	├g.10.25.graphml
│	│	│	│	├g.10.27.graphml
│	│	│	│	├g.10.28.graphml
│	│	│	│	├g.10.29.graphml
│	│	│	│	├g.10.3.graphml
│	│	│	│	├g.10.30.graphml
│	│	│	│	├g.10.31.graphml
│	│	│	│	├g.10.34.graphml
│	│	│	│	├g.10.37.graphml
│	│	│	│	├g.10.38.graphml
│	│	│	│	├g.10.39.graphml
│	│	│	│	├g.10.4.graphml
│	│	│	│	├g.10.40.graphml
│	│	│	│	├g.10.41.graphml
│	│	│	│	├g.10.42.graphml
│	│	│	│	├g.10.45.graphml
│	│	│	│	├g.10.46.graphml
│	│	│	│	├g.10.5.graphml
│	│	│	│	├g.10.50.graphml
│	│	│	│	├g.10.56.graphml
│	│	│	│	├g.10.57.graphml
│	│	│	│	├g.10.58.graphml
│	│	│	│	├g.10.6.graphml
│	│	│	│	├g.10.60.graphml
│	│	│	│	├g.10.61.graphml
│	│	│	│	├g.10.62.graphml
│	│	│	│	├g.10.68.graphml
│	│	│	│	├g.10.69.graphml
│	│	│	│	├g.10.7.graphml
│	│	│	│	├g.10.70.graphml
│	│	│	│	├g.10.71.graphml
│	│	│	│	├g.10.72.graphml
│	│	│	│	├g.10.74.graphml
│	│	│	│	├g.10.75.graphml
│	│	│	│	├g.10.78.graphml
│	│	│	│	├g.10.79.graphml
│	│	│	│	├g.10.8.graphml
│	│	│	│	├g.10.80.graphml
│	│	│	│	├g.10.82.graphml
│	│	│	│	├g.10.83.graphml
│	│	│	│	├g.10.85.graphml
│	│	│	│	├g.10.86.graphml
│	│	│	│	├g.10.88.graphml
│	│	│	│	├g.10.89.graphml
│	│	│	│	├g.10.9.graphml
│	│	│	│	├g.10.90.graphml
│	│	│	│	├g.10.91.graphml
│	│	│	│	├g.10.92.graphml
│	│	│	│	├g.10.93.graphml
│	│	│	│	├g.10.94.graphml
│	│	│	│	├g.12.8.graphml
│	│	│	│	├g.14.9.graphml
│	│	│	│	└Graph.log
│	│	│	├north.rb
│	│	│	├north2.rb
│	│	│	└rdep-rgl.rb
│	│	├Gemfile
│	│	├<images>
│	│	│	├example.jpg
│	│	│	├module_graph.jpg
│	│	│	└rgl_modules.png
│	│	├<lib>
│	│	│	└<rgl>
│	│	│	  	├adjacency.rb
│	│	│	  	├base.rb
│	│	│	  	├bellman_ford.rb
│	│	│	  	├bidirectional.rb
│	│	│	  	├bipartite.rb
│	│	│	  	├condensation.rb
│	│	│	  	├connected_components.rb
│	│	│	  	├dijkstra.rb
│	│	│	  	├dijkstra_visitor.rb
│	│	│	  	├dot.rb
│	│	│	  	├edge_properties_map.rb
│	│	│	  	├edmonds_karp.rb
│	│	│	  	├graphxml.rb
│	│	│	  	├graph_iterator.rb
│	│	│	  	├graph_visitor.rb
│	│	│	  	├graph_wrapper.rb
│	│	│	  	├implicit.rb
│	│	│	  	├mutable.rb
│	│	│	  	├path_builder.rb
│	│	│	  	├prim.rb
│	│	│	  	├rdot.rb
│	│	│	  	├topsort.rb
│	│	│	  	├transitivity.rb
│	│	│	  	├transitiv_closure.rb
│	│	│	  	└traversal.rb
│	│	├Rakefile
│	│	├<rakelib>
│	│	│	└dep_graph.rake
│	│	├README.md
│	│	├rgl.gemspec
│	│	├<script>
│	│	│	└test_all
│	│	└<test>
│	│	  	├bellman_ford_test.rb
│	│	  	├bipartite_test.rb
│	│	  	├components_test.rb
│	│	  	├cycles_test.rb
│	│	  	├dijkstra_issue24_test.rb
│	│	  	├dijkstra_test.rb
│	│	  	├directed_graph_test.rb
│	│	  	├dot_test.rb
│	│	  	├edge_properties_map_test.rb
│	│	  	├edge_test.rb
│	│	  	├edmonds_karp_test.rb
│	│	  	├graph_test.rb
│	│	  	├graph_xml_test.rb
│	│	  	├implicit_test.rb
│	│	  	├prim_test.rb
│	│	  	├rdot_test.rb
│	│	  	├test_helper.rb
│	│	  	├transitivity_test.rb
│	│	  	├traversal_test.rb
│	│	  	└undirected_graph_test.rb
│	└rgl-master.zip
├<scilab>
│	├benjaminBoboul.sce
│	└benjaminBoboul.sce.bak
└<swift>
      ├larryfox.swift
      ├larryfox.swift.bak
      ├raywenderlich.swift
      └raywenderlich.swift.bak


This file was created on December 01, 2017, 09:25

000graph_datastructures_representation
├<graph_datastructures_details>
│	├000graph_datastructures_detailsIntro.htm
│	├<algorithms>
│	├<arrays>
│	├<domains>
│	├graph_datastructures_details - 副本.htm
│	├graph_datastructures_details.htm
│	├graph_datastructures_detailsAlgorithms.htm
│	├graph_datastructures_detailsArrays.htm
│	├graph_datastructures_detailsDictionary.htm
│	├graph_datastructures_detailsDomains.htm
│	├graph_datastructures_detailsHybrid.htm
│	├graph_datastructures_detailsImplicit.htm
│	├graph_datastructures_detailsIndices.htm
│	├graph_datastructures_detailsLists.htm
│	├graph_datastructures_detailsMaps.htm
│	├graph_datastructures_detailsMatrices.htm
│	├graph_datastructures_detailsObjects.htm
│	├graph_datastructures_detailsPolynomials.htm
│	├graph_datastructures_detailsPrintable.htm
│	├graph_datastructures_detailsRows.htm
│	├graph_datastructures_detailsRules.htm
│	├graph_datastructures_detailsSequence.htm
│	├graph_datastructures_detailsSets.htm
│	├graph_datastructures_detailsStar.htm
│	├graph_datastructures_detailsTables.htm
│	├graph_datastructures_detailsVectors.htm
│	├<hybrid>
│	├<implicit>
│	│	└Sampath Kannan Implicat Representation of Graphs.docx
│	├<indices>
│	├<lists>
│	├<maps>
│	│	├Amit Patel Map representations.docx
│	│	└Ethan Using a Map for a Graph.docx
│	├<matrices>
│	├<objects>
│	│	└Kat Object and Pointer Graph representations.docx
│	├<polynomials>
│	├<printables>
│	├<rows>
│	│	├burkardt  Compressed Row (CR) Sparse Matrix File Format.docx
│	│	├Cheuk Compressed Row Storage.docx
│	│	├GNU Scientific Library – Reference Manual  Sparse Matrices Compressed Format.htm
│	│	├Jack Dongarra Compressed Row Storage.docx
│	│	├Scipy lecture Compressed Sparse Row Format (CSR).docx
│	│	├Sparse Matrix Compression Formats.htm
│	│	└SumNeuron Matrix Compression.docx
│	├<rules>
│	├<sequences>
│	├<sets>
│	├<stars>
│	├<tables>
│	└<vectors>
│	  	├Annamalai Representing graph as a vector.docx
│	  	├aroup Adjacency list Graph representation using vector and pair.docx
│	  	├David Corneliusen How can I create an adjacency matrix using vectors in a templated graph class in c.docx
│	  	├hubbu Making Adjacency List with Vectors.docx
│	  	└Parsons Vector representations of graphs.docx
├<graph_datastructures_literature>
│	├graph_datastructures_literature - 副本 (3).htm
│	├graph_datastructures_literature0.htm
│	├graph_datastructures_literatureA.htm
│	├graph_datastructures_literatureB.htm
│	├graph_datastructures_literatureC.htm
│	├graph_datastructures_literatureD.htm
│	├graph_datastructures_literatureE.htm
│	├graph_datastructures_literatureF.htm
│	├graph_datastructures_literatureG.htm
│	├graph_datastructures_literatureH.htm
│	├graph_datastructures_literatureI.htm
│	├graph_datastructures_literatureJ.htm
│	├graph_datastructures_literatureK.htm
│	├graph_datastructures_literatureL.htm
│	├graph_datastructures_literatureM.htm
│	├graph_datastructures_literatureN.htm
│	├graph_datastructures_literatureO.htm
│	├graph_datastructures_literatureP.htm
│	├graph_datastructures_literatureQ.htm
│	├graph_datastructures_literatureR.htm
│	├graph_datastructures_literatureS.htm
│	├graph_datastructures_literatureT.htm
│	├graph_datastructures_literatureU.htm
│	├graph_datastructures_literatureV.htm
│	├<graph_datastructures_literatureW>
│	│	└<Wagner2012>
│	│	  	├adjlist5.png
│	│	  	├capitals_smaller.gif
│	│	  	└capsnum.gif
│	├graph_datastructures_literatureW.htm
│	├graph_datastructures_literatureX.htm
│	├graph_datastructures_literatureY.htm
│	└graph_datastructures_literatureZ.htm
└<graph_datastructures_pdfpptdocx>
      ├Abiy Graph implementation and representation.docx
      ├Abu-Khzam A Hybrid Graph Representation for Exact Graph Algorithms p15.pdf
      ├Abu-Khzam A Hybrid Graph Representation for Recursive Backtracking Algorithms p12.pdf
      ├AHUJA Network Flows Theory, Algorithms, and Applications Ch1_3 p103.pdf
      ├AlgoList Undirected graphs representation.docx
      ├Amar Majority-Inverter Graph A Novel Data-Structure and Algorithms for Efficient Logic Optimization p6.pdf
      ├Appel An Alternate Graph Representation for the Tiger Compiler.docx
      ├Arikati Efficient computation of implicit representations of sparse graphs p16.pdf
      ├Atminas Implicit Representations and Factorial Properties of Graphs p28.pdf
      ├Barnes Graphs.pdf
      ├Barnwal Graph and its representations.docx
      ├Barták Graphs in Prolog.docx
      ├Basel Elementary Graph Algorithms PART-1 p34.pdf
      ├Beard Comparing object graph representation to adjacency list and matrix representations.docx
      ├Benoit Representing trees of higher degree p12.pdf
      ├Berkeley — Graph representations.docx
      ├Blelloch Lecture 13 — Shortest Weighted Paths p8.pdf
      ├Blelloch Lecture 7 Graph Representations Sets and Tables p11.pdf
      ├Bogner Feynman graph polynomials p35.pdf
      ├Boost Graph Library  Adjacency List - develop.docx
      ├Boost Graph Library  Adjacency Matrix - 1.51.0.docx
      ├Brabec Procedural Code Representation in a Flow Graph p12.pdf
      ├Braun FIRM A Graph-Based Intermediate Representation p8.pdf
      ├Brisaboa Compact Representation of Web Graphs with Extended Functionality p33.pdf
      ├Brisaboa K2trees for Compact Web Graph Representation p10.pdf
      ├Btechsmartclass Graph Representations.docx
      ├Buesser New Adjacency List and Multiplicity.pptx
      ├Buriol Web Graph representation and compression.ppt
      ├Burkardt GRAPH_REPRESENTATION.docx
      ├Cao Deep Neural Networks for Learning Graph Representations p8.pdf
      ├Catherine Clustering the Graph Representation of Data p26.pdf
      ├Chen Analysis of Algorithms I Graph Representation and BFS p41.pdf
      ├Chen EAGER Define and Construct an Enhanced Graph Representation for Multiscale Vector Field Data Summarization.docx
      ├Claude A Fast and CompactWeb Graph Representation p12.pdf
      ├CLAUDE Fast and Compact Web Graph Representations p30.pdf
      ├Codish Breaking Symmetries in Graph Representation p7.pdf
      ├COMPSCI Part 1 Graphs and Adjacency Matrices.pdf
      ├Cormen Representing graphs.docx
      ├Corn Adjacency Matrix.docx
      ├Cornell Lecture 21 Graph Representations and Traversals.docx
      ├Costantini Comparing different graph representations of logic programs under the Answer Set semantics p6.pdf
      ├CPLEX LP format.pdf
      ├Curtis An Implicit Representation of Chordal Comparabilty Graphs in Linear-time p14.pdf
      ├D'Autilia Shaping ideal cities the graph representation of the urban utopia p17.pdf
      ├de Greef Lecture 15 - Graph Data Structures and Traversals p37.pdf
      ├Deepa Data Structure for Graphs p4.pdf
      ├Depree Graph Operations And Representation p34 (2).pdf
      ├Depree Graph Operations And Representation p34.pdf
      ├Dezso LEMON – an Open Source C++ Graph Template Library1.pdf
      ├Dong Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance p67.pdf
      ├Du Lecture 3 Graph Representation for Regular Expressions p26.ppt
      ├Dvorak A dynamic data structure for counting subgraphs in sparse graphs p27.pdf
      ├Ediger STINGER High Performance Data Structure for Streaming Graphs p5.pdf
      ├Egyhazy On implementing graph representation p23.pdf
      ├Elite Graph Representation p27.pdf
      ├Ellis-Monaghan Graph Polynomials and Their Applications I The Tutte Polynomial p42.pdf
      ├Emms A matrix representation of graphs and its spectrum as a graph invariant p14.pdf
      ├ERDOS THE REPRESENTATION OF A GRAPH BY SET INTERSECTIONS p7.pdf
      ├Figueroa Tracking soccer players using the graph representation p4.pdf
      ├Gaillarda Graph representation of synonymy and translation resources for cross-linguistic modelisation of meaning p12.pdf
      ├Gansner GMap Visualizing Graphs and Clusters as Maps p8.pdf
      ├García Compact and Efficient Representations of Graphs p301.pdf
      ├Gavoille Shorter Implicit Representation for Planar Graphs and Bounded Treewidth Graphs p12.pdf
      ├Gkirtzou The Pyramid Quantized Weisfeiler-Lehman Graph Representation p17.pdf
      ├Goodrich Data Structures and Algorithms Introducing Graphs p9.pdf
      ├Gotshalks Graph Representation p12.pdf
      ├Grama Graph Algorithms p65.pdf
      ├GRAPH FILE FORMATS.pdf
      ├Graph Representation (2).pdf
      ├Graph Representation.pdf
      ├Graph Representation1.pdf
      ├graph_representation.pdf
      ├Gross Section 8.3 Graph Representations and Graph Isomorphism p11.pdf
      ├Hackerearth Graph Representation.docx
      ├Heap  Graph representation .docx
      ├Hedstrom Graph representation.docx
      ├Heissan Some Results on Graph Representations and Graph Colorings p60.pdf
      ├Hernandez Compressed Representation of Web and Social Networks via Dense Subgraphs p12.pdf
      ├Huan Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based acking Motifs p12.pdf
      ├HUAN Comparing Graph Representations of Protein Structure for Mining Family-Specific Residue-Based Packing Motifs p15.pdf
      ├Hugue Lecture 22 Graphs Representations and BFS.pdf
      ├Iglesias Graph representation of documents content and its suitability for text mining tasks p72.pdf
      ├Incidence tables of graphs.pdf
      ├Jampani Simultaneous Graph Representation Problems p94.pdf
      ├Joy A Standard for a Graph Representation for Functional Programs p8.pdf
      ├Kannan Implicit Representation of Graphs p11.pdf
      ├Kapanowski Weighted Graph Algorithms with Python p13.pdf
      ├Kapanowski Weighted graph algorithms with Python p26.pdf
      ├Kehr Genome alignment with graph data structures a comparison.docx
      ├Kenrick Implementing a Graph p29.pdf
      ├Kirsh An Implementation and Analysis of the Skip Graph Data Structure p12.pdf
      ├Kobler Interval graph representation with given interval and intersection lengths p10.pdf
      ├Kolter Graphs and Networks.pdf
      ├KOZA COMPRESSED MULTI-ROW STORAGE FORMAT FOR SPARSE MATRICES ON GRAPHICS PROCESSING UNITS p26.pdf
      ├Kudase A Brief Study of Graph Data Structure p5.pdf
      ├Kuhnert Space Efficient Algorithms for Graph Isomorphism and Representation p117.pdf
      ├Kumar Improved Algorithms and Data Structures for Solving Graph Problems in External Memories p34.pdf
      ├K?bler Interval graph representation with given interval and intersection lengths p11.pdf
      ├K?bler Interval Graph Representation with Given Interval and Intersection Lengths p13.pdf
      ├L18Graphs.pdf
      ├Lawlor Introduction to Graph Algorithms p8.pdf
      ├Lehmann Implementing Graph Query Languages over Compressed Data Structures A Progress Report p5.pdf
      ├Lei?a A Graph-Based Higher-Order Intermediate Representation p11.pdf
      ├Lenharth Graph Representations p5.pdf
      ├Loerch An Introduction to Graph Algorithms p46.pdf
      ├Lovasz Geometric Representations of Graphs p213.pdf
      ├Madduri Compact Graph Representations and Parallel Connectivity Algorithms for Massive Dynamic Network Analysis p11.pdf
      ├Madduri Scaling up graph algorithms on emerging multicore systems p22.pdf
      ├Maiya Visually Pleasing Graph Representation Using GraphDraw.docx
      ├Manchester Graph Representation and Traversal.docx
      ├Manevich Synthesizing Concurrent Graph Data Structures A Case Study p14.pdf
      ├Martin Graph Theory and Social Networks p148.pdf
      ├Matas The color adjacency graph of multi-coloured objects p18.pdf
      ├Mehlhorn Data Structures and Algorithms The Basic Toolbox - 8 Graph Representations p8.pdf.pdf
      ├Montes Graph Representation for Program Evolution an Overview p32.pdf
      ├Moore Introduction to Graphs p9.pdf
      ├Morris Graph Representations.docx
      ├Munro Dynamic Data Structures for Document Collections and Graphs p13.pdf
      ├Nanda Lecture 11 Graphs and their Adjacency Matrices p6.pdf
      ├NetworkGraph Theory Graph-based representations p13.pdf
      ├networkx_reference.pdf
      ├OJJ GRAPH REPRESENTATION.docx
      ├Okie Graphs - Terminology and Representation.docx
      ├Opendatastructures 12.2 AdjacencyLists A Graph as a Collection of Lists.docx
      ├opendatastructures.org.docx
      ├ORLIN DYNAMIC NETWORK FLOWS p115.pdf
      ├PageRank-Project.pdf
      ├Pahikkala Graph Kernels versus Graph Representations a Case Study in Parse Ranking p8.pdf
      ├Papadimitriou Combinatorial Algorithms & Data Structures Spring 2003 p9.pdf
      ├Park Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation p4.pdf
      ├Park Basic Graph Algorithms p38.pdf
      ├Patty Math 639, Compressed Row Storage (CRS) Format for Sparse Matrices p24.pdf
      ├Pfenning Lecture 23 Notes Representing Graphs.pdf
      ├Phukon The Composite Graph Model for Web Document and its Impacts on Graph Distance Measurement p8.pdf
      ├Piana A graph representation of basic macroeconomic scheme p27.pdf
      ├Picard Coinductive Graph Representation p64.pdf
      ├Picard Permutations in Coinductive Graph Representation p20.pdf
      ├Pisanski Graph representation.ppt
      ├Popov Algorithm of the Week Graphs and Their Representation.docx
      ├Popov Computer Algorithms Graphs and their Representation.docx
      ├PSF Python Patterns - Implementing Graphs.docx
      ├Rahman Implicit Representation of Graphs p42.pdf
      ├Rao Graph p19.pdf
      ├Reid-Miller Lecture 10 — Shortest Weighted Paths I p6.pdf
      ├Review on Graphs.pdf
      ├Rocca The giRaph package for graph representation in R p1.pdf
      ├Rotta Graph Representation.docx
      ├Rougier Implicit and Explicit Representations p17.pdf
      ├Rudich Implicit Representation of Graphs p12.pdf
      ├Sangam.docx
      ├Sb?rlea DFGR an Intermediate Graph Representation for Macro-Dataflow Programs p8.pdf
      ├Schwarz Graph Representations and Algorithms p164 (2).pdf
      ├Schwarz Graph Representations and Algorithms p164.pdf
      ├Sedziwy Effective graph representation p13.pdf
      ├Seibert Learning Aspect Graph Representations from View Sequences p8.pdf
      ├Shaffer graph.java.pdf
      ├Shai Transforming Engineering Problems through Graph Representations p28.pdf
      ├Shaia Graph theory representations of engineering systems and their embedded knowledge p13.pdf
      ├Shkotin Graph representation of context-free grammars p4.pdf
      ├Sidere Vector Representation of Graphs Application to the Classification of Symbols and Letters p6.pdf
      ├Siek Review of Elementary Graph Theory.docx
      ├Singh Role of Adjacency Matrix & Adjacency List in Graph Theory p5.pdf
      ├Situngkir Small World Network of Athletes Graph Representation of the World Professional Tennis Player p13.pdf
      ├Slesarenko How to select the best graph representation for a given task p18.pdf
      ├Sommer 8.1 Graph Representation in Memory p14.pdf
      ├Sowa Conceptual Graphs p26.pdf
      ├Stratis Graph Representation of Concurrent Programs in C++ p50.pdf
      ├Suanfazu Comparing object graph representation to adjacency list and matrix representations.docx
      ├Suanfazu Comparing object graph representation to adjacency list and matrix representations1.docx
      ├Sumitjain Graph Representation — Adjacency Matrix and Adjacency List.docx
      ├Tangwongsan Lecture 7 — Graph Representations, Sets, and Tables p11.pdf
      ├Thomas Pathfinding.pdf
      ├Thomsen Adjacency matrix code visualizer.docx
      ├Tilstra COMPARING MATRIX-BASED AND GRAPH-BASED REPRESENTATIONS FOR PRODUCT DESIGN p6.pdf
      ├Trinks Graph Polynomials and Their Representations p122.pdf
      ├Ullman Foundations of Computer Science CHAPTER 9 The Graph Data Model p78.pdf
      ├Wagner Graph Representation.docx
      ├Wang Handwritten Word Spotting Based on Graph Representation p13.pdf
      ├Wang Large-Scale Graph Processing Algorithms on the GPU p16.pdf
      ├Wang Text-Enhanced Representation Learning for Knowledge Graph p7.pdf
      ├Wolfram Graph Construction & Representation.docx
      ├Wu Structural Opinion Mining for Graph-based Sentiment Representation p10.pdf
      ├Xirouhakis an efficient graph representation p6.pdf
      ├Yin W-graph representations for Coxeter groups and Hecke algebras p101.pdf
      ├Zanibbi Graph Representations p2.pdf
      ├Zeps How to draw combinatorial map From graphs and edges to corner rotations and permutations p20.pdf
      ├Zewi VECTOR REPRESENTATION OF GRAPH DOMINATION p21.pdf
      ├Zewi Vector Representation of Graph Domination p66.pdf
      ├Zhao Semantic Single Video Segmentation with Robust Graph Representation p7.pdf
      └ZZZtest.txt